1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/etherdevice.h>
5 #include <linux/iopoll.h>
6 #include <net/rtnetlink.h>
7 #include "hclgevf_cmd.h"
8 #include "hclgevf_main.h"
11 #include "hclgevf_devlink.h"
13 #define HCLGEVF_NAME "hclgevf"
15 #define HCLGEVF_RESET_MAX_FAIL_CNT 5
17 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
18 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
21 static struct hnae3_ae_algo ae_algovf;
23 static struct workqueue_struct *hclgevf_wq;
25 static const struct pci_device_id ae_algovf_pci_tbl[] = {
26 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
27 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
28 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
29 /* required last entry */
33 static const u8 hclgevf_hash_key[] = {
34 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
35 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
36 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
37 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
38 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA
41 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
43 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_NIC_CSQ_BASEADDR_L_REG,
44 HCLGEVF_NIC_CSQ_BASEADDR_H_REG,
45 HCLGEVF_NIC_CSQ_DEPTH_REG,
46 HCLGEVF_NIC_CSQ_TAIL_REG,
47 HCLGEVF_NIC_CSQ_HEAD_REG,
48 HCLGEVF_NIC_CRQ_BASEADDR_L_REG,
49 HCLGEVF_NIC_CRQ_BASEADDR_H_REG,
50 HCLGEVF_NIC_CRQ_DEPTH_REG,
51 HCLGEVF_NIC_CRQ_TAIL_REG,
52 HCLGEVF_NIC_CRQ_HEAD_REG,
53 HCLGEVF_VECTOR0_CMDQ_SRC_REG,
54 HCLGEVF_VECTOR0_CMDQ_STATE_REG,
55 HCLGEVF_CMDQ_INTR_EN_REG,
56 HCLGEVF_CMDQ_INTR_GEN_REG};
58 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
62 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
63 HCLGEVF_RING_RX_ADDR_H_REG,
64 HCLGEVF_RING_RX_BD_NUM_REG,
65 HCLGEVF_RING_RX_BD_LENGTH_REG,
66 HCLGEVF_RING_RX_MERGE_EN_REG,
67 HCLGEVF_RING_RX_TAIL_REG,
68 HCLGEVF_RING_RX_HEAD_REG,
69 HCLGEVF_RING_RX_FBD_NUM_REG,
70 HCLGEVF_RING_RX_OFFSET_REG,
71 HCLGEVF_RING_RX_FBD_OFFSET_REG,
72 HCLGEVF_RING_RX_STASH_REG,
73 HCLGEVF_RING_RX_BD_ERR_REG,
74 HCLGEVF_RING_TX_ADDR_L_REG,
75 HCLGEVF_RING_TX_ADDR_H_REG,
76 HCLGEVF_RING_TX_BD_NUM_REG,
77 HCLGEVF_RING_TX_PRIORITY_REG,
78 HCLGEVF_RING_TX_TC_REG,
79 HCLGEVF_RING_TX_MERGE_EN_REG,
80 HCLGEVF_RING_TX_TAIL_REG,
81 HCLGEVF_RING_TX_HEAD_REG,
82 HCLGEVF_RING_TX_FBD_NUM_REG,
83 HCLGEVF_RING_TX_OFFSET_REG,
84 HCLGEVF_RING_TX_EBD_NUM_REG,
85 HCLGEVF_RING_TX_EBD_OFFSET_REG,
86 HCLGEVF_RING_TX_BD_ERR_REG,
89 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
90 HCLGEVF_TQP_INTR_GL0_REG,
91 HCLGEVF_TQP_INTR_GL1_REG,
92 HCLGEVF_TQP_INTR_GL2_REG,
93 HCLGEVF_TQP_INTR_RL_REG};
95 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
98 return container_of(handle, struct hclgevf_dev, nic);
99 else if (handle->client->type == HNAE3_CLIENT_ROCE)
100 return container_of(handle, struct hclgevf_dev, roce);
102 return container_of(handle, struct hclgevf_dev, nic);
105 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
107 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
108 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
109 struct hclgevf_desc desc;
110 struct hclgevf_tqp *tqp;
114 for (i = 0; i < kinfo->num_tqps; i++) {
115 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
116 hclgevf_cmd_setup_basic_desc(&desc,
117 HCLGEVF_OPC_QUERY_RX_STATUS,
120 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
121 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
123 dev_err(&hdev->pdev->dev,
124 "Query tqp stat fail, status = %d,queue = %d\n",
128 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
129 le32_to_cpu(desc.data[1]);
131 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
134 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
135 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
137 dev_err(&hdev->pdev->dev,
138 "Query tqp stat fail, status = %d,queue = %d\n",
142 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
143 le32_to_cpu(desc.data[1]);
149 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
151 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
152 struct hclgevf_tqp *tqp;
156 for (i = 0; i < kinfo->num_tqps; i++) {
157 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
158 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
160 for (i = 0; i < kinfo->num_tqps; i++) {
161 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
162 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
168 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
170 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
172 return kinfo->num_tqps * 2;
175 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
177 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
181 for (i = 0; i < kinfo->num_tqps; i++) {
182 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
183 struct hclgevf_tqp, q);
184 snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd",
186 buff += ETH_GSTRING_LEN;
189 for (i = 0; i < kinfo->num_tqps; i++) {
190 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
191 struct hclgevf_tqp, q);
192 snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd",
194 buff += ETH_GSTRING_LEN;
200 static void hclgevf_update_stats(struct hnae3_handle *handle,
201 struct net_device_stats *net_stats)
203 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
206 status = hclgevf_tqps_update_stats(handle);
208 dev_err(&hdev->pdev->dev,
209 "VF update of TQPS stats fail, status = %d.\n",
213 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
215 if (strset == ETH_SS_TEST)
217 else if (strset == ETH_SS_STATS)
218 return hclgevf_tqps_get_sset_count(handle, strset);
223 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
226 u8 *p = (char *)data;
228 if (strset == ETH_SS_STATS)
229 p = hclgevf_tqps_get_strings(handle, p);
232 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
234 hclgevf_tqps_get_stats(handle, data);
237 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,
241 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));
243 msg->subcode = subcode;
247 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev)
249 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
250 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE];
251 struct hclge_basic_info *basic_info;
252 struct hclge_vf_to_pf_msg send_msg;
256 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0);
257 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
260 dev_err(&hdev->pdev->dev,
261 "failed to get basic info from pf, ret = %d", status);
265 basic_info = (struct hclge_basic_info *)resp_msg;
267 hdev->hw_tc_map = basic_info->hw_tc_map;
268 hdev->mbx_api_version = basic_info->mbx_api_version;
269 caps = basic_info->pf_caps;
270 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps))
271 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
276 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
278 struct hnae3_handle *nic = &hdev->nic;
279 struct hclge_vf_to_pf_msg send_msg;
283 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
284 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);
285 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
288 dev_err(&hdev->pdev->dev,
289 "VF request to get port based vlan state failed %d",
294 nic->port_base_vlan_state = resp_msg;
299 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
301 #define HCLGEVF_TQPS_RSS_INFO_LEN 6
302 #define HCLGEVF_TQPS_ALLOC_OFFSET 0
303 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2
304 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4
306 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
307 struct hclge_vf_to_pf_msg send_msg;
310 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);
311 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
312 HCLGEVF_TQPS_RSS_INFO_LEN);
314 dev_err(&hdev->pdev->dev,
315 "VF request to get tqp info from PF failed %d",
320 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET],
322 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET],
324 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET],
330 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
332 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4
333 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0
334 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2
336 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
337 struct hclge_vf_to_pf_msg send_msg;
340 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);
341 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
342 HCLGEVF_TQPS_DEPTH_INFO_LEN);
344 dev_err(&hdev->pdev->dev,
345 "VF request to get tqp depth info from PF failed %d",
350 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET],
352 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET],
358 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
360 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
361 struct hclge_vf_to_pf_msg send_msg;
366 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);
367 memcpy(send_msg.data, &queue_id, sizeof(queue_id));
368 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,
371 qid_in_pf = *(u16 *)resp_data;
376 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
378 struct hclge_vf_to_pf_msg send_msg;
382 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);
383 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
386 dev_err(&hdev->pdev->dev,
387 "VF request to get the pf port media type failed %d",
392 hdev->hw.mac.media_type = resp_msg[0];
393 hdev->hw.mac.module_type = resp_msg[1];
398 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
400 struct hclgevf_tqp *tqp;
403 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
404 sizeof(struct hclgevf_tqp), GFP_KERNEL);
410 for (i = 0; i < hdev->num_tqps; i++) {
411 tqp->dev = &hdev->pdev->dev;
414 tqp->q.ae_algo = &ae_algovf;
415 tqp->q.buf_size = hdev->rx_buf_len;
416 tqp->q.tx_desc_num = hdev->num_tx_desc;
417 tqp->q.rx_desc_num = hdev->num_rx_desc;
419 /* need an extended offset to configure queues >=
420 * HCLGEVF_TQP_MAX_SIZE_DEV_V2.
422 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2)
423 tqp->q.io_base = hdev->hw.io_base +
424 HCLGEVF_TQP_REG_OFFSET +
425 i * HCLGEVF_TQP_REG_SIZE;
427 tqp->q.io_base = hdev->hw.io_base +
428 HCLGEVF_TQP_REG_OFFSET +
429 HCLGEVF_TQP_EXT_REG_OFFSET +
430 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) *
431 HCLGEVF_TQP_REG_SIZE;
439 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
441 struct hnae3_handle *nic = &hdev->nic;
442 struct hnae3_knic_private_info *kinfo;
443 u16 new_tqps = hdev->num_tqps;
448 kinfo->num_tx_desc = hdev->num_tx_desc;
449 kinfo->num_rx_desc = hdev->num_rx_desc;
450 kinfo->rx_buf_len = hdev->rx_buf_len;
451 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
452 if (hdev->hw_tc_map & BIT(i))
455 num_tc = num_tc ? num_tc : 1;
456 kinfo->tc_info.num_tc = num_tc;
457 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc);
458 new_tqps = kinfo->rss_size * num_tc;
459 kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
461 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
462 sizeof(struct hnae3_queue *), GFP_KERNEL);
466 for (i = 0; i < kinfo->num_tqps; i++) {
467 hdev->htqp[i].q.handle = &hdev->nic;
468 hdev->htqp[i].q.tqp_index = i;
469 kinfo->tqp[i] = &hdev->htqp[i].q;
472 /* after init the max rss_size and tqps, adjust the default tqp numbers
473 * and rss size with the actual vector numbers
475 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
476 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc,
482 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
484 struct hclge_vf_to_pf_msg send_msg;
487 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);
488 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
490 dev_err(&hdev->pdev->dev,
491 "VF failed to fetch link status(%d) from PF", status);
494 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
496 struct hnae3_handle *rhandle = &hdev->roce;
497 struct hnae3_handle *handle = &hdev->nic;
498 struct hnae3_client *rclient;
499 struct hnae3_client *client;
501 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))
504 client = handle->client;
505 rclient = hdev->roce_client;
508 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
509 if (link_state != hdev->hw.mac.link) {
510 hdev->hw.mac.link = link_state;
511 client->ops->link_status_change(handle, !!link_state);
512 if (rclient && rclient->ops->link_status_change)
513 rclient->ops->link_status_change(rhandle, !!link_state);
516 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);
519 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
521 #define HCLGEVF_ADVERTISING 0
522 #define HCLGEVF_SUPPORTED 1
524 struct hclge_vf_to_pf_msg send_msg;
526 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);
527 send_msg.data[0] = HCLGEVF_ADVERTISING;
528 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
529 send_msg.data[0] = HCLGEVF_SUPPORTED;
530 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
533 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
535 struct hnae3_handle *nic = &hdev->nic;
538 nic->ae_algo = &ae_algovf;
539 nic->pdev = hdev->pdev;
540 nic->numa_node_mask = hdev->numa_node_mask;
541 nic->flags |= HNAE3_SUPPORT_VF;
542 nic->kinfo.io_base = hdev->hw.io_base;
544 ret = hclgevf_knic_setup(hdev);
546 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
551 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
553 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
554 dev_warn(&hdev->pdev->dev,
555 "vector(vector_id %d) has been freed.\n", vector_id);
559 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
560 hdev->num_msi_left += 1;
561 hdev->num_msi_used -= 1;
564 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
565 struct hnae3_vector_info *vector_info)
567 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
568 struct hnae3_vector_info *vector = vector_info;
572 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
573 vector_num = min(hdev->num_msi_left, vector_num);
575 for (j = 0; j < vector_num; j++) {
576 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
577 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
578 vector->vector = pci_irq_vector(hdev->pdev, i);
579 vector->io_addr = hdev->hw.io_base +
580 HCLGEVF_VECTOR_REG_BASE +
581 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
582 hdev->vector_status[i] = 0;
583 hdev->vector_irq[i] = vector->vector;
592 hdev->num_msi_left -= alloc;
593 hdev->num_msi_used += alloc;
598 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
602 for (i = 0; i < hdev->num_msi; i++)
603 if (vector == hdev->vector_irq[i])
609 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
610 const u8 hfunc, const u8 *key)
612 struct hclgevf_rss_config_cmd *req;
613 unsigned int key_offset = 0;
614 struct hclgevf_desc desc;
619 key_counts = HCLGEVF_RSS_KEY_SIZE;
620 req = (struct hclgevf_rss_config_cmd *)desc.data;
623 hclgevf_cmd_setup_basic_desc(&desc,
624 HCLGEVF_OPC_RSS_GENERIC_CONFIG,
627 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
629 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
631 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts);
632 memcpy(req->hash_key,
633 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
635 key_counts -= key_size;
637 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
639 dev_err(&hdev->pdev->dev,
640 "Configure RSS config fail, status = %d\n",
649 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
651 return HCLGEVF_RSS_KEY_SIZE;
654 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
656 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
657 struct hclgevf_rss_indirection_table_cmd *req;
658 struct hclgevf_desc desc;
663 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
664 rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size /
665 HCLGEVF_RSS_CFG_TBL_SIZE;
667 for (i = 0; i < rss_cfg_tbl_num; i++) {
668 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
670 req->start_table_index =
671 cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE);
672 req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK);
673 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
675 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
677 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
679 dev_err(&hdev->pdev->dev,
680 "VF failed(=%d) to set RSS indirection table\n",
689 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size)
691 struct hclgevf_rss_tc_mode_cmd *req;
692 u16 tc_offset[HCLGEVF_MAX_TC_NUM];
693 u16 tc_valid[HCLGEVF_MAX_TC_NUM];
694 u16 tc_size[HCLGEVF_MAX_TC_NUM];
695 struct hclgevf_desc desc;
700 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
702 roundup_size = roundup_pow_of_two(rss_size);
703 roundup_size = ilog2(roundup_size);
705 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
706 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
707 tc_size[i] = roundup_size;
708 tc_offset[i] = rss_size * i;
711 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
712 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
715 hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B,
716 (tc_valid[i] & 0x1));
717 hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M,
718 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
719 hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B,
720 tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET &
722 hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M,
723 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
725 req->rss_tc_mode[i] = cpu_to_le16(mode);
727 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
729 dev_err(&hdev->pdev->dev,
730 "VF failed(=%d) to set rss tc mode\n", status);
735 /* for revision 0x20, vf shared the same rss config with pf */
736 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
738 #define HCLGEVF_RSS_MBX_RESP_LEN 8
739 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
740 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
741 struct hclge_vf_to_pf_msg send_msg;
742 u16 msg_num, hash_key_index;
746 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);
747 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
748 HCLGEVF_RSS_MBX_RESP_LEN;
749 for (index = 0; index < msg_num; index++) {
750 send_msg.data[0] = index;
751 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
752 HCLGEVF_RSS_MBX_RESP_LEN);
754 dev_err(&hdev->pdev->dev,
755 "VF get rss hash key from PF failed, ret=%d",
760 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
761 if (index == msg_num - 1)
762 memcpy(&rss_cfg->rss_hash_key[hash_key_index],
764 HCLGEVF_RSS_KEY_SIZE - hash_key_index);
766 memcpy(&rss_cfg->rss_hash_key[hash_key_index],
767 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
773 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
776 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
777 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
780 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
781 /* Get hash algorithm */
783 switch (rss_cfg->hash_algo) {
784 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
785 *hfunc = ETH_RSS_HASH_TOP;
787 case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
788 *hfunc = ETH_RSS_HASH_XOR;
791 *hfunc = ETH_RSS_HASH_UNKNOWN;
796 /* Get the RSS Key required by the user */
798 memcpy(key, rss_cfg->rss_hash_key,
799 HCLGEVF_RSS_KEY_SIZE);
802 *hfunc = ETH_RSS_HASH_TOP;
804 ret = hclgevf_get_rss_hash_key(hdev);
807 memcpy(key, rss_cfg->rss_hash_key,
808 HCLGEVF_RSS_KEY_SIZE);
813 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
814 indir[i] = rss_cfg->rss_indirection_tbl[i];
819 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
820 const u8 *key, const u8 hfunc)
822 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
823 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
826 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
827 /* Set the RSS Hash Key if specififed by the user */
830 case ETH_RSS_HASH_TOP:
832 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
834 case ETH_RSS_HASH_XOR:
836 HCLGEVF_RSS_HASH_ALGO_SIMPLE;
838 case ETH_RSS_HASH_NO_CHANGE:
844 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
849 /* Update the shadow RSS key with user specified qids */
850 memcpy(rss_cfg->rss_hash_key, key,
851 HCLGEVF_RSS_KEY_SIZE);
855 /* update the shadow RSS table with user specified qids */
856 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
857 rss_cfg->rss_indirection_tbl[i] = indir[i];
859 /* update the hardware */
860 return hclgevf_set_rss_indir_table(hdev);
863 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
865 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
867 if (nfc->data & RXH_L4_B_2_3)
868 hash_sets |= HCLGEVF_D_PORT_BIT;
870 hash_sets &= ~HCLGEVF_D_PORT_BIT;
872 if (nfc->data & RXH_IP_SRC)
873 hash_sets |= HCLGEVF_S_IP_BIT;
875 hash_sets &= ~HCLGEVF_S_IP_BIT;
877 if (nfc->data & RXH_IP_DST)
878 hash_sets |= HCLGEVF_D_IP_BIT;
880 hash_sets &= ~HCLGEVF_D_IP_BIT;
882 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
883 hash_sets |= HCLGEVF_V_TAG_BIT;
888 static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle,
889 struct ethtool_rxnfc *nfc,
890 struct hclgevf_rss_input_tuple_cmd *req)
892 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
893 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
896 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
897 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
898 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
899 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
900 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
901 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
902 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
903 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
905 tuple_sets = hclgevf_get_rss_hash_bits(nfc);
906 switch (nfc->flow_type) {
908 req->ipv4_tcp_en = tuple_sets;
911 req->ipv6_tcp_en = tuple_sets;
914 req->ipv4_udp_en = tuple_sets;
917 req->ipv6_udp_en = tuple_sets;
920 req->ipv4_sctp_en = tuple_sets;
923 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
924 (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)))
927 req->ipv6_sctp_en = tuple_sets;
930 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
933 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
942 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
943 struct ethtool_rxnfc *nfc)
945 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
946 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
947 struct hclgevf_rss_input_tuple_cmd *req;
948 struct hclgevf_desc desc;
951 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
955 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
958 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
959 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
961 ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req);
963 dev_err(&hdev->pdev->dev,
964 "failed to init rss tuple cmd, ret = %d\n", ret);
968 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
970 dev_err(&hdev->pdev->dev,
971 "Set rss tuple fail, status = %d\n", ret);
975 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
976 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
977 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
978 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
979 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
980 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
981 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
982 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
986 static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev,
987 int flow_type, u8 *tuple_sets)
991 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en;
994 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en;
997 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en;
1000 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en;
1003 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en;
1006 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en;
1010 *tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
1019 static u64 hclgevf_convert_rss_tuple(u8 tuple_sets)
1023 if (tuple_sets & HCLGEVF_D_PORT_BIT)
1024 tuple_data |= RXH_L4_B_2_3;
1025 if (tuple_sets & HCLGEVF_S_PORT_BIT)
1026 tuple_data |= RXH_L4_B_0_1;
1027 if (tuple_sets & HCLGEVF_D_IP_BIT)
1028 tuple_data |= RXH_IP_DST;
1029 if (tuple_sets & HCLGEVF_S_IP_BIT)
1030 tuple_data |= RXH_IP_SRC;
1035 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
1036 struct ethtool_rxnfc *nfc)
1038 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1042 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
1047 ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type,
1049 if (ret || !tuple_sets)
1052 nfc->data = hclgevf_convert_rss_tuple(tuple_sets);
1057 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
1058 struct hclgevf_rss_cfg *rss_cfg)
1060 struct hclgevf_rss_input_tuple_cmd *req;
1061 struct hclgevf_desc desc;
1064 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
1066 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
1068 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
1069 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
1070 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
1071 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
1072 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
1073 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
1074 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
1075 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
1077 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1079 dev_err(&hdev->pdev->dev,
1080 "Configure rss input fail, status = %d\n", ret);
1084 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
1086 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1087 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1089 return rss_cfg->rss_size;
1092 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
1094 struct hnae3_ring_chain_node *ring_chain)
1096 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1097 struct hclge_vf_to_pf_msg send_msg;
1098 struct hnae3_ring_chain_node *node;
1102 memset(&send_msg, 0, sizeof(send_msg));
1103 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :
1104 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
1105 send_msg.vector_id = vector_id;
1107 for (node = ring_chain; node; node = node->next) {
1108 send_msg.param[i].ring_type =
1109 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
1111 send_msg.param[i].tqp_index = node->tqp_index;
1112 send_msg.param[i].int_gl_index =
1113 hnae3_get_field(node->int_gl_idx,
1114 HNAE3_RING_GL_IDX_M,
1115 HNAE3_RING_GL_IDX_S);
1118 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {
1119 send_msg.ring_num = i;
1121 status = hclgevf_send_mbx_msg(hdev, &send_msg, false,
1124 dev_err(&hdev->pdev->dev,
1125 "Map TQP fail, status is %d.\n",
1136 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
1137 struct hnae3_ring_chain_node *ring_chain)
1139 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1142 vector_id = hclgevf_get_vector_index(hdev, vector);
1143 if (vector_id < 0) {
1144 dev_err(&handle->pdev->dev,
1145 "Get vector index fail. ret =%d\n", vector_id);
1149 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
1152 static int hclgevf_unmap_ring_from_vector(
1153 struct hnae3_handle *handle,
1155 struct hnae3_ring_chain_node *ring_chain)
1157 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1160 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1163 vector_id = hclgevf_get_vector_index(hdev, vector);
1164 if (vector_id < 0) {
1165 dev_err(&handle->pdev->dev,
1166 "Get vector index fail. ret =%d\n", vector_id);
1170 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
1172 dev_err(&handle->pdev->dev,
1173 "Unmap ring from vector fail. vector=%d, ret =%d\n",
1180 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
1182 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1185 vector_id = hclgevf_get_vector_index(hdev, vector);
1186 if (vector_id < 0) {
1187 dev_err(&handle->pdev->dev,
1188 "hclgevf_put_vector get vector index fail. ret =%d\n",
1193 hclgevf_free_vector(hdev, vector_id);
1198 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
1199 bool en_uc_pmc, bool en_mc_pmc,
1202 struct hnae3_handle *handle = &hdev->nic;
1203 struct hclge_vf_to_pf_msg send_msg;
1206 memset(&send_msg, 0, sizeof(send_msg));
1207 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;
1208 send_msg.en_bc = en_bc_pmc ? 1 : 0;
1209 send_msg.en_uc = en_uc_pmc ? 1 : 0;
1210 send_msg.en_mc = en_mc_pmc ? 1 : 0;
1211 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC,
1212 &handle->priv_flags) ? 1 : 0;
1214 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1216 dev_err(&hdev->pdev->dev,
1217 "Set promisc mode fail, status is %d.\n", ret);
1222 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
1225 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1228 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;
1230 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
1234 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
1236 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1238 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1239 hclgevf_task_schedule(hdev, 0);
1242 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
1244 struct hnae3_handle *handle = &hdev->nic;
1245 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;
1246 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;
1249 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {
1250 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);
1252 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1256 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id,
1257 u16 stream_id, bool enable)
1259 struct hclgevf_cfg_com_tqp_queue_cmd *req;
1260 struct hclgevf_desc desc;
1262 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
1264 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
1266 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
1267 req->stream_id = cpu_to_le16(stream_id);
1269 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;
1271 return hclgevf_cmd_send(&hdev->hw, &desc, 1);
1274 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable)
1276 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1280 for (i = 0; i < handle->kinfo.num_tqps; i++) {
1281 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable);
1289 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
1291 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1292 struct hclgevf_tqp *tqp;
1295 for (i = 0; i < kinfo->num_tqps; i++) {
1296 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
1297 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
1301 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)
1303 struct hclge_vf_to_pf_msg send_msg;
1304 u8 host_mac[ETH_ALEN];
1307 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);
1308 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,
1311 dev_err(&hdev->pdev->dev,
1312 "fail to get VF MAC from host %d", status);
1316 ether_addr_copy(p, host_mac);
1321 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
1323 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1324 u8 host_mac_addr[ETH_ALEN];
1326 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))
1329 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);
1330 if (hdev->has_pf_mac)
1331 ether_addr_copy(p, host_mac_addr);
1333 ether_addr_copy(p, hdev->hw.mac.mac_addr);
1336 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
1339 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1340 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
1341 struct hclge_vf_to_pf_msg send_msg;
1342 u8 *new_mac_addr = (u8 *)p;
1345 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);
1346 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;
1347 ether_addr_copy(send_msg.data, new_mac_addr);
1348 if (is_first && !hdev->has_pf_mac)
1349 eth_zero_addr(&send_msg.data[ETH_ALEN]);
1351 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);
1352 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1354 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
1359 static struct hclgevf_mac_addr_node *
1360 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)
1362 struct hclgevf_mac_addr_node *mac_node, *tmp;
1364 list_for_each_entry_safe(mac_node, tmp, list, node)
1365 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
1371 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,
1372 enum HCLGEVF_MAC_NODE_STATE state)
1375 /* from set_rx_mode or tmp_add_list */
1376 case HCLGEVF_MAC_TO_ADD:
1377 if (mac_node->state == HCLGEVF_MAC_TO_DEL)
1378 mac_node->state = HCLGEVF_MAC_ACTIVE;
1380 /* only from set_rx_mode */
1381 case HCLGEVF_MAC_TO_DEL:
1382 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1383 list_del(&mac_node->node);
1386 mac_node->state = HCLGEVF_MAC_TO_DEL;
1389 /* only from tmp_add_list, the mac_node->state won't be
1390 * HCLGEVF_MAC_ACTIVE
1392 case HCLGEVF_MAC_ACTIVE:
1393 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1394 mac_node->state = HCLGEVF_MAC_ACTIVE;
1399 static int hclgevf_update_mac_list(struct hnae3_handle *handle,
1400 enum HCLGEVF_MAC_NODE_STATE state,
1401 enum HCLGEVF_MAC_ADDR_TYPE mac_type,
1402 const unsigned char *addr)
1404 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1405 struct hclgevf_mac_addr_node *mac_node;
1406 struct list_head *list;
1408 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1409 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1411 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1413 /* if the mac addr is already in the mac list, no need to add a new
1414 * one into it, just check the mac addr state, convert it to a new
1415 * new state, or just remove it, or do nothing.
1417 mac_node = hclgevf_find_mac_node(list, addr);
1419 hclgevf_update_mac_node(mac_node, state);
1420 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1423 /* if this address is never added, unnecessary to delete */
1424 if (state == HCLGEVF_MAC_TO_DEL) {
1425 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1429 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
1431 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1435 mac_node->state = state;
1436 ether_addr_copy(mac_node->mac_addr, addr);
1437 list_add_tail(&mac_node->node, list);
1439 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1443 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
1444 const unsigned char *addr)
1446 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1447 HCLGEVF_MAC_ADDR_UC, addr);
1450 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1451 const unsigned char *addr)
1453 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1454 HCLGEVF_MAC_ADDR_UC, addr);
1457 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1458 const unsigned char *addr)
1460 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1461 HCLGEVF_MAC_ADDR_MC, addr);
1464 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1465 const unsigned char *addr)
1467 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1468 HCLGEVF_MAC_ADDR_MC, addr);
1471 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,
1472 struct hclgevf_mac_addr_node *mac_node,
1473 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1475 struct hclge_vf_to_pf_msg send_msg;
1478 if (mac_type == HCLGEVF_MAC_ADDR_UC) {
1479 code = HCLGE_MBX_SET_UNICAST;
1480 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1481 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;
1483 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;
1485 code = HCLGE_MBX_SET_MULTICAST;
1486 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1487 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;
1489 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;
1492 hclgevf_build_send_msg(&send_msg, code, subcode);
1493 ether_addr_copy(send_msg.data, mac_node->mac_addr);
1494 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1497 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,
1498 struct list_head *list,
1499 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1501 struct hclgevf_mac_addr_node *mac_node, *tmp;
1504 list_for_each_entry_safe(mac_node, tmp, list, node) {
1505 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);
1507 dev_err(&hdev->pdev->dev,
1508 "failed to configure mac %pM, state = %d, ret = %d\n",
1509 mac_node->mac_addr, mac_node->state, ret);
1512 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1513 mac_node->state = HCLGEVF_MAC_ACTIVE;
1515 list_del(&mac_node->node);
1521 static void hclgevf_sync_from_add_list(struct list_head *add_list,
1522 struct list_head *mac_list)
1524 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1526 list_for_each_entry_safe(mac_node, tmp, add_list, node) {
1527 /* if the mac address from tmp_add_list is not in the
1528 * uc/mc_mac_list, it means have received a TO_DEL request
1529 * during the time window of sending mac config request to PF
1530 * If mac_node state is ACTIVE, then change its state to TO_DEL,
1531 * then it will be removed at next time. If is TO_ADD, it means
1532 * send TO_ADD request failed, so just remove the mac node.
1534 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1536 hclgevf_update_mac_node(new_node, mac_node->state);
1537 list_del(&mac_node->node);
1539 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
1540 mac_node->state = HCLGEVF_MAC_TO_DEL;
1541 list_move_tail(&mac_node->node, mac_list);
1543 list_del(&mac_node->node);
1549 static void hclgevf_sync_from_del_list(struct list_head *del_list,
1550 struct list_head *mac_list)
1552 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1554 list_for_each_entry_safe(mac_node, tmp, del_list, node) {
1555 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1557 /* If the mac addr is exist in the mac list, it means
1558 * received a new request TO_ADD during the time window
1559 * of sending mac addr configurrequest to PF, so just
1560 * change the mac state to ACTIVE.
1562 new_node->state = HCLGEVF_MAC_ACTIVE;
1563 list_del(&mac_node->node);
1566 list_move_tail(&mac_node->node, mac_list);
1571 static void hclgevf_clear_list(struct list_head *list)
1573 struct hclgevf_mac_addr_node *mac_node, *tmp;
1575 list_for_each_entry_safe(mac_node, tmp, list, node) {
1576 list_del(&mac_node->node);
1581 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
1582 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1584 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1585 struct list_head tmp_add_list, tmp_del_list;
1586 struct list_head *list;
1588 INIT_LIST_HEAD(&tmp_add_list);
1589 INIT_LIST_HEAD(&tmp_del_list);
1591 /* move the mac addr to the tmp_add_list and tmp_del_list, then
1592 * we can add/delete these mac addr outside the spin lock
1594 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1595 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1597 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1599 list_for_each_entry_safe(mac_node, tmp, list, node) {
1600 switch (mac_node->state) {
1601 case HCLGEVF_MAC_TO_DEL:
1602 list_move_tail(&mac_node->node, &tmp_del_list);
1604 case HCLGEVF_MAC_TO_ADD:
1605 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
1609 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
1610 new_node->state = mac_node->state;
1611 list_add_tail(&new_node->node, &tmp_add_list);
1619 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1621 /* delete first, in order to get max mac table space for adding */
1622 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);
1623 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);
1625 /* if some mac addresses were added/deleted fail, move back to the
1626 * mac_list, and retry at next time.
1628 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1630 hclgevf_sync_from_del_list(&tmp_del_list, list);
1631 hclgevf_sync_from_add_list(&tmp_add_list, list);
1633 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1636 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)
1638 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);
1639 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);
1642 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)
1644 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1646 hclgevf_clear_list(&hdev->mac_table.uc_mac_list);
1647 hclgevf_clear_list(&hdev->mac_table.mc_mac_list);
1649 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1652 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
1654 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1655 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
1656 struct hclge_vf_to_pf_msg send_msg;
1658 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
1661 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1662 HCLGE_MBX_ENABLE_VLAN_FILTER);
1663 send_msg.data[0] = enable ? 1 : 0;
1665 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1668 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1669 __be16 proto, u16 vlan_id,
1672 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0
1673 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1
1674 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3
1676 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1677 struct hclge_vf_to_pf_msg send_msg;
1680 if (vlan_id > HCLGEVF_MAX_VLAN_ID)
1683 if (proto != htons(ETH_P_8021Q))
1684 return -EPROTONOSUPPORT;
1686 /* When device is resetting or reset failed, firmware is unable to
1687 * handle mailbox. Just record the vlan id, and remove it after
1690 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
1691 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {
1692 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1696 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1697 HCLGE_MBX_VLAN_FILTER);
1698 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill;
1699 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id,
1701 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto,
1703 /* when remove hw vlan filter failed, record the vlan id,
1704 * and try to remove it from hw later, to be consistence
1707 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1709 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1714 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)
1716 #define HCLGEVF_MAX_SYNC_COUNT 60
1717 struct hnae3_handle *handle = &hdev->nic;
1718 int ret, sync_cnt = 0;
1721 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1722 while (vlan_id != VLAN_N_VID) {
1723 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),
1728 clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1730 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)
1733 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1737 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1739 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1740 struct hclge_vf_to_pf_msg send_msg;
1742 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1743 HCLGE_MBX_VLAN_RX_OFF_CFG);
1744 send_msg.data[0] = enable ? 1 : 0;
1745 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1748 static int hclgevf_reset_tqp(struct hnae3_handle *handle)
1750 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U
1751 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1752 struct hclge_vf_to_pf_msg send_msg;
1753 u8 return_status = 0;
1757 /* disable vf queue before send queue reset msg to PF */
1758 ret = hclgevf_tqp_enable(handle, false);
1760 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n",
1765 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1767 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status,
1768 sizeof(return_status));
1769 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE)
1772 for (i = 1; i < handle->kinfo.num_tqps; i++) {
1773 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1774 memcpy(send_msg.data, &i, sizeof(i));
1775 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1783 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1785 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1786 struct hclge_vf_to_pf_msg send_msg;
1788 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);
1789 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu));
1790 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1793 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1794 enum hnae3_reset_notify_type type)
1796 struct hnae3_client *client = hdev->nic_client;
1797 struct hnae3_handle *handle = &hdev->nic;
1800 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||
1804 if (!client->ops->reset_notify)
1807 ret = client->ops->reset_notify(handle, type);
1809 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1815 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
1816 enum hnae3_reset_notify_type type)
1818 struct hnae3_client *client = hdev->roce_client;
1819 struct hnae3_handle *handle = &hdev->roce;
1822 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client)
1825 if (!client->ops->reset_notify)
1828 ret = client->ops->reset_notify(handle, type);
1830 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
1835 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1837 #define HCLGEVF_RESET_WAIT_US 20000
1838 #define HCLGEVF_RESET_WAIT_CNT 2000
1839 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \
1840 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1845 if (hdev->reset_type == HNAE3_VF_RESET)
1846 ret = readl_poll_timeout(hdev->hw.io_base +
1847 HCLGEVF_VF_RST_ING, val,
1848 !(val & HCLGEVF_VF_RST_ING_BIT),
1849 HCLGEVF_RESET_WAIT_US,
1850 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1852 ret = readl_poll_timeout(hdev->hw.io_base +
1853 HCLGEVF_RST_ING, val,
1854 !(val & HCLGEVF_RST_ING_BITS),
1855 HCLGEVF_RESET_WAIT_US,
1856 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1858 /* hardware completion status should be available by this time */
1860 dev_err(&hdev->pdev->dev,
1861 "couldn't get reset done status from h/w, timeout!\n");
1865 /* we will wait a bit more to let reset of the stack to complete. This
1866 * might happen in case reset assertion was made by PF. Yes, this also
1867 * means we might end up waiting bit more even for VF reset.
1874 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
1878 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
1880 reg_val |= HCLGEVF_NIC_SW_RST_RDY;
1882 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
1884 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG,
1888 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1892 /* uninitialize the nic client */
1893 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1897 /* re-initialize the hclge device */
1898 ret = hclgevf_reset_hdev(hdev);
1900 dev_err(&hdev->pdev->dev,
1901 "hclge device re-init failed, VF is disabled!\n");
1905 /* bring up the nic client again */
1906 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1910 /* clear handshake status with IMP */
1911 hclgevf_reset_handshake(hdev, false);
1913 /* bring up the nic to enable TX/RX again */
1914 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1917 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1919 #define HCLGEVF_RESET_SYNC_TIME 100
1921 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
1922 struct hclge_vf_to_pf_msg send_msg;
1925 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);
1926 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1928 dev_err(&hdev->pdev->dev,
1929 "failed to assert VF reset, ret = %d\n", ret);
1932 hdev->rst_stats.vf_func_rst_cnt++;
1935 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1936 /* inform hardware that preparatory work is done */
1937 msleep(HCLGEVF_RESET_SYNC_TIME);
1938 hclgevf_reset_handshake(hdev, true);
1939 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n",
1945 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
1947 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
1948 hdev->rst_stats.vf_func_rst_cnt);
1949 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1950 hdev->rst_stats.flr_rst_cnt);
1951 dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
1952 hdev->rst_stats.vf_rst_cnt);
1953 dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1954 hdev->rst_stats.rst_done_cnt);
1955 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1956 hdev->rst_stats.hw_rst_done_cnt);
1957 dev_info(&hdev->pdev->dev, "reset count: %u\n",
1958 hdev->rst_stats.rst_cnt);
1959 dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1960 hdev->rst_stats.rst_fail_cnt);
1961 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1962 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
1963 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
1964 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
1965 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1966 hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG));
1967 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1968 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
1969 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1972 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
1974 /* recover handshake status with IMP when reset fail */
1975 hclgevf_reset_handshake(hdev, true);
1976 hdev->rst_stats.rst_fail_cnt++;
1977 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
1978 hdev->rst_stats.rst_fail_cnt);
1980 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1981 set_bit(hdev->reset_type, &hdev->reset_pending);
1983 if (hclgevf_is_reset_pending(hdev)) {
1984 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1985 hclgevf_reset_task_schedule(hdev);
1987 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1988 hclgevf_dump_rst_info(hdev);
1992 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
1996 hdev->rst_stats.rst_cnt++;
1998 /* perform reset of the stack & ae device for a client */
1999 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2004 /* bring down the nic to stop any ongoing TX/RX */
2005 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
2010 return hclgevf_reset_prepare_wait(hdev);
2013 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
2017 hdev->rst_stats.hw_rst_done_cnt++;
2018 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2023 /* now, re-initialize the nic client and ae device */
2024 ret = hclgevf_reset_stack(hdev);
2027 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
2031 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2032 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1
2036 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1)
2039 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2043 hdev->last_reset_time = jiffies;
2044 hdev->rst_stats.rst_done_cnt++;
2045 hdev->rst_stats.rst_fail_cnt = 0;
2046 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2051 static void hclgevf_reset(struct hclgevf_dev *hdev)
2053 if (hclgevf_reset_prepare(hdev))
2056 /* check if VF could successfully fetch the hardware reset completion
2057 * status from the hardware
2059 if (hclgevf_reset_wait(hdev)) {
2060 /* can't do much in this situation, will disable VF */
2061 dev_err(&hdev->pdev->dev,
2062 "failed to fetch H/W reset completion status\n");
2066 if (hclgevf_reset_rebuild(hdev))
2072 hclgevf_reset_err_handle(hdev);
2075 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
2076 unsigned long *addr)
2078 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2080 /* return the highest priority reset level amongst all */
2081 if (test_bit(HNAE3_VF_RESET, addr)) {
2082 rst_level = HNAE3_VF_RESET;
2083 clear_bit(HNAE3_VF_RESET, addr);
2084 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
2085 clear_bit(HNAE3_VF_FUNC_RESET, addr);
2086 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
2087 rst_level = HNAE3_VF_FULL_RESET;
2088 clear_bit(HNAE3_VF_FULL_RESET, addr);
2089 clear_bit(HNAE3_VF_FUNC_RESET, addr);
2090 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
2091 rst_level = HNAE3_VF_PF_FUNC_RESET;
2092 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
2093 clear_bit(HNAE3_VF_FUNC_RESET, addr);
2094 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
2095 rst_level = HNAE3_VF_FUNC_RESET;
2096 clear_bit(HNAE3_VF_FUNC_RESET, addr);
2097 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
2098 rst_level = HNAE3_FLR_RESET;
2099 clear_bit(HNAE3_FLR_RESET, addr);
2105 static void hclgevf_reset_event(struct pci_dev *pdev,
2106 struct hnae3_handle *handle)
2108 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2109 struct hclgevf_dev *hdev = ae_dev->priv;
2111 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
2113 if (hdev->default_reset_request)
2115 hclgevf_get_reset_level(hdev,
2116 &hdev->default_reset_request);
2118 hdev->reset_level = HNAE3_VF_FUNC_RESET;
2120 /* reset of this VF requested */
2121 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
2122 hclgevf_reset_task_schedule(hdev);
2124 hdev->last_reset_time = jiffies;
2127 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2128 enum hnae3_reset_type rst_type)
2130 struct hclgevf_dev *hdev = ae_dev->priv;
2132 set_bit(rst_type, &hdev->default_reset_request);
2135 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
2137 writel(en ? 1 : 0, vector->addr);
2140 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
2141 enum hnae3_reset_type rst_type)
2143 #define HCLGEVF_RESET_RETRY_WAIT_MS 500
2144 #define HCLGEVF_RESET_RETRY_CNT 5
2146 struct hclgevf_dev *hdev = ae_dev->priv;
2151 down(&hdev->reset_sem);
2152 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2153 hdev->reset_type = rst_type;
2154 ret = hclgevf_reset_prepare(hdev);
2156 dev_err(&hdev->pdev->dev, "fail to prepare to reset, ret=%d\n",
2158 if (hdev->reset_pending ||
2159 retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) {
2160 dev_err(&hdev->pdev->dev,
2161 "reset_pending:0x%lx, retry_cnt:%d\n",
2162 hdev->reset_pending, retry_cnt);
2163 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2164 up(&hdev->reset_sem);
2165 msleep(HCLGEVF_RESET_RETRY_WAIT_MS);
2170 /* disable misc vector before reset done */
2171 hclgevf_enable_vector(&hdev->misc_vector, false);
2173 if (hdev->reset_type == HNAE3_FLR_RESET)
2174 hdev->rst_stats.flr_rst_cnt++;
2177 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev)
2179 struct hclgevf_dev *hdev = ae_dev->priv;
2182 hclgevf_enable_vector(&hdev->misc_vector, true);
2184 ret = hclgevf_reset_rebuild(hdev);
2186 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
2189 hdev->reset_type = HNAE3_NONE_RESET;
2190 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2191 up(&hdev->reset_sem);
2194 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
2196 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2198 return hdev->fw_version;
2201 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
2203 struct hclgevf_misc_vector *vector = &hdev->misc_vector;
2205 vector->vector_irq = pci_irq_vector(hdev->pdev,
2206 HCLGEVF_MISC_VECTOR_NUM);
2207 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
2208 /* vector status always valid for Vector 0 */
2209 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
2210 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
2212 hdev->num_msi_left -= 1;
2213 hdev->num_msi_used += 1;
2216 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
2218 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2219 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,
2221 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2224 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
2226 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2227 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,
2229 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2232 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
2233 unsigned long delay)
2235 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2236 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2237 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);
2240 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
2242 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3
2244 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
2247 down(&hdev->reset_sem);
2248 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2250 if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
2251 &hdev->reset_state)) {
2252 /* PF has intimated that it is about to reset the hardware.
2253 * We now have to poll & check if hardware has actually
2254 * completed the reset sequence. On hardware reset completion,
2255 * VF needs to reset the client and ae device.
2257 hdev->reset_attempts = 0;
2259 hdev->last_reset_time = jiffies;
2260 while ((hdev->reset_type =
2261 hclgevf_get_reset_level(hdev, &hdev->reset_pending))
2262 != HNAE3_NONE_RESET)
2263 hclgevf_reset(hdev);
2264 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
2265 &hdev->reset_state)) {
2266 /* we could be here when either of below happens:
2267 * 1. reset was initiated due to watchdog timeout caused by
2268 * a. IMP was earlier reset and our TX got choked down and
2269 * which resulted in watchdog reacting and inducing VF
2270 * reset. This also means our cmdq would be unreliable.
2271 * b. problem in TX due to other lower layer(example link
2272 * layer not functioning properly etc.)
2273 * 2. VF reset might have been initiated due to some config
2276 * NOTE: Theres no clear way to detect above cases than to react
2277 * to the response of PF for this reset request. PF will ack the
2278 * 1b and 2. cases but we will not get any intimation about 1a
2279 * from PF as cmdq would be in unreliable state i.e. mailbox
2280 * communication between PF and VF would be broken.
2282 * if we are never geting into pending state it means either:
2283 * 1. PF is not receiving our request which could be due to IMP
2286 * We cannot do much for 2. but to check first we can try reset
2287 * our PCIe + stack and see if it alleviates the problem.
2289 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
2290 /* prepare for full reset of stack + pcie interface */
2291 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
2293 /* "defer" schedule the reset task again */
2294 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2296 hdev->reset_attempts++;
2298 set_bit(hdev->reset_level, &hdev->reset_pending);
2299 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2301 hclgevf_reset_task_schedule(hdev);
2304 hdev->reset_type = HNAE3_NONE_RESET;
2305 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2306 up(&hdev->reset_sem);
2309 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
2311 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))
2314 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
2317 hclgevf_mbx_async_handler(hdev);
2319 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2322 static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
2324 struct hclge_vf_to_pf_msg send_msg;
2327 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
2330 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
2331 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2333 dev_err(&hdev->pdev->dev,
2334 "VF sends keep alive cmd failed(=%d)\n", ret);
2337 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
2339 unsigned long delta = round_jiffies_relative(HZ);
2340 struct hnae3_handle *handle = &hdev->nic;
2342 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2345 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
2346 delta = jiffies - hdev->last_serv_processed;
2348 if (delta < round_jiffies_relative(HZ)) {
2349 delta = round_jiffies_relative(HZ) - delta;
2354 hdev->serv_processed_cnt++;
2355 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))
2356 hclgevf_keep_alive(hdev);
2358 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {
2359 hdev->last_serv_processed = jiffies;
2363 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))
2364 hclgevf_tqps_update_stats(handle);
2366 /* VF does not need to request link status when this bit is set, because
2367 * PF will push its link status to VFs when link status changed.
2369 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state))
2370 hclgevf_request_link_info(hdev);
2372 hclgevf_update_link_mode(hdev);
2374 hclgevf_sync_vlan_filter(hdev);
2376 hclgevf_sync_mac_table(hdev);
2378 hclgevf_sync_promisc_mode(hdev);
2380 hdev->last_serv_processed = jiffies;
2383 hclgevf_task_schedule(hdev, delta);
2386 static void hclgevf_service_task(struct work_struct *work)
2388 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,
2391 hclgevf_reset_service_task(hdev);
2392 hclgevf_mailbox_service_task(hdev);
2393 hclgevf_periodic_service_task(hdev);
2395 /* Handle reset and mbx again in case periodical task delays the
2396 * handling by calling hclgevf_task_schedule() in
2397 * hclgevf_periodic_service_task()
2399 hclgevf_reset_service_task(hdev);
2400 hclgevf_mailbox_service_task(hdev);
2403 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
2405 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
2408 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
2411 u32 val, cmdq_stat_reg, rst_ing_reg;
2413 /* fetch the events from their corresponding regs */
2414 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
2415 HCLGEVF_VECTOR0_CMDQ_STATE_REG);
2416 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
2417 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
2418 dev_info(&hdev->pdev->dev,
2419 "receive reset interrupt 0x%x!\n", rst_ing_reg);
2420 set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
2421 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2422 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
2423 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
2424 hdev->rst_stats.vf_rst_cnt++;
2425 /* set up VF hardware reset status, its PF will clear
2426 * this status when PF has initialized done.
2428 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
2429 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,
2430 val | HCLGEVF_VF_RST_ING_BIT);
2431 return HCLGEVF_VECTOR0_EVENT_RST;
2434 /* check for vector0 mailbox(=CMDQ RX) event source */
2435 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
2436 /* for revision 0x21, clearing interrupt is writing bit 0
2437 * to the clear register, writing bit 1 means to keep the
2439 * for revision 0x20, the clear register is a read & write
2440 * register, so we should just write 0 to the bit we are
2441 * handling, and keep other bits as cmdq_stat_reg.
2443 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
2444 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2446 *clearval = cmdq_stat_reg &
2447 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2449 return HCLGEVF_VECTOR0_EVENT_MBX;
2452 /* print other vector0 event source */
2453 dev_info(&hdev->pdev->dev,
2454 "vector 0 interrupt from unknown source, cmdq_src = %#x\n",
2457 return HCLGEVF_VECTOR0_EVENT_OTHER;
2460 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
2462 enum hclgevf_evt_cause event_cause;
2463 struct hclgevf_dev *hdev = data;
2466 hclgevf_enable_vector(&hdev->misc_vector, false);
2467 event_cause = hclgevf_check_evt_cause(hdev, &clearval);
2469 switch (event_cause) {
2470 case HCLGEVF_VECTOR0_EVENT_RST:
2471 hclgevf_reset_task_schedule(hdev);
2473 case HCLGEVF_VECTOR0_EVENT_MBX:
2474 hclgevf_mbx_handler(hdev);
2480 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) {
2481 hclgevf_clear_event_cause(hdev, clearval);
2482 hclgevf_enable_vector(&hdev->misc_vector, true);
2488 static int hclgevf_configure(struct hclgevf_dev *hdev)
2492 hdev->gro_en = true;
2494 ret = hclgevf_get_basic_info(hdev);
2498 /* get current port based vlan state from PF */
2499 ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2503 /* get queue configuration from PF */
2504 ret = hclgevf_get_queue_info(hdev);
2508 /* get queue depth info from PF */
2509 ret = hclgevf_get_queue_depth(hdev);
2513 return hclgevf_get_pf_media_type(hdev);
2516 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
2518 struct pci_dev *pdev = ae_dev->pdev;
2519 struct hclgevf_dev *hdev;
2521 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
2526 hdev->ae_dev = ae_dev;
2527 ae_dev->priv = hdev;
2532 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
2534 struct hnae3_handle *roce = &hdev->roce;
2535 struct hnae3_handle *nic = &hdev->nic;
2537 roce->rinfo.num_vectors = hdev->num_roce_msix;
2539 if (hdev->num_msi_left < roce->rinfo.num_vectors ||
2540 hdev->num_msi_left == 0)
2543 roce->rinfo.base_vector = hdev->roce_base_vector;
2545 roce->rinfo.netdev = nic->kinfo.netdev;
2546 roce->rinfo.roce_io_base = hdev->hw.io_base;
2547 roce->rinfo.roce_mem_base = hdev->hw.mem_base;
2549 roce->pdev = nic->pdev;
2550 roce->ae_algo = nic->ae_algo;
2551 roce->numa_node_mask = nic->numa_node_mask;
2556 static int hclgevf_config_gro(struct hclgevf_dev *hdev)
2558 struct hclgevf_cfg_gro_status_cmd *req;
2559 struct hclgevf_desc desc;
2562 if (!hnae3_dev_gro_supported(hdev))
2565 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
2567 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
2569 req->gro_en = hdev->gro_en ? 1 : 0;
2571 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2573 dev_err(&hdev->pdev->dev,
2574 "VF GRO hardware config cmd failed, ret = %d.\n", ret);
2579 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev)
2581 u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size;
2582 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2583 struct hclgevf_rss_tuple_cfg *tuple_sets;
2586 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
2587 rss_cfg->rss_size = hdev->nic.kinfo.rss_size;
2588 tuple_sets = &rss_cfg->rss_tuple_sets;
2589 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2592 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
2594 rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size,
2595 sizeof(*rss_ind_tbl), GFP_KERNEL);
2599 rss_cfg->rss_indirection_tbl = rss_ind_tbl;
2600 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key,
2601 HCLGEVF_RSS_KEY_SIZE);
2603 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2604 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2605 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2606 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2607 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2608 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2609 tuple_sets->ipv6_sctp_en =
2610 hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ?
2611 HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT :
2612 HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2613 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2616 /* Initialize RSS indirect table */
2617 for (i = 0; i < rss_ind_tbl_size; i++)
2618 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size;
2623 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
2625 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2628 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2629 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
2630 rss_cfg->rss_hash_key);
2634 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
2639 ret = hclgevf_set_rss_indir_table(hdev);
2643 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size);
2646 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2648 struct hnae3_handle *nic = &hdev->nic;
2651 ret = hclgevf_en_hw_strip_rxvtag(nic, true);
2653 dev_err(&hdev->pdev->dev,
2654 "failed to enable rx vlan offload, ret = %d\n", ret);
2658 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2662 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)
2664 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000
2666 unsigned long last = hdev->serv_processed_cnt;
2669 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&
2670 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&
2671 last == hdev->serv_processed_cnt)
2675 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2677 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2680 hclgevf_task_schedule(hdev, 0);
2682 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2684 /* flush memory to make sure DOWN is seen by service task */
2685 smp_mb__before_atomic();
2686 hclgevf_flush_link_update(hdev);
2690 static int hclgevf_ae_start(struct hnae3_handle *handle)
2692 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2694 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2695 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state);
2697 hclgevf_reset_tqp_stats(handle);
2699 hclgevf_request_link_info(hdev);
2701 hclgevf_update_link_mode(hdev);
2706 static void hclgevf_ae_stop(struct hnae3_handle *handle)
2708 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2710 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2712 if (hdev->reset_type != HNAE3_VF_RESET)
2713 hclgevf_reset_tqp(handle);
2715 hclgevf_reset_tqp_stats(handle);
2716 hclgevf_update_link_status(hdev, 0);
2719 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2721 #define HCLGEVF_STATE_ALIVE 1
2722 #define HCLGEVF_STATE_NOT_ALIVE 0
2724 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2725 struct hclge_vf_to_pf_msg send_msg;
2727 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);
2728 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :
2729 HCLGEVF_STATE_NOT_ALIVE;
2730 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2733 static int hclgevf_client_start(struct hnae3_handle *handle)
2735 return hclgevf_set_alive(handle, true);
2738 static void hclgevf_client_stop(struct hnae3_handle *handle)
2740 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2743 ret = hclgevf_set_alive(handle, false);
2745 dev_warn(&hdev->pdev->dev,
2746 "%s failed %d\n", __func__, ret);
2749 static void hclgevf_state_init(struct hclgevf_dev *hdev)
2751 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2752 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2753 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2755 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
2757 mutex_init(&hdev->mbx_resp.mbx_mutex);
2758 sema_init(&hdev->reset_sem, 1);
2760 spin_lock_init(&hdev->mac_table.mac_list_lock);
2761 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);
2762 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);
2764 /* bring the device down */
2765 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2768 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2770 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2771 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);
2773 if (hdev->service_task.work.func)
2774 cancel_delayed_work_sync(&hdev->service_task);
2776 mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2779 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2781 struct pci_dev *pdev = hdev->pdev;
2785 if (hnae3_dev_roce_supported(hdev))
2786 vectors = pci_alloc_irq_vectors(pdev,
2787 hdev->roce_base_msix_offset + 1,
2791 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2793 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2797 "failed(%d) to allocate MSI/MSI-X vectors\n",
2801 if (vectors < hdev->num_msi)
2802 dev_warn(&hdev->pdev->dev,
2803 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2804 hdev->num_msi, vectors);
2806 hdev->num_msi = vectors;
2807 hdev->num_msi_left = vectors;
2809 hdev->base_msi_vector = pdev->irq;
2810 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
2812 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2813 sizeof(u16), GFP_KERNEL);
2814 if (!hdev->vector_status) {
2815 pci_free_irq_vectors(pdev);
2819 for (i = 0; i < hdev->num_msi; i++)
2820 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2822 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2823 sizeof(int), GFP_KERNEL);
2824 if (!hdev->vector_irq) {
2825 devm_kfree(&pdev->dev, hdev->vector_status);
2826 pci_free_irq_vectors(pdev);
2833 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2835 struct pci_dev *pdev = hdev->pdev;
2837 devm_kfree(&pdev->dev, hdev->vector_status);
2838 devm_kfree(&pdev->dev, hdev->vector_irq);
2839 pci_free_irq_vectors(pdev);
2842 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2846 hclgevf_get_misc_vector(hdev);
2848 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
2849 HCLGEVF_NAME, pci_name(hdev->pdev));
2850 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2851 0, hdev->misc_vector.name, hdev);
2853 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2854 hdev->misc_vector.vector_irq);
2858 hclgevf_clear_event_cause(hdev, 0);
2860 /* enable misc. vector(vector 0) */
2861 hclgevf_enable_vector(&hdev->misc_vector, true);
2866 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2868 /* disable misc vector(vector 0) */
2869 hclgevf_enable_vector(&hdev->misc_vector, false);
2870 synchronize_irq(hdev->misc_vector.vector_irq);
2871 free_irq(hdev->misc_vector.vector_irq, hdev);
2872 hclgevf_free_vector(hdev, 0);
2875 static void hclgevf_info_show(struct hclgevf_dev *hdev)
2877 struct device *dev = &hdev->pdev->dev;
2879 dev_info(dev, "VF info begin:\n");
2881 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
2882 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
2883 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
2884 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
2885 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
2886 dev_info(dev, "PF media type of this VF: %u\n",
2887 hdev->hw.mac.media_type);
2889 dev_info(dev, "VF info end.\n");
2892 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
2893 struct hnae3_client *client)
2895 struct hclgevf_dev *hdev = ae_dev->priv;
2896 int rst_cnt = hdev->rst_stats.rst_cnt;
2899 ret = client->ops->init_instance(&hdev->nic);
2903 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2904 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
2905 rst_cnt != hdev->rst_stats.rst_cnt) {
2906 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2908 client->ops->uninit_instance(&hdev->nic, 0);
2912 hnae3_set_client_init_flag(client, ae_dev, 1);
2914 if (netif_msg_drv(&hdev->nic))
2915 hclgevf_info_show(hdev);
2920 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
2921 struct hnae3_client *client)
2923 struct hclgevf_dev *hdev = ae_dev->priv;
2926 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
2930 ret = hclgevf_init_roce_base_info(hdev);
2934 ret = client->ops->init_instance(&hdev->roce);
2938 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2939 hnae3_set_client_init_flag(client, ae_dev, 1);
2944 static int hclgevf_init_client_instance(struct hnae3_client *client,
2945 struct hnae3_ae_dev *ae_dev)
2947 struct hclgevf_dev *hdev = ae_dev->priv;
2950 switch (client->type) {
2951 case HNAE3_CLIENT_KNIC:
2952 hdev->nic_client = client;
2953 hdev->nic.client = client;
2955 ret = hclgevf_init_nic_client_instance(ae_dev, client);
2959 ret = hclgevf_init_roce_client_instance(ae_dev,
2965 case HNAE3_CLIENT_ROCE:
2966 if (hnae3_dev_roce_supported(hdev)) {
2967 hdev->roce_client = client;
2968 hdev->roce.client = client;
2971 ret = hclgevf_init_roce_client_instance(ae_dev, client);
2983 hdev->nic_client = NULL;
2984 hdev->nic.client = NULL;
2987 hdev->roce_client = NULL;
2988 hdev->roce.client = NULL;
2992 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2993 struct hnae3_ae_dev *ae_dev)
2995 struct hclgevf_dev *hdev = ae_dev->priv;
2997 /* un-init roce, if it exists */
2998 if (hdev->roce_client) {
2999 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
3000 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
3001 hdev->roce_client = NULL;
3002 hdev->roce.client = NULL;
3005 /* un-init nic/unic, if this was not called by roce client */
3006 if (client->ops->uninit_instance && hdev->nic_client &&
3007 client->type != HNAE3_CLIENT_ROCE) {
3008 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
3010 client->ops->uninit_instance(&hdev->nic, 0);
3011 hdev->nic_client = NULL;
3012 hdev->nic.client = NULL;
3016 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)
3018 #define HCLGEVF_MEM_BAR 4
3020 struct pci_dev *pdev = hdev->pdev;
3021 struct hclgevf_hw *hw = &hdev->hw;
3023 /* for device does not have device memory, return directly */
3024 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))
3027 hw->mem_base = devm_ioremap_wc(&pdev->dev,
3028 pci_resource_start(pdev,
3030 pci_resource_len(pdev, HCLGEVF_MEM_BAR));
3031 if (!hw->mem_base) {
3032 dev_err(&pdev->dev, "failed to map device memory\n");
3039 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
3041 struct pci_dev *pdev = hdev->pdev;
3042 struct hclgevf_hw *hw;
3045 ret = pci_enable_device(pdev);
3047 dev_err(&pdev->dev, "failed to enable PCI device\n");
3051 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3053 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
3054 goto err_disable_device;
3057 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
3059 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
3060 goto err_disable_device;
3063 pci_set_master(pdev);
3066 hw->io_base = pci_iomap(pdev, 2, 0);
3068 dev_err(&pdev->dev, "can't map configuration register space\n");
3070 goto err_clr_master;
3073 ret = hclgevf_dev_mem_map(hdev);
3075 goto err_unmap_io_base;
3080 pci_iounmap(pdev, hdev->hw.io_base);
3082 pci_clear_master(pdev);
3083 pci_release_regions(pdev);
3085 pci_disable_device(pdev);
3090 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
3092 struct pci_dev *pdev = hdev->pdev;
3094 if (hdev->hw.mem_base)
3095 devm_iounmap(&pdev->dev, hdev->hw.mem_base);
3097 pci_iounmap(pdev, hdev->hw.io_base);
3098 pci_clear_master(pdev);
3099 pci_release_regions(pdev);
3100 pci_disable_device(pdev);
3103 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
3105 struct hclgevf_query_res_cmd *req;
3106 struct hclgevf_desc desc;
3109 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
3110 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
3112 dev_err(&hdev->pdev->dev,
3113 "query vf resource failed, ret = %d.\n", ret);
3117 req = (struct hclgevf_query_res_cmd *)desc.data;
3119 if (hnae3_dev_roce_supported(hdev)) {
3120 hdev->roce_base_msix_offset =
3121 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
3122 HCLGEVF_MSIX_OFT_ROCEE_M,
3123 HCLGEVF_MSIX_OFT_ROCEE_S);
3124 hdev->num_roce_msix =
3125 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
3126 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
3128 /* nic's msix numbers is always equals to the roce's. */
3129 hdev->num_nic_msix = hdev->num_roce_msix;
3131 /* VF should have NIC vectors and Roce vectors, NIC vectors
3132 * are queued before Roce vectors. The offset is fixed to 64.
3134 hdev->num_msi = hdev->num_roce_msix +
3135 hdev->roce_base_msix_offset;
3138 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
3139 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
3141 hdev->num_nic_msix = hdev->num_msi;
3144 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
3145 dev_err(&hdev->pdev->dev,
3146 "Just %u msi resources, not enough for vf(min:2).\n",
3147 hdev->num_nic_msix);
3154 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
3156 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U
3158 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3160 ae_dev->dev_specs.max_non_tso_bd_num =
3161 HCLGEVF_MAX_NON_TSO_BD_NUM;
3162 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3163 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3164 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3165 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME;
3168 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
3169 struct hclgevf_desc *desc)
3171 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3172 struct hclgevf_dev_specs_0_cmd *req0;
3173 struct hclgevf_dev_specs_1_cmd *req1;
3175 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
3176 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;
3178 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
3179 ae_dev->dev_specs.rss_ind_tbl_size =
3180 le16_to_cpu(req0->rss_ind_tbl_size);
3181 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
3182 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
3183 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
3184 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
3187 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)
3189 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
3191 if (!dev_specs->max_non_tso_bd_num)
3192 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM;
3193 if (!dev_specs->rss_ind_tbl_size)
3194 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3195 if (!dev_specs->rss_key_size)
3196 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3197 if (!dev_specs->max_int_gl)
3198 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3199 if (!dev_specs->max_frm_size)
3200 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME;
3203 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
3205 struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
3209 /* set default specifications as devices lower than version V3 do not
3210 * support querying specifications from firmware.
3212 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
3213 hclgevf_set_default_dev_specs(hdev);
3217 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3218 hclgevf_cmd_setup_basic_desc(&desc[i],
3219 HCLGEVF_OPC_QUERY_DEV_SPECS, true);
3220 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT);
3222 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS,
3225 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);
3229 hclgevf_parse_dev_specs(hdev, desc);
3230 hclgevf_check_dev_specs(hdev);
3235 static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
3237 struct pci_dev *pdev = hdev->pdev;
3240 if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
3241 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3242 hclgevf_misc_irq_uninit(hdev);
3243 hclgevf_uninit_msi(hdev);
3244 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3247 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3248 pci_set_master(pdev);
3249 ret = hclgevf_init_msi(hdev);
3252 "failed(%d) to init MSI/MSI-X\n", ret);
3256 ret = hclgevf_misc_irq_init(hdev);
3258 hclgevf_uninit_msi(hdev);
3259 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
3264 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3270 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)
3272 struct hclge_vf_to_pf_msg send_msg;
3274 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,
3275 HCLGE_MBX_VPORT_LIST_CLEAR);
3276 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3279 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev)
3281 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
3282 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1);
3285 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev)
3287 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
3288 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0);
3291 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
3293 struct pci_dev *pdev = hdev->pdev;
3296 ret = hclgevf_pci_reset(hdev);
3298 dev_err(&pdev->dev, "pci reset failed %d\n", ret);
3302 ret = hclgevf_cmd_init(hdev);
3304 dev_err(&pdev->dev, "cmd failed %d\n", ret);
3308 ret = hclgevf_rss_init_hw(hdev);
3310 dev_err(&hdev->pdev->dev,
3311 "failed(%d) to initialize RSS\n", ret);
3315 ret = hclgevf_config_gro(hdev);
3319 ret = hclgevf_init_vlan_config(hdev);
3321 dev_err(&hdev->pdev->dev,
3322 "failed(%d) to initialize VLAN config\n", ret);
3326 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
3328 hclgevf_init_rxd_adv_layout(hdev);
3330 dev_info(&hdev->pdev->dev, "Reset done\n");
3335 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
3337 struct pci_dev *pdev = hdev->pdev;
3340 ret = hclgevf_pci_init(hdev);
3344 ret = hclgevf_devlink_init(hdev);
3346 goto err_devlink_init;
3348 ret = hclgevf_cmd_queue_init(hdev);
3350 goto err_cmd_queue_init;
3352 ret = hclgevf_cmd_init(hdev);
3356 /* Get vf resource */
3357 ret = hclgevf_query_vf_resource(hdev);
3361 ret = hclgevf_query_dev_specs(hdev);
3364 "failed to query dev specifications, ret = %d\n", ret);
3368 ret = hclgevf_init_msi(hdev);
3370 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
3374 hclgevf_state_init(hdev);
3375 hdev->reset_level = HNAE3_VF_FUNC_RESET;
3376 hdev->reset_type = HNAE3_NONE_RESET;
3378 ret = hclgevf_misc_irq_init(hdev);
3380 goto err_misc_irq_init;
3382 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3384 ret = hclgevf_configure(hdev);
3386 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
3390 ret = hclgevf_alloc_tqps(hdev);
3392 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
3396 ret = hclgevf_set_handle_info(hdev);
3400 ret = hclgevf_config_gro(hdev);
3404 /* Initialize RSS for this VF */
3405 ret = hclgevf_rss_init_cfg(hdev);
3407 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
3411 ret = hclgevf_rss_init_hw(hdev);
3413 dev_err(&hdev->pdev->dev,
3414 "failed(%d) to initialize RSS\n", ret);
3418 /* ensure vf tbl list as empty before init*/
3419 ret = hclgevf_clear_vport_list(hdev);
3422 "failed to clear tbl list configuration, ret = %d.\n",
3427 ret = hclgevf_init_vlan_config(hdev);
3429 dev_err(&hdev->pdev->dev,
3430 "failed(%d) to initialize VLAN config\n", ret);
3434 hclgevf_init_rxd_adv_layout(hdev);
3436 hdev->last_reset_time = jiffies;
3437 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",
3438 HCLGEVF_DRIVER_NAME);
3440 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
3445 hclgevf_misc_irq_uninit(hdev);
3447 hclgevf_state_uninit(hdev);
3448 hclgevf_uninit_msi(hdev);
3450 hclgevf_cmd_uninit(hdev);
3452 hclgevf_devlink_uninit(hdev);
3454 hclgevf_pci_uninit(hdev);
3455 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3459 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
3461 struct hclge_vf_to_pf_msg send_msg;
3463 hclgevf_state_uninit(hdev);
3464 hclgevf_uninit_rxd_adv_layout(hdev);
3466 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);
3467 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3469 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3470 hclgevf_misc_irq_uninit(hdev);
3471 hclgevf_uninit_msi(hdev);
3474 hclgevf_cmd_uninit(hdev);
3475 hclgevf_devlink_uninit(hdev);
3476 hclgevf_pci_uninit(hdev);
3477 hclgevf_uninit_mac_list(hdev);
3480 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
3482 struct pci_dev *pdev = ae_dev->pdev;
3485 ret = hclgevf_alloc_hdev(ae_dev);
3487 dev_err(&pdev->dev, "hclge device allocation failed\n");
3491 ret = hclgevf_init_hdev(ae_dev->priv);
3493 dev_err(&pdev->dev, "hclge device initialization failed\n");
3500 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
3502 struct hclgevf_dev *hdev = ae_dev->priv;
3504 hclgevf_uninit_hdev(hdev);
3505 ae_dev->priv = NULL;
3508 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
3510 struct hnae3_handle *nic = &hdev->nic;
3511 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
3513 return min_t(u32, hdev->rss_size_max,
3514 hdev->num_tqps / kinfo->tc_info.num_tc);
3518 * hclgevf_get_channels - Get the current channels enabled and max supported.
3519 * @handle: hardware information for network interface
3520 * @ch: ethtool channels structure
3522 * We don't support separate tx and rx queues as channels. The other count
3523 * represents how many queues are being used for control. max_combined counts
3524 * how many queue pairs we can support. They may not be mapped 1 to 1 with
3525 * q_vectors since we support a lot more queue pairs than q_vectors.
3527 static void hclgevf_get_channels(struct hnae3_handle *handle,
3528 struct ethtool_channels *ch)
3530 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3532 ch->max_combined = hclgevf_get_max_channels(hdev);
3533 ch->other_count = 0;
3535 ch->combined_count = handle->kinfo.rss_size;
3538 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
3539 u16 *alloc_tqps, u16 *max_rss_size)
3541 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3543 *alloc_tqps = hdev->num_tqps;
3544 *max_rss_size = hdev->rss_size_max;
3547 static void hclgevf_update_rss_size(struct hnae3_handle *handle,
3550 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3551 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3554 kinfo->req_rss_size = new_tqps_num;
3556 max_rss_size = min_t(u16, hdev->rss_size_max,
3557 hdev->num_tqps / kinfo->tc_info.num_tc);
3559 /* Use the user's configuration when it is not larger than
3560 * max_rss_size, otherwise, use the maximum specification value.
3562 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
3563 kinfo->req_rss_size <= max_rss_size)
3564 kinfo->rss_size = kinfo->req_rss_size;
3565 else if (kinfo->rss_size > max_rss_size ||
3566 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))
3567 kinfo->rss_size = max_rss_size;
3569 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size;
3572 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
3573 bool rxfh_configured)
3575 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3576 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3577 u16 cur_rss_size = kinfo->rss_size;
3578 u16 cur_tqps = kinfo->num_tqps;
3583 hclgevf_update_rss_size(handle, new_tqps_num);
3585 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size);
3589 /* RSS indirection table has been configured by user */
3590 if (rxfh_configured)
3593 /* Reinitializes the rss indirect table according to the new RSS size */
3594 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size,
3595 sizeof(u32), GFP_KERNEL);
3599 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
3600 rss_indir[i] = i % kinfo->rss_size;
3602 hdev->rss_cfg.rss_size = kinfo->rss_size;
3604 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);
3606 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
3613 dev_info(&hdev->pdev->dev,
3614 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
3615 cur_rss_size, kinfo->rss_size,
3616 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
3621 static int hclgevf_get_status(struct hnae3_handle *handle)
3623 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3625 return hdev->hw.mac.link;
3628 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
3629 u8 *auto_neg, u32 *speed,
3632 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3635 *speed = hdev->hw.mac.speed;
3637 *duplex = hdev->hw.mac.duplex;
3639 *auto_neg = AUTONEG_DISABLE;
3642 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
3645 hdev->hw.mac.speed = speed;
3646 hdev->hw.mac.duplex = duplex;
3649 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
3651 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3652 bool gro_en_old = hdev->gro_en;
3655 hdev->gro_en = enable;
3656 ret = hclgevf_config_gro(hdev);
3658 hdev->gro_en = gro_en_old;
3663 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
3666 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3669 *media_type = hdev->hw.mac.media_type;
3672 *module_type = hdev->hw.mac.module_type;
3675 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
3677 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3679 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
3682 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle)
3684 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3686 return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
3689 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
3691 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3693 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
3696 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
3698 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3700 return hdev->rst_stats.hw_rst_done_cnt;
3703 static void hclgevf_get_link_mode(struct hnae3_handle *handle,
3704 unsigned long *supported,
3705 unsigned long *advertising)
3707 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3709 *supported = hdev->hw.mac.supported;
3710 *advertising = hdev->hw.mac.advertising;
3713 #define MAX_SEPARATE_NUM 4
3714 #define SEPARATOR_VALUE 0xFDFCFBFA
3715 #define REG_NUM_PER_LINE 4
3716 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
3718 static int hclgevf_get_regs_len(struct hnae3_handle *handle)
3720 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
3721 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3723 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
3724 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
3725 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
3726 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
3728 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
3729 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
3732 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
3735 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3736 int i, j, reg_um, separator_num;
3739 *version = hdev->fw_version;
3741 /* fetching per-VF registers values from VF PCIe register space */
3742 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
3743 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3744 for (i = 0; i < reg_um; i++)
3745 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
3746 for (i = 0; i < separator_num; i++)
3747 *reg++ = SEPARATOR_VALUE;
3749 reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
3750 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3751 for (i = 0; i < reg_um; i++)
3752 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
3753 for (i = 0; i < separator_num; i++)
3754 *reg++ = SEPARATOR_VALUE;
3756 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
3757 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3758 for (j = 0; j < hdev->num_tqps; j++) {
3759 for (i = 0; i < reg_um; i++)
3760 *reg++ = hclgevf_read_dev(&hdev->hw,
3761 ring_reg_addr_list[i] +
3763 for (i = 0; i < separator_num; i++)
3764 *reg++ = SEPARATOR_VALUE;
3767 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
3768 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3769 for (j = 0; j < hdev->num_msi_used - 1; j++) {
3770 for (i = 0; i < reg_um; i++)
3771 *reg++ = hclgevf_read_dev(&hdev->hw,
3772 tqp_intr_reg_addr_list[i] +
3774 for (i = 0; i < separator_num; i++)
3775 *reg++ = SEPARATOR_VALUE;
3779 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
3780 u8 *port_base_vlan_info, u8 data_size)
3782 struct hnae3_handle *nic = &hdev->nic;
3783 struct hclge_vf_to_pf_msg send_msg;
3788 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
3789 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {
3790 dev_warn(&hdev->pdev->dev,
3791 "is resetting when updating port based vlan info\n");
3796 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
3802 /* send msg to PF and wait update port based vlan info */
3803 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
3804 HCLGE_MBX_PORT_BASE_VLAN_CFG);
3805 memcpy(send_msg.data, port_base_vlan_info, data_size);
3806 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3808 if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
3809 nic->port_base_vlan_state = state;
3811 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
3814 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
3818 static const struct hnae3_ae_ops hclgevf_ops = {
3819 .init_ae_dev = hclgevf_init_ae_dev,
3820 .uninit_ae_dev = hclgevf_uninit_ae_dev,
3821 .reset_prepare = hclgevf_reset_prepare_general,
3822 .reset_done = hclgevf_reset_done,
3823 .init_client_instance = hclgevf_init_client_instance,
3824 .uninit_client_instance = hclgevf_uninit_client_instance,
3825 .start = hclgevf_ae_start,
3826 .stop = hclgevf_ae_stop,
3827 .client_start = hclgevf_client_start,
3828 .client_stop = hclgevf_client_stop,
3829 .map_ring_to_vector = hclgevf_map_ring_to_vector,
3830 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
3831 .get_vector = hclgevf_get_vector,
3832 .put_vector = hclgevf_put_vector,
3833 .reset_queue = hclgevf_reset_tqp,
3834 .get_mac_addr = hclgevf_get_mac_addr,
3835 .set_mac_addr = hclgevf_set_mac_addr,
3836 .add_uc_addr = hclgevf_add_uc_addr,
3837 .rm_uc_addr = hclgevf_rm_uc_addr,
3838 .add_mc_addr = hclgevf_add_mc_addr,
3839 .rm_mc_addr = hclgevf_rm_mc_addr,
3840 .get_stats = hclgevf_get_stats,
3841 .update_stats = hclgevf_update_stats,
3842 .get_strings = hclgevf_get_strings,
3843 .get_sset_count = hclgevf_get_sset_count,
3844 .get_rss_key_size = hclgevf_get_rss_key_size,
3845 .get_rss = hclgevf_get_rss,
3846 .set_rss = hclgevf_set_rss,
3847 .get_rss_tuple = hclgevf_get_rss_tuple,
3848 .set_rss_tuple = hclgevf_set_rss_tuple,
3849 .get_tc_size = hclgevf_get_tc_size,
3850 .get_fw_version = hclgevf_get_fw_version,
3851 .set_vlan_filter = hclgevf_set_vlan_filter,
3852 .enable_vlan_filter = hclgevf_enable_vlan_filter,
3853 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
3854 .reset_event = hclgevf_reset_event,
3855 .set_default_reset_request = hclgevf_set_def_reset_request,
3856 .set_channels = hclgevf_set_channels,
3857 .get_channels = hclgevf_get_channels,
3858 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
3859 .get_regs_len = hclgevf_get_regs_len,
3860 .get_regs = hclgevf_get_regs,
3861 .get_status = hclgevf_get_status,
3862 .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
3863 .get_media_type = hclgevf_get_media_type,
3864 .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
3865 .ae_dev_resetting = hclgevf_ae_dev_resetting,
3866 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
3867 .set_gro_en = hclgevf_gro_en,
3868 .set_mtu = hclgevf_set_mtu,
3869 .get_global_queue_id = hclgevf_get_qid_global,
3870 .set_timer_task = hclgevf_set_timer_task,
3871 .get_link_mode = hclgevf_get_link_mode,
3872 .set_promisc_mode = hclgevf_set_promisc_mode,
3873 .request_update_promisc_mode = hclgevf_request_update_promisc_mode,
3874 .get_cmdq_stat = hclgevf_get_cmdq_stat,
3877 static struct hnae3_ae_algo ae_algovf = {
3878 .ops = &hclgevf_ops,
3879 .pdev_id_table = ae_algovf_pci_tbl,
3882 static int hclgevf_init(void)
3884 pr_info("%s is initializing\n", HCLGEVF_NAME);
3886 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME);
3888 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);
3892 hnae3_register_ae_algo(&ae_algovf);
3897 static void hclgevf_exit(void)
3899 hnae3_unregister_ae_algo(&ae_algovf);
3900 destroy_workqueue(hclgevf_wq);
3902 module_init(hclgevf_init);
3903 module_exit(hclgevf_exit);
3905 MODULE_LICENSE("GPL");
3906 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3907 MODULE_DESCRIPTION("HCLGEVF Driver");
3908 MODULE_VERSION(HCLGEVF_MOD_VERSION);