1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
4 #ifndef __HCLGEVF_CMD_H
5 #define __HCLGEVF_CMD_H
7 #include <linux/types.h>
10 #define HCLGEVF_CMDQ_TX_TIMEOUT 30000
11 #define HCLGEVF_CMDQ_CLEAR_WAIT_TIME 200
12 #define HCLGEVF_CMDQ_RX_INVLD_B 0
13 #define HCLGEVF_CMDQ_RX_OUTVLD_B 1
26 struct hclgevf_desc_cb {
32 struct hclgevf_cmq_ring {
33 dma_addr_t desc_dma_addr;
34 struct hclgevf_desc *desc;
35 struct hclgevf_desc_cb *desc_cb;
36 struct hclgevf_dev *dev;
45 spinlock_t lock; /* Command queue lock */
48 enum hclgevf_cmd_return_status {
49 HCLGEVF_CMD_EXEC_SUCCESS = 0,
50 HCLGEVF_CMD_NO_AUTH = 1,
51 HCLGEVF_CMD_NOT_SUPPORTED = 2,
52 HCLGEVF_CMD_QUEUE_FULL = 3,
53 HCLGEVF_CMD_NEXT_ERR = 4,
54 HCLGEVF_CMD_UNEXE_ERR = 5,
55 HCLGEVF_CMD_PARA_ERR = 6,
56 HCLGEVF_CMD_RESULT_ERR = 7,
57 HCLGEVF_CMD_TIMEOUT = 8,
58 HCLGEVF_CMD_HILINK_ERR = 9,
59 HCLGEVF_CMD_QUEUE_ILLEGAL = 10,
60 HCLGEVF_CMD_INVALID = 11,
63 enum hclgevf_cmd_status {
64 HCLGEVF_STATUS_SUCCESS = 0,
65 HCLGEVF_ERR_CSQ_FULL = -1,
66 HCLGEVF_ERR_CSQ_TIMEOUT = -2,
67 HCLGEVF_ERR_CSQ_ERROR = -3
71 struct hclgevf_cmq_ring csq;
72 struct hclgevf_cmq_ring crq;
73 u16 tx_timeout; /* Tx timeout */
74 enum hclgevf_cmd_status last_status;
77 #define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT 0
78 #define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT 1
79 #define HCLGEVF_CMD_FLAG_NEXT_SHIFT 2
80 #define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT 3
81 #define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT 4
82 #define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT 5
84 #define HCLGEVF_CMD_FLAG_IN BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT)
85 #define HCLGEVF_CMD_FLAG_OUT BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT)
86 #define HCLGEVF_CMD_FLAG_NEXT BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT)
87 #define HCLGEVF_CMD_FLAG_WR BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT)
88 #define HCLGEVF_CMD_FLAG_NO_INTR BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT)
89 #define HCLGEVF_CMD_FLAG_ERR_INTR BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT)
91 enum hclgevf_opcode_type {
93 HCLGEVF_OPC_QUERY_FW_VER = 0x0001,
94 HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024,
95 HCLGEVF_OPC_QUERY_DEV_SPECS = 0x0050,
98 HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03,
99 HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13,
100 HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
102 HCLGEVF_OPC_GRO_GENERIC_CONFIG = 0x0C10,
104 HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01,
105 HCLGEVF_OPC_RSS_INPUT_TUPLE = 0x0D02,
106 HCLGEVF_OPC_RSS_INDIR_TABLE = 0x0D07,
107 HCLGEVF_OPC_RSS_TC_MODE = 0x0D08,
109 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,
112 #define HCLGEVF_TQP_REG_OFFSET 0x80000
113 #define HCLGEVF_TQP_REG_SIZE 0x200
115 #define HCLGEVF_TQP_MAX_SIZE_DEV_V2 1024
116 #define HCLGEVF_TQP_EXT_REG_OFFSET 0x100
118 struct hclgevf_tqp_map {
119 __le16 tqp_id; /* Absolute tqp id for in this pf */
120 u8 tqp_vf; /* VF id */
121 #define HCLGEVF_TQP_MAP_TYPE_PF 0
122 #define HCLGEVF_TQP_MAP_TYPE_VF 1
123 #define HCLGEVF_TQP_MAP_TYPE_B 0
124 #define HCLGEVF_TQP_MAP_EN_B 1
125 u8 tqp_flag; /* Indicate it's pf or vf tqp */
126 __le16 tqp_vid; /* Virtual id in this pf/vf */
130 #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10
132 enum hclgevf_int_type {
138 struct hclgevf_ctrl_vector_chain {
141 #define HCLGEVF_INT_TYPE_S 0
142 #define HCLGEVF_INT_TYPE_M 0x3
143 #define HCLGEVF_TQP_ID_S 2
144 #define HCLGEVF_TQP_ID_M (0x3fff << HCLGEVF_TQP_ID_S)
145 __le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD];
150 enum HCLGEVF_CAP_BITS {
151 HCLGEVF_CAP_UDP_GSO_B,
153 HCLGEVF_CAP_FD_FORWARD_TC_B,
155 HCLGEVF_CAP_INT_QL_B,
156 HCLGEVF_CAP_HW_TX_CSUM_B,
157 HCLGEVF_CAP_TX_PUSH_B,
158 HCLGEVF_CAP_PHY_IMP_B,
159 HCLGEVF_CAP_TQP_TXRX_INDEP_B,
160 HCLGEVF_CAP_HW_PAD_B,
162 HCLGEVF_CAP_UDP_TUNNEL_CSUM_B,
163 HCLGEVF_CAP_RXD_ADV_LAYOUT_B = 15,
166 enum HCLGEVF_API_CAP_BITS {
167 HCLGEVF_API_CAP_FLEX_RSS_TBL_B,
170 #define HCLGEVF_QUERY_CAP_LENGTH 3
171 struct hclgevf_query_version_cmd {
175 __le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
178 #define HCLGEVF_MSIX_OFT_ROCEE_S 0
179 #define HCLGEVF_MSIX_OFT_ROCEE_M (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
180 #define HCLGEVF_VEC_NUM_S 0
181 #define HCLGEVF_VEC_NUM_M (0xff << HCLGEVF_VEC_NUM_S)
182 struct hclgevf_query_res_cmd {
185 __le16 msixcap_localid_ba_nic;
186 __le16 msixcap_localid_ba_rocee;
187 __le16 vf_intr_vector_number;
191 #define HCLGEVF_GRO_EN_B 0
192 struct hclgevf_cfg_gro_status_cmd {
197 #define HCLGEVF_RSS_DEFAULT_OUTPORT_B 4
198 #define HCLGEVF_RSS_HASH_KEY_OFFSET_B 4
199 #define HCLGEVF_RSS_HASH_KEY_NUM 16
200 struct hclgevf_rss_config_cmd {
203 u8 hash_key[HCLGEVF_RSS_HASH_KEY_NUM];
206 struct hclgevf_rss_input_tuple_cmd {
218 #define HCLGEVF_RSS_CFG_TBL_SIZE 16
220 struct hclgevf_rss_indirection_table_cmd {
221 __le16 start_table_index;
222 __le16 rss_set_bitmap;
224 u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE];
227 #define HCLGEVF_RSS_TC_OFFSET_S 0
228 #define HCLGEVF_RSS_TC_OFFSET_M GENMASK(10, 0)
229 #define HCLGEVF_RSS_TC_SIZE_MSB_B 11
230 #define HCLGEVF_RSS_TC_SIZE_S 12
231 #define HCLGEVF_RSS_TC_SIZE_M GENMASK(14, 12)
232 #define HCLGEVF_RSS_TC_VALID_B 15
233 #define HCLGEVF_MAX_TC_NUM 8
234 #define HCLGEVF_RSS_TC_SIZE_MSB_OFFSET 3
236 struct hclgevf_rss_tc_mode_cmd {
237 __le16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
241 #define HCLGEVF_LINK_STS_B 0
242 #define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B)
243 struct hclgevf_link_status_cmd {
248 #define HCLGEVF_RING_ID_MASK 0x3ff
249 #define HCLGEVF_TQP_ENABLE_B 0
251 struct hclgevf_cfg_com_tqp_queue_cmd {
258 struct hclgevf_cfg_tx_queue_pointer_cmd {
267 #define HCLGEVF_TYPE_CRQ 0
268 #define HCLGEVF_TYPE_CSQ 1
269 #define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000
270 #define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004
271 #define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008
272 #define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010
273 #define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014
274 #define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018
275 #define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701c
276 #define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020
277 #define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024
278 #define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028
280 /* this bit indicates that the driver is ready for hardware reset */
281 #define HCLGEVF_NIC_SW_RST_RDY_B 16
282 #define HCLGEVF_NIC_SW_RST_RDY BIT(HCLGEVF_NIC_SW_RST_RDY_B)
284 #define HCLGEVF_NIC_CMQ_DESC_NUM 1024
285 #define HCLGEVF_NIC_CMQ_DESC_NUM_S 3
287 #define HCLGEVF_QUERY_DEV_SPECS_BD_NUM 4
289 struct hclgevf_dev_specs_0_cmd {
291 __le32 mac_entry_num;
292 __le32 mng_entry_num;
293 __le16 rss_ind_tbl_size;
296 u8 max_non_tso_bd_num;
300 #define HCLGEVF_DEF_MAX_INT_GL 0x1FE0U
302 struct hclgevf_dev_specs_1_cmd {
309 static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
311 writel(value, base + reg);
314 static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg)
316 u8 __iomem *reg_addr = READ_ONCE(base);
318 return readl(reg_addr + reg);
321 #define hclgevf_write_dev(a, reg, value) \
322 hclgevf_write_reg((a)->io_base, reg, value)
323 #define hclgevf_read_dev(a, reg) \
324 hclgevf_read_reg((a)->io_base, reg)
326 #define HCLGEVF_SEND_SYNC(flag) \
327 ((flag) & HCLGEVF_CMD_FLAG_NO_INTR)
329 int hclgevf_cmd_init(struct hclgevf_dev *hdev);
330 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
331 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
333 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
334 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
335 enum hclgevf_opcode_type opcode,