1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
7 #include <linux/types.h>
9 #include <linux/if_vlan.h>
11 #include "hclge_cmd.h"
14 #define HCLGE_MOD_VERSION "1.0"
15 #define HCLGE_DRIVER_NAME "hclge"
17 #define HCLGE_MAX_PF_NUM 8
19 #define HCLGE_INVALID_VPORT 0xffff
21 #define HCLGE_PF_CFG_BLOCK_SIZE 32
22 #define HCLGE_PF_CFG_DESC_NUM \
23 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
25 #define HCLGE_VECTOR_REG_BASE 0x20000
26 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
28 #define HCLGE_VECTOR_REG_OFFSET 0x4
29 #define HCLGE_VECTOR_VF_OFFSET 0x100000
31 #define HCLGE_RSS_IND_TBL_SIZE 512
32 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
33 #define HCLGE_RSS_KEY_SIZE 40
34 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
35 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1
36 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
37 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0)
38 #define HCLGE_RSS_CFG_TBL_NUM \
39 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
41 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
42 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
43 #define HCLGE_D_PORT_BIT BIT(0)
44 #define HCLGE_S_PORT_BIT BIT(1)
45 #define HCLGE_D_IP_BIT BIT(2)
46 #define HCLGE_S_IP_BIT BIT(3)
47 #define HCLGE_V_TAG_BIT BIT(4)
49 #define HCLGE_RSS_TC_SIZE_0 1
50 #define HCLGE_RSS_TC_SIZE_1 2
51 #define HCLGE_RSS_TC_SIZE_2 4
52 #define HCLGE_RSS_TC_SIZE_3 8
53 #define HCLGE_RSS_TC_SIZE_4 16
54 #define HCLGE_RSS_TC_SIZE_5 32
55 #define HCLGE_RSS_TC_SIZE_6 64
56 #define HCLGE_RSS_TC_SIZE_7 128
58 #define HCLGE_UMV_TBL_SIZE 3072
59 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
60 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
62 #define HCLGE_TQP_RESET_TRY_TIMES 10
64 #define HCLGE_PHY_PAGE_MDIX 0
65 #define HCLGE_PHY_PAGE_COPPER 0
67 /* Page Selection Reg. */
68 #define HCLGE_PHY_PAGE_REG 22
70 /* Copper Specific Control Register */
71 #define HCLGE_PHY_CSC_REG 16
73 /* Copper Specific Status Register */
74 #define HCLGE_PHY_CSS_REG 17
76 #define HCLGE_PHY_MDIX_CTRL_S 5
77 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
79 #define HCLGE_PHY_MDIX_STATUS_B 6
80 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
82 /* Factor used to calculate offset and bitmap of VF num */
83 #define HCLGE_VF_NUM_PER_CMD 64
84 #define HCLGE_VF_NUM_PER_BYTE 8
86 enum HLCGE_PORT_TYPE {
91 #define HCLGE_PF_ID_S 0
92 #define HCLGE_PF_ID_M GENMASK(2, 0)
93 #define HCLGE_VF_ID_S 3
94 #define HCLGE_VF_ID_M GENMASK(10, 3)
95 #define HCLGE_PORT_TYPE_B 11
96 #define HCLGE_NETWORK_PORT_ID_S 0
97 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
99 /* Reset related Registers */
100 #define HCLGE_MISC_RESET_STS_REG 0x20700
101 #define HCLGE_MISC_VECTOR_INT_STS 0x20800
102 #define HCLGE_GLOBAL_RESET_REG 0x20A00
103 #define HCLGE_GLOBAL_RESET_BIT 0
104 #define HCLGE_CORE_RESET_BIT 1
105 #define HCLGE_FUN_RST_ING 0x20C00
106 #define HCLGE_FUN_RST_ING_B 0
108 /* Vector0 register bits define */
109 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
110 #define HCLGE_VECTOR0_CORERESET_INT_B 6
111 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
113 /* Vector0 interrupt CMDQ event source register(RW) */
114 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
115 /* CMDQ register bits for RX event(=MBX event) */
116 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
118 #define HCLGE_MAC_DEFAULT_FRAME \
119 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN + ETH_DATA_LEN)
120 #define HCLGE_MAC_MIN_FRAME 64
121 #define HCLGE_MAC_MAX_FRAME 9728
123 #define HCLGE_SUPPORT_1G_BIT BIT(0)
124 #define HCLGE_SUPPORT_10G_BIT BIT(1)
125 #define HCLGE_SUPPORT_25G_BIT BIT(2)
126 #define HCLGE_SUPPORT_50G_BIT BIT(3)
127 #define HCLGE_SUPPORT_100G_BIT BIT(4)
129 enum HCLGE_DEV_STATE {
130 HCLGE_STATE_REINITING,
132 HCLGE_STATE_DISABLED,
133 HCLGE_STATE_REMOVING,
134 HCLGE_STATE_SERVICE_INITED,
135 HCLGE_STATE_SERVICE_SCHED,
136 HCLGE_STATE_RST_SERVICE_SCHED,
137 HCLGE_STATE_RST_HANDLING,
138 HCLGE_STATE_MBX_SERVICE_SCHED,
139 HCLGE_STATE_MBX_HANDLING,
140 HCLGE_STATE_STATISTICS_UPDATING,
141 HCLGE_STATE_CMD_DISABLE,
145 enum hclge_evt_cause {
146 HCLGE_VECTOR0_EVENT_RST,
147 HCLGE_VECTOR0_EVENT_MBX,
148 HCLGE_VECTOR0_EVENT_OTHER,
151 #define HCLGE_MPF_ENBALE 1
153 enum HCLGE_MAC_SPEED {
154 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
155 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
156 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
157 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
158 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
159 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
160 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
161 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */
164 enum HCLGE_MAC_DUPLEX {
173 u8 mac_addr[ETH_ALEN];
177 int link; /* store the link status of mac & phy (if phy exit)*/
178 struct phy_device *phydev;
179 struct mii_bus *mdio_bus;
180 phy_interface_t phy_if;
181 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
182 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
186 void __iomem *io_base;
187 struct hclge_mac mac;
189 struct hclge_cmq cmq;
193 struct hlcge_tqp_stats {
194 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
195 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
196 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
197 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
201 /* copy of device pointer from pci_dev,
202 * used when perform DMA mapping
205 struct hnae3_queue q;
206 struct hlcge_tqp_stats tqp_stats;
207 u16 index; /* Global index in a NIC controller */
221 #define HCLGE_PG_NUM 4
222 #define HCLGE_SCH_MODE_SP 0
223 #define HCLGE_SCH_MODE_DWRR 1
224 struct hclge_pg_info {
226 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
229 u8 tc_dwrr[HNAE3_MAX_TC];
232 struct hclge_tc_info {
234 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
247 u8 mac_addr[ETH_ALEN];
254 struct hclge_tm_info {
256 u8 num_pg; /* It must be 1 if vNET-Base schd */
257 u8 pg_dwrr[HCLGE_PG_NUM];
258 u8 prio_tc[HNAE3_MAX_USER_PRIO];
259 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
260 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
261 enum hclge_fc_mode fc_mode;
262 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
265 struct hclge_comm_stats_str {
266 char desc[ETH_GSTRING_LEN];
267 unsigned long offset;
270 /* mac stats ,opcode id: 0x0032 */
271 struct hclge_mac_stats {
272 u64 mac_tx_mac_pause_num;
273 u64 mac_rx_mac_pause_num;
274 u64 mac_tx_pfc_pri0_pkt_num;
275 u64 mac_tx_pfc_pri1_pkt_num;
276 u64 mac_tx_pfc_pri2_pkt_num;
277 u64 mac_tx_pfc_pri3_pkt_num;
278 u64 mac_tx_pfc_pri4_pkt_num;
279 u64 mac_tx_pfc_pri5_pkt_num;
280 u64 mac_tx_pfc_pri6_pkt_num;
281 u64 mac_tx_pfc_pri7_pkt_num;
282 u64 mac_rx_pfc_pri0_pkt_num;
283 u64 mac_rx_pfc_pri1_pkt_num;
284 u64 mac_rx_pfc_pri2_pkt_num;
285 u64 mac_rx_pfc_pri3_pkt_num;
286 u64 mac_rx_pfc_pri4_pkt_num;
287 u64 mac_rx_pfc_pri5_pkt_num;
288 u64 mac_rx_pfc_pri6_pkt_num;
289 u64 mac_rx_pfc_pri7_pkt_num;
290 u64 mac_tx_total_pkt_num;
291 u64 mac_tx_total_oct_num;
292 u64 mac_tx_good_pkt_num;
293 u64 mac_tx_bad_pkt_num;
294 u64 mac_tx_good_oct_num;
295 u64 mac_tx_bad_oct_num;
296 u64 mac_tx_uni_pkt_num;
297 u64 mac_tx_multi_pkt_num;
298 u64 mac_tx_broad_pkt_num;
299 u64 mac_tx_undersize_pkt_num;
300 u64 mac_tx_oversize_pkt_num;
301 u64 mac_tx_64_oct_pkt_num;
302 u64 mac_tx_65_127_oct_pkt_num;
303 u64 mac_tx_128_255_oct_pkt_num;
304 u64 mac_tx_256_511_oct_pkt_num;
305 u64 mac_tx_512_1023_oct_pkt_num;
306 u64 mac_tx_1024_1518_oct_pkt_num;
307 u64 mac_tx_1519_2047_oct_pkt_num;
308 u64 mac_tx_2048_4095_oct_pkt_num;
309 u64 mac_tx_4096_8191_oct_pkt_num;
311 u64 mac_tx_8192_9216_oct_pkt_num;
312 u64 mac_tx_9217_12287_oct_pkt_num;
313 u64 mac_tx_12288_16383_oct_pkt_num;
314 u64 mac_tx_1519_max_good_oct_pkt_num;
315 u64 mac_tx_1519_max_bad_oct_pkt_num;
317 u64 mac_rx_total_pkt_num;
318 u64 mac_rx_total_oct_num;
319 u64 mac_rx_good_pkt_num;
320 u64 mac_rx_bad_pkt_num;
321 u64 mac_rx_good_oct_num;
322 u64 mac_rx_bad_oct_num;
323 u64 mac_rx_uni_pkt_num;
324 u64 mac_rx_multi_pkt_num;
325 u64 mac_rx_broad_pkt_num;
326 u64 mac_rx_undersize_pkt_num;
327 u64 mac_rx_oversize_pkt_num;
328 u64 mac_rx_64_oct_pkt_num;
329 u64 mac_rx_65_127_oct_pkt_num;
330 u64 mac_rx_128_255_oct_pkt_num;
331 u64 mac_rx_256_511_oct_pkt_num;
332 u64 mac_rx_512_1023_oct_pkt_num;
333 u64 mac_rx_1024_1518_oct_pkt_num;
334 u64 mac_rx_1519_2047_oct_pkt_num;
335 u64 mac_rx_2048_4095_oct_pkt_num;
336 u64 mac_rx_4096_8191_oct_pkt_num;
338 u64 mac_rx_8192_9216_oct_pkt_num;
339 u64 mac_rx_9217_12287_oct_pkt_num;
340 u64 mac_rx_12288_16383_oct_pkt_num;
341 u64 mac_rx_1519_max_good_oct_pkt_num;
342 u64 mac_rx_1519_max_bad_oct_pkt_num;
344 u64 mac_tx_fragment_pkt_num;
345 u64 mac_tx_undermin_pkt_num;
346 u64 mac_tx_jabber_pkt_num;
347 u64 mac_tx_err_all_pkt_num;
348 u64 mac_tx_from_app_good_pkt_num;
349 u64 mac_tx_from_app_bad_pkt_num;
350 u64 mac_rx_fragment_pkt_num;
351 u64 mac_rx_undermin_pkt_num;
352 u64 mac_rx_jabber_pkt_num;
353 u64 mac_rx_fcs_err_pkt_num;
354 u64 mac_rx_send_app_good_pkt_num;
355 u64 mac_rx_send_app_bad_pkt_num;
358 #define HCLGE_STATS_TIMER_INTERVAL (60 * 5)
359 struct hclge_hw_stats {
360 struct hclge_mac_stats mac_stats;
364 struct hclge_vlan_type_cfg {
365 u16 rx_ot_fst_vlan_type;
366 u16 rx_ot_sec_vlan_type;
367 u16 rx_in_fst_vlan_type;
368 u16 rx_in_sec_vlan_type;
374 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
375 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
376 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
377 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
380 enum HCLGE_FD_KEY_TYPE {
381 HCLGE_FD_KEY_BASE_ON_PTYPE,
382 HCLGE_FD_KEY_BASE_ON_TUPLE,
385 enum HCLGE_FD_STAGE {
390 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet
391 * INNER_XXX indicate tuples in tunneled header of tunnel packet or
392 * tuples of non-tunnel packet
394 enum HCLGE_FD_TUPLE {
428 enum HCLGE_FD_META_DATA {
445 static const struct key_info meta_data_key_info[] = {
446 { PACKET_TYPE_ID, 6},
456 static const struct key_info tuple_key_info[] = {
457 { OUTER_DST_MAC, 48},
458 { OUTER_SRC_MAC, 48},
459 { OUTER_VLAN_TAG_FST, 16},
460 { OUTER_VLAN_TAG_SEC, 16},
461 { OUTER_ETH_TYPE, 16},
464 { OUTER_IP_PROTO, 8},
468 { OUTER_SRC_PORT, 16},
469 { OUTER_DST_PORT, 16},
471 { OUTER_TUN_VNI, 24},
472 { OUTER_TUN_FLOW_ID, 8},
473 { INNER_DST_MAC, 48},
474 { INNER_SRC_MAC, 48},
475 { INNER_VLAN_TAG_FST, 16},
476 { INNER_VLAN_TAG_SEC, 16},
477 { INNER_ETH_TYPE, 16},
480 { INNER_IP_PROTO, 8},
484 { INNER_SRC_PORT, 16},
485 { INNER_DST_PORT, 16},
489 #define MAX_KEY_LENGTH 400
490 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
491 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
492 #define MAX_META_DATA_LENGTH 32
494 enum HCLGE_FD_PACKET_TYPE {
499 enum HCLGE_FD_ACTION {
500 HCLGE_FD_ACTION_ACCEPT_PACKET,
501 HCLGE_FD_ACTION_DROP_PACKET,
504 struct hclge_fd_key_cfg {
506 u8 inner_sipv6_word_en;
507 u8 inner_dipv6_word_en;
508 u8 outer_sipv6_word_en;
509 u8 outer_dipv6_word_en;
511 u32 meta_data_active;
514 struct hclge_fd_cfg {
519 u32 rule_num[2]; /* rule entry number */
520 u16 cnt_num[2]; /* rule hit counter number */
521 struct hclge_fd_key_cfg key_cfg[2];
524 struct hclge_fd_rule_tuples {
537 struct hclge_fd_rule {
538 struct hlist_node rule_node;
539 struct hclge_fd_rule_tuples tuples;
540 struct hclge_fd_rule_tuples tuples_mask;
549 struct hclge_fd_ad_data {
552 u8 forward_to_direct_queue;
557 u8 write_rule_id_to_bd;
562 /* For each bit of TCAM entry, it uses a pair of 'x' and
563 * 'y' to indicate which value to match, like below:
564 * ----------------------------------
565 * | bit x | bit y | search value |
566 * ----------------------------------
567 * | 0 | 0 | always hit |
568 * ----------------------------------
569 * | 1 | 0 | match '0' |
570 * ----------------------------------
571 * | 0 | 1 | match '1' |
572 * ----------------------------------
573 * | 1 | 1 | invalid |
574 * ----------------------------------
575 * Then for input key(k) and mask(v), we can calculate the value by
580 #define calc_x(x, k, v) ((x) = (~(k) & (v)))
581 #define calc_y(y, k, v) \
583 const typeof(k) _k_ = (k); \
584 const typeof(v) _v_ = (v); \
585 (y) = (_k_ ^ ~_v_) & (_k_); \
588 #define HCLGE_VPORT_NUM 256
590 struct pci_dev *pdev;
591 struct hnae3_ae_dev *ae_dev;
593 struct hclge_misc_vector misc_vector;
594 struct hclge_hw_stats hw_stats;
597 enum hnae3_reset_type reset_type;
598 unsigned long reset_request; /* reset has been requested */
599 unsigned long reset_pending; /* client rst is pending to be served */
601 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
602 u16 num_tqps; /* Num task queue pairs of this PF */
603 u16 num_req_vfs; /* Num VFs requested for this PF */
605 u16 base_tqp_pid; /* Base task tqp physical id of this PF */
606 u16 alloc_rss_size; /* Allocated RSS task queue */
607 u16 rss_size_max; /* HW defined max RSS task queue */
609 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
610 u16 num_alloc_vport; /* Num vports this driver supports */
616 enum hclge_fc_mode fc_mode_last_time;
618 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
619 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
626 struct hclge_tm_info tm_info;
631 u16 roce_base_msix_offset;
635 u16 num_roce_msi; /* Num of roce vectors for this PF */
636 int roce_base_vector;
638 u16 pending_udp_bitmap;
643 u16 adminq_work_limit; /* Num of admin receive queue desc to process */
644 unsigned long service_timer_period;
645 unsigned long service_timer_previous;
646 struct timer_list service_timer;
647 struct work_struct service_task;
648 struct work_struct rst_service_task;
649 struct work_struct mbx_service_task;
652 int num_alloc_vfs; /* Actual number of VFs allocated */
654 struct hclge_tqp *htqp;
655 struct hclge_vport *vport;
657 struct dentry *hclge_dbgfs;
659 struct hnae3_client *nic_client;
660 struct hnae3_client *roce_client;
662 #define HCLGE_FLAG_MAIN BIT(0)
663 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)
664 #define HCLGE_FLAG_DCB_ENABLE BIT(2)
665 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
668 u32 pkt_buf_size; /* Total pf buf size for tx/rx */
669 u32 mps; /* Max packet size */
671 struct hclge_vlan_type_cfg vlan_type_cfg;
673 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
675 struct hclge_fd_cfg fd_cfg;
676 struct hlist_head fd_rule_list;
677 u16 hclge_fd_rule_num;
680 /* max available unicast mac vlan space */
682 /* private unicast mac vlan space, it's same for PF and its VFs */
684 /* unicast mac vlan space shared by PF and its VFs */
686 struct mutex umv_mutex; /* protect share_umv_size */
689 /* VPort level vlan tag configuration for TX direction */
690 struct hclge_tx_vtag_cfg {
691 bool accept_tag1; /* Whether accept tag1 packet from host */
692 bool accept_untag1; /* Whether accept untag1 packet from host */
695 bool insert_tag1_en; /* Whether insert inner vlan tag */
696 bool insert_tag2_en; /* Whether insert outer vlan tag */
697 u16 default_tag1; /* The default inner vlan tag to insert */
698 u16 default_tag2; /* The default outer vlan tag to insert */
701 /* VPort level vlan tag configuration for RX direction */
702 struct hclge_rx_vtag_cfg {
703 bool strip_tag1_en; /* Whether strip inner vlan tag */
704 bool strip_tag2_en; /* Whether strip outer vlan tag */
705 bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */
706 bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */
709 struct hclge_rss_tuple_cfg {
721 u16 alloc_tqps; /* Allocated Tx/Rx queues */
723 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
724 /* User configured lookup table entries */
725 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
726 int rss_algo; /* User configured hash algorithm */
727 /* User configured rss tuple sets */
728 struct hclge_rss_tuple_cfg rss_tuple_sets;
733 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
736 struct hclge_tx_vtag_cfg txvlan_cfg;
737 struct hclge_rx_vtag_cfg rxvlan_cfg;
742 struct hclge_dev *back; /* Back reference to associated dev */
743 struct hnae3_handle nic;
744 struct hnae3_handle roce;
747 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
748 bool en_mc, bool en_bc, int vport_id);
750 int hclge_add_uc_addr_common(struct hclge_vport *vport,
751 const unsigned char *addr);
752 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
753 const unsigned char *addr);
754 int hclge_add_mc_addr_common(struct hclge_vport *vport,
755 const unsigned char *addr);
756 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
757 const unsigned char *addr);
759 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
760 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
761 int vector_id, bool en,
762 struct hnae3_ring_chain_node *ring_chain);
764 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
766 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
771 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
772 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
773 u16 vlan_id, bool is_kill);
774 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
776 int hclge_buffer_alloc(struct hclge_dev *hdev);
777 int hclge_rss_init_hw(struct hclge_dev *hdev);
778 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
780 void hclge_mbx_handler(struct hclge_dev *hdev);
781 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
782 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
783 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
784 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);