1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
7 #include <linux/types.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kfifo.h>
11 #include <net/devlink.h>
13 #include "hclge_cmd.h"
14 #include "hclge_ptp.h"
17 #define HCLGE_MOD_VERSION "1.0"
18 #define HCLGE_DRIVER_NAME "hclge"
20 #define HCLGE_MAX_PF_NUM 8
22 #define HCLGE_VF_VPORT_START_NUM 1
24 #define HCLGE_RD_FIRST_STATS_NUM 2
25 #define HCLGE_RD_OTHER_STATS_NUM 4
27 #define HCLGE_INVALID_VPORT 0xffff
29 #define HCLGE_PF_CFG_BLOCK_SIZE 32
30 #define HCLGE_PF_CFG_DESC_NUM \
31 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
33 #define HCLGE_VECTOR_REG_BASE 0x20000
34 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000
35 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
37 #define HCLGE_VECTOR_REG_OFFSET 0x4
38 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000
39 #define HCLGE_VECTOR_VF_OFFSET 0x100000
41 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
42 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
43 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
44 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
45 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
46 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
47 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701C
48 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
49 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
50 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
52 #define HCLGE_CMDQ_INTR_STS_REG 0x27104
53 #define HCLGE_CMDQ_INTR_EN_REG 0x27108
54 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
56 /* bar registers for common func */
57 #define HCLGE_GRO_EN_REG 0x28000
58 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008
60 /* bar registers for rcb */
61 #define HCLGE_RING_RX_ADDR_L_REG 0x80000
62 #define HCLGE_RING_RX_ADDR_H_REG 0x80004
63 #define HCLGE_RING_RX_BD_NUM_REG 0x80008
64 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
65 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014
66 #define HCLGE_RING_RX_TAIL_REG 0x80018
67 #define HCLGE_RING_RX_HEAD_REG 0x8001C
68 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020
69 #define HCLGE_RING_RX_OFFSET_REG 0x80024
70 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
71 #define HCLGE_RING_RX_STASH_REG 0x80030
72 #define HCLGE_RING_RX_BD_ERR_REG 0x80034
73 #define HCLGE_RING_TX_ADDR_L_REG 0x80040
74 #define HCLGE_RING_TX_ADDR_H_REG 0x80044
75 #define HCLGE_RING_TX_BD_NUM_REG 0x80048
76 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C
77 #define HCLGE_RING_TX_TC_REG 0x80050
78 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054
79 #define HCLGE_RING_TX_TAIL_REG 0x80058
80 #define HCLGE_RING_TX_HEAD_REG 0x8005C
81 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060
82 #define HCLGE_RING_TX_OFFSET_REG 0x80064
83 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068
84 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
85 #define HCLGE_RING_TX_BD_ERR_REG 0x80074
86 #define HCLGE_RING_EN_REG 0x80090
88 /* bar registers for tqp interrupt */
89 #define HCLGE_TQP_INTR_CTRL_REG 0x20000
90 #define HCLGE_TQP_INTR_GL0_REG 0x20100
91 #define HCLGE_TQP_INTR_GL1_REG 0x20200
92 #define HCLGE_TQP_INTR_GL2_REG 0x20300
93 #define HCLGE_TQP_INTR_RL_REG 0x20900
95 #define HCLGE_RSS_IND_TBL_SIZE 512
96 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
97 #define HCLGE_RSS_KEY_SIZE 40
98 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
99 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1
100 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
101 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0)
103 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
104 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
105 #define HCLGE_D_PORT_BIT BIT(0)
106 #define HCLGE_S_PORT_BIT BIT(1)
107 #define HCLGE_D_IP_BIT BIT(2)
108 #define HCLGE_S_IP_BIT BIT(3)
109 #define HCLGE_V_TAG_BIT BIT(4)
110 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \
111 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT)
113 #define HCLGE_RSS_TC_SIZE_0 1
114 #define HCLGE_RSS_TC_SIZE_1 2
115 #define HCLGE_RSS_TC_SIZE_2 4
116 #define HCLGE_RSS_TC_SIZE_3 8
117 #define HCLGE_RSS_TC_SIZE_4 16
118 #define HCLGE_RSS_TC_SIZE_5 32
119 #define HCLGE_RSS_TC_SIZE_6 64
120 #define HCLGE_RSS_TC_SIZE_7 128
122 #define HCLGE_UMV_TBL_SIZE 3072
123 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
124 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
126 #define HCLGE_TQP_RESET_TRY_TIMES 200
128 #define HCLGE_PHY_PAGE_MDIX 0
129 #define HCLGE_PHY_PAGE_COPPER 0
131 /* Page Selection Reg. */
132 #define HCLGE_PHY_PAGE_REG 22
134 /* Copper Specific Control Register */
135 #define HCLGE_PHY_CSC_REG 16
137 /* Copper Specific Status Register */
138 #define HCLGE_PHY_CSS_REG 17
140 #define HCLGE_PHY_MDIX_CTRL_S 5
141 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
143 #define HCLGE_PHY_MDIX_STATUS_B 6
144 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
146 #define HCLGE_GET_DFX_REG_TYPE_CNT 4
148 /* Factor used to calculate offset and bitmap of VF num */
149 #define HCLGE_VF_NUM_PER_CMD 64
151 #define HCLGE_MAX_QSET_NUM 1024
153 #define HCLGE_DBG_RESET_INFO_LEN 1024
155 enum HLCGE_PORT_TYPE {
160 #define PF_VPORT_ID 0
162 #define HCLGE_PF_ID_S 0
163 #define HCLGE_PF_ID_M GENMASK(2, 0)
164 #define HCLGE_VF_ID_S 3
165 #define HCLGE_VF_ID_M GENMASK(10, 3)
166 #define HCLGE_PORT_TYPE_B 11
167 #define HCLGE_NETWORK_PORT_ID_S 0
168 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
170 /* Reset related Registers */
171 #define HCLGE_PF_OTHER_INT_REG 0x20600
172 #define HCLGE_MISC_RESET_STS_REG 0x20700
173 #define HCLGE_MISC_VECTOR_INT_STS 0x20800
174 #define HCLGE_GLOBAL_RESET_REG 0x20A00
175 #define HCLGE_GLOBAL_RESET_BIT 0
176 #define HCLGE_CORE_RESET_BIT 1
177 #define HCLGE_IMP_RESET_BIT 2
178 #define HCLGE_RESET_INT_M GENMASK(7, 5)
179 #define HCLGE_FUN_RST_ING 0x20C00
180 #define HCLGE_FUN_RST_ING_B 0
182 /* Vector0 register bits define */
183 #define HCLGE_VECTOR0_REG_PTP_INT_B 0
184 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
185 #define HCLGE_VECTOR0_CORERESET_INT_B 6
186 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
188 /* Vector0 interrupt CMDQ event source register(RW) */
189 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
190 /* CMDQ register bits for RX event(=MBX event) */
191 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
193 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1
194 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U
195 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
196 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U
197 #define HCLGE_TRIGGER_IMP_RESET_B 7U
199 #define HCLGE_MAC_DEFAULT_FRAME \
200 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
201 #define HCLGE_MAC_MIN_FRAME 64
202 #define HCLGE_MAC_MAX_FRAME 9728
204 #define HCLGE_SUPPORT_1G_BIT BIT(0)
205 #define HCLGE_SUPPORT_10G_BIT BIT(1)
206 #define HCLGE_SUPPORT_25G_BIT BIT(2)
207 #define HCLGE_SUPPORT_50G_BIT BIT(3)
208 #define HCLGE_SUPPORT_100G_BIT BIT(4)
209 /* to be compatible with exsit board */
210 #define HCLGE_SUPPORT_40G_BIT BIT(5)
211 #define HCLGE_SUPPORT_100M_BIT BIT(6)
212 #define HCLGE_SUPPORT_10M_BIT BIT(7)
213 #define HCLGE_SUPPORT_200G_BIT BIT(8)
214 #define HCLGE_SUPPORT_GE \
215 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
217 enum HCLGE_DEV_STATE {
218 HCLGE_STATE_REINITING,
220 HCLGE_STATE_DISABLED,
221 HCLGE_STATE_REMOVING,
222 HCLGE_STATE_NIC_REGISTERED,
223 HCLGE_STATE_ROCE_REGISTERED,
224 HCLGE_STATE_SERVICE_INITED,
225 HCLGE_STATE_RST_SERVICE_SCHED,
226 HCLGE_STATE_RST_HANDLING,
227 HCLGE_STATE_MBX_SERVICE_SCHED,
228 HCLGE_STATE_MBX_HANDLING,
229 HCLGE_STATE_ERR_SERVICE_SCHED,
230 HCLGE_STATE_STATISTICS_UPDATING,
231 HCLGE_STATE_CMD_DISABLE,
232 HCLGE_STATE_LINK_UPDATING,
233 HCLGE_STATE_RST_FAIL,
234 HCLGE_STATE_FD_TBL_CHANGED,
235 HCLGE_STATE_FD_CLEAR_ALL,
236 HCLGE_STATE_FD_USER_DEF_CHANGED,
238 HCLGE_STATE_PTP_TX_HANDLING,
242 enum hclge_evt_cause {
243 HCLGE_VECTOR0_EVENT_RST,
244 HCLGE_VECTOR0_EVENT_MBX,
245 HCLGE_VECTOR0_EVENT_ERR,
246 HCLGE_VECTOR0_EVENT_PTP,
247 HCLGE_VECTOR0_EVENT_OTHER,
250 enum HCLGE_MAC_SPEED {
251 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */
252 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
253 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
254 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
255 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
256 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
257 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
258 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
259 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
260 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */
263 enum HCLGE_MAC_DUPLEX {
268 #define QUERY_SFP_SPEED 0
269 #define QUERY_ACTIVE_SPEED 1
275 u8 media_type; /* port media type, e.g. fibre/copper/backplane */
276 u8 mac_addr[ETH_ALEN];
280 u8 speed_type; /* 0: sfp speed, 1: active speed */
283 u32 speed_ability; /* speed ability supported by current media */
284 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
285 u32 fec_mode; /* active fec mode */
288 int link; /* store the link status of mac & phy (if phy exists) */
289 struct phy_device *phydev;
290 struct mii_bus *mdio_bus;
291 phy_interface_t phy_if;
292 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
293 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
297 void __iomem *io_base;
298 void __iomem *mem_base;
299 struct hclge_mac mac;
301 struct hclge_cmq cmq;
305 struct hlcge_tqp_stats {
306 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
307 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
308 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
309 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
313 /* copy of device pointer from pci_dev,
314 * used when perform DMA mapping
317 struct hnae3_queue q;
318 struct hlcge_tqp_stats tqp_stats;
319 u16 index; /* Global index in a NIC controller */
333 #define HCLGE_FILTER_TYPE_VF 0
334 #define HCLGE_FILTER_TYPE_PORT 1
335 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)
336 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)
337 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)
338 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2)
339 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3)
340 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \
341 | HCLGE_FILTER_FE_ROCE_EGRESS_B)
342 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \
343 | HCLGE_FILTER_FE_ROCE_INGRESS_B)
345 enum hclge_vlan_fltr_cap {
347 HCLGE_VLAN_FLTR_CAN_MDF,
349 enum hclge_link_fail_code {
351 HCLGE_LF_REF_CLOCK_LOST,
352 HCLGE_LF_XSFP_TX_DISABLE,
353 HCLGE_LF_XSFP_ABSENT,
356 #define HCLGE_LINK_STATUS_DOWN 0
357 #define HCLGE_LINK_STATUS_UP 1
359 #define HCLGE_PG_NUM 4
360 #define HCLGE_SCH_MODE_SP 0
361 #define HCLGE_SCH_MODE_DWRR 1
362 struct hclge_pg_info {
364 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
367 u8 tc_dwrr[HNAE3_MAX_TC];
370 struct hclge_tc_info {
372 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
386 u8 mac_addr[ETH_ALEN];
389 u32 tx_spare_buf_size;
394 struct hclge_tm_info {
396 u8 num_pg; /* It must be 1 if vNET-Base schd */
397 u8 pg_dwrr[HCLGE_PG_NUM];
398 u8 prio_tc[HNAE3_MAX_USER_PRIO];
399 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
400 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
401 enum hclge_fc_mode fc_mode;
402 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
403 u8 pfc_en; /* PFC enabled or not for user priority */
406 struct hclge_comm_stats_str {
407 char desc[ETH_GSTRING_LEN];
408 unsigned long offset;
411 /* mac stats ,opcode id: 0x0032 */
412 struct hclge_mac_stats {
413 u64 mac_tx_mac_pause_num;
414 u64 mac_rx_mac_pause_num;
415 u64 mac_tx_pfc_pri0_pkt_num;
416 u64 mac_tx_pfc_pri1_pkt_num;
417 u64 mac_tx_pfc_pri2_pkt_num;
418 u64 mac_tx_pfc_pri3_pkt_num;
419 u64 mac_tx_pfc_pri4_pkt_num;
420 u64 mac_tx_pfc_pri5_pkt_num;
421 u64 mac_tx_pfc_pri6_pkt_num;
422 u64 mac_tx_pfc_pri7_pkt_num;
423 u64 mac_rx_pfc_pri0_pkt_num;
424 u64 mac_rx_pfc_pri1_pkt_num;
425 u64 mac_rx_pfc_pri2_pkt_num;
426 u64 mac_rx_pfc_pri3_pkt_num;
427 u64 mac_rx_pfc_pri4_pkt_num;
428 u64 mac_rx_pfc_pri5_pkt_num;
429 u64 mac_rx_pfc_pri6_pkt_num;
430 u64 mac_rx_pfc_pri7_pkt_num;
431 u64 mac_tx_total_pkt_num;
432 u64 mac_tx_total_oct_num;
433 u64 mac_tx_good_pkt_num;
434 u64 mac_tx_bad_pkt_num;
435 u64 mac_tx_good_oct_num;
436 u64 mac_tx_bad_oct_num;
437 u64 mac_tx_uni_pkt_num;
438 u64 mac_tx_multi_pkt_num;
439 u64 mac_tx_broad_pkt_num;
440 u64 mac_tx_undersize_pkt_num;
441 u64 mac_tx_oversize_pkt_num;
442 u64 mac_tx_64_oct_pkt_num;
443 u64 mac_tx_65_127_oct_pkt_num;
444 u64 mac_tx_128_255_oct_pkt_num;
445 u64 mac_tx_256_511_oct_pkt_num;
446 u64 mac_tx_512_1023_oct_pkt_num;
447 u64 mac_tx_1024_1518_oct_pkt_num;
448 u64 mac_tx_1519_2047_oct_pkt_num;
449 u64 mac_tx_2048_4095_oct_pkt_num;
450 u64 mac_tx_4096_8191_oct_pkt_num;
452 u64 mac_tx_8192_9216_oct_pkt_num;
453 u64 mac_tx_9217_12287_oct_pkt_num;
454 u64 mac_tx_12288_16383_oct_pkt_num;
455 u64 mac_tx_1519_max_good_oct_pkt_num;
456 u64 mac_tx_1519_max_bad_oct_pkt_num;
458 u64 mac_rx_total_pkt_num;
459 u64 mac_rx_total_oct_num;
460 u64 mac_rx_good_pkt_num;
461 u64 mac_rx_bad_pkt_num;
462 u64 mac_rx_good_oct_num;
463 u64 mac_rx_bad_oct_num;
464 u64 mac_rx_uni_pkt_num;
465 u64 mac_rx_multi_pkt_num;
466 u64 mac_rx_broad_pkt_num;
467 u64 mac_rx_undersize_pkt_num;
468 u64 mac_rx_oversize_pkt_num;
469 u64 mac_rx_64_oct_pkt_num;
470 u64 mac_rx_65_127_oct_pkt_num;
471 u64 mac_rx_128_255_oct_pkt_num;
472 u64 mac_rx_256_511_oct_pkt_num;
473 u64 mac_rx_512_1023_oct_pkt_num;
474 u64 mac_rx_1024_1518_oct_pkt_num;
475 u64 mac_rx_1519_2047_oct_pkt_num;
476 u64 mac_rx_2048_4095_oct_pkt_num;
477 u64 mac_rx_4096_8191_oct_pkt_num;
479 u64 mac_rx_8192_9216_oct_pkt_num;
480 u64 mac_rx_9217_12287_oct_pkt_num;
481 u64 mac_rx_12288_16383_oct_pkt_num;
482 u64 mac_rx_1519_max_good_oct_pkt_num;
483 u64 mac_rx_1519_max_bad_oct_pkt_num;
485 u64 mac_tx_fragment_pkt_num;
486 u64 mac_tx_undermin_pkt_num;
487 u64 mac_tx_jabber_pkt_num;
488 u64 mac_tx_err_all_pkt_num;
489 u64 mac_tx_from_app_good_pkt_num;
490 u64 mac_tx_from_app_bad_pkt_num;
491 u64 mac_rx_fragment_pkt_num;
492 u64 mac_rx_undermin_pkt_num;
493 u64 mac_rx_jabber_pkt_num;
494 u64 mac_rx_fcs_err_pkt_num;
495 u64 mac_rx_send_app_good_pkt_num;
496 u64 mac_rx_send_app_bad_pkt_num;
497 u64 mac_tx_pfc_pause_pkt_num;
498 u64 mac_rx_pfc_pause_pkt_num;
499 u64 mac_tx_ctrl_pkt_num;
500 u64 mac_rx_ctrl_pkt_num;
503 #define HCLGE_STATS_TIMER_INTERVAL 300UL
505 struct hclge_vlan_type_cfg {
506 u16 rx_ot_fst_vlan_type;
507 u16 rx_ot_sec_vlan_type;
508 u16 rx_in_fst_vlan_type;
509 u16 rx_in_sec_vlan_type;
515 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
516 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
517 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
518 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
521 enum HCLGE_FD_KEY_TYPE {
522 HCLGE_FD_KEY_BASE_ON_PTYPE,
523 HCLGE_FD_KEY_BASE_ON_TUPLE,
526 enum HCLGE_FD_STAGE {
532 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet
533 * INNER_XXX indicate tuples in tunneled header of tunnel packet or
534 * tuples of non-tunnel packet
536 enum HCLGE_FD_TUPLE {
570 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \
571 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV))
573 enum HCLGE_FD_META_DATA {
585 enum HCLGE_FD_KEY_OPT {
596 u8 key_length; /* use bit as unit */
597 enum HCLGE_FD_KEY_OPT key_opt;
602 #define MAX_KEY_LENGTH 400
603 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
604 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
605 #define MAX_META_DATA_LENGTH 32
607 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000
608 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0)
609 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0)
610 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0)
612 /* assigned by firmware, the real filter number for each pf may be less */
613 #define MAX_FD_FILTER_NUM 4096
614 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL
616 enum HCLGE_FD_ACTIVE_RULE_TYPE {
618 HCLGE_FD_ARFS_ACTIVE,
620 HCLGE_FD_TC_FLOWER_ACTIVE,
623 enum HCLGE_FD_PACKET_TYPE {
628 enum HCLGE_FD_ACTION {
629 HCLGE_FD_ACTION_SELECT_QUEUE,
630 HCLGE_FD_ACTION_DROP_PACKET,
631 HCLGE_FD_ACTION_SELECT_TC,
634 enum HCLGE_FD_NODE_STATE {
641 enum HCLGE_FD_USER_DEF_LAYER {
642 HCLGE_FD_USER_DEF_NONE,
643 HCLGE_FD_USER_DEF_L2,
644 HCLGE_FD_USER_DEF_L3,
645 HCLGE_FD_USER_DEF_L4,
648 #define HCLGE_FD_USER_DEF_LAYER_NUM 3
649 struct hclge_fd_user_def_cfg {
654 struct hclge_fd_user_def_info {
655 enum HCLGE_FD_USER_DEF_LAYER layer;
661 struct hclge_fd_key_cfg {
663 u8 inner_sipv6_word_en;
664 u8 inner_dipv6_word_en;
665 u8 outer_sipv6_word_en;
666 u8 outer_dipv6_word_en;
668 u32 meta_data_active;
671 struct hclge_fd_cfg {
673 u16 max_key_length; /* use bit as unit */
674 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
675 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
676 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
677 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM];
682 struct hclge_fd_rule_tuples {
683 u8 src_mac[ETH_ALEN];
684 u8 dst_mac[ETH_ALEN];
685 /* Be compatible for ip address of both ipv4 and ipv6.
686 * For ipv4 address, we store it in src/dst_ip[3].
688 u32 src_ip[IPV6_SIZE];
689 u32 dst_ip[IPV6_SIZE];
701 struct hclge_fd_rule {
702 struct hlist_node rule_node;
703 struct hclge_fd_rule_tuples tuples;
704 struct hclge_fd_rule_tuples tuples_mask;
709 unsigned long cookie;
713 u16 flow_id; /* only used for arfs */
716 struct hclge_fd_user_def_info user_def;
722 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
723 enum HCLGE_FD_NODE_STATE state;
727 struct hclge_fd_ad_data {
730 u8 forward_to_direct_queue;
735 u8 write_rule_id_to_bd;
742 enum HCLGE_MAC_NODE_STATE {
748 struct hclge_mac_node {
749 struct list_head node;
750 enum HCLGE_MAC_NODE_STATE state;
751 u8 mac_addr[ETH_ALEN];
754 enum HCLGE_MAC_ADDR_TYPE {
759 struct hclge_vport_vlan_cfg {
760 struct list_head node;
765 struct hclge_rst_stats {
766 u32 reset_done_cnt; /* the number of reset has completed */
767 u32 hw_reset_done_cnt; /* the number of HW reset has completed */
768 u32 pf_rst_cnt; /* the number of PF reset */
769 u32 flr_rst_cnt; /* the number of FLR */
770 u32 global_rst_cnt; /* the number of GLOBAL */
771 u32 imp_rst_cnt; /* the number of IMP reset */
772 u32 reset_cnt; /* the number of reset */
773 u32 reset_fail_cnt; /* the number of reset fail */
776 /* time and register status when mac tunnel interruption occur */
777 struct hclge_mac_tnl_stats {
782 #define HCLGE_RESET_INTERVAL (10 * HZ)
783 #define HCLGE_WAIT_RESET_DONE 100
786 struct hclge_vf_vlan_cfg {
801 /* For each bit of TCAM entry, it uses a pair of 'x' and
802 * 'y' to indicate which value to match, like below:
803 * ----------------------------------
804 * | bit x | bit y | search value |
805 * ----------------------------------
806 * | 0 | 0 | always hit |
807 * ----------------------------------
808 * | 1 | 0 | match '0' |
809 * ----------------------------------
810 * | 0 | 1 | match '1' |
811 * ----------------------------------
812 * | 1 | 1 | invalid |
813 * ----------------------------------
814 * Then for input key(k) and mask(v), we can calculate the value by
819 #define calc_x(x, k, v) (x = ~(k) & (v))
820 #define calc_y(y, k, v) \
822 const typeof(k) _k_ = (k); \
823 const typeof(v) _v_ = (v); \
824 (y) = (_k_ ^ ~_v_) & (_k_); \
827 #define HCLGE_MAC_TNL_LOG_SIZE 8
828 #define HCLGE_VPORT_NUM 256
830 struct pci_dev *pdev;
831 struct hnae3_ae_dev *ae_dev;
833 struct hclge_misc_vector misc_vector;
834 struct hclge_mac_stats mac_stats;
836 unsigned long flr_state;
837 unsigned long last_reset_time;
839 enum hnae3_reset_type reset_type;
840 enum hnae3_reset_type reset_level;
841 unsigned long default_reset_request;
842 unsigned long reset_request; /* reset has been requested */
843 unsigned long reset_pending; /* client rst is pending to be served */
844 struct hclge_rst_stats rst_stats;
845 struct semaphore reset_sem; /* protect reset process */
847 u16 num_tqps; /* Num task queue pairs of this PF */
848 u16 num_req_vfs; /* Num VFs requested for this PF */
850 u16 base_tqp_pid; /* Base task tqp physical id of this PF */
851 u16 alloc_rss_size; /* Allocated RSS task queue */
852 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */
853 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */
854 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */
856 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
857 u16 num_alloc_vport; /* Num vports this driver supports */
860 u16 num_tx_desc; /* desc num of per tx queue */
861 u16 num_rx_desc; /* desc num of per rx queue */
863 enum hclge_fc_mode fc_mode_last_time;
864 u8 support_sfp_query;
866 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
867 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
874 struct hclge_tm_info tm_info;
882 u16 num_nic_msi; /* Num of nic vectors for this PF */
883 u16 num_roce_msi; /* Num of roce vectors for this PF */
884 int roce_base_vector;
886 unsigned long service_timer_period;
887 unsigned long service_timer_previous;
888 struct timer_list reset_timer;
889 struct delayed_work service_task;
892 int num_alloc_vfs; /* Actual number of VFs allocated */
894 struct hclge_tqp *htqp;
895 struct hclge_vport *vport;
897 struct dentry *hclge_dbgfs;
899 struct hnae3_client *nic_client;
900 struct hnae3_client *roce_client;
902 #define HCLGE_FLAG_MAIN BIT(0)
903 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)
904 #define HCLGE_FLAG_DCB_ENABLE BIT(2)
905 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
908 u32 pkt_buf_size; /* Total pf buf size for tx/rx */
909 u32 tx_buf_size; /* Tx buffer size for each TC */
910 u32 dv_buf_size; /* Dv buffer size for each TC */
912 u32 mps; /* Max packet size */
913 /* vport_lock protect resource shared by vports */
914 struct mutex vport_lock;
916 struct hclge_vlan_type_cfg vlan_type_cfg;
918 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
919 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
921 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
923 struct hclge_fd_cfg fd_cfg;
924 struct hlist_head fd_rule_list;
925 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
926 u16 hclge_fd_rule_num;
927 unsigned long serv_processed_cnt;
928 unsigned long last_serv_processed;
929 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
930 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
935 /* max available unicast mac vlan space */
937 /* private unicast mac vlan space, it's same for PF and its VFs */
939 /* unicast mac vlan space shared by PF and its VFs */
942 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
943 HCLGE_MAC_TNL_LOG_SIZE);
945 /* affinity mask and notify for misc interrupt */
946 cpumask_t affinity_mask;
947 struct irq_affinity_notify affinity_notify;
948 struct hclge_ptp *ptp;
949 struct devlink *devlink;
952 /* VPort level vlan tag configuration for TX direction */
953 struct hclge_tx_vtag_cfg {
954 bool accept_tag1; /* Whether accept tag1 packet from host */
955 bool accept_untag1; /* Whether accept untag1 packet from host */
958 bool insert_tag1_en; /* Whether insert inner vlan tag */
959 bool insert_tag2_en; /* Whether insert outer vlan tag */
960 u16 default_tag1; /* The default inner vlan tag to insert */
961 u16 default_tag2; /* The default outer vlan tag to insert */
962 bool tag_shift_mode_en;
965 /* VPort level vlan tag configuration for RX direction */
966 struct hclge_rx_vtag_cfg {
967 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
968 bool strip_tag1_en; /* Whether strip inner vlan tag */
969 bool strip_tag2_en; /* Whether strip outer vlan tag */
970 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */
971 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */
972 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */
973 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */
976 struct hclge_rss_tuple_cfg {
987 enum HCLGE_VPORT_STATE {
988 HCLGE_VPORT_STATE_ALIVE,
989 HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
990 HCLGE_VPORT_STATE_PROMISC_CHANGE,
991 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
992 HCLGE_VPORT_STATE_MAX
995 struct hclge_vlan_info {
996 u16 vlan_proto; /* so far support 802.1Q only */
1001 struct hclge_port_base_vlan_config {
1003 struct hclge_vlan_info vlan_info;
1006 struct hclge_vf_info {
1017 struct hclge_vport {
1018 u16 alloc_tqps; /* Allocated Tx/Rx queues */
1020 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
1021 /* User configured lookup table entries */
1022 u16 *rss_indirection_tbl;
1023 int rss_algo; /* User configured hash algorithm */
1024 /* User configured rss tuple sets */
1025 struct hclge_rss_tuple_cfg rss_tuple_sets;
1030 u32 bw_limit; /* VSI BW Limit (0 = disabled) */
1033 bool req_vlan_fltr_en;
1034 bool cur_vlan_fltr_en;
1035 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
1036 struct hclge_port_base_vlan_config port_base_vlan_cfg;
1037 struct hclge_tx_vtag_cfg txvlan_cfg;
1038 struct hclge_rx_vtag_cfg rxvlan_cfg;
1043 struct hclge_dev *back; /* Back reference to associated dev */
1044 struct hnae3_handle nic;
1045 struct hnae3_handle roce;
1047 unsigned long state;
1048 unsigned long last_active_jiffies;
1049 u32 mps; /* Max packet size */
1050 struct hclge_vf_info vf_info;
1052 u8 overflow_promisc_flags;
1053 u8 last_promisc_flags;
1055 spinlock_t mac_list_lock; /* protect mac address need to add/detele */
1056 struct list_head uc_mac_list; /* Store VF unicast table */
1057 struct list_head mc_mac_list; /* Store VF multicast table */
1058 struct list_head vlan_list; /* Store VF vlan table */
1061 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
1062 bool en_mc_pmc, bool en_bc_pmc);
1063 int hclge_add_uc_addr_common(struct hclge_vport *vport,
1064 const unsigned char *addr);
1065 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
1066 const unsigned char *addr);
1067 int hclge_add_mc_addr_common(struct hclge_vport *vport,
1068 const unsigned char *addr);
1069 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
1070 const unsigned char *addr);
1072 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
1073 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
1074 int vector_id, bool en,
1075 struct hnae3_ring_chain_node *ring_chain);
1077 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
1079 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
1084 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
1086 return !!hdev->reset_pending;
1089 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
1090 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
1091 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
1092 u16 vlan_id, bool is_kill);
1093 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
1095 int hclge_buffer_alloc(struct hclge_dev *hdev);
1096 int hclge_rss_init_hw(struct hclge_dev *hdev);
1097 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
1099 void hclge_mbx_handler(struct hclge_dev *hdev);
1100 int hclge_reset_tqp(struct hnae3_handle *handle);
1101 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
1102 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
1103 int hclge_vport_start(struct hclge_vport *vport);
1104 void hclge_vport_stop(struct hclge_vport *vport);
1105 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
1106 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
1107 char *buf, int len);
1108 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
1109 int hclge_notify_client(struct hclge_dev *hdev,
1110 enum hnae3_reset_notify_type type);
1111 int hclge_update_mac_list(struct hclge_vport *vport,
1112 enum HCLGE_MAC_NODE_STATE state,
1113 enum HCLGE_MAC_ADDR_TYPE mac_type,
1114 const unsigned char *addr);
1115 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
1116 const u8 *old_addr, const u8 *new_addr);
1117 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
1118 enum HCLGE_MAC_ADDR_TYPE mac_type);
1119 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
1120 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
1121 void hclge_restore_mac_table_common(struct hclge_vport *vport);
1122 void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
1123 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
1124 struct hclge_vlan_info *vlan_info);
1125 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
1127 struct hclge_vlan_info *vlan_info);
1128 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
1129 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
1130 struct hclge_desc *desc);
1131 void hclge_report_hw_error(struct hclge_dev *hdev,
1132 enum hnae3_hw_error_type type);
1133 void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
1134 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len);
1135 int hclge_push_vf_link_status(struct hclge_vport *vport);
1136 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en);