2 * Copyright (c) 2016~2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #ifndef __HCLGE_MAIN_H
11 #define __HCLGE_MAIN_H
13 #include <linux/types.h>
14 #include <linux/phy.h>
15 #include "hclge_cmd.h"
18 #define HCLGE_MOD_VERSION "v1.0"
19 #define HCLGE_DRIVER_NAME "hclge"
21 #define HCLGE_INVALID_VPORT 0xffff
23 #define HCLGE_ROCE_VECTOR_OFFSET 96
25 #define HCLGE_PF_CFG_BLOCK_SIZE 32
26 #define HCLGE_PF_CFG_DESC_NUM \
27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
29 #define HCLGE_VECTOR_REG_BASE 0x20000
30 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
32 #define HCLGE_VECTOR_REG_OFFSET 0x4
33 #define HCLGE_VECTOR_VF_OFFSET 0x100000
35 #define HCLGE_RSS_IND_TBL_SIZE 512
36 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
37 #define HCLGE_RSS_KEY_SIZE 40
38 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
39 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1
40 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
41 #define HCLGE_RSS_HASH_ALGO_MASK 0xf
42 #define HCLGE_RSS_CFG_TBL_NUM \
43 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
45 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
46 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
47 #define HCLGE_D_PORT_BIT BIT(0)
48 #define HCLGE_S_PORT_BIT BIT(1)
49 #define HCLGE_D_IP_BIT BIT(2)
50 #define HCLGE_S_IP_BIT BIT(3)
51 #define HCLGE_V_TAG_BIT BIT(4)
53 #define HCLGE_RSS_TC_SIZE_0 1
54 #define HCLGE_RSS_TC_SIZE_1 2
55 #define HCLGE_RSS_TC_SIZE_2 4
56 #define HCLGE_RSS_TC_SIZE_3 8
57 #define HCLGE_RSS_TC_SIZE_4 16
58 #define HCLGE_RSS_TC_SIZE_5 32
59 #define HCLGE_RSS_TC_SIZE_6 64
60 #define HCLGE_RSS_TC_SIZE_7 128
62 #define HCLGE_TQP_RESET_TRY_TIMES 10
64 #define HCLGE_PHY_PAGE_MDIX 0
65 #define HCLGE_PHY_PAGE_COPPER 0
67 /* Page Selection Reg. */
68 #define HCLGE_PHY_PAGE_REG 22
70 /* Copper Specific Control Register */
71 #define HCLGE_PHY_CSC_REG 16
73 /* Copper Specific Status Register */
74 #define HCLGE_PHY_CSS_REG 17
76 #define HCLGE_PHY_MDIX_CTRL_S (5)
77 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
79 #define HCLGE_PHY_MDIX_STATUS_B (6)
80 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B (11)
82 /* Factor used to calculate offset and bitmap of VF num */
83 #define HCLGE_VF_NUM_PER_CMD 64
84 #define HCLGE_VF_NUM_PER_BYTE 8
86 /* Reset related Registers */
87 #define HCLGE_MISC_RESET_STS_REG 0x20700
88 #define HCLGE_GLOBAL_RESET_REG 0x20A00
89 #define HCLGE_GLOBAL_RESET_BIT 0x0
90 #define HCLGE_CORE_RESET_BIT 0x1
91 #define HCLGE_FUN_RST_ING 0x20C00
92 #define HCLGE_FUN_RST_ING_B 0
94 /* Vector0 register bits define */
95 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
96 #define HCLGE_VECTOR0_CORERESET_INT_B 6
97 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
99 /* Vector0 interrupt CMDQ event source register(RW) */
100 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
101 /* CMDQ register bits for RX event(=MBX event) */
102 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
104 #define HCLGE_MAC_DEFAULT_FRAME \
105 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN + ETH_DATA_LEN)
106 #define HCLGE_MAC_MIN_FRAME 64
107 #define HCLGE_MAC_MAX_FRAME 9728
109 #define HCLGE_SUPPORT_1G_BIT BIT(0)
110 #define HCLGE_SUPPORT_10G_BIT BIT(1)
111 #define HCLGE_SUPPORT_25G_BIT BIT(2)
112 #define HCLGE_SUPPORT_50G_BIT BIT(3)
113 #define HCLGE_SUPPORT_100G_BIT BIT(4)
115 enum HCLGE_DEV_STATE {
116 HCLGE_STATE_REINITING,
118 HCLGE_STATE_DISABLED,
119 HCLGE_STATE_REMOVING,
120 HCLGE_STATE_SERVICE_INITED,
121 HCLGE_STATE_SERVICE_SCHED,
122 HCLGE_STATE_RST_SERVICE_SCHED,
123 HCLGE_STATE_RST_HANDLING,
124 HCLGE_STATE_MBX_SERVICE_SCHED,
125 HCLGE_STATE_MBX_HANDLING,
126 HCLGE_STATE_STATISTICS_UPDATING,
130 enum hclge_evt_cause {
131 HCLGE_VECTOR0_EVENT_RST,
132 HCLGE_VECTOR0_EVENT_MBX,
133 HCLGE_VECTOR0_EVENT_OTHER,
136 #define HCLGE_MPF_ENBALE 1
144 enum HCLGE_MAC_SPEED {
145 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
146 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
147 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
148 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
149 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
150 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
151 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
152 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */
155 enum HCLGE_MAC_DUPLEX {
160 enum hclge_mta_dmac_sel_type {
161 HCLGE_MAC_ADDR_47_36,
162 HCLGE_MAC_ADDR_46_35,
163 HCLGE_MAC_ADDR_45_34,
164 HCLGE_MAC_ADDR_44_33,
171 u8 mac_addr[ETH_ALEN];
175 int link; /* store the link status of mac & phy (if phy exit)*/
176 struct phy_device *phydev;
177 struct mii_bus *mdio_bus;
178 phy_interface_t phy_if;
179 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
180 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
184 void __iomem *io_base;
185 struct hclge_mac mac;
187 struct hclge_cmq cmq;
188 struct hclge_caps caps;
193 struct hlcge_tqp_stats {
194 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
195 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
196 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
197 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
201 struct device *dev; /* Device for DMA mapping */
202 struct hnae3_queue q;
203 struct hlcge_tqp_stats tqp_stats;
204 u16 index; /* Global index in a NIC controller */
218 #define HCLGE_PG_NUM 4
219 #define HCLGE_SCH_MODE_SP 0
220 #define HCLGE_SCH_MODE_DWRR 1
221 struct hclge_pg_info {
223 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
226 u8 tc_dwrr[HNAE3_MAX_TC];
229 struct hclge_tc_info {
231 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
244 u8 mac_addr[ETH_ALEN];
250 struct hclge_tm_info {
252 u8 num_pg; /* It must be 1 if vNET-Base schd */
253 u8 pg_dwrr[HCLGE_PG_NUM];
254 u8 prio_tc[HNAE3_MAX_USER_PRIO];
255 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
256 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
257 enum hclge_fc_mode fc_mode;
258 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
261 struct hclge_comm_stats_str {
262 char desc[ETH_GSTRING_LEN];
263 unsigned long offset;
266 /* all 64bit stats, opcode id: 0x0030 */
267 struct hclge_64_bit_stats {
269 u64 igu_rx_oversize_pkt;
270 u64 igu_rx_undersize_pkt;
271 u64 igu_rx_out_all_pkt;
273 u64 igu_rx_multi_pkt;
274 u64 igu_rx_broad_pkt;
278 u64 egu_tx_out_all_pkt;
280 u64 egu_tx_multi_pkt;
281 u64 egu_tx_broad_pkt;
283 /* ssu_ppp packet stats */
284 u64 ssu_ppp_mac_key_num;
285 u64 ssu_ppp_host_key_num;
286 u64 ppp_ssu_mac_rlt_num;
287 u64 ppp_ssu_host_rlt_num;
289 /* ssu_tx_in_out_dfx_stats */
292 /* ssu_rx_in_out_dfx_stats */
297 /* all 32bit stats, opcode id: 0x0031 */
298 struct hclge_32_bit_stats {
300 u64 igu_rx_no_eof_pkt;
301 u64 igu_rx_no_sof_pkt;
304 u64 ssu_full_drop_num;
305 u64 ssu_part_drop_num;
306 u64 ppp_key_drop_num;
307 u64 ppp_rlt_drop_num;
308 u64 ssu_key_drop_num;
309 u64 pkt_curr_buf_cnt;
312 u64 qcn_fb_invaild_cnt;
314 u64 rx_packet_tc0_in_cnt;
315 u64 rx_packet_tc1_in_cnt;
316 u64 rx_packet_tc2_in_cnt;
317 u64 rx_packet_tc3_in_cnt;
318 u64 rx_packet_tc4_in_cnt;
319 u64 rx_packet_tc5_in_cnt;
320 u64 rx_packet_tc6_in_cnt;
321 u64 rx_packet_tc7_in_cnt;
322 u64 rx_packet_tc0_out_cnt;
323 u64 rx_packet_tc1_out_cnt;
324 u64 rx_packet_tc2_out_cnt;
325 u64 rx_packet_tc3_out_cnt;
326 u64 rx_packet_tc4_out_cnt;
327 u64 rx_packet_tc5_out_cnt;
328 u64 rx_packet_tc6_out_cnt;
329 u64 rx_packet_tc7_out_cnt;
331 /* Tx packet level statistics */
332 u64 tx_packet_tc0_in_cnt;
333 u64 tx_packet_tc1_in_cnt;
334 u64 tx_packet_tc2_in_cnt;
335 u64 tx_packet_tc3_in_cnt;
336 u64 tx_packet_tc4_in_cnt;
337 u64 tx_packet_tc5_in_cnt;
338 u64 tx_packet_tc6_in_cnt;
339 u64 tx_packet_tc7_in_cnt;
340 u64 tx_packet_tc0_out_cnt;
341 u64 tx_packet_tc1_out_cnt;
342 u64 tx_packet_tc2_out_cnt;
343 u64 tx_packet_tc3_out_cnt;
344 u64 tx_packet_tc4_out_cnt;
345 u64 tx_packet_tc5_out_cnt;
346 u64 tx_packet_tc6_out_cnt;
347 u64 tx_packet_tc7_out_cnt;
349 /* packet buffer statistics */
350 u64 pkt_curr_buf_tc0_cnt;
351 u64 pkt_curr_buf_tc1_cnt;
352 u64 pkt_curr_buf_tc2_cnt;
353 u64 pkt_curr_buf_tc3_cnt;
354 u64 pkt_curr_buf_tc4_cnt;
355 u64 pkt_curr_buf_tc5_cnt;
356 u64 pkt_curr_buf_tc6_cnt;
357 u64 pkt_curr_buf_tc7_cnt;
360 u64 lo_pri_unicast_rlt_drop_num;
361 u64 hi_pri_multicast_rlt_drop_num;
362 u64 lo_pri_multicast_rlt_drop_num;
363 u64 rx_oq_drop_pkt_cnt;
364 u64 tx_oq_drop_pkt_cnt;
365 u64 nic_l2_err_drop_pkt_cnt;
366 u64 roc_l2_err_drop_pkt_cnt;
369 /* mac stats ,opcode id: 0x0032 */
370 struct hclge_mac_stats {
371 u64 mac_tx_mac_pause_num;
372 u64 mac_rx_mac_pause_num;
373 u64 mac_tx_pfc_pri0_pkt_num;
374 u64 mac_tx_pfc_pri1_pkt_num;
375 u64 mac_tx_pfc_pri2_pkt_num;
376 u64 mac_tx_pfc_pri3_pkt_num;
377 u64 mac_tx_pfc_pri4_pkt_num;
378 u64 mac_tx_pfc_pri5_pkt_num;
379 u64 mac_tx_pfc_pri6_pkt_num;
380 u64 mac_tx_pfc_pri7_pkt_num;
381 u64 mac_rx_pfc_pri0_pkt_num;
382 u64 mac_rx_pfc_pri1_pkt_num;
383 u64 mac_rx_pfc_pri2_pkt_num;
384 u64 mac_rx_pfc_pri3_pkt_num;
385 u64 mac_rx_pfc_pri4_pkt_num;
386 u64 mac_rx_pfc_pri5_pkt_num;
387 u64 mac_rx_pfc_pri6_pkt_num;
388 u64 mac_rx_pfc_pri7_pkt_num;
389 u64 mac_tx_total_pkt_num;
390 u64 mac_tx_total_oct_num;
391 u64 mac_tx_good_pkt_num;
392 u64 mac_tx_bad_pkt_num;
393 u64 mac_tx_good_oct_num;
394 u64 mac_tx_bad_oct_num;
395 u64 mac_tx_uni_pkt_num;
396 u64 mac_tx_multi_pkt_num;
397 u64 mac_tx_broad_pkt_num;
398 u64 mac_tx_undersize_pkt_num;
399 u64 mac_tx_oversize_pkt_num;
400 u64 mac_tx_64_oct_pkt_num;
401 u64 mac_tx_65_127_oct_pkt_num;
402 u64 mac_tx_128_255_oct_pkt_num;
403 u64 mac_tx_256_511_oct_pkt_num;
404 u64 mac_tx_512_1023_oct_pkt_num;
405 u64 mac_tx_1024_1518_oct_pkt_num;
406 u64 mac_tx_1519_2047_oct_pkt_num;
407 u64 mac_tx_2048_4095_oct_pkt_num;
408 u64 mac_tx_4096_8191_oct_pkt_num;
409 u64 mac_tx_8192_12287_oct_pkt_num; /* valid for GE MAC only */
410 u64 mac_tx_8192_9216_oct_pkt_num; /* valid for LGE & CGE MAC only */
411 u64 mac_tx_9217_12287_oct_pkt_num; /* valid for LGE & CGE MAC */
412 u64 mac_tx_12288_16383_oct_pkt_num;
413 u64 mac_tx_1519_max_good_oct_pkt_num;
414 u64 mac_tx_1519_max_bad_oct_pkt_num;
416 u64 mac_rx_total_pkt_num;
417 u64 mac_rx_total_oct_num;
418 u64 mac_rx_good_pkt_num;
419 u64 mac_rx_bad_pkt_num;
420 u64 mac_rx_good_oct_num;
421 u64 mac_rx_bad_oct_num;
422 u64 mac_rx_uni_pkt_num;
423 u64 mac_rx_multi_pkt_num;
424 u64 mac_rx_broad_pkt_num;
425 u64 mac_rx_undersize_pkt_num;
426 u64 mac_rx_oversize_pkt_num;
427 u64 mac_rx_64_oct_pkt_num;
428 u64 mac_rx_65_127_oct_pkt_num;
429 u64 mac_rx_128_255_oct_pkt_num;
430 u64 mac_rx_256_511_oct_pkt_num;
431 u64 mac_rx_512_1023_oct_pkt_num;
432 u64 mac_rx_1024_1518_oct_pkt_num;
433 u64 mac_rx_1519_2047_oct_pkt_num;
434 u64 mac_rx_2048_4095_oct_pkt_num;
435 u64 mac_rx_4096_8191_oct_pkt_num;
436 u64 mac_rx_8192_12287_oct_pkt_num;/* valid for GE MAC only */
437 u64 mac_rx_8192_9216_oct_pkt_num; /* valid for LGE & CGE MAC only */
438 u64 mac_rx_9217_12287_oct_pkt_num; /* valid for LGE & CGE MAC only */
439 u64 mac_rx_12288_16383_oct_pkt_num;
440 u64 mac_rx_1519_max_good_oct_pkt_num;
441 u64 mac_rx_1519_max_bad_oct_pkt_num;
443 u64 mac_tx_fragment_pkt_num;
444 u64 mac_tx_undermin_pkt_num;
445 u64 mac_tx_jabber_pkt_num;
446 u64 mac_tx_err_all_pkt_num;
447 u64 mac_tx_from_app_good_pkt_num;
448 u64 mac_tx_from_app_bad_pkt_num;
449 u64 mac_rx_fragment_pkt_num;
450 u64 mac_rx_undermin_pkt_num;
451 u64 mac_rx_jabber_pkt_num;
452 u64 mac_rx_fcs_err_pkt_num;
453 u64 mac_rx_send_app_good_pkt_num;
454 u64 mac_rx_send_app_bad_pkt_num;
457 #define HCLGE_STATS_TIMER_INTERVAL (60 * 5)
458 struct hclge_hw_stats {
459 struct hclge_mac_stats mac_stats;
460 struct hclge_64_bit_stats all_64_bit_stats;
461 struct hclge_32_bit_stats all_32_bit_stats;
465 struct hclge_vlan_type_cfg {
466 u16 rx_ot_fst_vlan_type;
467 u16 rx_ot_sec_vlan_type;
468 u16 rx_in_fst_vlan_type;
469 u16 rx_in_sec_vlan_type;
475 struct pci_dev *pdev;
476 struct hnae3_ae_dev *ae_dev;
478 struct hclge_misc_vector misc_vector;
479 struct hclge_hw_stats hw_stats;
482 enum hnae3_reset_type reset_type;
483 unsigned long reset_request; /* reset has been requested */
484 unsigned long reset_pending; /* client rst is pending to be served */
486 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
487 u16 num_tqps; /* Num task queue pairs of this PF */
488 u16 num_req_vfs; /* Num VFs requested for this PF */
490 /* Base task tqp physical id of this PF */
492 u16 alloc_rss_size; /* Allocated RSS task queue */
493 u16 rss_size_max; /* HW defined max RSS task queue */
495 /* Num of guaranteed filters for this PF */
496 u16 fdir_pf_filter_count;
497 u16 num_alloc_vport; /* Num vports this driver supports */
503 enum hclge_fc_mode fc_mode_last_time;
505 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
506 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
513 struct hclge_tm_info tm_info;
521 u16 num_roce_msi; /* Num of roce vectors for this PF */
522 int roce_base_vector;
524 u16 pending_udp_bitmap;
529 u16 adminq_work_limit; /* Num of admin receive queue desc to process */
530 unsigned long service_timer_period;
531 unsigned long service_timer_previous;
532 struct timer_list service_timer;
533 struct work_struct service_task;
534 struct work_struct rst_service_task;
535 struct work_struct mbx_service_task;
538 int num_alloc_vfs; /* Actual number of VFs allocated */
540 struct hclge_tqp *htqp;
541 struct hclge_vport *vport;
543 struct dentry *hclge_dbgfs;
545 struct hnae3_client *nic_client;
546 struct hnae3_client *roce_client;
548 #define HCLGE_FLAG_MAIN BIT(0)
549 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)
550 #define HCLGE_FLAG_DCB_ENABLE BIT(2)
551 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
554 u32 pkt_buf_size; /* Total pf buf size for tx/rx */
555 u32 mps; /* Max packet size */
557 enum hclge_mta_dmac_sel_type mta_mac_sel_type;
558 bool enable_mta; /* Mutilcast filter enable */
559 bool accept_mta_mc; /* Whether accept mta filter multicast */
561 struct hclge_vlan_type_cfg vlan_type_cfg;
567 /* VPort level vlan tag configuration for TX direction */
568 struct hclge_tx_vtag_cfg {
569 bool accept_tag; /* Whether accept tagged packet from host */
570 bool accept_untag; /* Whether accept untagged packet from host */
571 bool insert_tag1_en; /* Whether insert inner vlan tag */
572 bool insert_tag2_en; /* Whether insert outer vlan tag */
573 u16 default_tag1; /* The default inner vlan tag to insert */
574 u16 default_tag2; /* The default outer vlan tag to insert */
577 /* VPort level vlan tag configuration for RX direction */
578 struct hclge_rx_vtag_cfg {
579 bool strip_tag1_en; /* Whether strip inner vlan tag */
580 bool strip_tag2_en; /* Whether strip outer vlan tag */
581 bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */
582 bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */
585 struct hclge_rss_tuple_cfg {
597 u16 alloc_tqps; /* Allocated Tx/Rx queues */
599 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
600 /* User configured lookup table entries */
601 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
602 int rss_algo; /* User configured hash algorithm */
603 /* User configured rss tuple sets */
604 struct hclge_rss_tuple_cfg rss_tuple_sets;
609 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
612 struct hclge_tx_vtag_cfg txvlan_cfg;
613 struct hclge_rx_vtag_cfg rxvlan_cfg;
616 struct hclge_dev *back; /* Back reference to associated dev */
617 struct hnae3_handle nic;
618 struct hnae3_handle roce;
621 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
622 bool en_mc, bool en_bc, int vport_id);
624 int hclge_add_uc_addr_common(struct hclge_vport *vport,
625 const unsigned char *addr);
626 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
627 const unsigned char *addr);
628 int hclge_add_mc_addr_common(struct hclge_vport *vport,
629 const unsigned char *addr);
630 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
631 const unsigned char *addr);
633 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
636 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
637 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
638 int vector_id, bool en,
639 struct hnae3_ring_chain_node *ring_chain);
641 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
643 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
648 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
649 int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid,
650 bool is_kill, u16 vlan, u8 qos, __be16 proto);
652 int hclge_buffer_alloc(struct hclge_dev *hdev);
653 int hclge_rss_init_hw(struct hclge_dev *hdev);
654 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
656 void hclge_mbx_handler(struct hclge_dev *hdev);
657 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
658 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
659 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
660 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);