drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <net/rtnetlink.h>
  16 #include "hclge_cmd.h"
  17 #include "hclge_dcb.h"
  18 #include "hclge_main.h"
  19 #include "hclge_mbx.h"
  20 #include "hclge_mdio.h"
  21 #include "hclge_tm.h"
  22 #include "hnae3.h"
  23
  24 #define HCLGE_NAME                      "hclge"
  25 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  26 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
  27 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
  28 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
  29
  30 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
  31                                      enum hclge_mta_dmac_sel_type mta_mac_sel,
  32                                      bool enable);
  33 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
  34 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  35 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  36
  37 static struct hnae3_ae_algo ae_algo;
  38
  39 static const struct pci_device_id ae_algo_pci_tbl[] = {
  40         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  41         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  42         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  43         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  44         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  45         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  46         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  47         /* required last entry */
  48         {0, }
  49 };
  50
  51 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  52
  53 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
  54         "Mac    Loopback test",
  55         "Serdes Loopback test",
  56         "Phy    Loopback test"
  57 };
  58
  59 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
  60         {"igu_rx_oversize_pkt",
  61                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
  62         {"igu_rx_undersize_pkt",
  63                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
  64         {"igu_rx_out_all_pkt",
  65                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
  66         {"igu_rx_uni_pkt",
  67                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
  68         {"igu_rx_multi_pkt",
  69                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
  70         {"igu_rx_broad_pkt",
  71                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
  72         {"egu_tx_out_all_pkt",
  73                 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
  74         {"egu_tx_uni_pkt",
  75                 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
  76         {"egu_tx_multi_pkt",
  77                 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
  78         {"egu_tx_broad_pkt",
  79                 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
  80         {"ssu_ppp_mac_key_num",
  81                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
  82         {"ssu_ppp_host_key_num",
  83                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
  84         {"ppp_ssu_mac_rlt_num",
  85                 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
  86         {"ppp_ssu_host_rlt_num",
  87                 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
  88         {"ssu_tx_in_num",
  89                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
  90         {"ssu_tx_out_num",
  91                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
  92         {"ssu_rx_in_num",
  93                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
  94         {"ssu_rx_out_num",
  95                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
  96 };
  97
  98 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
  99         {"igu_rx_err_pkt",
 100                 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
 101         {"igu_rx_no_eof_pkt",
 102                 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
 103         {"igu_rx_no_sof_pkt",
 104                 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
 105         {"egu_tx_1588_pkt",
 106                 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
 107         {"ssu_full_drop_num",
 108                 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
 109         {"ssu_part_drop_num",
 110                 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
 111         {"ppp_key_drop_num",
 112                 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
 113         {"ppp_rlt_drop_num",
 114                 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
 115         {"ssu_key_drop_num",
 116                 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
 117         {"pkt_curr_buf_cnt",
 118                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
 119         {"qcn_fb_rcv_cnt",
 120                 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
 121         {"qcn_fb_drop_cnt",
 122                 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
 123         {"qcn_fb_invaild_cnt",
 124                 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
 125         {"rx_packet_tc0_in_cnt",
 126                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
 127         {"rx_packet_tc1_in_cnt",
 128                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
 129         {"rx_packet_tc2_in_cnt",
 130                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
 131         {"rx_packet_tc3_in_cnt",
 132                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
 133         {"rx_packet_tc4_in_cnt",
 134                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
 135         {"rx_packet_tc5_in_cnt",
 136                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
 137         {"rx_packet_tc6_in_cnt",
 138                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
 139         {"rx_packet_tc7_in_cnt",
 140                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
 141         {"rx_packet_tc0_out_cnt",
 142                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
 143         {"rx_packet_tc1_out_cnt",
 144                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
 145         {"rx_packet_tc2_out_cnt",
 146                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
 147         {"rx_packet_tc3_out_cnt",
 148                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
 149         {"rx_packet_tc4_out_cnt",
 150                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
 151         {"rx_packet_tc5_out_cnt",
 152                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
 153         {"rx_packet_tc6_out_cnt",
 154                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
 155         {"rx_packet_tc7_out_cnt",
 156                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
 157         {"tx_packet_tc0_in_cnt",
 158                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
 159         {"tx_packet_tc1_in_cnt",
 160                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
 161         {"tx_packet_tc2_in_cnt",
 162                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
 163         {"tx_packet_tc3_in_cnt",
 164                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
 165         {"tx_packet_tc4_in_cnt",
 166                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
 167         {"tx_packet_tc5_in_cnt",
 168                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
 169         {"tx_packet_tc6_in_cnt",
 170                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
 171         {"tx_packet_tc7_in_cnt",
 172                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
 173         {"tx_packet_tc0_out_cnt",
 174                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
 175         {"tx_packet_tc1_out_cnt",
 176                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
 177         {"tx_packet_tc2_out_cnt",
 178                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
 179         {"tx_packet_tc3_out_cnt",
 180                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
 181         {"tx_packet_tc4_out_cnt",
 182                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
 183         {"tx_packet_tc5_out_cnt",
 184                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
 185         {"tx_packet_tc6_out_cnt",
 186                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
 187         {"tx_packet_tc7_out_cnt",
 188                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
 189         {"pkt_curr_buf_tc0_cnt",
 190                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
 191         {"pkt_curr_buf_tc1_cnt",
 192                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
 193         {"pkt_curr_buf_tc2_cnt",
 194                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
 195         {"pkt_curr_buf_tc3_cnt",
 196                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
 197         {"pkt_curr_buf_tc4_cnt",
 198                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
 199         {"pkt_curr_buf_tc5_cnt",
 200                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
 201         {"pkt_curr_buf_tc6_cnt",
 202                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
 203         {"pkt_curr_buf_tc7_cnt",
 204                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
 205         {"mb_uncopy_num",
 206                 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
 207         {"lo_pri_unicast_rlt_drop_num",
 208                 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
 209         {"hi_pri_multicast_rlt_drop_num",
 210                 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
 211         {"lo_pri_multicast_rlt_drop_num",
 212                 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
 213         {"rx_oq_drop_pkt_cnt",
 214                 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
 215         {"tx_oq_drop_pkt_cnt",
 216                 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
 217         {"nic_l2_err_drop_pkt_cnt",
 218                 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
 219         {"roc_l2_err_drop_pkt_cnt",
 220                 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
 221 };
 222
 223 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
 224         {"mac_tx_mac_pause_num",
 225                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
 226         {"mac_rx_mac_pause_num",
 227                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
 228         {"mac_tx_pfc_pri0_pkt_num",
 229                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
 230         {"mac_tx_pfc_pri1_pkt_num",
 231                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
 232         {"mac_tx_pfc_pri2_pkt_num",
 233                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
 234         {"mac_tx_pfc_pri3_pkt_num",
 235                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
 236         {"mac_tx_pfc_pri4_pkt_num",
 237                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
 238         {"mac_tx_pfc_pri5_pkt_num",
 239                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
 240         {"mac_tx_pfc_pri6_pkt_num",
 241                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
 242         {"mac_tx_pfc_pri7_pkt_num",
 243                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
 244         {"mac_rx_pfc_pri0_pkt_num",
 245                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
 246         {"mac_rx_pfc_pri1_pkt_num",
 247                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
 248         {"mac_rx_pfc_pri2_pkt_num",
 249                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
 250         {"mac_rx_pfc_pri3_pkt_num",
 251                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
 252         {"mac_rx_pfc_pri4_pkt_num",
 253                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
 254         {"mac_rx_pfc_pri5_pkt_num",
 255                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
 256         {"mac_rx_pfc_pri6_pkt_num",
 257                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
 258         {"mac_rx_pfc_pri7_pkt_num",
 259                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
 260         {"mac_tx_total_pkt_num",
 261                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
 262         {"mac_tx_total_oct_num",
 263                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
 264         {"mac_tx_good_pkt_num",
 265                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 266         {"mac_tx_bad_pkt_num",
 267                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 268         {"mac_tx_good_oct_num",
 269                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 270         {"mac_tx_bad_oct_num",
 271                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 272         {"mac_tx_uni_pkt_num",
 273                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 274         {"mac_tx_multi_pkt_num",
 275                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 276         {"mac_tx_broad_pkt_num",
 277                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 278         {"mac_tx_undersize_pkt_num",
 279                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 280         {"mac_tx_oversize_pkt_num",
 281                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 282         {"mac_tx_64_oct_pkt_num",
 283                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 284         {"mac_tx_65_127_oct_pkt_num",
 285                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 286         {"mac_tx_128_255_oct_pkt_num",
 287                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 288         {"mac_tx_256_511_oct_pkt_num",
 289                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 290         {"mac_tx_512_1023_oct_pkt_num",
 291                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 292         {"mac_tx_1024_1518_oct_pkt_num",
 293                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 294         {"mac_tx_1519_2047_oct_pkt_num",
 295                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 296         {"mac_tx_2048_4095_oct_pkt_num",
 297                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 298         {"mac_tx_4096_8191_oct_pkt_num",
 299                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 300         {"mac_tx_8192_9216_oct_pkt_num",
 301                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 302         {"mac_tx_9217_12287_oct_pkt_num",
 303                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 304         {"mac_tx_12288_16383_oct_pkt_num",
 305                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 306         {"mac_tx_1519_max_good_pkt_num",
 307                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 308         {"mac_tx_1519_max_bad_pkt_num",
 309                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 310         {"mac_rx_total_pkt_num",
 311                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 312         {"mac_rx_total_oct_num",
 313                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 314         {"mac_rx_good_pkt_num",
 315                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 316         {"mac_rx_bad_pkt_num",
 317                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 318         {"mac_rx_good_oct_num",
 319                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 320         {"mac_rx_bad_oct_num",
 321                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 322         {"mac_rx_uni_pkt_num",
 323                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 324         {"mac_rx_multi_pkt_num",
 325                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 326         {"mac_rx_broad_pkt_num",
 327                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 328         {"mac_rx_undersize_pkt_num",
 329                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 330         {"mac_rx_oversize_pkt_num",
 331                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 332         {"mac_rx_64_oct_pkt_num",
 333                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 334         {"mac_rx_65_127_oct_pkt_num",
 335                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 336         {"mac_rx_128_255_oct_pkt_num",
 337                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 338         {"mac_rx_256_511_oct_pkt_num",
 339                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 340         {"mac_rx_512_1023_oct_pkt_num",
 341                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 342         {"mac_rx_1024_1518_oct_pkt_num",
 343                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 344         {"mac_rx_1519_2047_oct_pkt_num",
 345                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 346         {"mac_rx_2048_4095_oct_pkt_num",
 347                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 348         {"mac_rx_4096_8191_oct_pkt_num",
 349                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 350         {"mac_rx_8192_9216_oct_pkt_num",
 351                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 352         {"mac_rx_9217_12287_oct_pkt_num",
 353                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 354         {"mac_rx_12288_16383_oct_pkt_num",
 355                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 356         {"mac_rx_1519_max_good_pkt_num",
 357                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 358         {"mac_rx_1519_max_bad_pkt_num",
 359                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 360
 361         {"mac_tx_fragment_pkt_num",
 362                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 363         {"mac_tx_undermin_pkt_num",
 364                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 365         {"mac_tx_jabber_pkt_num",
 366                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 367         {"mac_tx_err_all_pkt_num",
 368                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 369         {"mac_tx_from_app_good_pkt_num",
 370                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 371         {"mac_tx_from_app_bad_pkt_num",
 372                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 373         {"mac_rx_fragment_pkt_num",
 374                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 375         {"mac_rx_undermin_pkt_num",
 376                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 377         {"mac_rx_jabber_pkt_num",
 378                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 379         {"mac_rx_fcs_err_pkt_num",
 380                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 381         {"mac_rx_send_app_good_pkt_num",
 382                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 383         {"mac_rx_send_app_bad_pkt_num",
 384                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 385 };
 386
 387 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 388         {
 389                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 390                 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
 391                 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
 392                 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
 393                 .i_port_bitmap = 0x1,
 394         },
 395 };
 396
 397 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
 398 {
 399 #define HCLGE_64_BIT_CMD_NUM 5
 400 #define HCLGE_64_BIT_RTN_DATANUM 4
 401         u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
 402         struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
 403         __le64 *desc_data;
 404         int i, k, n;
 405         int ret;
 406
 407         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
 408         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
 409         if (ret) {
 410                 dev_err(&hdev->pdev->dev,
 411                         "Get 64 bit pkt stats fail, status = %d.\n", ret);
 412                 return ret;
 413         }
 414
 415         for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
 416                 if (unlikely(i == 0)) {
 417                         desc_data = (__le64 *)(&desc[i].data[0]);
 418                         n = HCLGE_64_BIT_RTN_DATANUM - 1;
 419                 } else {
 420                         desc_data = (__le64 *)(&desc[i]);
 421                         n = HCLGE_64_BIT_RTN_DATANUM;
 422                 }
 423                 for (k = 0; k < n; k++) {
 424                         *data++ += le64_to_cpu(*desc_data);
 425                         desc_data++;
 426                 }
 427         }
 428
 429         return 0;
 430 }
 431
 432 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
 433 {
 434         stats->pkt_curr_buf_cnt     = 0;
 435         stats->pkt_curr_buf_tc0_cnt = 0;
 436         stats->pkt_curr_buf_tc1_cnt = 0;
 437         stats->pkt_curr_buf_tc2_cnt = 0;
 438         stats->pkt_curr_buf_tc3_cnt = 0;
 439         stats->pkt_curr_buf_tc4_cnt = 0;
 440         stats->pkt_curr_buf_tc5_cnt = 0;
 441         stats->pkt_curr_buf_tc6_cnt = 0;
 442         stats->pkt_curr_buf_tc7_cnt = 0;
 443 }
 444
 445 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
 446 {
 447 #define HCLGE_32_BIT_CMD_NUM 8
 448 #define HCLGE_32_BIT_RTN_DATANUM 8
 449
 450         struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
 451         struct hclge_32_bit_stats *all_32_bit_stats;
 452         __le32 *desc_data;
 453         int i, k, n;
 454         u64 *data;
 455         int ret;
 456
 457         all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
 458         data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
 459
 460         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
 461         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
 462         if (ret) {
 463                 dev_err(&hdev->pdev->dev,
 464                         "Get 32 bit pkt stats fail, status = %d.\n", ret);
 465
 466                 return ret;
 467         }
 468
 469         hclge_reset_partial_32bit_counter(all_32_bit_stats);
 470         for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
 471                 if (unlikely(i == 0)) {
 472                         __le16 *desc_data_16bit;
 473
 474                         all_32_bit_stats->igu_rx_err_pkt +=
 475                                 le32_to_cpu(desc[i].data[0]);
 476
 477                         desc_data_16bit = (__le16 *)&desc[i].data[1];
 478                         all_32_bit_stats->igu_rx_no_eof_pkt +=
 479                                 le16_to_cpu(*desc_data_16bit);
 480
 481                         desc_data_16bit++;
 482                         all_32_bit_stats->igu_rx_no_sof_pkt +=
 483                                 le16_to_cpu(*desc_data_16bit);
 484
 485                         desc_data = &desc[i].data[2];
 486                         n = HCLGE_32_BIT_RTN_DATANUM - 4;
 487                 } else {
 488                         desc_data = (__le32 *)&desc[i];
 489                         n = HCLGE_32_BIT_RTN_DATANUM;
 490                 }
 491                 for (k = 0; k < n; k++) {
 492                         *data++ += le32_to_cpu(*desc_data);
 493                         desc_data++;
 494                 }
 495         }
 496
 497         return 0;
 498 }
 499
 500 static int hclge_mac_update_stats(struct hclge_dev *hdev)
 501 {
 502 #define HCLGE_MAC_CMD_NUM 21
 503 #define HCLGE_RTN_DATA_NUM 4
 504
 505         u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
 506         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 507         __le64 *desc_data;
 508         int i, k, n;
 509         int ret;
 510
 511         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 512         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 513         if (ret) {
 514                 dev_err(&hdev->pdev->dev,
 515                         "Get MAC pkt stats fail, status = %d.\n", ret);
 516
 517                 return ret;
 518         }
 519
 520         for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
 521                 if (unlikely(i == 0)) {
 522                         desc_data = (__le64 *)(&desc[i].data[0]);
 523                         n = HCLGE_RTN_DATA_NUM - 2;
 524                 } else {
 525                         desc_data = (__le64 *)(&desc[i]);
 526                         n = HCLGE_RTN_DATA_NUM;
 527                 }
 528                 for (k = 0; k < n; k++) {
 529                         *data++ += le64_to_cpu(*desc_data);
 530                         desc_data++;
 531                 }
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
 538 {
 539         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 540         struct hclge_vport *vport = hclge_get_vport(handle);
 541         struct hclge_dev *hdev = vport->back;
 542         struct hnae3_queue *queue;
 543         struct hclge_desc desc[1];
 544         struct hclge_tqp *tqp;
 545         int ret, i;
 546
 547         for (i = 0; i < kinfo->num_tqps; i++) {
 548                 queue = handle->kinfo.tqp[i];
 549                 tqp = container_of(queue, struct hclge_tqp, q);
 550                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 551                 hclge_cmd_setup_basic_desc(&desc[0],
 552                                            HCLGE_OPC_QUERY_RX_STATUS,
 553                                            true);
 554
 555                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 556                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 557                 if (ret) {
 558                         dev_err(&hdev->pdev->dev,
 559                                 "Query tqp stat fail, status = %d,queue = %d\n",
 560                                 ret,    i);
 561                         return ret;
 562                 }
 563                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 564                         le32_to_cpu(desc[0].data[1]);
 565         }
 566
 567         for (i = 0; i < kinfo->num_tqps; i++) {
 568                 queue = handle->kinfo.tqp[i];
 569                 tqp = container_of(queue, struct hclge_tqp, q);
 570                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 571                 hclge_cmd_setup_basic_desc(&desc[0],
 572                                            HCLGE_OPC_QUERY_TX_STATUS,
 573                                            true);
 574
 575                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 576                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 577                 if (ret) {
 578                         dev_err(&hdev->pdev->dev,
 579                                 "Query tqp stat fail, status = %d,queue = %d\n",
 580                                 ret, i);
 581                         return ret;
 582                 }
 583                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 584                         le32_to_cpu(desc[0].data[1]);
 585         }
 586
 587         return 0;
 588 }
 589
 590 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 591 {
 592         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 593         struct hclge_tqp *tqp;
 594         u64 *buff = data;
 595         int i;
 596
 597         for (i = 0; i < kinfo->num_tqps; i++) {
 598                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 599                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 600         }
 601
 602         for (i = 0; i < kinfo->num_tqps; i++) {
 603                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 604                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 605         }
 606
 607         return buff;
 608 }
 609
 610 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
 611 {
 612         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 613
 614         return kinfo->num_tqps * (2);
 615 }
 616
 617 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 618 {
 619         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 620         u8 *buff = data;
 621         int i = 0;
 622
 623         for (i = 0; i < kinfo->num_tqps; i++) {
 624                 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
 625                         struct hclge_tqp, q);
 626                 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
 627                          tqp->index);
 628                 buff = buff + ETH_GSTRING_LEN;
 629         }
 630
 631         for (i = 0; i < kinfo->num_tqps; i++) {
 632                 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
 633                         struct hclge_tqp, q);
 634                 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
 635                          tqp->index);
 636                 buff = buff + ETH_GSTRING_LEN;
 637         }
 638
 639         return buff;
 640 }
 641
 642 static u64 *hclge_comm_get_stats(void *comm_stats,
 643                                  const struct hclge_comm_stats_str strs[],
 644                                  int size, u64 *data)
 645 {
 646         u64 *buf = data;
 647         u32 i;
 648
 649         for (i = 0; i < size; i++)
 650                 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
 651
 652         return buf + size;
 653 }
 654
 655 static u8 *hclge_comm_get_strings(u32 stringset,
 656                                   const struct hclge_comm_stats_str strs[],
 657                                   int size, u8 *data)
 658 {
 659         char *buff = (char *)data;
 660         u32 i;
 661
 662         if (stringset != ETH_SS_STATS)
 663                 return buff;
 664
 665         for (i = 0; i < size; i++) {
 666                 snprintf(buff, ETH_GSTRING_LEN,
 667                          strs[i].desc);
 668                 buff = buff + ETH_GSTRING_LEN;
 669         }
 670
 671         return (u8 *)buff;
 672 }
 673
 674 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
 675                                  struct net_device_stats *net_stats)
 676 {
 677         net_stats->tx_dropped = 0;
 678         net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
 679         net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
 680         net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
 681
 682         net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 683         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 684         net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
 685         net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
 686         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 687
 688         net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
 689         net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
 690
 691         net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 692         net_stats->rx_length_errors =
 693                 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 694         net_stats->rx_length_errors +=
 695                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 696         net_stats->rx_over_errors =
 697                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 698 }
 699
 700 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 701 {
 702         struct hnae3_handle *handle;
 703         int status;
 704
 705         handle = &hdev->vport[0].nic;
 706         if (handle->client) {
 707                 status = hclge_tqps_update_stats(handle);
 708                 if (status) {
 709                         dev_err(&hdev->pdev->dev,
 710                                 "Update TQPS stats fail, status = %d.\n",
 711                                 status);
 712                 }
 713         }
 714
 715         status = hclge_mac_update_stats(hdev);
 716         if (status)
 717                 dev_err(&hdev->pdev->dev,
 718                         "Update MAC stats fail, status = %d.\n", status);
 719
 720         status = hclge_32_bit_update_stats(hdev);
 721         if (status)
 722                 dev_err(&hdev->pdev->dev,
 723                         "Update 32 bit stats fail, status = %d.\n",
 724                         status);
 725
 726         hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
 727 }
 728
 729 static void hclge_update_stats(struct hnae3_handle *handle,
 730                                struct net_device_stats *net_stats)
 731 {
 732         struct hclge_vport *vport = hclge_get_vport(handle);
 733         struct hclge_dev *hdev = vport->back;
 734         struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
 735         int status;
 736
 737         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 738                 return;
 739
 740         status = hclge_mac_update_stats(hdev);
 741         if (status)
 742                 dev_err(&hdev->pdev->dev,
 743                         "Update MAC stats fail, status = %d.\n",
 744                         status);
 745
 746         status = hclge_32_bit_update_stats(hdev);
 747         if (status)
 748                 dev_err(&hdev->pdev->dev,
 749                         "Update 32 bit stats fail, status = %d.\n",
 750                         status);
 751
 752         status = hclge_64_bit_update_stats(hdev);
 753         if (status)
 754                 dev_err(&hdev->pdev->dev,
 755                         "Update 64 bit stats fail, status = %d.\n",
 756                         status);
 757
 758         status = hclge_tqps_update_stats(handle);
 759         if (status)
 760                 dev_err(&hdev->pdev->dev,
 761                         "Update TQPS stats fail, status = %d.\n",
 762                         status);
 763
 764         hclge_update_netstat(hw_stats, net_stats);
 765
 766         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 767 }
 768
 769 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 770 {
 771 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
 772
 773         struct hclge_vport *vport = hclge_get_vport(handle);
 774         struct hclge_dev *hdev = vport->back;
 775         int count = 0;
 776
 777         /* Loopback test support rules:
 778          * mac: only GE mode support
 779          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 780          * phy: only support when phy device exist on board
 781          */
 782         if (stringset == ETH_SS_TEST) {
 783                 /* clear loopback bit flags at first */
 784                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 785                 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 786                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 787                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 788                         count += 1;
 789                         handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
 790                 }
 791
 792                 count++;
 793                 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
 794         } else if (stringset == ETH_SS_STATS) {
 795                 count = ARRAY_SIZE(g_mac_stats_string) +
 796                         ARRAY_SIZE(g_all_32bit_stats_string) +
 797                         ARRAY_SIZE(g_all_64bit_stats_string) +
 798                         hclge_tqps_get_sset_count(handle, stringset);
 799         }
 800
 801         return count;
 802 }
 803
 804 static void hclge_get_strings(struct hnae3_handle *handle,
 805                               u32 stringset,
 806                               u8 *data)
 807 {
 808         u8 *p = (char *)data;
 809         int size;
 810
 811         if (stringset == ETH_SS_STATS) {
 812                 size = ARRAY_SIZE(g_mac_stats_string);
 813                 p = hclge_comm_get_strings(stringset,
 814                                            g_mac_stats_string,
 815                                            size,
 816                                            p);
 817                 size = ARRAY_SIZE(g_all_32bit_stats_string);
 818                 p = hclge_comm_get_strings(stringset,
 819                                            g_all_32bit_stats_string,
 820                                            size,
 821                                            p);
 822                 size = ARRAY_SIZE(g_all_64bit_stats_string);
 823                 p = hclge_comm_get_strings(stringset,
 824                                            g_all_64bit_stats_string,
 825                                            size,
 826                                            p);
 827                 p = hclge_tqps_get_strings(handle, p);
 828         } else if (stringset == ETH_SS_TEST) {
 829                 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
 830                         memcpy(p,
 831                                hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
 832                                ETH_GSTRING_LEN);
 833                         p += ETH_GSTRING_LEN;
 834                 }
 835                 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
 836                         memcpy(p,
 837                                hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
 838                                ETH_GSTRING_LEN);
 839                         p += ETH_GSTRING_LEN;
 840                 }
 841                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 842                         memcpy(p,
 843                                hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
 844                                ETH_GSTRING_LEN);
 845                         p += ETH_GSTRING_LEN;
 846                 }
 847         }
 848 }
 849
 850 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 851 {
 852         struct hclge_vport *vport = hclge_get_vport(handle);
 853         struct hclge_dev *hdev = vport->back;
 854         u64 *p;
 855
 856         p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
 857                                  g_mac_stats_string,
 858                                  ARRAY_SIZE(g_mac_stats_string),
 859                                  data);
 860         p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
 861                                  g_all_32bit_stats_string,
 862                                  ARRAY_SIZE(g_all_32bit_stats_string),
 863                                  p);
 864         p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
 865                                  g_all_64bit_stats_string,
 866                                  ARRAY_SIZE(g_all_64bit_stats_string),
 867                                  p);
 868         p = hclge_tqps_get_stats(handle, p);
 869 }
 870
 871 static int hclge_parse_func_status(struct hclge_dev *hdev,
 872                                    struct hclge_func_status_cmd *status)
 873 {
 874         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 875                 return -EINVAL;
 876
 877         /* Set the pf to main pf */
 878         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 879                 hdev->flag |= HCLGE_FLAG_MAIN;
 880         else
 881                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 882
 883         return 0;
 884 }
 885
 886 static int hclge_query_function_status(struct hclge_dev *hdev)
 887 {
 888         struct hclge_func_status_cmd *req;
 889         struct hclge_desc desc;
 890         int timeout = 0;
 891         int ret;
 892
 893         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 894         req = (struct hclge_func_status_cmd *)desc.data;
 895
 896         do {
 897                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 898                 if (ret) {
 899                         dev_err(&hdev->pdev->dev,
 900                                 "query function status failed %d.\n",
 901                                 ret);
 902
 903                         return ret;
 904                 }
 905
 906                 /* Check pf reset is done */
 907                 if (req->pf_state)
 908                         break;
 909                 usleep_range(1000, 2000);
 910         } while (timeout++ < 5);
 911
 912         ret = hclge_parse_func_status(hdev, req);
 913
 914         return ret;
 915 }
 916
 917 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 918 {
 919         struct hclge_pf_res_cmd *req;
 920         struct hclge_desc desc;
 921         int ret;
 922
 923         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 924         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 925         if (ret) {
 926                 dev_err(&hdev->pdev->dev,
 927                         "query pf resource failed %d.\n", ret);
 928                 return ret;
 929         }
 930
 931         req = (struct hclge_pf_res_cmd *)desc.data;
 932         hdev->num_tqps = __le16_to_cpu(req->tqp_num);
 933         hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 934
 935         if (hnae3_dev_roce_supported(hdev)) {
 936                 hdev->roce_base_msix_offset =
 937                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
 938                                 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
 939                 hdev->num_roce_msi =
 940                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 941                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 942
 943                 /* PF should have NIC vectors and Roce vectors,
 944                  * NIC vectors are queued before Roce vectors.
 945                  */
 946                 hdev->num_msi = hdev->num_roce_msi  +
 947                                 hdev->roce_base_msix_offset;
 948         } else {
 949                 hdev->num_msi =
 950                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 951                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 952         }
 953
 954         return 0;
 955 }
 956
 957 static int hclge_parse_speed(int speed_cmd, int *speed)
 958 {
 959         switch (speed_cmd) {
 960         case 6:
 961                 *speed = HCLGE_MAC_SPEED_10M;
 962                 break;
 963         case 7:
 964                 *speed = HCLGE_MAC_SPEED_100M;
 965                 break;
 966         case 0:
 967                 *speed = HCLGE_MAC_SPEED_1G;
 968                 break;
 969         case 1:
 970                 *speed = HCLGE_MAC_SPEED_10G;
 971                 break;
 972         case 2:
 973                 *speed = HCLGE_MAC_SPEED_25G;
 974                 break;
 975         case 3:
 976                 *speed = HCLGE_MAC_SPEED_40G;
 977                 break;
 978         case 4:
 979                 *speed = HCLGE_MAC_SPEED_50G;
 980                 break;
 981         case 5:
 982                 *speed = HCLGE_MAC_SPEED_100G;
 983                 break;
 984         default:
 985                 return -EINVAL;
 986         }
 987
 988         return 0;
 989 }
 990
 991 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
 992                                         u8 speed_ability)
 993 {
 994         unsigned long *supported = hdev->hw.mac.supported;
 995
 996         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
 997                 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 998                         supported);
 999
1000         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1001                 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1002                         supported);
1003
1004         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1005                 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1006                         supported);
1007
1008         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1009                 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1010                         supported);
1011
1012         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1013                 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1014                         supported);
1015
1016         set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1017         set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1018 }
1019
1020 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1021 {
1022         u8 media_type = hdev->hw.mac.media_type;
1023
1024         if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1025                 return;
1026
1027         hclge_parse_fiber_link_mode(hdev, speed_ability);
1028 }
1029
1030 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1031 {
1032         struct hclge_cfg_param_cmd *req;
1033         u64 mac_addr_tmp_high;
1034         u64 mac_addr_tmp;
1035         int i;
1036
1037         req = (struct hclge_cfg_param_cmd *)desc[0].data;
1038
1039         /* get the configuration */
1040         cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1041                                               HCLGE_CFG_VMDQ_M,
1042                                               HCLGE_CFG_VMDQ_S);
1043         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1044                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1045         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1046                                             HCLGE_CFG_TQP_DESC_N_M,
1047                                             HCLGE_CFG_TQP_DESC_N_S);
1048
1049         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1050                                         HCLGE_CFG_PHY_ADDR_M,
1051                                         HCLGE_CFG_PHY_ADDR_S);
1052         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1053                                           HCLGE_CFG_MEDIA_TP_M,
1054                                           HCLGE_CFG_MEDIA_TP_S);
1055         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1056                                           HCLGE_CFG_RX_BUF_LEN_M,
1057                                           HCLGE_CFG_RX_BUF_LEN_S);
1058         /* get mac_address */
1059         mac_addr_tmp = __le32_to_cpu(req->param[2]);
1060         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1061                                             HCLGE_CFG_MAC_ADDR_H_M,
1062                                             HCLGE_CFG_MAC_ADDR_H_S);
1063
1064         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1065
1066         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1067                                              HCLGE_CFG_DEFAULT_SPEED_M,
1068                                              HCLGE_CFG_DEFAULT_SPEED_S);
1069         cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1070                                             HCLGE_CFG_RSS_SIZE_M,
1071                                             HCLGE_CFG_RSS_SIZE_S);
1072
1073         for (i = 0; i < ETH_ALEN; i++)
1074                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1075
1076         req = (struct hclge_cfg_param_cmd *)desc[1].data;
1077         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1078
1079         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1080                                              HCLGE_CFG_SPEED_ABILITY_M,
1081                                              HCLGE_CFG_SPEED_ABILITY_S);
1082 }
1083
1084 /* hclge_get_cfg: query the static parameter from flash
1085  * @hdev: pointer to struct hclge_dev
1086  * @hcfg: the config structure to be getted
1087  */
1088 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1089 {
1090         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1091         struct hclge_cfg_param_cmd *req;
1092         int i, ret;
1093
1094         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1095                 u32 offset = 0;
1096
1097                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1098                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1099                                            true);
1100                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1101                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1102                 /* Len should be united by 4 bytes when send to hardware */
1103                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1104                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1105                 req->offset = cpu_to_le32(offset);
1106         }
1107
1108         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1109         if (ret) {
1110                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1111                 return ret;
1112         }
1113
1114         hclge_parse_cfg(hcfg, desc);
1115
1116         return 0;
1117 }
1118
1119 static int hclge_get_cap(struct hclge_dev *hdev)
1120 {
1121         int ret;
1122
1123         ret = hclge_query_function_status(hdev);
1124         if (ret) {
1125                 dev_err(&hdev->pdev->dev,
1126                         "query function status error %d.\n", ret);
1127                 return ret;
1128         }
1129
1130         /* get pf resource */
1131         ret = hclge_query_pf_resource(hdev);
1132         if (ret)
1133                 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
1134
1135         return ret;
1136 }
1137
1138 static int hclge_configure(struct hclge_dev *hdev)
1139 {
1140         struct hclge_cfg cfg;
1141         int ret, i;
1142
1143         ret = hclge_get_cfg(hdev, &cfg);
1144         if (ret) {
1145                 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1146                 return ret;
1147         }
1148
1149         hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1150         hdev->base_tqp_pid = 0;
1151         hdev->rss_size_max = cfg.rss_size_max;
1152         hdev->rx_buf_len = cfg.rx_buf_len;
1153         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1154         hdev->hw.mac.media_type = cfg.media_type;
1155         hdev->hw.mac.phy_addr = cfg.phy_addr;
1156         hdev->num_desc = cfg.tqp_desc_num;
1157         hdev->tm_info.num_pg = 1;
1158         hdev->tc_max = cfg.tc_num;
1159         hdev->tm_info.hw_pfc_map = 0;
1160
1161         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1162         if (ret) {
1163                 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1164                 return ret;
1165         }
1166
1167         hclge_parse_link_mode(hdev, cfg.speed_ability);
1168
1169         if ((hdev->tc_max > HNAE3_MAX_TC) ||
1170             (hdev->tc_max < 1)) {
1171                 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1172                          hdev->tc_max);
1173                 hdev->tc_max = 1;
1174         }
1175
1176         /* Dev does not support DCB */
1177         if (!hnae3_dev_dcb_supported(hdev)) {
1178                 hdev->tc_max = 1;
1179                 hdev->pfc_max = 0;
1180         } else {
1181                 hdev->pfc_max = hdev->tc_max;
1182         }
1183
1184         hdev->tm_info.num_tc = hdev->tc_max;
1185
1186         /* Currently not support uncontiuous tc */
1187         for (i = 0; i < hdev->tm_info.num_tc; i++)
1188                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1189
1190         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1191
1192         return ret;
1193 }
1194
1195 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1196                             int tso_mss_max)
1197 {
1198         struct hclge_cfg_tso_status_cmd *req;
1199         struct hclge_desc desc;
1200         u16 tso_mss;
1201
1202         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1203
1204         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1205
1206         tso_mss = 0;
1207         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1208                         HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1209         req->tso_mss_min = cpu_to_le16(tso_mss);
1210
1211         tso_mss = 0;
1212         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1213                         HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1214         req->tso_mss_max = cpu_to_le16(tso_mss);
1215
1216         return hclge_cmd_send(&hdev->hw, &desc, 1);
1217 }
1218
1219 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1220 {
1221         struct hclge_tqp *tqp;
1222         int i;
1223
1224         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1225                                   sizeof(struct hclge_tqp), GFP_KERNEL);
1226         if (!hdev->htqp)
1227                 return -ENOMEM;
1228
1229         tqp = hdev->htqp;
1230
1231         for (i = 0; i < hdev->num_tqps; i++) {
1232                 tqp->dev = &hdev->pdev->dev;
1233                 tqp->index = i;
1234
1235                 tqp->q.ae_algo = &ae_algo;
1236                 tqp->q.buf_size = hdev->rx_buf_len;
1237                 tqp->q.desc_num = hdev->num_desc;
1238                 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1239                         i * HCLGE_TQP_REG_SIZE;
1240
1241                 tqp++;
1242         }
1243
1244         return 0;
1245 }
1246
1247 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1248                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
1249 {
1250         struct hclge_tqp_map_cmd *req;
1251         struct hclge_desc desc;
1252         int ret;
1253
1254         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1255
1256         req = (struct hclge_tqp_map_cmd *)desc.data;
1257         req->tqp_id = cpu_to_le16(tqp_pid);
1258         req->tqp_vf = func_id;
1259         req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1260                         1 << HCLGE_TQP_MAP_EN_B;
1261         req->tqp_vid = cpu_to_le16(tqp_vid);
1262
1263         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1264         if (ret)
1265                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1266
1267         return ret;
1268 }
1269
1270 static int  hclge_assign_tqp(struct hclge_vport *vport)
1271 {
1272         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1273         struct hclge_dev *hdev = vport->back;
1274         int i, alloced;
1275
1276         for (i = 0, alloced = 0; i < hdev->num_tqps &&
1277              alloced < kinfo->num_tqps; i++) {
1278                 if (!hdev->htqp[i].alloced) {
1279                         hdev->htqp[i].q.handle = &vport->nic;
1280                         hdev->htqp[i].q.tqp_index = alloced;
1281                         hdev->htqp[i].q.desc_num = kinfo->num_desc;
1282                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
1283                         hdev->htqp[i].alloced = true;
1284                         alloced++;
1285                 }
1286         }
1287         vport->alloc_tqps = kinfo->num_tqps;
1288
1289         return 0;
1290 }
1291
1292 static int hclge_knic_setup(struct hclge_vport *vport,
1293                             u16 num_tqps, u16 num_desc)
1294 {
1295         struct hnae3_handle *nic = &vport->nic;
1296         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1297         struct hclge_dev *hdev = vport->back;
1298         int i, ret;
1299
1300         kinfo->num_desc = num_desc;
1301         kinfo->rx_buf_len = hdev->rx_buf_len;
1302         kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1303         kinfo->rss_size
1304                 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1305         kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1306
1307         for (i = 0; i < HNAE3_MAX_TC; i++) {
1308                 if (hdev->hw_tc_map & BIT(i)) {
1309                         kinfo->tc_info[i].enable = true;
1310                         kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1311                         kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1312                         kinfo->tc_info[i].tc = i;
1313                 } else {
1314                         /* Set to default queue if TC is disable */
1315                         kinfo->tc_info[i].enable = false;
1316                         kinfo->tc_info[i].tqp_offset = 0;
1317                         kinfo->tc_info[i].tqp_count = 1;
1318                         kinfo->tc_info[i].tc = 0;
1319                 }
1320         }
1321
1322         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1323                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1324         if (!kinfo->tqp)
1325                 return -ENOMEM;
1326
1327         ret = hclge_assign_tqp(vport);
1328         if (ret)
1329                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1330
1331         return ret;
1332 }
1333
1334 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1335                                   struct hclge_vport *vport)
1336 {
1337         struct hnae3_handle *nic = &vport->nic;
1338         struct hnae3_knic_private_info *kinfo;
1339         u16 i;
1340
1341         kinfo = &nic->kinfo;
1342         for (i = 0; i < kinfo->num_tqps; i++) {
1343                 struct hclge_tqp *q =
1344                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
1345                 bool is_pf;
1346                 int ret;
1347
1348                 is_pf = !(vport->vport_id);
1349                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1350                                              i, is_pf);
1351                 if (ret)
1352                         return ret;
1353         }
1354
1355         return 0;
1356 }
1357
1358 static int hclge_map_tqp(struct hclge_dev *hdev)
1359 {
1360         struct hclge_vport *vport = hdev->vport;
1361         u16 i, num_vport;
1362
1363         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1364         for (i = 0; i < num_vport; i++) {
1365                 int ret;
1366
1367                 ret = hclge_map_tqp_to_vport(hdev, vport);
1368                 if (ret)
1369                         return ret;
1370
1371                 vport++;
1372         }
1373
1374         return 0;
1375 }
1376
1377 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1378 {
1379         /* this would be initialized later */
1380 }
1381
1382 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1383 {
1384         struct hnae3_handle *nic = &vport->nic;
1385         struct hclge_dev *hdev = vport->back;
1386         int ret;
1387
1388         nic->pdev = hdev->pdev;
1389         nic->ae_algo = &ae_algo;
1390         nic->numa_node_mask = hdev->numa_node_mask;
1391
1392         if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1393                 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
1394                 if (ret) {
1395                         dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1396                                 ret);
1397                         return ret;
1398                 }
1399         } else {
1400                 hclge_unic_setup(vport, num_tqps);
1401         }
1402
1403         return 0;
1404 }
1405
1406 static int hclge_alloc_vport(struct hclge_dev *hdev)
1407 {
1408         struct pci_dev *pdev = hdev->pdev;
1409         struct hclge_vport *vport;
1410         u32 tqp_main_vport;
1411         u32 tqp_per_vport;
1412         int num_vport, i;
1413         int ret;
1414
1415         /* We need to alloc a vport for main NIC of PF */
1416         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1417
1418         if (hdev->num_tqps < num_vport) {
1419                 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1420                         hdev->num_tqps, num_vport);
1421                 return -EINVAL;
1422         }
1423
1424         /* Alloc the same number of TQPs for every vport */
1425         tqp_per_vport = hdev->num_tqps / num_vport;
1426         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1427
1428         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1429                              GFP_KERNEL);
1430         if (!vport)
1431                 return -ENOMEM;
1432
1433         hdev->vport = vport;
1434         hdev->num_alloc_vport = num_vport;
1435
1436         if (IS_ENABLED(CONFIG_PCI_IOV))
1437                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1438
1439         for (i = 0; i < num_vport; i++) {
1440                 vport->back = hdev;
1441                 vport->vport_id = i;
1442
1443                 if (i == 0)
1444                         ret = hclge_vport_setup(vport, tqp_main_vport);
1445                 else
1446                         ret = hclge_vport_setup(vport, tqp_per_vport);
1447                 if (ret) {
1448                         dev_err(&pdev->dev,
1449                                 "vport setup failed for vport %d, %d\n",
1450                                 i, ret);
1451                         return ret;
1452                 }
1453
1454                 vport++;
1455         }
1456
1457         return 0;
1458 }
1459
1460 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1461                                     struct hclge_pkt_buf_alloc *buf_alloc)
1462 {
1463 /* TX buffer size is unit by 128 byte */
1464 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1465 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1466         struct hclge_tx_buff_alloc_cmd *req;
1467         struct hclge_desc desc;
1468         int ret;
1469         u8 i;
1470
1471         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1472
1473         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1474         for (i = 0; i < HCLGE_TC_NUM; i++) {
1475                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1476
1477                 req->tx_pkt_buff[i] =
1478                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1479                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1480         }
1481
1482         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1483         if (ret)
1484                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1485                         ret);
1486
1487         return ret;
1488 }
1489
1490 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1491                                  struct hclge_pkt_buf_alloc *buf_alloc)
1492 {
1493         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1494
1495         if (ret)
1496                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1497
1498         return ret;
1499 }
1500
1501 static int hclge_get_tc_num(struct hclge_dev *hdev)
1502 {
1503         int i, cnt = 0;
1504
1505         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1506                 if (hdev->hw_tc_map & BIT(i))
1507                         cnt++;
1508         return cnt;
1509 }
1510
1511 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1512 {
1513         int i, cnt = 0;
1514
1515         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1516                 if (hdev->hw_tc_map & BIT(i) &&
1517                     hdev->tm_info.hw_pfc_map & BIT(i))
1518                         cnt++;
1519         return cnt;
1520 }
1521
1522 /* Get the number of pfc enabled TCs, which have private buffer */
1523 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1524                                   struct hclge_pkt_buf_alloc *buf_alloc)
1525 {
1526         struct hclge_priv_buf *priv;
1527         int i, cnt = 0;
1528
1529         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1530                 priv = &buf_alloc->priv_buf[i];
1531                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1532                     priv->enable)
1533                         cnt++;
1534         }
1535
1536         return cnt;
1537 }
1538
1539 /* Get the number of pfc disabled TCs, which have private buffer */
1540 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1541                                      struct hclge_pkt_buf_alloc *buf_alloc)
1542 {
1543         struct hclge_priv_buf *priv;
1544         int i, cnt = 0;
1545
1546         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1547                 priv = &buf_alloc->priv_buf[i];
1548                 if (hdev->hw_tc_map & BIT(i) &&
1549                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1550                     priv->enable)
1551                         cnt++;
1552         }
1553
1554         return cnt;
1555 }
1556
1557 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1558 {
1559         struct hclge_priv_buf *priv;
1560         u32 rx_priv = 0;
1561         int i;
1562
1563         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1564                 priv = &buf_alloc->priv_buf[i];
1565                 if (priv->enable)
1566                         rx_priv += priv->buf_size;
1567         }
1568         return rx_priv;
1569 }
1570
1571 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1572 {
1573         u32 i, total_tx_size = 0;
1574
1575         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1576                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1577
1578         return total_tx_size;
1579 }
1580
1581 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1582                                 struct hclge_pkt_buf_alloc *buf_alloc,
1583                                 u32 rx_all)
1584 {
1585         u32 shared_buf_min, shared_buf_tc, shared_std;
1586         int tc_num, pfc_enable_num;
1587         u32 shared_buf;
1588         u32 rx_priv;
1589         int i;
1590
1591         tc_num = hclge_get_tc_num(hdev);
1592         pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1593
1594         if (hnae3_dev_dcb_supported(hdev))
1595                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1596         else
1597                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1598
1599         shared_buf_tc = pfc_enable_num * hdev->mps +
1600                         (tc_num - pfc_enable_num) * hdev->mps / 2 +
1601                         hdev->mps;
1602         shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1603
1604         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1605         if (rx_all <= rx_priv + shared_std)
1606                 return false;
1607
1608         shared_buf = rx_all - rx_priv;
1609         buf_alloc->s_buf.buf_size = shared_buf;
1610         buf_alloc->s_buf.self.high = shared_buf;
1611         buf_alloc->s_buf.self.low =  2 * hdev->mps;
1612
1613         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1614                 if ((hdev->hw_tc_map & BIT(i)) &&
1615                     (hdev->tm_info.hw_pfc_map & BIT(i))) {
1616                         buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1617                         buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1618                 } else {
1619                         buf_alloc->s_buf.tc_thrd[i].low = 0;
1620                         buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1621                 }
1622         }
1623
1624         return true;
1625 }
1626
1627 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1628                                 struct hclge_pkt_buf_alloc *buf_alloc)
1629 {
1630         u32 i, total_size;
1631
1632         total_size = hdev->pkt_buf_size;
1633
1634         /* alloc tx buffer for all enabled tc */
1635         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1636                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1637
1638                 if (total_size < HCLGE_DEFAULT_TX_BUF)
1639                         return -ENOMEM;
1640
1641                 if (hdev->hw_tc_map & BIT(i))
1642                         priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1643                 else
1644                         priv->tx_buf_size = 0;
1645
1646                 total_size -= priv->tx_buf_size;
1647         }
1648
1649         return 0;
1650 }
1651
1652 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1653  * @hdev: pointer to struct hclge_dev
1654  * @buf_alloc: pointer to buffer calculation data
1655  * @return: 0: calculate sucessful, negative: fail
1656  */
1657 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1658                                 struct hclge_pkt_buf_alloc *buf_alloc)
1659 {
1660         u32 rx_all = hdev->pkt_buf_size;
1661         int no_pfc_priv_num, pfc_priv_num;
1662         struct hclge_priv_buf *priv;
1663         int i;
1664
1665         rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1666
1667         /* When DCB is not supported, rx private
1668          * buffer is not allocated.
1669          */
1670         if (!hnae3_dev_dcb_supported(hdev)) {
1671                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1672                         return -ENOMEM;
1673
1674                 return 0;
1675         }
1676
1677         /* step 1, try to alloc private buffer for all enabled tc */
1678         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1679                 priv = &buf_alloc->priv_buf[i];
1680                 if (hdev->hw_tc_map & BIT(i)) {
1681                         priv->enable = 1;
1682                         if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1683                                 priv->wl.low = hdev->mps;
1684                                 priv->wl.high = priv->wl.low + hdev->mps;
1685                                 priv->buf_size = priv->wl.high +
1686                                                 HCLGE_DEFAULT_DV;
1687                         } else {
1688                                 priv->wl.low = 0;
1689                                 priv->wl.high = 2 * hdev->mps;
1690                                 priv->buf_size = priv->wl.high;
1691                         }
1692                 } else {
1693                         priv->enable = 0;
1694                         priv->wl.low = 0;
1695                         priv->wl.high = 0;
1696                         priv->buf_size = 0;
1697                 }
1698         }
1699
1700         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1701                 return 0;
1702
1703         /* step 2, try to decrease the buffer size of
1704          * no pfc TC's private buffer
1705          */
1706         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1707                 priv = &buf_alloc->priv_buf[i];
1708
1709                 priv->enable = 0;
1710                 priv->wl.low = 0;
1711                 priv->wl.high = 0;
1712                 priv->buf_size = 0;
1713
1714                 if (!(hdev->hw_tc_map & BIT(i)))
1715                         continue;
1716
1717                 priv->enable = 1;
1718
1719                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1720                         priv->wl.low = 128;
1721                         priv->wl.high = priv->wl.low + hdev->mps;
1722                         priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1723                 } else {
1724                         priv->wl.low = 0;
1725                         priv->wl.high = hdev->mps;
1726                         priv->buf_size = priv->wl.high;
1727                 }
1728         }
1729
1730         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1731                 return 0;
1732
1733         /* step 3, try to reduce the number of pfc disabled TCs,
1734          * which have private buffer
1735          */
1736         /* get the total no pfc enable TC number, which have private buffer */
1737         no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1738
1739         /* let the last to be cleared first */
1740         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1741                 priv = &buf_alloc->priv_buf[i];
1742
1743                 if (hdev->hw_tc_map & BIT(i) &&
1744                     !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1745                         /* Clear the no pfc TC private buffer */
1746                         priv->wl.low = 0;
1747                         priv->wl.high = 0;
1748                         priv->buf_size = 0;
1749                         priv->enable = 0;
1750                         no_pfc_priv_num--;
1751                 }
1752
1753                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1754                     no_pfc_priv_num == 0)
1755                         break;
1756         }
1757
1758         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1759                 return 0;
1760
1761         /* step 4, try to reduce the number of pfc enabled TCs
1762          * which have private buffer.
1763          */
1764         pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1765
1766         /* let the last to be cleared first */
1767         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1768                 priv = &buf_alloc->priv_buf[i];
1769
1770                 if (hdev->hw_tc_map & BIT(i) &&
1771                     hdev->tm_info.hw_pfc_map & BIT(i)) {
1772                         /* Reduce the number of pfc TC with private buffer */
1773                         priv->wl.low = 0;
1774                         priv->enable = 0;
1775                         priv->wl.high = 0;
1776                         priv->buf_size = 0;
1777                         pfc_priv_num--;
1778                 }
1779
1780                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1781                     pfc_priv_num == 0)
1782                         break;
1783         }
1784         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1785                 return 0;
1786
1787         return -ENOMEM;
1788 }
1789
1790 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1791                                    struct hclge_pkt_buf_alloc *buf_alloc)
1792 {
1793         struct hclge_rx_priv_buff_cmd *req;
1794         struct hclge_desc desc;
1795         int ret;
1796         int i;
1797
1798         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1799         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1800
1801         /* Alloc private buffer TCs */
1802         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1803                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1804
1805                 req->buf_num[i] =
1806                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1807                 req->buf_num[i] |=
1808                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1809         }
1810
1811         req->shared_buf =
1812                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1813                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
1814
1815         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1816         if (ret)
1817                 dev_err(&hdev->pdev->dev,
1818                         "rx private buffer alloc cmd failed %d\n", ret);
1819
1820         return ret;
1821 }
1822
1823 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1824                                    struct hclge_pkt_buf_alloc *buf_alloc)
1825 {
1826         struct hclge_rx_priv_wl_buf *req;
1827         struct hclge_priv_buf *priv;
1828         struct hclge_desc desc[2];
1829         int i, j;
1830         int ret;
1831
1832         for (i = 0; i < 2; i++) {
1833                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1834                                            false);
1835                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1836
1837                 /* The first descriptor set the NEXT bit to 1 */
1838                 if (i == 0)
1839                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1840                 else
1841                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1842
1843                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1844                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1845
1846                         priv = &buf_alloc->priv_buf[idx];
1847                         req->tc_wl[j].high =
1848                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1849                         req->tc_wl[j].high |=
1850                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1851                         req->tc_wl[j].low =
1852                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1853                         req->tc_wl[j].low |=
1854                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1855                 }
1856         }
1857
1858         /* Send 2 descriptor at one time */
1859         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1860         if (ret)
1861                 dev_err(&hdev->pdev->dev,
1862                         "rx private waterline config cmd failed %d\n",
1863                         ret);
1864         return ret;
1865 }
1866
1867 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1868                                     struct hclge_pkt_buf_alloc *buf_alloc)
1869 {
1870         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1871         struct hclge_rx_com_thrd *req;
1872         struct hclge_desc desc[2];
1873         struct hclge_tc_thrd *tc;
1874         int i, j;
1875         int ret;
1876
1877         for (i = 0; i < 2; i++) {
1878                 hclge_cmd_setup_basic_desc(&desc[i],
1879                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1880                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1881
1882                 /* The first descriptor set the NEXT bit to 1 */
1883                 if (i == 0)
1884                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1885                 else
1886                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1887
1888                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1889                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1890
1891                         req->com_thrd[j].high =
1892                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1893                         req->com_thrd[j].high |=
1894                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1895                         req->com_thrd[j].low =
1896                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1897                         req->com_thrd[j].low |=
1898                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1899                 }
1900         }
1901
1902         /* Send 2 descriptors at one time */
1903         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1904         if (ret)
1905                 dev_err(&hdev->pdev->dev,
1906                         "common threshold config cmd failed %d\n", ret);
1907         return ret;
1908 }
1909
1910 static int hclge_common_wl_config(struct hclge_dev *hdev,
1911                                   struct hclge_pkt_buf_alloc *buf_alloc)
1912 {
1913         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1914         struct hclge_rx_com_wl *req;
1915         struct hclge_desc desc;
1916         int ret;
1917
1918         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1919
1920         req = (struct hclge_rx_com_wl *)desc.data;
1921         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1922         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1923
1924         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1925         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1926
1927         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1928         if (ret)
1929                 dev_err(&hdev->pdev->dev,
1930                         "common waterline config cmd failed %d\n", ret);
1931
1932         return ret;
1933 }
1934
1935 int hclge_buffer_alloc(struct hclge_dev *hdev)
1936 {
1937         struct hclge_pkt_buf_alloc *pkt_buf;
1938         int ret;
1939
1940         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1941         if (!pkt_buf)
1942                 return -ENOMEM;
1943
1944         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1945         if (ret) {
1946                 dev_err(&hdev->pdev->dev,
1947                         "could not calc tx buffer size for all TCs %d\n", ret);
1948                 goto out;
1949         }
1950
1951         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1952         if (ret) {
1953                 dev_err(&hdev->pdev->dev,
1954                         "could not alloc tx buffers %d\n", ret);
1955                 goto out;
1956         }
1957
1958         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1959         if (ret) {
1960                 dev_err(&hdev->pdev->dev,
1961                         "could not calc rx priv buffer size for all TCs %d\n",
1962                         ret);
1963                 goto out;
1964         }
1965
1966         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1967         if (ret) {
1968                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1969                         ret);
1970                 goto out;
1971         }
1972
1973         if (hnae3_dev_dcb_supported(hdev)) {
1974                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1975                 if (ret) {
1976                         dev_err(&hdev->pdev->dev,
1977                                 "could not configure rx private waterline %d\n",
1978                                 ret);
1979                         goto out;
1980                 }
1981
1982                 ret = hclge_common_thrd_config(hdev, pkt_buf);
1983                 if (ret) {
1984                         dev_err(&hdev->pdev->dev,
1985                                 "could not configure common threshold %d\n",
1986                                 ret);
1987                         goto out;
1988                 }
1989         }
1990
1991         ret = hclge_common_wl_config(hdev, pkt_buf);
1992         if (ret)
1993                 dev_err(&hdev->pdev->dev,
1994                         "could not configure common waterline %d\n", ret);
1995
1996 out:
1997         kfree(pkt_buf);
1998         return ret;
1999 }
2000
2001 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2002 {
2003         struct hnae3_handle *roce = &vport->roce;
2004         struct hnae3_handle *nic = &vport->nic;
2005
2006         roce->rinfo.num_vectors = vport->back->num_roce_msi;
2007
2008         if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2009             vport->back->num_msi_left == 0)
2010                 return -EINVAL;
2011
2012         roce->rinfo.base_vector = vport->back->roce_base_vector;
2013
2014         roce->rinfo.netdev = nic->kinfo.netdev;
2015         roce->rinfo.roce_io_base = vport->back->hw.io_base;
2016
2017         roce->pdev = nic->pdev;
2018         roce->ae_algo = nic->ae_algo;
2019         roce->numa_node_mask = nic->numa_node_mask;
2020
2021         return 0;
2022 }
2023
2024 static int hclge_init_msi(struct hclge_dev *hdev)
2025 {
2026         struct pci_dev *pdev = hdev->pdev;
2027         int vectors;
2028         int i;
2029
2030         vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2031                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
2032         if (vectors < 0) {
2033                 dev_err(&pdev->dev,
2034                         "failed(%d) to allocate MSI/MSI-X vectors\n",
2035                         vectors);
2036                 return vectors;
2037         }
2038         if (vectors < hdev->num_msi)
2039                 dev_warn(&hdev->pdev->dev,
2040                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2041                          hdev->num_msi, vectors);
2042
2043         hdev->num_msi = vectors;
2044         hdev->num_msi_left = vectors;
2045         hdev->base_msi_vector = pdev->irq;
2046         hdev->roce_base_vector = hdev->base_msi_vector +
2047                                 hdev->roce_base_msix_offset;
2048
2049         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2050                                            sizeof(u16), GFP_KERNEL);
2051         if (!hdev->vector_status) {
2052                 pci_free_irq_vectors(pdev);
2053                 return -ENOMEM;
2054         }
2055
2056         for (i = 0; i < hdev->num_msi; i++)
2057                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2058
2059         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2060                                         sizeof(int), GFP_KERNEL);
2061         if (!hdev->vector_irq) {
2062                 pci_free_irq_vectors(pdev);
2063                 return -ENOMEM;
2064         }
2065
2066         return 0;
2067 }
2068
2069 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2070 {
2071         struct hclge_mac *mac = &hdev->hw.mac;
2072
2073         if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2074                 mac->duplex = (u8)duplex;
2075         else
2076                 mac->duplex = HCLGE_MAC_FULL;
2077
2078         mac->speed = speed;
2079 }
2080
2081 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2082 {
2083         struct hclge_config_mac_speed_dup_cmd *req;
2084         struct hclge_desc desc;
2085         int ret;
2086
2087         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2088
2089         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2090
2091         hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2092
2093         switch (speed) {
2094         case HCLGE_MAC_SPEED_10M:
2095                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2096                                 HCLGE_CFG_SPEED_S, 6);
2097                 break;
2098         case HCLGE_MAC_SPEED_100M:
2099                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2100                                 HCLGE_CFG_SPEED_S, 7);
2101                 break;
2102         case HCLGE_MAC_SPEED_1G:
2103                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2104                                 HCLGE_CFG_SPEED_S, 0);
2105                 break;
2106         case HCLGE_MAC_SPEED_10G:
2107                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2108                                 HCLGE_CFG_SPEED_S, 1);
2109                 break;
2110         case HCLGE_MAC_SPEED_25G:
2111                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2112                                 HCLGE_CFG_SPEED_S, 2);
2113                 break;
2114         case HCLGE_MAC_SPEED_40G:
2115                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2116                                 HCLGE_CFG_SPEED_S, 3);
2117                 break;
2118         case HCLGE_MAC_SPEED_50G:
2119                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2120                                 HCLGE_CFG_SPEED_S, 4);
2121                 break;
2122         case HCLGE_MAC_SPEED_100G:
2123                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2124                                 HCLGE_CFG_SPEED_S, 5);
2125                 break;
2126         default:
2127                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2128                 return -EINVAL;
2129         }
2130
2131         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2132                       1);
2133
2134         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2135         if (ret) {
2136                 dev_err(&hdev->pdev->dev,
2137                         "mac speed/duplex config cmd failed %d.\n", ret);
2138                 return ret;
2139         }
2140
2141         hclge_check_speed_dup(hdev, duplex, speed);
2142
2143         return 0;
2144 }
2145
2146 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2147                                      u8 duplex)
2148 {
2149         struct hclge_vport *vport = hclge_get_vport(handle);
2150         struct hclge_dev *hdev = vport->back;
2151
2152         return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2153 }
2154
2155 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2156                                         u8 *duplex)
2157 {
2158         struct hclge_query_an_speed_dup_cmd *req;
2159         struct hclge_desc desc;
2160         int speed_tmp;
2161         int ret;
2162
2163         req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2164
2165         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2166         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2167         if (ret) {
2168                 dev_err(&hdev->pdev->dev,
2169                         "mac speed/autoneg/duplex query cmd failed %d\n",
2170                         ret);
2171                 return ret;
2172         }
2173
2174         *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2175         speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2176                                     HCLGE_QUERY_SPEED_S);
2177
2178         ret = hclge_parse_speed(speed_tmp, speed);
2179         if (ret)
2180                 dev_err(&hdev->pdev->dev,
2181                         "could not parse speed(=%d), %d\n", speed_tmp, ret);
2182
2183         return ret;
2184 }
2185
2186 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2187 {
2188         struct hclge_config_auto_neg_cmd *req;
2189         struct hclge_desc desc;
2190         u32 flag = 0;
2191         int ret;
2192
2193         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2194
2195         req = (struct hclge_config_auto_neg_cmd *)desc.data;
2196         hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2197         req->cfg_an_cmd_flag = cpu_to_le32(flag);
2198
2199         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2200         if (ret)
2201                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2202                         ret);
2203
2204         return ret;
2205 }
2206
2207 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2208 {
2209         struct hclge_vport *vport = hclge_get_vport(handle);
2210         struct hclge_dev *hdev = vport->back;
2211
2212         return hclge_set_autoneg_en(hdev, enable);
2213 }
2214
2215 static int hclge_get_autoneg(struct hnae3_handle *handle)
2216 {
2217         struct hclge_vport *vport = hclge_get_vport(handle);
2218         struct hclge_dev *hdev = vport->back;
2219         struct phy_device *phydev = hdev->hw.mac.phydev;
2220
2221         if (phydev)
2222                 return phydev->autoneg;
2223
2224         return hdev->hw.mac.autoneg;
2225 }
2226
2227 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2228                                            bool mask_vlan,
2229                                            u8 *mac_mask)
2230 {
2231         struct hclge_mac_vlan_mask_entry_cmd *req;
2232         struct hclge_desc desc;
2233         int status;
2234
2235         req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2236         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2237
2238         hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2239                       mask_vlan ? 1 : 0);
2240         ether_addr_copy(req->mac_mask, mac_mask);
2241
2242         status = hclge_cmd_send(&hdev->hw, &desc, 1);
2243         if (status)
2244                 dev_err(&hdev->pdev->dev,
2245                         "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2246                         status);
2247
2248         return status;
2249 }
2250
2251 static int hclge_mac_init(struct hclge_dev *hdev)
2252 {
2253         struct hnae3_handle *handle = &hdev->vport[0].nic;
2254         struct net_device *netdev = handle->kinfo.netdev;
2255         struct hclge_mac *mac = &hdev->hw.mac;
2256         u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2257         struct hclge_vport *vport;
2258         int mtu;
2259         int ret;
2260         int i;
2261
2262         ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2263         if (ret) {
2264                 dev_err(&hdev->pdev->dev,
2265                         "Config mac speed dup fail ret=%d\n", ret);
2266                 return ret;
2267         }
2268
2269         mac->link = 0;
2270
2271         /* Initialize the MTA table work mode */
2272         hdev->enable_mta        = true;
2273         hdev->mta_mac_sel_type  = HCLGE_MAC_ADDR_47_36;
2274
2275         ret = hclge_set_mta_filter_mode(hdev,
2276                                         hdev->mta_mac_sel_type,
2277                                         hdev->enable_mta);
2278         if (ret) {
2279                 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2280                         ret);
2281                 return ret;
2282         }
2283
2284         for (i = 0; i < hdev->num_alloc_vport; i++) {
2285                 vport = &hdev->vport[i];
2286                 vport->accept_mta_mc = false;
2287
2288                 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2289                 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2290                 if (ret) {
2291                         dev_err(&hdev->pdev->dev,
2292                                 "set mta filter mode fail ret=%d\n", ret);
2293                         return ret;
2294                 }
2295         }
2296
2297         ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2298         if (ret) {
2299                 dev_err(&hdev->pdev->dev,
2300                         "set default mac_vlan_mask fail ret=%d\n", ret);
2301                 return ret;
2302         }
2303
2304         if (netdev)
2305                 mtu = netdev->mtu;
2306         else
2307                 mtu = ETH_DATA_LEN;
2308
2309         ret = hclge_set_mtu(handle, mtu);
2310         if (ret)
2311                 dev_err(&hdev->pdev->dev,
2312                         "set mtu failed ret=%d\n", ret);
2313
2314         return ret;
2315 }
2316
2317 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2318 {
2319         if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2320                 schedule_work(&hdev->mbx_service_task);
2321 }
2322
2323 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2324 {
2325         if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2326                 schedule_work(&hdev->rst_service_task);
2327 }
2328
2329 static void hclge_task_schedule(struct hclge_dev *hdev)
2330 {
2331         if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2332             !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2333             !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2334                 (void)schedule_work(&hdev->service_task);
2335 }
2336
2337 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2338 {
2339         struct hclge_link_status_cmd *req;
2340         struct hclge_desc desc;
2341         int link_status;
2342         int ret;
2343
2344         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2345         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2346         if (ret) {
2347                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2348                         ret);
2349                 return ret;
2350         }
2351
2352         req = (struct hclge_link_status_cmd *)desc.data;
2353         link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2354
2355         return !!link_status;
2356 }
2357
2358 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2359 {
2360         int mac_state;
2361         int link_stat;
2362
2363         mac_state = hclge_get_mac_link_status(hdev);
2364
2365         if (hdev->hw.mac.phydev) {
2366                 if (!genphy_read_status(hdev->hw.mac.phydev))
2367                         link_stat = mac_state &
2368                                 hdev->hw.mac.phydev->link;
2369                 else
2370                         link_stat = 0;
2371
2372         } else {
2373                 link_stat = mac_state;
2374         }
2375
2376         return !!link_stat;
2377 }
2378
2379 static void hclge_update_link_status(struct hclge_dev *hdev)
2380 {
2381         struct hnae3_client *client = hdev->nic_client;
2382         struct hnae3_handle *handle;
2383         int state;
2384         int i;
2385
2386         if (!client)
2387                 return;
2388         state = hclge_get_mac_phy_link(hdev);
2389         if (state != hdev->hw.mac.link) {
2390                 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2391                         handle = &hdev->vport[i].nic;
2392                         client->ops->link_status_change(handle, state);
2393                 }
2394                 hdev->hw.mac.link = state;
2395         }
2396 }
2397
2398 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2399 {
2400         struct hclge_mac mac = hdev->hw.mac;
2401         u8 duplex;
2402         int speed;
2403         int ret;
2404
2405         /* get the speed and duplex as autoneg'result from mac cmd when phy
2406          * doesn't exit.
2407          */
2408         if (mac.phydev || !mac.autoneg)
2409                 return 0;
2410
2411         ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2412         if (ret) {
2413                 dev_err(&hdev->pdev->dev,
2414                         "mac autoneg/speed/duplex query failed %d\n", ret);
2415                 return ret;
2416         }
2417
2418         if ((mac.speed != speed) || (mac.duplex != duplex)) {
2419                 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2420                 if (ret) {
2421                         dev_err(&hdev->pdev->dev,
2422                                 "mac speed/duplex config failed %d\n", ret);
2423                         return ret;
2424                 }
2425         }
2426
2427         return 0;
2428 }
2429
2430 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2431 {
2432         struct hclge_vport *vport = hclge_get_vport(handle);
2433         struct hclge_dev *hdev = vport->back;
2434
2435         return hclge_update_speed_duplex(hdev);
2436 }
2437
2438 static int hclge_get_status(struct hnae3_handle *handle)
2439 {
2440         struct hclge_vport *vport = hclge_get_vport(handle);
2441         struct hclge_dev *hdev = vport->back;
2442
2443         hclge_update_link_status(hdev);
2444
2445         return hdev->hw.mac.link;
2446 }
2447
2448 static void hclge_service_timer(struct timer_list *t)
2449 {
2450         struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2451
2452         mod_timer(&hdev->service_timer, jiffies + HZ);
2453         hdev->hw_stats.stats_timer++;
2454         hclge_task_schedule(hdev);
2455 }
2456
2457 static void hclge_service_complete(struct hclge_dev *hdev)
2458 {
2459         WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2460
2461         /* Flush memory before next watchdog */
2462         smp_mb__before_atomic();
2463         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2464 }
2465
2466 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2467 {
2468         u32 rst_src_reg;
2469         u32 cmdq_src_reg;
2470
2471         /* fetch the events from their corresponding regs */
2472         rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
2473         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2474
2475         /* Assumption: If by any chance reset and mailbox events are reported
2476          * together then we will only process reset event in this go and will
2477          * defer the processing of the mailbox events. Since, we would have not
2478          * cleared RX CMDQ event this time we would receive again another
2479          * interrupt from H/W just for the mailbox.
2480          */
2481
2482         /* check for vector0 reset event sources */
2483         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2484                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2485                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2486                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2487                 return HCLGE_VECTOR0_EVENT_RST;
2488         }
2489
2490         if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2491                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2492                 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2493                 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2494                 return HCLGE_VECTOR0_EVENT_RST;
2495         }
2496
2497         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2498                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2499                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2500                 return HCLGE_VECTOR0_EVENT_RST;
2501         }
2502
2503         /* check for vector0 mailbox(=CMDQ RX) event source */
2504         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2505                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2506                 *clearval = cmdq_src_reg;
2507                 return HCLGE_VECTOR0_EVENT_MBX;
2508         }
2509
2510         return HCLGE_VECTOR0_EVENT_OTHER;
2511 }
2512
2513 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2514                                     u32 regclr)
2515 {
2516         switch (event_type) {
2517         case HCLGE_VECTOR0_EVENT_RST:
2518                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2519                 break;
2520         case HCLGE_VECTOR0_EVENT_MBX:
2521                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2522                 break;
2523         }
2524 }
2525
2526 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2527 {
2528         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2529                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2530                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2531                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2532         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2533 }
2534
2535 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2536 {
2537         writel(enable ? 1 : 0, vector->addr);
2538 }
2539
2540 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2541 {
2542         struct hclge_dev *hdev = data;
2543         u32 event_cause;
2544         u32 clearval;
2545
2546         hclge_enable_vector(&hdev->misc_vector, false);
2547         event_cause = hclge_check_event_cause(hdev, &clearval);
2548
2549         /* vector 0 interrupt is shared with reset and mailbox source events.*/
2550         switch (event_cause) {
2551         case HCLGE_VECTOR0_EVENT_RST:
2552                 hclge_reset_task_schedule(hdev);
2553                 break;
2554         case HCLGE_VECTOR0_EVENT_MBX:
2555                 /* If we are here then,
2556                  * 1. Either we are not handling any mbx task and we are not
2557                  *    scheduled as well
2558                  *                        OR
2559                  * 2. We could be handling a mbx task but nothing more is
2560                  *    scheduled.
2561                  * In both cases, we should schedule mbx task as there are more
2562                  * mbx messages reported by this interrupt.
2563                  */
2564                 hclge_mbx_task_schedule(hdev);
2565                 break;
2566         default:
2567                 dev_warn(&hdev->pdev->dev,
2568                          "received unknown or unhandled event of vector0\n");
2569                 break;
2570         }
2571
2572         /* clear the source of interrupt if it is not cause by reset */
2573         if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2574                 hclge_clear_event_cause(hdev, event_cause, clearval);
2575                 hclge_enable_vector(&hdev->misc_vector, true);
2576         }
2577
2578         return IRQ_HANDLED;
2579 }
2580
2581 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2582 {
2583         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2584                 dev_warn(&hdev->pdev->dev,
2585                          "vector(vector_id %d) has been freed.\n", vector_id);
2586                 return;
2587         }
2588
2589         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2590         hdev->num_msi_left += 1;
2591         hdev->num_msi_used -= 1;
2592 }
2593
2594 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2595 {
2596         struct hclge_misc_vector *vector = &hdev->misc_vector;
2597
2598         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2599
2600         vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2601         hdev->vector_status[0] = 0;
2602
2603         hdev->num_msi_left -= 1;
2604         hdev->num_msi_used += 1;
2605 }
2606
2607 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2608 {
2609         int ret;
2610
2611         hclge_get_misc_vector(hdev);
2612
2613         /* this would be explicitly freed in the end */
2614         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2615                           0, "hclge_misc", hdev);
2616         if (ret) {
2617                 hclge_free_vector(hdev, 0);
2618                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2619                         hdev->misc_vector.vector_irq);
2620         }
2621
2622         return ret;
2623 }
2624
2625 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2626 {
2627         free_irq(hdev->misc_vector.vector_irq, hdev);
2628         hclge_free_vector(hdev, 0);
2629 }
2630
2631 static int hclge_notify_client(struct hclge_dev *hdev,
2632                                enum hnae3_reset_notify_type type)
2633 {
2634         struct hnae3_client *client = hdev->nic_client;
2635         u16 i;
2636
2637         if (!client->ops->reset_notify)
2638                 return -EOPNOTSUPP;
2639
2640         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2641                 struct hnae3_handle *handle = &hdev->vport[i].nic;
2642                 int ret;
2643
2644                 ret = client->ops->reset_notify(handle, type);
2645                 if (ret)
2646                         return ret;
2647         }
2648
2649         return 0;
2650 }
2651
2652 static int hclge_reset_wait(struct hclge_dev *hdev)
2653 {
2654 #define HCLGE_RESET_WATI_MS     100
2655 #define HCLGE_RESET_WAIT_CNT    5
2656         u32 val, reg, reg_bit;
2657         u32 cnt = 0;
2658
2659         switch (hdev->reset_type) {
2660         case HNAE3_GLOBAL_RESET:
2661                 reg = HCLGE_GLOBAL_RESET_REG;
2662                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2663                 break;
2664         case HNAE3_CORE_RESET:
2665                 reg = HCLGE_GLOBAL_RESET_REG;
2666                 reg_bit = HCLGE_CORE_RESET_BIT;
2667                 break;
2668         case HNAE3_FUNC_RESET:
2669                 reg = HCLGE_FUN_RST_ING;
2670                 reg_bit = HCLGE_FUN_RST_ING_B;
2671                 break;
2672         default:
2673                 dev_err(&hdev->pdev->dev,
2674                         "Wait for unsupported reset type: %d\n",
2675                         hdev->reset_type);
2676                 return -EINVAL;
2677         }
2678
2679         val = hclge_read_dev(&hdev->hw, reg);
2680         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2681                 msleep(HCLGE_RESET_WATI_MS);
2682                 val = hclge_read_dev(&hdev->hw, reg);
2683                 cnt++;
2684         }
2685
2686         if (cnt >= HCLGE_RESET_WAIT_CNT) {
2687                 dev_warn(&hdev->pdev->dev,
2688                          "Wait for reset timeout: %d\n", hdev->reset_type);
2689                 return -EBUSY;
2690         }
2691
2692         return 0;
2693 }
2694
2695 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2696 {
2697         struct hclge_desc desc;
2698         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2699         int ret;
2700
2701         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2702         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2703         req->fun_reset_vfid = func_id;
2704
2705         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2706         if (ret)
2707                 dev_err(&hdev->pdev->dev,
2708                         "send function reset cmd fail, status =%d\n", ret);
2709
2710         return ret;
2711 }
2712
2713 static void hclge_do_reset(struct hclge_dev *hdev)
2714 {
2715         struct pci_dev *pdev = hdev->pdev;
2716         u32 val;
2717
2718         switch (hdev->reset_type) {
2719         case HNAE3_GLOBAL_RESET:
2720                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2721                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2722                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2723                 dev_info(&pdev->dev, "Global Reset requested\n");
2724                 break;
2725         case HNAE3_CORE_RESET:
2726                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2727                 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2728                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2729                 dev_info(&pdev->dev, "Core Reset requested\n");
2730                 break;
2731         case HNAE3_FUNC_RESET:
2732                 dev_info(&pdev->dev, "PF Reset requested\n");
2733                 hclge_func_reset_cmd(hdev, 0);
2734                 /* schedule again to check later */
2735                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2736                 hclge_reset_task_schedule(hdev);
2737                 break;
2738         default:
2739                 dev_warn(&pdev->dev,
2740                          "Unsupported reset type: %d\n", hdev->reset_type);
2741                 break;
2742         }
2743 }
2744
2745 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2746                                                    unsigned long *addr)
2747 {
2748         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2749
2750         /* return the highest priority reset level amongst all */
2751         if (test_bit(HNAE3_GLOBAL_RESET, addr))
2752                 rst_level = HNAE3_GLOBAL_RESET;
2753         else if (test_bit(HNAE3_CORE_RESET, addr))
2754                 rst_level = HNAE3_CORE_RESET;
2755         else if (test_bit(HNAE3_IMP_RESET, addr))
2756                 rst_level = HNAE3_IMP_RESET;
2757         else if (test_bit(HNAE3_FUNC_RESET, addr))
2758                 rst_level = HNAE3_FUNC_RESET;
2759
2760         /* now, clear all other resets */
2761         clear_bit(HNAE3_GLOBAL_RESET, addr);
2762         clear_bit(HNAE3_CORE_RESET, addr);
2763         clear_bit(HNAE3_IMP_RESET, addr);
2764         clear_bit(HNAE3_FUNC_RESET, addr);
2765
2766         return rst_level;
2767 }
2768
2769 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2770 {
2771         u32 clearval = 0;
2772
2773         switch (hdev->reset_type) {
2774         case HNAE3_IMP_RESET:
2775                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2776                 break;
2777         case HNAE3_GLOBAL_RESET:
2778                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2779                 break;
2780         case HNAE3_CORE_RESET:
2781                 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2782                 break;
2783         default:
2784                 break;
2785         }
2786
2787         if (!clearval)
2788                 return;
2789
2790         hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2791         hclge_enable_vector(&hdev->misc_vector, true);
2792 }
2793
2794 static void hclge_reset(struct hclge_dev *hdev)
2795 {
2796         struct hnae3_handle *handle;
2797
2798         /* perform reset of the stack & ae device for a client */
2799         handle = &hdev->vport[0].nic;
2800         rtnl_lock();
2801         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2802
2803         if (!hclge_reset_wait(hdev)) {
2804                 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2805                 hclge_reset_ae_dev(hdev->ae_dev);
2806                 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2807
2808                 hclge_clear_reset_cause(hdev);
2809         } else {
2810                 /* schedule again to check pending resets later */
2811                 set_bit(hdev->reset_type, &hdev->reset_pending);
2812                 hclge_reset_task_schedule(hdev);
2813         }
2814
2815         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2816         handle->last_reset_time = jiffies;
2817         rtnl_unlock();
2818 }
2819
2820 static void hclge_reset_event(struct hnae3_handle *handle)
2821 {
2822         struct hclge_vport *vport = hclge_get_vport(handle);
2823         struct hclge_dev *hdev = vport->back;
2824
2825         /* check if this is a new reset request and we are not here just because
2826          * last reset attempt did not succeed and watchdog hit us again. We will
2827          * know this if last reset request did not occur very recently (watchdog
2828          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2829          * In case of new request we reset the "reset level" to PF reset.
2830          * And if it is a repeat reset request of the most recent one then we
2831          * want to make sure we throttle the reset request. Therefore, we will
2832          * not allow it again before 3*HZ times.
2833          */
2834         if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2835                 return;
2836         else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2837                 handle->reset_level = HNAE3_FUNC_RESET;
2838
2839         dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2840                  handle->reset_level);
2841
2842         /* request reset & schedule reset task */
2843         set_bit(handle->reset_level, &hdev->reset_request);
2844         hclge_reset_task_schedule(hdev);
2845
2846         if (handle->reset_level < HNAE3_GLOBAL_RESET)
2847                 handle->reset_level++;
2848 }
2849
2850 static void hclge_reset_subtask(struct hclge_dev *hdev)
2851 {
2852         /* check if there is any ongoing reset in the hardware. This status can
2853          * be checked from reset_pending. If there is then, we need to wait for
2854          * hardware to complete reset.
2855          *    a. If we are able to figure out in reasonable time that hardware
2856          *       has fully resetted then, we can proceed with driver, client
2857          *       reset.
2858          *    b. else, we can come back later to check this status so re-sched
2859          *       now.
2860          */
2861         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2862         if (hdev->reset_type != HNAE3_NONE_RESET)
2863                 hclge_reset(hdev);
2864
2865         /* check if we got any *new* reset requests to be honored */
2866         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2867         if (hdev->reset_type != HNAE3_NONE_RESET)
2868                 hclge_do_reset(hdev);
2869
2870         hdev->reset_type = HNAE3_NONE_RESET;
2871 }
2872
2873 static void hclge_reset_service_task(struct work_struct *work)
2874 {
2875         struct hclge_dev *hdev =
2876                 container_of(work, struct hclge_dev, rst_service_task);
2877
2878         if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2879                 return;
2880
2881         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2882
2883         hclge_reset_subtask(hdev);
2884
2885         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2886 }
2887
2888 static void hclge_mailbox_service_task(struct work_struct *work)
2889 {
2890         struct hclge_dev *hdev =
2891                 container_of(work, struct hclge_dev, mbx_service_task);
2892
2893         if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2894                 return;
2895
2896         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2897
2898         hclge_mbx_handler(hdev);
2899
2900         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2901 }
2902
2903 static void hclge_service_task(struct work_struct *work)
2904 {
2905         struct hclge_dev *hdev =
2906                 container_of(work, struct hclge_dev, service_task);
2907
2908         if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2909                 hclge_update_stats_for_all(hdev);
2910                 hdev->hw_stats.stats_timer = 0;
2911         }
2912
2913         hclge_update_speed_duplex(hdev);
2914         hclge_update_link_status(hdev);
2915         hclge_service_complete(hdev);
2916 }
2917
2918 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2919 {
2920         /* VF handle has no client */
2921         if (!handle->client)
2922                 return container_of(handle, struct hclge_vport, nic);
2923         else if (handle->client->type == HNAE3_CLIENT_ROCE)
2924                 return container_of(handle, struct hclge_vport, roce);
2925         else
2926                 return container_of(handle, struct hclge_vport, nic);
2927 }
2928
2929 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2930                             struct hnae3_vector_info *vector_info)
2931 {
2932         struct hclge_vport *vport = hclge_get_vport(handle);
2933         struct hnae3_vector_info *vector = vector_info;
2934         struct hclge_dev *hdev = vport->back;
2935         int alloc = 0;
2936         int i, j;
2937
2938         vector_num = min(hdev->num_msi_left, vector_num);
2939
2940         for (j = 0; j < vector_num; j++) {
2941                 for (i = 1; i < hdev->num_msi; i++) {
2942                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2943                                 vector->vector = pci_irq_vector(hdev->pdev, i);
2944                                 vector->io_addr = hdev->hw.io_base +
2945                                         HCLGE_VECTOR_REG_BASE +
2946                                         (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2947                                         vport->vport_id *
2948                                         HCLGE_VECTOR_VF_OFFSET;
2949                                 hdev->vector_status[i] = vport->vport_id;
2950                                 hdev->vector_irq[i] = vector->vector;
2951
2952                                 vector++;
2953                                 alloc++;
2954
2955                                 break;
2956                         }
2957                 }
2958         }
2959         hdev->num_msi_left -= alloc;
2960         hdev->num_msi_used += alloc;
2961
2962         return alloc;
2963 }
2964
2965 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2966 {
2967         int i;
2968
2969         for (i = 0; i < hdev->num_msi; i++)
2970                 if (vector == hdev->vector_irq[i])
2971                         return i;
2972
2973         return -EINVAL;
2974 }
2975
2976 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2977 {
2978         struct hclge_vport *vport = hclge_get_vport(handle);
2979         struct hclge_dev *hdev = vport->back;
2980         int vector_id;
2981
2982         vector_id = hclge_get_vector_index(hdev, vector);
2983         if (vector_id < 0) {
2984                 dev_err(&hdev->pdev->dev,
2985                         "Get vector index fail. vector_id =%d\n", vector_id);
2986                 return vector_id;
2987         }
2988
2989         hclge_free_vector(hdev, vector_id);
2990
2991         return 0;
2992 }
2993
2994 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2995 {
2996         return HCLGE_RSS_KEY_SIZE;
2997 }
2998
2999 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3000 {
3001         return HCLGE_RSS_IND_TBL_SIZE;
3002 }
3003
3004 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3005                                   const u8 hfunc, const u8 *key)
3006 {
3007         struct hclge_rss_config_cmd *req;
3008         struct hclge_desc desc;
3009         int key_offset;
3010         int key_size;
3011         int ret;
3012
3013         req = (struct hclge_rss_config_cmd *)desc.data;
3014
3015         for (key_offset = 0; key_offset < 3; key_offset++) {
3016                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3017                                            false);
3018
3019                 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3020                 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3021
3022                 if (key_offset == 2)
3023                         key_size =
3024                         HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3025                 else
3026                         key_size = HCLGE_RSS_HASH_KEY_NUM;
3027
3028                 memcpy(req->hash_key,
3029                        key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3030
3031                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3032                 if (ret) {
3033                         dev_err(&hdev->pdev->dev,
3034                                 "Configure RSS config fail, status = %d\n",
3035                                 ret);
3036                         return ret;
3037                 }
3038         }
3039         return 0;
3040 }
3041
3042 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
3043 {
3044         struct hclge_rss_indirection_table_cmd *req;
3045         struct hclge_desc desc;
3046         int i, j;
3047         int ret;
3048
3049         req = (struct hclge_rss_indirection_table_cmd *)desc.data;
3050
3051         for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3052                 hclge_cmd_setup_basic_desc
3053                         (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3054
3055                 req->start_table_index =
3056                         cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3057                 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
3058
3059                 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3060                         req->rss_result[j] =
3061                                 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3062
3063                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3064                 if (ret) {
3065                         dev_err(&hdev->pdev->dev,
3066                                 "Configure rss indir table fail,status = %d\n",
3067                                 ret);
3068                         return ret;
3069                 }
3070         }
3071         return 0;
3072 }
3073
3074 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3075                                  u16 *tc_size, u16 *tc_offset)
3076 {
3077         struct hclge_rss_tc_mode_cmd *req;
3078         struct hclge_desc desc;
3079         int ret;
3080         int i;
3081
3082         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3083         req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3084
3085         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3086                 u16 mode = 0;
3087
3088                 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3089                 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3090                                 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3091                 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3092                                 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3093
3094                 req->rss_tc_mode[i] = cpu_to_le16(mode);
3095         }
3096
3097         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3098         if (ret)
3099                 dev_err(&hdev->pdev->dev,
3100                         "Configure rss tc mode fail, status = %d\n", ret);
3101
3102         return ret;
3103 }
3104
3105 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3106 {
3107         struct hclge_rss_input_tuple_cmd *req;
3108         struct hclge_desc desc;
3109         int ret;
3110
3111         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3112
3113         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3114
3115         /* Get the tuple cfg from pf */
3116         req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3117         req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3118         req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3119         req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3120         req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3121         req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3122         req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3123         req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
3124         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3125         if (ret)
3126                 dev_err(&hdev->pdev->dev,
3127                         "Configure rss input fail, status = %d\n", ret);
3128         return ret;
3129 }
3130
3131 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3132                          u8 *key, u8 *hfunc)
3133 {
3134         struct hclge_vport *vport = hclge_get_vport(handle);
3135         int i;
3136
3137         /* Get hash algorithm */
3138         if (hfunc)
3139                 *hfunc = vport->rss_algo;
3140
3141         /* Get the RSS Key required by the user */
3142         if (key)
3143                 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3144
3145         /* Get indirect table */
3146         if (indir)
3147                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3148                         indir[i] =  vport->rss_indirection_tbl[i];
3149
3150         return 0;
3151 }
3152
3153 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3154                          const  u8 *key, const  u8 hfunc)
3155 {
3156         struct hclge_vport *vport = hclge_get_vport(handle);
3157         struct hclge_dev *hdev = vport->back;
3158         u8 hash_algo;
3159         int ret, i;
3160
3161         /* Set the RSS Hash Key if specififed by the user */
3162         if (key) {
3163
3164                 if (hfunc == ETH_RSS_HASH_TOP ||
3165                     hfunc == ETH_RSS_HASH_NO_CHANGE)
3166                         hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3167                 else
3168                         return -EINVAL;
3169                 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3170                 if (ret)
3171                         return ret;
3172
3173                 /* Update the shadow RSS key with user specified qids */
3174                 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3175                 vport->rss_algo = hash_algo;
3176         }
3177
3178         /* Update the shadow RSS table with user specified qids */
3179         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3180                 vport->rss_indirection_tbl[i] = indir[i];
3181
3182         /* Update the hardware */
3183         return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
3184 }
3185
3186 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3187 {
3188         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3189
3190         if (nfc->data & RXH_L4_B_2_3)
3191                 hash_sets |= HCLGE_D_PORT_BIT;
3192         else
3193                 hash_sets &= ~HCLGE_D_PORT_BIT;
3194
3195         if (nfc->data & RXH_IP_SRC)
3196                 hash_sets |= HCLGE_S_IP_BIT;
3197         else
3198                 hash_sets &= ~HCLGE_S_IP_BIT;
3199
3200         if (nfc->data & RXH_IP_DST)
3201                 hash_sets |= HCLGE_D_IP_BIT;
3202         else
3203                 hash_sets &= ~HCLGE_D_IP_BIT;
3204
3205         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3206                 hash_sets |= HCLGE_V_TAG_BIT;
3207
3208         return hash_sets;
3209 }
3210
3211 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3212                                struct ethtool_rxnfc *nfc)
3213 {
3214         struct hclge_vport *vport = hclge_get_vport(handle);
3215         struct hclge_dev *hdev = vport->back;
3216         struct hclge_rss_input_tuple_cmd *req;
3217         struct hclge_desc desc;
3218         u8 tuple_sets;
3219         int ret;
3220
3221         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3222                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
3223                 return -EINVAL;
3224
3225         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3226         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3227
3228         req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3229         req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3230         req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3231         req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3232         req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3233         req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3234         req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3235         req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
3236
3237         tuple_sets = hclge_get_rss_hash_bits(nfc);
3238         switch (nfc->flow_type) {
3239         case TCP_V4_FLOW:
3240                 req->ipv4_tcp_en = tuple_sets;
3241                 break;
3242         case TCP_V6_FLOW:
3243                 req->ipv6_tcp_en = tuple_sets;
3244                 break;
3245         case UDP_V4_FLOW:
3246                 req->ipv4_udp_en = tuple_sets;
3247                 break;
3248         case UDP_V6_FLOW:
3249                 req->ipv6_udp_en = tuple_sets;
3250                 break;
3251         case SCTP_V4_FLOW:
3252                 req->ipv4_sctp_en = tuple_sets;
3253                 break;
3254         case SCTP_V6_FLOW:
3255                 if ((nfc->data & RXH_L4_B_0_1) ||
3256                     (nfc->data & RXH_L4_B_2_3))
3257                         return -EINVAL;
3258
3259                 req->ipv6_sctp_en = tuple_sets;
3260                 break;
3261         case IPV4_FLOW:
3262                 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3263                 break;
3264         case IPV6_FLOW:
3265                 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3266                 break;
3267         default:
3268                 return -EINVAL;
3269         }
3270
3271         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3272         if (ret) {
3273                 dev_err(&hdev->pdev->dev,
3274                         "Set rss tuple fail, status = %d\n", ret);
3275                 return ret;
3276         }
3277
3278         vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3279         vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3280         vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3281         vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3282         vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3283         vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3284         vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3285         vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3286         return 0;
3287 }
3288
3289 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3290                                struct ethtool_rxnfc *nfc)
3291 {
3292         struct hclge_vport *vport = hclge_get_vport(handle);
3293         u8 tuple_sets;
3294
3295         nfc->data = 0;
3296
3297         switch (nfc->flow_type) {
3298         case TCP_V4_FLOW:
3299                 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3300                 break;
3301         case UDP_V4_FLOW:
3302                 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3303                 break;
3304         case TCP_V6_FLOW:
3305                 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3306                 break;
3307         case UDP_V6_FLOW:
3308                 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3309                 break;
3310         case SCTP_V4_FLOW:
3311                 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3312                 break;
3313         case SCTP_V6_FLOW:
3314                 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3315                 break;
3316         case IPV4_FLOW:
3317         case IPV6_FLOW:
3318                 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3319                 break;
3320         default:
3321                 return -EINVAL;
3322         }
3323
3324         if (!tuple_sets)
3325                 return 0;
3326
3327         if (tuple_sets & HCLGE_D_PORT_BIT)
3328                 nfc->data |= RXH_L4_B_2_3;
3329         if (tuple_sets & HCLGE_S_PORT_BIT)
3330                 nfc->data |= RXH_L4_B_0_1;
3331         if (tuple_sets & HCLGE_D_IP_BIT)
3332                 nfc->data |= RXH_IP_DST;
3333         if (tuple_sets & HCLGE_S_IP_BIT)
3334                 nfc->data |= RXH_IP_SRC;
3335
3336         return 0;
3337 }
3338
3339 static int hclge_get_tc_size(struct hnae3_handle *handle)
3340 {
3341         struct hclge_vport *vport = hclge_get_vport(handle);
3342         struct hclge_dev *hdev = vport->back;
3343
3344         return hdev->rss_size_max;
3345 }
3346
3347 int hclge_rss_init_hw(struct hclge_dev *hdev)
3348 {
3349         struct hclge_vport *vport = hdev->vport;
3350         u8 *rss_indir = vport[0].rss_indirection_tbl;
3351         u16 rss_size = vport[0].alloc_rss_size;
3352         u8 *key = vport[0].rss_hash_key;
3353         u8 hfunc = vport[0].rss_algo;
3354         u16 tc_offset[HCLGE_MAX_TC_NUM];
3355         u16 tc_valid[HCLGE_MAX_TC_NUM];
3356         u16 tc_size[HCLGE_MAX_TC_NUM];
3357         u16 roundup_size;
3358         int i, ret;
3359
3360         ret = hclge_set_rss_indir_table(hdev, rss_indir);
3361         if (ret)
3362                 return ret;
3363
3364         ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3365         if (ret)
3366                 return ret;
3367
3368         ret = hclge_set_rss_input_tuple(hdev);
3369         if (ret)
3370                 return ret;
3371
3372         /* Each TC have the same queue size, and tc_size set to hardware is
3373          * the log2 of roundup power of two of rss_size, the acutal queue
3374          * size is limited by indirection table.
3375          */
3376         if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3377                 dev_err(&hdev->pdev->dev,
3378                         "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3379                         rss_size);
3380                 return -EINVAL;
3381         }
3382
3383         roundup_size = roundup_pow_of_two(rss_size);
3384         roundup_size = ilog2(roundup_size);
3385
3386         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3387                 tc_valid[i] = 0;
3388
3389                 if (!(hdev->hw_tc_map & BIT(i)))
3390                         continue;
3391
3392                 tc_valid[i] = 1;
3393                 tc_size[i] = roundup_size;
3394                 tc_offset[i] = rss_size * i;
3395         }
3396
3397         return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3398 }
3399
3400 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3401 {
3402         struct hclge_vport *vport = hdev->vport;
3403         int i, j;
3404
3405         for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3406                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3407                         vport[j].rss_indirection_tbl[i] =
3408                                 i % vport[j].alloc_rss_size;
3409         }
3410 }
3411
3412 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3413 {
3414         struct hclge_vport *vport = hdev->vport;
3415         int i;
3416
3417         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3418                 vport[i].rss_tuple_sets.ipv4_tcp_en =
3419                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3420                 vport[i].rss_tuple_sets.ipv4_udp_en =
3421                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3422                 vport[i].rss_tuple_sets.ipv4_sctp_en =
3423                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3424                 vport[i].rss_tuple_sets.ipv4_fragment_en =
3425                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3426                 vport[i].rss_tuple_sets.ipv6_tcp_en =
3427                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3428                 vport[i].rss_tuple_sets.ipv6_udp_en =
3429                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3430                 vport[i].rss_tuple_sets.ipv6_sctp_en =
3431                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3432                 vport[i].rss_tuple_sets.ipv6_fragment_en =
3433                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3434
3435                 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3436
3437                 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3438         }
3439
3440         hclge_rss_indir_init_cfg(hdev);
3441 }
3442
3443 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3444                                 int vector_id, bool en,
3445                                 struct hnae3_ring_chain_node *ring_chain)
3446 {
3447         struct hclge_dev *hdev = vport->back;
3448         struct hnae3_ring_chain_node *node;
3449         struct hclge_desc desc;
3450         struct hclge_ctrl_vector_chain_cmd *req
3451                 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3452         enum hclge_cmd_status status;
3453         enum hclge_opcode_type op;
3454         u16 tqp_type_and_id;
3455         int i;
3456
3457         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3458         hclge_cmd_setup_basic_desc(&desc, op, false);
3459         req->int_vector_id = vector_id;
3460
3461         i = 0;
3462         for (node = ring_chain; node; node = node->next) {
3463                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3464                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
3465                                 HCLGE_INT_TYPE_S,
3466                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3467                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3468                                 HCLGE_TQP_ID_S, node->tqp_index);
3469                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3470                                 HCLGE_INT_GL_IDX_S,
3471                                 hnae3_get_field(node->int_gl_idx,
3472                                                 HNAE3_RING_GL_IDX_M,
3473                                                 HNAE3_RING_GL_IDX_S));
3474                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3475                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3476                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3477                         req->vfid = vport->vport_id;
3478
3479                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
3480                         if (status) {
3481                                 dev_err(&hdev->pdev->dev,
3482                                         "Map TQP fail, status is %d.\n",
3483                                         status);
3484                                 return -EIO;
3485                         }
3486                         i = 0;
3487
3488                         hclge_cmd_setup_basic_desc(&desc,
3489                                                    op,
3490                                                    false);
3491                         req->int_vector_id = vector_id;
3492                 }
3493         }
3494
3495         if (i > 0) {
3496                 req->int_cause_num = i;
3497                 req->vfid = vport->vport_id;
3498                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3499                 if (status) {
3500                         dev_err(&hdev->pdev->dev,
3501                                 "Map TQP fail, status is %d.\n", status);
3502                         return -EIO;
3503                 }
3504         }
3505
3506         return 0;
3507 }
3508
3509 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3510                                     int vector,
3511                                     struct hnae3_ring_chain_node *ring_chain)
3512 {
3513         struct hclge_vport *vport = hclge_get_vport(handle);
3514         struct hclge_dev *hdev = vport->back;
3515         int vector_id;
3516
3517         vector_id = hclge_get_vector_index(hdev, vector);
3518         if (vector_id < 0) {
3519                 dev_err(&hdev->pdev->dev,
3520                         "Get vector index fail. vector_id =%d\n", vector_id);
3521                 return vector_id;
3522         }
3523
3524         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3525 }
3526
3527 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3528                                        int vector,
3529                                        struct hnae3_ring_chain_node *ring_chain)
3530 {
3531         struct hclge_vport *vport = hclge_get_vport(handle);
3532         struct hclge_dev *hdev = vport->back;
3533         int vector_id, ret;
3534
3535         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3536                 return 0;
3537
3538         vector_id = hclge_get_vector_index(hdev, vector);
3539         if (vector_id < 0) {
3540                 dev_err(&handle->pdev->dev,
3541                         "Get vector index fail. ret =%d\n", vector_id);
3542                 return vector_id;
3543         }
3544
3545         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3546         if (ret)
3547                 dev_err(&handle->pdev->dev,
3548                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3549                         vector_id,
3550                         ret);
3551
3552         return ret;
3553 }
3554
3555 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3556                                struct hclge_promisc_param *param)
3557 {
3558         struct hclge_promisc_cfg_cmd *req;
3559         struct hclge_desc desc;
3560         int ret;
3561
3562         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3563
3564         req = (struct hclge_promisc_cfg_cmd *)desc.data;
3565         req->vf_id = param->vf_id;
3566
3567         /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3568          * pdev revision(0x20), new revision support them. The
3569          * value of this two fields will not return error when driver
3570          * send command to fireware in revision(0x20).
3571          */
3572         req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3573                 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3574
3575         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3576         if (ret)
3577                 dev_err(&hdev->pdev->dev,
3578                         "Set promisc mode fail, status is %d.\n", ret);
3579
3580         return ret;
3581 }
3582
3583 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3584                               bool en_mc, bool en_bc, int vport_id)
3585 {
3586         if (!param)
3587                 return;
3588
3589         memset(param, 0, sizeof(struct hclge_promisc_param));
3590         if (en_uc)
3591                 param->enable = HCLGE_PROMISC_EN_UC;
3592         if (en_mc)
3593                 param->enable |= HCLGE_PROMISC_EN_MC;
3594         if (en_bc)
3595                 param->enable |= HCLGE_PROMISC_EN_BC;
3596         param->vf_id = vport_id;
3597 }
3598
3599 static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3600                                    bool en_mc_pmc)
3601 {
3602         struct hclge_vport *vport = hclge_get_vport(handle);
3603         struct hclge_dev *hdev = vport->back;
3604         struct hclge_promisc_param param;
3605
3606         hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3607                                  vport->vport_id);
3608         hclge_cmd_set_promisc_mode(hdev, &param);
3609 }
3610
3611 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3612 {
3613         struct hclge_desc desc;
3614         struct hclge_config_mac_mode_cmd *req =
3615                 (struct hclge_config_mac_mode_cmd *)desc.data;
3616         u32 loop_en = 0;
3617         int ret;
3618
3619         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3620         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3621         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3622         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3623         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3624         hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3625         hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3626         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3627         hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3628         hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3629         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3630         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3631         hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3632         hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3633         hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3634         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3635
3636         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3637         if (ret)
3638                 dev_err(&hdev->pdev->dev,
3639                         "mac enable fail, ret =%d.\n", ret);
3640 }
3641
3642 static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
3643 {
3644         struct hclge_config_mac_mode_cmd *req;
3645         struct hclge_desc desc;
3646         u32 loop_en;
3647         int ret;
3648
3649         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3650         /* 1 Read out the MAC mode config at first */
3651         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3652         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3653         if (ret) {
3654                 dev_err(&hdev->pdev->dev,
3655                         "mac loopback get fail, ret =%d.\n", ret);
3656                 return ret;
3657         }
3658
3659         /* 2 Then setup the loopback flag */
3660         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3661         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
3662
3663         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3664
3665         /* 3 Config mac work mode with loopback flag
3666          * and its original configure parameters
3667          */
3668         hclge_cmd_reuse_desc(&desc, false);
3669         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3670         if (ret)
3671                 dev_err(&hdev->pdev->dev,
3672                         "mac loopback set fail, ret =%d.\n", ret);
3673         return ret;
3674 }
3675
3676 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3677 {
3678 #define HCLGE_SERDES_RETRY_MS   10
3679 #define HCLGE_SERDES_RETRY_NUM  100
3680         struct hclge_serdes_lb_cmd *req;
3681         struct hclge_desc desc;
3682         int ret, i = 0;
3683
3684         req = (struct hclge_serdes_lb_cmd *)&desc.data[0];
3685         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3686
3687         if (en) {
3688                 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3689                 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3690         } else {
3691                 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3692         }
3693
3694         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3695         if (ret) {
3696                 dev_err(&hdev->pdev->dev,
3697                         "serdes loopback set fail, ret = %d\n", ret);
3698                 return ret;
3699         }
3700
3701         do {
3702                 msleep(HCLGE_SERDES_RETRY_MS);
3703                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3704                                            true);
3705                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3706                 if (ret) {
3707                         dev_err(&hdev->pdev->dev,
3708                                 "serdes loopback get, ret = %d\n", ret);
3709                         return ret;
3710                 }
3711         } while (++i < HCLGE_SERDES_RETRY_NUM &&
3712                  !(req->result & HCLGE_CMD_SERDES_DONE_B));
3713
3714         if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3715                 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3716                 return -EBUSY;
3717         } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3718                 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3719                 return -EIO;
3720         }
3721
3722         return 0;
3723 }
3724
3725 static int hclge_set_loopback(struct hnae3_handle *handle,
3726                               enum hnae3_loop loop_mode, bool en)
3727 {
3728         struct hclge_vport *vport = hclge_get_vport(handle);
3729         struct hclge_dev *hdev = vport->back;
3730         int ret;
3731
3732         switch (loop_mode) {
3733         case HNAE3_MAC_INTER_LOOP_MAC:
3734                 ret = hclge_set_mac_loopback(hdev, en);
3735                 break;
3736         case HNAE3_MAC_INTER_LOOP_SERDES:
3737                 ret = hclge_set_serdes_loopback(hdev, en);
3738                 break;
3739         default:
3740                 ret = -ENOTSUPP;
3741                 dev_err(&hdev->pdev->dev,
3742                         "loop_mode %d is not supported\n", loop_mode);
3743                 break;
3744         }
3745
3746         return ret;
3747 }
3748
3749 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3750                             int stream_id, bool enable)
3751 {
3752         struct hclge_desc desc;
3753         struct hclge_cfg_com_tqp_queue_cmd *req =
3754                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3755         int ret;
3756
3757         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3758         req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3759         req->stream_id = cpu_to_le16(stream_id);
3760         req->enable |= enable << HCLGE_TQP_ENABLE_B;
3761
3762         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3763         if (ret)
3764                 dev_err(&hdev->pdev->dev,
3765                         "Tqp enable fail, status =%d.\n", ret);
3766         return ret;
3767 }
3768
3769 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3770 {
3771         struct hclge_vport *vport = hclge_get_vport(handle);
3772         struct hnae3_queue *queue;
3773         struct hclge_tqp *tqp;
3774         int i;
3775
3776         for (i = 0; i < vport->alloc_tqps; i++) {
3777                 queue = handle->kinfo.tqp[i];
3778                 tqp = container_of(queue, struct hclge_tqp, q);
3779                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3780         }
3781 }
3782
3783 static int hclge_ae_start(struct hnae3_handle *handle)
3784 {
3785         struct hclge_vport *vport = hclge_get_vport(handle);
3786         struct hclge_dev *hdev = vport->back;
3787         int i;
3788
3789         for (i = 0; i < vport->alloc_tqps; i++)
3790                 hclge_tqp_enable(hdev, i, 0, true);
3791
3792         /* mac enable */
3793         hclge_cfg_mac_mode(hdev, true);
3794         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3795         mod_timer(&hdev->service_timer, jiffies + HZ);
3796         hdev->hw.mac.link = 0;
3797
3798         /* reset tqp stats */
3799         hclge_reset_tqp_stats(handle);
3800
3801         hclge_mac_start_phy(hdev);
3802
3803         return 0;
3804 }
3805
3806 static void hclge_ae_stop(struct hnae3_handle *handle)
3807 {
3808         struct hclge_vport *vport = hclge_get_vport(handle);
3809         struct hclge_dev *hdev = vport->back;
3810         int i;
3811
3812         del_timer_sync(&hdev->service_timer);
3813         cancel_work_sync(&hdev->service_task);
3814         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
3815
3816         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3817                 hclge_mac_stop_phy(hdev);
3818                 return;
3819         }
3820
3821         for (i = 0; i < vport->alloc_tqps; i++)
3822                 hclge_tqp_enable(hdev, i, 0, false);
3823
3824         /* Mac disable */
3825         hclge_cfg_mac_mode(hdev, false);
3826
3827         hclge_mac_stop_phy(hdev);
3828
3829         /* reset tqp stats */
3830         hclge_reset_tqp_stats(handle);
3831         del_timer_sync(&hdev->service_timer);
3832         cancel_work_sync(&hdev->service_task);
3833         hclge_update_link_status(hdev);
3834 }
3835
3836 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3837                                          u16 cmdq_resp, u8  resp_code,
3838                                          enum hclge_mac_vlan_tbl_opcode op)
3839 {
3840         struct hclge_dev *hdev = vport->back;
3841         int return_status = -EIO;
3842
3843         if (cmdq_resp) {
3844                 dev_err(&hdev->pdev->dev,
3845                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3846                         cmdq_resp);
3847                 return -EIO;
3848         }
3849
3850         if (op == HCLGE_MAC_VLAN_ADD) {
3851                 if ((!resp_code) || (resp_code == 1)) {
3852                         return_status = 0;
3853                 } else if (resp_code == 2) {
3854                         return_status = -ENOSPC;
3855                         dev_err(&hdev->pdev->dev,
3856                                 "add mac addr failed for uc_overflow.\n");
3857                 } else if (resp_code == 3) {
3858                         return_status = -ENOSPC;
3859                         dev_err(&hdev->pdev->dev,
3860                                 "add mac addr failed for mc_overflow.\n");
3861                 } else {
3862                         dev_err(&hdev->pdev->dev,
3863                                 "add mac addr failed for undefined, code=%d.\n",
3864                                 resp_code);
3865                 }
3866         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3867                 if (!resp_code) {
3868                         return_status = 0;
3869                 } else if (resp_code == 1) {
3870                         return_status = -ENOENT;
3871                         dev_dbg(&hdev->pdev->dev,
3872                                 "remove mac addr failed for miss.\n");
3873                 } else {
3874                         dev_err(&hdev->pdev->dev,
3875                                 "remove mac addr failed for undefined, code=%d.\n",
3876                                 resp_code);
3877                 }
3878         } else if (op == HCLGE_MAC_VLAN_LKUP) {
3879                 if (!resp_code) {
3880                         return_status = 0;
3881                 } else if (resp_code == 1) {
3882                         return_status = -ENOENT;
3883                         dev_dbg(&hdev->pdev->dev,
3884                                 "lookup mac addr failed for miss.\n");
3885                 } else {
3886                         dev_err(&hdev->pdev->dev,
3887                                 "lookup mac addr failed for undefined, code=%d.\n",
3888                                 resp_code);
3889                 }
3890         } else {
3891                 return_status = -EINVAL;
3892                 dev_err(&hdev->pdev->dev,
3893                         "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3894                         op);
3895         }
3896
3897         return return_status;
3898 }
3899
3900 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3901 {
3902         int word_num;
3903         int bit_num;
3904
3905         if (vfid > 255 || vfid < 0)
3906                 return -EIO;
3907
3908         if (vfid >= 0 && vfid <= 191) {
3909                 word_num = vfid / 32;
3910                 bit_num  = vfid % 32;
3911                 if (clr)
3912                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3913                 else
3914                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3915         } else {
3916                 word_num = (vfid - 192) / 32;
3917                 bit_num  = vfid % 32;
3918                 if (clr)
3919                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3920                 else
3921                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3922         }
3923
3924         return 0;
3925 }
3926
3927 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3928 {
3929 #define HCLGE_DESC_NUMBER 3
3930 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3931         int i, j;
3932
3933         for (i = 1; i < HCLGE_DESC_NUMBER; i++)
3934                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3935                         if (desc[i].data[j])
3936                                 return false;
3937
3938         return true;
3939 }
3940
3941 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3942                                    const u8 *addr)
3943 {
3944         const unsigned char *mac_addr = addr;
3945         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3946                        (mac_addr[0]) | (mac_addr[1] << 8);
3947         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
3948
3949         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3950         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3951 }
3952
3953 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3954                                            const u8 *addr)
3955 {
3956         u16 high_val = addr[1] | (addr[0] << 8);
3957         struct hclge_dev *hdev = vport->back;
3958         u32 rsh = 4 - hdev->mta_mac_sel_type;
3959         u16 ret_val = (high_val >> rsh) & 0xfff;
3960
3961         return ret_val;
3962 }
3963
3964 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3965                                      enum hclge_mta_dmac_sel_type mta_mac_sel,
3966                                      bool enable)
3967 {
3968         struct hclge_mta_filter_mode_cmd *req;
3969         struct hclge_desc desc;
3970         int ret;
3971
3972         req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3973         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3974
3975         hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3976                       enable);
3977         hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3978                         HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3979
3980         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3981         if (ret)
3982                 dev_err(&hdev->pdev->dev,
3983                         "Config mat filter mode failed for cmd_send, ret =%d.\n",
3984                         ret);
3985
3986         return ret;
3987 }
3988
3989 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3990                               u8 func_id,
3991                               bool enable)
3992 {
3993         struct hclge_cfg_func_mta_filter_cmd *req;
3994         struct hclge_desc desc;
3995         int ret;
3996
3997         req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3998         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3999
4000         hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
4001                       enable);
4002         req->function_id = func_id;
4003
4004         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4005         if (ret)
4006                 dev_err(&hdev->pdev->dev,
4007                         "Config func_id enable failed for cmd_send, ret =%d.\n",
4008                         ret);
4009
4010         return ret;
4011 }
4012
4013 static int hclge_set_mta_table_item(struct hclge_vport *vport,
4014                                     u16 idx,
4015                                     bool enable)
4016 {
4017         struct hclge_dev *hdev = vport->back;
4018         struct hclge_cfg_func_mta_item_cmd *req;
4019         struct hclge_desc desc;
4020         u16 item_idx = 0;
4021         int ret;
4022
4023         req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
4024         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
4025         hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
4026
4027         hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4028                         HCLGE_CFG_MTA_ITEM_IDX_S, idx);
4029         req->item_idx = cpu_to_le16(item_idx);
4030
4031         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4032         if (ret) {
4033                 dev_err(&hdev->pdev->dev,
4034                         "Config mta table item failed for cmd_send, ret =%d.\n",
4035                         ret);
4036                 return ret;
4037         }
4038
4039         if (enable)
4040                 set_bit(idx, vport->mta_shadow);
4041         else
4042                 clear_bit(idx, vport->mta_shadow);
4043
4044         return 0;
4045 }
4046
4047 static int hclge_update_mta_status(struct hnae3_handle *handle)
4048 {
4049         unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4050         struct hclge_vport *vport = hclge_get_vport(handle);
4051         struct net_device *netdev = handle->kinfo.netdev;
4052         struct netdev_hw_addr *ha;
4053         u16 tbl_idx;
4054
4055         memset(mta_status, 0, sizeof(mta_status));
4056
4057         /* update mta_status from mc addr list */
4058         netdev_for_each_mc_addr(ha, netdev) {
4059                 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4060                 set_bit(tbl_idx, mta_status);
4061         }
4062
4063         return hclge_update_mta_status_common(vport, mta_status,
4064                                         0, HCLGE_MTA_TBL_SIZE, true);
4065 }
4066
4067 int hclge_update_mta_status_common(struct hclge_vport *vport,
4068                                    unsigned long *status,
4069                                    u16 idx,
4070                                    u16 count,
4071                                    bool update_filter)
4072 {
4073         struct hclge_dev *hdev = vport->back;
4074         u16 update_max = idx + count;
4075         u16 check_max;
4076         int ret = 0;
4077         bool used;
4078         u16 i;
4079
4080         /* setup mta check range */
4081         if (update_filter) {
4082                 i = 0;
4083                 check_max = HCLGE_MTA_TBL_SIZE;
4084         } else {
4085                 i = idx;
4086                 check_max = update_max;
4087         }
4088
4089         used = false;
4090         /* check and update all mta item */
4091         for (; i < check_max; i++) {
4092                 /* ignore unused item */
4093                 if (!test_bit(i, vport->mta_shadow))
4094                         continue;
4095
4096                 /* if i in update range then update it */
4097                 if (i >= idx && i < update_max)
4098                         if (!test_bit(i - idx, status))
4099                                 hclge_set_mta_table_item(vport, i, false);
4100
4101                 if (!used && test_bit(i, vport->mta_shadow))
4102                         used = true;
4103         }
4104
4105         /* no longer use mta, disable it */
4106         if (vport->accept_mta_mc && update_filter && !used) {
4107                 ret = hclge_cfg_func_mta_filter(hdev,
4108                                                 vport->vport_id,
4109                                                 false);
4110                 if (ret)
4111                         dev_err(&hdev->pdev->dev,
4112                                 "disable func mta filter fail ret=%d\n",
4113                                 ret);
4114                 else
4115                         vport->accept_mta_mc = false;
4116         }
4117
4118         return ret;
4119 }
4120
4121 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
4122                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
4123 {
4124         struct hclge_dev *hdev = vport->back;
4125         struct hclge_desc desc;
4126         u8 resp_code;
4127         u16 retval;
4128         int ret;
4129
4130         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4131
4132         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4133
4134         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4135         if (ret) {
4136                 dev_err(&hdev->pdev->dev,
4137                         "del mac addr failed for cmd_send, ret =%d.\n",
4138                         ret);
4139                 return ret;
4140         }
4141         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4142         retval = le16_to_cpu(desc.retval);
4143
4144         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4145                                              HCLGE_MAC_VLAN_REMOVE);
4146 }
4147
4148 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
4149                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
4150                                      struct hclge_desc *desc,
4151                                      bool is_mc)
4152 {
4153         struct hclge_dev *hdev = vport->back;
4154         u8 resp_code;
4155         u16 retval;
4156         int ret;
4157
4158         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4159         if (is_mc) {
4160                 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4161                 memcpy(desc[0].data,
4162                        req,
4163                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4164                 hclge_cmd_setup_basic_desc(&desc[1],
4165                                            HCLGE_OPC_MAC_VLAN_ADD,
4166                                            true);
4167                 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4168                 hclge_cmd_setup_basic_desc(&desc[2],
4169                                            HCLGE_OPC_MAC_VLAN_ADD,
4170                                            true);
4171                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4172         } else {
4173                 memcpy(desc[0].data,
4174                        req,
4175                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4176                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4177         }
4178         if (ret) {
4179                 dev_err(&hdev->pdev->dev,
4180                         "lookup mac addr failed for cmd_send, ret =%d.\n",
4181                         ret);
4182                 return ret;
4183         }
4184         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4185         retval = le16_to_cpu(desc[0].retval);
4186
4187         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4188                                              HCLGE_MAC_VLAN_LKUP);
4189 }
4190
4191 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
4192                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
4193                                   struct hclge_desc *mc_desc)
4194 {
4195         struct hclge_dev *hdev = vport->back;
4196         int cfg_status;
4197         u8 resp_code;
4198         u16 retval;
4199         int ret;
4200
4201         if (!mc_desc) {
4202                 struct hclge_desc desc;
4203
4204                 hclge_cmd_setup_basic_desc(&desc,
4205                                            HCLGE_OPC_MAC_VLAN_ADD,
4206                                            false);
4207                 memcpy(desc.data, req,
4208                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4209                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4210                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4211                 retval = le16_to_cpu(desc.retval);
4212
4213                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4214                                                            resp_code,
4215                                                            HCLGE_MAC_VLAN_ADD);
4216         } else {
4217                 hclge_cmd_reuse_desc(&mc_desc[0], false);
4218                 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4219                 hclge_cmd_reuse_desc(&mc_desc[1], false);
4220                 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4221                 hclge_cmd_reuse_desc(&mc_desc[2], false);
4222                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4223                 memcpy(mc_desc[0].data, req,
4224                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4225                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
4226                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4227                 retval = le16_to_cpu(mc_desc[0].retval);
4228
4229                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4230                                                            resp_code,
4231                                                            HCLGE_MAC_VLAN_ADD);
4232         }
4233
4234         if (ret) {
4235                 dev_err(&hdev->pdev->dev,
4236                         "add mac addr failed for cmd_send, ret =%d.\n",
4237                         ret);
4238                 return ret;
4239         }
4240
4241         return cfg_status;
4242 }
4243
4244 static int hclge_add_uc_addr(struct hnae3_handle *handle,
4245                              const unsigned char *addr)
4246 {
4247         struct hclge_vport *vport = hclge_get_vport(handle);
4248
4249         return hclge_add_uc_addr_common(vport, addr);
4250 }
4251
4252 int hclge_add_uc_addr_common(struct hclge_vport *vport,
4253                              const unsigned char *addr)
4254 {
4255         struct hclge_dev *hdev = vport->back;
4256         struct hclge_mac_vlan_tbl_entry_cmd req;
4257         struct hclge_desc desc;
4258         u16 egress_port = 0;
4259         int ret;
4260
4261         /* mac addr check */
4262         if (is_zero_ether_addr(addr) ||
4263             is_broadcast_ether_addr(addr) ||
4264             is_multicast_ether_addr(addr)) {
4265                 dev_err(&hdev->pdev->dev,
4266                         "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4267                          addr,
4268                          is_zero_ether_addr(addr),
4269                          is_broadcast_ether_addr(addr),
4270                          is_multicast_ether_addr(addr));
4271                 return -EINVAL;
4272         }
4273
4274         memset(&req, 0, sizeof(req));
4275         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4276
4277         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4278                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4279
4280         req.egress_port = cpu_to_le16(egress_port);
4281
4282         hclge_prepare_mac_addr(&req, addr);
4283
4284         /* Lookup the mac address in the mac_vlan table, and add
4285          * it if the entry is inexistent. Repeated unicast entry
4286          * is not allowed in the mac vlan table.
4287          */
4288         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4289         if (ret == -ENOENT)
4290                 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4291
4292         /* check if we just hit the duplicate */
4293         if (!ret)
4294                 ret = -EINVAL;
4295
4296         dev_err(&hdev->pdev->dev,
4297                 "PF failed to add unicast entry(%pM) in the MAC table\n",
4298                 addr);
4299
4300         return ret;
4301 }
4302
4303 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4304                             const unsigned char *addr)
4305 {
4306         struct hclge_vport *vport = hclge_get_vport(handle);
4307
4308         return hclge_rm_uc_addr_common(vport, addr);
4309 }
4310
4311 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4312                             const unsigned char *addr)
4313 {
4314         struct hclge_dev *hdev = vport->back;
4315         struct hclge_mac_vlan_tbl_entry_cmd req;
4316         int ret;
4317
4318         /* mac addr check */
4319         if (is_zero_ether_addr(addr) ||
4320             is_broadcast_ether_addr(addr) ||
4321             is_multicast_ether_addr(addr)) {
4322                 dev_dbg(&hdev->pdev->dev,
4323                         "Remove mac err! invalid mac:%pM.\n",
4324                          addr);
4325                 return -EINVAL;
4326         }
4327
4328         memset(&req, 0, sizeof(req));
4329         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4330         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4331         hclge_prepare_mac_addr(&req, addr);
4332         ret = hclge_remove_mac_vlan_tbl(vport, &req);
4333
4334         return ret;
4335 }
4336
4337 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4338                              const unsigned char *addr)
4339 {
4340         struct hclge_vport *vport = hclge_get_vport(handle);
4341
4342         return hclge_add_mc_addr_common(vport, addr);
4343 }
4344
4345 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4346                              const unsigned char *addr)
4347 {
4348         struct hclge_dev *hdev = vport->back;
4349         struct hclge_mac_vlan_tbl_entry_cmd req;
4350         struct hclge_desc desc[3];
4351         u16 tbl_idx;
4352         int status;
4353
4354         /* mac addr check */
4355         if (!is_multicast_ether_addr(addr)) {
4356                 dev_err(&hdev->pdev->dev,
4357                         "Add mc mac err! invalid mac:%pM.\n",
4358                          addr);
4359                 return -EINVAL;
4360         }
4361         memset(&req, 0, sizeof(req));
4362         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4363         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4364         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4365         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4366         hclge_prepare_mac_addr(&req, addr);
4367         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4368         if (!status) {
4369                 /* This mac addr exist, update VFID for it */
4370                 hclge_update_desc_vfid(desc, vport->vport_id, false);
4371                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4372         } else {
4373                 /* This mac addr do not exist, add new entry for it */
4374                 memset(desc[0].data, 0, sizeof(desc[0].data));
4375                 memset(desc[1].data, 0, sizeof(desc[0].data));
4376                 memset(desc[2].data, 0, sizeof(desc[0].data));
4377                 hclge_update_desc_vfid(desc, vport->vport_id, false);
4378                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4379         }
4380
4381         /* If mc mac vlan table is full, use MTA table */
4382         if (status == -ENOSPC) {
4383                 if (!vport->accept_mta_mc) {
4384                         status = hclge_cfg_func_mta_filter(hdev,
4385                                                            vport->vport_id,
4386                                                            true);
4387                         if (status) {
4388                                 dev_err(&hdev->pdev->dev,
4389                                         "set mta filter mode fail ret=%d\n",
4390                                         status);
4391                                 return status;
4392                         }
4393                         vport->accept_mta_mc = true;
4394                 }
4395
4396                 /* Set MTA table for this MAC address */
4397                 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4398                 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4399         }
4400
4401         return status;
4402 }
4403
4404 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4405                             const unsigned char *addr)
4406 {
4407         struct hclge_vport *vport = hclge_get_vport(handle);
4408
4409         return hclge_rm_mc_addr_common(vport, addr);
4410 }
4411
4412 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4413                             const unsigned char *addr)
4414 {
4415         struct hclge_dev *hdev = vport->back;
4416         struct hclge_mac_vlan_tbl_entry_cmd req;
4417         enum hclge_cmd_status status;
4418         struct hclge_desc desc[3];
4419
4420         /* mac addr check */
4421         if (!is_multicast_ether_addr(addr)) {
4422                 dev_dbg(&hdev->pdev->dev,
4423                         "Remove mc mac err! invalid mac:%pM.\n",
4424                          addr);
4425                 return -EINVAL;
4426         }
4427
4428         memset(&req, 0, sizeof(req));
4429         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4430         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4431         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4432         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4433         hclge_prepare_mac_addr(&req, addr);
4434         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4435         if (!status) {
4436                 /* This mac addr exist, remove this handle's VFID for it */
4437                 hclge_update_desc_vfid(desc, vport->vport_id, true);
4438
4439                 if (hclge_is_all_function_id_zero(desc))
4440                         /* All the vfid is zero, so need to delete this entry */
4441                         status = hclge_remove_mac_vlan_tbl(vport, &req);
4442                 else
4443                         /* Not all the vfid is zero, update the vfid */
4444                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4445
4446         } else {
4447                 /* Maybe this mac address is in mta table, but it cannot be
4448                  * deleted here because an entry of mta represents an address
4449                  * range rather than a specific address. the delete action to
4450                  * all entries will take effect in update_mta_status called by
4451                  * hns3_nic_set_rx_mode.
4452                  */
4453                 status = 0;
4454         }
4455
4456         return status;
4457 }
4458
4459 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4460                                               u16 cmdq_resp, u8 resp_code)
4461 {
4462 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
4463 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
4464 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
4465 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
4466
4467         int return_status;
4468
4469         if (cmdq_resp) {
4470                 dev_err(&hdev->pdev->dev,
4471                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4472                         cmdq_resp);
4473                 return -EIO;
4474         }
4475
4476         switch (resp_code) {
4477         case HCLGE_ETHERTYPE_SUCCESS_ADD:
4478         case HCLGE_ETHERTYPE_ALREADY_ADD:
4479                 return_status = 0;
4480                 break;
4481         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4482                 dev_err(&hdev->pdev->dev,
4483                         "add mac ethertype failed for manager table overflow.\n");
4484                 return_status = -EIO;
4485                 break;
4486         case HCLGE_ETHERTYPE_KEY_CONFLICT:
4487                 dev_err(&hdev->pdev->dev,
4488                         "add mac ethertype failed for key conflict.\n");
4489                 return_status = -EIO;
4490                 break;
4491         default:
4492                 dev_err(&hdev->pdev->dev,
4493                         "add mac ethertype failed for undefined, code=%d.\n",
4494                         resp_code);
4495                 return_status = -EIO;
4496         }
4497
4498         return return_status;
4499 }
4500
4501 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4502                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
4503 {
4504         struct hclge_desc desc;
4505         u8 resp_code;
4506         u16 retval;
4507         int ret;
4508
4509         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4510         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4511
4512         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4513         if (ret) {
4514                 dev_err(&hdev->pdev->dev,
4515                         "add mac ethertype failed for cmd_send, ret =%d.\n",
4516                         ret);
4517                 return ret;
4518         }
4519
4520         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4521         retval = le16_to_cpu(desc.retval);
4522
4523         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4524 }
4525
4526 static int init_mgr_tbl(struct hclge_dev *hdev)
4527 {
4528         int ret;
4529         int i;
4530
4531         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4532                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4533                 if (ret) {
4534                         dev_err(&hdev->pdev->dev,
4535                                 "add mac ethertype failed, ret =%d.\n",
4536                                 ret);
4537                         return ret;
4538                 }
4539         }
4540
4541         return 0;
4542 }
4543
4544 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4545 {
4546         struct hclge_vport *vport = hclge_get_vport(handle);
4547         struct hclge_dev *hdev = vport->back;
4548
4549         ether_addr_copy(p, hdev->hw.mac.mac_addr);
4550 }
4551
4552 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4553                               bool is_first)
4554 {
4555         const unsigned char *new_addr = (const unsigned char *)p;
4556         struct hclge_vport *vport = hclge_get_vport(handle);
4557         struct hclge_dev *hdev = vport->back;
4558         int ret;
4559
4560         /* mac addr check */
4561         if (is_zero_ether_addr(new_addr) ||
4562             is_broadcast_ether_addr(new_addr) ||
4563             is_multicast_ether_addr(new_addr)) {
4564                 dev_err(&hdev->pdev->dev,
4565                         "Change uc mac err! invalid mac:%p.\n",
4566                          new_addr);
4567                 return -EINVAL;
4568         }
4569
4570         if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
4571                 dev_warn(&hdev->pdev->dev,
4572                          "remove old uc mac address fail.\n");
4573
4574         ret = hclge_add_uc_addr(handle, new_addr);
4575         if (ret) {
4576                 dev_err(&hdev->pdev->dev,
4577                         "add uc mac address fail, ret =%d.\n",
4578                         ret);
4579
4580                 if (!is_first &&
4581                     hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
4582                         dev_err(&hdev->pdev->dev,
4583                                 "restore uc mac address fail.\n");
4584
4585                 return -EIO;
4586         }
4587
4588         ret = hclge_pause_addr_cfg(hdev, new_addr);
4589         if (ret) {
4590                 dev_err(&hdev->pdev->dev,
4591                         "configure mac pause address fail, ret =%d.\n",
4592                         ret);
4593                 return -EIO;
4594         }
4595
4596         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4597
4598         return 0;
4599 }
4600
4601 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4602                                       bool filter_en)
4603 {
4604         struct hclge_vlan_filter_ctrl_cmd *req;
4605         struct hclge_desc desc;
4606         int ret;
4607
4608         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4609
4610         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4611         req->vlan_type = vlan_type;
4612         req->vlan_fe = filter_en;
4613
4614         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4615         if (ret)
4616                 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4617                         ret);
4618
4619         return ret;
4620 }
4621
4622 #define HCLGE_FILTER_TYPE_VF            0
4623 #define HCLGE_FILTER_TYPE_PORT          1
4624
4625 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4626 {
4627         struct hclge_vport *vport = hclge_get_vport(handle);
4628         struct hclge_dev *hdev = vport->back;
4629
4630         hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4631 }
4632
4633 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4634                                     bool is_kill, u16 vlan, u8 qos,
4635                                     __be16 proto)
4636 {
4637 #define HCLGE_MAX_VF_BYTES  16
4638         struct hclge_vlan_filter_vf_cfg_cmd *req0;
4639         struct hclge_vlan_filter_vf_cfg_cmd *req1;
4640         struct hclge_desc desc[2];
4641         u8 vf_byte_val;
4642         u8 vf_byte_off;
4643         int ret;
4644
4645         hclge_cmd_setup_basic_desc(&desc[0],
4646                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4647         hclge_cmd_setup_basic_desc(&desc[1],
4648                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4649
4650         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4651
4652         vf_byte_off = vfid / 8;
4653         vf_byte_val = 1 << (vfid % 8);
4654
4655         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4656         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4657
4658         req0->vlan_id  = cpu_to_le16(vlan);
4659         req0->vlan_cfg = is_kill;
4660
4661         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4662                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4663         else
4664                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4665
4666         ret = hclge_cmd_send(&hdev->hw, desc, 2);
4667         if (ret) {
4668                 dev_err(&hdev->pdev->dev,
4669                         "Send vf vlan command fail, ret =%d.\n",
4670                         ret);
4671                 return ret;
4672         }
4673
4674         if (!is_kill) {
4675 #define HCLGE_VF_VLAN_NO_ENTRY  2
4676                 if (!req0->resp_code || req0->resp_code == 1)
4677                         return 0;
4678
4679                 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4680                         dev_warn(&hdev->pdev->dev,
4681                                  "vf vlan table is full, vf vlan filter is disabled\n");
4682                         return 0;
4683                 }
4684
4685                 dev_err(&hdev->pdev->dev,
4686                         "Add vf vlan filter fail, ret =%d.\n",
4687                         req0->resp_code);
4688         } else {
4689                 if (!req0->resp_code)
4690                         return 0;
4691
4692                 dev_err(&hdev->pdev->dev,
4693                         "Kill vf vlan filter fail, ret =%d.\n",
4694                         req0->resp_code);
4695         }
4696
4697         return -EIO;
4698 }
4699
4700 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4701                                       u16 vlan_id, bool is_kill)
4702 {
4703         struct hclge_vlan_filter_pf_cfg_cmd *req;
4704         struct hclge_desc desc;
4705         u8 vlan_offset_byte_val;
4706         u8 vlan_offset_byte;
4707         u8 vlan_offset_160;
4708         int ret;
4709
4710         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4711
4712         vlan_offset_160 = vlan_id / 160;
4713         vlan_offset_byte = (vlan_id % 160) / 8;
4714         vlan_offset_byte_val = 1 << (vlan_id % 8);
4715
4716         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4717         req->vlan_offset = vlan_offset_160;
4718         req->vlan_cfg = is_kill;
4719         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4720
4721         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4722         if (ret)
4723                 dev_err(&hdev->pdev->dev,
4724                         "port vlan command, send fail, ret =%d.\n", ret);
4725         return ret;
4726 }
4727
4728 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4729                                     u16 vport_id, u16 vlan_id, u8 qos,
4730                                     bool is_kill)
4731 {
4732         u16 vport_idx, vport_num = 0;
4733         int ret;
4734
4735         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4736                                        0, proto);
4737         if (ret) {
4738                 dev_err(&hdev->pdev->dev,
4739                         "Set %d vport vlan filter config fail, ret =%d.\n",
4740                         vport_id, ret);
4741                 return ret;
4742         }
4743
4744         /* vlan 0 may be added twice when 8021q module is enabled */
4745         if (!is_kill && !vlan_id &&
4746             test_bit(vport_id, hdev->vlan_table[vlan_id]))
4747                 return 0;
4748
4749         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
4750                 dev_err(&hdev->pdev->dev,
4751                         "Add port vlan failed, vport %d is already in vlan %d\n",
4752                         vport_id, vlan_id);
4753                 return -EINVAL;
4754         }
4755
4756         if (is_kill &&
4757             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4758                 dev_err(&hdev->pdev->dev,
4759                         "Delete port vlan failed, vport %d is not in vlan %d\n",
4760                         vport_id, vlan_id);
4761                 return -EINVAL;
4762         }
4763
4764         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4765                 vport_num++;
4766
4767         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4768                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4769                                                  is_kill);
4770
4771         return ret;
4772 }
4773
4774 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4775                           u16 vlan_id, bool is_kill)
4776 {
4777         struct hclge_vport *vport = hclge_get_vport(handle);
4778         struct hclge_dev *hdev = vport->back;
4779
4780         return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4781                                         0, is_kill);
4782 }
4783
4784 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4785                                     u16 vlan, u8 qos, __be16 proto)
4786 {
4787         struct hclge_vport *vport = hclge_get_vport(handle);
4788         struct hclge_dev *hdev = vport->back;
4789
4790         if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4791                 return -EINVAL;
4792         if (proto != htons(ETH_P_8021Q))
4793                 return -EPROTONOSUPPORT;
4794
4795         return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
4796 }
4797
4798 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4799 {
4800         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4801         struct hclge_vport_vtag_tx_cfg_cmd *req;
4802         struct hclge_dev *hdev = vport->back;
4803         struct hclge_desc desc;
4804         int status;
4805
4806         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4807
4808         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4809         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4810         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4811         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4812                       vcfg->accept_tag1 ? 1 : 0);
4813         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4814                       vcfg->accept_untag1 ? 1 : 0);
4815         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4816                       vcfg->accept_tag2 ? 1 : 0);
4817         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4818                       vcfg->accept_untag2 ? 1 : 0);
4819         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4820                       vcfg->insert_tag1_en ? 1 : 0);
4821         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4822                       vcfg->insert_tag2_en ? 1 : 0);
4823         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4824
4825         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4826         req->vf_bitmap[req->vf_offset] =
4827                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4828
4829         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4830         if (status)
4831                 dev_err(&hdev->pdev->dev,
4832                         "Send port txvlan cfg command fail, ret =%d\n",
4833                         status);
4834
4835         return status;
4836 }
4837
4838 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4839 {
4840         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4841         struct hclge_vport_vtag_rx_cfg_cmd *req;
4842         struct hclge_dev *hdev = vport->back;
4843         struct hclge_desc desc;
4844         int status;
4845
4846         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4847
4848         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4849         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4850                       vcfg->strip_tag1_en ? 1 : 0);
4851         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4852                       vcfg->strip_tag2_en ? 1 : 0);
4853         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4854                       vcfg->vlan1_vlan_prionly ? 1 : 0);
4855         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4856                       vcfg->vlan2_vlan_prionly ? 1 : 0);
4857
4858         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4859         req->vf_bitmap[req->vf_offset] =
4860                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4861
4862         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4863         if (status)
4864                 dev_err(&hdev->pdev->dev,
4865                         "Send port rxvlan cfg command fail, ret =%d\n",
4866                         status);
4867
4868         return status;
4869 }
4870
4871 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4872 {
4873         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4874         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4875         struct hclge_desc desc;
4876         int status;
4877
4878         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4879         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4880         rx_req->ot_fst_vlan_type =
4881                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4882         rx_req->ot_sec_vlan_type =
4883                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4884         rx_req->in_fst_vlan_type =
4885                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4886         rx_req->in_sec_vlan_type =
4887                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4888
4889         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4890         if (status) {
4891                 dev_err(&hdev->pdev->dev,
4892                         "Send rxvlan protocol type command fail, ret =%d\n",
4893                         status);
4894                 return status;
4895         }
4896
4897         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4898
4899         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4900         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4901         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4902
4903         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4904         if (status)
4905                 dev_err(&hdev->pdev->dev,
4906                         "Send txvlan protocol type command fail, ret =%d\n",
4907                         status);
4908
4909         return status;
4910 }
4911
4912 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4913 {
4914 #define HCLGE_DEF_VLAN_TYPE             0x8100
4915
4916         struct hnae3_handle *handle;
4917         struct hclge_vport *vport;
4918         int ret;
4919         int i;
4920
4921         ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4922         if (ret)
4923                 return ret;
4924
4925         ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
4926         if (ret)
4927                 return ret;
4928
4929         hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4930         hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4931         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4932         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4933         hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4934         hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4935
4936         ret = hclge_set_vlan_protocol_type(hdev);
4937         if (ret)
4938                 return ret;
4939
4940         for (i = 0; i < hdev->num_alloc_vport; i++) {
4941                 vport = &hdev->vport[i];
4942                 vport->txvlan_cfg.accept_tag1 = true;
4943                 vport->txvlan_cfg.accept_untag1 = true;
4944
4945                 /* accept_tag2 and accept_untag2 are not supported on
4946                  * pdev revision(0x20), new revision support them. The
4947                  * value of this two fields will not return error when driver
4948                  * send command to fireware in revision(0x20).
4949                  * This two fields can not configured by user.
4950                  */
4951                 vport->txvlan_cfg.accept_tag2 = true;
4952                 vport->txvlan_cfg.accept_untag2 = true;
4953
4954                 vport->txvlan_cfg.insert_tag1_en = false;
4955                 vport->txvlan_cfg.insert_tag2_en = false;
4956                 vport->txvlan_cfg.default_tag1 = 0;
4957                 vport->txvlan_cfg.default_tag2 = 0;
4958
4959                 ret = hclge_set_vlan_tx_offload_cfg(vport);
4960                 if (ret)
4961                         return ret;
4962
4963                 vport->rxvlan_cfg.strip_tag1_en = false;
4964                 vport->rxvlan_cfg.strip_tag2_en = true;
4965                 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4966                 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4967
4968                 ret = hclge_set_vlan_rx_offload_cfg(vport);
4969                 if (ret)
4970                         return ret;
4971         }
4972
4973         handle = &hdev->vport[0].nic;
4974         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4975 }
4976
4977 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4978 {
4979         struct hclge_vport *vport = hclge_get_vport(handle);
4980
4981         vport->rxvlan_cfg.strip_tag1_en = false;
4982         vport->rxvlan_cfg.strip_tag2_en = enable;
4983         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4984         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4985
4986         return hclge_set_vlan_rx_offload_cfg(vport);
4987 }
4988
4989 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
4990 {
4991         struct hclge_config_max_frm_size_cmd *req;
4992         struct hclge_desc desc;
4993         int max_frm_size;
4994         int ret;
4995
4996         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4997
4998         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4999             max_frm_size > HCLGE_MAC_MAX_FRAME)
5000                 return -EINVAL;
5001
5002         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
5003
5004         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
5005
5006         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
5007         req->max_frm_size = cpu_to_le16(max_frm_size);
5008         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
5009
5010         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5011         if (ret)
5012                 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
5013         else
5014                 hdev->mps = max_frm_size;
5015
5016         return ret;
5017 }
5018
5019 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5020 {
5021         struct hclge_vport *vport = hclge_get_vport(handle);
5022         struct hclge_dev *hdev = vport->back;
5023         int ret;
5024
5025         ret = hclge_set_mac_mtu(hdev, new_mtu);
5026         if (ret) {
5027                 dev_err(&hdev->pdev->dev,
5028                         "Change mtu fail, ret =%d\n", ret);
5029                 return ret;
5030         }
5031
5032         ret = hclge_buffer_alloc(hdev);
5033         if (ret)
5034                 dev_err(&hdev->pdev->dev,
5035                         "Allocate buffer fail, ret =%d\n", ret);
5036
5037         return ret;
5038 }
5039
5040 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5041                                     bool enable)
5042 {
5043         struct hclge_reset_tqp_queue_cmd *req;
5044         struct hclge_desc desc;
5045         int ret;
5046
5047         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5048
5049         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
5050         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5051         hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
5052
5053         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5054         if (ret) {
5055                 dev_err(&hdev->pdev->dev,
5056                         "Send tqp reset cmd error, status =%d\n", ret);
5057                 return ret;
5058         }
5059
5060         return 0;
5061 }
5062
5063 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5064 {
5065         struct hclge_reset_tqp_queue_cmd *req;
5066         struct hclge_desc desc;
5067         int ret;
5068
5069         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5070
5071         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
5072         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5073
5074         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5075         if (ret) {
5076                 dev_err(&hdev->pdev->dev,
5077                         "Get reset status error, status =%d\n", ret);
5078                 return ret;
5079         }
5080
5081         return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
5082 }
5083
5084 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5085                                           u16 queue_id)
5086 {
5087         struct hnae3_queue *queue;
5088         struct hclge_tqp *tqp;
5089
5090         queue = handle->kinfo.tqp[queue_id];
5091         tqp = container_of(queue, struct hclge_tqp, q);
5092
5093         return tqp->index;
5094 }
5095
5096 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
5097 {
5098         struct hclge_vport *vport = hclge_get_vport(handle);
5099         struct hclge_dev *hdev = vport->back;
5100         int reset_try_times = 0;
5101         int reset_status;
5102         u16 queue_gid;
5103         int ret;
5104
5105         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5106                 return;
5107
5108         queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5109
5110         ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5111         if (ret) {
5112                 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5113                 return;
5114         }
5115
5116         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5117         if (ret) {
5118                 dev_warn(&hdev->pdev->dev,
5119                          "Send reset tqp cmd fail, ret = %d\n", ret);
5120                 return;
5121         }
5122
5123         reset_try_times = 0;
5124         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5125                 /* Wait for tqp hw reset */
5126                 msleep(20);
5127                 reset_status = hclge_get_reset_status(hdev, queue_gid);
5128                 if (reset_status)
5129                         break;
5130         }
5131
5132         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5133                 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5134                 return;
5135         }
5136
5137         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5138         if (ret) {
5139                 dev_warn(&hdev->pdev->dev,
5140                          "Deassert the soft reset fail, ret = %d\n", ret);
5141                 return;
5142         }
5143 }
5144
5145 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5146 {
5147         struct hclge_dev *hdev = vport->back;
5148         int reset_try_times = 0;
5149         int reset_status;
5150         u16 queue_gid;
5151         int ret;
5152
5153         queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5154
5155         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5156         if (ret) {
5157                 dev_warn(&hdev->pdev->dev,
5158                          "Send reset tqp cmd fail, ret = %d\n", ret);
5159                 return;
5160         }
5161
5162         reset_try_times = 0;
5163         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5164                 /* Wait for tqp hw reset */
5165                 msleep(20);
5166                 reset_status = hclge_get_reset_status(hdev, queue_gid);
5167                 if (reset_status)
5168                         break;
5169         }
5170
5171         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5172                 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5173                 return;
5174         }
5175
5176         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5177         if (ret)
5178                 dev_warn(&hdev->pdev->dev,
5179                          "Deassert the soft reset fail, ret = %d\n", ret);
5180 }
5181
5182 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5183 {
5184         struct hclge_vport *vport = hclge_get_vport(handle);
5185         struct hclge_dev *hdev = vport->back;
5186
5187         return hdev->fw_version;
5188 }
5189
5190 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5191                                    u32 *flowctrl_adv)
5192 {
5193         struct hclge_vport *vport = hclge_get_vport(handle);
5194         struct hclge_dev *hdev = vport->back;
5195         struct phy_device *phydev = hdev->hw.mac.phydev;
5196
5197         if (!phydev)
5198                 return;
5199
5200         *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5201                          (phydev->advertising & ADVERTISED_Asym_Pause);
5202 }
5203
5204 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5205 {
5206         struct phy_device *phydev = hdev->hw.mac.phydev;
5207
5208         if (!phydev)
5209                 return;
5210
5211         phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5212
5213         if (rx_en)
5214                 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5215
5216         if (tx_en)
5217                 phydev->advertising ^= ADVERTISED_Asym_Pause;
5218 }
5219
5220 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5221 {
5222         int ret;
5223
5224         if (rx_en && tx_en)
5225                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
5226         else if (rx_en && !tx_en)
5227                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
5228         else if (!rx_en && tx_en)
5229                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
5230         else
5231                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
5232
5233         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
5234                 return 0;
5235
5236         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5237         if (ret) {
5238                 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5239                         ret);
5240                 return ret;
5241         }
5242
5243         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
5244
5245         return 0;
5246 }
5247
5248 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5249 {
5250         struct phy_device *phydev = hdev->hw.mac.phydev;
5251         u16 remote_advertising = 0;
5252         u16 local_advertising = 0;
5253         u32 rx_pause, tx_pause;
5254         u8 flowctl;
5255
5256         if (!phydev->link || !phydev->autoneg)
5257                 return 0;
5258
5259         if (phydev->advertising & ADVERTISED_Pause)
5260                 local_advertising = ADVERTISE_PAUSE_CAP;
5261
5262         if (phydev->advertising & ADVERTISED_Asym_Pause)
5263                 local_advertising |= ADVERTISE_PAUSE_ASYM;
5264
5265         if (phydev->pause)
5266                 remote_advertising = LPA_PAUSE_CAP;
5267
5268         if (phydev->asym_pause)
5269                 remote_advertising |= LPA_PAUSE_ASYM;
5270
5271         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5272                                            remote_advertising);
5273         tx_pause = flowctl & FLOW_CTRL_TX;
5274         rx_pause = flowctl & FLOW_CTRL_RX;
5275
5276         if (phydev->duplex == HCLGE_MAC_HALF) {
5277                 tx_pause = 0;
5278                 rx_pause = 0;
5279         }
5280
5281         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5282 }
5283
5284 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5285                                  u32 *rx_en, u32 *tx_en)
5286 {
5287         struct hclge_vport *vport = hclge_get_vport(handle);
5288         struct hclge_dev *hdev = vport->back;
5289
5290         *auto_neg = hclge_get_autoneg(handle);
5291
5292         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5293                 *rx_en = 0;
5294                 *tx_en = 0;
5295                 return;
5296         }
5297
5298         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5299                 *rx_en = 1;
5300                 *tx_en = 0;
5301         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5302                 *tx_en = 1;
5303                 *rx_en = 0;
5304         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5305                 *rx_en = 1;
5306                 *tx_en = 1;
5307         } else {
5308                 *rx_en = 0;
5309                 *tx_en = 0;
5310         }
5311 }
5312
5313 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5314                                 u32 rx_en, u32 tx_en)
5315 {
5316         struct hclge_vport *vport = hclge_get_vport(handle);
5317         struct hclge_dev *hdev = vport->back;
5318         struct phy_device *phydev = hdev->hw.mac.phydev;
5319         u32 fc_autoneg;
5320
5321         fc_autoneg = hclge_get_autoneg(handle);
5322         if (auto_neg != fc_autoneg) {
5323                 dev_info(&hdev->pdev->dev,
5324                          "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5325                 return -EOPNOTSUPP;
5326         }
5327
5328         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5329                 dev_info(&hdev->pdev->dev,
5330                          "Priority flow control enabled. Cannot set link flow control.\n");
5331                 return -EOPNOTSUPP;
5332         }
5333
5334         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5335
5336         if (!fc_autoneg)
5337                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5338
5339         /* Only support flow control negotiation for netdev with
5340          * phy attached for now.
5341          */
5342         if (!phydev)
5343                 return -EOPNOTSUPP;
5344
5345         return phy_start_aneg(phydev);
5346 }
5347
5348 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5349                                           u8 *auto_neg, u32 *speed, u8 *duplex)
5350 {
5351         struct hclge_vport *vport = hclge_get_vport(handle);
5352         struct hclge_dev *hdev = vport->back;
5353
5354         if (speed)
5355                 *speed = hdev->hw.mac.speed;
5356         if (duplex)
5357                 *duplex = hdev->hw.mac.duplex;
5358         if (auto_neg)
5359                 *auto_neg = hdev->hw.mac.autoneg;
5360 }
5361
5362 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5363 {
5364         struct hclge_vport *vport = hclge_get_vport(handle);
5365         struct hclge_dev *hdev = vport->back;
5366
5367         if (media_type)
5368                 *media_type = hdev->hw.mac.media_type;
5369 }
5370
5371 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5372                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5373 {
5374         struct hclge_vport *vport = hclge_get_vport(handle);
5375         struct hclge_dev *hdev = vport->back;
5376         struct phy_device *phydev = hdev->hw.mac.phydev;
5377         int mdix_ctrl, mdix, retval, is_resolved;
5378
5379         if (!phydev) {
5380                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5381                 *tp_mdix = ETH_TP_MDI_INVALID;
5382                 return;
5383         }
5384
5385         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5386
5387         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5388         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5389                                     HCLGE_PHY_MDIX_CTRL_S);
5390
5391         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5392         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5393         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5394
5395         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5396
5397         switch (mdix_ctrl) {
5398         case 0x0:
5399                 *tp_mdix_ctrl = ETH_TP_MDI;
5400                 break;
5401         case 0x1:
5402                 *tp_mdix_ctrl = ETH_TP_MDI_X;
5403                 break;
5404         case 0x3:
5405                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5406                 break;
5407         default:
5408                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5409                 break;
5410         }
5411
5412         if (!is_resolved)
5413                 *tp_mdix = ETH_TP_MDI_INVALID;
5414         else if (mdix)
5415                 *tp_mdix = ETH_TP_MDI_X;
5416         else
5417                 *tp_mdix = ETH_TP_MDI;
5418 }
5419
5420 static int hclge_init_instance_hw(struct hclge_dev *hdev)
5421 {
5422         return hclge_mac_connect_phy(hdev);
5423 }
5424
5425 static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
5426 {
5427         hclge_mac_disconnect_phy(hdev);
5428 }
5429
5430 static int hclge_init_client_instance(struct hnae3_client *client,
5431                                       struct hnae3_ae_dev *ae_dev)
5432 {
5433         struct hclge_dev *hdev = ae_dev->priv;
5434         struct hclge_vport *vport;
5435         int i, ret;
5436
5437         for (i = 0; i <  hdev->num_vmdq_vport + 1; i++) {
5438                 vport = &hdev->vport[i];
5439
5440                 switch (client->type) {
5441                 case HNAE3_CLIENT_KNIC:
5442
5443                         hdev->nic_client = client;
5444                         vport->nic.client = client;
5445                         ret = client->ops->init_instance(&vport->nic);
5446                         if (ret)
5447                                 return ret;
5448
5449                         ret = hclge_init_instance_hw(hdev);
5450                         if (ret) {
5451                                 client->ops->uninit_instance(&vport->nic,
5452                                                              0);
5453                                 return ret;
5454                         }
5455
5456                         if (hdev->roce_client &&
5457                             hnae3_dev_roce_supported(hdev)) {
5458                                 struct hnae3_client *rc = hdev->roce_client;
5459
5460                                 ret = hclge_init_roce_base_info(vport);
5461                                 if (ret)
5462                                         return ret;
5463
5464                                 ret = rc->ops->init_instance(&vport->roce);
5465                                 if (ret)
5466                                         return ret;
5467                         }
5468
5469                         break;
5470                 case HNAE3_CLIENT_UNIC:
5471                         hdev->nic_client = client;
5472                         vport->nic.client = client;
5473
5474                         ret = client->ops->init_instance(&vport->nic);
5475                         if (ret)
5476                                 return ret;
5477
5478                         break;
5479                 case HNAE3_CLIENT_ROCE:
5480                         if (hnae3_dev_roce_supported(hdev)) {
5481                                 hdev->roce_client = client;
5482                                 vport->roce.client = client;
5483                         }
5484
5485                         if (hdev->roce_client && hdev->nic_client) {
5486                                 ret = hclge_init_roce_base_info(vport);
5487                                 if (ret)
5488                                         return ret;
5489
5490                                 ret = client->ops->init_instance(&vport->roce);
5491                                 if (ret)
5492                                         return ret;
5493                         }
5494                 }
5495         }
5496
5497         return 0;
5498 }
5499
5500 static void hclge_uninit_client_instance(struct hnae3_client *client,
5501                                          struct hnae3_ae_dev *ae_dev)
5502 {
5503         struct hclge_dev *hdev = ae_dev->priv;
5504         struct hclge_vport *vport;
5505         int i;
5506
5507         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5508                 vport = &hdev->vport[i];
5509                 if (hdev->roce_client) {
5510                         hdev->roce_client->ops->uninit_instance(&vport->roce,
5511                                                                 0);
5512                         hdev->roce_client = NULL;
5513                         vport->roce.client = NULL;
5514                 }
5515                 if (client->type == HNAE3_CLIENT_ROCE)
5516                         return;
5517                 if (client->ops->uninit_instance) {
5518                         hclge_uninit_instance_hw(hdev);
5519                         client->ops->uninit_instance(&vport->nic, 0);
5520                         hdev->nic_client = NULL;
5521                         vport->nic.client = NULL;
5522                 }
5523         }
5524 }
5525
5526 static int hclge_pci_init(struct hclge_dev *hdev)
5527 {
5528         struct pci_dev *pdev = hdev->pdev;
5529         struct hclge_hw *hw;
5530         int ret;
5531
5532         ret = pci_enable_device(pdev);
5533         if (ret) {
5534                 dev_err(&pdev->dev, "failed to enable PCI device\n");
5535                 return ret;
5536         }
5537
5538         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5539         if (ret) {
5540                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5541                 if (ret) {
5542                         dev_err(&pdev->dev,
5543                                 "can't set consistent PCI DMA");
5544                         goto err_disable_device;
5545                 }
5546                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5547         }
5548
5549         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5550         if (ret) {
5551                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5552                 goto err_disable_device;
5553         }
5554
5555         pci_set_master(pdev);
5556         hw = &hdev->hw;
5557         hw->io_base = pcim_iomap(pdev, 2, 0);
5558         if (!hw->io_base) {
5559                 dev_err(&pdev->dev, "Can't map configuration register space\n");
5560                 ret = -ENOMEM;
5561                 goto err_clr_master;
5562         }
5563
5564         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5565
5566         return 0;
5567 err_clr_master:
5568         pci_clear_master(pdev);
5569         pci_release_regions(pdev);
5570 err_disable_device:
5571         pci_disable_device(pdev);
5572
5573         return ret;
5574 }
5575
5576 static void hclge_pci_uninit(struct hclge_dev *hdev)
5577 {
5578         struct pci_dev *pdev = hdev->pdev;
5579
5580         pcim_iounmap(pdev, hdev->hw.io_base);
5581         pci_free_irq_vectors(pdev);
5582         pci_clear_master(pdev);
5583         pci_release_mem_regions(pdev);
5584         pci_disable_device(pdev);
5585 }
5586
5587 static void hclge_state_init(struct hclge_dev *hdev)
5588 {
5589         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5590         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5591         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5592         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5593         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5594         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5595 }
5596
5597 static void hclge_state_uninit(struct hclge_dev *hdev)
5598 {
5599         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5600
5601         if (hdev->service_timer.function)
5602                 del_timer_sync(&hdev->service_timer);
5603         if (hdev->service_task.func)
5604                 cancel_work_sync(&hdev->service_task);
5605         if (hdev->rst_service_task.func)
5606                 cancel_work_sync(&hdev->rst_service_task);
5607         if (hdev->mbx_service_task.func)
5608                 cancel_work_sync(&hdev->mbx_service_task);
5609 }
5610
5611 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5612 {
5613         struct pci_dev *pdev = ae_dev->pdev;
5614         struct hclge_dev *hdev;
5615         int ret;
5616
5617         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5618         if (!hdev) {
5619                 ret = -ENOMEM;
5620                 goto out;
5621         }
5622
5623         hdev->pdev = pdev;
5624         hdev->ae_dev = ae_dev;
5625         hdev->reset_type = HNAE3_NONE_RESET;
5626         ae_dev->priv = hdev;
5627
5628         ret = hclge_pci_init(hdev);
5629         if (ret) {
5630                 dev_err(&pdev->dev, "PCI init failed\n");
5631                 goto out;
5632         }
5633
5634         /* Firmware command queue initialize */
5635         ret = hclge_cmd_queue_init(hdev);
5636         if (ret) {
5637                 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5638                 goto err_pci_uninit;
5639         }
5640
5641         /* Firmware command initialize */
5642         ret = hclge_cmd_init(hdev);
5643         if (ret)
5644                 goto err_cmd_uninit;
5645
5646         ret = hclge_get_cap(hdev);
5647         if (ret) {
5648                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5649                         ret);
5650                 goto err_cmd_uninit;
5651         }
5652
5653         ret = hclge_configure(hdev);
5654         if (ret) {
5655                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5656                 goto err_cmd_uninit;
5657         }
5658
5659         ret = hclge_init_msi(hdev);
5660         if (ret) {
5661                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
5662                 goto err_cmd_uninit;
5663         }
5664
5665         ret = hclge_misc_irq_init(hdev);
5666         if (ret) {
5667                 dev_err(&pdev->dev,
5668                         "Misc IRQ(vector0) init error, ret = %d.\n",
5669                         ret);
5670                 goto err_msi_uninit;
5671         }
5672
5673         ret = hclge_alloc_tqps(hdev);
5674         if (ret) {
5675                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5676                 goto err_msi_irq_uninit;
5677         }
5678
5679         ret = hclge_alloc_vport(hdev);
5680         if (ret) {
5681                 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5682                 goto err_msi_irq_uninit;
5683         }
5684
5685         ret = hclge_map_tqp(hdev);
5686         if (ret) {
5687                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5688                 goto err_msi_irq_uninit;
5689         }
5690
5691         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5692                 ret = hclge_mac_mdio_config(hdev);
5693                 if (ret) {
5694                         dev_err(&hdev->pdev->dev,
5695                                 "mdio config fail ret=%d\n", ret);
5696                         goto err_msi_irq_uninit;
5697                 }
5698         }
5699
5700         ret = hclge_mac_init(hdev);
5701         if (ret) {
5702                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5703                 goto err_mdiobus_unreg;
5704         }
5705
5706         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5707         if (ret) {
5708                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5709                 goto err_mdiobus_unreg;
5710         }
5711
5712         ret = hclge_init_vlan_config(hdev);
5713         if (ret) {
5714                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5715                 goto err_mdiobus_unreg;
5716         }
5717
5718         ret = hclge_tm_schd_init(hdev);
5719         if (ret) {
5720                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5721                 goto err_mdiobus_unreg;
5722         }
5723
5724         hclge_rss_init_cfg(hdev);
5725         ret = hclge_rss_init_hw(hdev);
5726         if (ret) {
5727                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5728                 goto err_mdiobus_unreg;
5729         }
5730
5731         ret = init_mgr_tbl(hdev);
5732         if (ret) {
5733                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
5734                 goto err_mdiobus_unreg;
5735         }
5736
5737         hclge_dcb_ops_set(hdev);
5738
5739         timer_setup(&hdev->service_timer, hclge_service_timer, 0);
5740         INIT_WORK(&hdev->service_task, hclge_service_task);
5741         INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5742         INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5743
5744         hclge_clear_all_event_cause(hdev);
5745
5746         /* Enable MISC vector(vector0) */
5747         hclge_enable_vector(&hdev->misc_vector, true);
5748
5749         hclge_state_init(hdev);
5750
5751         pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5752         return 0;
5753
5754 err_mdiobus_unreg:
5755         if (hdev->hw.mac.phydev)
5756                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
5757 err_msi_irq_uninit:
5758         hclge_misc_irq_uninit(hdev);
5759 err_msi_uninit:
5760         pci_free_irq_vectors(pdev);
5761 err_cmd_uninit:
5762         hclge_destroy_cmd_queue(&hdev->hw);
5763 err_pci_uninit:
5764         pcim_iounmap(pdev, hdev->hw.io_base);
5765         pci_clear_master(pdev);
5766         pci_release_regions(pdev);
5767         pci_disable_device(pdev);
5768 out:
5769         return ret;
5770 }
5771
5772 static void hclge_stats_clear(struct hclge_dev *hdev)
5773 {
5774         memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5775 }
5776
5777 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5778 {
5779         struct hclge_dev *hdev = ae_dev->priv;
5780         struct pci_dev *pdev = ae_dev->pdev;
5781         int ret;
5782
5783         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5784
5785         hclge_stats_clear(hdev);
5786         memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
5787
5788         ret = hclge_cmd_init(hdev);
5789         if (ret) {
5790                 dev_err(&pdev->dev, "Cmd queue init failed\n");
5791                 return ret;
5792         }
5793
5794         ret = hclge_get_cap(hdev);
5795         if (ret) {
5796                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5797                         ret);
5798                 return ret;
5799         }
5800
5801         ret = hclge_configure(hdev);
5802         if (ret) {
5803                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5804                 return ret;
5805         }
5806
5807         ret = hclge_map_tqp(hdev);
5808         if (ret) {
5809                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5810                 return ret;
5811         }
5812
5813         ret = hclge_mac_init(hdev);
5814         if (ret) {
5815                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5816                 return ret;
5817         }
5818
5819         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5820         if (ret) {
5821                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5822                 return ret;
5823         }
5824
5825         ret = hclge_init_vlan_config(hdev);
5826         if (ret) {
5827                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5828                 return ret;
5829         }
5830
5831         ret = hclge_tm_init_hw(hdev);
5832         if (ret) {
5833                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
5834                 return ret;
5835         }
5836
5837         ret = hclge_rss_init_hw(hdev);
5838         if (ret) {
5839                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5840                 return ret;
5841         }
5842
5843         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5844                  HCLGE_DRIVER_NAME);
5845
5846         return 0;
5847 }
5848
5849 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5850 {
5851         struct hclge_dev *hdev = ae_dev->priv;
5852         struct hclge_mac *mac = &hdev->hw.mac;
5853
5854         hclge_state_uninit(hdev);
5855
5856         if (mac->phydev)
5857                 mdiobus_unregister(mac->mdio_bus);
5858
5859         /* Disable MISC vector(vector0) */
5860         hclge_enable_vector(&hdev->misc_vector, false);
5861         synchronize_irq(hdev->misc_vector.vector_irq);
5862
5863         hclge_destroy_cmd_queue(&hdev->hw);
5864         hclge_misc_irq_uninit(hdev);
5865         hclge_pci_uninit(hdev);
5866         ae_dev->priv = NULL;
5867 }
5868
5869 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5870 {
5871         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5872         struct hclge_vport *vport = hclge_get_vport(handle);
5873         struct hclge_dev *hdev = vport->back;
5874
5875         return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5876 }
5877
5878 static void hclge_get_channels(struct hnae3_handle *handle,
5879                                struct ethtool_channels *ch)
5880 {
5881         struct hclge_vport *vport = hclge_get_vport(handle);
5882
5883         ch->max_combined = hclge_get_max_channels(handle);
5884         ch->other_count = 1;
5885         ch->max_other = 1;
5886         ch->combined_count = vport->alloc_tqps;
5887 }
5888
5889 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5890                                         u16 *free_tqps, u16 *max_rss_size)
5891 {
5892         struct hclge_vport *vport = hclge_get_vport(handle);
5893         struct hclge_dev *hdev = vport->back;
5894         u16 temp_tqps = 0;
5895         int i;
5896
5897         for (i = 0; i < hdev->num_tqps; i++) {
5898                 if (!hdev->htqp[i].alloced)
5899                         temp_tqps++;
5900         }
5901         *free_tqps = temp_tqps;
5902         *max_rss_size = hdev->rss_size_max;
5903 }
5904
5905 static void hclge_release_tqp(struct hclge_vport *vport)
5906 {
5907         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5908         struct hclge_dev *hdev = vport->back;
5909         int i;
5910
5911         for (i = 0; i < kinfo->num_tqps; i++) {
5912                 struct hclge_tqp *tqp =
5913                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
5914
5915                 tqp->q.handle = NULL;
5916                 tqp->q.tqp_index = 0;
5917                 tqp->alloced = false;
5918         }
5919
5920         devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5921         kinfo->tqp = NULL;
5922 }
5923
5924 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5925 {
5926         struct hclge_vport *vport = hclge_get_vport(handle);
5927         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5928         struct hclge_dev *hdev = vport->back;
5929         int cur_rss_size = kinfo->rss_size;
5930         int cur_tqps = kinfo->num_tqps;
5931         u16 tc_offset[HCLGE_MAX_TC_NUM];
5932         u16 tc_valid[HCLGE_MAX_TC_NUM];
5933         u16 tc_size[HCLGE_MAX_TC_NUM];
5934         u16 roundup_size;
5935         u32 *rss_indir;
5936         int ret, i;
5937
5938         /* Free old tqps, and reallocate with new tqp number when nic setup */
5939         hclge_release_tqp(vport);
5940
5941         ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
5942         if (ret) {
5943                 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5944                 return ret;
5945         }
5946
5947         ret = hclge_map_tqp_to_vport(hdev, vport);
5948         if (ret) {
5949                 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5950                 return ret;
5951         }
5952
5953         ret = hclge_tm_schd_init(hdev);
5954         if (ret) {
5955                 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5956                 return ret;
5957         }
5958
5959         roundup_size = roundup_pow_of_two(kinfo->rss_size);
5960         roundup_size = ilog2(roundup_size);
5961         /* Set the RSS TC mode according to the new RSS size */
5962         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5963                 tc_valid[i] = 0;
5964
5965                 if (!(hdev->hw_tc_map & BIT(i)))
5966                         continue;
5967
5968                 tc_valid[i] = 1;
5969                 tc_size[i] = roundup_size;
5970                 tc_offset[i] = kinfo->rss_size * i;
5971         }
5972         ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5973         if (ret)
5974                 return ret;
5975
5976         /* Reinitializes the rss indirect table according to the new RSS size */
5977         rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5978         if (!rss_indir)
5979                 return -ENOMEM;
5980
5981         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5982                 rss_indir[i] = i % kinfo->rss_size;
5983
5984         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5985         if (ret)
5986                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5987                         ret);
5988
5989         kfree(rss_indir);
5990
5991         if (!ret)
5992                 dev_info(&hdev->pdev->dev,
5993                          "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5994                          cur_rss_size, kinfo->rss_size,
5995                          cur_tqps, kinfo->rss_size * kinfo->num_tc);
5996
5997         return ret;
5998 }
5999
6000 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
6001                               u32 *regs_num_64_bit)
6002 {
6003         struct hclge_desc desc;
6004         u32 total_num;
6005         int ret;
6006
6007         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
6008         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6009         if (ret) {
6010                 dev_err(&hdev->pdev->dev,
6011                         "Query register number cmd failed, ret = %d.\n", ret);
6012                 return ret;
6013         }
6014
6015         *regs_num_32_bit = le32_to_cpu(desc.data[0]);
6016         *regs_num_64_bit = le32_to_cpu(desc.data[1]);
6017
6018         total_num = *regs_num_32_bit + *regs_num_64_bit;
6019         if (!total_num)
6020                 return -EINVAL;
6021
6022         return 0;
6023 }
6024
6025 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6026                                  void *data)
6027 {
6028 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6029
6030         struct hclge_desc *desc;
6031         u32 *reg_val = data;
6032         __le32 *desc_data;
6033         int cmd_num;
6034         int i, k, n;
6035         int ret;
6036
6037         if (regs_num == 0)
6038                 return 0;
6039
6040         cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6041         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6042         if (!desc)
6043                 return -ENOMEM;
6044
6045         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6046         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6047         if (ret) {
6048                 dev_err(&hdev->pdev->dev,
6049                         "Query 32 bit register cmd failed, ret = %d.\n", ret);
6050                 kfree(desc);
6051                 return ret;
6052         }
6053
6054         for (i = 0; i < cmd_num; i++) {
6055                 if (i == 0) {
6056                         desc_data = (__le32 *)(&desc[i].data[0]);
6057                         n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6058                 } else {
6059                         desc_data = (__le32 *)(&desc[i]);
6060                         n = HCLGE_32_BIT_REG_RTN_DATANUM;
6061                 }
6062                 for (k = 0; k < n; k++) {
6063                         *reg_val++ = le32_to_cpu(*desc_data++);
6064
6065                         regs_num--;
6066                         if (!regs_num)
6067                                 break;
6068                 }
6069         }
6070
6071         kfree(desc);
6072         return 0;
6073 }
6074
6075 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6076                                  void *data)
6077 {
6078 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6079
6080         struct hclge_desc *desc;
6081         u64 *reg_val = data;
6082         __le64 *desc_data;
6083         int cmd_num;
6084         int i, k, n;
6085         int ret;
6086
6087         if (regs_num == 0)
6088                 return 0;
6089
6090         cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6091         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6092         if (!desc)
6093                 return -ENOMEM;
6094
6095         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6096         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6097         if (ret) {
6098                 dev_err(&hdev->pdev->dev,
6099                         "Query 64 bit register cmd failed, ret = %d.\n", ret);
6100                 kfree(desc);
6101                 return ret;
6102         }
6103
6104         for (i = 0; i < cmd_num; i++) {
6105                 if (i == 0) {
6106                         desc_data = (__le64 *)(&desc[i].data[0]);
6107                         n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6108                 } else {
6109                         desc_data = (__le64 *)(&desc[i]);
6110                         n = HCLGE_64_BIT_REG_RTN_DATANUM;
6111                 }
6112                 for (k = 0; k < n; k++) {
6113                         *reg_val++ = le64_to_cpu(*desc_data++);
6114
6115                         regs_num--;
6116                         if (!regs_num)
6117                                 break;
6118                 }
6119         }
6120
6121         kfree(desc);
6122         return 0;
6123 }
6124
6125 static int hclge_get_regs_len(struct hnae3_handle *handle)
6126 {
6127         struct hclge_vport *vport = hclge_get_vport(handle);
6128         struct hclge_dev *hdev = vport->back;
6129         u32 regs_num_32_bit, regs_num_64_bit;
6130         int ret;
6131
6132         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6133         if (ret) {
6134                 dev_err(&hdev->pdev->dev,
6135                         "Get register number failed, ret = %d.\n", ret);
6136                 return -EOPNOTSUPP;
6137         }
6138
6139         return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6140 }
6141
6142 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6143                            void *data)
6144 {
6145         struct hclge_vport *vport = hclge_get_vport(handle);
6146         struct hclge_dev *hdev = vport->back;
6147         u32 regs_num_32_bit, regs_num_64_bit;
6148         int ret;
6149
6150         *version = hdev->fw_version;
6151
6152         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6153         if (ret) {
6154                 dev_err(&hdev->pdev->dev,
6155                         "Get register number failed, ret = %d.\n", ret);
6156                 return;
6157         }
6158
6159         ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6160         if (ret) {
6161                 dev_err(&hdev->pdev->dev,
6162                         "Get 32 bit register failed, ret = %d.\n", ret);
6163                 return;
6164         }
6165
6166         data = (u32 *)data + regs_num_32_bit;
6167         ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6168                                     data);
6169         if (ret)
6170                 dev_err(&hdev->pdev->dev,
6171                         "Get 64 bit register failed, ret = %d.\n", ret);
6172 }
6173
6174 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
6175 {
6176         struct hclge_set_led_state_cmd *req;
6177         struct hclge_desc desc;
6178         int ret;
6179
6180         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6181
6182         req = (struct hclge_set_led_state_cmd *)desc.data;
6183         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
6184                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6185
6186         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6187         if (ret)
6188                 dev_err(&hdev->pdev->dev,
6189                         "Send set led state cmd error, ret =%d\n", ret);
6190
6191         return ret;
6192 }
6193
6194 enum hclge_led_status {
6195         HCLGE_LED_OFF,
6196         HCLGE_LED_ON,
6197         HCLGE_LED_NO_CHANGE = 0xFF,
6198 };
6199
6200 static int hclge_set_led_id(struct hnae3_handle *handle,
6201                             enum ethtool_phys_id_state status)
6202 {
6203         struct hclge_vport *vport = hclge_get_vport(handle);
6204         struct hclge_dev *hdev = vport->back;
6205
6206         switch (status) {
6207         case ETHTOOL_ID_ACTIVE:
6208                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
6209         case ETHTOOL_ID_INACTIVE:
6210                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
6211         default:
6212                 return -EINVAL;
6213         }
6214 }
6215
6216 static void hclge_get_link_mode(struct hnae3_handle *handle,
6217                                 unsigned long *supported,
6218                                 unsigned long *advertising)
6219 {
6220         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6221         struct hclge_vport *vport = hclge_get_vport(handle);
6222         struct hclge_dev *hdev = vport->back;
6223         unsigned int idx = 0;
6224
6225         for (; idx < size; idx++) {
6226                 supported[idx] = hdev->hw.mac.supported[idx];
6227                 advertising[idx] = hdev->hw.mac.advertising[idx];
6228         }
6229 }
6230
6231 static void hclge_get_port_type(struct hnae3_handle *handle,
6232                                 u8 *port_type)
6233 {
6234         struct hclge_vport *vport = hclge_get_vport(handle);
6235         struct hclge_dev *hdev = vport->back;
6236         u8 media_type = hdev->hw.mac.media_type;
6237
6238         switch (media_type) {
6239         case HNAE3_MEDIA_TYPE_FIBER:
6240                 *port_type = PORT_FIBRE;
6241                 break;
6242         case HNAE3_MEDIA_TYPE_COPPER:
6243                 *port_type = PORT_TP;
6244                 break;
6245         case HNAE3_MEDIA_TYPE_UNKNOWN:
6246         default:
6247                 *port_type = PORT_OTHER;
6248                 break;
6249         }
6250 }
6251
6252 static const struct hnae3_ae_ops hclge_ops = {
6253         .init_ae_dev = hclge_init_ae_dev,
6254         .uninit_ae_dev = hclge_uninit_ae_dev,
6255         .init_client_instance = hclge_init_client_instance,
6256         .uninit_client_instance = hclge_uninit_client_instance,
6257         .map_ring_to_vector = hclge_map_ring_to_vector,
6258         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
6259         .get_vector = hclge_get_vector,
6260         .put_vector = hclge_put_vector,
6261         .set_promisc_mode = hclge_set_promisc_mode,
6262         .set_loopback = hclge_set_loopback,
6263         .start = hclge_ae_start,
6264         .stop = hclge_ae_stop,
6265         .get_status = hclge_get_status,
6266         .get_ksettings_an_result = hclge_get_ksettings_an_result,
6267         .update_speed_duplex_h = hclge_update_speed_duplex_h,
6268         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6269         .get_media_type = hclge_get_media_type,
6270         .get_rss_key_size = hclge_get_rss_key_size,
6271         .get_rss_indir_size = hclge_get_rss_indir_size,
6272         .get_rss = hclge_get_rss,
6273         .set_rss = hclge_set_rss,
6274         .set_rss_tuple = hclge_set_rss_tuple,
6275         .get_rss_tuple = hclge_get_rss_tuple,
6276         .get_tc_size = hclge_get_tc_size,
6277         .get_mac_addr = hclge_get_mac_addr,
6278         .set_mac_addr = hclge_set_mac_addr,
6279         .add_uc_addr = hclge_add_uc_addr,
6280         .rm_uc_addr = hclge_rm_uc_addr,
6281         .add_mc_addr = hclge_add_mc_addr,
6282         .rm_mc_addr = hclge_rm_mc_addr,
6283         .update_mta_status = hclge_update_mta_status,
6284         .set_autoneg = hclge_set_autoneg,
6285         .get_autoneg = hclge_get_autoneg,
6286         .get_pauseparam = hclge_get_pauseparam,
6287         .set_pauseparam = hclge_set_pauseparam,
6288         .set_mtu = hclge_set_mtu,
6289         .reset_queue = hclge_reset_tqp,
6290         .get_stats = hclge_get_stats,
6291         .update_stats = hclge_update_stats,
6292         .get_strings = hclge_get_strings,
6293         .get_sset_count = hclge_get_sset_count,
6294         .get_fw_version = hclge_get_fw_version,
6295         .get_mdix_mode = hclge_get_mdix_mode,
6296         .enable_vlan_filter = hclge_enable_vlan_filter,
6297         .set_vlan_filter = hclge_set_vlan_filter,
6298         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
6299         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
6300         .reset_event = hclge_reset_event,
6301         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6302         .set_channels = hclge_set_channels,
6303         .get_channels = hclge_get_channels,
6304         .get_flowctrl_adv = hclge_get_flowctrl_adv,
6305         .get_regs_len = hclge_get_regs_len,
6306         .get_regs = hclge_get_regs,
6307         .set_led_id = hclge_set_led_id,
6308         .get_link_mode = hclge_get_link_mode,
6309         .get_port_type = hclge_get_port_type,
6310 };
6311
6312 static struct hnae3_ae_algo ae_algo = {
6313         .ops = &hclge_ops,
6314         .pdev_id_table = ae_algo_pci_tbl,
6315 };
6316
6317 static int hclge_init(void)
6318 {
6319         pr_info("%s is initializing\n", HCLGE_NAME);
6320
6321         hnae3_register_ae_algo(&ae_algo);
6322
6323         return 0;
6324 }
6325
6326 static void hclge_exit(void)
6327 {
6328         hnae3_unregister_ae_algo(&ae_algo);
6329 }
6330 module_init(hclge_init);
6331 module_exit(hclge_exit);
6332
6333 MODULE_LICENSE("GPL");
6334 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6335 MODULE_DESCRIPTION("HCLGE Driver");
6336 MODULE_VERSION(HCLGE_MOD_VERSION);