drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <net/rtnetlink.h>
  16 #include "hclge_cmd.h"
  17 #include "hclge_dcb.h"
  18 #include "hclge_main.h"
  19 #include "hclge_mbx.h"
  20 #include "hclge_mdio.h"
  21 #include "hclge_tm.h"
  22 #include "hclge_err.h"
  23 #include "hnae3.h"
  24
  25 #define HCLGE_NAME                      "hclge"
  26 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  27 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
  28
  29 #define HCLGE_BUF_SIZE_UNIT     256
  30
  31 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
  32 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  33 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  34 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
  35                                u16 *allocated_size, bool is_alloc);
  36
  37 static struct hnae3_ae_algo ae_algo;
  38
  39 static const struct pci_device_id ae_algo_pci_tbl[] = {
  40         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  41         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  42         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  43         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  44         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  45         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  46         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  47         /* required last entry */
  48         {0, }
  49 };
  50
  51 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  52
  53 static const u32 cmdq_reg_addr_list[] = {HCLGE_CMDQ_TX_ADDR_L_REG,
  54                                          HCLGE_CMDQ_TX_ADDR_H_REG,
  55                                          HCLGE_CMDQ_TX_DEPTH_REG,
  56                                          HCLGE_CMDQ_TX_TAIL_REG,
  57                                          HCLGE_CMDQ_TX_HEAD_REG,
  58                                          HCLGE_CMDQ_RX_ADDR_L_REG,
  59                                          HCLGE_CMDQ_RX_ADDR_H_REG,
  60                                          HCLGE_CMDQ_RX_DEPTH_REG,
  61                                          HCLGE_CMDQ_RX_TAIL_REG,
  62                                          HCLGE_CMDQ_RX_HEAD_REG,
  63                                          HCLGE_VECTOR0_CMDQ_SRC_REG,
  64                                          HCLGE_CMDQ_INTR_STS_REG,
  65                                          HCLGE_CMDQ_INTR_EN_REG,
  66                                          HCLGE_CMDQ_INTR_GEN_REG};
  67
  68 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
  69                                            HCLGE_VECTOR0_OTER_EN_REG,
  70                                            HCLGE_MISC_RESET_STS_REG,
  71                                            HCLGE_MISC_VECTOR_INT_STS,
  72                                            HCLGE_GLOBAL_RESET_REG,
  73                                            HCLGE_FUN_RST_ING,
  74                                            HCLGE_GRO_EN_REG};
  75
  76 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG,
  77                                          HCLGE_RING_RX_ADDR_H_REG,
  78                                          HCLGE_RING_RX_BD_NUM_REG,
  79                                          HCLGE_RING_RX_BD_LENGTH_REG,
  80                                          HCLGE_RING_RX_MERGE_EN_REG,
  81                                          HCLGE_RING_RX_TAIL_REG,
  82                                          HCLGE_RING_RX_HEAD_REG,
  83                                          HCLGE_RING_RX_FBD_NUM_REG,
  84                                          HCLGE_RING_RX_OFFSET_REG,
  85                                          HCLGE_RING_RX_FBD_OFFSET_REG,
  86                                          HCLGE_RING_RX_STASH_REG,
  87                                          HCLGE_RING_RX_BD_ERR_REG,
  88                                          HCLGE_RING_TX_ADDR_L_REG,
  89                                          HCLGE_RING_TX_ADDR_H_REG,
  90                                          HCLGE_RING_TX_BD_NUM_REG,
  91                                          HCLGE_RING_TX_PRIORITY_REG,
  92                                          HCLGE_RING_TX_TC_REG,
  93                                          HCLGE_RING_TX_MERGE_EN_REG,
  94                                          HCLGE_RING_TX_TAIL_REG,
  95                                          HCLGE_RING_TX_HEAD_REG,
  96                                          HCLGE_RING_TX_FBD_NUM_REG,
  97                                          HCLGE_RING_TX_OFFSET_REG,
  98                                          HCLGE_RING_TX_EBD_NUM_REG,
  99                                          HCLGE_RING_TX_EBD_OFFSET_REG,
 100                                          HCLGE_RING_TX_BD_ERR_REG,
 101                                          HCLGE_RING_EN_REG};
 102
 103 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
 104                                              HCLGE_TQP_INTR_GL0_REG,
 105                                              HCLGE_TQP_INTR_GL1_REG,
 106                                              HCLGE_TQP_INTR_GL2_REG,
 107                                              HCLGE_TQP_INTR_RL_REG};
 108
 109 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
 110         "App    Loopback test",
 111         "Serdes serial Loopback test",
 112         "Serdes parallel Loopback test",
 113         "Phy    Loopback test"
 114 };
 115
 116 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
 117         {"mac_tx_mac_pause_num",
 118                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
 119         {"mac_rx_mac_pause_num",
 120                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
 121         {"mac_tx_control_pkt_num",
 122                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)},
 123         {"mac_rx_control_pkt_num",
 124                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)},
 125         {"mac_tx_pfc_pkt_num",
 126                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)},
 127         {"mac_tx_pfc_pri0_pkt_num",
 128                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
 129         {"mac_tx_pfc_pri1_pkt_num",
 130                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
 131         {"mac_tx_pfc_pri2_pkt_num",
 132                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
 133         {"mac_tx_pfc_pri3_pkt_num",
 134                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
 135         {"mac_tx_pfc_pri4_pkt_num",
 136                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
 137         {"mac_tx_pfc_pri5_pkt_num",
 138                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
 139         {"mac_tx_pfc_pri6_pkt_num",
 140                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
 141         {"mac_tx_pfc_pri7_pkt_num",
 142                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
 143         {"mac_rx_pfc_pkt_num",
 144                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)},
 145         {"mac_rx_pfc_pri0_pkt_num",
 146                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
 147         {"mac_rx_pfc_pri1_pkt_num",
 148                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
 149         {"mac_rx_pfc_pri2_pkt_num",
 150                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
 151         {"mac_rx_pfc_pri3_pkt_num",
 152                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
 153         {"mac_rx_pfc_pri4_pkt_num",
 154                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
 155         {"mac_rx_pfc_pri5_pkt_num",
 156                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
 157         {"mac_rx_pfc_pri6_pkt_num",
 158                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
 159         {"mac_rx_pfc_pri7_pkt_num",
 160                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
 161         {"mac_tx_total_pkt_num",
 162                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
 163         {"mac_tx_total_oct_num",
 164                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
 165         {"mac_tx_good_pkt_num",
 166                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 167         {"mac_tx_bad_pkt_num",
 168                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 169         {"mac_tx_good_oct_num",
 170                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 171         {"mac_tx_bad_oct_num",
 172                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 173         {"mac_tx_uni_pkt_num",
 174                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 175         {"mac_tx_multi_pkt_num",
 176                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 177         {"mac_tx_broad_pkt_num",
 178                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 179         {"mac_tx_undersize_pkt_num",
 180                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 181         {"mac_tx_oversize_pkt_num",
 182                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 183         {"mac_tx_64_oct_pkt_num",
 184                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 185         {"mac_tx_65_127_oct_pkt_num",
 186                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 187         {"mac_tx_128_255_oct_pkt_num",
 188                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 189         {"mac_tx_256_511_oct_pkt_num",
 190                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 191         {"mac_tx_512_1023_oct_pkt_num",
 192                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 193         {"mac_tx_1024_1518_oct_pkt_num",
 194                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 195         {"mac_tx_1519_2047_oct_pkt_num",
 196                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 197         {"mac_tx_2048_4095_oct_pkt_num",
 198                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 199         {"mac_tx_4096_8191_oct_pkt_num",
 200                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 201         {"mac_tx_8192_9216_oct_pkt_num",
 202                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 203         {"mac_tx_9217_12287_oct_pkt_num",
 204                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 205         {"mac_tx_12288_16383_oct_pkt_num",
 206                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 207         {"mac_tx_1519_max_good_pkt_num",
 208                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 209         {"mac_tx_1519_max_bad_pkt_num",
 210                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 211         {"mac_rx_total_pkt_num",
 212                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 213         {"mac_rx_total_oct_num",
 214                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 215         {"mac_rx_good_pkt_num",
 216                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 217         {"mac_rx_bad_pkt_num",
 218                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 219         {"mac_rx_good_oct_num",
 220                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 221         {"mac_rx_bad_oct_num",
 222                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 223         {"mac_rx_uni_pkt_num",
 224                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 225         {"mac_rx_multi_pkt_num",
 226                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 227         {"mac_rx_broad_pkt_num",
 228                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 229         {"mac_rx_undersize_pkt_num",
 230                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 231         {"mac_rx_oversize_pkt_num",
 232                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 233         {"mac_rx_64_oct_pkt_num",
 234                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 235         {"mac_rx_65_127_oct_pkt_num",
 236                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 237         {"mac_rx_128_255_oct_pkt_num",
 238                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 239         {"mac_rx_256_511_oct_pkt_num",
 240                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 241         {"mac_rx_512_1023_oct_pkt_num",
 242                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 243         {"mac_rx_1024_1518_oct_pkt_num",
 244                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 245         {"mac_rx_1519_2047_oct_pkt_num",
 246                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 247         {"mac_rx_2048_4095_oct_pkt_num",
 248                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 249         {"mac_rx_4096_8191_oct_pkt_num",
 250                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 251         {"mac_rx_8192_9216_oct_pkt_num",
 252                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 253         {"mac_rx_9217_12287_oct_pkt_num",
 254                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 255         {"mac_rx_12288_16383_oct_pkt_num",
 256                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 257         {"mac_rx_1519_max_good_pkt_num",
 258                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 259         {"mac_rx_1519_max_bad_pkt_num",
 260                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 261
 262         {"mac_tx_fragment_pkt_num",
 263                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 264         {"mac_tx_undermin_pkt_num",
 265                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 266         {"mac_tx_jabber_pkt_num",
 267                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 268         {"mac_tx_err_all_pkt_num",
 269                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 270         {"mac_tx_from_app_good_pkt_num",
 271                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 272         {"mac_tx_from_app_bad_pkt_num",
 273                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 274         {"mac_rx_fragment_pkt_num",
 275                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 276         {"mac_rx_undermin_pkt_num",
 277                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 278         {"mac_rx_jabber_pkt_num",
 279                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 280         {"mac_rx_fcs_err_pkt_num",
 281                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 282         {"mac_rx_send_app_good_pkt_num",
 283                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 284         {"mac_rx_send_app_bad_pkt_num",
 285                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 286 };
 287
 288 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 289         {
 290                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 291                 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
 292                 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
 293                 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
 294                 .i_port_bitmap = 0x1,
 295         },
 296 };
 297
 298 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
 299 {
 300 #define HCLGE_MAC_CMD_NUM 21
 301
 302         u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
 303         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 304         __le64 *desc_data;
 305         int i, k, n;
 306         int ret;
 307
 308         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 309         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 310         if (ret) {
 311                 dev_err(&hdev->pdev->dev,
 312                         "Get MAC pkt stats fail, status = %d.\n", ret);
 313
 314                 return ret;
 315         }
 316
 317         for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
 318                 /* for special opcode 0032, only the first desc has the head */
 319                 if (unlikely(i == 0)) {
 320                         desc_data = (__le64 *)(&desc[i].data[0]);
 321                         n = HCLGE_RD_FIRST_STATS_NUM;
 322                 } else {
 323                         desc_data = (__le64 *)(&desc[i]);
 324                         n = HCLGE_RD_OTHER_STATS_NUM;
 325                 }
 326
 327                 for (k = 0; k < n; k++) {
 328                         *data += le64_to_cpu(*desc_data);
 329                         data++;
 330                         desc_data++;
 331                 }
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev, u32 desc_num)
 338 {
 339         u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
 340         struct hclge_desc *desc;
 341         __le64 *desc_data;
 342         u16 i, k, n;
 343         int ret;
 344
 345         desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_KERNEL);
 346         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true);
 347         ret = hclge_cmd_send(&hdev->hw, desc, desc_num);
 348         if (ret) {
 349                 kfree(desc);
 350                 return ret;
 351         }
 352
 353         for (i = 0; i < desc_num; i++) {
 354                 /* for special opcode 0034, only the first desc has the head */
 355                 if (i == 0) {
 356                         desc_data = (__le64 *)(&desc[i].data[0]);
 357                         n = HCLGE_RD_FIRST_STATS_NUM;
 358                 } else {
 359                         desc_data = (__le64 *)(&desc[i]);
 360                         n = HCLGE_RD_OTHER_STATS_NUM;
 361                 }
 362
 363                 for (k = 0; k < n; k++) {
 364                         *data += le64_to_cpu(*desc_data);
 365                         data++;
 366                         desc_data++;
 367                 }
 368         }
 369
 370         kfree(desc);
 371
 372         return 0;
 373 }
 374
 375 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *desc_num)
 376 {
 377         struct hclge_desc desc;
 378         __le32 *desc_data;
 379         u32 reg_num;
 380         int ret;
 381
 382         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
 383         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 384         if (ret)
 385                 return ret;
 386
 387         desc_data = (__le32 *)(&desc.data[0]);
 388         reg_num = le32_to_cpu(*desc_data);
 389
 390         *desc_num = 1 + ((reg_num - 3) >> 2) +
 391                     (u32)(((reg_num - 3) & 0x3) ? 1 : 0);
 392
 393         return 0;
 394 }
 395
 396 static int hclge_mac_update_stats(struct hclge_dev *hdev)
 397 {
 398         u32 desc_num;
 399         int ret;
 400
 401         ret = hclge_mac_query_reg_num(hdev, &desc_num);
 402
 403         /* The firmware supports the new statistics acquisition method */
 404         if (!ret)
 405                 ret = hclge_mac_update_stats_complete(hdev, desc_num);
 406         else if (ret == -EOPNOTSUPP)
 407                 ret = hclge_mac_update_stats_defective(hdev);
 408         else
 409                 dev_err(&hdev->pdev->dev, "query mac reg num fail!\n");
 410
 411         return ret;
 412 }
 413
 414 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
 415 {
 416         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 417         struct hclge_vport *vport = hclge_get_vport(handle);
 418         struct hclge_dev *hdev = vport->back;
 419         struct hnae3_queue *queue;
 420         struct hclge_desc desc[1];
 421         struct hclge_tqp *tqp;
 422         int ret, i;
 423
 424         for (i = 0; i < kinfo->num_tqps; i++) {
 425                 queue = handle->kinfo.tqp[i];
 426                 tqp = container_of(queue, struct hclge_tqp, q);
 427                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 428                 hclge_cmd_setup_basic_desc(&desc[0],
 429                                            HCLGE_OPC_QUERY_RX_STATUS,
 430                                            true);
 431
 432                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 433                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 434                 if (ret) {
 435                         dev_err(&hdev->pdev->dev,
 436                                 "Query tqp stat fail, status = %d,queue = %d\n",
 437                                 ret,    i);
 438                         return ret;
 439                 }
 440                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 441                         le32_to_cpu(desc[0].data[1]);
 442         }
 443
 444         for (i = 0; i < kinfo->num_tqps; i++) {
 445                 queue = handle->kinfo.tqp[i];
 446                 tqp = container_of(queue, struct hclge_tqp, q);
 447                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 448                 hclge_cmd_setup_basic_desc(&desc[0],
 449                                            HCLGE_OPC_QUERY_TX_STATUS,
 450                                            true);
 451
 452                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 453                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 454                 if (ret) {
 455                         dev_err(&hdev->pdev->dev,
 456                                 "Query tqp stat fail, status = %d,queue = %d\n",
 457                                 ret, i);
 458                         return ret;
 459                 }
 460                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 461                         le32_to_cpu(desc[0].data[1]);
 462         }
 463
 464         return 0;
 465 }
 466
 467 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 468 {
 469         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 470         struct hclge_tqp *tqp;
 471         u64 *buff = data;
 472         int i;
 473
 474         for (i = 0; i < kinfo->num_tqps; i++) {
 475                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 476                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 477         }
 478
 479         for (i = 0; i < kinfo->num_tqps; i++) {
 480                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 481                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 482         }
 483
 484         return buff;
 485 }
 486
 487 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
 488 {
 489         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 490
 491         return kinfo->num_tqps * (2);
 492 }
 493
 494 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 495 {
 496         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 497         u8 *buff = data;
 498         int i = 0;
 499
 500         for (i = 0; i < kinfo->num_tqps; i++) {
 501                 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
 502                         struct hclge_tqp, q);
 503                 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
 504                          tqp->index);
 505                 buff = buff + ETH_GSTRING_LEN;
 506         }
 507
 508         for (i = 0; i < kinfo->num_tqps; i++) {
 509                 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
 510                         struct hclge_tqp, q);
 511                 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
 512                          tqp->index);
 513                 buff = buff + ETH_GSTRING_LEN;
 514         }
 515
 516         return buff;
 517 }
 518
 519 static u64 *hclge_comm_get_stats(void *comm_stats,
 520                                  const struct hclge_comm_stats_str strs[],
 521                                  int size, u64 *data)
 522 {
 523         u64 *buf = data;
 524         u32 i;
 525
 526         for (i = 0; i < size; i++)
 527                 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
 528
 529         return buf + size;
 530 }
 531
 532 static u8 *hclge_comm_get_strings(u32 stringset,
 533                                   const struct hclge_comm_stats_str strs[],
 534                                   int size, u8 *data)
 535 {
 536         char *buff = (char *)data;
 537         u32 i;
 538
 539         if (stringset != ETH_SS_STATS)
 540                 return buff;
 541
 542         for (i = 0; i < size; i++) {
 543                 snprintf(buff, ETH_GSTRING_LEN,
 544                          strs[i].desc);
 545                 buff = buff + ETH_GSTRING_LEN;
 546         }
 547
 548         return (u8 *)buff;
 549 }
 550
 551 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 552 {
 553         struct hnae3_handle *handle;
 554         int status;
 555
 556         handle = &hdev->vport[0].nic;
 557         if (handle->client) {
 558                 status = hclge_tqps_update_stats(handle);
 559                 if (status) {
 560                         dev_err(&hdev->pdev->dev,
 561                                 "Update TQPS stats fail, status = %d.\n",
 562                                 status);
 563                 }
 564         }
 565
 566         status = hclge_mac_update_stats(hdev);
 567         if (status)
 568                 dev_err(&hdev->pdev->dev,
 569                         "Update MAC stats fail, status = %d.\n", status);
 570 }
 571
 572 static void hclge_update_stats(struct hnae3_handle *handle,
 573                                struct net_device_stats *net_stats)
 574 {
 575         struct hclge_vport *vport = hclge_get_vport(handle);
 576         struct hclge_dev *hdev = vport->back;
 577         int status;
 578
 579         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 580                 return;
 581
 582         status = hclge_mac_update_stats(hdev);
 583         if (status)
 584                 dev_err(&hdev->pdev->dev,
 585                         "Update MAC stats fail, status = %d.\n",
 586                         status);
 587
 588         status = hclge_tqps_update_stats(handle);
 589         if (status)
 590                 dev_err(&hdev->pdev->dev,
 591                         "Update TQPS stats fail, status = %d.\n",
 592                         status);
 593
 594         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 595 }
 596
 597 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 598 {
 599 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
 600                 HNAE3_SUPPORT_PHY_LOOPBACK |\
 601                 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
 602                 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
 603
 604         struct hclge_vport *vport = hclge_get_vport(handle);
 605         struct hclge_dev *hdev = vport->back;
 606         int count = 0;
 607
 608         /* Loopback test support rules:
 609          * mac: only GE mode support
 610          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 611          * phy: only support when phy device exist on board
 612          */
 613         if (stringset == ETH_SS_TEST) {
 614                 /* clear loopback bit flags at first */
 615                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 616                 if (hdev->pdev->revision >= 0x21 ||
 617                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 618                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 619                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 620                         count += 1;
 621                         handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
 622                 }
 623
 624                 count += 2;
 625                 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 626                 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
 627         } else if (stringset == ETH_SS_STATS) {
 628                 count = ARRAY_SIZE(g_mac_stats_string) +
 629                         hclge_tqps_get_sset_count(handle, stringset);
 630         }
 631
 632         return count;
 633 }
 634
 635 static void hclge_get_strings(struct hnae3_handle *handle,
 636                               u32 stringset,
 637                               u8 *data)
 638 {
 639         u8 *p = (char *)data;
 640         int size;
 641
 642         if (stringset == ETH_SS_STATS) {
 643                 size = ARRAY_SIZE(g_mac_stats_string);
 644                 p = hclge_comm_get_strings(stringset,
 645                                            g_mac_stats_string,
 646                                            size,
 647                                            p);
 648                 p = hclge_tqps_get_strings(handle, p);
 649         } else if (stringset == ETH_SS_TEST) {
 650                 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
 651                         memcpy(p,
 652                                hns3_nic_test_strs[HNAE3_LOOP_APP],
 653                                ETH_GSTRING_LEN);
 654                         p += ETH_GSTRING_LEN;
 655                 }
 656                 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
 657                         memcpy(p,
 658                                hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
 659                                ETH_GSTRING_LEN);
 660                         p += ETH_GSTRING_LEN;
 661                 }
 662                 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
 663                         memcpy(p,
 664                                hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
 665                                ETH_GSTRING_LEN);
 666                         p += ETH_GSTRING_LEN;
 667                 }
 668                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 669                         memcpy(p,
 670                                hns3_nic_test_strs[HNAE3_LOOP_PHY],
 671                                ETH_GSTRING_LEN);
 672                         p += ETH_GSTRING_LEN;
 673                 }
 674         }
 675 }
 676
 677 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 678 {
 679         struct hclge_vport *vport = hclge_get_vport(handle);
 680         struct hclge_dev *hdev = vport->back;
 681         u64 *p;
 682
 683         p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
 684                                  g_mac_stats_string,
 685                                  ARRAY_SIZE(g_mac_stats_string),
 686                                  data);
 687         p = hclge_tqps_get_stats(handle, p);
 688 }
 689
 690 static int hclge_parse_func_status(struct hclge_dev *hdev,
 691                                    struct hclge_func_status_cmd *status)
 692 {
 693         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 694                 return -EINVAL;
 695
 696         /* Set the pf to main pf */
 697         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 698                 hdev->flag |= HCLGE_FLAG_MAIN;
 699         else
 700                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 701
 702         return 0;
 703 }
 704
 705 static int hclge_query_function_status(struct hclge_dev *hdev)
 706 {
 707         struct hclge_func_status_cmd *req;
 708         struct hclge_desc desc;
 709         int timeout = 0;
 710         int ret;
 711
 712         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 713         req = (struct hclge_func_status_cmd *)desc.data;
 714
 715         do {
 716                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 717                 if (ret) {
 718                         dev_err(&hdev->pdev->dev,
 719                                 "query function status failed %d.\n",
 720                                 ret);
 721
 722                         return ret;
 723                 }
 724
 725                 /* Check pf reset is done */
 726                 if (req->pf_state)
 727                         break;
 728                 usleep_range(1000, 2000);
 729         } while (timeout++ < 5);
 730
 731         ret = hclge_parse_func_status(hdev, req);
 732
 733         return ret;
 734 }
 735
 736 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 737 {
 738         struct hclge_pf_res_cmd *req;
 739         struct hclge_desc desc;
 740         int ret;
 741
 742         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 743         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 744         if (ret) {
 745                 dev_err(&hdev->pdev->dev,
 746                         "query pf resource failed %d.\n", ret);
 747                 return ret;
 748         }
 749
 750         req = (struct hclge_pf_res_cmd *)desc.data;
 751         hdev->num_tqps = __le16_to_cpu(req->tqp_num);
 752         hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 753
 754         if (req->tx_buf_size)
 755                 hdev->tx_buf_size =
 756                         __le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
 757         else
 758                 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
 759
 760         hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
 761
 762         if (req->dv_buf_size)
 763                 hdev->dv_buf_size =
 764                         __le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
 765         else
 766                 hdev->dv_buf_size = HCLGE_DEFAULT_DV;
 767
 768         hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
 769
 770         if (hnae3_dev_roce_supported(hdev)) {
 771                 hdev->roce_base_msix_offset =
 772                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
 773                                 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
 774                 hdev->num_roce_msi =
 775                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 776                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 777
 778                 /* PF should have NIC vectors and Roce vectors,
 779                  * NIC vectors are queued before Roce vectors.
 780                  */
 781                 hdev->num_msi = hdev->num_roce_msi  +
 782                                 hdev->roce_base_msix_offset;
 783         } else {
 784                 hdev->num_msi =
 785                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 786                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 787         }
 788
 789         return 0;
 790 }
 791
 792 static int hclge_parse_speed(int speed_cmd, int *speed)
 793 {
 794         switch (speed_cmd) {
 795         case 6:
 796                 *speed = HCLGE_MAC_SPEED_10M;
 797                 break;
 798         case 7:
 799                 *speed = HCLGE_MAC_SPEED_100M;
 800                 break;
 801         case 0:
 802                 *speed = HCLGE_MAC_SPEED_1G;
 803                 break;
 804         case 1:
 805                 *speed = HCLGE_MAC_SPEED_10G;
 806                 break;
 807         case 2:
 808                 *speed = HCLGE_MAC_SPEED_25G;
 809                 break;
 810         case 3:
 811                 *speed = HCLGE_MAC_SPEED_40G;
 812                 break;
 813         case 4:
 814                 *speed = HCLGE_MAC_SPEED_50G;
 815                 break;
 816         case 5:
 817                 *speed = HCLGE_MAC_SPEED_100G;
 818                 break;
 819         default:
 820                 return -EINVAL;
 821         }
 822
 823         return 0;
 824 }
 825
 826 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
 827                                         u8 speed_ability)
 828 {
 829         unsigned long *supported = hdev->hw.mac.supported;
 830
 831         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
 832                 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 833                         supported);
 834
 835         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
 836                 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 837                         supported);
 838
 839         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
 840                 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 841                         supported);
 842
 843         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
 844                 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
 845                         supported);
 846
 847         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
 848                 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 849                         supported);
 850
 851         set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 852         set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
 853 }
 854
 855 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
 856 {
 857         u8 media_type = hdev->hw.mac.media_type;
 858
 859         if (media_type != HNAE3_MEDIA_TYPE_FIBER)
 860                 return;
 861
 862         hclge_parse_fiber_link_mode(hdev, speed_ability);
 863 }
 864
 865 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
 866 {
 867         struct hclge_cfg_param_cmd *req;
 868         u64 mac_addr_tmp_high;
 869         u64 mac_addr_tmp;
 870         int i;
 871
 872         req = (struct hclge_cfg_param_cmd *)desc[0].data;
 873
 874         /* get the configuration */
 875         cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 876                                               HCLGE_CFG_VMDQ_M,
 877                                               HCLGE_CFG_VMDQ_S);
 878         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 879                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
 880         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 881                                             HCLGE_CFG_TQP_DESC_N_M,
 882                                             HCLGE_CFG_TQP_DESC_N_S);
 883
 884         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
 885                                         HCLGE_CFG_PHY_ADDR_M,
 886                                         HCLGE_CFG_PHY_ADDR_S);
 887         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
 888                                           HCLGE_CFG_MEDIA_TP_M,
 889                                           HCLGE_CFG_MEDIA_TP_S);
 890         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
 891                                           HCLGE_CFG_RX_BUF_LEN_M,
 892                                           HCLGE_CFG_RX_BUF_LEN_S);
 893         /* get mac_address */
 894         mac_addr_tmp = __le32_to_cpu(req->param[2]);
 895         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
 896                                             HCLGE_CFG_MAC_ADDR_H_M,
 897                                             HCLGE_CFG_MAC_ADDR_H_S);
 898
 899         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
 900
 901         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
 902                                              HCLGE_CFG_DEFAULT_SPEED_M,
 903                                              HCLGE_CFG_DEFAULT_SPEED_S);
 904         cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
 905                                             HCLGE_CFG_RSS_SIZE_M,
 906                                             HCLGE_CFG_RSS_SIZE_S);
 907
 908         for (i = 0; i < ETH_ALEN; i++)
 909                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
 910
 911         req = (struct hclge_cfg_param_cmd *)desc[1].data;
 912         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
 913
 914         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
 915                                              HCLGE_CFG_SPEED_ABILITY_M,
 916                                              HCLGE_CFG_SPEED_ABILITY_S);
 917         cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
 918                                          HCLGE_CFG_UMV_TBL_SPACE_M,
 919                                          HCLGE_CFG_UMV_TBL_SPACE_S);
 920         if (!cfg->umv_space)
 921                 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
 922 }
 923
 924 /* hclge_get_cfg: query the static parameter from flash
 925  * @hdev: pointer to struct hclge_dev
 926  * @hcfg: the config structure to be getted
 927  */
 928 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
 929 {
 930         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
 931         struct hclge_cfg_param_cmd *req;
 932         int i, ret;
 933
 934         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
 935                 u32 offset = 0;
 936
 937                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
 938                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
 939                                            true);
 940                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
 941                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
 942                 /* Len should be united by 4 bytes when send to hardware */
 943                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
 944                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
 945                 req->offset = cpu_to_le32(offset);
 946         }
 947
 948         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
 949         if (ret) {
 950                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
 951                 return ret;
 952         }
 953
 954         hclge_parse_cfg(hcfg, desc);
 955
 956         return 0;
 957 }
 958
 959 static int hclge_get_cap(struct hclge_dev *hdev)
 960 {
 961         int ret;
 962
 963         ret = hclge_query_function_status(hdev);
 964         if (ret) {
 965                 dev_err(&hdev->pdev->dev,
 966                         "query function status error %d.\n", ret);
 967                 return ret;
 968         }
 969
 970         /* get pf resource */
 971         ret = hclge_query_pf_resource(hdev);
 972         if (ret)
 973                 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
 974
 975         return ret;
 976 }
 977
 978 static int hclge_configure(struct hclge_dev *hdev)
 979 {
 980         struct hclge_cfg cfg;
 981         int ret, i;
 982
 983         ret = hclge_get_cfg(hdev, &cfg);
 984         if (ret) {
 985                 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
 986                 return ret;
 987         }
 988
 989         hdev->num_vmdq_vport = cfg.vmdq_vport_num;
 990         hdev->base_tqp_pid = 0;
 991         hdev->rss_size_max = cfg.rss_size_max;
 992         hdev->rx_buf_len = cfg.rx_buf_len;
 993         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
 994         hdev->hw.mac.media_type = cfg.media_type;
 995         hdev->hw.mac.phy_addr = cfg.phy_addr;
 996         hdev->num_desc = cfg.tqp_desc_num;
 997         hdev->tm_info.num_pg = 1;
 998         hdev->tc_max = cfg.tc_num;
 999         hdev->tm_info.hw_pfc_map = 0;
1000         hdev->wanted_umv_size = cfg.umv_space;
1001
1002         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1003         if (ret) {
1004                 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1005                 return ret;
1006         }
1007
1008         hclge_parse_link_mode(hdev, cfg.speed_ability);
1009
1010         if ((hdev->tc_max > HNAE3_MAX_TC) ||
1011             (hdev->tc_max < 1)) {
1012                 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1013                          hdev->tc_max);
1014                 hdev->tc_max = 1;
1015         }
1016
1017         /* Dev does not support DCB */
1018         if (!hnae3_dev_dcb_supported(hdev)) {
1019                 hdev->tc_max = 1;
1020                 hdev->pfc_max = 0;
1021         } else {
1022                 hdev->pfc_max = hdev->tc_max;
1023         }
1024
1025         hdev->tm_info.num_tc = 1;
1026
1027         /* Currently not support uncontiuous tc */
1028         for (i = 0; i < hdev->tm_info.num_tc; i++)
1029                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1030
1031         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1032
1033         return ret;
1034 }
1035
1036 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1037                             int tso_mss_max)
1038 {
1039         struct hclge_cfg_tso_status_cmd *req;
1040         struct hclge_desc desc;
1041         u16 tso_mss;
1042
1043         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1044
1045         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1046
1047         tso_mss = 0;
1048         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1049                         HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1050         req->tso_mss_min = cpu_to_le16(tso_mss);
1051
1052         tso_mss = 0;
1053         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1054                         HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1055         req->tso_mss_max = cpu_to_le16(tso_mss);
1056
1057         return hclge_cmd_send(&hdev->hw, &desc, 1);
1058 }
1059
1060 static int hclge_config_gro(struct hclge_dev *hdev, bool en)
1061 {
1062         struct hclge_cfg_gro_status_cmd *req;
1063         struct hclge_desc desc;
1064         int ret;
1065
1066         if (!hnae3_dev_gro_supported(hdev))
1067                 return 0;
1068
1069         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
1070         req = (struct hclge_cfg_gro_status_cmd *)desc.data;
1071
1072         req->gro_en = cpu_to_le16(en ? 1 : 0);
1073
1074         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1075         if (ret)
1076                 dev_err(&hdev->pdev->dev,
1077                         "GRO hardware config cmd failed, ret = %d\n", ret);
1078
1079         return ret;
1080 }
1081
1082 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1083 {
1084         struct hclge_tqp *tqp;
1085         int i;
1086
1087         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1088                                   sizeof(struct hclge_tqp), GFP_KERNEL);
1089         if (!hdev->htqp)
1090                 return -ENOMEM;
1091
1092         tqp = hdev->htqp;
1093
1094         for (i = 0; i < hdev->num_tqps; i++) {
1095                 tqp->dev = &hdev->pdev->dev;
1096                 tqp->index = i;
1097
1098                 tqp->q.ae_algo = &ae_algo;
1099                 tqp->q.buf_size = hdev->rx_buf_len;
1100                 tqp->q.desc_num = hdev->num_desc;
1101                 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1102                         i * HCLGE_TQP_REG_SIZE;
1103
1104                 tqp++;
1105         }
1106
1107         return 0;
1108 }
1109
1110 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1111                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
1112 {
1113         struct hclge_tqp_map_cmd *req;
1114         struct hclge_desc desc;
1115         int ret;
1116
1117         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1118
1119         req = (struct hclge_tqp_map_cmd *)desc.data;
1120         req->tqp_id = cpu_to_le16(tqp_pid);
1121         req->tqp_vf = func_id;
1122         req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1123                         1 << HCLGE_TQP_MAP_EN_B;
1124         req->tqp_vid = cpu_to_le16(tqp_vid);
1125
1126         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1127         if (ret)
1128                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1129
1130         return ret;
1131 }
1132
1133 static int  hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps)
1134 {
1135         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1136         struct hclge_dev *hdev = vport->back;
1137         int i, alloced;
1138
1139         for (i = 0, alloced = 0; i < hdev->num_tqps &&
1140              alloced < num_tqps; i++) {
1141                 if (!hdev->htqp[i].alloced) {
1142                         hdev->htqp[i].q.handle = &vport->nic;
1143                         hdev->htqp[i].q.tqp_index = alloced;
1144                         hdev->htqp[i].q.desc_num = kinfo->num_desc;
1145                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
1146                         hdev->htqp[i].alloced = true;
1147                         alloced++;
1148                 }
1149         }
1150         vport->alloc_tqps = alloced;
1151         kinfo->rss_size = min_t(u16, hdev->rss_size_max,
1152                                 vport->alloc_tqps / hdev->tm_info.num_tc);
1153
1154         return 0;
1155 }
1156
1157 static int hclge_knic_setup(struct hclge_vport *vport,
1158                             u16 num_tqps, u16 num_desc)
1159 {
1160         struct hnae3_handle *nic = &vport->nic;
1161         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1162         struct hclge_dev *hdev = vport->back;
1163         int ret;
1164
1165         kinfo->num_desc = num_desc;
1166         kinfo->rx_buf_len = hdev->rx_buf_len;
1167
1168         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
1169                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1170         if (!kinfo->tqp)
1171                 return -ENOMEM;
1172
1173         ret = hclge_assign_tqp(vport, num_tqps);
1174         if (ret)
1175                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1176
1177         return ret;
1178 }
1179
1180 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1181                                   struct hclge_vport *vport)
1182 {
1183         struct hnae3_handle *nic = &vport->nic;
1184         struct hnae3_knic_private_info *kinfo;
1185         u16 i;
1186
1187         kinfo = &nic->kinfo;
1188         for (i = 0; i < vport->alloc_tqps; i++) {
1189                 struct hclge_tqp *q =
1190                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
1191                 bool is_pf;
1192                 int ret;
1193
1194                 is_pf = !(vport->vport_id);
1195                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1196                                              i, is_pf);
1197                 if (ret)
1198                         return ret;
1199         }
1200
1201         return 0;
1202 }
1203
1204 static int hclge_map_tqp(struct hclge_dev *hdev)
1205 {
1206         struct hclge_vport *vport = hdev->vport;
1207         u16 i, num_vport;
1208
1209         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1210         for (i = 0; i < num_vport; i++) {
1211                 int ret;
1212
1213                 ret = hclge_map_tqp_to_vport(hdev, vport);
1214                 if (ret)
1215                         return ret;
1216
1217                 vport++;
1218         }
1219
1220         return 0;
1221 }
1222
1223 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1224 {
1225         /* this would be initialized later */
1226 }
1227
1228 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1229 {
1230         struct hnae3_handle *nic = &vport->nic;
1231         struct hclge_dev *hdev = vport->back;
1232         int ret;
1233
1234         nic->pdev = hdev->pdev;
1235         nic->ae_algo = &ae_algo;
1236         nic->numa_node_mask = hdev->numa_node_mask;
1237
1238         if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1239                 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
1240                 if (ret) {
1241                         dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1242                                 ret);
1243                         return ret;
1244                 }
1245         } else {
1246                 hclge_unic_setup(vport, num_tqps);
1247         }
1248
1249         return 0;
1250 }
1251
1252 static int hclge_alloc_vport(struct hclge_dev *hdev)
1253 {
1254         struct pci_dev *pdev = hdev->pdev;
1255         struct hclge_vport *vport;
1256         u32 tqp_main_vport;
1257         u32 tqp_per_vport;
1258         int num_vport, i;
1259         int ret;
1260
1261         /* We need to alloc a vport for main NIC of PF */
1262         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1263
1264         if (hdev->num_tqps < num_vport) {
1265                 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1266                         hdev->num_tqps, num_vport);
1267                 return -EINVAL;
1268         }
1269
1270         /* Alloc the same number of TQPs for every vport */
1271         tqp_per_vport = hdev->num_tqps / num_vport;
1272         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1273
1274         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1275                              GFP_KERNEL);
1276         if (!vport)
1277                 return -ENOMEM;
1278
1279         hdev->vport = vport;
1280         hdev->num_alloc_vport = num_vport;
1281
1282         if (IS_ENABLED(CONFIG_PCI_IOV))
1283                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1284
1285         for (i = 0; i < num_vport; i++) {
1286                 vport->back = hdev;
1287                 vport->vport_id = i;
1288                 vport->mps = HCLGE_MAC_DEFAULT_FRAME;
1289
1290                 if (i == 0)
1291                         ret = hclge_vport_setup(vport, tqp_main_vport);
1292                 else
1293                         ret = hclge_vport_setup(vport, tqp_per_vport);
1294                 if (ret) {
1295                         dev_err(&pdev->dev,
1296                                 "vport setup failed for vport %d, %d\n",
1297                                 i, ret);
1298                         return ret;
1299                 }
1300
1301                 vport++;
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1308                                     struct hclge_pkt_buf_alloc *buf_alloc)
1309 {
1310 /* TX buffer size is unit by 128 byte */
1311 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1312 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1313         struct hclge_tx_buff_alloc_cmd *req;
1314         struct hclge_desc desc;
1315         int ret;
1316         u8 i;
1317
1318         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1319
1320         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1321         for (i = 0; i < HCLGE_TC_NUM; i++) {
1322                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1323
1324                 req->tx_pkt_buff[i] =
1325                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1326                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1327         }
1328
1329         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1330         if (ret)
1331                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1332                         ret);
1333
1334         return ret;
1335 }
1336
1337 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1338                                  struct hclge_pkt_buf_alloc *buf_alloc)
1339 {
1340         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1341
1342         if (ret)
1343                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1344
1345         return ret;
1346 }
1347
1348 static int hclge_get_tc_num(struct hclge_dev *hdev)
1349 {
1350         int i, cnt = 0;
1351
1352         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1353                 if (hdev->hw_tc_map & BIT(i))
1354                         cnt++;
1355         return cnt;
1356 }
1357
1358 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1359 {
1360         int i, cnt = 0;
1361
1362         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1363                 if (hdev->hw_tc_map & BIT(i) &&
1364                     hdev->tm_info.hw_pfc_map & BIT(i))
1365                         cnt++;
1366         return cnt;
1367 }
1368
1369 /* Get the number of pfc enabled TCs, which have private buffer */
1370 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1371                                   struct hclge_pkt_buf_alloc *buf_alloc)
1372 {
1373         struct hclge_priv_buf *priv;
1374         int i, cnt = 0;
1375
1376         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1377                 priv = &buf_alloc->priv_buf[i];
1378                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1379                     priv->enable)
1380                         cnt++;
1381         }
1382
1383         return cnt;
1384 }
1385
1386 /* Get the number of pfc disabled TCs, which have private buffer */
1387 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1388                                      struct hclge_pkt_buf_alloc *buf_alloc)
1389 {
1390         struct hclge_priv_buf *priv;
1391         int i, cnt = 0;
1392
1393         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1394                 priv = &buf_alloc->priv_buf[i];
1395                 if (hdev->hw_tc_map & BIT(i) &&
1396                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1397                     priv->enable)
1398                         cnt++;
1399         }
1400
1401         return cnt;
1402 }
1403
1404 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1405 {
1406         struct hclge_priv_buf *priv;
1407         u32 rx_priv = 0;
1408         int i;
1409
1410         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1411                 priv = &buf_alloc->priv_buf[i];
1412                 if (priv->enable)
1413                         rx_priv += priv->buf_size;
1414         }
1415         return rx_priv;
1416 }
1417
1418 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1419 {
1420         u32 i, total_tx_size = 0;
1421
1422         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1423                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1424
1425         return total_tx_size;
1426 }
1427
1428 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1429                                 struct hclge_pkt_buf_alloc *buf_alloc,
1430                                 u32 rx_all)
1431 {
1432         u32 shared_buf_min, shared_buf_tc, shared_std;
1433         int tc_num, pfc_enable_num;
1434         u32 shared_buf, aligned_mps;
1435         u32 rx_priv;
1436         int i;
1437
1438         tc_num = hclge_get_tc_num(hdev);
1439         pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1440         aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1441
1442         if (hnae3_dev_dcb_supported(hdev))
1443                 shared_buf_min = 2 * aligned_mps + hdev->dv_buf_size;
1444         else
1445                 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
1446                                         + hdev->dv_buf_size;
1447
1448         shared_buf_tc = pfc_enable_num * aligned_mps +
1449                         (tc_num - pfc_enable_num) * aligned_mps / 2 +
1450                         aligned_mps;
1451         shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
1452                              HCLGE_BUF_SIZE_UNIT);
1453
1454         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1455         if (rx_all < rx_priv + shared_std)
1456                 return false;
1457
1458         shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
1459         buf_alloc->s_buf.buf_size = shared_buf;
1460         if (hnae3_dev_dcb_supported(hdev)) {
1461                 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
1462                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1463                         - roundup(aligned_mps / 2, HCLGE_BUF_SIZE_UNIT);
1464         } else {
1465                 buf_alloc->s_buf.self.high = aligned_mps +
1466                                                 HCLGE_NON_DCB_ADDITIONAL_BUF;
1467                 buf_alloc->s_buf.self.low =
1468                         roundup(aligned_mps / 2, HCLGE_BUF_SIZE_UNIT);
1469         }
1470
1471         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1472                 if ((hdev->hw_tc_map & BIT(i)) &&
1473                     (hdev->tm_info.hw_pfc_map & BIT(i))) {
1474                         buf_alloc->s_buf.tc_thrd[i].low = aligned_mps;
1475                         buf_alloc->s_buf.tc_thrd[i].high = 2 * aligned_mps;
1476                 } else {
1477                         buf_alloc->s_buf.tc_thrd[i].low = 0;
1478                         buf_alloc->s_buf.tc_thrd[i].high = aligned_mps;
1479                 }
1480         }
1481
1482         return true;
1483 }
1484
1485 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1486                                 struct hclge_pkt_buf_alloc *buf_alloc)
1487 {
1488         u32 i, total_size;
1489
1490         total_size = hdev->pkt_buf_size;
1491
1492         /* alloc tx buffer for all enabled tc */
1493         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1494                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1495
1496                 if (total_size < hdev->tx_buf_size)
1497                         return -ENOMEM;
1498
1499                 if (hdev->hw_tc_map & BIT(i))
1500                         priv->tx_buf_size = hdev->tx_buf_size;
1501                 else
1502                         priv->tx_buf_size = 0;
1503
1504                 total_size -= priv->tx_buf_size;
1505         }
1506
1507         return 0;
1508 }
1509
1510 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1511  * @hdev: pointer to struct hclge_dev
1512  * @buf_alloc: pointer to buffer calculation data
1513  * @return: 0: calculate sucessful, negative: fail
1514  */
1515 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1516                                 struct hclge_pkt_buf_alloc *buf_alloc)
1517 {
1518         u32 rx_all = hdev->pkt_buf_size, aligned_mps;
1519         int no_pfc_priv_num, pfc_priv_num;
1520         struct hclge_priv_buf *priv;
1521         int i;
1522
1523         aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1524         rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1525
1526         /* When DCB is not supported, rx private
1527          * buffer is not allocated.
1528          */
1529         if (!hnae3_dev_dcb_supported(hdev)) {
1530                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1531                         return -ENOMEM;
1532
1533                 return 0;
1534         }
1535
1536         /* step 1, try to alloc private buffer for all enabled tc */
1537         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1538                 priv = &buf_alloc->priv_buf[i];
1539                 if (hdev->hw_tc_map & BIT(i)) {
1540                         priv->enable = 1;
1541                         if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1542                                 priv->wl.low = aligned_mps;
1543                                 priv->wl.high =
1544                                         roundup(priv->wl.low + aligned_mps,
1545                                                 HCLGE_BUF_SIZE_UNIT);
1546                                 priv->buf_size = priv->wl.high +
1547                                         hdev->dv_buf_size;
1548                         } else {
1549                                 priv->wl.low = 0;
1550                                 priv->wl.high = 2 * aligned_mps;
1551                                 priv->buf_size = priv->wl.high +
1552                                                 hdev->dv_buf_size;
1553                         }
1554                 } else {
1555                         priv->enable = 0;
1556                         priv->wl.low = 0;
1557                         priv->wl.high = 0;
1558                         priv->buf_size = 0;
1559                 }
1560         }
1561
1562         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1563                 return 0;
1564
1565         /* step 2, try to decrease the buffer size of
1566          * no pfc TC's private buffer
1567          */
1568         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1569                 priv = &buf_alloc->priv_buf[i];
1570
1571                 priv->enable = 0;
1572                 priv->wl.low = 0;
1573                 priv->wl.high = 0;
1574                 priv->buf_size = 0;
1575
1576                 if (!(hdev->hw_tc_map & BIT(i)))
1577                         continue;
1578
1579                 priv->enable = 1;
1580
1581                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1582                         priv->wl.low = 256;
1583                         priv->wl.high = priv->wl.low + aligned_mps;
1584                         priv->buf_size = priv->wl.high + hdev->dv_buf_size;
1585                 } else {
1586                         priv->wl.low = 0;
1587                         priv->wl.high = aligned_mps;
1588                         priv->buf_size = priv->wl.high + hdev->dv_buf_size;
1589                 }
1590         }
1591
1592         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1593                 return 0;
1594
1595         /* step 3, try to reduce the number of pfc disabled TCs,
1596          * which have private buffer
1597          */
1598         /* get the total no pfc enable TC number, which have private buffer */
1599         no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1600
1601         /* let the last to be cleared first */
1602         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1603                 priv = &buf_alloc->priv_buf[i];
1604
1605                 if (hdev->hw_tc_map & BIT(i) &&
1606                     !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1607                         /* Clear the no pfc TC private buffer */
1608                         priv->wl.low = 0;
1609                         priv->wl.high = 0;
1610                         priv->buf_size = 0;
1611                         priv->enable = 0;
1612                         no_pfc_priv_num--;
1613                 }
1614
1615                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1616                     no_pfc_priv_num == 0)
1617                         break;
1618         }
1619
1620         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1621                 return 0;
1622
1623         /* step 4, try to reduce the number of pfc enabled TCs
1624          * which have private buffer.
1625          */
1626         pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1627
1628         /* let the last to be cleared first */
1629         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1630                 priv = &buf_alloc->priv_buf[i];
1631
1632                 if (hdev->hw_tc_map & BIT(i) &&
1633                     hdev->tm_info.hw_pfc_map & BIT(i)) {
1634                         /* Reduce the number of pfc TC with private buffer */
1635                         priv->wl.low = 0;
1636                         priv->enable = 0;
1637                         priv->wl.high = 0;
1638                         priv->buf_size = 0;
1639                         pfc_priv_num--;
1640                 }
1641
1642                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1643                     pfc_priv_num == 0)
1644                         break;
1645         }
1646         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1647                 return 0;
1648
1649         return -ENOMEM;
1650 }
1651
1652 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1653                                    struct hclge_pkt_buf_alloc *buf_alloc)
1654 {
1655         struct hclge_rx_priv_buff_cmd *req;
1656         struct hclge_desc desc;
1657         int ret;
1658         int i;
1659
1660         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1661         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1662
1663         /* Alloc private buffer TCs */
1664         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1665                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1666
1667                 req->buf_num[i] =
1668                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1669                 req->buf_num[i] |=
1670                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1671         }
1672
1673         req->shared_buf =
1674                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1675                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
1676
1677         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1678         if (ret)
1679                 dev_err(&hdev->pdev->dev,
1680                         "rx private buffer alloc cmd failed %d\n", ret);
1681
1682         return ret;
1683 }
1684
1685 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1686                                    struct hclge_pkt_buf_alloc *buf_alloc)
1687 {
1688         struct hclge_rx_priv_wl_buf *req;
1689         struct hclge_priv_buf *priv;
1690         struct hclge_desc desc[2];
1691         int i, j;
1692         int ret;
1693
1694         for (i = 0; i < 2; i++) {
1695                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1696                                            false);
1697                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1698
1699                 /* The first descriptor set the NEXT bit to 1 */
1700                 if (i == 0)
1701                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1702                 else
1703                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1704
1705                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1706                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1707
1708                         priv = &buf_alloc->priv_buf[idx];
1709                         req->tc_wl[j].high =
1710                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1711                         req->tc_wl[j].high |=
1712                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1713                         req->tc_wl[j].low =
1714                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1715                         req->tc_wl[j].low |=
1716                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1717                 }
1718         }
1719
1720         /* Send 2 descriptor at one time */
1721         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1722         if (ret)
1723                 dev_err(&hdev->pdev->dev,
1724                         "rx private waterline config cmd failed %d\n",
1725                         ret);
1726         return ret;
1727 }
1728
1729 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1730                                     struct hclge_pkt_buf_alloc *buf_alloc)
1731 {
1732         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1733         struct hclge_rx_com_thrd *req;
1734         struct hclge_desc desc[2];
1735         struct hclge_tc_thrd *tc;
1736         int i, j;
1737         int ret;
1738
1739         for (i = 0; i < 2; i++) {
1740                 hclge_cmd_setup_basic_desc(&desc[i],
1741                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1742                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1743
1744                 /* The first descriptor set the NEXT bit to 1 */
1745                 if (i == 0)
1746                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1747                 else
1748                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1749
1750                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1751                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1752
1753                         req->com_thrd[j].high =
1754                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1755                         req->com_thrd[j].high |=
1756                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1757                         req->com_thrd[j].low =
1758                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1759                         req->com_thrd[j].low |=
1760                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1761                 }
1762         }
1763
1764         /* Send 2 descriptors at one time */
1765         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1766         if (ret)
1767                 dev_err(&hdev->pdev->dev,
1768                         "common threshold config cmd failed %d\n", ret);
1769         return ret;
1770 }
1771
1772 static int hclge_common_wl_config(struct hclge_dev *hdev,
1773                                   struct hclge_pkt_buf_alloc *buf_alloc)
1774 {
1775         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1776         struct hclge_rx_com_wl *req;
1777         struct hclge_desc desc;
1778         int ret;
1779
1780         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1781
1782         req = (struct hclge_rx_com_wl *)desc.data;
1783         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1784         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1785
1786         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1787         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1788
1789         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1790         if (ret)
1791                 dev_err(&hdev->pdev->dev,
1792                         "common waterline config cmd failed %d\n", ret);
1793
1794         return ret;
1795 }
1796
1797 int hclge_buffer_alloc(struct hclge_dev *hdev)
1798 {
1799         struct hclge_pkt_buf_alloc *pkt_buf;
1800         int ret;
1801
1802         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1803         if (!pkt_buf)
1804                 return -ENOMEM;
1805
1806         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1807         if (ret) {
1808                 dev_err(&hdev->pdev->dev,
1809                         "could not calc tx buffer size for all TCs %d\n", ret);
1810                 goto out;
1811         }
1812
1813         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1814         if (ret) {
1815                 dev_err(&hdev->pdev->dev,
1816                         "could not alloc tx buffers %d\n", ret);
1817                 goto out;
1818         }
1819
1820         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1821         if (ret) {
1822                 dev_err(&hdev->pdev->dev,
1823                         "could not calc rx priv buffer size for all TCs %d\n",
1824                         ret);
1825                 goto out;
1826         }
1827
1828         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1829         if (ret) {
1830                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1831                         ret);
1832                 goto out;
1833         }
1834
1835         if (hnae3_dev_dcb_supported(hdev)) {
1836                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1837                 if (ret) {
1838                         dev_err(&hdev->pdev->dev,
1839                                 "could not configure rx private waterline %d\n",
1840                                 ret);
1841                         goto out;
1842                 }
1843
1844                 ret = hclge_common_thrd_config(hdev, pkt_buf);
1845                 if (ret) {
1846                         dev_err(&hdev->pdev->dev,
1847                                 "could not configure common threshold %d\n",
1848                                 ret);
1849                         goto out;
1850                 }
1851         }
1852
1853         ret = hclge_common_wl_config(hdev, pkt_buf);
1854         if (ret)
1855                 dev_err(&hdev->pdev->dev,
1856                         "could not configure common waterline %d\n", ret);
1857
1858 out:
1859         kfree(pkt_buf);
1860         return ret;
1861 }
1862
1863 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1864 {
1865         struct hnae3_handle *roce = &vport->roce;
1866         struct hnae3_handle *nic = &vport->nic;
1867
1868         roce->rinfo.num_vectors = vport->back->num_roce_msi;
1869
1870         if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1871             vport->back->num_msi_left == 0)
1872                 return -EINVAL;
1873
1874         roce->rinfo.base_vector = vport->back->roce_base_vector;
1875
1876         roce->rinfo.netdev = nic->kinfo.netdev;
1877         roce->rinfo.roce_io_base = vport->back->hw.io_base;
1878
1879         roce->pdev = nic->pdev;
1880         roce->ae_algo = nic->ae_algo;
1881         roce->numa_node_mask = nic->numa_node_mask;
1882
1883         return 0;
1884 }
1885
1886 static int hclge_init_msi(struct hclge_dev *hdev)
1887 {
1888         struct pci_dev *pdev = hdev->pdev;
1889         int vectors;
1890         int i;
1891
1892         vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1893                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
1894         if (vectors < 0) {
1895                 dev_err(&pdev->dev,
1896                         "failed(%d) to allocate MSI/MSI-X vectors\n",
1897                         vectors);
1898                 return vectors;
1899         }
1900         if (vectors < hdev->num_msi)
1901                 dev_warn(&hdev->pdev->dev,
1902                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1903                          hdev->num_msi, vectors);
1904
1905         hdev->num_msi = vectors;
1906         hdev->num_msi_left = vectors;
1907         hdev->base_msi_vector = pdev->irq;
1908         hdev->roce_base_vector = hdev->base_msi_vector +
1909                                 hdev->roce_base_msix_offset;
1910
1911         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1912                                            sizeof(u16), GFP_KERNEL);
1913         if (!hdev->vector_status) {
1914                 pci_free_irq_vectors(pdev);
1915                 return -ENOMEM;
1916         }
1917
1918         for (i = 0; i < hdev->num_msi; i++)
1919                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1920
1921         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1922                                         sizeof(int), GFP_KERNEL);
1923         if (!hdev->vector_irq) {
1924                 pci_free_irq_vectors(pdev);
1925                 return -ENOMEM;
1926         }
1927
1928         return 0;
1929 }
1930
1931 static u8 hclge_check_speed_dup(u8 duplex, int speed)
1932 {
1933
1934         if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1935                 duplex = HCLGE_MAC_FULL;
1936
1937         return duplex;
1938 }
1939
1940 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1941                                       u8 duplex)
1942 {
1943         struct hclge_config_mac_speed_dup_cmd *req;
1944         struct hclge_desc desc;
1945         int ret;
1946
1947         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
1948
1949         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1950
1951         hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
1952
1953         switch (speed) {
1954         case HCLGE_MAC_SPEED_10M:
1955                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1956                                 HCLGE_CFG_SPEED_S, 6);
1957                 break;
1958         case HCLGE_MAC_SPEED_100M:
1959                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1960                                 HCLGE_CFG_SPEED_S, 7);
1961                 break;
1962         case HCLGE_MAC_SPEED_1G:
1963                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1964                                 HCLGE_CFG_SPEED_S, 0);
1965                 break;
1966         case HCLGE_MAC_SPEED_10G:
1967                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1968                                 HCLGE_CFG_SPEED_S, 1);
1969                 break;
1970         case HCLGE_MAC_SPEED_25G:
1971                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1972                                 HCLGE_CFG_SPEED_S, 2);
1973                 break;
1974         case HCLGE_MAC_SPEED_40G:
1975                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1976                                 HCLGE_CFG_SPEED_S, 3);
1977                 break;
1978         case HCLGE_MAC_SPEED_50G:
1979                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1980                                 HCLGE_CFG_SPEED_S, 4);
1981                 break;
1982         case HCLGE_MAC_SPEED_100G:
1983                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1984                                 HCLGE_CFG_SPEED_S, 5);
1985                 break;
1986         default:
1987                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
1988                 return -EINVAL;
1989         }
1990
1991         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1992                       1);
1993
1994         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1995         if (ret) {
1996                 dev_err(&hdev->pdev->dev,
1997                         "mac speed/duplex config cmd failed %d.\n", ret);
1998                 return ret;
1999         }
2000
2001         return 0;
2002 }
2003
2004 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2005 {
2006         int ret;
2007
2008         duplex = hclge_check_speed_dup(duplex, speed);
2009         if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
2010                 return 0;
2011
2012         ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
2013         if (ret)
2014                 return ret;
2015
2016         hdev->hw.mac.speed = speed;
2017         hdev->hw.mac.duplex = duplex;
2018
2019         return 0;
2020 }
2021
2022 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2023                                      u8 duplex)
2024 {
2025         struct hclge_vport *vport = hclge_get_vport(handle);
2026         struct hclge_dev *hdev = vport->back;
2027
2028         return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2029 }
2030
2031 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2032 {
2033         struct hclge_config_auto_neg_cmd *req;
2034         struct hclge_desc desc;
2035         u32 flag = 0;
2036         int ret;
2037
2038         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2039
2040         req = (struct hclge_config_auto_neg_cmd *)desc.data;
2041         hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2042         req->cfg_an_cmd_flag = cpu_to_le32(flag);
2043
2044         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2045         if (ret)
2046                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2047                         ret);
2048
2049         return ret;
2050 }
2051
2052 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2053 {
2054         struct hclge_vport *vport = hclge_get_vport(handle);
2055         struct hclge_dev *hdev = vport->back;
2056
2057         return hclge_set_autoneg_en(hdev, enable);
2058 }
2059
2060 static int hclge_get_autoneg(struct hnae3_handle *handle)
2061 {
2062         struct hclge_vport *vport = hclge_get_vport(handle);
2063         struct hclge_dev *hdev = vport->back;
2064         struct phy_device *phydev = hdev->hw.mac.phydev;
2065
2066         if (phydev)
2067                 return phydev->autoneg;
2068
2069         return hdev->hw.mac.autoneg;
2070 }
2071
2072 static int hclge_mac_init(struct hclge_dev *hdev)
2073 {
2074         struct hclge_mac *mac = &hdev->hw.mac;
2075         int ret;
2076
2077         hdev->support_sfp_query = true;
2078         hdev->hw.mac.duplex = HCLGE_MAC_FULL;
2079         ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
2080                                          hdev->hw.mac.duplex);
2081         if (ret) {
2082                 dev_err(&hdev->pdev->dev,
2083                         "Config mac speed dup fail ret=%d\n", ret);
2084                 return ret;
2085         }
2086
2087         mac->link = 0;
2088
2089         ret = hclge_set_mac_mtu(hdev, hdev->mps);
2090         if (ret) {
2091                 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret);
2092                 return ret;
2093         }
2094
2095         ret = hclge_buffer_alloc(hdev);
2096         if (ret)
2097                 dev_err(&hdev->pdev->dev,
2098                         "allocate buffer fail, ret=%d\n", ret);
2099
2100         return ret;
2101 }
2102
2103 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2104 {
2105         if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2106                 schedule_work(&hdev->mbx_service_task);
2107 }
2108
2109 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2110 {
2111         if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2112                 schedule_work(&hdev->rst_service_task);
2113 }
2114
2115 static void hclge_task_schedule(struct hclge_dev *hdev)
2116 {
2117         if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2118             !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2119             !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2120                 (void)schedule_work(&hdev->service_task);
2121 }
2122
2123 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2124 {
2125         struct hclge_link_status_cmd *req;
2126         struct hclge_desc desc;
2127         int link_status;
2128         int ret;
2129
2130         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2131         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2132         if (ret) {
2133                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2134                         ret);
2135                 return ret;
2136         }
2137
2138         req = (struct hclge_link_status_cmd *)desc.data;
2139         link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2140
2141         return !!link_status;
2142 }
2143
2144 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2145 {
2146         int mac_state;
2147         int link_stat;
2148
2149         if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2150                 return 0;
2151
2152         mac_state = hclge_get_mac_link_status(hdev);
2153
2154         if (hdev->hw.mac.phydev) {
2155                 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
2156                         link_stat = mac_state &
2157                                 hdev->hw.mac.phydev->link;
2158                 else
2159                         link_stat = 0;
2160
2161         } else {
2162                 link_stat = mac_state;
2163         }
2164
2165         return !!link_stat;
2166 }
2167
2168 static void hclge_update_link_status(struct hclge_dev *hdev)
2169 {
2170         struct hnae3_client *rclient = hdev->roce_client;
2171         struct hnae3_client *client = hdev->nic_client;
2172         struct hnae3_handle *rhandle;
2173         struct hnae3_handle *handle;
2174         int state;
2175         int i;
2176
2177         if (!client)
2178                 return;
2179         state = hclge_get_mac_phy_link(hdev);
2180         if (state != hdev->hw.mac.link) {
2181                 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2182                         handle = &hdev->vport[i].nic;
2183                         client->ops->link_status_change(handle, state);
2184                         rhandle = &hdev->vport[i].roce;
2185                         if (rclient && rclient->ops->link_status_change)
2186                                 rclient->ops->link_status_change(rhandle,
2187                                                                  state);
2188                 }
2189                 hdev->hw.mac.link = state;
2190         }
2191 }
2192
2193 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed)
2194 {
2195         struct hclge_sfp_speed_cmd *resp = NULL;
2196         struct hclge_desc desc;
2197         int ret;
2198
2199         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SFP_GET_SPEED, true);
2200         resp = (struct hclge_sfp_speed_cmd *)desc.data;
2201         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2202         if (ret == -EOPNOTSUPP) {
2203                 dev_warn(&hdev->pdev->dev,
2204                          "IMP do not support get SFP speed %d\n", ret);
2205                 return ret;
2206         } else if (ret) {
2207                 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret);
2208                 return ret;
2209         }
2210
2211         *speed = resp->sfp_speed;
2212
2213         return 0;
2214 }
2215
2216 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2217 {
2218         struct hclge_mac mac = hdev->hw.mac;
2219         int speed;
2220         int ret;
2221
2222         /* get the speed from SFP cmd when phy
2223          * doesn't exit.
2224          */
2225         if (mac.phydev)
2226                 return 0;
2227
2228         /* if IMP does not support get SFP/qSFP speed, return directly */
2229         if (!hdev->support_sfp_query)
2230                 return 0;
2231
2232         ret = hclge_get_sfp_speed(hdev, &speed);
2233         if (ret == -EOPNOTSUPP) {
2234                 hdev->support_sfp_query = false;
2235                 return ret;
2236         } else if (ret) {
2237                 return ret;
2238         }
2239
2240         if (speed == HCLGE_MAC_SPEED_UNKNOWN)
2241                 return 0; /* do nothing if no SFP */
2242
2243         /* must config full duplex for SFP */
2244         return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL);
2245 }
2246
2247 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2248 {
2249         struct hclge_vport *vport = hclge_get_vport(handle);
2250         struct hclge_dev *hdev = vport->back;
2251
2252         return hclge_update_speed_duplex(hdev);
2253 }
2254
2255 static int hclge_get_status(struct hnae3_handle *handle)
2256 {
2257         struct hclge_vport *vport = hclge_get_vport(handle);
2258         struct hclge_dev *hdev = vport->back;
2259
2260         hclge_update_link_status(hdev);
2261
2262         return hdev->hw.mac.link;
2263 }
2264
2265 static void hclge_service_timer(struct timer_list *t)
2266 {
2267         struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2268
2269         mod_timer(&hdev->service_timer, jiffies + HZ);
2270         hdev->hw_stats.stats_timer++;
2271         hclge_task_schedule(hdev);
2272 }
2273
2274 static void hclge_service_complete(struct hclge_dev *hdev)
2275 {
2276         WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2277
2278         /* Flush memory before next watchdog */
2279         smp_mb__before_atomic();
2280         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2281 }
2282
2283 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2284 {
2285         u32 rst_src_reg, cmdq_src_reg, msix_src_reg;
2286
2287         /* fetch the events from their corresponding regs */
2288         rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
2289         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2290         msix_src_reg = hclge_read_dev(&hdev->hw,
2291                                       HCLGE_VECTOR0_PF_OTHER_INT_STS_REG);
2292
2293         /* Assumption: If by any chance reset and mailbox events are reported
2294          * together then we will only process reset event in this go and will
2295          * defer the processing of the mailbox events. Since, we would have not
2296          * cleared RX CMDQ event this time we would receive again another
2297          * interrupt from H/W just for the mailbox.
2298          */
2299
2300         /* check for vector0 reset event sources */
2301         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2302                 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
2303                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2304                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2305                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2306                 return HCLGE_VECTOR0_EVENT_RST;
2307         }
2308
2309         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2310                 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
2311                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2312                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2313                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2314                 return HCLGE_VECTOR0_EVENT_RST;
2315         }
2316
2317         if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2318                 dev_info(&hdev->pdev->dev, "core reset interrupt\n");
2319                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2320                 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2321                 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2322                 return HCLGE_VECTOR0_EVENT_RST;
2323         }
2324
2325         /* check for vector0 msix event source */
2326         if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK)
2327                 return HCLGE_VECTOR0_EVENT_ERR;
2328
2329         /* check for vector0 mailbox(=CMDQ RX) event source */
2330         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2331                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2332                 *clearval = cmdq_src_reg;
2333                 return HCLGE_VECTOR0_EVENT_MBX;
2334         }
2335
2336         return HCLGE_VECTOR0_EVENT_OTHER;
2337 }
2338
2339 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2340                                     u32 regclr)
2341 {
2342         switch (event_type) {
2343         case HCLGE_VECTOR0_EVENT_RST:
2344                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2345                 break;
2346         case HCLGE_VECTOR0_EVENT_MBX:
2347                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2348                 break;
2349         default:
2350                 break;
2351         }
2352 }
2353
2354 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2355 {
2356         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2357                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2358                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2359                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2360         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2361 }
2362
2363 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2364 {
2365         writel(enable ? 1 : 0, vector->addr);
2366 }
2367
2368 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2369 {
2370         struct hclge_dev *hdev = data;
2371         u32 event_cause;
2372         u32 clearval;
2373
2374         hclge_enable_vector(&hdev->misc_vector, false);
2375         event_cause = hclge_check_event_cause(hdev, &clearval);
2376
2377         /* vector 0 interrupt is shared with reset and mailbox source events.*/
2378         switch (event_cause) {
2379         case HCLGE_VECTOR0_EVENT_ERR:
2380                 /* we do not know what type of reset is required now. This could
2381                  * only be decided after we fetch the type of errors which
2382                  * caused this event. Therefore, we will do below for now:
2383                  * 1. Assert HNAE3_UNKNOWN_RESET type of reset. This means we
2384                  *    have defered type of reset to be used.
2385                  * 2. Schedule the reset serivce task.
2386                  * 3. When service task receives  HNAE3_UNKNOWN_RESET type it
2387                  *    will fetch the correct type of reset.  This would be done
2388                  *    by first decoding the types of errors.
2389                  */
2390                 set_bit(HNAE3_UNKNOWN_RESET, &hdev->reset_request);
2391                 /* fall through */
2392         case HCLGE_VECTOR0_EVENT_RST:
2393                 hclge_reset_task_schedule(hdev);
2394                 break;
2395         case HCLGE_VECTOR0_EVENT_MBX:
2396                 /* If we are here then,
2397                  * 1. Either we are not handling any mbx task and we are not
2398                  *    scheduled as well
2399                  *                        OR
2400                  * 2. We could be handling a mbx task but nothing more is
2401                  *    scheduled.
2402                  * In both cases, we should schedule mbx task as there are more
2403                  * mbx messages reported by this interrupt.
2404                  */
2405                 hclge_mbx_task_schedule(hdev);
2406                 break;
2407         default:
2408                 dev_warn(&hdev->pdev->dev,
2409                          "received unknown or unhandled event of vector0\n");
2410                 break;
2411         }
2412
2413         /* clear the source of interrupt if it is not cause by reset */
2414         if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
2415                 hclge_clear_event_cause(hdev, event_cause, clearval);
2416                 hclge_enable_vector(&hdev->misc_vector, true);
2417         }
2418
2419         return IRQ_HANDLED;
2420 }
2421
2422 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2423 {
2424         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2425                 dev_warn(&hdev->pdev->dev,
2426                          "vector(vector_id %d) has been freed.\n", vector_id);
2427                 return;
2428         }
2429
2430         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2431         hdev->num_msi_left += 1;
2432         hdev->num_msi_used -= 1;
2433 }
2434
2435 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2436 {
2437         struct hclge_misc_vector *vector = &hdev->misc_vector;
2438
2439         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2440
2441         vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2442         hdev->vector_status[0] = 0;
2443
2444         hdev->num_msi_left -= 1;
2445         hdev->num_msi_used += 1;
2446 }
2447
2448 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2449 {
2450         int ret;
2451
2452         hclge_get_misc_vector(hdev);
2453
2454         /* this would be explicitly freed in the end */
2455         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2456                           0, "hclge_misc", hdev);
2457         if (ret) {
2458                 hclge_free_vector(hdev, 0);
2459                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2460                         hdev->misc_vector.vector_irq);
2461         }
2462
2463         return ret;
2464 }
2465
2466 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2467 {
2468         free_irq(hdev->misc_vector.vector_irq, hdev);
2469         hclge_free_vector(hdev, 0);
2470 }
2471
2472 int hclge_notify_client(struct hclge_dev *hdev,
2473                         enum hnae3_reset_notify_type type)
2474 {
2475         struct hnae3_client *client = hdev->nic_client;
2476         u16 i;
2477
2478         if (!client->ops->reset_notify)
2479                 return -EOPNOTSUPP;
2480
2481         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2482                 struct hnae3_handle *handle = &hdev->vport[i].nic;
2483                 int ret;
2484
2485                 ret = client->ops->reset_notify(handle, type);
2486                 if (ret) {
2487                         dev_err(&hdev->pdev->dev,
2488                                 "notify nic client failed %d(%d)\n", type, ret);
2489                         return ret;
2490                 }
2491         }
2492
2493         return 0;
2494 }
2495
2496 static int hclge_notify_roce_client(struct hclge_dev *hdev,
2497                                     enum hnae3_reset_notify_type type)
2498 {
2499         struct hnae3_client *client = hdev->roce_client;
2500         int ret = 0;
2501         u16 i;
2502
2503         if (!client)
2504                 return 0;
2505
2506         if (!client->ops->reset_notify)
2507                 return -EOPNOTSUPP;
2508
2509         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2510                 struct hnae3_handle *handle = &hdev->vport[i].roce;
2511
2512                 ret = client->ops->reset_notify(handle, type);
2513                 if (ret) {
2514                         dev_err(&hdev->pdev->dev,
2515                                 "notify roce client failed %d(%d)",
2516                                 type, ret);
2517                         return ret;
2518                 }
2519         }
2520
2521         return ret;
2522 }
2523
2524 static int hclge_reset_wait(struct hclge_dev *hdev)
2525 {
2526 #define HCLGE_RESET_WATI_MS     100
2527 #define HCLGE_RESET_WAIT_CNT    200
2528         u32 val, reg, reg_bit;
2529         u32 cnt = 0;
2530
2531         switch (hdev->reset_type) {
2532         case HNAE3_IMP_RESET:
2533                 reg = HCLGE_GLOBAL_RESET_REG;
2534                 reg_bit = HCLGE_IMP_RESET_BIT;
2535                 break;
2536         case HNAE3_GLOBAL_RESET:
2537                 reg = HCLGE_GLOBAL_RESET_REG;
2538                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2539                 break;
2540         case HNAE3_CORE_RESET:
2541                 reg = HCLGE_GLOBAL_RESET_REG;
2542                 reg_bit = HCLGE_CORE_RESET_BIT;
2543                 break;
2544         case HNAE3_FUNC_RESET:
2545                 reg = HCLGE_FUN_RST_ING;
2546                 reg_bit = HCLGE_FUN_RST_ING_B;
2547                 break;
2548         case HNAE3_FLR_RESET:
2549                 break;
2550         default:
2551                 dev_err(&hdev->pdev->dev,
2552                         "Wait for unsupported reset type: %d\n",
2553                         hdev->reset_type);
2554                 return -EINVAL;
2555         }
2556
2557         if (hdev->reset_type == HNAE3_FLR_RESET) {
2558                 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
2559                        cnt++ < HCLGE_RESET_WAIT_CNT)
2560                         msleep(HCLGE_RESET_WATI_MS);
2561
2562                 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
2563                         dev_err(&hdev->pdev->dev,
2564                                 "flr wait timeout: %d\n", cnt);
2565                         return -EBUSY;
2566                 }
2567
2568                 return 0;
2569         }
2570
2571         val = hclge_read_dev(&hdev->hw, reg);
2572         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2573                 msleep(HCLGE_RESET_WATI_MS);
2574                 val = hclge_read_dev(&hdev->hw, reg);
2575                 cnt++;
2576         }
2577
2578         if (cnt >= HCLGE_RESET_WAIT_CNT) {
2579                 dev_warn(&hdev->pdev->dev,
2580                          "Wait for reset timeout: %d\n", hdev->reset_type);
2581                 return -EBUSY;
2582         }
2583
2584         return 0;
2585 }
2586
2587 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
2588 {
2589         struct hclge_vf_rst_cmd *req;
2590         struct hclge_desc desc;
2591
2592         req = (struct hclge_vf_rst_cmd *)desc.data;
2593         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
2594         req->dest_vfid = func_id;
2595
2596         if (reset)
2597                 req->vf_rst = 0x1;
2598
2599         return hclge_cmd_send(&hdev->hw, &desc, 1);
2600 }
2601
2602 int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
2603 {
2604         int i;
2605
2606         for (i = hdev->num_vmdq_vport + 1; i < hdev->num_alloc_vport; i++) {
2607                 struct hclge_vport *vport = &hdev->vport[i];
2608                 int ret;
2609
2610                 /* Send cmd to set/clear VF's FUNC_RST_ING */
2611                 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
2612                 if (ret) {
2613                         dev_err(&hdev->pdev->dev,
2614                                 "set vf(%d) rst failed %d!\n",
2615                                 vport->vport_id, ret);
2616                         return ret;
2617                 }
2618
2619                 if (!reset)
2620                         continue;
2621
2622                 /* Inform VF to process the reset.
2623                  * hclge_inform_reset_assert_to_vf may fail if VF
2624                  * driver is not loaded.
2625                  */
2626                 ret = hclge_inform_reset_assert_to_vf(vport);
2627                 if (ret)
2628                         dev_warn(&hdev->pdev->dev,
2629                                  "inform reset to vf(%d) failed %d!\n",
2630                                  vport->vport_id, ret);
2631         }
2632
2633         return 0;
2634 }
2635
2636 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2637 {
2638         struct hclge_desc desc;
2639         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2640         int ret;
2641
2642         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2643         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2644         req->fun_reset_vfid = func_id;
2645
2646         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2647         if (ret)
2648                 dev_err(&hdev->pdev->dev,
2649                         "send function reset cmd fail, status =%d\n", ret);
2650
2651         return ret;
2652 }
2653
2654 static void hclge_do_reset(struct hclge_dev *hdev)
2655 {
2656         struct pci_dev *pdev = hdev->pdev;
2657         u32 val;
2658
2659         switch (hdev->reset_type) {
2660         case HNAE3_GLOBAL_RESET:
2661                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2662                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2663                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2664                 dev_info(&pdev->dev, "Global Reset requested\n");
2665                 break;
2666         case HNAE3_CORE_RESET:
2667                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2668                 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2669                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2670                 dev_info(&pdev->dev, "Core Reset requested\n");
2671                 break;
2672         case HNAE3_FUNC_RESET:
2673                 dev_info(&pdev->dev, "PF Reset requested\n");
2674                 /* schedule again to check later */
2675                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2676                 hclge_reset_task_schedule(hdev);
2677                 break;
2678         case HNAE3_FLR_RESET:
2679                 dev_info(&pdev->dev, "FLR requested\n");
2680                 /* schedule again to check later */
2681                 set_bit(HNAE3_FLR_RESET, &hdev->reset_pending);
2682                 hclge_reset_task_schedule(hdev);
2683                 break;
2684         default:
2685                 dev_warn(&pdev->dev,
2686                          "Unsupported reset type: %d\n", hdev->reset_type);
2687                 break;
2688         }
2689 }
2690
2691 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2692                                                    unsigned long *addr)
2693 {
2694         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2695
2696         /* first, resolve any unknown reset type to the known type(s) */
2697         if (test_bit(HNAE3_UNKNOWN_RESET, addr)) {
2698                 /* we will intentionally ignore any errors from this function
2699                  *  as we will end up in *some* reset request in any case
2700                  */
2701                 hclge_handle_hw_msix_error(hdev, addr);
2702                 clear_bit(HNAE3_UNKNOWN_RESET, addr);
2703                 /* We defered the clearing of the error event which caused
2704                  * interrupt since it was not posssible to do that in
2705                  * interrupt context (and this is the reason we introduced
2706                  * new UNKNOWN reset type). Now, the errors have been
2707                  * handled and cleared in hardware we can safely enable
2708                  * interrupts. This is an exception to the norm.
2709                  */
2710                 hclge_enable_vector(&hdev->misc_vector, true);
2711         }
2712
2713         /* return the highest priority reset level amongst all */
2714         if (test_bit(HNAE3_IMP_RESET, addr)) {
2715                 rst_level = HNAE3_IMP_RESET;
2716                 clear_bit(HNAE3_IMP_RESET, addr);
2717                 clear_bit(HNAE3_GLOBAL_RESET, addr);
2718                 clear_bit(HNAE3_CORE_RESET, addr);
2719                 clear_bit(HNAE3_FUNC_RESET, addr);
2720         } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
2721                 rst_level = HNAE3_GLOBAL_RESET;
2722                 clear_bit(HNAE3_GLOBAL_RESET, addr);
2723                 clear_bit(HNAE3_CORE_RESET, addr);
2724                 clear_bit(HNAE3_FUNC_RESET, addr);
2725         } else if (test_bit(HNAE3_CORE_RESET, addr)) {
2726                 rst_level = HNAE3_CORE_RESET;
2727                 clear_bit(HNAE3_CORE_RESET, addr);
2728                 clear_bit(HNAE3_FUNC_RESET, addr);
2729         } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
2730                 rst_level = HNAE3_FUNC_RESET;
2731                 clear_bit(HNAE3_FUNC_RESET, addr);
2732         } else if (test_bit(HNAE3_FLR_RESET, addr)) {
2733                 rst_level = HNAE3_FLR_RESET;
2734                 clear_bit(HNAE3_FLR_RESET, addr);
2735         }
2736
2737         return rst_level;
2738 }
2739
2740 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2741 {
2742         u32 clearval = 0;
2743
2744         switch (hdev->reset_type) {
2745         case HNAE3_IMP_RESET:
2746                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2747                 break;
2748         case HNAE3_GLOBAL_RESET:
2749                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2750                 break;
2751         case HNAE3_CORE_RESET:
2752                 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2753                 break;
2754         default:
2755                 break;
2756         }
2757
2758         if (!clearval)
2759                 return;
2760
2761         hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2762         hclge_enable_vector(&hdev->misc_vector, true);
2763 }
2764
2765 static int hclge_reset_prepare_down(struct hclge_dev *hdev)
2766 {
2767         int ret = 0;
2768
2769         switch (hdev->reset_type) {
2770         case HNAE3_FUNC_RESET:
2771                 /* fall through */
2772         case HNAE3_FLR_RESET:
2773                 ret = hclge_set_all_vf_rst(hdev, true);
2774                 break;
2775         default:
2776                 break;
2777         }
2778
2779         return ret;
2780 }
2781
2782 static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
2783 {
2784         u32 reg_val;
2785         int ret = 0;
2786
2787         switch (hdev->reset_type) {
2788         case HNAE3_FUNC_RESET:
2789                 /* There is no mechanism for PF to know if VF has stopped IO
2790                  * for now, just wait 100 ms for VF to stop IO
2791                  */
2792                 msleep(100);
2793                 ret = hclge_func_reset_cmd(hdev, 0);
2794                 if (ret) {
2795                         dev_err(&hdev->pdev->dev,
2796                                 "asserting function reset fail %d!\n", ret);
2797                         return ret;
2798                 }
2799
2800                 /* After performaning pf reset, it is not necessary to do the
2801                  * mailbox handling or send any command to firmware, because
2802                  * any mailbox handling or command to firmware is only valid
2803                  * after hclge_cmd_init is called.
2804                  */
2805                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2806                 break;
2807         case HNAE3_FLR_RESET:
2808                 /* There is no mechanism for PF to know if VF has stopped IO
2809                  * for now, just wait 100 ms for VF to stop IO
2810                  */
2811                 msleep(100);
2812                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2813                 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
2814                 break;
2815         case HNAE3_IMP_RESET:
2816                 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
2817                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
2818                                 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
2819                 break;
2820         default:
2821                 break;
2822         }
2823
2824         dev_info(&hdev->pdev->dev, "prepare wait ok\n");
2825
2826         return ret;
2827 }
2828
2829 static bool hclge_reset_err_handle(struct hclge_dev *hdev, bool is_timeout)
2830 {
2831 #define MAX_RESET_FAIL_CNT 5
2832 #define RESET_UPGRADE_DELAY_SEC 10
2833
2834         if (hdev->reset_pending) {
2835                 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
2836                          hdev->reset_pending);
2837                 return true;
2838         } else if ((hdev->reset_type != HNAE3_IMP_RESET) &&
2839                    (hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) &
2840                     BIT(HCLGE_IMP_RESET_BIT))) {
2841                 dev_info(&hdev->pdev->dev,
2842                          "reset failed because IMP Reset is pending\n");
2843                 hclge_clear_reset_cause(hdev);
2844                 return false;
2845         } else if (hdev->reset_fail_cnt < MAX_RESET_FAIL_CNT) {
2846                 hdev->reset_fail_cnt++;
2847                 if (is_timeout) {
2848                         set_bit(hdev->reset_type, &hdev->reset_pending);
2849                         dev_info(&hdev->pdev->dev,
2850                                  "re-schedule to wait for hw reset done\n");
2851                         return true;
2852                 }
2853
2854                 dev_info(&hdev->pdev->dev, "Upgrade reset level\n");
2855                 hclge_clear_reset_cause(hdev);
2856                 mod_timer(&hdev->reset_timer,
2857                           jiffies + RESET_UPGRADE_DELAY_SEC * HZ);
2858
2859                 return false;
2860         }
2861
2862         hclge_clear_reset_cause(hdev);
2863         dev_err(&hdev->pdev->dev, "Reset fail!\n");
2864         return false;
2865 }
2866
2867 static int hclge_reset_prepare_up(struct hclge_dev *hdev)
2868 {
2869         int ret = 0;
2870
2871         switch (hdev->reset_type) {
2872         case HNAE3_FUNC_RESET:
2873                 /* fall through */
2874         case HNAE3_FLR_RESET:
2875                 ret = hclge_set_all_vf_rst(hdev, false);
2876                 break;
2877         default:
2878                 break;
2879         }
2880
2881         return ret;
2882 }
2883
2884 static void hclge_reset(struct hclge_dev *hdev)
2885 {
2886         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2887         bool is_timeout = false;
2888         int ret;
2889
2890         /* Initialize ae_dev reset status as well, in case enet layer wants to
2891          * know if device is undergoing reset
2892          */
2893         ae_dev->reset_type = hdev->reset_type;
2894         hdev->reset_count++;
2895         /* perform reset of the stack & ae device for a client */
2896         ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2897         if (ret)
2898                 goto err_reset;
2899
2900         ret = hclge_reset_prepare_down(hdev);
2901         if (ret)
2902                 goto err_reset;
2903
2904         rtnl_lock();
2905         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2906         if (ret)
2907                 goto err_reset_lock;
2908
2909         rtnl_unlock();
2910
2911         ret = hclge_reset_prepare_wait(hdev);
2912         if (ret)
2913                 goto err_reset;
2914
2915         if (hclge_reset_wait(hdev)) {
2916                 is_timeout = true;
2917                 goto err_reset;
2918         }
2919
2920         ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2921         if (ret)
2922                 goto err_reset;
2923
2924         rtnl_lock();
2925         ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2926         if (ret)
2927                 goto err_reset_lock;
2928
2929         ret = hclge_reset_ae_dev(hdev->ae_dev);
2930         if (ret)
2931                 goto err_reset_lock;
2932
2933         ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2934         if (ret)
2935                 goto err_reset_lock;
2936
2937         ret = hclge_notify_client(hdev, HNAE3_RESTORE_CLIENT);
2938         if (ret)
2939                 goto err_reset_lock;
2940
2941         hclge_clear_reset_cause(hdev);
2942
2943         ret = hclge_reset_prepare_up(hdev);
2944         if (ret)
2945                 goto err_reset_lock;
2946
2947         ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2948         if (ret)
2949                 goto err_reset_lock;
2950
2951         rtnl_unlock();
2952
2953         ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2954         if (ret)
2955                 goto err_reset;
2956
2957         ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2958         if (ret)
2959                 goto err_reset;
2960
2961         hdev->last_reset_time = jiffies;
2962         hdev->reset_fail_cnt = 0;
2963         ae_dev->reset_type = HNAE3_NONE_RESET;
2964
2965         return;
2966
2967 err_reset_lock:
2968         rtnl_unlock();
2969 err_reset:
2970         if (hclge_reset_err_handle(hdev, is_timeout))
2971                 hclge_reset_task_schedule(hdev);
2972 }
2973
2974 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2975 {
2976         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2977         struct hclge_dev *hdev = ae_dev->priv;
2978
2979         /* We might end up getting called broadly because of 2 below cases:
2980          * 1. Recoverable error was conveyed through APEI and only way to bring
2981          *    normalcy is to reset.
2982          * 2. A new reset request from the stack due to timeout
2983          *
2984          * For the first case,error event might not have ae handle available.
2985          * check if this is a new reset request and we are not here just because
2986          * last reset attempt did not succeed and watchdog hit us again. We will
2987          * know this if last reset request did not occur very recently (watchdog
2988          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2989          * In case of new request we reset the "reset level" to PF reset.
2990          * And if it is a repeat reset request of the most recent one then we
2991          * want to make sure we throttle the reset request. Therefore, we will
2992          * not allow it again before 3*HZ times.
2993          */
2994         if (!handle)
2995                 handle = &hdev->vport[0].nic;
2996
2997         if (time_before(jiffies, (hdev->last_reset_time + 3 * HZ)))
2998                 return;
2999         else if (hdev->default_reset_request)
3000                 hdev->reset_level =
3001                         hclge_get_reset_level(hdev,
3002                                               &hdev->default_reset_request);
3003         else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ)))
3004                 hdev->reset_level = HNAE3_FUNC_RESET;
3005
3006         dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
3007                  hdev->reset_level);
3008
3009         /* request reset & schedule reset task */
3010         set_bit(hdev->reset_level, &hdev->reset_request);
3011         hclge_reset_task_schedule(hdev);
3012
3013         if (hdev->reset_level < HNAE3_GLOBAL_RESET)
3014                 hdev->reset_level++;
3015 }
3016
3017 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
3018                                         enum hnae3_reset_type rst_type)
3019 {
3020         struct hclge_dev *hdev = ae_dev->priv;
3021
3022         set_bit(rst_type, &hdev->default_reset_request);
3023 }
3024
3025 static void hclge_reset_timer(struct timer_list *t)
3026 {
3027         struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
3028
3029         dev_info(&hdev->pdev->dev,
3030                  "triggering global reset in reset timer\n");
3031         set_bit(HNAE3_GLOBAL_RESET, &hdev->default_reset_request);
3032         hclge_reset_event(hdev->pdev, NULL);
3033 }
3034
3035 static void hclge_reset_subtask(struct hclge_dev *hdev)
3036 {
3037         /* check if there is any ongoing reset in the hardware. This status can
3038          * be checked from reset_pending. If there is then, we need to wait for
3039          * hardware to complete reset.
3040          *    a. If we are able to figure out in reasonable time that hardware
3041          *       has fully resetted then, we can proceed with driver, client
3042          *       reset.
3043          *    b. else, we can come back later to check this status so re-sched
3044          *       now.
3045          */
3046         hdev->last_reset_time = jiffies;
3047         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
3048         if (hdev->reset_type != HNAE3_NONE_RESET)
3049                 hclge_reset(hdev);
3050
3051         /* check if we got any *new* reset requests to be honored */
3052         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
3053         if (hdev->reset_type != HNAE3_NONE_RESET)
3054                 hclge_do_reset(hdev);
3055
3056         hdev->reset_type = HNAE3_NONE_RESET;
3057 }
3058
3059 static void hclge_reset_service_task(struct work_struct *work)
3060 {
3061         struct hclge_dev *hdev =
3062                 container_of(work, struct hclge_dev, rst_service_task);
3063
3064         if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3065                 return;
3066
3067         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
3068
3069         hclge_reset_subtask(hdev);
3070
3071         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
3072 }
3073
3074 static void hclge_mailbox_service_task(struct work_struct *work)
3075 {
3076         struct hclge_dev *hdev =
3077                 container_of(work, struct hclge_dev, mbx_service_task);
3078
3079         if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
3080                 return;
3081
3082         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
3083
3084         hclge_mbx_handler(hdev);
3085
3086         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
3087 }
3088
3089 static void hclge_update_vport_alive(struct hclge_dev *hdev)
3090 {
3091         int i;
3092
3093         /* start from vport 1 for PF is always alive */
3094         for (i = 1; i < hdev->num_alloc_vport; i++) {
3095                 struct hclge_vport *vport = &hdev->vport[i];
3096
3097                 if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ))
3098                         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
3099
3100                 /* If vf is not alive, set to default value */
3101                 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3102                         vport->mps = HCLGE_MAC_DEFAULT_FRAME;
3103         }
3104 }
3105
3106 static void hclge_service_task(struct work_struct *work)
3107 {
3108         struct hclge_dev *hdev =
3109                 container_of(work, struct hclge_dev, service_task);
3110
3111         if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
3112                 hclge_update_stats_for_all(hdev);
3113                 hdev->hw_stats.stats_timer = 0;
3114         }
3115
3116         hclge_update_speed_duplex(hdev);
3117         hclge_update_link_status(hdev);
3118         hclge_update_vport_alive(hdev);
3119         hclge_service_complete(hdev);
3120 }
3121
3122 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
3123 {
3124         /* VF handle has no client */
3125         if (!handle->client)
3126                 return container_of(handle, struct hclge_vport, nic);
3127         else if (handle->client->type == HNAE3_CLIENT_ROCE)
3128                 return container_of(handle, struct hclge_vport, roce);
3129         else
3130                 return container_of(handle, struct hclge_vport, nic);
3131 }
3132
3133 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
3134                             struct hnae3_vector_info *vector_info)
3135 {
3136         struct hclge_vport *vport = hclge_get_vport(handle);
3137         struct hnae3_vector_info *vector = vector_info;
3138         struct hclge_dev *hdev = vport->back;
3139         int alloc = 0;
3140         int i, j;
3141
3142         vector_num = min(hdev->num_msi_left, vector_num);
3143
3144         for (j = 0; j < vector_num; j++) {
3145                 for (i = 1; i < hdev->num_msi; i++) {
3146                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
3147                                 vector->vector = pci_irq_vector(hdev->pdev, i);
3148                                 vector->io_addr = hdev->hw.io_base +
3149                                         HCLGE_VECTOR_REG_BASE +
3150                                         (i - 1) * HCLGE_VECTOR_REG_OFFSET +
3151                                         vport->vport_id *
3152                                         HCLGE_VECTOR_VF_OFFSET;
3153                                 hdev->vector_status[i] = vport->vport_id;
3154                                 hdev->vector_irq[i] = vector->vector;
3155
3156                                 vector++;
3157                                 alloc++;
3158
3159                                 break;
3160                         }
3161                 }
3162         }
3163         hdev->num_msi_left -= alloc;
3164         hdev->num_msi_used += alloc;
3165
3166         return alloc;
3167 }
3168
3169 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
3170 {
3171         int i;
3172
3173         for (i = 0; i < hdev->num_msi; i++)
3174                 if (vector == hdev->vector_irq[i])
3175                         return i;
3176
3177         return -EINVAL;
3178 }
3179
3180 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
3181 {
3182         struct hclge_vport *vport = hclge_get_vport(handle);
3183         struct hclge_dev *hdev = vport->back;
3184         int vector_id;
3185
3186         vector_id = hclge_get_vector_index(hdev, vector);
3187         if (vector_id < 0) {
3188                 dev_err(&hdev->pdev->dev,
3189                         "Get vector index fail. vector_id =%d\n", vector_id);
3190                 return vector_id;
3191         }
3192
3193         hclge_free_vector(hdev, vector_id);
3194
3195         return 0;
3196 }
3197
3198 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3199 {
3200         return HCLGE_RSS_KEY_SIZE;
3201 }
3202
3203 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3204 {
3205         return HCLGE_RSS_IND_TBL_SIZE;
3206 }
3207
3208 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3209                                   const u8 hfunc, const u8 *key)
3210 {
3211         struct hclge_rss_config_cmd *req;
3212         struct hclge_desc desc;
3213         int key_offset;
3214         int key_size;
3215         int ret;
3216
3217         req = (struct hclge_rss_config_cmd *)desc.data;
3218
3219         for (key_offset = 0; key_offset < 3; key_offset++) {
3220                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3221                                            false);
3222
3223                 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3224                 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3225
3226                 if (key_offset == 2)
3227                         key_size =
3228                         HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3229                 else
3230                         key_size = HCLGE_RSS_HASH_KEY_NUM;
3231
3232                 memcpy(req->hash_key,
3233                        key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3234
3235                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3236                 if (ret) {
3237                         dev_err(&hdev->pdev->dev,
3238                                 "Configure RSS config fail, status = %d\n",
3239                                 ret);
3240                         return ret;
3241                 }
3242         }
3243         return 0;
3244 }
3245
3246 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
3247 {
3248         struct hclge_rss_indirection_table_cmd *req;
3249         struct hclge_desc desc;
3250         int i, j;
3251         int ret;
3252
3253         req = (struct hclge_rss_indirection_table_cmd *)desc.data;
3254
3255         for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3256                 hclge_cmd_setup_basic_desc
3257                         (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3258
3259                 req->start_table_index =
3260                         cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3261                 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
3262
3263                 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3264                         req->rss_result[j] =
3265                                 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3266
3267                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3268                 if (ret) {
3269                         dev_err(&hdev->pdev->dev,
3270                                 "Configure rss indir table fail,status = %d\n",
3271                                 ret);
3272                         return ret;
3273                 }
3274         }
3275         return 0;
3276 }
3277
3278 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3279                                  u16 *tc_size, u16 *tc_offset)
3280 {
3281         struct hclge_rss_tc_mode_cmd *req;
3282         struct hclge_desc desc;
3283         int ret;
3284         int i;
3285
3286         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3287         req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3288
3289         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3290                 u16 mode = 0;
3291
3292                 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3293                 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3294                                 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3295                 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3296                                 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3297
3298                 req->rss_tc_mode[i] = cpu_to_le16(mode);
3299         }
3300
3301         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3302         if (ret)
3303                 dev_err(&hdev->pdev->dev,
3304                         "Configure rss tc mode fail, status = %d\n", ret);
3305
3306         return ret;
3307 }
3308
3309 static void hclge_get_rss_type(struct hclge_vport *vport)
3310 {
3311         if (vport->rss_tuple_sets.ipv4_tcp_en ||
3312             vport->rss_tuple_sets.ipv4_udp_en ||
3313             vport->rss_tuple_sets.ipv4_sctp_en ||
3314             vport->rss_tuple_sets.ipv6_tcp_en ||
3315             vport->rss_tuple_sets.ipv6_udp_en ||
3316             vport->rss_tuple_sets.ipv6_sctp_en)
3317                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
3318         else if (vport->rss_tuple_sets.ipv4_fragment_en ||
3319                  vport->rss_tuple_sets.ipv6_fragment_en)
3320                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
3321         else
3322                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
3323 }
3324
3325 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3326 {
3327         struct hclge_rss_input_tuple_cmd *req;
3328         struct hclge_desc desc;
3329         int ret;
3330
3331         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3332
3333         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3334
3335         /* Get the tuple cfg from pf */
3336         req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3337         req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3338         req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3339         req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3340         req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3341         req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3342         req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3343         req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
3344         hclge_get_rss_type(&hdev->vport[0]);
3345         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3346         if (ret)
3347                 dev_err(&hdev->pdev->dev,
3348                         "Configure rss input fail, status = %d\n", ret);
3349         return ret;
3350 }
3351
3352 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3353                          u8 *key, u8 *hfunc)
3354 {
3355         struct hclge_vport *vport = hclge_get_vport(handle);
3356         int i;
3357
3358         /* Get hash algorithm */
3359         if (hfunc) {
3360                 switch (vport->rss_algo) {
3361                 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
3362                         *hfunc = ETH_RSS_HASH_TOP;
3363                         break;
3364                 case HCLGE_RSS_HASH_ALGO_SIMPLE:
3365                         *hfunc = ETH_RSS_HASH_XOR;
3366                         break;
3367                 default:
3368                         *hfunc = ETH_RSS_HASH_UNKNOWN;
3369                         break;
3370                 }
3371         }
3372
3373         /* Get the RSS Key required by the user */
3374         if (key)
3375                 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3376
3377         /* Get indirect table */
3378         if (indir)
3379                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3380                         indir[i] =  vport->rss_indirection_tbl[i];
3381
3382         return 0;
3383 }
3384
3385 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3386                          const  u8 *key, const  u8 hfunc)
3387 {
3388         struct hclge_vport *vport = hclge_get_vport(handle);
3389         struct hclge_dev *hdev = vport->back;
3390         u8 hash_algo;
3391         int ret, i;
3392
3393         /* Set the RSS Hash Key if specififed by the user */
3394         if (key) {
3395                 switch (hfunc) {
3396                 case ETH_RSS_HASH_TOP:
3397                         hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3398                         break;
3399                 case ETH_RSS_HASH_XOR:
3400                         hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
3401                         break;
3402                 case ETH_RSS_HASH_NO_CHANGE:
3403                         hash_algo = vport->rss_algo;
3404                         break;
3405                 default:
3406                         return -EINVAL;
3407                 }
3408
3409                 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3410                 if (ret)
3411                         return ret;
3412
3413                 /* Update the shadow RSS key with user specified qids */
3414                 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3415                 vport->rss_algo = hash_algo;
3416         }
3417
3418         /* Update the shadow RSS table with user specified qids */
3419         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3420                 vport->rss_indirection_tbl[i] = indir[i];
3421
3422         /* Update the hardware */
3423         return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
3424 }
3425
3426 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3427 {
3428         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3429
3430         if (nfc->data & RXH_L4_B_2_3)
3431                 hash_sets |= HCLGE_D_PORT_BIT;
3432         else
3433                 hash_sets &= ~HCLGE_D_PORT_BIT;
3434
3435         if (nfc->data & RXH_IP_SRC)
3436                 hash_sets |= HCLGE_S_IP_BIT;
3437         else
3438                 hash_sets &= ~HCLGE_S_IP_BIT;
3439
3440         if (nfc->data & RXH_IP_DST)
3441                 hash_sets |= HCLGE_D_IP_BIT;
3442         else
3443                 hash_sets &= ~HCLGE_D_IP_BIT;
3444
3445         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3446                 hash_sets |= HCLGE_V_TAG_BIT;
3447
3448         return hash_sets;
3449 }
3450
3451 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3452                                struct ethtool_rxnfc *nfc)
3453 {
3454         struct hclge_vport *vport = hclge_get_vport(handle);
3455         struct hclge_dev *hdev = vport->back;
3456         struct hclge_rss_input_tuple_cmd *req;
3457         struct hclge_desc desc;
3458         u8 tuple_sets;
3459         int ret;
3460
3461         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3462                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
3463                 return -EINVAL;
3464
3465         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3466         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3467
3468         req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3469         req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3470         req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3471         req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3472         req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3473         req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3474         req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3475         req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
3476
3477         tuple_sets = hclge_get_rss_hash_bits(nfc);
3478         switch (nfc->flow_type) {
3479         case TCP_V4_FLOW:
3480                 req->ipv4_tcp_en = tuple_sets;
3481                 break;
3482         case TCP_V6_FLOW:
3483                 req->ipv6_tcp_en = tuple_sets;
3484                 break;
3485         case UDP_V4_FLOW:
3486                 req->ipv4_udp_en = tuple_sets;
3487                 break;
3488         case UDP_V6_FLOW:
3489                 req->ipv6_udp_en = tuple_sets;
3490                 break;
3491         case SCTP_V4_FLOW:
3492                 req->ipv4_sctp_en = tuple_sets;
3493                 break;
3494         case SCTP_V6_FLOW:
3495                 if ((nfc->data & RXH_L4_B_0_1) ||
3496                     (nfc->data & RXH_L4_B_2_3))
3497                         return -EINVAL;
3498
3499                 req->ipv6_sctp_en = tuple_sets;
3500                 break;
3501         case IPV4_FLOW:
3502                 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3503                 break;
3504         case IPV6_FLOW:
3505                 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3506                 break;
3507         default:
3508                 return -EINVAL;
3509         }
3510
3511         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3512         if (ret) {
3513                 dev_err(&hdev->pdev->dev,
3514                         "Set rss tuple fail, status = %d\n", ret);
3515                 return ret;
3516         }
3517
3518         vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3519         vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3520         vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3521         vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3522         vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3523         vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3524         vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3525         vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3526         hclge_get_rss_type(vport);
3527         return 0;
3528 }
3529
3530 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3531                                struct ethtool_rxnfc *nfc)
3532 {
3533         struct hclge_vport *vport = hclge_get_vport(handle);
3534         u8 tuple_sets;
3535
3536         nfc->data = 0;
3537
3538         switch (nfc->flow_type) {
3539         case TCP_V4_FLOW:
3540                 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3541                 break;
3542         case UDP_V4_FLOW:
3543                 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3544                 break;
3545         case TCP_V6_FLOW:
3546                 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3547                 break;
3548         case UDP_V6_FLOW:
3549                 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3550                 break;
3551         case SCTP_V4_FLOW:
3552                 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3553                 break;
3554         case SCTP_V6_FLOW:
3555                 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3556                 break;
3557         case IPV4_FLOW:
3558         case IPV6_FLOW:
3559                 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3560                 break;
3561         default:
3562                 return -EINVAL;
3563         }
3564
3565         if (!tuple_sets)
3566                 return 0;
3567
3568         if (tuple_sets & HCLGE_D_PORT_BIT)
3569                 nfc->data |= RXH_L4_B_2_3;
3570         if (tuple_sets & HCLGE_S_PORT_BIT)
3571                 nfc->data |= RXH_L4_B_0_1;
3572         if (tuple_sets & HCLGE_D_IP_BIT)
3573                 nfc->data |= RXH_IP_DST;
3574         if (tuple_sets & HCLGE_S_IP_BIT)
3575                 nfc->data |= RXH_IP_SRC;
3576
3577         return 0;
3578 }
3579
3580 static int hclge_get_tc_size(struct hnae3_handle *handle)
3581 {
3582         struct hclge_vport *vport = hclge_get_vport(handle);
3583         struct hclge_dev *hdev = vport->back;
3584
3585         return hdev->rss_size_max;
3586 }
3587
3588 int hclge_rss_init_hw(struct hclge_dev *hdev)
3589 {
3590         struct hclge_vport *vport = hdev->vport;
3591         u8 *rss_indir = vport[0].rss_indirection_tbl;
3592         u16 rss_size = vport[0].alloc_rss_size;
3593         u8 *key = vport[0].rss_hash_key;
3594         u8 hfunc = vport[0].rss_algo;
3595         u16 tc_offset[HCLGE_MAX_TC_NUM];
3596         u16 tc_valid[HCLGE_MAX_TC_NUM];
3597         u16 tc_size[HCLGE_MAX_TC_NUM];
3598         u16 roundup_size;
3599         int i, ret;
3600
3601         ret = hclge_set_rss_indir_table(hdev, rss_indir);
3602         if (ret)
3603                 return ret;
3604
3605         ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3606         if (ret)
3607                 return ret;
3608
3609         ret = hclge_set_rss_input_tuple(hdev);
3610         if (ret)
3611                 return ret;
3612
3613         /* Each TC have the same queue size, and tc_size set to hardware is
3614          * the log2 of roundup power of two of rss_size, the acutal queue
3615          * size is limited by indirection table.
3616          */
3617         if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3618                 dev_err(&hdev->pdev->dev,
3619                         "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3620                         rss_size);
3621                 return -EINVAL;
3622         }
3623
3624         roundup_size = roundup_pow_of_two(rss_size);
3625         roundup_size = ilog2(roundup_size);
3626
3627         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3628                 tc_valid[i] = 0;
3629
3630                 if (!(hdev->hw_tc_map & BIT(i)))
3631                         continue;
3632
3633                 tc_valid[i] = 1;
3634                 tc_size[i] = roundup_size;
3635                 tc_offset[i] = rss_size * i;
3636         }
3637
3638         return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3639 }
3640
3641 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3642 {
3643         struct hclge_vport *vport = hdev->vport;
3644         int i, j;
3645
3646         for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3647                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3648                         vport[j].rss_indirection_tbl[i] =
3649                                 i % vport[j].alloc_rss_size;
3650         }
3651 }
3652
3653 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3654 {
3655         struct hclge_vport *vport = hdev->vport;
3656         int i;
3657
3658         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3659                 vport[i].rss_tuple_sets.ipv4_tcp_en =
3660                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3661                 vport[i].rss_tuple_sets.ipv4_udp_en =
3662                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3663                 vport[i].rss_tuple_sets.ipv4_sctp_en =
3664                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3665                 vport[i].rss_tuple_sets.ipv4_fragment_en =
3666                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3667                 vport[i].rss_tuple_sets.ipv6_tcp_en =
3668                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3669                 vport[i].rss_tuple_sets.ipv6_udp_en =
3670                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3671                 vport[i].rss_tuple_sets.ipv6_sctp_en =
3672                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3673                 vport[i].rss_tuple_sets.ipv6_fragment_en =
3674                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3675
3676                 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3677
3678                 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3679         }
3680
3681         hclge_rss_indir_init_cfg(hdev);
3682 }
3683
3684 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3685                                 int vector_id, bool en,
3686                                 struct hnae3_ring_chain_node *ring_chain)
3687 {
3688         struct hclge_dev *hdev = vport->back;
3689         struct hnae3_ring_chain_node *node;
3690         struct hclge_desc desc;
3691         struct hclge_ctrl_vector_chain_cmd *req
3692                 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3693         enum hclge_cmd_status status;
3694         enum hclge_opcode_type op;
3695         u16 tqp_type_and_id;
3696         int i;
3697
3698         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3699         hclge_cmd_setup_basic_desc(&desc, op, false);
3700         req->int_vector_id = vector_id;
3701
3702         i = 0;
3703         for (node = ring_chain; node; node = node->next) {
3704                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3705                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
3706                                 HCLGE_INT_TYPE_S,
3707                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3708                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3709                                 HCLGE_TQP_ID_S, node->tqp_index);
3710                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3711                                 HCLGE_INT_GL_IDX_S,
3712                                 hnae3_get_field(node->int_gl_idx,
3713                                                 HNAE3_RING_GL_IDX_M,
3714                                                 HNAE3_RING_GL_IDX_S));
3715                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3716                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3717                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3718                         req->vfid = vport->vport_id;
3719
3720                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
3721                         if (status) {
3722                                 dev_err(&hdev->pdev->dev,
3723                                         "Map TQP fail, status is %d.\n",
3724                                         status);
3725                                 return -EIO;
3726                         }
3727                         i = 0;
3728
3729                         hclge_cmd_setup_basic_desc(&desc,
3730                                                    op,
3731                                                    false);
3732                         req->int_vector_id = vector_id;
3733                 }
3734         }
3735
3736         if (i > 0) {
3737                 req->int_cause_num = i;
3738                 req->vfid = vport->vport_id;
3739                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3740                 if (status) {
3741                         dev_err(&hdev->pdev->dev,
3742                                 "Map TQP fail, status is %d.\n", status);
3743                         return -EIO;
3744                 }
3745         }
3746
3747         return 0;
3748 }
3749
3750 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3751                                     int vector,
3752                                     struct hnae3_ring_chain_node *ring_chain)
3753 {
3754         struct hclge_vport *vport = hclge_get_vport(handle);
3755         struct hclge_dev *hdev = vport->back;
3756         int vector_id;
3757
3758         vector_id = hclge_get_vector_index(hdev, vector);
3759         if (vector_id < 0) {
3760                 dev_err(&hdev->pdev->dev,
3761                         "Get vector index fail. vector_id =%d\n", vector_id);
3762                 return vector_id;
3763         }
3764
3765         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3766 }
3767
3768 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3769                                        int vector,
3770                                        struct hnae3_ring_chain_node *ring_chain)
3771 {
3772         struct hclge_vport *vport = hclge_get_vport(handle);
3773         struct hclge_dev *hdev = vport->back;
3774         int vector_id, ret;
3775
3776         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3777                 return 0;
3778
3779         vector_id = hclge_get_vector_index(hdev, vector);
3780         if (vector_id < 0) {
3781                 dev_err(&handle->pdev->dev,
3782                         "Get vector index fail. ret =%d\n", vector_id);
3783                 return vector_id;
3784         }
3785
3786         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3787         if (ret)
3788                 dev_err(&handle->pdev->dev,
3789                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3790                         vector_id,
3791                         ret);
3792
3793         return ret;
3794 }
3795
3796 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3797                                struct hclge_promisc_param *param)
3798 {
3799         struct hclge_promisc_cfg_cmd *req;
3800         struct hclge_desc desc;
3801         int ret;
3802
3803         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3804
3805         req = (struct hclge_promisc_cfg_cmd *)desc.data;
3806         req->vf_id = param->vf_id;
3807
3808         /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3809          * pdev revision(0x20), new revision support them. The
3810          * value of this two fields will not return error when driver
3811          * send command to fireware in revision(0x20).
3812          */
3813         req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3814                 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3815
3816         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3817         if (ret)
3818                 dev_err(&hdev->pdev->dev,
3819                         "Set promisc mode fail, status is %d.\n", ret);
3820
3821         return ret;
3822 }
3823
3824 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3825                               bool en_mc, bool en_bc, int vport_id)
3826 {
3827         if (!param)
3828                 return;
3829
3830         memset(param, 0, sizeof(struct hclge_promisc_param));
3831         if (en_uc)
3832                 param->enable = HCLGE_PROMISC_EN_UC;
3833         if (en_mc)
3834                 param->enable |= HCLGE_PROMISC_EN_MC;
3835         if (en_bc)
3836                 param->enable |= HCLGE_PROMISC_EN_BC;
3837         param->vf_id = vport_id;
3838 }
3839
3840 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3841                                   bool en_mc_pmc)
3842 {
3843         struct hclge_vport *vport = hclge_get_vport(handle);
3844         struct hclge_dev *hdev = vport->back;
3845         struct hclge_promisc_param param;
3846
3847         hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3848                                  vport->vport_id);
3849         return hclge_cmd_set_promisc_mode(hdev, &param);
3850 }
3851
3852 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3853 {
3854         struct hclge_get_fd_mode_cmd *req;
3855         struct hclge_desc desc;
3856         int ret;
3857
3858         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3859
3860         req = (struct hclge_get_fd_mode_cmd *)desc.data;
3861
3862         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3863         if (ret) {
3864                 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3865                 return ret;
3866         }
3867
3868         *fd_mode = req->mode;
3869
3870         return ret;
3871 }
3872
3873 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3874                                    u32 *stage1_entry_num,
3875                                    u32 *stage2_entry_num,
3876                                    u16 *stage1_counter_num,
3877                                    u16 *stage2_counter_num)
3878 {
3879         struct hclge_get_fd_allocation_cmd *req;
3880         struct hclge_desc desc;
3881         int ret;
3882
3883         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3884
3885         req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3886
3887         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3888         if (ret) {
3889                 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3890                         ret);
3891                 return ret;
3892         }
3893
3894         *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3895         *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3896         *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3897         *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3898
3899         return ret;
3900 }
3901
3902 static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3903 {
3904         struct hclge_set_fd_key_config_cmd *req;
3905         struct hclge_fd_key_cfg *stage;
3906         struct hclge_desc desc;
3907         int ret;
3908
3909         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3910
3911         req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3912         stage = &hdev->fd_cfg.key_cfg[stage_num];
3913         req->stage = stage_num;
3914         req->key_select = stage->key_sel;
3915         req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3916         req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3917         req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3918         req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3919         req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3920         req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3921
3922         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3923         if (ret)
3924                 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3925
3926         return ret;
3927 }
3928
3929 static int hclge_init_fd_config(struct hclge_dev *hdev)
3930 {
3931 #define LOW_2_WORDS             0x03
3932         struct hclge_fd_key_cfg *key_cfg;
3933         int ret;
3934
3935         if (!hnae3_dev_fd_supported(hdev))
3936                 return 0;
3937
3938         ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3939         if (ret)
3940                 return ret;
3941
3942         switch (hdev->fd_cfg.fd_mode) {
3943         case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3944                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3945                 break;
3946         case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3947                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3948                 break;
3949         default:
3950                 dev_err(&hdev->pdev->dev,
3951                         "Unsupported flow director mode %d\n",
3952                         hdev->fd_cfg.fd_mode);
3953                 return -EOPNOTSUPP;
3954         }
3955
3956         hdev->fd_cfg.fd_en = true;
3957         hdev->fd_cfg.proto_support =
3958                 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3959                 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3960         key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3961         key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3962         key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3963         key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3964         key_cfg->outer_sipv6_word_en = 0;
3965         key_cfg->outer_dipv6_word_en = 0;
3966
3967         key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3968                                 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3969                                 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3970                                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3971
3972         /* If use max 400bit key, we can support tuples for ether type */
3973         if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3974                 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3975                 key_cfg->tuple_active |=
3976                                 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3977         }
3978
3979         /* roce_type is used to filter roce frames
3980          * dst_vport is used to specify the rule
3981          */
3982         key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3983
3984         ret = hclge_get_fd_allocation(hdev,
3985                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3986                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3987                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3988                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3989         if (ret)
3990                 return ret;
3991
3992         return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3993 }
3994
3995 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3996                                 int loc, u8 *key, bool is_add)
3997 {
3998         struct hclge_fd_tcam_config_1_cmd *req1;
3999         struct hclge_fd_tcam_config_2_cmd *req2;
4000         struct hclge_fd_tcam_config_3_cmd *req3;
4001         struct hclge_desc desc[3];
4002         int ret;
4003
4004         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
4005         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4006         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
4007         desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4008         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
4009
4010         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
4011         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
4012         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
4013
4014         req1->stage = stage;
4015         req1->xy_sel = sel_x ? 1 : 0;
4016         hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
4017         req1->index = cpu_to_le32(loc);
4018         req1->entry_vld = sel_x ? is_add : 0;
4019
4020         if (key) {
4021                 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
4022                 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
4023                        sizeof(req2->tcam_data));
4024                 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
4025                        sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
4026         }
4027
4028         ret = hclge_cmd_send(&hdev->hw, desc, 3);
4029         if (ret)
4030                 dev_err(&hdev->pdev->dev,
4031                         "config tcam key fail, ret=%d\n",
4032                         ret);
4033
4034         return ret;
4035 }
4036
4037 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
4038                               struct hclge_fd_ad_data *action)
4039 {
4040         struct hclge_fd_ad_config_cmd *req;
4041         struct hclge_desc desc;
4042         u64 ad_data = 0;
4043         int ret;
4044
4045         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
4046
4047         req = (struct hclge_fd_ad_config_cmd *)desc.data;
4048         req->index = cpu_to_le32(loc);
4049         req->stage = stage;
4050
4051         hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
4052                       action->write_rule_id_to_bd);
4053         hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
4054                         action->rule_id);
4055         ad_data <<= 32;
4056         hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
4057         hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
4058                       action->forward_to_direct_queue);
4059         hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
4060                         action->queue_id);
4061         hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
4062         hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
4063                         HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
4064         hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
4065         hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
4066                         action->counter_id);
4067
4068         req->ad_data = cpu_to_le64(ad_data);
4069         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4070         if (ret)
4071                 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
4072
4073         return ret;
4074 }
4075
4076 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
4077                                    struct hclge_fd_rule *rule)
4078 {
4079         u16 tmp_x_s, tmp_y_s;
4080         u32 tmp_x_l, tmp_y_l;
4081         int i;
4082
4083         if (rule->unused_tuple & tuple_bit)
4084                 return true;
4085
4086         switch (tuple_bit) {
4087         case 0:
4088                 return false;
4089         case BIT(INNER_DST_MAC):
4090                 for (i = 0; i < 6; i++) {
4091                         calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
4092                                rule->tuples_mask.dst_mac[i]);
4093                         calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
4094                                rule->tuples_mask.dst_mac[i]);
4095                 }
4096
4097                 return true;
4098         case BIT(INNER_SRC_MAC):
4099                 for (i = 0; i < 6; i++) {
4100                         calc_x(key_x[5 - i], rule->tuples.src_mac[i],
4101                                rule->tuples.src_mac[i]);
4102                         calc_y(key_y[5 - i], rule->tuples.src_mac[i],
4103                                rule->tuples.src_mac[i]);
4104                 }
4105
4106                 return true;
4107         case BIT(INNER_VLAN_TAG_FST):
4108                 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
4109                        rule->tuples_mask.vlan_tag1);
4110                 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
4111                        rule->tuples_mask.vlan_tag1);
4112                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4113                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4114
4115                 return true;
4116         case BIT(INNER_ETH_TYPE):
4117                 calc_x(tmp_x_s, rule->tuples.ether_proto,
4118                        rule->tuples_mask.ether_proto);
4119                 calc_y(tmp_y_s, rule->tuples.ether_proto,
4120                        rule->tuples_mask.ether_proto);
4121                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4122                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4123
4124                 return true;
4125         case BIT(INNER_IP_TOS):
4126                 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
4127                 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
4128
4129                 return true;
4130         case BIT(INNER_IP_PROTO):
4131                 calc_x(*key_x, rule->tuples.ip_proto,
4132                        rule->tuples_mask.ip_proto);
4133                 calc_y(*key_y, rule->tuples.ip_proto,
4134                        rule->tuples_mask.ip_proto);
4135
4136                 return true;
4137         case BIT(INNER_SRC_IP):
4138                 calc_x(tmp_x_l, rule->tuples.src_ip[3],
4139                        rule->tuples_mask.src_ip[3]);
4140                 calc_y(tmp_y_l, rule->tuples.src_ip[3],
4141                        rule->tuples_mask.src_ip[3]);
4142                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
4143                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
4144
4145                 return true;
4146         case BIT(INNER_DST_IP):
4147                 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
4148                        rule->tuples_mask.dst_ip[3]);
4149                 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
4150                        rule->tuples_mask.dst_ip[3]);
4151                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
4152                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
4153
4154                 return true;
4155         case BIT(INNER_SRC_PORT):
4156                 calc_x(tmp_x_s, rule->tuples.src_port,
4157                        rule->tuples_mask.src_port);
4158                 calc_y(tmp_y_s, rule->tuples.src_port,
4159                        rule->tuples_mask.src_port);
4160                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4161                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4162
4163                 return true;
4164         case BIT(INNER_DST_PORT):
4165                 calc_x(tmp_x_s, rule->tuples.dst_port,
4166                        rule->tuples_mask.dst_port);
4167                 calc_y(tmp_y_s, rule->tuples.dst_port,
4168                        rule->tuples_mask.dst_port);
4169                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4170                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4171
4172                 return true;
4173         default:
4174                 return false;
4175         }
4176 }
4177
4178 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
4179                                  u8 vf_id, u8 network_port_id)
4180 {
4181         u32 port_number = 0;
4182
4183         if (port_type == HOST_PORT) {
4184                 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
4185                                 pf_id);
4186                 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
4187                                 vf_id);
4188                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
4189         } else {
4190                 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
4191                                 HCLGE_NETWORK_PORT_ID_S, network_port_id);
4192                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
4193         }
4194
4195         return port_number;
4196 }
4197
4198 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
4199                                        __le32 *key_x, __le32 *key_y,
4200                                        struct hclge_fd_rule *rule)
4201 {
4202         u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
4203         u8 cur_pos = 0, tuple_size, shift_bits;
4204         int i;
4205
4206         for (i = 0; i < MAX_META_DATA; i++) {
4207                 tuple_size = meta_data_key_info[i].key_length;
4208                 tuple_bit = key_cfg->meta_data_active & BIT(i);
4209
4210                 switch (tuple_bit) {
4211                 case BIT(ROCE_TYPE):
4212                         hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
4213                         cur_pos += tuple_size;
4214                         break;
4215                 case BIT(DST_VPORT):
4216                         port_number = hclge_get_port_number(HOST_PORT, 0,
4217                                                             rule->vf_id, 0);
4218                         hnae3_set_field(meta_data,
4219                                         GENMASK(cur_pos + tuple_size, cur_pos),
4220                                         cur_pos, port_number);
4221                         cur_pos += tuple_size;
4222                         break;
4223                 default:
4224                         break;
4225                 }
4226         }
4227
4228         calc_x(tmp_x, meta_data, 0xFFFFFFFF);
4229         calc_y(tmp_y, meta_data, 0xFFFFFFFF);
4230         shift_bits = sizeof(meta_data) * 8 - cur_pos;
4231
4232         *key_x = cpu_to_le32(tmp_x << shift_bits);
4233         *key_y = cpu_to_le32(tmp_y << shift_bits);
4234 }
4235
4236 /* A complete key is combined with meta data key and tuple key.
4237  * Meta data key is stored at the MSB region, and tuple key is stored at
4238  * the LSB region, unused bits will be filled 0.
4239  */
4240 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
4241                             struct hclge_fd_rule *rule)
4242 {
4243         struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
4244         u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
4245         u8 *cur_key_x, *cur_key_y;
4246         int i, ret, tuple_size;
4247         u8 meta_data_region;
4248
4249         memset(key_x, 0, sizeof(key_x));
4250         memset(key_y, 0, sizeof(key_y));
4251         cur_key_x = key_x;
4252         cur_key_y = key_y;
4253
4254         for (i = 0 ; i < MAX_TUPLE; i++) {
4255                 bool tuple_valid;
4256                 u32 check_tuple;
4257
4258                 tuple_size = tuple_key_info[i].key_length / 8;
4259                 check_tuple = key_cfg->tuple_active & BIT(i);
4260
4261                 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
4262                                                      cur_key_y, rule);
4263                 if (tuple_valid) {
4264                         cur_key_x += tuple_size;
4265                         cur_key_y += tuple_size;
4266                 }
4267         }
4268
4269         meta_data_region = hdev->fd_cfg.max_key_length / 8 -
4270                         MAX_META_DATA_LENGTH / 8;
4271
4272         hclge_fd_convert_meta_data(key_cfg,
4273                                    (__le32 *)(key_x + meta_data_region),
4274                                    (__le32 *)(key_y + meta_data_region),
4275                                    rule);
4276
4277         ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
4278                                    true);
4279         if (ret) {
4280                 dev_err(&hdev->pdev->dev,
4281                         "fd key_y config fail, loc=%d, ret=%d\n",
4282                         rule->queue_id, ret);
4283                 return ret;
4284         }
4285
4286         ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
4287                                    true);
4288         if (ret)
4289                 dev_err(&hdev->pdev->dev,
4290                         "fd key_x config fail, loc=%d, ret=%d\n",
4291                         rule->queue_id, ret);
4292         return ret;
4293 }
4294
4295 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
4296                                struct hclge_fd_rule *rule)
4297 {
4298         struct hclge_fd_ad_data ad_data;
4299
4300         ad_data.ad_id = rule->location;
4301
4302         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4303                 ad_data.drop_packet = true;
4304                 ad_data.forward_to_direct_queue = false;
4305                 ad_data.queue_id = 0;
4306         } else {
4307                 ad_data.drop_packet = false;
4308                 ad_data.forward_to_direct_queue = true;
4309                 ad_data.queue_id = rule->queue_id;
4310         }
4311
4312         ad_data.use_counter = false;
4313         ad_data.counter_id = 0;
4314
4315         ad_data.use_next_stage = false;
4316         ad_data.next_input_key = 0;
4317
4318         ad_data.write_rule_id_to_bd = true;
4319         ad_data.rule_id = rule->location;
4320
4321         return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
4322 }
4323
4324 static int hclge_fd_check_spec(struct hclge_dev *hdev,
4325                                struct ethtool_rx_flow_spec *fs, u32 *unused)
4326 {
4327         struct ethtool_tcpip4_spec *tcp_ip4_spec;
4328         struct ethtool_usrip4_spec *usr_ip4_spec;
4329         struct ethtool_tcpip6_spec *tcp_ip6_spec;
4330         struct ethtool_usrip6_spec *usr_ip6_spec;
4331         struct ethhdr *ether_spec;
4332
4333         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4334                 return -EINVAL;
4335
4336         if (!(fs->flow_type & hdev->fd_cfg.proto_support))
4337                 return -EOPNOTSUPP;
4338
4339         if ((fs->flow_type & FLOW_EXT) &&
4340             (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
4341                 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
4342                 return -EOPNOTSUPP;
4343         }
4344
4345         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4346         case SCTP_V4_FLOW:
4347         case TCP_V4_FLOW:
4348         case UDP_V4_FLOW:
4349                 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
4350                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
4351
4352                 if (!tcp_ip4_spec->ip4src)
4353                         *unused |= BIT(INNER_SRC_IP);
4354
4355                 if (!tcp_ip4_spec->ip4dst)
4356                         *unused |= BIT(INNER_DST_IP);
4357
4358                 if (!tcp_ip4_spec->psrc)
4359                         *unused |= BIT(INNER_SRC_PORT);
4360
4361                 if (!tcp_ip4_spec->pdst)
4362                         *unused |= BIT(INNER_DST_PORT);
4363
4364                 if (!tcp_ip4_spec->tos)
4365                         *unused |= BIT(INNER_IP_TOS);
4366
4367                 break;
4368         case IP_USER_FLOW:
4369                 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
4370                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4371                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
4372
4373                 if (!usr_ip4_spec->ip4src)
4374                         *unused |= BIT(INNER_SRC_IP);
4375
4376                 if (!usr_ip4_spec->ip4dst)
4377                         *unused |= BIT(INNER_DST_IP);
4378
4379                 if (!usr_ip4_spec->tos)
4380                         *unused |= BIT(INNER_IP_TOS);
4381
4382                 if (!usr_ip4_spec->proto)
4383                         *unused |= BIT(INNER_IP_PROTO);
4384
4385                 if (usr_ip4_spec->l4_4_bytes)
4386                         return -EOPNOTSUPP;
4387
4388                 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
4389                         return -EOPNOTSUPP;
4390
4391                 break;
4392         case SCTP_V6_FLOW:
4393         case TCP_V6_FLOW:
4394         case UDP_V6_FLOW:
4395                 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
4396                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4397                         BIT(INNER_IP_TOS);
4398
4399                 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
4400                     !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
4401                         *unused |= BIT(INNER_SRC_IP);
4402
4403                 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
4404                     !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
4405                         *unused |= BIT(INNER_DST_IP);
4406
4407                 if (!tcp_ip6_spec->psrc)
4408                         *unused |= BIT(INNER_SRC_PORT);
4409
4410                 if (!tcp_ip6_spec->pdst)
4411                         *unused |= BIT(INNER_DST_PORT);
4412
4413                 if (tcp_ip6_spec->tclass)
4414                         return -EOPNOTSUPP;
4415
4416                 break;
4417         case IPV6_USER_FLOW:
4418                 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
4419                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4420                         BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
4421                         BIT(INNER_DST_PORT);
4422
4423                 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
4424                     !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
4425                         *unused |= BIT(INNER_SRC_IP);
4426
4427                 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
4428                     !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
4429                         *unused |= BIT(INNER_DST_IP);
4430
4431                 if (!usr_ip6_spec->l4_proto)
4432                         *unused |= BIT(INNER_IP_PROTO);
4433
4434                 if (usr_ip6_spec->tclass)
4435                         return -EOPNOTSUPP;
4436
4437                 if (usr_ip6_spec->l4_4_bytes)
4438                         return -EOPNOTSUPP;
4439
4440                 break;
4441         case ETHER_FLOW:
4442                 ether_spec = &fs->h_u.ether_spec;
4443                 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
4444                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
4445                         BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
4446
4447                 if (is_zero_ether_addr(ether_spec->h_source))
4448                         *unused |= BIT(INNER_SRC_MAC);
4449
4450                 if (is_zero_ether_addr(ether_spec->h_dest))
4451                         *unused |= BIT(INNER_DST_MAC);
4452
4453                 if (!ether_spec->h_proto)
4454                         *unused |= BIT(INNER_ETH_TYPE);
4455
4456                 break;
4457         default:
4458                 return -EOPNOTSUPP;
4459         }
4460
4461         if ((fs->flow_type & FLOW_EXT)) {
4462                 if (fs->h_ext.vlan_etype)
4463                         return -EOPNOTSUPP;
4464                 if (!fs->h_ext.vlan_tci)
4465                         *unused |= BIT(INNER_VLAN_TAG_FST);
4466
4467                 if (fs->m_ext.vlan_tci) {
4468                         if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
4469                                 return -EINVAL;
4470                 }
4471         } else {
4472                 *unused |= BIT(INNER_VLAN_TAG_FST);
4473         }
4474
4475         if (fs->flow_type & FLOW_MAC_EXT) {
4476                 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
4477                         return -EOPNOTSUPP;
4478
4479                 if (is_zero_ether_addr(fs->h_ext.h_dest))
4480                         *unused |= BIT(INNER_DST_MAC);
4481                 else
4482                         *unused &= ~(BIT(INNER_DST_MAC));
4483         }
4484
4485         return 0;
4486 }
4487
4488 static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
4489 {
4490         struct hclge_fd_rule *rule = NULL;
4491         struct hlist_node *node2;
4492
4493         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4494                 if (rule->location >= location)
4495                         break;
4496         }
4497
4498         return  rule && rule->location == location;
4499 }
4500
4501 static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
4502                                      struct hclge_fd_rule *new_rule,
4503                                      u16 location,
4504                                      bool is_add)
4505 {
4506         struct hclge_fd_rule *rule = NULL, *parent = NULL;
4507         struct hlist_node *node2;
4508
4509         if (is_add && !new_rule)
4510                 return -EINVAL;
4511
4512         hlist_for_each_entry_safe(rule, node2,
4513                                   &hdev->fd_rule_list, rule_node) {
4514                 if (rule->location >= location)
4515                         break;
4516                 parent = rule;
4517         }
4518
4519         if (rule && rule->location == location) {
4520                 hlist_del(&rule->rule_node);
4521                 kfree(rule);
4522                 hdev->hclge_fd_rule_num--;
4523
4524                 if (!is_add)
4525                         return 0;
4526
4527         } else if (!is_add) {
4528                 dev_err(&hdev->pdev->dev,
4529                         "delete fail, rule %d is inexistent\n",
4530                         location);
4531                 return -EINVAL;
4532         }
4533
4534         INIT_HLIST_NODE(&new_rule->rule_node);
4535
4536         if (parent)
4537                 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4538         else
4539                 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4540
4541         hdev->hclge_fd_rule_num++;
4542
4543         return 0;
4544 }
4545
4546 static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4547                               struct ethtool_rx_flow_spec *fs,
4548                               struct hclge_fd_rule *rule)
4549 {
4550         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4551
4552         switch (flow_type) {
4553         case SCTP_V4_FLOW:
4554         case TCP_V4_FLOW:
4555         case UDP_V4_FLOW:
4556                 rule->tuples.src_ip[3] =
4557                                 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4558                 rule->tuples_mask.src_ip[3] =
4559                                 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4560
4561                 rule->tuples.dst_ip[3] =
4562                                 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4563                 rule->tuples_mask.dst_ip[3] =
4564                                 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4565
4566                 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4567                 rule->tuples_mask.src_port =
4568                                 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4569
4570                 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4571                 rule->tuples_mask.dst_port =
4572                                 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4573
4574                 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4575                 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4576
4577                 rule->tuples.ether_proto = ETH_P_IP;
4578                 rule->tuples_mask.ether_proto = 0xFFFF;
4579
4580                 break;
4581         case IP_USER_FLOW:
4582                 rule->tuples.src_ip[3] =
4583                                 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4584                 rule->tuples_mask.src_ip[3] =
4585                                 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4586
4587                 rule->tuples.dst_ip[3] =
4588                                 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4589                 rule->tuples_mask.dst_ip[3] =
4590                                 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4591
4592                 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4593                 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4594
4595                 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4596                 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4597
4598                 rule->tuples.ether_proto = ETH_P_IP;
4599                 rule->tuples_mask.ether_proto = 0xFFFF;
4600
4601                 break;
4602         case SCTP_V6_FLOW:
4603         case TCP_V6_FLOW:
4604         case UDP_V6_FLOW:
4605                 be32_to_cpu_array(rule->tuples.src_ip,
4606                                   fs->h_u.tcp_ip6_spec.ip6src, 4);
4607                 be32_to_cpu_array(rule->tuples_mask.src_ip,
4608                                   fs->m_u.tcp_ip6_spec.ip6src, 4);
4609
4610                 be32_to_cpu_array(rule->tuples.dst_ip,
4611                                   fs->h_u.tcp_ip6_spec.ip6dst, 4);
4612                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4613                                   fs->m_u.tcp_ip6_spec.ip6dst, 4);
4614
4615                 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4616                 rule->tuples_mask.src_port =
4617                                 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4618
4619                 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4620                 rule->tuples_mask.dst_port =
4621                                 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4622
4623                 rule->tuples.ether_proto = ETH_P_IPV6;
4624                 rule->tuples_mask.ether_proto = 0xFFFF;
4625
4626                 break;
4627         case IPV6_USER_FLOW:
4628                 be32_to_cpu_array(rule->tuples.src_ip,
4629                                   fs->h_u.usr_ip6_spec.ip6src, 4);
4630                 be32_to_cpu_array(rule->tuples_mask.src_ip,
4631                                   fs->m_u.usr_ip6_spec.ip6src, 4);
4632
4633                 be32_to_cpu_array(rule->tuples.dst_ip,
4634                                   fs->h_u.usr_ip6_spec.ip6dst, 4);
4635                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4636                                   fs->m_u.usr_ip6_spec.ip6dst, 4);
4637
4638                 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4639                 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4640
4641                 rule->tuples.ether_proto = ETH_P_IPV6;
4642                 rule->tuples_mask.ether_proto = 0xFFFF;
4643
4644                 break;
4645         case ETHER_FLOW:
4646                 ether_addr_copy(rule->tuples.src_mac,
4647                                 fs->h_u.ether_spec.h_source);
4648                 ether_addr_copy(rule->tuples_mask.src_mac,
4649                                 fs->m_u.ether_spec.h_source);
4650
4651                 ether_addr_copy(rule->tuples.dst_mac,
4652                                 fs->h_u.ether_spec.h_dest);
4653                 ether_addr_copy(rule->tuples_mask.dst_mac,
4654                                 fs->m_u.ether_spec.h_dest);
4655
4656                 rule->tuples.ether_proto =
4657                                 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4658                 rule->tuples_mask.ether_proto =
4659                                 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4660
4661                 break;
4662         default:
4663                 return -EOPNOTSUPP;
4664         }
4665
4666         switch (flow_type) {
4667         case SCTP_V4_FLOW:
4668         case SCTP_V6_FLOW:
4669                 rule->tuples.ip_proto = IPPROTO_SCTP;
4670                 rule->tuples_mask.ip_proto = 0xFF;
4671                 break;
4672         case TCP_V4_FLOW:
4673         case TCP_V6_FLOW:
4674                 rule->tuples.ip_proto = IPPROTO_TCP;
4675                 rule->tuples_mask.ip_proto = 0xFF;
4676                 break;
4677         case UDP_V4_FLOW:
4678         case UDP_V6_FLOW:
4679                 rule->tuples.ip_proto = IPPROTO_UDP;
4680                 rule->tuples_mask.ip_proto = 0xFF;
4681                 break;
4682         default:
4683                 break;
4684         }
4685
4686         if ((fs->flow_type & FLOW_EXT)) {
4687                 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4688                 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4689         }
4690
4691         if (fs->flow_type & FLOW_MAC_EXT) {
4692                 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4693                 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4694         }
4695
4696         return 0;
4697 }
4698
4699 static int hclge_add_fd_entry(struct hnae3_handle *handle,
4700                               struct ethtool_rxnfc *cmd)
4701 {
4702         struct hclge_vport *vport = hclge_get_vport(handle);
4703         struct hclge_dev *hdev = vport->back;
4704         u16 dst_vport_id = 0, q_index = 0;
4705         struct ethtool_rx_flow_spec *fs;
4706         struct hclge_fd_rule *rule;
4707         u32 unused = 0;
4708         u8 action;
4709         int ret;
4710
4711         if (!hnae3_dev_fd_supported(hdev))
4712                 return -EOPNOTSUPP;
4713
4714         if (!hdev->fd_cfg.fd_en) {
4715                 dev_warn(&hdev->pdev->dev,
4716                          "Please enable flow director first\n");
4717                 return -EOPNOTSUPP;
4718         }
4719
4720         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4721
4722         ret = hclge_fd_check_spec(hdev, fs, &unused);
4723         if (ret) {
4724                 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4725                 return ret;
4726         }
4727
4728         if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4729                 action = HCLGE_FD_ACTION_DROP_PACKET;
4730         } else {
4731                 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4732                 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4733                 u16 tqps;
4734
4735                 if (vf > hdev->num_req_vfs) {
4736                         dev_err(&hdev->pdev->dev,
4737                                 "Error: vf id (%d) > max vf num (%d)\n",
4738                                 vf, hdev->num_req_vfs);
4739                         return -EINVAL;
4740                 }
4741
4742                 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4743                 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4744
4745                 if (ring >= tqps) {
4746                         dev_err(&hdev->pdev->dev,
4747                                 "Error: queue id (%d) > max tqp num (%d)\n",
4748                                 ring, tqps - 1);
4749                         return -EINVAL;
4750                 }
4751
4752                 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4753                 q_index = ring;
4754         }
4755
4756         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4757         if (!rule)
4758                 return -ENOMEM;
4759
4760         ret = hclge_fd_get_tuple(hdev, fs, rule);
4761         if (ret)
4762                 goto free_rule;
4763
4764         rule->flow_type = fs->flow_type;
4765
4766         rule->location = fs->location;
4767         rule->unused_tuple = unused;
4768         rule->vf_id = dst_vport_id;
4769         rule->queue_id = q_index;
4770         rule->action = action;
4771
4772         ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4773         if (ret)
4774                 goto free_rule;
4775
4776         ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4777         if (ret)
4778                 goto free_rule;
4779
4780         ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4781         if (ret)
4782                 goto free_rule;
4783
4784         return ret;
4785
4786 free_rule:
4787         kfree(rule);
4788         return ret;
4789 }
4790
4791 static int hclge_del_fd_entry(struct hnae3_handle *handle,
4792                               struct ethtool_rxnfc *cmd)
4793 {
4794         struct hclge_vport *vport = hclge_get_vport(handle);
4795         struct hclge_dev *hdev = vport->back;
4796         struct ethtool_rx_flow_spec *fs;
4797         int ret;
4798
4799         if (!hnae3_dev_fd_supported(hdev))
4800                 return -EOPNOTSUPP;
4801
4802         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4803
4804         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4805                 return -EINVAL;
4806
4807         if (!hclge_fd_rule_exist(hdev, fs->location)) {
4808                 dev_err(&hdev->pdev->dev,
4809                         "Delete fail, rule %d is inexistent\n",
4810                         fs->location);
4811                 return -ENOENT;
4812         }
4813
4814         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4815                                    fs->location, NULL, false);
4816         if (ret)
4817                 return ret;
4818
4819         return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4820                                          false);
4821 }
4822
4823 static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4824                                      bool clear_list)
4825 {
4826         struct hclge_vport *vport = hclge_get_vport(handle);
4827         struct hclge_dev *hdev = vport->back;
4828         struct hclge_fd_rule *rule;
4829         struct hlist_node *node;
4830
4831         if (!hnae3_dev_fd_supported(hdev))
4832                 return;
4833
4834         if (clear_list) {
4835                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4836                                           rule_node) {
4837                         hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4838                                              rule->location, NULL, false);
4839                         hlist_del(&rule->rule_node);
4840                         kfree(rule);
4841                         hdev->hclge_fd_rule_num--;
4842                 }
4843         } else {
4844                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4845                                           rule_node)
4846                         hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4847                                              rule->location, NULL, false);
4848         }
4849 }
4850
4851 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4852 {
4853         struct hclge_vport *vport = hclge_get_vport(handle);
4854         struct hclge_dev *hdev = vport->back;
4855         struct hclge_fd_rule *rule;
4856         struct hlist_node *node;
4857         int ret;
4858
4859         /* Return ok here, because reset error handling will check this
4860          * return value. If error is returned here, the reset process will
4861          * fail.
4862          */
4863         if (!hnae3_dev_fd_supported(hdev))
4864                 return 0;
4865
4866         /* if fd is disabled, should not restore it when reset */
4867         if (!hdev->fd_cfg.fd_en)
4868                 return 0;
4869
4870         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4871                 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4872                 if (!ret)
4873                         ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4874
4875                 if (ret) {
4876                         dev_warn(&hdev->pdev->dev,
4877                                  "Restore rule %d failed, remove it\n",
4878                                  rule->location);
4879                         hlist_del(&rule->rule_node);
4880                         kfree(rule);
4881                         hdev->hclge_fd_rule_num--;
4882                 }
4883         }
4884         return 0;
4885 }
4886
4887 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4888                                  struct ethtool_rxnfc *cmd)
4889 {
4890         struct hclge_vport *vport = hclge_get_vport(handle);
4891         struct hclge_dev *hdev = vport->back;
4892
4893         if (!hnae3_dev_fd_supported(hdev))
4894                 return -EOPNOTSUPP;
4895
4896         cmd->rule_cnt = hdev->hclge_fd_rule_num;
4897         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4898
4899         return 0;
4900 }
4901
4902 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4903                                   struct ethtool_rxnfc *cmd)
4904 {
4905         struct hclge_vport *vport = hclge_get_vport(handle);
4906         struct hclge_fd_rule *rule = NULL;
4907         struct hclge_dev *hdev = vport->back;
4908         struct ethtool_rx_flow_spec *fs;
4909         struct hlist_node *node2;
4910
4911         if (!hnae3_dev_fd_supported(hdev))
4912                 return -EOPNOTSUPP;
4913
4914         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4915
4916         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4917                 if (rule->location >= fs->location)
4918                         break;
4919         }
4920
4921         if (!rule || fs->location != rule->location)
4922                 return -ENOENT;
4923
4924         fs->flow_type = rule->flow_type;
4925         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4926         case SCTP_V4_FLOW:
4927         case TCP_V4_FLOW:
4928         case UDP_V4_FLOW:
4929                 fs->h_u.tcp_ip4_spec.ip4src =
4930                                 cpu_to_be32(rule->tuples.src_ip[3]);
4931                 fs->m_u.tcp_ip4_spec.ip4src =
4932                                 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4933                                 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4934
4935                 fs->h_u.tcp_ip4_spec.ip4dst =
4936                                 cpu_to_be32(rule->tuples.dst_ip[3]);
4937                 fs->m_u.tcp_ip4_spec.ip4dst =
4938                                 rule->unused_tuple & BIT(INNER_DST_IP) ?
4939                                 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4940
4941                 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4942                 fs->m_u.tcp_ip4_spec.psrc =
4943                                 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4944                                 0 : cpu_to_be16(rule->tuples_mask.src_port);
4945
4946                 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4947                 fs->m_u.tcp_ip4_spec.pdst =
4948                                 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4949                                 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4950
4951                 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4952                 fs->m_u.tcp_ip4_spec.tos =
4953                                 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4954                                 0 : rule->tuples_mask.ip_tos;
4955
4956                 break;
4957         case IP_USER_FLOW:
4958                 fs->h_u.usr_ip4_spec.ip4src =
4959                                 cpu_to_be32(rule->tuples.src_ip[3]);
4960                 fs->m_u.tcp_ip4_spec.ip4src =
4961                                 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4962                                 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4963
4964                 fs->h_u.usr_ip4_spec.ip4dst =
4965                                 cpu_to_be32(rule->tuples.dst_ip[3]);
4966                 fs->m_u.usr_ip4_spec.ip4dst =
4967                                 rule->unused_tuple & BIT(INNER_DST_IP) ?
4968                                 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4969
4970                 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4971                 fs->m_u.usr_ip4_spec.tos =
4972                                 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4973                                 0 : rule->tuples_mask.ip_tos;
4974
4975                 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4976                 fs->m_u.usr_ip4_spec.proto =
4977                                 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4978                                 0 : rule->tuples_mask.ip_proto;
4979
4980                 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4981
4982                 break;
4983         case SCTP_V6_FLOW:
4984         case TCP_V6_FLOW:
4985         case UDP_V6_FLOW:
4986                 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4987                                   rule->tuples.src_ip, 4);
4988                 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4989                         memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4990                 else
4991                         cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4992                                           rule->tuples_mask.src_ip, 4);
4993
4994                 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4995                                   rule->tuples.dst_ip, 4);
4996                 if (rule->unused_tuple & BIT(INNER_DST_IP))
4997                         memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4998                 else
4999                         cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
5000                                           rule->tuples_mask.dst_ip, 4);
5001
5002                 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
5003                 fs->m_u.tcp_ip6_spec.psrc =
5004                                 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
5005                                 0 : cpu_to_be16(rule->tuples_mask.src_port);
5006
5007                 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
5008                 fs->m_u.tcp_ip6_spec.pdst =
5009                                 rule->unused_tuple & BIT(INNER_DST_PORT) ?
5010                                 0 : cpu_to_be16(rule->tuples_mask.dst_port);
5011
5012                 break;
5013         case IPV6_USER_FLOW:
5014                 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
5015                                   rule->tuples.src_ip, 4);
5016                 if (rule->unused_tuple & BIT(INNER_SRC_IP))
5017                         memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
5018                 else
5019                         cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
5020                                           rule->tuples_mask.src_ip, 4);
5021
5022                 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
5023                                   rule->tuples.dst_ip, 4);
5024                 if (rule->unused_tuple & BIT(INNER_DST_IP))
5025                         memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
5026                 else
5027                         cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
5028                                           rule->tuples_mask.dst_ip, 4);
5029
5030                 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
5031                 fs->m_u.usr_ip6_spec.l4_proto =
5032                                 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
5033                                 0 : rule->tuples_mask.ip_proto;
5034
5035                 break;
5036         case ETHER_FLOW:
5037                 ether_addr_copy(fs->h_u.ether_spec.h_source,
5038                                 rule->tuples.src_mac);
5039                 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
5040                         eth_zero_addr(fs->m_u.ether_spec.h_source);
5041                 else
5042                         ether_addr_copy(fs->m_u.ether_spec.h_source,
5043                                         rule->tuples_mask.src_mac);
5044
5045                 ether_addr_copy(fs->h_u.ether_spec.h_dest,
5046                                 rule->tuples.dst_mac);
5047                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
5048                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
5049                 else
5050                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
5051                                         rule->tuples_mask.dst_mac);
5052
5053                 fs->h_u.ether_spec.h_proto =
5054                                 cpu_to_be16(rule->tuples.ether_proto);
5055                 fs->m_u.ether_spec.h_proto =
5056                                 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
5057                                 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
5058
5059                 break;
5060         default:
5061                 return -EOPNOTSUPP;
5062         }
5063
5064         if (fs->flow_type & FLOW_EXT) {
5065                 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
5066                 fs->m_ext.vlan_tci =
5067                                 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
5068                                 cpu_to_be16(VLAN_VID_MASK) :
5069                                 cpu_to_be16(rule->tuples_mask.vlan_tag1);
5070         }
5071
5072         if (fs->flow_type & FLOW_MAC_EXT) {
5073                 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
5074                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
5075                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
5076                 else
5077                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
5078                                         rule->tuples_mask.dst_mac);
5079         }
5080
5081         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
5082                 fs->ring_cookie = RX_CLS_FLOW_DISC;
5083         } else {
5084                 u64 vf_id;
5085
5086                 fs->ring_cookie = rule->queue_id;
5087                 vf_id = rule->vf_id;
5088                 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
5089                 fs->ring_cookie |= vf_id;
5090         }
5091
5092         return 0;
5093 }
5094
5095 static int hclge_get_all_rules(struct hnae3_handle *handle,
5096                                struct ethtool_rxnfc *cmd, u32 *rule_locs)
5097 {
5098         struct hclge_vport *vport = hclge_get_vport(handle);
5099         struct hclge_dev *hdev = vport->back;
5100         struct hclge_fd_rule *rule;
5101         struct hlist_node *node2;
5102         int cnt = 0;
5103
5104         if (!hnae3_dev_fd_supported(hdev))
5105                 return -EOPNOTSUPP;
5106
5107         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
5108
5109         hlist_for_each_entry_safe(rule, node2,
5110                                   &hdev->fd_rule_list, rule_node) {
5111                 if (cnt == cmd->rule_cnt)
5112                         return -EMSGSIZE;
5113
5114                 rule_locs[cnt] = rule->location;
5115                 cnt++;
5116         }
5117
5118         cmd->rule_cnt = cnt;
5119
5120         return 0;
5121 }
5122
5123 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
5124 {
5125         struct hclge_vport *vport = hclge_get_vport(handle);
5126         struct hclge_dev *hdev = vport->back;
5127
5128         return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
5129                hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
5130 }
5131
5132 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
5133 {
5134         struct hclge_vport *vport = hclge_get_vport(handle);
5135         struct hclge_dev *hdev = vport->back;
5136
5137         return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5138 }
5139
5140 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
5141 {
5142         struct hclge_vport *vport = hclge_get_vport(handle);
5143         struct hclge_dev *hdev = vport->back;
5144
5145         return hdev->reset_count;
5146 }
5147
5148 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
5149 {
5150         struct hclge_vport *vport = hclge_get_vport(handle);
5151         struct hclge_dev *hdev = vport->back;
5152
5153         hdev->fd_cfg.fd_en = enable;
5154         if (!enable)
5155                 hclge_del_all_fd_entries(handle, false);
5156         else
5157                 hclge_restore_fd_entries(handle);
5158 }
5159
5160 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
5161 {
5162         struct hclge_desc desc;
5163         struct hclge_config_mac_mode_cmd *req =
5164                 (struct hclge_config_mac_mode_cmd *)desc.data;
5165         u32 loop_en = 0;
5166         int ret;
5167
5168         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
5169         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
5170         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
5171         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
5172         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
5173         hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
5174         hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
5175         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
5176         hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
5177         hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
5178         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
5179         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
5180         hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
5181         hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
5182         hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
5183         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
5184
5185         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5186         if (ret)
5187                 dev_err(&hdev->pdev->dev,
5188                         "mac enable fail, ret =%d.\n", ret);
5189 }
5190
5191 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
5192 {
5193         struct hclge_config_mac_mode_cmd *req;
5194         struct hclge_desc desc;
5195         u32 loop_en;
5196         int ret;
5197
5198         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
5199         /* 1 Read out the MAC mode config at first */
5200         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
5201         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5202         if (ret) {
5203                 dev_err(&hdev->pdev->dev,
5204                         "mac loopback get fail, ret =%d.\n", ret);
5205                 return ret;
5206         }
5207
5208         /* 2 Then setup the loopback flag */
5209         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
5210         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
5211         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
5212         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
5213
5214         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
5215
5216         /* 3 Config mac work mode with loopback flag
5217          * and its original configure parameters
5218          */
5219         hclge_cmd_reuse_desc(&desc, false);
5220         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5221         if (ret)
5222                 dev_err(&hdev->pdev->dev,
5223                         "mac loopback set fail, ret =%d.\n", ret);
5224         return ret;
5225 }
5226
5227 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
5228                                      enum hnae3_loop loop_mode)
5229 {
5230 #define HCLGE_SERDES_RETRY_MS   10
5231 #define HCLGE_SERDES_RETRY_NUM  100
5232         struct hclge_serdes_lb_cmd *req;
5233         struct hclge_desc desc;
5234         int ret, i = 0;
5235         u8 loop_mode_b;
5236
5237         req = (struct hclge_serdes_lb_cmd *)desc.data;
5238         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
5239
5240         switch (loop_mode) {
5241         case HNAE3_LOOP_SERIAL_SERDES:
5242                 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
5243                 break;
5244         case HNAE3_LOOP_PARALLEL_SERDES:
5245                 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
5246                 break;
5247         default:
5248                 dev_err(&hdev->pdev->dev,
5249                         "unsupported serdes loopback mode %d\n", loop_mode);
5250                 return -ENOTSUPP;
5251         }
5252
5253         if (en) {
5254                 req->enable = loop_mode_b;
5255                 req->mask = loop_mode_b;
5256         } else {
5257                 req->mask = loop_mode_b;
5258         }
5259
5260         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5261         if (ret) {
5262                 dev_err(&hdev->pdev->dev,
5263                         "serdes loopback set fail, ret = %d\n", ret);
5264                 return ret;
5265         }
5266
5267         do {
5268                 msleep(HCLGE_SERDES_RETRY_MS);
5269                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
5270                                            true);
5271                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5272                 if (ret) {
5273                         dev_err(&hdev->pdev->dev,
5274                                 "serdes loopback get, ret = %d\n", ret);
5275                         return ret;
5276                 }
5277         } while (++i < HCLGE_SERDES_RETRY_NUM &&
5278                  !(req->result & HCLGE_CMD_SERDES_DONE_B));
5279
5280         if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
5281                 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
5282                 return -EBUSY;
5283         } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
5284                 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
5285                 return -EIO;
5286         }
5287
5288         hclge_cfg_mac_mode(hdev, en);
5289         return 0;
5290 }
5291
5292 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
5293                             int stream_id, bool enable)
5294 {
5295         struct hclge_desc desc;
5296         struct hclge_cfg_com_tqp_queue_cmd *req =
5297                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
5298         int ret;
5299
5300         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
5301         req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
5302         req->stream_id = cpu_to_le16(stream_id);
5303         req->enable |= enable << HCLGE_TQP_ENABLE_B;
5304
5305         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5306         if (ret)
5307                 dev_err(&hdev->pdev->dev,
5308                         "Tqp enable fail, status =%d.\n", ret);
5309         return ret;
5310 }
5311
5312 static int hclge_set_loopback(struct hnae3_handle *handle,
5313                               enum hnae3_loop loop_mode, bool en)
5314 {
5315         struct hclge_vport *vport = hclge_get_vport(handle);
5316         struct hnae3_knic_private_info *kinfo;
5317         struct hclge_dev *hdev = vport->back;
5318         int i, ret;
5319
5320         switch (loop_mode) {
5321         case HNAE3_LOOP_APP:
5322                 ret = hclge_set_app_loopback(hdev, en);
5323                 break;
5324         case HNAE3_LOOP_SERIAL_SERDES:
5325         case HNAE3_LOOP_PARALLEL_SERDES:
5326                 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
5327                 break;
5328         default:
5329                 ret = -ENOTSUPP;
5330                 dev_err(&hdev->pdev->dev,
5331                         "loop_mode %d is not supported\n", loop_mode);
5332                 break;
5333         }
5334
5335         if (ret)
5336                 return ret;
5337
5338         kinfo = &vport->nic.kinfo;
5339         for (i = 0; i < kinfo->num_tqps; i++) {
5340                 ret = hclge_tqp_enable(hdev, i, 0, en);
5341                 if (ret)
5342                         return ret;
5343         }
5344
5345         return 0;
5346 }
5347
5348 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
5349 {
5350         struct hclge_vport *vport = hclge_get_vport(handle);
5351         struct hnae3_knic_private_info *kinfo;
5352         struct hnae3_queue *queue;
5353         struct hclge_tqp *tqp;
5354         int i;
5355
5356         kinfo = &vport->nic.kinfo;
5357         for (i = 0; i < kinfo->num_tqps; i++) {
5358                 queue = handle->kinfo.tqp[i];
5359                 tqp = container_of(queue, struct hclge_tqp, q);
5360                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
5361         }
5362 }
5363
5364 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable)
5365 {
5366         struct hclge_vport *vport = hclge_get_vport(handle);
5367         struct hclge_dev *hdev = vport->back;
5368
5369         if (enable) {
5370                 mod_timer(&hdev->service_timer, jiffies + HZ);
5371         } else {
5372                 del_timer_sync(&hdev->service_timer);
5373                 cancel_work_sync(&hdev->service_task);
5374                 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
5375         }
5376 }
5377
5378 static int hclge_ae_start(struct hnae3_handle *handle)
5379 {
5380         struct hclge_vport *vport = hclge_get_vport(handle);
5381         struct hclge_dev *hdev = vport->back;
5382
5383         /* mac enable */
5384         hclge_cfg_mac_mode(hdev, true);
5385         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
5386         hdev->hw.mac.link = 0;
5387
5388         /* reset tqp stats */
5389         hclge_reset_tqp_stats(handle);
5390
5391         hclge_mac_start_phy(hdev);
5392
5393         return 0;
5394 }
5395
5396 static void hclge_ae_stop(struct hnae3_handle *handle)
5397 {
5398         struct hclge_vport *vport = hclge_get_vport(handle);
5399         struct hclge_dev *hdev = vport->back;
5400         int i;
5401
5402         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5403
5404         /* If it is not PF reset, the firmware will disable the MAC,
5405          * so it only need to stop phy here.
5406          */
5407         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
5408             hdev->reset_type != HNAE3_FUNC_RESET) {
5409                 hclge_mac_stop_phy(hdev);
5410                 return;
5411         }
5412
5413         for (i = 0; i < handle->kinfo.num_tqps; i++)
5414                 hclge_reset_tqp(handle, i);
5415
5416         /* Mac disable */
5417         hclge_cfg_mac_mode(hdev, false);
5418
5419         hclge_mac_stop_phy(hdev);
5420
5421         /* reset tqp stats */
5422         hclge_reset_tqp_stats(handle);
5423         hclge_update_link_status(hdev);
5424 }
5425
5426 int hclge_vport_start(struct hclge_vport *vport)
5427 {
5428         set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
5429         vport->last_active_jiffies = jiffies;
5430         return 0;
5431 }
5432
5433 void hclge_vport_stop(struct hclge_vport *vport)
5434 {
5435         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
5436 }
5437
5438 static int hclge_client_start(struct hnae3_handle *handle)
5439 {
5440         struct hclge_vport *vport = hclge_get_vport(handle);
5441
5442         return hclge_vport_start(vport);
5443 }
5444
5445 static void hclge_client_stop(struct hnae3_handle *handle)
5446 {
5447         struct hclge_vport *vport = hclge_get_vport(handle);
5448
5449         hclge_vport_stop(vport);
5450 }
5451
5452 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
5453                                          u16 cmdq_resp, u8  resp_code,
5454                                          enum hclge_mac_vlan_tbl_opcode op)
5455 {
5456         struct hclge_dev *hdev = vport->back;
5457         int return_status = -EIO;
5458
5459         if (cmdq_resp) {
5460                 dev_err(&hdev->pdev->dev,
5461                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
5462                         cmdq_resp);
5463                 return -EIO;
5464         }
5465
5466         if (op == HCLGE_MAC_VLAN_ADD) {
5467                 if ((!resp_code) || (resp_code == 1)) {
5468                         return_status = 0;
5469                 } else if (resp_code == 2) {
5470                         return_status = -ENOSPC;
5471                         dev_err(&hdev->pdev->dev,
5472                                 "add mac addr failed for uc_overflow.\n");
5473                 } else if (resp_code == 3) {
5474                         return_status = -ENOSPC;
5475                         dev_err(&hdev->pdev->dev,
5476                                 "add mac addr failed for mc_overflow.\n");
5477                 } else {
5478                         dev_err(&hdev->pdev->dev,
5479                                 "add mac addr failed for undefined, code=%d.\n",
5480                                 resp_code);
5481                 }
5482         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
5483                 if (!resp_code) {
5484                         return_status = 0;
5485                 } else if (resp_code == 1) {
5486                         return_status = -ENOENT;
5487                         dev_dbg(&hdev->pdev->dev,
5488                                 "remove mac addr failed for miss.\n");
5489                 } else {
5490                         dev_err(&hdev->pdev->dev,
5491                                 "remove mac addr failed for undefined, code=%d.\n",
5492                                 resp_code);
5493                 }
5494         } else if (op == HCLGE_MAC_VLAN_LKUP) {
5495                 if (!resp_code) {
5496                         return_status = 0;
5497                 } else if (resp_code == 1) {
5498                         return_status = -ENOENT;
5499                         dev_dbg(&hdev->pdev->dev,
5500                                 "lookup mac addr failed for miss.\n");
5501                 } else {
5502                         dev_err(&hdev->pdev->dev,
5503                                 "lookup mac addr failed for undefined, code=%d.\n",
5504                                 resp_code);
5505                 }
5506         } else {
5507                 return_status = -EINVAL;
5508                 dev_err(&hdev->pdev->dev,
5509                         "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
5510                         op);
5511         }
5512
5513         return return_status;
5514 }
5515
5516 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
5517 {
5518         int word_num;
5519         int bit_num;
5520
5521         if (vfid > 255 || vfid < 0)
5522                 return -EIO;
5523
5524         if (vfid >= 0 && vfid <= 191) {
5525                 word_num = vfid / 32;
5526                 bit_num  = vfid % 32;
5527                 if (clr)
5528                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
5529                 else
5530                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
5531         } else {
5532                 word_num = (vfid - 192) / 32;
5533                 bit_num  = vfid % 32;
5534                 if (clr)
5535                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
5536                 else
5537                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
5538         }
5539
5540         return 0;
5541 }
5542
5543 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
5544 {
5545 #define HCLGE_DESC_NUMBER 3
5546 #define HCLGE_FUNC_NUMBER_PER_DESC 6
5547         int i, j;
5548
5549         for (i = 1; i < HCLGE_DESC_NUMBER; i++)
5550                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
5551                         if (desc[i].data[j])
5552                                 return false;
5553
5554         return true;
5555 }
5556
5557 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
5558                                    const u8 *addr)
5559 {
5560         const unsigned char *mac_addr = addr;
5561         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
5562                        (mac_addr[0]) | (mac_addr[1] << 8);
5563         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
5564
5565         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
5566         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
5567 }
5568
5569 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
5570                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
5571 {
5572         struct hclge_dev *hdev = vport->back;
5573         struct hclge_desc desc;
5574         u8 resp_code;
5575         u16 retval;
5576         int ret;
5577
5578         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
5579
5580         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5581
5582         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5583         if (ret) {
5584                 dev_err(&hdev->pdev->dev,
5585                         "del mac addr failed for cmd_send, ret =%d.\n",
5586                         ret);
5587                 return ret;
5588         }
5589         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5590         retval = le16_to_cpu(desc.retval);
5591
5592         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
5593                                              HCLGE_MAC_VLAN_REMOVE);
5594 }
5595
5596 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
5597                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
5598                                      struct hclge_desc *desc,
5599                                      bool is_mc)
5600 {
5601         struct hclge_dev *hdev = vport->back;
5602         u8 resp_code;
5603         u16 retval;
5604         int ret;
5605
5606         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
5607         if (is_mc) {
5608                 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5609                 memcpy(desc[0].data,
5610                        req,
5611                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5612                 hclge_cmd_setup_basic_desc(&desc[1],
5613                                            HCLGE_OPC_MAC_VLAN_ADD,
5614                                            true);
5615                 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5616                 hclge_cmd_setup_basic_desc(&desc[2],
5617                                            HCLGE_OPC_MAC_VLAN_ADD,
5618                                            true);
5619                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5620         } else {
5621                 memcpy(desc[0].data,
5622                        req,
5623                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5624                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
5625         }
5626         if (ret) {
5627                 dev_err(&hdev->pdev->dev,
5628                         "lookup mac addr failed for cmd_send, ret =%d.\n",
5629                         ret);
5630                 return ret;
5631         }
5632         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
5633         retval = le16_to_cpu(desc[0].retval);
5634
5635         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
5636                                              HCLGE_MAC_VLAN_LKUP);
5637 }
5638
5639 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
5640                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
5641                                   struct hclge_desc *mc_desc)
5642 {
5643         struct hclge_dev *hdev = vport->back;
5644         int cfg_status;
5645         u8 resp_code;
5646         u16 retval;
5647         int ret;
5648
5649         if (!mc_desc) {
5650                 struct hclge_desc desc;
5651
5652                 hclge_cmd_setup_basic_desc(&desc,
5653                                            HCLGE_OPC_MAC_VLAN_ADD,
5654                                            false);
5655                 memcpy(desc.data, req,
5656                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5657                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5658                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5659                 retval = le16_to_cpu(desc.retval);
5660
5661                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
5662                                                            resp_code,
5663                                                            HCLGE_MAC_VLAN_ADD);
5664         } else {
5665                 hclge_cmd_reuse_desc(&mc_desc[0], false);
5666                 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5667                 hclge_cmd_reuse_desc(&mc_desc[1], false);
5668                 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5669                 hclge_cmd_reuse_desc(&mc_desc[2], false);
5670                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
5671                 memcpy(mc_desc[0].data, req,
5672                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5673                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
5674                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
5675                 retval = le16_to_cpu(mc_desc[0].retval);
5676
5677                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
5678                                                            resp_code,
5679                                                            HCLGE_MAC_VLAN_ADD);
5680         }
5681
5682         if (ret) {
5683                 dev_err(&hdev->pdev->dev,
5684                         "add mac addr failed for cmd_send, ret =%d.\n",
5685                         ret);
5686                 return ret;
5687         }
5688
5689         return cfg_status;
5690 }
5691
5692 static int hclge_init_umv_space(struct hclge_dev *hdev)
5693 {
5694         u16 allocated_size = 0;
5695         int ret;
5696
5697         ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5698                                   true);
5699         if (ret)
5700                 return ret;
5701
5702         if (allocated_size < hdev->wanted_umv_size)
5703                 dev_warn(&hdev->pdev->dev,
5704                          "Alloc umv space failed, want %d, get %d\n",
5705                          hdev->wanted_umv_size, allocated_size);
5706
5707         mutex_init(&hdev->umv_mutex);
5708         hdev->max_umv_size = allocated_size;
5709         hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5710         hdev->share_umv_size = hdev->priv_umv_size +
5711                         hdev->max_umv_size % (hdev->num_req_vfs + 2);
5712
5713         return 0;
5714 }
5715
5716 static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5717 {
5718         int ret;
5719
5720         if (hdev->max_umv_size > 0) {
5721                 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5722                                           false);
5723                 if (ret)
5724                         return ret;
5725                 hdev->max_umv_size = 0;
5726         }
5727         mutex_destroy(&hdev->umv_mutex);
5728
5729         return 0;
5730 }
5731
5732 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5733                                u16 *allocated_size, bool is_alloc)
5734 {
5735         struct hclge_umv_spc_alc_cmd *req;
5736         struct hclge_desc desc;
5737         int ret;
5738
5739         req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5740         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5741         hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5742         req->space_size = cpu_to_le32(space_size);
5743
5744         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5745         if (ret) {
5746                 dev_err(&hdev->pdev->dev,
5747                         "%s umv space failed for cmd_send, ret =%d\n",
5748                         is_alloc ? "allocate" : "free", ret);
5749                 return ret;
5750         }
5751
5752         if (is_alloc && allocated_size)
5753                 *allocated_size = le32_to_cpu(desc.data[1]);
5754
5755         return 0;
5756 }
5757
5758 static void hclge_reset_umv_space(struct hclge_dev *hdev)
5759 {
5760         struct hclge_vport *vport;
5761         int i;
5762
5763         for (i = 0; i < hdev->num_alloc_vport; i++) {
5764                 vport = &hdev->vport[i];
5765                 vport->used_umv_num = 0;
5766         }
5767
5768         mutex_lock(&hdev->umv_mutex);
5769         hdev->share_umv_size = hdev->priv_umv_size +
5770                         hdev->max_umv_size % (hdev->num_req_vfs + 2);
5771         mutex_unlock(&hdev->umv_mutex);
5772 }
5773
5774 static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5775 {
5776         struct hclge_dev *hdev = vport->back;
5777         bool is_full;
5778
5779         mutex_lock(&hdev->umv_mutex);
5780         is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5781                    hdev->share_umv_size == 0);
5782         mutex_unlock(&hdev->umv_mutex);
5783
5784         return is_full;
5785 }
5786
5787 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5788 {
5789         struct hclge_dev *hdev = vport->back;
5790
5791         mutex_lock(&hdev->umv_mutex);
5792         if (is_free) {
5793                 if (vport->used_umv_num > hdev->priv_umv_size)
5794                         hdev->share_umv_size++;
5795                 vport->used_umv_num--;
5796         } else {
5797                 if (vport->used_umv_num >= hdev->priv_umv_size)
5798                         hdev->share_umv_size--;
5799                 vport->used_umv_num++;
5800         }
5801         mutex_unlock(&hdev->umv_mutex);
5802 }
5803
5804 static int hclge_add_uc_addr(struct hnae3_handle *handle,
5805                              const unsigned char *addr)
5806 {
5807         struct hclge_vport *vport = hclge_get_vport(handle);
5808
5809         return hclge_add_uc_addr_common(vport, addr);
5810 }
5811
5812 int hclge_add_uc_addr_common(struct hclge_vport *vport,
5813                              const unsigned char *addr)
5814 {
5815         struct hclge_dev *hdev = vport->back;
5816         struct hclge_mac_vlan_tbl_entry_cmd req;
5817         struct hclge_desc desc;
5818         u16 egress_port = 0;
5819         int ret;
5820
5821         /* mac addr check */
5822         if (is_zero_ether_addr(addr) ||
5823             is_broadcast_ether_addr(addr) ||
5824             is_multicast_ether_addr(addr)) {
5825                 dev_err(&hdev->pdev->dev,
5826                         "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
5827                          addr,
5828                          is_zero_ether_addr(addr),
5829                          is_broadcast_ether_addr(addr),
5830                          is_multicast_ether_addr(addr));
5831                 return -EINVAL;
5832         }
5833
5834         memset(&req, 0, sizeof(req));
5835         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5836
5837         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
5838                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
5839
5840         req.egress_port = cpu_to_le16(egress_port);
5841
5842         hclge_prepare_mac_addr(&req, addr);
5843
5844         /* Lookup the mac address in the mac_vlan table, and add
5845          * it if the entry is inexistent. Repeated unicast entry
5846          * is not allowed in the mac vlan table.
5847          */
5848         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
5849         if (ret == -ENOENT) {
5850                 if (!hclge_is_umv_space_full(vport)) {
5851                         ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5852                         if (!ret)
5853                                 hclge_update_umv_space(vport, false);
5854                         return ret;
5855                 }
5856
5857                 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5858                         hdev->priv_umv_size);
5859
5860                 return -ENOSPC;
5861         }
5862
5863         /* check if we just hit the duplicate */
5864         if (!ret)
5865                 ret = -EINVAL;
5866
5867         dev_err(&hdev->pdev->dev,
5868                 "PF failed to add unicast entry(%pM) in the MAC table\n",
5869                 addr);
5870
5871         return ret;
5872 }
5873
5874 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
5875                             const unsigned char *addr)
5876 {
5877         struct hclge_vport *vport = hclge_get_vport(handle);
5878
5879         return hclge_rm_uc_addr_common(vport, addr);
5880 }
5881
5882 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
5883                             const unsigned char *addr)
5884 {
5885         struct hclge_dev *hdev = vport->back;
5886         struct hclge_mac_vlan_tbl_entry_cmd req;
5887         int ret;
5888
5889         /* mac addr check */
5890         if (is_zero_ether_addr(addr) ||
5891             is_broadcast_ether_addr(addr) ||
5892             is_multicast_ether_addr(addr)) {
5893                 dev_dbg(&hdev->pdev->dev,
5894                         "Remove mac err! invalid mac:%pM.\n",
5895                          addr);
5896                 return -EINVAL;
5897         }
5898
5899         memset(&req, 0, sizeof(req));
5900         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5901         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5902         hclge_prepare_mac_addr(&req, addr);
5903         ret = hclge_remove_mac_vlan_tbl(vport, &req);
5904         if (!ret)
5905                 hclge_update_umv_space(vport, true);
5906
5907         return ret;
5908 }
5909
5910 static int hclge_add_mc_addr(struct hnae3_handle *handle,
5911                              const unsigned char *addr)
5912 {
5913         struct hclge_vport *vport = hclge_get_vport(handle);
5914
5915         return hclge_add_mc_addr_common(vport, addr);
5916 }
5917
5918 int hclge_add_mc_addr_common(struct hclge_vport *vport,
5919                              const unsigned char *addr)
5920 {
5921         struct hclge_dev *hdev = vport->back;
5922         struct hclge_mac_vlan_tbl_entry_cmd req;
5923         struct hclge_desc desc[3];
5924         int status;
5925
5926         /* mac addr check */
5927         if (!is_multicast_ether_addr(addr)) {
5928                 dev_err(&hdev->pdev->dev,
5929                         "Add mc mac err! invalid mac:%pM.\n",
5930                          addr);
5931                 return -EINVAL;
5932         }
5933         memset(&req, 0, sizeof(req));
5934         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5935         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5936         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
5937         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5938         hclge_prepare_mac_addr(&req, addr);
5939         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5940         if (!status) {
5941                 /* This mac addr exist, update VFID for it */
5942                 hclge_update_desc_vfid(desc, vport->vport_id, false);
5943                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5944         } else {
5945                 /* This mac addr do not exist, add new entry for it */
5946                 memset(desc[0].data, 0, sizeof(desc[0].data));
5947                 memset(desc[1].data, 0, sizeof(desc[0].data));
5948                 memset(desc[2].data, 0, sizeof(desc[0].data));
5949                 hclge_update_desc_vfid(desc, vport->vport_id, false);
5950                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5951         }
5952
5953         if (status == -ENOSPC)
5954                 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
5955
5956         return status;
5957 }
5958
5959 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
5960                             const unsigned char *addr)
5961 {
5962         struct hclge_vport *vport = hclge_get_vport(handle);
5963
5964         return hclge_rm_mc_addr_common(vport, addr);
5965 }
5966
5967 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
5968                             const unsigned char *addr)
5969 {
5970         struct hclge_dev *hdev = vport->back;
5971         struct hclge_mac_vlan_tbl_entry_cmd req;
5972         enum hclge_cmd_status status;
5973         struct hclge_desc desc[3];
5974
5975         /* mac addr check */
5976         if (!is_multicast_ether_addr(addr)) {
5977                 dev_dbg(&hdev->pdev->dev,
5978                         "Remove mc mac err! invalid mac:%pM.\n",
5979                          addr);
5980                 return -EINVAL;
5981         }
5982
5983         memset(&req, 0, sizeof(req));
5984         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5985         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5986         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
5987         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5988         hclge_prepare_mac_addr(&req, addr);
5989         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5990         if (!status) {
5991                 /* This mac addr exist, remove this handle's VFID for it */
5992                 hclge_update_desc_vfid(desc, vport->vport_id, true);
5993
5994                 if (hclge_is_all_function_id_zero(desc))
5995                         /* All the vfid is zero, so need to delete this entry */
5996                         status = hclge_remove_mac_vlan_tbl(vport, &req);
5997                 else
5998                         /* Not all the vfid is zero, update the vfid */
5999                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
6000
6001         } else {
6002                 /* Maybe this mac address is in mta table, but it cannot be
6003                  * deleted here because an entry of mta represents an address
6004                  * range rather than a specific address. the delete action to
6005                  * all entries will take effect in update_mta_status called by
6006                  * hns3_nic_set_rx_mode.
6007                  */
6008                 status = 0;
6009         }
6010
6011         return status;
6012 }
6013
6014 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
6015                                               u16 cmdq_resp, u8 resp_code)
6016 {
6017 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
6018 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
6019 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
6020 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
6021
6022         int return_status;
6023
6024         if (cmdq_resp) {
6025                 dev_err(&hdev->pdev->dev,
6026                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
6027                         cmdq_resp);
6028                 return -EIO;
6029         }
6030
6031         switch (resp_code) {
6032         case HCLGE_ETHERTYPE_SUCCESS_ADD:
6033         case HCLGE_ETHERTYPE_ALREADY_ADD:
6034                 return_status = 0;
6035                 break;
6036         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
6037                 dev_err(&hdev->pdev->dev,
6038                         "add mac ethertype failed for manager table overflow.\n");
6039                 return_status = -EIO;
6040                 break;
6041         case HCLGE_ETHERTYPE_KEY_CONFLICT:
6042                 dev_err(&hdev->pdev->dev,
6043                         "add mac ethertype failed for key conflict.\n");
6044                 return_status = -EIO;
6045                 break;
6046         default:
6047                 dev_err(&hdev->pdev->dev,
6048                         "add mac ethertype failed for undefined, code=%d.\n",
6049                         resp_code);
6050                 return_status = -EIO;
6051         }
6052
6053         return return_status;
6054 }
6055
6056 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
6057                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
6058 {
6059         struct hclge_desc desc;
6060         u8 resp_code;
6061         u16 retval;
6062         int ret;
6063
6064         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
6065         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
6066
6067         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6068         if (ret) {
6069                 dev_err(&hdev->pdev->dev,
6070                         "add mac ethertype failed for cmd_send, ret =%d.\n",
6071                         ret);
6072                 return ret;
6073         }
6074
6075         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
6076         retval = le16_to_cpu(desc.retval);
6077
6078         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
6079 }
6080
6081 static int init_mgr_tbl(struct hclge_dev *hdev)
6082 {
6083         int ret;
6084         int i;
6085
6086         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
6087                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
6088                 if (ret) {
6089                         dev_err(&hdev->pdev->dev,
6090                                 "add mac ethertype failed, ret =%d.\n",
6091                                 ret);
6092                         return ret;
6093                 }
6094         }
6095
6096         return 0;
6097 }
6098
6099 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
6100 {
6101         struct hclge_vport *vport = hclge_get_vport(handle);
6102         struct hclge_dev *hdev = vport->back;
6103
6104         ether_addr_copy(p, hdev->hw.mac.mac_addr);
6105 }
6106
6107 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
6108                               bool is_first)
6109 {
6110         const unsigned char *new_addr = (const unsigned char *)p;
6111         struct hclge_vport *vport = hclge_get_vport(handle);
6112         struct hclge_dev *hdev = vport->back;
6113         int ret;
6114
6115         /* mac addr check */
6116         if (is_zero_ether_addr(new_addr) ||
6117             is_broadcast_ether_addr(new_addr) ||
6118             is_multicast_ether_addr(new_addr)) {
6119                 dev_err(&hdev->pdev->dev,
6120                         "Change uc mac err! invalid mac:%p.\n",
6121                          new_addr);
6122                 return -EINVAL;
6123         }
6124
6125         if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
6126                 dev_warn(&hdev->pdev->dev,
6127                          "remove old uc mac address fail.\n");
6128
6129         ret = hclge_add_uc_addr(handle, new_addr);
6130         if (ret) {
6131                 dev_err(&hdev->pdev->dev,
6132                         "add uc mac address fail, ret =%d.\n",
6133                         ret);
6134
6135                 if (!is_first &&
6136                     hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
6137                         dev_err(&hdev->pdev->dev,
6138                                 "restore uc mac address fail.\n");
6139
6140                 return -EIO;
6141         }
6142
6143         ret = hclge_pause_addr_cfg(hdev, new_addr);
6144         if (ret) {
6145                 dev_err(&hdev->pdev->dev,
6146                         "configure mac pause address fail, ret =%d.\n",
6147                         ret);
6148                 return -EIO;
6149         }
6150
6151         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
6152
6153         return 0;
6154 }
6155
6156 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
6157                           int cmd)
6158 {
6159         struct hclge_vport *vport = hclge_get_vport(handle);
6160         struct hclge_dev *hdev = vport->back;
6161
6162         if (!hdev->hw.mac.phydev)
6163                 return -EOPNOTSUPP;
6164
6165         return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
6166 }
6167
6168 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
6169                                       u8 fe_type, bool filter_en)
6170 {
6171         struct hclge_vlan_filter_ctrl_cmd *req;
6172         struct hclge_desc desc;
6173         int ret;
6174
6175         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
6176
6177         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
6178         req->vlan_type = vlan_type;
6179         req->vlan_fe = filter_en ? fe_type : 0;
6180
6181         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6182         if (ret)
6183                 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
6184                         ret);
6185
6186         return ret;
6187 }
6188
6189 #define HCLGE_FILTER_TYPE_VF            0
6190 #define HCLGE_FILTER_TYPE_PORT          1
6191 #define HCLGE_FILTER_FE_EGRESS_V1_B     BIT(0)
6192 #define HCLGE_FILTER_FE_NIC_INGRESS_B   BIT(0)
6193 #define HCLGE_FILTER_FE_NIC_EGRESS_B    BIT(1)
6194 #define HCLGE_FILTER_FE_ROCE_INGRESS_B  BIT(2)
6195 #define HCLGE_FILTER_FE_ROCE_EGRESS_B   BIT(3)
6196 #define HCLGE_FILTER_FE_EGRESS          (HCLGE_FILTER_FE_NIC_EGRESS_B \
6197                                         | HCLGE_FILTER_FE_ROCE_EGRESS_B)
6198 #define HCLGE_FILTER_FE_INGRESS         (HCLGE_FILTER_FE_NIC_INGRESS_B \
6199                                         | HCLGE_FILTER_FE_ROCE_INGRESS_B)
6200
6201 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
6202 {
6203         struct hclge_vport *vport = hclge_get_vport(handle);
6204         struct hclge_dev *hdev = vport->back;
6205
6206         if (hdev->pdev->revision >= 0x21) {
6207                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6208                                            HCLGE_FILTER_FE_EGRESS, enable);
6209                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6210                                            HCLGE_FILTER_FE_INGRESS, enable);
6211         } else {
6212                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6213                                            HCLGE_FILTER_FE_EGRESS_V1_B, enable);
6214         }
6215         if (enable)
6216                 handle->netdev_flags |= HNAE3_VLAN_FLTR;
6217         else
6218                 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
6219 }
6220
6221 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
6222                                     bool is_kill, u16 vlan, u8 qos,
6223                                     __be16 proto)
6224 {
6225 #define HCLGE_MAX_VF_BYTES  16
6226         struct hclge_vlan_filter_vf_cfg_cmd *req0;
6227         struct hclge_vlan_filter_vf_cfg_cmd *req1;
6228         struct hclge_desc desc[2];
6229         u8 vf_byte_val;
6230         u8 vf_byte_off;
6231         int ret;
6232
6233         hclge_cmd_setup_basic_desc(&desc[0],
6234                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
6235         hclge_cmd_setup_basic_desc(&desc[1],
6236                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
6237
6238         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
6239
6240         vf_byte_off = vfid / 8;
6241         vf_byte_val = 1 << (vfid % 8);
6242
6243         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
6244         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
6245
6246         req0->vlan_id  = cpu_to_le16(vlan);
6247         req0->vlan_cfg = is_kill;
6248
6249         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
6250                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
6251         else
6252                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
6253
6254         ret = hclge_cmd_send(&hdev->hw, desc, 2);
6255         if (ret) {
6256                 dev_err(&hdev->pdev->dev,
6257                         "Send vf vlan command fail, ret =%d.\n",
6258                         ret);
6259                 return ret;
6260         }
6261
6262         if (!is_kill) {
6263 #define HCLGE_VF_VLAN_NO_ENTRY  2
6264                 if (!req0->resp_code || req0->resp_code == 1)
6265                         return 0;
6266
6267                 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
6268                         dev_warn(&hdev->pdev->dev,
6269                                  "vf vlan table is full, vf vlan filter is disabled\n");
6270                         return 0;
6271                 }
6272
6273                 dev_err(&hdev->pdev->dev,
6274                         "Add vf vlan filter fail, ret =%d.\n",
6275                         req0->resp_code);
6276         } else {
6277 #define HCLGE_VF_VLAN_DEL_NO_FOUND      1
6278                 if (!req0->resp_code)
6279                         return 0;
6280
6281                 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
6282                         dev_warn(&hdev->pdev->dev,
6283                                  "vlan %d filter is not in vf vlan table\n",
6284                                  vlan);
6285                         return 0;
6286                 }
6287
6288                 dev_err(&hdev->pdev->dev,
6289                         "Kill vf vlan filter fail, ret =%d.\n",
6290                         req0->resp_code);
6291         }
6292
6293         return -EIO;
6294 }
6295
6296 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
6297                                       u16 vlan_id, bool is_kill)
6298 {
6299         struct hclge_vlan_filter_pf_cfg_cmd *req;
6300         struct hclge_desc desc;
6301         u8 vlan_offset_byte_val;
6302         u8 vlan_offset_byte;
6303         u8 vlan_offset_160;
6304         int ret;
6305
6306         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
6307
6308         vlan_offset_160 = vlan_id / 160;
6309         vlan_offset_byte = (vlan_id % 160) / 8;
6310         vlan_offset_byte_val = 1 << (vlan_id % 8);
6311
6312         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
6313         req->vlan_offset = vlan_offset_160;
6314         req->vlan_cfg = is_kill;
6315         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
6316
6317         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6318         if (ret)
6319                 dev_err(&hdev->pdev->dev,
6320                         "port vlan command, send fail, ret =%d.\n", ret);
6321         return ret;
6322 }
6323
6324 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
6325                                     u16 vport_id, u16 vlan_id, u8 qos,
6326                                     bool is_kill)
6327 {
6328         u16 vport_idx, vport_num = 0;
6329         int ret;
6330
6331         if (is_kill && !vlan_id)
6332                 return 0;
6333
6334         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
6335                                        0, proto);
6336         if (ret) {
6337                 dev_err(&hdev->pdev->dev,
6338                         "Set %d vport vlan filter config fail, ret =%d.\n",
6339                         vport_id, ret);
6340                 return ret;
6341         }
6342
6343         /* vlan 0 may be added twice when 8021q module is enabled */
6344         if (!is_kill && !vlan_id &&
6345             test_bit(vport_id, hdev->vlan_table[vlan_id]))
6346                 return 0;
6347
6348         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
6349                 dev_err(&hdev->pdev->dev,
6350                         "Add port vlan failed, vport %d is already in vlan %d\n",
6351                         vport_id, vlan_id);
6352                 return -EINVAL;
6353         }
6354
6355         if (is_kill &&
6356             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
6357                 dev_err(&hdev->pdev->dev,
6358                         "Delete port vlan failed, vport %d is not in vlan %d\n",
6359                         vport_id, vlan_id);
6360                 return -EINVAL;
6361         }
6362
6363         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
6364                 vport_num++;
6365
6366         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
6367                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
6368                                                  is_kill);
6369
6370         return ret;
6371 }
6372
6373 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
6374                           u16 vlan_id, bool is_kill)
6375 {
6376         struct hclge_vport *vport = hclge_get_vport(handle);
6377         struct hclge_dev *hdev = vport->back;
6378
6379         return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
6380                                         0, is_kill);
6381 }
6382
6383 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
6384                                     u16 vlan, u8 qos, __be16 proto)
6385 {
6386         struct hclge_vport *vport = hclge_get_vport(handle);
6387         struct hclge_dev *hdev = vport->back;
6388
6389         if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
6390                 return -EINVAL;
6391         if (proto != htons(ETH_P_8021Q))
6392                 return -EPROTONOSUPPORT;
6393
6394         return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
6395 }
6396
6397 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
6398 {
6399         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
6400         struct hclge_vport_vtag_tx_cfg_cmd *req;
6401         struct hclge_dev *hdev = vport->back;
6402         struct hclge_desc desc;
6403         int status;
6404
6405         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
6406
6407         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
6408         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
6409         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
6410         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
6411                       vcfg->accept_tag1 ? 1 : 0);
6412         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
6413                       vcfg->accept_untag1 ? 1 : 0);
6414         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
6415                       vcfg->accept_tag2 ? 1 : 0);
6416         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
6417                       vcfg->accept_untag2 ? 1 : 0);
6418         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
6419                       vcfg->insert_tag1_en ? 1 : 0);
6420         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
6421                       vcfg->insert_tag2_en ? 1 : 0);
6422         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
6423
6424         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6425         req->vf_bitmap[req->vf_offset] =
6426                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6427
6428         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6429         if (status)
6430                 dev_err(&hdev->pdev->dev,
6431                         "Send port txvlan cfg command fail, ret =%d\n",
6432                         status);
6433
6434         return status;
6435 }
6436
6437 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
6438 {
6439         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
6440         struct hclge_vport_vtag_rx_cfg_cmd *req;
6441         struct hclge_dev *hdev = vport->back;
6442         struct hclge_desc desc;
6443         int status;
6444
6445         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
6446
6447         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
6448         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
6449                       vcfg->strip_tag1_en ? 1 : 0);
6450         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
6451                       vcfg->strip_tag2_en ? 1 : 0);
6452         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
6453                       vcfg->vlan1_vlan_prionly ? 1 : 0);
6454         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
6455                       vcfg->vlan2_vlan_prionly ? 1 : 0);
6456
6457         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6458         req->vf_bitmap[req->vf_offset] =
6459                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6460
6461         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6462         if (status)
6463                 dev_err(&hdev->pdev->dev,
6464                         "Send port rxvlan cfg command fail, ret =%d\n",
6465                         status);
6466
6467         return status;
6468 }
6469
6470 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
6471 {
6472         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
6473         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
6474         struct hclge_desc desc;
6475         int status;
6476
6477         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
6478         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
6479         rx_req->ot_fst_vlan_type =
6480                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
6481         rx_req->ot_sec_vlan_type =
6482                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
6483         rx_req->in_fst_vlan_type =
6484                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
6485         rx_req->in_sec_vlan_type =
6486                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
6487
6488         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6489         if (status) {
6490                 dev_err(&hdev->pdev->dev,
6491                         "Send rxvlan protocol type command fail, ret =%d\n",
6492                         status);
6493                 return status;
6494         }
6495
6496         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
6497
6498         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
6499         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
6500         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
6501
6502         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6503         if (status)
6504                 dev_err(&hdev->pdev->dev,
6505                         "Send txvlan protocol type command fail, ret =%d\n",
6506                         status);
6507
6508         return status;
6509 }
6510
6511 static int hclge_init_vlan_config(struct hclge_dev *hdev)
6512 {
6513 #define HCLGE_DEF_VLAN_TYPE             0x8100
6514
6515         struct hnae3_handle *handle = &hdev->vport[0].nic;
6516         struct hclge_vport *vport;
6517         int ret;
6518         int i;
6519
6520         if (hdev->pdev->revision >= 0x21) {
6521                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6522                                                  HCLGE_FILTER_FE_EGRESS, true);
6523                 if (ret)
6524                         return ret;
6525
6526                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6527                                                  HCLGE_FILTER_FE_INGRESS, true);
6528                 if (ret)
6529                         return ret;
6530         } else {
6531                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6532                                                  HCLGE_FILTER_FE_EGRESS_V1_B,
6533                                                  true);
6534                 if (ret)
6535                         return ret;
6536         }
6537
6538         handle->netdev_flags |= HNAE3_VLAN_FLTR;
6539
6540         hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6541         hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6542         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6543         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6544         hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
6545         hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
6546
6547         ret = hclge_set_vlan_protocol_type(hdev);
6548         if (ret)
6549                 return ret;
6550
6551         for (i = 0; i < hdev->num_alloc_vport; i++) {
6552                 vport = &hdev->vport[i];
6553                 vport->txvlan_cfg.accept_tag1 = true;
6554                 vport->txvlan_cfg.accept_untag1 = true;
6555
6556                 /* accept_tag2 and accept_untag2 are not supported on
6557                  * pdev revision(0x20), new revision support them. The
6558                  * value of this two fields will not return error when driver
6559                  * send command to fireware in revision(0x20).
6560                  * This two fields can not configured by user.
6561                  */
6562                 vport->txvlan_cfg.accept_tag2 = true;
6563                 vport->txvlan_cfg.accept_untag2 = true;
6564
6565                 vport->txvlan_cfg.insert_tag1_en = false;
6566                 vport->txvlan_cfg.insert_tag2_en = false;
6567                 vport->txvlan_cfg.default_tag1 = 0;
6568                 vport->txvlan_cfg.default_tag2 = 0;
6569
6570                 ret = hclge_set_vlan_tx_offload_cfg(vport);
6571                 if (ret)
6572                         return ret;
6573
6574                 vport->rxvlan_cfg.strip_tag1_en = false;
6575                 vport->rxvlan_cfg.strip_tag2_en = true;
6576                 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6577                 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6578
6579                 ret = hclge_set_vlan_rx_offload_cfg(vport);
6580                 if (ret)
6581                         return ret;
6582         }
6583
6584         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
6585 }
6586
6587 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
6588 {
6589         struct hclge_vport *vport = hclge_get_vport(handle);
6590
6591         vport->rxvlan_cfg.strip_tag1_en = false;
6592         vport->rxvlan_cfg.strip_tag2_en = enable;
6593         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6594         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6595
6596         return hclge_set_vlan_rx_offload_cfg(vport);
6597 }
6598
6599 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps)
6600 {
6601         struct hclge_config_max_frm_size_cmd *req;
6602         struct hclge_desc desc;
6603
6604         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
6605
6606         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
6607         req->max_frm_size = cpu_to_le16(new_mps);
6608         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
6609
6610         return hclge_cmd_send(&hdev->hw, &desc, 1);
6611 }
6612
6613 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
6614 {
6615         struct hclge_vport *vport = hclge_get_vport(handle);
6616
6617         return hclge_set_vport_mtu(vport, new_mtu);
6618 }
6619
6620 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu)
6621 {
6622         struct hclge_dev *hdev = vport->back;
6623         int i, max_frm_size, ret = 0;
6624
6625         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
6626         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
6627             max_frm_size > HCLGE_MAC_MAX_FRAME)
6628                 return -EINVAL;
6629
6630         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
6631         mutex_lock(&hdev->vport_lock);
6632         /* VF's mps must fit within hdev->mps */
6633         if (vport->vport_id && max_frm_size > hdev->mps) {
6634                 mutex_unlock(&hdev->vport_lock);
6635                 return -EINVAL;
6636         } else if (vport->vport_id) {
6637                 vport->mps = max_frm_size;
6638                 mutex_unlock(&hdev->vport_lock);
6639                 return 0;
6640         }
6641
6642         /* PF's mps must be greater then VF's mps */
6643         for (i = 1; i < hdev->num_alloc_vport; i++)
6644                 if (max_frm_size < hdev->vport[i].mps) {
6645                         mutex_unlock(&hdev->vport_lock);
6646                         return -EINVAL;
6647                 }
6648
6649         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
6650
6651         ret = hclge_set_mac_mtu(hdev, max_frm_size);
6652         if (ret) {
6653                 dev_err(&hdev->pdev->dev,
6654                         "Change mtu fail, ret =%d\n", ret);
6655                 goto out;
6656         }
6657
6658         hdev->mps = max_frm_size;
6659         vport->mps = max_frm_size;
6660
6661         ret = hclge_buffer_alloc(hdev);
6662         if (ret)
6663                 dev_err(&hdev->pdev->dev,
6664                         "Allocate buffer fail, ret =%d\n", ret);
6665
6666 out:
6667         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
6668         mutex_unlock(&hdev->vport_lock);
6669         return ret;
6670 }
6671
6672 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
6673                                     bool enable)
6674 {
6675         struct hclge_reset_tqp_queue_cmd *req;
6676         struct hclge_desc desc;
6677         int ret;
6678
6679         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
6680
6681         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
6682         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6683         hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
6684
6685         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6686         if (ret) {
6687                 dev_err(&hdev->pdev->dev,
6688                         "Send tqp reset cmd error, status =%d\n", ret);
6689                 return ret;
6690         }
6691
6692         return 0;
6693 }
6694
6695 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
6696 {
6697         struct hclge_reset_tqp_queue_cmd *req;
6698         struct hclge_desc desc;
6699         int ret;
6700
6701         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
6702
6703         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
6704         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6705
6706         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6707         if (ret) {
6708                 dev_err(&hdev->pdev->dev,
6709                         "Get reset status error, status =%d\n", ret);
6710                 return ret;
6711         }
6712
6713         return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
6714 }
6715
6716 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
6717 {
6718         struct hnae3_queue *queue;
6719         struct hclge_tqp *tqp;
6720
6721         queue = handle->kinfo.tqp[queue_id];
6722         tqp = container_of(queue, struct hclge_tqp, q);
6723
6724         return tqp->index;
6725 }
6726
6727 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
6728 {
6729         struct hclge_vport *vport = hclge_get_vport(handle);
6730         struct hclge_dev *hdev = vport->back;
6731         int reset_try_times = 0;
6732         int reset_status;
6733         u16 queue_gid;
6734         int ret = 0;
6735
6736         queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
6737
6738         ret = hclge_tqp_enable(hdev, queue_id, 0, false);
6739         if (ret) {
6740                 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
6741                 return ret;
6742         }
6743
6744         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6745         if (ret) {
6746                 dev_err(&hdev->pdev->dev,
6747                         "Send reset tqp cmd fail, ret = %d\n", ret);
6748                 return ret;
6749         }
6750
6751         reset_try_times = 0;
6752         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6753                 /* Wait for tqp hw reset */
6754                 msleep(20);
6755                 reset_status = hclge_get_reset_status(hdev, queue_gid);
6756                 if (reset_status)
6757                         break;
6758         }
6759
6760         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6761                 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
6762                 return ret;
6763         }
6764
6765         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6766         if (ret)
6767                 dev_err(&hdev->pdev->dev,
6768                         "Deassert the soft reset fail, ret = %d\n", ret);
6769
6770         return ret;
6771 }
6772
6773 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
6774 {
6775         struct hclge_dev *hdev = vport->back;
6776         int reset_try_times = 0;
6777         int reset_status;
6778         u16 queue_gid;
6779         int ret;
6780
6781         queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
6782
6783         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6784         if (ret) {
6785                 dev_warn(&hdev->pdev->dev,
6786                          "Send reset tqp cmd fail, ret = %d\n", ret);
6787                 return;
6788         }
6789
6790         reset_try_times = 0;
6791         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6792                 /* Wait for tqp hw reset */
6793                 msleep(20);
6794                 reset_status = hclge_get_reset_status(hdev, queue_gid);
6795                 if (reset_status)
6796                         break;
6797         }
6798
6799         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6800                 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
6801                 return;
6802         }
6803
6804         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6805         if (ret)
6806                 dev_warn(&hdev->pdev->dev,
6807                          "Deassert the soft reset fail, ret = %d\n", ret);
6808 }
6809
6810 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
6811 {
6812         struct hclge_vport *vport = hclge_get_vport(handle);
6813         struct hclge_dev *hdev = vport->back;
6814
6815         return hdev->fw_version;
6816 }
6817
6818 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6819 {
6820         struct phy_device *phydev = hdev->hw.mac.phydev;
6821
6822         if (!phydev)
6823                 return;
6824
6825         phy_set_asym_pause(phydev, rx_en, tx_en);
6826 }
6827
6828 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6829 {
6830         int ret;
6831
6832         if (rx_en && tx_en)
6833                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
6834         else if (rx_en && !tx_en)
6835                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
6836         else if (!rx_en && tx_en)
6837                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
6838         else
6839                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
6840
6841         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
6842                 return 0;
6843
6844         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
6845         if (ret) {
6846                 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
6847                         ret);
6848                 return ret;
6849         }
6850
6851         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
6852
6853         return 0;
6854 }
6855
6856 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
6857 {
6858         struct phy_device *phydev = hdev->hw.mac.phydev;
6859         u16 remote_advertising = 0;
6860         u16 local_advertising = 0;
6861         u32 rx_pause, tx_pause;
6862         u8 flowctl;
6863
6864         if (!phydev->link || !phydev->autoneg)
6865                 return 0;
6866
6867         local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
6868
6869         if (phydev->pause)
6870                 remote_advertising = LPA_PAUSE_CAP;
6871
6872         if (phydev->asym_pause)
6873                 remote_advertising |= LPA_PAUSE_ASYM;
6874
6875         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
6876                                            remote_advertising);
6877         tx_pause = flowctl & FLOW_CTRL_TX;
6878         rx_pause = flowctl & FLOW_CTRL_RX;
6879
6880         if (phydev->duplex == HCLGE_MAC_HALF) {
6881                 tx_pause = 0;
6882                 rx_pause = 0;
6883         }
6884
6885         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
6886 }
6887
6888 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
6889                                  u32 *rx_en, u32 *tx_en)
6890 {
6891         struct hclge_vport *vport = hclge_get_vport(handle);
6892         struct hclge_dev *hdev = vport->back;
6893
6894         *auto_neg = hclge_get_autoneg(handle);
6895
6896         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6897                 *rx_en = 0;
6898                 *tx_en = 0;
6899                 return;
6900         }
6901
6902         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
6903                 *rx_en = 1;
6904                 *tx_en = 0;
6905         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
6906                 *tx_en = 1;
6907                 *rx_en = 0;
6908         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
6909                 *rx_en = 1;
6910                 *tx_en = 1;
6911         } else {
6912                 *rx_en = 0;
6913                 *tx_en = 0;
6914         }
6915 }
6916
6917 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
6918                                 u32 rx_en, u32 tx_en)
6919 {
6920         struct hclge_vport *vport = hclge_get_vport(handle);
6921         struct hclge_dev *hdev = vport->back;
6922         struct phy_device *phydev = hdev->hw.mac.phydev;
6923         u32 fc_autoneg;
6924
6925         fc_autoneg = hclge_get_autoneg(handle);
6926         if (auto_neg != fc_autoneg) {
6927                 dev_info(&hdev->pdev->dev,
6928                          "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
6929                 return -EOPNOTSUPP;
6930         }
6931
6932         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6933                 dev_info(&hdev->pdev->dev,
6934                          "Priority flow control enabled. Cannot set link flow control.\n");
6935                 return -EOPNOTSUPP;
6936         }
6937
6938         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
6939
6940         if (!fc_autoneg)
6941                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
6942
6943         /* Only support flow control negotiation for netdev with
6944          * phy attached for now.
6945          */
6946         if (!phydev)
6947                 return -EOPNOTSUPP;
6948
6949         return phy_start_aneg(phydev);
6950 }
6951
6952 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
6953                                           u8 *auto_neg, u32 *speed, u8 *duplex)
6954 {
6955         struct hclge_vport *vport = hclge_get_vport(handle);
6956         struct hclge_dev *hdev = vport->back;
6957
6958         if (speed)
6959                 *speed = hdev->hw.mac.speed;
6960         if (duplex)
6961                 *duplex = hdev->hw.mac.duplex;
6962         if (auto_neg)
6963                 *auto_neg = hdev->hw.mac.autoneg;
6964 }
6965
6966 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
6967 {
6968         struct hclge_vport *vport = hclge_get_vport(handle);
6969         struct hclge_dev *hdev = vport->back;
6970
6971         if (media_type)
6972                 *media_type = hdev->hw.mac.media_type;
6973 }
6974
6975 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
6976                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
6977 {
6978         struct hclge_vport *vport = hclge_get_vport(handle);
6979         struct hclge_dev *hdev = vport->back;
6980         struct phy_device *phydev = hdev->hw.mac.phydev;
6981         int mdix_ctrl, mdix, retval, is_resolved;
6982
6983         if (!phydev) {
6984                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6985                 *tp_mdix = ETH_TP_MDI_INVALID;
6986                 return;
6987         }
6988
6989         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
6990
6991         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
6992         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
6993                                     HCLGE_PHY_MDIX_CTRL_S);
6994
6995         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
6996         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
6997         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
6998
6999         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
7000
7001         switch (mdix_ctrl) {
7002         case 0x0:
7003                 *tp_mdix_ctrl = ETH_TP_MDI;
7004                 break;
7005         case 0x1:
7006                 *tp_mdix_ctrl = ETH_TP_MDI_X;
7007                 break;
7008         case 0x3:
7009                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
7010                 break;
7011         default:
7012                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
7013                 break;
7014         }
7015
7016         if (!is_resolved)
7017                 *tp_mdix = ETH_TP_MDI_INVALID;
7018         else if (mdix)
7019                 *tp_mdix = ETH_TP_MDI_X;
7020         else
7021                 *tp_mdix = ETH_TP_MDI;
7022 }
7023
7024 static int hclge_init_instance_hw(struct hclge_dev *hdev)
7025 {
7026         return hclge_mac_connect_phy(hdev);
7027 }
7028
7029 static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
7030 {
7031         hclge_mac_disconnect_phy(hdev);
7032 }
7033
7034 static int hclge_init_client_instance(struct hnae3_client *client,
7035                                       struct hnae3_ae_dev *ae_dev)
7036 {
7037         struct hclge_dev *hdev = ae_dev->priv;
7038         struct hclge_vport *vport;
7039         int i, ret;
7040
7041         for (i = 0; i <  hdev->num_vmdq_vport + 1; i++) {
7042                 vport = &hdev->vport[i];
7043
7044                 switch (client->type) {
7045                 case HNAE3_CLIENT_KNIC:
7046
7047                         hdev->nic_client = client;
7048                         vport->nic.client = client;
7049                         ret = client->ops->init_instance(&vport->nic);
7050                         if (ret)
7051                                 goto clear_nic;
7052
7053                         ret = hclge_init_instance_hw(hdev);
7054                         if (ret) {
7055                                 client->ops->uninit_instance(&vport->nic,
7056                                                              0);
7057                                 goto clear_nic;
7058                         }
7059
7060                         hnae3_set_client_init_flag(client, ae_dev, 1);
7061
7062                         if (hdev->roce_client &&
7063                             hnae3_dev_roce_supported(hdev)) {
7064                                 struct hnae3_client *rc = hdev->roce_client;
7065
7066                                 ret = hclge_init_roce_base_info(vport);
7067                                 if (ret)
7068                                         goto clear_roce;
7069
7070                                 ret = rc->ops->init_instance(&vport->roce);
7071                                 if (ret)
7072                                         goto clear_roce;
7073
7074                                 hnae3_set_client_init_flag(hdev->roce_client,
7075                                                            ae_dev, 1);
7076                         }
7077
7078                         break;
7079                 case HNAE3_CLIENT_UNIC:
7080                         hdev->nic_client = client;
7081                         vport->nic.client = client;
7082
7083                         ret = client->ops->init_instance(&vport->nic);
7084                         if (ret)
7085                                 goto clear_nic;
7086
7087                         hnae3_set_client_init_flag(client, ae_dev, 1);
7088
7089                         break;
7090                 case HNAE3_CLIENT_ROCE:
7091                         if (hnae3_dev_roce_supported(hdev)) {
7092                                 hdev->roce_client = client;
7093                                 vport->roce.client = client;
7094                         }
7095
7096                         if (hdev->roce_client && hdev->nic_client) {
7097                                 ret = hclge_init_roce_base_info(vport);
7098                                 if (ret)
7099                                         goto clear_roce;
7100
7101                                 ret = client->ops->init_instance(&vport->roce);
7102                                 if (ret)
7103                                         goto clear_roce;
7104
7105                                 hnae3_set_client_init_flag(client, ae_dev, 1);
7106                         }
7107
7108                         break;
7109                 default:
7110                         return -EINVAL;
7111                 }
7112         }
7113
7114         return 0;
7115
7116 clear_nic:
7117         hdev->nic_client = NULL;
7118         vport->nic.client = NULL;
7119         return ret;
7120 clear_roce:
7121         hdev->roce_client = NULL;
7122         vport->roce.client = NULL;
7123         return ret;
7124 }
7125
7126 static void hclge_uninit_client_instance(struct hnae3_client *client,
7127                                          struct hnae3_ae_dev *ae_dev)
7128 {
7129         struct hclge_dev *hdev = ae_dev->priv;
7130         struct hclge_vport *vport;
7131         int i;
7132
7133         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
7134                 vport = &hdev->vport[i];
7135                 if (hdev->roce_client) {
7136                         hdev->roce_client->ops->uninit_instance(&vport->roce,
7137                                                                 0);
7138                         hdev->roce_client = NULL;
7139                         vport->roce.client = NULL;
7140                 }
7141                 if (client->type == HNAE3_CLIENT_ROCE)
7142                         return;
7143                 if (hdev->nic_client && client->ops->uninit_instance) {
7144                         hclge_uninit_instance_hw(hdev);
7145                         client->ops->uninit_instance(&vport->nic, 0);
7146                         hdev->nic_client = NULL;
7147                         vport->nic.client = NULL;
7148                 }
7149         }
7150 }
7151
7152 static int hclge_pci_init(struct hclge_dev *hdev)
7153 {
7154         struct pci_dev *pdev = hdev->pdev;
7155         struct hclge_hw *hw;
7156         int ret;
7157
7158         ret = pci_enable_device(pdev);
7159         if (ret) {
7160                 dev_err(&pdev->dev, "failed to enable PCI device\n");
7161                 return ret;
7162         }
7163
7164         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7165         if (ret) {
7166                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7167                 if (ret) {
7168                         dev_err(&pdev->dev,
7169                                 "can't set consistent PCI DMA");
7170                         goto err_disable_device;
7171                 }
7172                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
7173         }
7174
7175         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
7176         if (ret) {
7177                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
7178                 goto err_disable_device;
7179         }
7180
7181         pci_set_master(pdev);
7182         hw = &hdev->hw;
7183         hw->io_base = pcim_iomap(pdev, 2, 0);
7184         if (!hw->io_base) {
7185                 dev_err(&pdev->dev, "Can't map configuration register space\n");
7186                 ret = -ENOMEM;
7187                 goto err_clr_master;
7188         }
7189
7190         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
7191
7192         return 0;
7193 err_clr_master:
7194         pci_clear_master(pdev);
7195         pci_release_regions(pdev);
7196 err_disable_device:
7197         pci_disable_device(pdev);
7198
7199         return ret;
7200 }
7201
7202 static void hclge_pci_uninit(struct hclge_dev *hdev)
7203 {
7204         struct pci_dev *pdev = hdev->pdev;
7205
7206         pcim_iounmap(pdev, hdev->hw.io_base);
7207         pci_free_irq_vectors(pdev);
7208         pci_clear_master(pdev);
7209         pci_release_mem_regions(pdev);
7210         pci_disable_device(pdev);
7211 }
7212
7213 static void hclge_state_init(struct hclge_dev *hdev)
7214 {
7215         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
7216         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7217         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
7218         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
7219         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
7220         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
7221 }
7222
7223 static void hclge_state_uninit(struct hclge_dev *hdev)
7224 {
7225         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7226
7227         if (hdev->service_timer.function)
7228                 del_timer_sync(&hdev->service_timer);
7229         if (hdev->reset_timer.function)
7230                 del_timer_sync(&hdev->reset_timer);
7231         if (hdev->service_task.func)
7232                 cancel_work_sync(&hdev->service_task);
7233         if (hdev->rst_service_task.func)
7234                 cancel_work_sync(&hdev->rst_service_task);
7235         if (hdev->mbx_service_task.func)
7236                 cancel_work_sync(&hdev->mbx_service_task);
7237 }
7238
7239 static void hclge_flr_prepare(struct hnae3_ae_dev *ae_dev)
7240 {
7241 #define HCLGE_FLR_WAIT_MS       100
7242 #define HCLGE_FLR_WAIT_CNT      50
7243         struct hclge_dev *hdev = ae_dev->priv;
7244         int cnt = 0;
7245
7246         clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
7247         clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
7248         set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
7249         hclge_reset_event(hdev->pdev, NULL);
7250
7251         while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
7252                cnt++ < HCLGE_FLR_WAIT_CNT)
7253                 msleep(HCLGE_FLR_WAIT_MS);
7254
7255         if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
7256                 dev_err(&hdev->pdev->dev,
7257                         "flr wait down timeout: %d\n", cnt);
7258 }
7259
7260 static void hclge_flr_done(struct hnae3_ae_dev *ae_dev)
7261 {
7262         struct hclge_dev *hdev = ae_dev->priv;
7263
7264         set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
7265 }
7266
7267 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
7268 {
7269         struct pci_dev *pdev = ae_dev->pdev;
7270         struct hclge_dev *hdev;
7271         int ret;
7272
7273         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
7274         if (!hdev) {
7275                 ret = -ENOMEM;
7276                 goto out;
7277         }
7278
7279         hdev->pdev = pdev;
7280         hdev->ae_dev = ae_dev;
7281         hdev->reset_type = HNAE3_NONE_RESET;
7282         hdev->reset_level = HNAE3_FUNC_RESET;
7283         ae_dev->priv = hdev;
7284         hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
7285
7286         mutex_init(&hdev->vport_lock);
7287
7288         ret = hclge_pci_init(hdev);
7289         if (ret) {
7290                 dev_err(&pdev->dev, "PCI init failed\n");
7291                 goto out;
7292         }
7293
7294         /* Firmware command queue initialize */
7295         ret = hclge_cmd_queue_init(hdev);
7296         if (ret) {
7297                 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
7298                 goto err_pci_uninit;
7299         }
7300
7301         /* Firmware command initialize */
7302         ret = hclge_cmd_init(hdev);
7303         if (ret)
7304                 goto err_cmd_uninit;
7305
7306         ret = hclge_get_cap(hdev);
7307         if (ret) {
7308                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
7309                         ret);
7310                 goto err_cmd_uninit;
7311         }
7312
7313         ret = hclge_configure(hdev);
7314         if (ret) {
7315                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
7316                 goto err_cmd_uninit;
7317         }
7318
7319         ret = hclge_init_msi(hdev);
7320         if (ret) {
7321                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
7322                 goto err_cmd_uninit;
7323         }
7324
7325         ret = hclge_misc_irq_init(hdev);
7326         if (ret) {
7327                 dev_err(&pdev->dev,
7328                         "Misc IRQ(vector0) init error, ret = %d.\n",
7329                         ret);
7330                 goto err_msi_uninit;
7331         }
7332
7333         ret = hclge_alloc_tqps(hdev);
7334         if (ret) {
7335                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
7336                 goto err_msi_irq_uninit;
7337         }
7338
7339         ret = hclge_alloc_vport(hdev);
7340         if (ret) {
7341                 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
7342                 goto err_msi_irq_uninit;
7343         }
7344
7345         ret = hclge_map_tqp(hdev);
7346         if (ret) {
7347                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
7348                 goto err_msi_irq_uninit;
7349         }
7350
7351         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
7352                 ret = hclge_mac_mdio_config(hdev);
7353                 if (ret) {
7354                         dev_err(&hdev->pdev->dev,
7355                                 "mdio config fail ret=%d\n", ret);
7356                         goto err_msi_irq_uninit;
7357                 }
7358         }
7359
7360         ret = hclge_init_umv_space(hdev);
7361         if (ret) {
7362                 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
7363                 goto err_msi_irq_uninit;
7364         }
7365
7366         ret = hclge_mac_init(hdev);
7367         if (ret) {
7368                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7369                 goto err_mdiobus_unreg;
7370         }
7371
7372         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7373         if (ret) {
7374                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7375                 goto err_mdiobus_unreg;
7376         }
7377
7378         ret = hclge_config_gro(hdev, true);
7379         if (ret)
7380                 goto err_mdiobus_unreg;
7381
7382         ret = hclge_init_vlan_config(hdev);
7383         if (ret) {
7384                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7385                 goto err_mdiobus_unreg;
7386         }
7387
7388         ret = hclge_tm_schd_init(hdev);
7389         if (ret) {
7390                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
7391                 goto err_mdiobus_unreg;
7392         }
7393
7394         hclge_rss_init_cfg(hdev);
7395         ret = hclge_rss_init_hw(hdev);
7396         if (ret) {
7397                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7398                 goto err_mdiobus_unreg;
7399         }
7400
7401         ret = init_mgr_tbl(hdev);
7402         if (ret) {
7403                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
7404                 goto err_mdiobus_unreg;
7405         }
7406
7407         ret = hclge_init_fd_config(hdev);
7408         if (ret) {
7409                 dev_err(&pdev->dev,
7410                         "fd table init fail, ret=%d\n", ret);
7411                 goto err_mdiobus_unreg;
7412         }
7413
7414         ret = hclge_hw_error_set_state(hdev, true);
7415         if (ret) {
7416                 dev_err(&pdev->dev,
7417                         "fail(%d) to enable hw error interrupts\n", ret);
7418                 goto err_mdiobus_unreg;
7419         }
7420
7421         hclge_dcb_ops_set(hdev);
7422
7423         timer_setup(&hdev->service_timer, hclge_service_timer, 0);
7424         timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
7425         INIT_WORK(&hdev->service_task, hclge_service_task);
7426         INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
7427         INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
7428
7429         hclge_clear_all_event_cause(hdev);
7430
7431         /* Enable MISC vector(vector0) */
7432         hclge_enable_vector(&hdev->misc_vector, true);
7433
7434         hclge_state_init(hdev);
7435         hdev->last_reset_time = jiffies;
7436
7437         pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
7438         return 0;
7439
7440 err_mdiobus_unreg:
7441         if (hdev->hw.mac.phydev)
7442                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
7443 err_msi_irq_uninit:
7444         hclge_misc_irq_uninit(hdev);
7445 err_msi_uninit:
7446         pci_free_irq_vectors(pdev);
7447 err_cmd_uninit:
7448         hclge_destroy_cmd_queue(&hdev->hw);
7449 err_pci_uninit:
7450         pcim_iounmap(pdev, hdev->hw.io_base);
7451         pci_clear_master(pdev);
7452         pci_release_regions(pdev);
7453         pci_disable_device(pdev);
7454 out:
7455         return ret;
7456 }
7457
7458 static void hclge_stats_clear(struct hclge_dev *hdev)
7459 {
7460         memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
7461 }
7462
7463 static void hclge_reset_vport_state(struct hclge_dev *hdev)
7464 {
7465         struct hclge_vport *vport = hdev->vport;
7466         int i;
7467
7468         for (i = 0; i < hdev->num_alloc_vport; i++) {
7469                 hclge_vport_start(vport);
7470                 vport++;
7471         }
7472 }
7473
7474 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
7475 {
7476         struct hclge_dev *hdev = ae_dev->priv;
7477         struct pci_dev *pdev = ae_dev->pdev;
7478         int ret;
7479
7480         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7481
7482         hclge_stats_clear(hdev);
7483         memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
7484
7485         ret = hclge_cmd_init(hdev);
7486         if (ret) {
7487                 dev_err(&pdev->dev, "Cmd queue init failed\n");
7488                 return ret;
7489         }
7490
7491         ret = hclge_map_tqp(hdev);
7492         if (ret) {
7493                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
7494                 return ret;
7495         }
7496
7497         hclge_reset_umv_space(hdev);
7498
7499         ret = hclge_mac_init(hdev);
7500         if (ret) {
7501                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7502                 return ret;
7503         }
7504
7505         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7506         if (ret) {
7507                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7508                 return ret;
7509         }
7510
7511         ret = hclge_config_gro(hdev, true);
7512         if (ret)
7513                 return ret;
7514
7515         ret = hclge_init_vlan_config(hdev);
7516         if (ret) {
7517                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7518                 return ret;
7519         }
7520
7521         ret = hclge_tm_init_hw(hdev, true);
7522         if (ret) {
7523                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
7524                 return ret;
7525         }
7526
7527         ret = hclge_rss_init_hw(hdev);
7528         if (ret) {
7529                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7530                 return ret;
7531         }
7532
7533         ret = hclge_init_fd_config(hdev);
7534         if (ret) {
7535                 dev_err(&pdev->dev,
7536                         "fd table init fail, ret=%d\n", ret);
7537                 return ret;
7538         }
7539
7540         /* Re-enable the hw error interrupts because
7541          * the interrupts get disabled on core/global reset.
7542          */
7543         ret = hclge_hw_error_set_state(hdev, true);
7544         if (ret) {
7545                 dev_err(&pdev->dev,
7546                         "fail(%d) to re-enable HNS hw error interrupts\n", ret);
7547                 return ret;
7548         }
7549
7550         hclge_reset_vport_state(hdev);
7551
7552         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
7553                  HCLGE_DRIVER_NAME);
7554
7555         return 0;
7556 }
7557
7558 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
7559 {
7560         struct hclge_dev *hdev = ae_dev->priv;
7561         struct hclge_mac *mac = &hdev->hw.mac;
7562
7563         hclge_state_uninit(hdev);
7564
7565         if (mac->phydev)
7566                 mdiobus_unregister(mac->mdio_bus);
7567
7568         hclge_uninit_umv_space(hdev);
7569
7570         /* Disable MISC vector(vector0) */
7571         hclge_enable_vector(&hdev->misc_vector, false);
7572         synchronize_irq(hdev->misc_vector.vector_irq);
7573
7574         hclge_hw_error_set_state(hdev, false);
7575         hclge_destroy_cmd_queue(&hdev->hw);
7576         hclge_misc_irq_uninit(hdev);
7577         hclge_pci_uninit(hdev);
7578         mutex_destroy(&hdev->vport_lock);
7579         ae_dev->priv = NULL;
7580 }
7581
7582 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
7583 {
7584         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7585         struct hclge_vport *vport = hclge_get_vport(handle);
7586         struct hclge_dev *hdev = vport->back;
7587
7588         return min_t(u32, hdev->rss_size_max,
7589                      vport->alloc_tqps / kinfo->num_tc);
7590 }
7591
7592 static void hclge_get_channels(struct hnae3_handle *handle,
7593                                struct ethtool_channels *ch)
7594 {
7595         ch->max_combined = hclge_get_max_channels(handle);
7596         ch->other_count = 1;
7597         ch->max_other = 1;
7598         ch->combined_count = handle->kinfo.rss_size;
7599 }
7600
7601 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
7602                                         u16 *alloc_tqps, u16 *max_rss_size)
7603 {
7604         struct hclge_vport *vport = hclge_get_vport(handle);
7605         struct hclge_dev *hdev = vport->back;
7606
7607         *alloc_tqps = vport->alloc_tqps;
7608         *max_rss_size = hdev->rss_size_max;
7609 }
7610
7611 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
7612                               bool rxfh_configured)
7613 {
7614         struct hclge_vport *vport = hclge_get_vport(handle);
7615         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7616         struct hclge_dev *hdev = vport->back;
7617         int cur_rss_size = kinfo->rss_size;
7618         int cur_tqps = kinfo->num_tqps;
7619         u16 tc_offset[HCLGE_MAX_TC_NUM];
7620         u16 tc_valid[HCLGE_MAX_TC_NUM];
7621         u16 tc_size[HCLGE_MAX_TC_NUM];
7622         u16 roundup_size;
7623         u32 *rss_indir;
7624         int ret, i;
7625
7626         kinfo->req_rss_size = new_tqps_num;
7627
7628         ret = hclge_tm_vport_map_update(hdev);
7629         if (ret) {
7630                 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret);
7631                 return ret;
7632         }
7633
7634         roundup_size = roundup_pow_of_two(kinfo->rss_size);
7635         roundup_size = ilog2(roundup_size);
7636         /* Set the RSS TC mode according to the new RSS size */
7637         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
7638                 tc_valid[i] = 0;
7639
7640                 if (!(hdev->hw_tc_map & BIT(i)))
7641                         continue;
7642
7643                 tc_valid[i] = 1;
7644                 tc_size[i] = roundup_size;
7645                 tc_offset[i] = kinfo->rss_size * i;
7646         }
7647         ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
7648         if (ret)
7649                 return ret;
7650
7651         /* RSS indirection table has been configuared by user */
7652         if (rxfh_configured)
7653                 goto out;
7654
7655         /* Reinitializes the rss indirect table according to the new RSS size */
7656         rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
7657         if (!rss_indir)
7658                 return -ENOMEM;
7659
7660         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
7661                 rss_indir[i] = i % kinfo->rss_size;
7662
7663         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
7664         if (ret)
7665                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
7666                         ret);
7667
7668         kfree(rss_indir);
7669
7670 out:
7671         if (!ret)
7672                 dev_info(&hdev->pdev->dev,
7673                          "Channels changed, rss_size from %d to %d, tqps from %d to %d",
7674                          cur_rss_size, kinfo->rss_size,
7675                          cur_tqps, kinfo->rss_size * kinfo->num_tc);
7676
7677         return ret;
7678 }
7679
7680 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
7681                               u32 *regs_num_64_bit)
7682 {
7683         struct hclge_desc desc;
7684         u32 total_num;
7685         int ret;
7686
7687         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
7688         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7689         if (ret) {
7690                 dev_err(&hdev->pdev->dev,
7691                         "Query register number cmd failed, ret = %d.\n", ret);
7692                 return ret;
7693         }
7694
7695         *regs_num_32_bit = le32_to_cpu(desc.data[0]);
7696         *regs_num_64_bit = le32_to_cpu(desc.data[1]);
7697
7698         total_num = *regs_num_32_bit + *regs_num_64_bit;
7699         if (!total_num)
7700                 return -EINVAL;
7701
7702         return 0;
7703 }
7704
7705 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7706                                  void *data)
7707 {
7708 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
7709
7710         struct hclge_desc *desc;
7711         u32 *reg_val = data;
7712         __le32 *desc_data;
7713         int cmd_num;
7714         int i, k, n;
7715         int ret;
7716
7717         if (regs_num == 0)
7718                 return 0;
7719
7720         cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
7721         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7722         if (!desc)
7723                 return -ENOMEM;
7724
7725         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
7726         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7727         if (ret) {
7728                 dev_err(&hdev->pdev->dev,
7729                         "Query 32 bit register cmd failed, ret = %d.\n", ret);
7730                 kfree(desc);
7731                 return ret;
7732         }
7733
7734         for (i = 0; i < cmd_num; i++) {
7735                 if (i == 0) {
7736                         desc_data = (__le32 *)(&desc[i].data[0]);
7737                         n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
7738                 } else {
7739                         desc_data = (__le32 *)(&desc[i]);
7740                         n = HCLGE_32_BIT_REG_RTN_DATANUM;
7741                 }
7742                 for (k = 0; k < n; k++) {
7743                         *reg_val++ = le32_to_cpu(*desc_data++);
7744
7745                         regs_num--;
7746                         if (!regs_num)
7747                                 break;
7748                 }
7749         }
7750
7751         kfree(desc);
7752         return 0;
7753 }
7754
7755 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7756                                  void *data)
7757 {
7758 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
7759
7760         struct hclge_desc *desc;
7761         u64 *reg_val = data;
7762         __le64 *desc_data;
7763         int cmd_num;
7764         int i, k, n;
7765         int ret;
7766
7767         if (regs_num == 0)
7768                 return 0;
7769
7770         cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
7771         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7772         if (!desc)
7773                 return -ENOMEM;
7774
7775         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
7776         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7777         if (ret) {
7778                 dev_err(&hdev->pdev->dev,
7779                         "Query 64 bit register cmd failed, ret = %d.\n", ret);
7780                 kfree(desc);
7781                 return ret;
7782         }
7783
7784         for (i = 0; i < cmd_num; i++) {
7785                 if (i == 0) {
7786                         desc_data = (__le64 *)(&desc[i].data[0]);
7787                         n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
7788                 } else {
7789                         desc_data = (__le64 *)(&desc[i]);
7790                         n = HCLGE_64_BIT_REG_RTN_DATANUM;
7791                 }
7792                 for (k = 0; k < n; k++) {
7793                         *reg_val++ = le64_to_cpu(*desc_data++);
7794
7795                         regs_num--;
7796                         if (!regs_num)
7797                                 break;
7798                 }
7799         }
7800
7801         kfree(desc);
7802         return 0;
7803 }
7804
7805 #define MAX_SEPARATE_NUM        4
7806 #define SEPARATOR_VALUE         0xFFFFFFFF
7807 #define REG_NUM_PER_LINE        4
7808 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(u32))
7809
7810 static int hclge_get_regs_len(struct hnae3_handle *handle)
7811 {
7812         int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
7813         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7814         struct hclge_vport *vport = hclge_get_vport(handle);
7815         struct hclge_dev *hdev = vport->back;
7816         u32 regs_num_32_bit, regs_num_64_bit;
7817         int ret;
7818
7819         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7820         if (ret) {
7821                 dev_err(&hdev->pdev->dev,
7822                         "Get register number failed, ret = %d.\n", ret);
7823                 return -EOPNOTSUPP;
7824         }
7825
7826         cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
7827         common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
7828         ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
7829         tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
7830
7831         return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps +
7832                 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE +
7833                 regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
7834 }
7835
7836 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
7837                            void *data)
7838 {
7839         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7840         struct hclge_vport *vport = hclge_get_vport(handle);
7841         struct hclge_dev *hdev = vport->back;
7842         u32 regs_num_32_bit, regs_num_64_bit;
7843         int i, j, reg_um, separator_num;
7844         u32 *reg = data;
7845         int ret;
7846
7847         *version = hdev->fw_version;
7848
7849         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7850         if (ret) {
7851                 dev_err(&hdev->pdev->dev,
7852                         "Get register number failed, ret = %d.\n", ret);
7853                 return;
7854         }
7855
7856         /* fetching per-PF registers valus from PF PCIe register space */
7857         reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
7858         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7859         for (i = 0; i < reg_um; i++)
7860                 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
7861         for (i = 0; i < separator_num; i++)
7862                 *reg++ = SEPARATOR_VALUE;
7863
7864         reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
7865         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7866         for (i = 0; i < reg_um; i++)
7867                 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
7868         for (i = 0; i < separator_num; i++)
7869                 *reg++ = SEPARATOR_VALUE;
7870
7871         reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
7872         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7873         for (j = 0; j < kinfo->num_tqps; j++) {
7874                 for (i = 0; i < reg_um; i++)
7875                         *reg++ = hclge_read_dev(&hdev->hw,
7876                                                 ring_reg_addr_list[i] +
7877                                                 0x200 * j);
7878                 for (i = 0; i < separator_num; i++)
7879                         *reg++ = SEPARATOR_VALUE;
7880         }
7881
7882         reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
7883         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7884         for (j = 0; j < hdev->num_msi_used - 1; j++) {
7885                 for (i = 0; i < reg_um; i++)
7886                         *reg++ = hclge_read_dev(&hdev->hw,
7887                                                 tqp_intr_reg_addr_list[i] +
7888                                                 4 * j);
7889                 for (i = 0; i < separator_num; i++)
7890                         *reg++ = SEPARATOR_VALUE;
7891         }
7892
7893         /* fetching PF common registers values from firmware */
7894         ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg);
7895         if (ret) {
7896                 dev_err(&hdev->pdev->dev,
7897                         "Get 32 bit register failed, ret = %d.\n", ret);
7898                 return;
7899         }
7900
7901         reg += regs_num_32_bit;
7902         ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg);
7903         if (ret)
7904                 dev_err(&hdev->pdev->dev,
7905                         "Get 64 bit register failed, ret = %d.\n", ret);
7906 }
7907
7908 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
7909 {
7910         struct hclge_set_led_state_cmd *req;
7911         struct hclge_desc desc;
7912         int ret;
7913
7914         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
7915
7916         req = (struct hclge_set_led_state_cmd *)desc.data;
7917         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
7918                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
7919
7920         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7921         if (ret)
7922                 dev_err(&hdev->pdev->dev,
7923                         "Send set led state cmd error, ret =%d\n", ret);
7924
7925         return ret;
7926 }
7927
7928 enum hclge_led_status {
7929         HCLGE_LED_OFF,
7930         HCLGE_LED_ON,
7931         HCLGE_LED_NO_CHANGE = 0xFF,
7932 };
7933
7934 static int hclge_set_led_id(struct hnae3_handle *handle,
7935                             enum ethtool_phys_id_state status)
7936 {
7937         struct hclge_vport *vport = hclge_get_vport(handle);
7938         struct hclge_dev *hdev = vport->back;
7939
7940         switch (status) {
7941         case ETHTOOL_ID_ACTIVE:
7942                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
7943         case ETHTOOL_ID_INACTIVE:
7944                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
7945         default:
7946                 return -EINVAL;
7947         }
7948 }
7949
7950 static void hclge_get_link_mode(struct hnae3_handle *handle,
7951                                 unsigned long *supported,
7952                                 unsigned long *advertising)
7953 {
7954         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
7955         struct hclge_vport *vport = hclge_get_vport(handle);
7956         struct hclge_dev *hdev = vport->back;
7957         unsigned int idx = 0;
7958
7959         for (; idx < size; idx++) {
7960                 supported[idx] = hdev->hw.mac.supported[idx];
7961                 advertising[idx] = hdev->hw.mac.advertising[idx];
7962         }
7963 }
7964
7965 static int hclge_gro_en(struct hnae3_handle *handle, int enable)
7966 {
7967         struct hclge_vport *vport = hclge_get_vport(handle);
7968         struct hclge_dev *hdev = vport->back;
7969
7970         return hclge_config_gro(hdev, enable);
7971 }
7972
7973 static const struct hnae3_ae_ops hclge_ops = {
7974         .init_ae_dev = hclge_init_ae_dev,
7975         .uninit_ae_dev = hclge_uninit_ae_dev,
7976         .flr_prepare = hclge_flr_prepare,
7977         .flr_done = hclge_flr_done,
7978         .init_client_instance = hclge_init_client_instance,
7979         .uninit_client_instance = hclge_uninit_client_instance,
7980         .map_ring_to_vector = hclge_map_ring_to_vector,
7981         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
7982         .get_vector = hclge_get_vector,
7983         .put_vector = hclge_put_vector,
7984         .set_promisc_mode = hclge_set_promisc_mode,
7985         .set_loopback = hclge_set_loopback,
7986         .start = hclge_ae_start,
7987         .stop = hclge_ae_stop,
7988         .client_start = hclge_client_start,
7989         .client_stop = hclge_client_stop,
7990         .get_status = hclge_get_status,
7991         .get_ksettings_an_result = hclge_get_ksettings_an_result,
7992         .update_speed_duplex_h = hclge_update_speed_duplex_h,
7993         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
7994         .get_media_type = hclge_get_media_type,
7995         .get_rss_key_size = hclge_get_rss_key_size,
7996         .get_rss_indir_size = hclge_get_rss_indir_size,
7997         .get_rss = hclge_get_rss,
7998         .set_rss = hclge_set_rss,
7999         .set_rss_tuple = hclge_set_rss_tuple,
8000         .get_rss_tuple = hclge_get_rss_tuple,
8001         .get_tc_size = hclge_get_tc_size,
8002         .get_mac_addr = hclge_get_mac_addr,
8003         .set_mac_addr = hclge_set_mac_addr,
8004         .do_ioctl = hclge_do_ioctl,
8005         .add_uc_addr = hclge_add_uc_addr,
8006         .rm_uc_addr = hclge_rm_uc_addr,
8007         .add_mc_addr = hclge_add_mc_addr,
8008         .rm_mc_addr = hclge_rm_mc_addr,
8009         .set_autoneg = hclge_set_autoneg,
8010         .get_autoneg = hclge_get_autoneg,
8011         .get_pauseparam = hclge_get_pauseparam,
8012         .set_pauseparam = hclge_set_pauseparam,
8013         .set_mtu = hclge_set_mtu,
8014         .reset_queue = hclge_reset_tqp,
8015         .get_stats = hclge_get_stats,
8016         .update_stats = hclge_update_stats,
8017         .get_strings = hclge_get_strings,
8018         .get_sset_count = hclge_get_sset_count,
8019         .get_fw_version = hclge_get_fw_version,
8020         .get_mdix_mode = hclge_get_mdix_mode,
8021         .enable_vlan_filter = hclge_enable_vlan_filter,
8022         .set_vlan_filter = hclge_set_vlan_filter,
8023         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
8024         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
8025         .reset_event = hclge_reset_event,
8026         .set_default_reset_request = hclge_set_def_reset_request,
8027         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
8028         .set_channels = hclge_set_channels,
8029         .get_channels = hclge_get_channels,
8030         .get_regs_len = hclge_get_regs_len,
8031         .get_regs = hclge_get_regs,
8032         .set_led_id = hclge_set_led_id,
8033         .get_link_mode = hclge_get_link_mode,
8034         .add_fd_entry = hclge_add_fd_entry,
8035         .del_fd_entry = hclge_del_fd_entry,
8036         .del_all_fd_entries = hclge_del_all_fd_entries,
8037         .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
8038         .get_fd_rule_info = hclge_get_fd_rule_info,
8039         .get_fd_all_rules = hclge_get_all_rules,
8040         .restore_fd_rules = hclge_restore_fd_entries,
8041         .enable_fd = hclge_enable_fd,
8042         .dbg_run_cmd = hclge_dbg_run_cmd,
8043         .handle_hw_ras_error = hclge_handle_hw_ras_error,
8044         .get_hw_reset_stat = hclge_get_hw_reset_stat,
8045         .ae_dev_resetting = hclge_ae_dev_resetting,
8046         .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
8047         .set_gro_en = hclge_gro_en,
8048         .get_global_queue_id = hclge_covert_handle_qid_global,
8049         .set_timer_task = hclge_set_timer_task,
8050 };
8051
8052 static struct hnae3_ae_algo ae_algo = {
8053         .ops = &hclge_ops,
8054         .pdev_id_table = ae_algo_pci_tbl,
8055 };
8056
8057 static int hclge_init(void)
8058 {
8059         pr_info("%s is initializing\n", HCLGE_NAME);
8060
8061         hnae3_register_ae_algo(&ae_algo);
8062
8063         return 0;
8064 }
8065
8066 static void hclge_exit(void)
8067 {
8068         hnae3_unregister_ae_algo(&ae_algo);
8069 }
8070 module_init(hclge_init);
8071 module_exit(hclge_exit);
8072
8073 MODULE_LICENSE("GPL");
8074 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
8075 MODULE_DESCRIPTION("HCLGE Driver");
8076 MODULE_VERSION(HCLGE_MOD_VERSION);