1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
7 #include "hclge_main.h"
9 #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
10 #define HCLGE_RAS_REG_NFE_MASK 0xFF00
11 #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
13 #define HCLGE_VECTOR0_PF_OTHER_INT_STS_REG 0x20800
14 #define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
16 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
17 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
18 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
19 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
20 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
21 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
22 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
23 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000
24 #define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100
25 #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
26 #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
27 #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
28 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
29 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
30 #define HCLGE_IGU_ERR_INT_EN 0x0000066F
31 #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
32 #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
33 #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
34 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
35 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
36 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
37 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
38 #define HCLGE_PPP_PF_ERR_INT_EN 0x0003
39 #define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003
40 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F
41 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
42 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
43 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
44 #define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3
45 #define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
46 #define HCLGE_NCSI_ERR_INT_EN 0x3
47 #define HCLGE_NCSI_ERR_INT_TYPE 0x9
48 #define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF
49 #define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
50 #define HCLGE_MAC_TNL_INT_EN GENMASK(7, 0)
51 #define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(7, 0)
52 #define HCLGE_MAC_TNL_INT_CLR GENMASK(7, 0)
53 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
54 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
55 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
56 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
57 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
58 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
59 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB
60 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
61 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
62 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
63 #define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
64 #define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
65 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
66 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
67 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
68 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
69 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101
70 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
71 #define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)
72 #define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
73 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
74 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
75 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
76 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
78 #define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
79 #define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF
80 #define HCLGE_IGU_INT_MASK GENMASK(3, 0)
81 #define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
82 #define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)
83 #define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)
84 #define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK GENMASK(29, 28)
85 #define HCLGE_PPU_PF_INT_RAS_MASK 0x18
86 #define HCLGE_PPU_PF_INT_MSIX_MASK 0x27
87 #define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)
88 #define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)
89 #define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)
91 #define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF
92 #define HCLGE_ROCEE_RAS_CE_INT_EN 0x1
93 #define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF
94 #define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1
95 #define HCLGE_ROCEE_RERR_INT_MASK BIT(0)
96 #define HCLGE_ROCEE_BERR_INT_MASK BIT(1)
97 #define HCLGE_ROCEE_ECC_INT_MASK BIT(2)
98 #define HCLGE_ROCEE_OVF_INT_MASK BIT(3)
99 #define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000
100 #define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F
102 enum hclge_err_int_type {
103 HCLGE_ERR_INT_MSIX = 0,
104 HCLGE_ERR_INT_RAS_CE = 1,
105 HCLGE_ERR_INT_RAS_NFE = 2,
106 HCLGE_ERR_INT_RAS_FE = 3,
109 struct hclge_hw_blk {
112 int (*config_err_int)(struct hclge_dev *hdev, bool en);
115 struct hclge_hw_error {
118 enum hnae3_reset_type reset_level;
121 int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
122 int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
123 pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
124 int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
125 unsigned long *reset_requests);