drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include "hclge_main.h"
   5 #include "hclge_dcb.h"
   6 #include "hclge_tm.h"
   7 #include "hnae3.h"
   8
   9 #define BW_PERCENT      100
  10
  11 static int hclge_ieee_ets_to_tm_info(struct hclge_dev *hdev,
  12                                      struct ieee_ets *ets)
  13 {
  14         u8 i;
  15
  16         for (i = 0; i < HNAE3_MAX_TC; i++) {
  17                 switch (ets->tc_tsa[i]) {
  18                 case IEEE_8021QAZ_TSA_STRICT:
  19                         hdev->tm_info.tc_info[i].tc_sch_mode =
  20                                 HCLGE_SCH_MODE_SP;
  21                         hdev->tm_info.pg_info[0].tc_dwrr[i] = 0;
  22                         break;
  23                 case IEEE_8021QAZ_TSA_ETS:
  24                         hdev->tm_info.tc_info[i].tc_sch_mode =
  25                                 HCLGE_SCH_MODE_DWRR;
  26                         hdev->tm_info.pg_info[0].tc_dwrr[i] =
  27                                 ets->tc_tx_bw[i];
  28                         break;
  29                 default:
  30                         /* Hardware only supports SP (strict priority)
  31                          * or ETS (enhanced transmission selection)
  32                          * algorithms, if we receive some other value
  33                          * from dcbnl, then throw an error.
  34                          */
  35                         return -EINVAL;
  36                 }
  37         }
  38
  39         hclge_tm_prio_tc_info_update(hdev, ets->prio_tc);
  40
  41         return 0;
  42 }
  43
  44 static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,
  45                                       struct ieee_ets *ets)
  46 {
  47         u32 i;
  48
  49         memset(ets, 0, sizeof(*ets));
  50         ets->willing = 1;
  51         ets->ets_cap = hdev->tc_max;
  52
  53         for (i = 0; i < HNAE3_MAX_TC; i++) {
  54                 ets->prio_tc[i] = hdev->tm_info.prio_tc[i];
  55                 ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
  56
  57                 if (hdev->tm_info.tc_info[i].tc_sch_mode ==
  58                     HCLGE_SCH_MODE_SP)
  59                         ets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT;
  60                 else
  61                         ets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
  62         }
  63 }
  64
  65 /* IEEE std */
  66 static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets)
  67 {
  68         struct hclge_vport *vport = hclge_get_vport(h);
  69         struct hclge_dev *hdev = vport->back;
  70
  71         hclge_tm_info_to_ieee_ets(hdev, ets);
  72
  73         return 0;
  74 }
  75
  76 static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc,
  77                                      u8 *prio_tc)
  78 {
  79         int i;
  80
  81         if (num_tc > hdev->tc_max) {
  82                 dev_err(&hdev->pdev->dev,
  83                         "tc num checking failed, %u > tc_max(%u)\n",
  84                         num_tc, hdev->tc_max);
  85                 return -EINVAL;
  86         }
  87
  88         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
  89                 if (prio_tc[i] >= num_tc) {
  90                         dev_err(&hdev->pdev->dev,
  91                                 "prio_tc[%d] checking failed, %u >= num_tc(%u)\n",
  92                                 i, prio_tc[i], num_tc);
  93                         return -EINVAL;
  94                 }
  95         }
  96
  97         if (num_tc > hdev->vport[0].alloc_tqps) {
  98                 dev_err(&hdev->pdev->dev,
  99                         "allocated tqp checking failed, %u > tqp(%u)\n",
 100                         num_tc, hdev->vport[0].alloc_tqps);
 101                 return -EINVAL;
 102         }
 103
 104         return 0;
 105 }
 106
 107 static u8 hclge_ets_tc_changed(struct hclge_dev *hdev, struct ieee_ets *ets,
 108                                bool *changed)
 109 {
 110         u8 max_tc_id = 0;
 111         u8 i;
 112
 113         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
 114                 if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])
 115                         *changed = true;
 116
 117                 if (ets->prio_tc[i] > max_tc_id)
 118                         max_tc_id = ets->prio_tc[i];
 119         }
 120
 121         /* return max tc number, max tc id need to plus 1 */
 122         return max_tc_id + 1;
 123 }
 124
 125 static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
 126                                        struct ieee_ets *ets, bool *changed)
 127 {
 128         bool has_ets_tc = false;
 129         u32 total_ets_bw = 0;
 130         u8 i;
 131
 132         for (i = 0; i < hdev->tc_max; i++) {
 133                 switch (ets->tc_tsa[i]) {
 134                 case IEEE_8021QAZ_TSA_STRICT:
 135                         if (hdev->tm_info.tc_info[i].tc_sch_mode !=
 136                                 HCLGE_SCH_MODE_SP)
 137                                 *changed = true;
 138                         break;
 139                 case IEEE_8021QAZ_TSA_ETS:
 140                         if (hdev->tm_info.tc_info[i].tc_sch_mode !=
 141                                 HCLGE_SCH_MODE_DWRR)
 142                                 *changed = true;
 143
 144                         total_ets_bw += ets->tc_tx_bw[i];
 145                         has_ets_tc = true;
 146                         break;
 147                 default:
 148                         return -EINVAL;
 149                 }
 150         }
 151
 152         if (has_ets_tc && total_ets_bw != BW_PERCENT)
 153                 return -EINVAL;
 154
 155         return 0;
 156 }
 157
 158 static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
 159                               u8 *tc, bool *changed)
 160 {
 161         u8 tc_num;
 162         int ret;
 163
 164         tc_num = hclge_ets_tc_changed(hdev, ets, changed);
 165
 166         ret = hclge_dcb_common_validate(hdev, tc_num, ets->prio_tc);
 167         if (ret)
 168                 return ret;
 169
 170         ret = hclge_ets_sch_mode_validate(hdev, ets, changed);
 171         if (ret)
 172                 return ret;
 173
 174         *tc = tc_num;
 175         if (*tc != hdev->tm_info.num_tc)
 176                 *changed = true;
 177
 178         return 0;
 179 }
 180
 181 static int hclge_map_update(struct hclge_dev *hdev)
 182 {
 183         int ret;
 184
 185         ret = hclge_tm_schd_setup_hw(hdev);
 186         if (ret)
 187                 return ret;
 188
 189         ret = hclge_pause_setup_hw(hdev, false);
 190         if (ret)
 191                 return ret;
 192
 193         ret = hclge_buffer_alloc(hdev);
 194         if (ret)
 195                 return ret;
 196
 197         hclge_rss_indir_init_cfg(hdev);
 198
 199         return hclge_rss_init_hw(hdev);
 200 }
 201
 202 static int hclge_notify_down_uinit(struct hclge_dev *hdev)
 203 {
 204         int ret;
 205
 206         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
 207         if (ret)
 208                 return ret;
 209
 210         return hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
 211 }
 212
 213 static int hclge_notify_init_up(struct hclge_dev *hdev)
 214 {
 215         int ret;
 216
 217         ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
 218         if (ret)
 219                 return ret;
 220
 221         return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 222 }
 223
 224 static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)
 225 {
 226         struct hclge_vport *vport = hclge_get_vport(h);
 227         struct net_device *netdev = h->kinfo.netdev;
 228         struct hclge_dev *hdev = vport->back;
 229         bool map_changed = false;
 230         u8 num_tc = 0;
 231         int ret;
 232
 233         if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
 234             hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 235                 return -EINVAL;
 236
 237         ret = hclge_ets_validate(hdev, ets, &num_tc, &map_changed);
 238         if (ret)
 239                 return ret;
 240
 241         if (map_changed) {
 242                 netif_dbg(h, drv, netdev, "set ets\n");
 243
 244                 ret = hclge_notify_down_uinit(hdev);
 245                 if (ret)
 246                         return ret;
 247         }
 248
 249         hclge_tm_schd_info_update(hdev, num_tc);
 250
 251         ret = hclge_ieee_ets_to_tm_info(hdev, ets);
 252         if (ret)
 253                 goto err_out;
 254
 255         if (map_changed) {
 256                 ret = hclge_map_update(hdev);
 257                 if (ret)
 258                         goto err_out;
 259
 260                 return hclge_notify_init_up(hdev);
 261         }
 262
 263         return hclge_tm_dwrr_cfg(hdev);
 264
 265 err_out:
 266         if (!map_changed)
 267                 return ret;
 268
 269         hclge_notify_init_up(hdev);
 270
 271         return ret;
 272 }
 273
 274 static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 275 {
 276         u64 requests[HNAE3_MAX_TC], indications[HNAE3_MAX_TC];
 277         struct hclge_vport *vport = hclge_get_vport(h);
 278         struct hclge_dev *hdev = vport->back;
 279         int ret;
 280         u8 i;
 281
 282         memset(pfc, 0, sizeof(*pfc));
 283         pfc->pfc_cap = hdev->pfc_max;
 284         pfc->pfc_en = hdev->tm_info.pfc_en;
 285
 286         ret = hclge_pfc_tx_stats_get(hdev, requests);
 287         if (ret)
 288                 return ret;
 289
 290         ret = hclge_pfc_rx_stats_get(hdev, indications);
 291         if (ret)
 292                 return ret;
 293
 294         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
 295                 pfc->requests[i] = requests[i];
 296                 pfc->indications[i] = indications[i];
 297         }
 298         return 0;
 299 }
 300
 301 static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 302 {
 303         struct hclge_vport *vport = hclge_get_vport(h);
 304         struct net_device *netdev = h->kinfo.netdev;
 305         struct hclge_dev *hdev = vport->back;
 306         u8 i, j, pfc_map, *prio_tc;
 307         int ret;
 308
 309         if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
 310             hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 311                 return -EINVAL;
 312
 313         if (pfc->pfc_en == hdev->tm_info.pfc_en)
 314                 return 0;
 315
 316         prio_tc = hdev->tm_info.prio_tc;
 317         pfc_map = 0;
 318
 319         for (i = 0; i < hdev->tm_info.num_tc; i++) {
 320                 for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
 321                         if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) {
 322                                 pfc_map |= BIT(i);
 323                                 break;
 324                         }
 325                 }
 326         }
 327
 328         hdev->tm_info.hw_pfc_map = pfc_map;
 329         hdev->tm_info.pfc_en = pfc->pfc_en;
 330
 331         netif_dbg(h, drv, netdev,
 332                   "set pfc: pfc_en=%x, pfc_map=%x, num_tc=%u\n",
 333                   pfc->pfc_en, pfc_map, hdev->tm_info.num_tc);
 334
 335         hclge_tm_pfc_info_update(hdev);
 336
 337         ret = hclge_pause_setup_hw(hdev, false);
 338         if (ret)
 339                 return ret;
 340
 341         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
 342         if (ret)
 343                 return ret;
 344
 345         ret = hclge_buffer_alloc(hdev);
 346         if (ret) {
 347                 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 348                 return ret;
 349         }
 350
 351         return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 352 }
 353
 354 /* DCBX configuration */
 355 static u8 hclge_getdcbx(struct hnae3_handle *h)
 356 {
 357         struct hclge_vport *vport = hclge_get_vport(h);
 358         struct hclge_dev *hdev = vport->back;
 359
 360         if (hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 361                 return 0;
 362
 363         return hdev->dcbx_cap;
 364 }
 365
 366 static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode)
 367 {
 368         struct hclge_vport *vport = hclge_get_vport(h);
 369         struct net_device *netdev = h->kinfo.netdev;
 370         struct hclge_dev *hdev = vport->back;
 371
 372         netif_dbg(h, drv, netdev, "set dcbx: mode=%u\n", mode);
 373
 374         /* No support for LLD_MANAGED modes or CEE */
 375         if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
 376             (mode & DCB_CAP_DCBX_VER_CEE) ||
 377             !(mode & DCB_CAP_DCBX_HOST))
 378                 return 1;
 379
 380         hdev->dcbx_cap = mode;
 381
 382         return 0;
 383 }
 384
 385 static int hclge_mqprio_qopt_check(struct hclge_dev *hdev,
 386                                    struct tc_mqprio_qopt_offload *mqprio_qopt)
 387 {
 388         u16 queue_sum = 0;
 389         int ret;
 390         int i;
 391
 392         if (!mqprio_qopt->qopt.num_tc) {
 393                 mqprio_qopt->qopt.num_tc = 1;
 394                 return 0;
 395         }
 396
 397         ret = hclge_dcb_common_validate(hdev, mqprio_qopt->qopt.num_tc,
 398                                         mqprio_qopt->qopt.prio_tc_map);
 399         if (ret)
 400                 return ret;
 401
 402         for (i = 0; i < mqprio_qopt->qopt.num_tc; i++) {
 403                 if (!is_power_of_2(mqprio_qopt->qopt.count[i])) {
 404                         dev_err(&hdev->pdev->dev,
 405                                 "qopt queue count must be power of 2\n");
 406                         return -EINVAL;
 407                 }
 408
 409                 if (mqprio_qopt->qopt.count[i] > hdev->pf_rss_size_max) {
 410                         dev_err(&hdev->pdev->dev,
 411                                 "qopt queue count should be no more than %u\n",
 412                                 hdev->pf_rss_size_max);
 413                         return -EINVAL;
 414                 }
 415
 416                 if (mqprio_qopt->qopt.offset[i] != queue_sum) {
 417                         dev_err(&hdev->pdev->dev,
 418                                 "qopt queue offset must start from 0, and being continuous\n");
 419                         return -EINVAL;
 420                 }
 421
 422                 if (mqprio_qopt->min_rate[i] || mqprio_qopt->max_rate[i]) {
 423                         dev_err(&hdev->pdev->dev,
 424                                 "qopt tx_rate is not supported\n");
 425                         return -EOPNOTSUPP;
 426                 }
 427
 428                 queue_sum = mqprio_qopt->qopt.offset[i];
 429                 queue_sum += mqprio_qopt->qopt.count[i];
 430         }
 431         if (hdev->vport[0].alloc_tqps < queue_sum) {
 432                 dev_err(&hdev->pdev->dev,
 433                         "qopt queue count sum should be less than %u\n",
 434                         hdev->vport[0].alloc_tqps);
 435                 return -EINVAL;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static void hclge_sync_mqprio_qopt(struct hnae3_tc_info *tc_info,
 442                                    struct tc_mqprio_qopt_offload *mqprio_qopt)
 443 {
 444         int i;
 445
 446         memset(tc_info, 0, sizeof(*tc_info));
 447         tc_info->num_tc = mqprio_qopt->qopt.num_tc;
 448         memcpy(tc_info->prio_tc, mqprio_qopt->qopt.prio_tc_map,
 449                sizeof_field(struct hnae3_tc_info, prio_tc));
 450         memcpy(tc_info->tqp_count, mqprio_qopt->qopt.count,
 451                sizeof_field(struct hnae3_tc_info, tqp_count));
 452         memcpy(tc_info->tqp_offset, mqprio_qopt->qopt.offset,
 453                sizeof_field(struct hnae3_tc_info, tqp_offset));
 454
 455         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
 456                 set_bit(tc_info->prio_tc[i], &tc_info->tc_en);
 457 }
 458
 459 static int hclge_config_tc(struct hclge_dev *hdev,
 460                            struct hnae3_tc_info *tc_info)
 461 {
 462         int i;
 463
 464         hclge_tm_schd_info_update(hdev, tc_info->num_tc);
 465         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
 466                 hdev->tm_info.prio_tc[i] = tc_info->prio_tc[i];
 467
 468         return hclge_map_update(hdev);
 469 }
 470
 471 /* Set up TC for hardware offloaded mqprio in channel mode */
 472 static int hclge_setup_tc(struct hnae3_handle *h,
 473                           struct tc_mqprio_qopt_offload *mqprio_qopt)
 474 {
 475         struct hclge_vport *vport = hclge_get_vport(h);
 476         struct hnae3_knic_private_info *kinfo;
 477         struct hclge_dev *hdev = vport->back;
 478         struct hnae3_tc_info old_tc_info;
 479         u8 tc = mqprio_qopt->qopt.num_tc;
 480         int ret;
 481
 482         /* if client unregistered, it's not allowed to change
 483          * mqprio configuration, which may cause uninit ring
 484          * fail.
 485          */
 486         if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state))
 487                 return -EBUSY;
 488
 489         if (hdev->flag & HCLGE_FLAG_DCB_ENABLE)
 490                 return -EINVAL;
 491
 492         ret = hclge_mqprio_qopt_check(hdev, mqprio_qopt);
 493         if (ret) {
 494                 dev_err(&hdev->pdev->dev,
 495                         "failed to check mqprio qopt params, ret = %d\n", ret);
 496                 return ret;
 497         }
 498
 499         ret = hclge_notify_down_uinit(hdev);
 500         if (ret)
 501                 return ret;
 502
 503         kinfo = &vport->nic.kinfo;
 504         memcpy(&old_tc_info, &kinfo->tc_info, sizeof(old_tc_info));
 505         hclge_sync_mqprio_qopt(&kinfo->tc_info, mqprio_qopt);
 506         kinfo->tc_info.mqprio_active = tc > 0;
 507
 508         ret = hclge_config_tc(hdev, &kinfo->tc_info);
 509         if (ret)
 510                 goto err_out;
 511
 512         hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
 513
 514         if (tc > 1)
 515                 hdev->flag |= HCLGE_FLAG_MQPRIO_ENABLE;
 516         else
 517                 hdev->flag &= ~HCLGE_FLAG_MQPRIO_ENABLE;
 518
 519         return hclge_notify_init_up(hdev);
 520
 521 err_out:
 522         /* roll-back */
 523         memcpy(&kinfo->tc_info, &old_tc_info, sizeof(old_tc_info));
 524         if (hclge_config_tc(hdev, &kinfo->tc_info))
 525                 dev_err(&hdev->pdev->dev,
 526                         "failed to roll back tc configuration\n");
 527
 528         hclge_notify_init_up(hdev);
 529
 530         return ret;
 531 }
 532
 533 static const struct hnae3_dcb_ops hns3_dcb_ops = {
 534         .ieee_getets    = hclge_ieee_getets,
 535         .ieee_setets    = hclge_ieee_setets,
 536         .ieee_getpfc    = hclge_ieee_getpfc,
 537         .ieee_setpfc    = hclge_ieee_setpfc,
 538         .getdcbx        = hclge_getdcbx,
 539         .setdcbx        = hclge_setdcbx,
 540         .setup_tc       = hclge_setup_tc,
 541 };
 542
 543 void hclge_dcb_ops_set(struct hclge_dev *hdev)
 544 {
 545         struct hclge_vport *vport = hdev->vport;
 546         struct hnae3_knic_private_info *kinfo;
 547
 548         /* Hdev does not support DCB or vport is
 549          * not a pf, then dcb_ops is not set.
 550          */
 551         if (!hnae3_dev_dcb_supported(hdev) ||
 552             vport->vport_id != 0)
 553                 return;
 554
 555         kinfo = &vport->nic.kinfo;
 556         kinfo->dcb_ops = &hns3_dcb_ops;
 557         hdev->dcbx_cap = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_HOST;
 558 }