drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #ifndef __HCLGE_CMD_H
   5 #define __HCLGE_CMD_H
   6 #include <linux/types.h>
   7 #include <linux/io.h>
   8 #include <linux/etherdevice.h>
   9 #include "hnae3.h"
  10
  11 #define HCLGE_CMDQ_TX_TIMEOUT           30000
  12 #define HCLGE_DESC_DATA_LEN             6
  13
  14 struct hclge_dev;
  15 struct hclge_desc {
  16         __le16 opcode;
  17
  18 #define HCLGE_CMDQ_RX_INVLD_B           0
  19 #define HCLGE_CMDQ_RX_OUTVLD_B          1
  20
  21         __le16 flag;
  22         __le16 retval;
  23         __le16 rsv;
  24         __le32 data[HCLGE_DESC_DATA_LEN];
  25 };
  26
  27 struct hclge_cmq_ring {
  28         dma_addr_t desc_dma_addr;
  29         struct hclge_desc *desc;
  30         struct hclge_dev *dev;
  31         u32 head;
  32         u32 tail;
  33
  34         u16 buf_size;
  35         u16 desc_num;
  36         int next_to_use;
  37         int next_to_clean;
  38         u8 ring_type; /* cmq ring type */
  39         spinlock_t lock; /* Command queue lock */
  40 };
  41
  42 enum hclge_cmd_return_status {
  43         HCLGE_CMD_EXEC_SUCCESS  = 0,
  44         HCLGE_CMD_NO_AUTH       = 1,
  45         HCLGE_CMD_NOT_SUPPORTED = 2,
  46         HCLGE_CMD_QUEUE_FULL    = 3,
  47         HCLGE_CMD_NEXT_ERR      = 4,
  48         HCLGE_CMD_UNEXE_ERR     = 5,
  49         HCLGE_CMD_PARA_ERR      = 6,
  50         HCLGE_CMD_RESULT_ERR    = 7,
  51         HCLGE_CMD_TIMEOUT       = 8,
  52         HCLGE_CMD_HILINK_ERR    = 9,
  53         HCLGE_CMD_QUEUE_ILLEGAL = 10,
  54         HCLGE_CMD_INVALID       = 11,
  55 };
  56
  57 enum hclge_cmd_status {
  58         HCLGE_STATUS_SUCCESS    = 0,
  59         HCLGE_ERR_CSQ_FULL      = -1,
  60         HCLGE_ERR_CSQ_TIMEOUT   = -2,
  61         HCLGE_ERR_CSQ_ERROR     = -3,
  62 };
  63
  64 struct hclge_misc_vector {
  65         u8 __iomem *addr;
  66         int vector_irq;
  67         char name[HNAE3_INT_NAME_LEN];
  68 };
  69
  70 struct hclge_cmq {
  71         struct hclge_cmq_ring csq;
  72         struct hclge_cmq_ring crq;
  73         u16 tx_timeout;
  74         enum hclge_cmd_status last_status;
  75 };
  76
  77 #define HCLGE_CMD_FLAG_IN       BIT(0)
  78 #define HCLGE_CMD_FLAG_OUT      BIT(1)
  79 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
  80 #define HCLGE_CMD_FLAG_WR       BIT(3)
  81 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
  82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  83
  84 enum hclge_opcode_type {
  85         /* Generic commands */
  86         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  87         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  88         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  89         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  90         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  91         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
  92         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
  93         HCLGE_OPC_PF_RST_DONE           = 0x0026,
  94         HCLGE_OPC_QUERY_VF_RST_RDY      = 0x0027,
  95
  96         HCLGE_OPC_STATS_64_BIT          = 0x0030,
  97         HCLGE_OPC_STATS_32_BIT          = 0x0031,
  98         HCLGE_OPC_STATS_MAC             = 0x0032,
  99         HCLGE_OPC_QUERY_MAC_REG_NUM     = 0x0033,
 100         HCLGE_OPC_STATS_MAC_ALL         = 0x0034,
 101
 102         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
 103         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
 104         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
 105         HCLGE_OPC_DFX_BD_NUM            = 0x0043,
 106         HCLGE_OPC_DFX_BIOS_COMMON_REG   = 0x0044,
 107         HCLGE_OPC_DFX_SSU_REG_0         = 0x0045,
 108         HCLGE_OPC_DFX_SSU_REG_1         = 0x0046,
 109         HCLGE_OPC_DFX_IGU_EGU_REG       = 0x0047,
 110         HCLGE_OPC_DFX_RPU_REG_0         = 0x0048,
 111         HCLGE_OPC_DFX_RPU_REG_1         = 0x0049,
 112         HCLGE_OPC_DFX_NCSI_REG          = 0x004A,
 113         HCLGE_OPC_DFX_RTC_REG           = 0x004B,
 114         HCLGE_OPC_DFX_PPP_REG           = 0x004C,
 115         HCLGE_OPC_DFX_RCB_REG           = 0x004D,
 116         HCLGE_OPC_DFX_TQP_REG           = 0x004E,
 117         HCLGE_OPC_DFX_SSU_REG_2         = 0x004F,
 118
 119         HCLGE_OPC_QUERY_DEV_SPECS       = 0x0050,
 120
 121         /* MAC command */
 122         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
 123         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
 124         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 125         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 126         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 127         HCLGE_OPC_QUERY_MAC_TNL_INT     = 0x0310,
 128         HCLGE_OPC_MAC_TNL_INT_EN        = 0x0311,
 129         HCLGE_OPC_CLEAR_MAC_TNL_INT     = 0x0312,
 130         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
 131         HCLGE_OPC_CONFIG_FEC_MODE       = 0x031A,
 132
 133         /* PFC/Pause commands */
 134         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 135         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 136         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 137         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 138         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 139         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 140         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 141         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 142         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 143         HCLGE_OPC_QOS_MAP               = 0x070A,
 144
 145         /* ETS/scheduler commands */
 146         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 147         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 148         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 149         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 150         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 151         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 152         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 153         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 154         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 155         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 156         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 157         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 158         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 159         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 160         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 161         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 162         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 163         HCLGE_OPC_TM_NODES              = 0x0816,
 164         HCLGE_OPC_ETS_TC_WEIGHT         = 0x0843,
 165         HCLGE_OPC_QSET_DFX_STS          = 0x0844,
 166         HCLGE_OPC_PRI_DFX_STS           = 0x0845,
 167         HCLGE_OPC_PG_DFX_STS            = 0x0846,
 168         HCLGE_OPC_PORT_DFX_STS          = 0x0847,
 169         HCLGE_OPC_SCH_NQ_CNT            = 0x0848,
 170         HCLGE_OPC_SCH_RQ_CNT            = 0x0849,
 171         HCLGE_OPC_TM_INTERNAL_STS       = 0x0850,
 172         HCLGE_OPC_TM_INTERNAL_CNT       = 0x0851,
 173         HCLGE_OPC_TM_INTERNAL_STS_1     = 0x0852,
 174
 175         /* Packet buffer allocate commands */
 176         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 177         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 178         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 179         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 180         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 181         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 182
 183         /* TQP management command */
 184         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 185
 186         /* TQP commands */
 187         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 188         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 189         HCLGE_OPC_QUERY_TX_STATS        = 0x0B03,
 190         HCLGE_OPC_TQP_TX_QUEUE_TC       = 0x0B04,
 191         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 192         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 193         HCLGE_OPC_QUERY_RX_STATS        = 0x0B13,
 194         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 195         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 196         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 197         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 198
 199         /* PPU commands */
 200         HCLGE_OPC_PPU_PF_OTHER_INT_DFX  = 0x0B4A,
 201
 202         /* TSO command */
 203         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 204         HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
 205
 206         /* RSS commands */
 207         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 208         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 209         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 210         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 211
 212         /* Promisuous mode command */
 213         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 214
 215         /* Vlan offload commands */
 216         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 217         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 218
 219         /* Interrupts commands */
 220         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 221         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 222
 223         /* MAC commands */
 224         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 225         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 226         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 227         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 228         HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
 229         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 230         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 231
 232         /* MAC VLAN commands */
 233         HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
 234
 235         /* VLAN commands */
 236         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 237         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 238         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 239
 240         /* Flow Director commands */
 241         HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
 242         HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
 243         HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
 244         HCLGE_OPC_FD_TCAM_OP            = 0x1203,
 245         HCLGE_OPC_FD_AD_OP              = 0x1204,
 246
 247         /* MDIO command */
 248         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 249
 250         /* QCN commands */
 251         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 252         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 253         HCLGE_OPC_QCN_SHAPPING_CFG      = 0x1A03,
 254         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 255         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 256         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 257         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 258         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 259
 260         /* Mailbox command */
 261         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 262
 263         /* Led command */
 264         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 265
 266         /* NCL config command */
 267         HCLGE_OPC_QUERY_NCL_CONFIG      = 0x7011,
 268
 269         /* M7 stats command */
 270         HCLGE_OPC_M7_STATS_BD           = 0x7012,
 271         HCLGE_OPC_M7_STATS_INFO         = 0x7013,
 272         HCLGE_OPC_M7_COMPAT_CFG         = 0x701A,
 273
 274         /* SFP command */
 275         HCLGE_OPC_GET_SFP_EEPROM        = 0x7100,
 276         HCLGE_OPC_GET_SFP_EXIST         = 0x7101,
 277         HCLGE_OPC_GET_SFP_INFO          = 0x7104,
 278
 279         /* Error INT commands */
 280         HCLGE_MAC_COMMON_INT_EN         = 0x030E,
 281         HCLGE_TM_SCH_ECC_INT_EN         = 0x0829,
 282         HCLGE_SSU_ECC_INT_CMD           = 0x0989,
 283         HCLGE_SSU_COMMON_INT_CMD        = 0x098C,
 284         HCLGE_PPU_MPF_ECC_INT_CMD       = 0x0B40,
 285         HCLGE_PPU_MPF_OTHER_INT_CMD     = 0x0B41,
 286         HCLGE_PPU_PF_OTHER_INT_CMD      = 0x0B42,
 287         HCLGE_COMMON_ECC_INT_CFG        = 0x1505,
 288         HCLGE_QUERY_RAS_INT_STS_BD_NUM  = 0x1510,
 289         HCLGE_QUERY_CLEAR_MPF_RAS_INT   = 0x1511,
 290         HCLGE_QUERY_CLEAR_PF_RAS_INT    = 0x1512,
 291         HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
 292         HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT      = 0x1514,
 293         HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT       = 0x1515,
 294         HCLGE_CONFIG_ROCEE_RAS_INT_EN   = 0x1580,
 295         HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
 296         HCLGE_ROCEE_PF_RAS_INT_CMD      = 0x1584,
 297         HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD      = 0x1585,
 298         HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD      = 0x1586,
 299         HCLGE_IGU_EGU_TNL_INT_EN        = 0x1803,
 300         HCLGE_IGU_COMMON_INT_EN         = 0x1806,
 301         HCLGE_TM_QCN_MEM_INT_CFG        = 0x1A14,
 302         HCLGE_PPP_CMD0_INT_CMD          = 0x2100,
 303         HCLGE_PPP_CMD1_INT_CMD          = 0x2101,
 304         HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
 305         HCLGE_NCSI_INT_EN               = 0x2401,
 306
 307         /* PHY command */
 308         HCLGE_OPC_PHY_LINK_KSETTING     = 0x7025,
 309 };
 310
 311 #define HCLGE_TQP_REG_OFFSET            0x80000
 312 #define HCLGE_TQP_REG_SIZE              0x200
 313
 314 #define HCLGE_TQP_MAX_SIZE_DEV_V2       1024
 315 #define HCLGE_TQP_EXT_REG_OFFSET        0x100
 316
 317 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 318 #define HCLGE_RCB_INIT_FLAG_EN_B        0
 319 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
 320 struct hclge_config_rcb_init_cmd {
 321         __le16 rcb_init_flag;
 322         u8 rsv[22];
 323 };
 324
 325 struct hclge_tqp_map_cmd {
 326         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 327         u8 tqp_vf;      /* VF id */
 328 #define HCLGE_TQP_MAP_TYPE_PF           0
 329 #define HCLGE_TQP_MAP_TYPE_VF           1
 330 #define HCLGE_TQP_MAP_TYPE_B            0
 331 #define HCLGE_TQP_MAP_EN_B              1
 332         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 333         __le16 tqp_vid; /* Virtual id in this pf/vf */
 334         u8 rsv[18];
 335 };
 336
 337 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 338
 339 enum hclge_int_type {
 340         HCLGE_INT_TX,
 341         HCLGE_INT_RX,
 342         HCLGE_INT_EVENT,
 343 };
 344
 345 struct hclge_ctrl_vector_chain_cmd {
 346 #define HCLGE_VECTOR_ID_L_S     0
 347 #define HCLGE_VECTOR_ID_L_M     GENMASK(7, 0)
 348         u8 int_vector_id_l;
 349         u8 int_cause_num;
 350 #define HCLGE_INT_TYPE_S        0
 351 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 352 #define HCLGE_TQP_ID_S          2
 353 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
 354 #define HCLGE_INT_GL_IDX_S      13
 355 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 356         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 357         u8 vfid;
 358 #define HCLGE_VECTOR_ID_H_S     8
 359 #define HCLGE_VECTOR_ID_H_M     GENMASK(15, 8)
 360         u8 int_vector_id_h;
 361 };
 362
 363 #define HCLGE_MAX_TC_NUM                8
 364 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 365 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 366 struct hclge_tx_buff_alloc_cmd {
 367         __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
 368         u8 tx_buff_rsv[8];
 369 };
 370
 371 struct hclge_rx_priv_buff_cmd {
 372         __le16 buf_num[HCLGE_MAX_TC_NUM];
 373         __le16 shared_buf;
 374         u8 rsv[6];
 375 };
 376
 377 enum HCLGE_CAP_BITS {
 378         HCLGE_CAP_UDP_GSO_B,
 379         HCLGE_CAP_QB_B,
 380         HCLGE_CAP_FD_FORWARD_TC_B,
 381         HCLGE_CAP_PTP_B,
 382         HCLGE_CAP_INT_QL_B,
 383         HCLGE_CAP_HW_TX_CSUM_B,
 384         HCLGE_CAP_TX_PUSH_B,
 385         HCLGE_CAP_PHY_IMP_B,
 386         HCLGE_CAP_TQP_TXRX_INDEP_B,
 387         HCLGE_CAP_HW_PAD_B,
 388         HCLGE_CAP_STASH_B,
 389         HCLGE_CAP_UDP_TUNNEL_CSUM_B,
 390         HCLGE_CAP_FEC_B = 13,
 391         HCLGE_CAP_PAUSE_B = 14,
 392 };
 393
 394 enum HCLGE_API_CAP_BITS {
 395         HCLGE_API_CAP_FLEX_RSS_TBL_B,
 396 };
 397
 398 #define HCLGE_QUERY_CAP_LENGTH          3
 399 struct hclge_query_version_cmd {
 400         __le32 firmware;
 401         __le32 hardware;
 402         __le32 api_caps;
 403         __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
 404 };
 405
 406 #define HCLGE_RX_PRIV_EN_B      15
 407 #define HCLGE_TC_NUM_ONE_DESC   4
 408 struct hclge_priv_wl {
 409         __le16 high;
 410         __le16 low;
 411 };
 412
 413 struct hclge_rx_priv_wl_buf {
 414         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 415 };
 416
 417 struct hclge_rx_com_thrd {
 418         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 419 };
 420
 421 struct hclge_rx_com_wl {
 422         struct hclge_priv_wl com_wl;
 423 };
 424
 425 struct hclge_waterline {
 426         u32 low;
 427         u32 high;
 428 };
 429
 430 struct hclge_tc_thrd {
 431         u32 low;
 432         u32 high;
 433 };
 434
 435 struct hclge_priv_buf {
 436         struct hclge_waterline wl;      /* Waterline for low and high*/
 437         u32 buf_size;   /* TC private buffer size */
 438         u32 tx_buf_size;
 439         u32 enable;     /* Enable TC private buffer or not */
 440 };
 441
 442 struct hclge_shared_buf {
 443         struct hclge_waterline self;
 444         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 445         u32 buf_size;
 446 };
 447
 448 struct hclge_pkt_buf_alloc {
 449         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 450         struct hclge_shared_buf s_buf;
 451 };
 452
 453 #define HCLGE_RX_COM_WL_EN_B    15
 454 struct hclge_rx_com_wl_buf_cmd {
 455         __le16 high_wl;
 456         __le16 low_wl;
 457         u8 rsv[20];
 458 };
 459
 460 #define HCLGE_RX_PKT_EN_B       15
 461 struct hclge_rx_pkt_buf_cmd {
 462         __le16 high_pkt;
 463         __le16 low_pkt;
 464         u8 rsv[20];
 465 };
 466
 467 #define HCLGE_PF_STATE_DONE_B   0
 468 #define HCLGE_PF_STATE_MAIN_B   1
 469 #define HCLGE_PF_STATE_BOND_B   2
 470 #define HCLGE_PF_STATE_MAC_N_B  6
 471 #define HCLGE_PF_MAC_NUM_MASK   0x3
 472 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 473 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 474 #define HCLGE_VF_RST_STATUS_CMD 4
 475
 476 struct hclge_func_status_cmd {
 477         __le32  vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
 478         u8 pf_state;
 479         u8 mac_id;
 480         u8 rsv1;
 481         u8 pf_cnt_in_mac;
 482         u8 pf_num;
 483         u8 vf_num;
 484         u8 rsv[2];
 485 };
 486
 487 struct hclge_pf_res_cmd {
 488         __le16 tqp_num;
 489         __le16 buf_size;
 490         __le16 msixcap_localid_ba_nic;
 491         __le16 msixcap_localid_number_nic;
 492         __le16 pf_intr_vector_number_roce;
 493         __le16 pf_own_fun_number;
 494         __le16 tx_buf_size;
 495         __le16 dv_buf_size;
 496         __le16 ext_tqp_num;
 497         u8 rsv[6];
 498 };
 499
 500 #define HCLGE_CFG_OFFSET_S      0
 501 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 502 #define HCLGE_CFG_RD_LEN_S      24
 503 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 504 #define HCLGE_CFG_RD_LEN_BYTES  16
 505 #define HCLGE_CFG_RD_LEN_UNIT   4
 506
 507 #define HCLGE_CFG_VMDQ_S        0
 508 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
 509 #define HCLGE_CFG_TC_NUM_S      8
 510 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 511 #define HCLGE_CFG_TQP_DESC_N_S  16
 512 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 513 #define HCLGE_CFG_PHY_ADDR_S    0
 514 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 515 #define HCLGE_CFG_MEDIA_TP_S    8
 516 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 517 #define HCLGE_CFG_RX_BUF_LEN_S  16
 518 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 519 #define HCLGE_CFG_MAC_ADDR_H_S  0
 520 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 521 #define HCLGE_CFG_DEFAULT_SPEED_S       16
 522 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 523 #define HCLGE_CFG_RSS_SIZE_S    24
 524 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 525 #define HCLGE_CFG_SPEED_ABILITY_S       0
 526 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 527 #define HCLGE_CFG_SPEED_ABILITY_EXT_S   10
 528 #define HCLGE_CFG_SPEED_ABILITY_EXT_M   GENMASK(15, 10)
 529 #define HCLGE_CFG_UMV_TBL_SPACE_S       16
 530 #define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
 531 #define HCLGE_CFG_PF_RSS_SIZE_S         0
 532 #define HCLGE_CFG_PF_RSS_SIZE_M         GENMASK(3, 0)
 533
 534 #define HCLGE_CFG_CMD_CNT               4
 535
 536 struct hclge_cfg_param_cmd {
 537         __le32 offset;
 538         __le32 rsv;
 539         __le32 param[HCLGE_CFG_CMD_CNT];
 540 };
 541
 542 #define HCLGE_MAC_MODE          0x0
 543 #define HCLGE_DESC_NUM          0x40
 544
 545 #define HCLGE_ALLOC_VALID_B     0
 546 struct hclge_vf_num_cmd {
 547         u8 alloc_valid;
 548         u8 rsv[23];
 549 };
 550
 551 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 552 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 553 #define HCLGE_RSS_HASH_KEY_NUM          16
 554 struct hclge_rss_config_cmd {
 555         u8 hash_config;
 556         u8 rsv[7];
 557         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 558 };
 559
 560 struct hclge_rss_input_tuple_cmd {
 561         u8 ipv4_tcp_en;
 562         u8 ipv4_udp_en;
 563         u8 ipv4_sctp_en;
 564         u8 ipv4_fragment_en;
 565         u8 ipv6_tcp_en;
 566         u8 ipv6_udp_en;
 567         u8 ipv6_sctp_en;
 568         u8 ipv6_fragment_en;
 569         u8 rsv[16];
 570 };
 571
 572 #define HCLGE_RSS_CFG_TBL_SIZE  16
 573 #define HCLGE_RSS_CFG_TBL_SIZE_H        4
 574 #define HCLGE_RSS_CFG_TBL_BW_H          2U
 575 #define HCLGE_RSS_CFG_TBL_BW_L          8U
 576
 577 struct hclge_rss_indirection_table_cmd {
 578         __le16 start_table_index;
 579         __le16 rss_set_bitmap;
 580         u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H];
 581         u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE];
 582 };
 583
 584 #define HCLGE_RSS_TC_OFFSET_S           0
 585 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(10, 0)
 586 #define HCLGE_RSS_TC_SIZE_MSB_B         11
 587 #define HCLGE_RSS_TC_SIZE_S             12
 588 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 589 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET    3
 590 #define HCLGE_RSS_TC_VALID_B            15
 591 struct hclge_rss_tc_mode_cmd {
 592         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 593         u8 rsv[8];
 594 };
 595
 596 #define HCLGE_LINK_STATUS_UP_B  0
 597 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
 598 struct hclge_link_status_cmd {
 599         u8 status;
 600         u8 rsv[23];
 601 };
 602
 603 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */
 604 #define HCLGE_PROMISC_EN_UC     1
 605 #define HCLGE_PROMISC_EN_MC     2
 606 #define HCLGE_PROMISC_EN_BC     3
 607 #define HCLGE_PROMISC_TX_EN     4
 608 #define HCLGE_PROMISC_RX_EN     5
 609
 610 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */
 611 #define HCLGE_PROMISC_UC_RX_EN  2
 612 #define HCLGE_PROMISC_MC_RX_EN  3
 613 #define HCLGE_PROMISC_BC_RX_EN  4
 614 #define HCLGE_PROMISC_UC_TX_EN  5
 615 #define HCLGE_PROMISC_MC_TX_EN  6
 616 #define HCLGE_PROMISC_BC_TX_EN  7
 617
 618 struct hclge_promisc_cfg_cmd {
 619         u8 promisc;
 620         u8 vf_id;
 621         u8 extend_promisc;
 622         u8 rsv0[21];
 623 };
 624
 625 enum hclge_promisc_type {
 626         HCLGE_UNICAST   = 1,
 627         HCLGE_MULTICAST = 2,
 628         HCLGE_BROADCAST = 3,
 629 };
 630
 631 #define HCLGE_MAC_TX_EN_B       6
 632 #define HCLGE_MAC_RX_EN_B       7
 633 #define HCLGE_MAC_PAD_TX_B      11
 634 #define HCLGE_MAC_PAD_RX_B      12
 635 #define HCLGE_MAC_1588_TX_B     13
 636 #define HCLGE_MAC_1588_RX_B     14
 637 #define HCLGE_MAC_APP_LP_B      15
 638 #define HCLGE_MAC_LINE_LP_B     16
 639 #define HCLGE_MAC_FCS_TX_B      17
 640 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 641 #define HCLGE_MAC_RX_FCS_STRIP_B        19
 642 #define HCLGE_MAC_RX_FCS_B      20
 643 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 644 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 645
 646 struct hclge_config_mac_mode_cmd {
 647         __le32 txrx_pad_fcs_loop_en;
 648         u8 rsv[20];
 649 };
 650
 651 struct hclge_pf_rst_sync_cmd {
 652 #define HCLGE_PF_RST_ALL_VF_RDY_B       0
 653         u8 all_vf_ready;
 654         u8 rsv[23];
 655 };
 656
 657 #define HCLGE_CFG_SPEED_S               0
 658 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 659
 660 #define HCLGE_CFG_DUPLEX_B              7
 661 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 662
 663 struct hclge_config_mac_speed_dup_cmd {
 664         u8 speed_dup;
 665
 666 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 667         u8 mac_change_fec_en;
 668         u8 rsv[22];
 669 };
 670
 671 #define HCLGE_TQP_ENABLE_B              0
 672
 673 #define HCLGE_MAC_CFG_AN_EN_B           0
 674 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
 675 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 676 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 677 #define HCLGE_MAC_CFG_AN_RST_B          4
 678
 679 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 680
 681 struct hclge_config_auto_neg_cmd {
 682         __le32  cfg_an_cmd_flag;
 683         u8      rsv[20];
 684 };
 685
 686 struct hclge_sfp_info_cmd {
 687         __le32 speed;
 688         u8 query_type; /* 0: sfp speed, 1: active speed */
 689         u8 active_fec;
 690         u8 autoneg; /* autoneg state */
 691         u8 autoneg_ability; /* whether support autoneg */
 692         __le32 speed_ability; /* speed ability for current media */
 693         __le32 module_type;
 694         u8 rsv[8];
 695 };
 696
 697 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B     0
 698 #define HCLGE_MAC_CFG_FEC_MODE_S        1
 699 #define HCLGE_MAC_CFG_FEC_MODE_M        GENMASK(3, 1)
 700 #define HCLGE_MAC_CFG_FEC_SET_DEF_B     0
 701 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B     1
 702
 703 #define HCLGE_MAC_FEC_OFF               0
 704 #define HCLGE_MAC_FEC_BASER             1
 705 #define HCLGE_MAC_FEC_RS                2
 706 struct hclge_config_fec_cmd {
 707         u8 fec_mode;
 708         u8 default_config;
 709         u8 rsv[22];
 710 };
 711
 712 #define HCLGE_MAC_UPLINK_PORT           0x100
 713
 714 struct hclge_config_max_frm_size_cmd {
 715         __le16  max_frm_size;
 716         u8      min_frm_size;
 717         u8      rsv[21];
 718 };
 719
 720 enum hclge_mac_vlan_tbl_opcode {
 721         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 722         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 723         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 724         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 725 };
 726
 727 enum hclge_mac_vlan_add_resp_code {
 728         HCLGE_ADD_UC_OVERFLOW = 2,      /* ADD failed for UC overflow */
 729         HCLGE_ADD_MC_OVERFLOW,          /* ADD failed for MC overflow */
 730 };
 731
 732 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
 733 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
 734 #define HCLGE_MAC_EPORT_SW_EN_B         12
 735 #define HCLGE_MAC_EPORT_TYPE_B          11
 736 #define HCLGE_MAC_EPORT_VFID_S          3
 737 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 738 #define HCLGE_MAC_EPORT_PFID_S          0
 739 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 740 struct hclge_mac_vlan_tbl_entry_cmd {
 741         u8      flags;
 742         u8      resp_code;
 743         __le16  vlan_tag;
 744         __le32  mac_addr_hi32;
 745         __le16  mac_addr_lo16;
 746         __le16  rsv1;
 747         u8      entry_type;
 748         u8      mc_mac_en;
 749         __le16  egress_port;
 750         __le16  egress_queue;
 751         u8      rsv2[6];
 752 };
 753
 754 #define HCLGE_UMV_SPC_ALC_B     0
 755 struct hclge_umv_spc_alc_cmd {
 756         u8 allocate;
 757         u8 rsv1[3];
 758         __le32 space_size;
 759         u8 rsv2[16];
 760 };
 761
 762 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 763 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 764 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 765
 766 struct hclge_mac_mgr_tbl_entry_cmd {
 767         u8      flags;
 768         u8      resp_code;
 769         __le16  vlan_tag;
 770         u8      mac_addr[ETH_ALEN];
 771         __le16  rsv1;
 772         __le16  ethter_type;
 773         __le16  egress_port;
 774         __le16  egress_queue;
 775         u8      sw_port_id_aware;
 776         u8      rsv2;
 777         u8      i_port_bitmap;
 778         u8      i_port_direction;
 779         u8      rsv3[2];
 780 };
 781
 782 struct hclge_vlan_filter_ctrl_cmd {
 783         u8 vlan_type;
 784         u8 vlan_fe;
 785         u8 rsv1[2];
 786         u8 vf_id;
 787         u8 rsv2[19];
 788 };
 789
 790 #define HCLGE_VLAN_ID_OFFSET_STEP       160
 791 #define HCLGE_VLAN_BYTE_SIZE            8
 792 #define HCLGE_VLAN_OFFSET_BITMAP \
 793         (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
 794
 795 struct hclge_vlan_filter_pf_cfg_cmd {
 796         u8 vlan_offset;
 797         u8 vlan_cfg;
 798         u8 rsv[2];
 799         u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
 800 };
 801
 802 #define HCLGE_MAX_VF_BYTES  16
 803
 804 struct hclge_vlan_filter_vf_cfg_cmd {
 805         __le16 vlan_id;
 806         u8  resp_code;
 807         u8  rsv;
 808         u8  vlan_cfg;
 809         u8  rsv1[3];
 810         u8  vf_bitmap[HCLGE_MAX_VF_BYTES];
 811 };
 812
 813 #define HCLGE_SWITCH_ANTI_SPOOF_B       0U
 814 #define HCLGE_SWITCH_ALW_LPBK_B         1U
 815 #define HCLGE_SWITCH_ALW_LCL_LPBK_B     2U
 816 #define HCLGE_SWITCH_ALW_DST_OVRD_B     3U
 817 #define HCLGE_SWITCH_NO_MASK            0x0
 818 #define HCLGE_SWITCH_ANTI_SPOOF_MASK    0xFE
 819 #define HCLGE_SWITCH_ALW_LPBK_MASK      0xFD
 820 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK  0xFB
 821 #define HCLGE_SWITCH_LW_DST_OVRD_MASK   0xF7
 822
 823 struct hclge_mac_vlan_switch_cmd {
 824         u8 roce_sel;
 825         u8 rsv1[3];
 826         __le32 func_id;
 827         u8 switch_param;
 828         u8 rsv2[3];
 829         u8 param_mask;
 830         u8 rsv3[11];
 831 };
 832
 833 enum hclge_mac_vlan_cfg_sel {
 834         HCLGE_MAC_VLAN_NIC_SEL = 0,
 835         HCLGE_MAC_VLAN_ROCE_SEL,
 836 };
 837
 838 #define HCLGE_ACCEPT_TAG1_B             0
 839 #define HCLGE_ACCEPT_UNTAG1_B           1
 840 #define HCLGE_PORT_INS_TAG1_EN_B        2
 841 #define HCLGE_PORT_INS_TAG2_EN_B        3
 842 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
 843 #define HCLGE_ACCEPT_TAG2_B             5
 844 #define HCLGE_ACCEPT_UNTAG2_B           6
 845 #define HCLGE_TAG_SHIFT_MODE_EN_B       7
 846 #define HCLGE_VF_NUM_PER_BYTE           8
 847
 848 struct hclge_vport_vtag_tx_cfg_cmd {
 849         u8 vport_vlan_cfg;
 850         u8 vf_offset;
 851         u8 rsv1[2];
 852         __le16 def_vlan_tag1;
 853         __le16 def_vlan_tag2;
 854         u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
 855         u8 rsv2[8];
 856 };
 857
 858 #define HCLGE_REM_TAG1_EN_B             0
 859 #define HCLGE_REM_TAG2_EN_B             1
 860 #define HCLGE_SHOW_TAG1_EN_B            2
 861 #define HCLGE_SHOW_TAG2_EN_B            3
 862 #define HCLGE_DISCARD_TAG1_EN_B         5
 863 #define HCLGE_DISCARD_TAG2_EN_B         6
 864 struct hclge_vport_vtag_rx_cfg_cmd {
 865         u8 vport_vlan_cfg;
 866         u8 vf_offset;
 867         u8 rsv1[6];
 868         u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
 869         u8 rsv2[8];
 870 };
 871
 872 struct hclge_tx_vlan_type_cfg_cmd {
 873         __le16 ot_vlan_type;
 874         __le16 in_vlan_type;
 875         u8 rsv[20];
 876 };
 877
 878 struct hclge_rx_vlan_type_cfg_cmd {
 879         __le16 ot_fst_vlan_type;
 880         __le16 ot_sec_vlan_type;
 881         __le16 in_fst_vlan_type;
 882         __le16 in_sec_vlan_type;
 883         u8 rsv[16];
 884 };
 885
 886 struct hclge_cfg_com_tqp_queue_cmd {
 887         __le16 tqp_id;
 888         __le16 stream_id;
 889         u8 enable;
 890         u8 rsv[19];
 891 };
 892
 893 struct hclge_cfg_tx_queue_pointer_cmd {
 894         __le16 tqp_id;
 895         __le16 tx_tail;
 896         __le16 tx_head;
 897         __le16 fbd_num;
 898         __le16 ring_offset;
 899         u8 rsv[14];
 900 };
 901
 902 #pragma pack(1)
 903 struct hclge_mac_ethertype_idx_rd_cmd {
 904         u8      flags;
 905         u8      resp_code;
 906         __le16  vlan_tag;
 907         u8      mac_addr[ETH_ALEN];
 908         __le16  index;
 909         __le16  ethter_type;
 910         __le16  egress_port;
 911         __le16  egress_queue;
 912         __le16  rev0;
 913         u8      i_port_bitmap;
 914         u8      i_port_direction;
 915         u8      rev1[2];
 916 };
 917
 918 #pragma pack()
 919
 920 #define HCLGE_TSO_MSS_MIN_S     0
 921 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 922
 923 #define HCLGE_TSO_MSS_MAX_S     16
 924 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 925
 926 struct hclge_cfg_tso_status_cmd {
 927         __le16 tso_mss_min;
 928         __le16 tso_mss_max;
 929         u8 rsv[20];
 930 };
 931
 932 #define HCLGE_GRO_EN_B          0
 933 struct hclge_cfg_gro_status_cmd {
 934         u8 gro_en;
 935         u8 rsv[23];
 936 };
 937
 938 #define HCLGE_TSO_MSS_MIN       256
 939 #define HCLGE_TSO_MSS_MAX       9668
 940
 941 #define HCLGE_TQP_RESET_B       0
 942 struct hclge_reset_tqp_queue_cmd {
 943         __le16 tqp_id;
 944         u8 reset_req;
 945         u8 ready_to_reset;
 946         u8 rsv[20];
 947 };
 948
 949 #define HCLGE_CFG_RESET_MAC_B           3
 950 #define HCLGE_CFG_RESET_FUNC_B          7
 951 struct hclge_reset_cmd {
 952         u8 mac_func_reset;
 953         u8 fun_reset_vfid;
 954         u8 rsv[22];
 955 };
 956
 957 #define HCLGE_PF_RESET_DONE_BIT         BIT(0)
 958
 959 struct hclge_pf_rst_done_cmd {
 960         u8 pf_rst_done;
 961         u8 rsv[23];
 962 };
 963
 964 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 965 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
 966 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
 967 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
 968 struct hclge_serdes_lb_cmd {
 969         u8 mask;
 970         u8 enable;
 971         u8 result;
 972         u8 rsv[21];
 973 };
 974
 975 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
 976 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
 977 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
 978 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
 979 #define HCLGE_NON_DCB_ADDITIONAL_BUF    0x1400  /* 5120 byte */
 980
 981 #define HCLGE_TYPE_CRQ                  0
 982 #define HCLGE_TYPE_CSQ                  1
 983 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
 984 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
 985 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
 986 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
 987 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
 988 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
 989 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
 990 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
 991 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
 992 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
 993
 994 /* this bit indicates that the driver is ready for hardware reset */
 995 #define HCLGE_NIC_SW_RST_RDY_B          16
 996 #define HCLGE_NIC_SW_RST_RDY            BIT(HCLGE_NIC_SW_RST_RDY_B)
 997
 998 #define HCLGE_NIC_CMQ_DESC_NUM          1024
 999 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
1000
1001 #define HCLGE_LED_LOCATE_STATE_S        0
1002 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
1003
1004 struct hclge_set_led_state_cmd {
1005         u8 rsv1[3];
1006         u8 locate_led_config;
1007         u8 rsv2[20];
1008 };
1009
1010 struct hclge_get_fd_mode_cmd {
1011         u8 mode;
1012         u8 enable;
1013         u8 rsv[22];
1014 };
1015
1016 struct hclge_get_fd_allocation_cmd {
1017         __le32 stage1_entry_num;
1018         __le32 stage2_entry_num;
1019         __le16 stage1_counter_num;
1020         __le16 stage2_counter_num;
1021         u8 rsv[12];
1022 };
1023
1024 struct hclge_set_fd_key_config_cmd {
1025         u8 stage;
1026         u8 key_select;
1027         u8 inner_sipv6_word_en;
1028         u8 inner_dipv6_word_en;
1029         u8 outer_sipv6_word_en;
1030         u8 outer_dipv6_word_en;
1031         u8 rsv1[2];
1032         __le32 tuple_mask;
1033         __le32 meta_data_mask;
1034         u8 rsv2[8];
1035 };
1036
1037 #define HCLGE_FD_EPORT_SW_EN_B          0
1038 struct hclge_fd_tcam_config_1_cmd {
1039         u8 stage;
1040         u8 xy_sel;
1041         u8 port_info;
1042         u8 rsv1[1];
1043         __le32 index;
1044         u8 entry_vld;
1045         u8 rsv2[7];
1046         u8 tcam_data[8];
1047 };
1048
1049 struct hclge_fd_tcam_config_2_cmd {
1050         u8 tcam_data[24];
1051 };
1052
1053 struct hclge_fd_tcam_config_3_cmd {
1054         u8 tcam_data[20];
1055         u8 rsv[4];
1056 };
1057
1058 #define HCLGE_FD_AD_DROP_B              0
1059 #define HCLGE_FD_AD_DIRECT_QID_B        1
1060 #define HCLGE_FD_AD_QID_S               2
1061 #define HCLGE_FD_AD_QID_M               GENMASK(11, 2)
1062 #define HCLGE_FD_AD_USE_COUNTER_B       12
1063 #define HCLGE_FD_AD_COUNTER_NUM_S       13
1064 #define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
1065 #define HCLGE_FD_AD_NXT_STEP_B          20
1066 #define HCLGE_FD_AD_NXT_KEY_S           21
1067 #define HCLGE_FD_AD_NXT_KEY_M           GENMASK(25, 21)
1068 #define HCLGE_FD_AD_WR_RULE_ID_B        0
1069 #define HCLGE_FD_AD_RULE_ID_S           1
1070 #define HCLGE_FD_AD_RULE_ID_M           GENMASK(12, 1)
1071 #define HCLGE_FD_AD_TC_OVRD_B           16
1072 #define HCLGE_FD_AD_TC_SIZE_S           17
1073 #define HCLGE_FD_AD_TC_SIZE_M           GENMASK(20, 17)
1074
1075 struct hclge_fd_ad_config_cmd {
1076         u8 stage;
1077         u8 rsv1[3];
1078         __le32 index;
1079         __le64 ad_data;
1080         u8 rsv2[8];
1081 };
1082
1083 struct hclge_get_m7_bd_cmd {
1084         __le32 bd_num;
1085         u8 rsv[20];
1086 };
1087
1088 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1089         __le16 over_8bd_no_fe_qid;
1090         __le16 over_8bd_no_fe_vf_id;
1091         __le16 tso_mss_cmp_min_err_qid;
1092         __le16 tso_mss_cmp_min_err_vf_id;
1093         __le16 tso_mss_cmp_max_err_qid;
1094         __le16 tso_mss_cmp_max_err_vf_id;
1095         __le16 tx_rd_fbd_poison_qid;
1096         __le16 tx_rd_fbd_poison_vf_id;
1097         __le16 rx_rd_fbd_poison_qid;
1098         __le16 rx_rd_fbd_poison_vf_id;
1099         u8 rsv[4];
1100 };
1101
1102 #define HCLGE_LINK_EVENT_REPORT_EN_B    0
1103 #define HCLGE_NCSI_ERROR_REPORT_EN_B    1
1104 #define HCLGE_PHY_IMP_EN_B              2
1105 struct hclge_firmware_compat_cmd {
1106         __le32 compat;
1107         u8 rsv[20];
1108 };
1109
1110 #define HCLGE_SFP_INFO_CMD_NUM  6
1111 #define HCLGE_SFP_INFO_BD0_LEN  20
1112 #define HCLGE_SFP_INFO_BDX_LEN  24
1113 #define HCLGE_SFP_INFO_MAX_LEN \
1114         (HCLGE_SFP_INFO_BD0_LEN + \
1115         (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1116
1117 struct hclge_sfp_info_bd0_cmd {
1118         __le16 offset;
1119         __le16 read_len;
1120         u8 data[HCLGE_SFP_INFO_BD0_LEN];
1121 };
1122
1123 #define HCLGE_QUERY_DEV_SPECS_BD_NUM            4
1124
1125 struct hclge_dev_specs_0_cmd {
1126         __le32 rsv0;
1127         __le32 mac_entry_num;
1128         __le32 mng_entry_num;
1129         __le16 rss_ind_tbl_size;
1130         __le16 rss_key_size;
1131         __le16 int_ql_max;
1132         u8 max_non_tso_bd_num;
1133         u8 rsv1;
1134         __le32 max_tm_rate;
1135 };
1136
1137 #define HCLGE_DEF_MAX_INT_GL            0x1FE0U
1138
1139 struct hclge_dev_specs_1_cmd {
1140         __le16 max_frm_size;
1141         __le16 max_qset_num;
1142         __le16 max_int_gl;
1143         u8 rsv1[18];
1144 };
1145
1146 #define HCLGE_PHY_LINK_SETTING_BD_NUM           2
1147
1148 struct hclge_phy_link_ksetting_0_cmd {
1149         __le32 speed;
1150         u8 duplex;
1151         u8 autoneg;
1152         u8 eth_tp_mdix;
1153         u8 eth_tp_mdix_ctrl;
1154         u8 port;
1155         u8 transceiver;
1156         u8 phy_address;
1157         u8 rsv;
1158         __le32 supported;
1159         __le32 advertising;
1160         __le32 lp_advertising;
1161 };
1162
1163 struct hclge_phy_link_ksetting_1_cmd {
1164         u8 master_slave_cfg;
1165         u8 master_slave_state;
1166         u8 rsv[22];
1167 };
1168
1169 int hclge_cmd_init(struct hclge_dev *hdev);
1170 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1171 {
1172         writel(value, base + reg);
1173 }
1174
1175 #define hclge_write_dev(a, reg, value) \
1176         hclge_write_reg((a)->io_base, reg, value)
1177 #define hclge_read_dev(a, reg) \
1178         hclge_read_reg((a)->io_base, reg)
1179
1180 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1181 {
1182         u8 __iomem *reg_addr = READ_ONCE(base);
1183
1184         return readl(reg_addr + reg);
1185 }
1186
1187 #define HCLGE_SEND_SYNC(flag) \
1188         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1189
1190 struct hclge_hw;
1191 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1192 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1193                                 enum hclge_opcode_type opcode, bool is_read);
1194 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1195
1196 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1197                                            struct hclge_desc *desc);
1198 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1199                                           struct hclge_desc *desc);
1200
1201 void hclge_cmd_uninit(struct hclge_dev *hdev);
1202 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1203 #endif