drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #ifndef __HCLGE_CMD_H
   5 #define __HCLGE_CMD_H
   6 #include <linux/types.h>
   7 #include <linux/io.h>
   8
   9 #define HCLGE_CMDQ_TX_TIMEOUT           30000
  10
  11 struct hclge_dev;
  12 struct hclge_desc {
  13         __le16 opcode;
  14
  15 #define HCLGE_CMDQ_RX_INVLD_B           0
  16 #define HCLGE_CMDQ_RX_OUTVLD_B          1
  17
  18         __le16 flag;
  19         __le16 retval;
  20         __le16 rsv;
  21         __le32 data[6];
  22 };
  23
  24 struct hclge_cmq_ring {
  25         dma_addr_t desc_dma_addr;
  26         struct hclge_desc *desc;
  27         struct hclge_dev *dev;
  28         u32 head;
  29         u32 tail;
  30
  31         u16 buf_size;
  32         u16 desc_num;
  33         int next_to_use;
  34         int next_to_clean;
  35         u8 ring_type; /* cmq ring type */
  36         spinlock_t lock; /* Command queue lock */
  37 };
  38
  39 enum hclge_cmd_return_status {
  40         HCLGE_CMD_EXEC_SUCCESS  = 0,
  41         HCLGE_CMD_NO_AUTH       = 1,
  42         HCLGE_CMD_NOT_SUPPORTED = 2,
  43         HCLGE_CMD_QUEUE_FULL    = 3,
  44         HCLGE_CMD_NEXT_ERR      = 4,
  45         HCLGE_CMD_UNEXE_ERR     = 5,
  46         HCLGE_CMD_PARA_ERR      = 6,
  47         HCLGE_CMD_RESULT_ERR    = 7,
  48         HCLGE_CMD_TIMEOUT       = 8,
  49         HCLGE_CMD_HILINK_ERR    = 9,
  50         HCLGE_CMD_QUEUE_ILLEGAL = 10,
  51         HCLGE_CMD_INVALID       = 11,
  52 };
  53
  54 enum hclge_cmd_status {
  55         HCLGE_STATUS_SUCCESS    = 0,
  56         HCLGE_ERR_CSQ_FULL      = -1,
  57         HCLGE_ERR_CSQ_TIMEOUT   = -2,
  58         HCLGE_ERR_CSQ_ERROR     = -3,
  59 };
  60
  61 struct hclge_misc_vector {
  62         u8 __iomem *addr;
  63         int vector_irq;
  64 };
  65
  66 struct hclge_cmq {
  67         struct hclge_cmq_ring csq;
  68         struct hclge_cmq_ring crq;
  69         u16 tx_timeout;
  70         enum hclge_cmd_status last_status;
  71 };
  72
  73 #define HCLGE_CMD_FLAG_IN       BIT(0)
  74 #define HCLGE_CMD_FLAG_OUT      BIT(1)
  75 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
  76 #define HCLGE_CMD_FLAG_WR       BIT(3)
  77 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
  78 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  79
  80 enum hclge_opcode_type {
  81         /* Generic commands */
  82         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  83         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  84         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  85         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  86         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  87         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
  88         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
  89         HCLGE_OPC_PF_RST_DONE           = 0x0026,
  90
  91         HCLGE_OPC_STATS_64_BIT          = 0x0030,
  92         HCLGE_OPC_STATS_32_BIT          = 0x0031,
  93         HCLGE_OPC_STATS_MAC             = 0x0032,
  94         HCLGE_OPC_QUERY_MAC_REG_NUM     = 0x0033,
  95         HCLGE_OPC_STATS_MAC_ALL         = 0x0034,
  96
  97         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
  98         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
  99         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
 100         HCLGE_OPC_DFX_BD_NUM            = 0x0043,
 101         HCLGE_OPC_DFX_BIOS_COMMON_REG   = 0x0044,
 102         HCLGE_OPC_DFX_SSU_REG_0         = 0x0045,
 103         HCLGE_OPC_DFX_SSU_REG_1         = 0x0046,
 104         HCLGE_OPC_DFX_IGU_EGU_REG       = 0x0047,
 105         HCLGE_OPC_DFX_RPU_REG_0         = 0x0048,
 106         HCLGE_OPC_DFX_RPU_REG_1         = 0x0049,
 107         HCLGE_OPC_DFX_NCSI_REG          = 0x004A,
 108         HCLGE_OPC_DFX_RTC_REG           = 0x004B,
 109         HCLGE_OPC_DFX_PPP_REG           = 0x004C,
 110         HCLGE_OPC_DFX_RCB_REG           = 0x004D,
 111         HCLGE_OPC_DFX_TQP_REG           = 0x004E,
 112         HCLGE_OPC_DFX_SSU_REG_2         = 0x004F,
 113         HCLGE_OPC_DFX_QUERY_CHIP_CAP    = 0x0050,
 114
 115         /* MAC command */
 116         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
 117         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
 118         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 119         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 120         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 121         HCLGE_OPC_QUERY_MAC_TNL_INT     = 0x0310,
 122         HCLGE_OPC_MAC_TNL_INT_EN        = 0x0311,
 123         HCLGE_OPC_CLEAR_MAC_TNL_INT     = 0x0312,
 124         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
 125         HCLGE_OPC_CONFIG_FEC_MODE       = 0x031A,
 126
 127         /* PFC/Pause commands */
 128         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 129         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 130         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 131         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 132         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 133         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 134         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 135         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 136         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 137         HCLGE_OPC_QOS_MAP               = 0x070A,
 138
 139         /* ETS/scheduler commands */
 140         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 141         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 142         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 143         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 144         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 145         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 146         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 147         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 148         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 149         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 150         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 151         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 152         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 153         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 154         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 155         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 156         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 157         HCLGE_OPC_ETS_TC_WEIGHT         = 0x0843,
 158         HCLGE_OPC_QSET_DFX_STS          = 0x0844,
 159         HCLGE_OPC_PRI_DFX_STS           = 0x0845,
 160         HCLGE_OPC_PG_DFX_STS            = 0x0846,
 161         HCLGE_OPC_PORT_DFX_STS          = 0x0847,
 162         HCLGE_OPC_SCH_NQ_CNT            = 0x0848,
 163         HCLGE_OPC_SCH_RQ_CNT            = 0x0849,
 164         HCLGE_OPC_TM_INTERNAL_STS       = 0x0850,
 165         HCLGE_OPC_TM_INTERNAL_CNT       = 0x0851,
 166         HCLGE_OPC_TM_INTERNAL_STS_1     = 0x0852,
 167
 168         /* Packet buffer allocate commands */
 169         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 170         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 171         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 172         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 173         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 174         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 175
 176         /* TQP management command */
 177         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 178
 179         /* TQP commands */
 180         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 181         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 182         HCLGE_OPC_QUERY_TX_STATUS       = 0x0B03,
 183         HCLGE_OPC_TQP_TX_QUEUE_TC       = 0x0B04,
 184         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 185         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 186         HCLGE_OPC_QUERY_RX_STATUS       = 0x0B13,
 187         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 188         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 189         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 190         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 191
 192         /* PPU commands */
 193         HCLGE_OPC_PPU_PF_OTHER_INT_DFX  = 0x0B4A,
 194
 195         /* TSO command */
 196         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 197         HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
 198
 199         /* RSS commands */
 200         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 201         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 202         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 203         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 204
 205         /* Promisuous mode command */
 206         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 207
 208         /* Vlan offload commands */
 209         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 210         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 211
 212         /* Interrupts commands */
 213         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 214         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 215
 216         /* MAC commands */
 217         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 218         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 219         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 220         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 221         HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
 222         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 223         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 224
 225         /* VLAN commands */
 226         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 227         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 228         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 229
 230         /* Flow Director commands */
 231         HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
 232         HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
 233         HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
 234         HCLGE_OPC_FD_TCAM_OP            = 0x1203,
 235         HCLGE_OPC_FD_AD_OP              = 0x1204,
 236
 237         /* MDIO command */
 238         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 239
 240         /* QCN commands */
 241         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 242         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 243         HCLGE_OPC_QCN_SHAPPING_IR_CFG   = 0x1A03,
 244         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 245         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 246         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 247         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 248         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 249
 250         /* Mailbox command */
 251         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 252
 253         /* Led command */
 254         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 255
 256         /* NCL config command */
 257         HCLGE_OPC_QUERY_NCL_CONFIG      = 0x7011,
 258         /* M7 stats command */
 259         HCLGE_OPC_M7_STATS_BD           = 0x7012,
 260         HCLGE_OPC_M7_STATS_INFO         = 0x7013,
 261         HCLGE_OPC_M7_COMPAT_CFG         = 0x701A,
 262
 263         /* SFP command */
 264         HCLGE_OPC_GET_SFP_INFO          = 0x7104,
 265
 266         /* Error INT commands */
 267         HCLGE_MAC_COMMON_INT_EN         = 0x030E,
 268         HCLGE_TM_SCH_ECC_INT_EN         = 0x0829,
 269         HCLGE_SSU_ECC_INT_CMD           = 0x0989,
 270         HCLGE_SSU_COMMON_INT_CMD        = 0x098C,
 271         HCLGE_PPU_MPF_ECC_INT_CMD       = 0x0B40,
 272         HCLGE_PPU_MPF_OTHER_INT_CMD     = 0x0B41,
 273         HCLGE_PPU_PF_OTHER_INT_CMD      = 0x0B42,
 274         HCLGE_COMMON_ECC_INT_CFG        = 0x1505,
 275         HCLGE_QUERY_RAS_INT_STS_BD_NUM  = 0x1510,
 276         HCLGE_QUERY_CLEAR_MPF_RAS_INT   = 0x1511,
 277         HCLGE_QUERY_CLEAR_PF_RAS_INT    = 0x1512,
 278         HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
 279         HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT      = 0x1514,
 280         HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT       = 0x1515,
 281         HCLGE_CONFIG_ROCEE_RAS_INT_EN   = 0x1580,
 282         HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
 283         HCLGE_ROCEE_PF_RAS_INT_CMD      = 0x1584,
 284         HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD      = 0x1585,
 285         HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD      = 0x1586,
 286         HCLGE_IGU_EGU_TNL_INT_EN        = 0x1803,
 287         HCLGE_IGU_COMMON_INT_EN         = 0x1806,
 288         HCLGE_TM_QCN_MEM_INT_CFG        = 0x1A14,
 289         HCLGE_PPP_CMD0_INT_CMD          = 0x2100,
 290         HCLGE_PPP_CMD1_INT_CMD          = 0x2101,
 291         HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
 292         HCLGE_NCSI_INT_EN               = 0x2401,
 293 };
 294
 295 #define HCLGE_TQP_REG_OFFSET            0x80000
 296 #define HCLGE_TQP_REG_SIZE              0x200
 297
 298 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 299 #define HCLGE_RCB_INIT_FLAG_EN_B        0
 300 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
 301 struct hclge_config_rcb_init_cmd {
 302         __le16 rcb_init_flag;
 303         u8 rsv[22];
 304 };
 305
 306 struct hclge_tqp_map_cmd {
 307         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 308         u8 tqp_vf;      /* VF id */
 309 #define HCLGE_TQP_MAP_TYPE_PF           0
 310 #define HCLGE_TQP_MAP_TYPE_VF           1
 311 #define HCLGE_TQP_MAP_TYPE_B            0
 312 #define HCLGE_TQP_MAP_EN_B              1
 313         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 314         __le16 tqp_vid; /* Virtual id in this pf/vf */
 315         u8 rsv[18];
 316 };
 317
 318 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 319
 320 enum hclge_int_type {
 321         HCLGE_INT_TX,
 322         HCLGE_INT_RX,
 323         HCLGE_INT_EVENT,
 324 };
 325
 326 struct hclge_ctrl_vector_chain_cmd {
 327         u8 int_vector_id;
 328         u8 int_cause_num;
 329 #define HCLGE_INT_TYPE_S        0
 330 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 331 #define HCLGE_TQP_ID_S          2
 332 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
 333 #define HCLGE_INT_GL_IDX_S      13
 334 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 335         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 336         u8 vfid;
 337         u8 rsv;
 338 };
 339
 340 #define HCLGE_MAX_TC_NUM                8
 341 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 342 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 343 struct hclge_tx_buff_alloc_cmd {
 344         __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
 345         u8 tx_buff_rsv[8];
 346 };
 347
 348 struct hclge_rx_priv_buff_cmd {
 349         __le16 buf_num[HCLGE_MAX_TC_NUM];
 350         __le16 shared_buf;
 351         u8 rsv[6];
 352 };
 353
 354 struct hclge_query_version_cmd {
 355         __le32 firmware;
 356         __le32 firmware_rsv[5];
 357 };
 358
 359 #define HCLGE_RX_PRIV_EN_B      15
 360 #define HCLGE_TC_NUM_ONE_DESC   4
 361 struct hclge_priv_wl {
 362         __le16 high;
 363         __le16 low;
 364 };
 365
 366 struct hclge_rx_priv_wl_buf {
 367         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 368 };
 369
 370 struct hclge_rx_com_thrd {
 371         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 372 };
 373
 374 struct hclge_rx_com_wl {
 375         struct hclge_priv_wl com_wl;
 376 };
 377
 378 struct hclge_waterline {
 379         u32 low;
 380         u32 high;
 381 };
 382
 383 struct hclge_tc_thrd {
 384         u32 low;
 385         u32 high;
 386 };
 387
 388 struct hclge_priv_buf {
 389         struct hclge_waterline wl;      /* Waterline for low and high*/
 390         u32 buf_size;   /* TC private buffer size */
 391         u32 tx_buf_size;
 392         u32 enable;     /* Enable TC private buffer or not */
 393 };
 394
 395 struct hclge_shared_buf {
 396         struct hclge_waterline self;
 397         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 398         u32 buf_size;
 399 };
 400
 401 struct hclge_pkt_buf_alloc {
 402         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 403         struct hclge_shared_buf s_buf;
 404 };
 405
 406 #define HCLGE_RX_COM_WL_EN_B    15
 407 struct hclge_rx_com_wl_buf_cmd {
 408         __le16 high_wl;
 409         __le16 low_wl;
 410         u8 rsv[20];
 411 };
 412
 413 #define HCLGE_RX_PKT_EN_B       15
 414 struct hclge_rx_pkt_buf_cmd {
 415         __le16 high_pkt;
 416         __le16 low_pkt;
 417         u8 rsv[20];
 418 };
 419
 420 #define HCLGE_PF_STATE_DONE_B   0
 421 #define HCLGE_PF_STATE_MAIN_B   1
 422 #define HCLGE_PF_STATE_BOND_B   2
 423 #define HCLGE_PF_STATE_MAC_N_B  6
 424 #define HCLGE_PF_MAC_NUM_MASK   0x3
 425 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 426 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 427 struct hclge_func_status_cmd {
 428         __le32  vf_rst_state[4];
 429         u8 pf_state;
 430         u8 mac_id;
 431         u8 rsv1;
 432         u8 pf_cnt_in_mac;
 433         u8 pf_num;
 434         u8 vf_num;
 435         u8 rsv[2];
 436 };
 437
 438 struct hclge_pf_res_cmd {
 439         __le16 tqp_num;
 440         __le16 buf_size;
 441         __le16 msixcap_localid_ba_nic;
 442         __le16 msixcap_localid_ba_rocee;
 443 #define HCLGE_MSIX_OFT_ROCEE_S          0
 444 #define HCLGE_MSIX_OFT_ROCEE_M          GENMASK(15, 0)
 445 #define HCLGE_PF_VEC_NUM_S              0
 446 #define HCLGE_PF_VEC_NUM_M              GENMASK(7, 0)
 447         __le16 pf_intr_vector_number;
 448         __le16 pf_own_fun_number;
 449         __le16 tx_buf_size;
 450         __le16 dv_buf_size;
 451         __le32 rsv[2];
 452 };
 453
 454 #define HCLGE_CFG_OFFSET_S      0
 455 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 456 #define HCLGE_CFG_RD_LEN_S      24
 457 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 458 #define HCLGE_CFG_RD_LEN_BYTES  16
 459 #define HCLGE_CFG_RD_LEN_UNIT   4
 460
 461 #define HCLGE_CFG_VMDQ_S        0
 462 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
 463 #define HCLGE_CFG_TC_NUM_S      8
 464 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 465 #define HCLGE_CFG_TQP_DESC_N_S  16
 466 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 467 #define HCLGE_CFG_PHY_ADDR_S    0
 468 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 469 #define HCLGE_CFG_MEDIA_TP_S    8
 470 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 471 #define HCLGE_CFG_RX_BUF_LEN_S  16
 472 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 473 #define HCLGE_CFG_MAC_ADDR_H_S  0
 474 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 475 #define HCLGE_CFG_DEFAULT_SPEED_S       16
 476 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 477 #define HCLGE_CFG_RSS_SIZE_S    24
 478 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 479 #define HCLGE_CFG_SPEED_ABILITY_S       0
 480 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 481 #define HCLGE_CFG_UMV_TBL_SPACE_S       16
 482 #define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
 483
 484 struct hclge_cfg_param_cmd {
 485         __le32 offset;
 486         __le32 rsv;
 487         __le32 param[4];
 488 };
 489
 490 #define HCLGE_MAC_MODE          0x0
 491 #define HCLGE_DESC_NUM          0x40
 492
 493 #define HCLGE_ALLOC_VALID_B     0
 494 struct hclge_vf_num_cmd {
 495         u8 alloc_valid;
 496         u8 rsv[23];
 497 };
 498
 499 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 500 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 501 #define HCLGE_RSS_HASH_KEY_NUM          16
 502 struct hclge_rss_config_cmd {
 503         u8 hash_config;
 504         u8 rsv[7];
 505         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 506 };
 507
 508 struct hclge_rss_input_tuple_cmd {
 509         u8 ipv4_tcp_en;
 510         u8 ipv4_udp_en;
 511         u8 ipv4_sctp_en;
 512         u8 ipv4_fragment_en;
 513         u8 ipv6_tcp_en;
 514         u8 ipv6_udp_en;
 515         u8 ipv6_sctp_en;
 516         u8 ipv6_fragment_en;
 517         u8 rsv[16];
 518 };
 519
 520 #define HCLGE_RSS_CFG_TBL_SIZE  16
 521
 522 struct hclge_rss_indirection_table_cmd {
 523         __le16 start_table_index;
 524         __le16 rss_set_bitmap;
 525         u8 rsv[4];
 526         u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
 527 };
 528
 529 #define HCLGE_RSS_TC_OFFSET_S           0
 530 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(9, 0)
 531 #define HCLGE_RSS_TC_SIZE_S             12
 532 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 533 #define HCLGE_RSS_TC_VALID_B            15
 534 struct hclge_rss_tc_mode_cmd {
 535         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 536         u8 rsv[8];
 537 };
 538
 539 #define HCLGE_LINK_STATUS_UP_B  0
 540 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
 541 struct hclge_link_status_cmd {
 542         u8 status;
 543         u8 rsv[23];
 544 };
 545
 546 struct hclge_promisc_param {
 547         u8 vf_id;
 548         u8 enable;
 549 };
 550
 551 #define HCLGE_PROMISC_TX_EN_B   BIT(4)
 552 #define HCLGE_PROMISC_RX_EN_B   BIT(5)
 553 #define HCLGE_PROMISC_EN_B      1
 554 #define HCLGE_PROMISC_EN_ALL    0x7
 555 #define HCLGE_PROMISC_EN_UC     0x1
 556 #define HCLGE_PROMISC_EN_MC     0x2
 557 #define HCLGE_PROMISC_EN_BC     0x4
 558 struct hclge_promisc_cfg_cmd {
 559         u8 flag;
 560         u8 vf_id;
 561         __le16 rsv0;
 562         u8 rsv1[20];
 563 };
 564
 565 enum hclge_promisc_type {
 566         HCLGE_UNICAST   = 1,
 567         HCLGE_MULTICAST = 2,
 568         HCLGE_BROADCAST = 3,
 569 };
 570
 571 #define HCLGE_MAC_TX_EN_B       6
 572 #define HCLGE_MAC_RX_EN_B       7
 573 #define HCLGE_MAC_PAD_TX_B      11
 574 #define HCLGE_MAC_PAD_RX_B      12
 575 #define HCLGE_MAC_1588_TX_B     13
 576 #define HCLGE_MAC_1588_RX_B     14
 577 #define HCLGE_MAC_APP_LP_B      15
 578 #define HCLGE_MAC_LINE_LP_B     16
 579 #define HCLGE_MAC_FCS_TX_B      17
 580 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 581 #define HCLGE_MAC_RX_FCS_STRIP_B        19
 582 #define HCLGE_MAC_RX_FCS_B      20
 583 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 584 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 585
 586 struct hclge_config_mac_mode_cmd {
 587         __le32 txrx_pad_fcs_loop_en;
 588         u8 rsv[20];
 589 };
 590
 591 #define HCLGE_CFG_SPEED_S               0
 592 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 593
 594 #define HCLGE_CFG_DUPLEX_B              7
 595 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 596
 597 struct hclge_config_mac_speed_dup_cmd {
 598         u8 speed_dup;
 599
 600 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 601         u8 mac_change_fec_en;
 602         u8 rsv[22];
 603 };
 604
 605 #define HCLGE_RING_ID_MASK              GENMASK(9, 0)
 606 #define HCLGE_TQP_ENABLE_B              0
 607
 608 #define HCLGE_MAC_CFG_AN_EN_B           0
 609 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
 610 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 611 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 612 #define HCLGE_MAC_CFG_AN_RST_B          4
 613
 614 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 615
 616 struct hclge_config_auto_neg_cmd {
 617         __le32  cfg_an_cmd_flag;
 618         u8      rsv[20];
 619 };
 620
 621 struct hclge_sfp_info_cmd {
 622         __le32 speed;
 623         u8 query_type; /* 0: sfp speed, 1: active speed */
 624         u8 active_fec;
 625         u8 autoneg; /* autoneg state */
 626         u8 autoneg_ability; /* whether support autoneg */
 627         __le32 speed_ability; /* speed ability for current media */
 628         __le32 module_type;
 629         u8 rsv[8];
 630 };
 631
 632 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B     0
 633 #define HCLGE_MAC_CFG_FEC_MODE_S        1
 634 #define HCLGE_MAC_CFG_FEC_MODE_M        GENMASK(3, 1)
 635 #define HCLGE_MAC_CFG_FEC_SET_DEF_B     0
 636 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B     1
 637
 638 #define HCLGE_MAC_FEC_OFF               0
 639 #define HCLGE_MAC_FEC_BASER             1
 640 #define HCLGE_MAC_FEC_RS                2
 641 struct hclge_config_fec_cmd {
 642         u8 fec_mode;
 643         u8 default_config;
 644         u8 rsv[22];
 645 };
 646
 647 #define HCLGE_MAC_UPLINK_PORT           0x100
 648
 649 struct hclge_config_max_frm_size_cmd {
 650         __le16  max_frm_size;
 651         u8      min_frm_size;
 652         u8      rsv[21];
 653 };
 654
 655 enum hclge_mac_vlan_tbl_opcode {
 656         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 657         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 658         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 659         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 660 };
 661
 662 enum hclge_mac_vlan_add_resp_code {
 663         HCLGE_ADD_UC_OVERFLOW = 2,      /* ADD failed for UC overflow */
 664         HCLGE_ADD_MC_OVERFLOW,          /* ADD failed for MC overflow */
 665 };
 666
 667 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
 668 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
 669 #define HCLGE_MAC_EPORT_SW_EN_B         12
 670 #define HCLGE_MAC_EPORT_TYPE_B          11
 671 #define HCLGE_MAC_EPORT_VFID_S          3
 672 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 673 #define HCLGE_MAC_EPORT_PFID_S          0
 674 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 675 struct hclge_mac_vlan_tbl_entry_cmd {
 676         u8      flags;
 677         u8      resp_code;
 678         __le16  vlan_tag;
 679         __le32  mac_addr_hi32;
 680         __le16  mac_addr_lo16;
 681         __le16  rsv1;
 682         u8      entry_type;
 683         u8      mc_mac_en;
 684         __le16  egress_port;
 685         __le16  egress_queue;
 686         u8      rsv2[6];
 687 };
 688
 689 #define HCLGE_UMV_SPC_ALC_B     0
 690 struct hclge_umv_spc_alc_cmd {
 691         u8 allocate;
 692         u8 rsv1[3];
 693         __le32 space_size;
 694         u8 rsv2[16];
 695 };
 696
 697 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 698 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 699 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 700
 701 struct hclge_mac_mgr_tbl_entry_cmd {
 702         u8      flags;
 703         u8      resp_code;
 704         __le16  vlan_tag;
 705         __le32  mac_addr_hi32;
 706         __le16  mac_addr_lo16;
 707         __le16  rsv1;
 708         __le16  ethter_type;
 709         __le16  egress_port;
 710         __le16  egress_queue;
 711         u8      sw_port_id_aware;
 712         u8      rsv2;
 713         u8      i_port_bitmap;
 714         u8      i_port_direction;
 715         u8      rsv3[2];
 716 };
 717
 718 struct hclge_mac_vlan_add_cmd {
 719         __le16  flags;
 720         __le16  mac_addr_hi16;
 721         __le32  mac_addr_lo32;
 722         __le32  mac_addr_msk_hi32;
 723         __le16  mac_addr_msk_lo16;
 724         __le16  vlan_tag;
 725         __le16  ingress_port;
 726         __le16  egress_port;
 727         u8      rsv[4];
 728 };
 729
 730 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
 731 struct hclge_mac_vlan_remove_cmd {
 732         __le16  flags;
 733         __le16  mac_addr_hi16;
 734         __le32  mac_addr_lo32;
 735         __le32  mac_addr_msk_hi32;
 736         __le16  mac_addr_msk_lo16;
 737         __le16  vlan_tag;
 738         __le16  ingress_port;
 739         __le16  egress_port;
 740         u8      rsv[4];
 741 };
 742
 743 struct hclge_vlan_filter_ctrl_cmd {
 744         u8 vlan_type;
 745         u8 vlan_fe;
 746         u8 rsv1[2];
 747         u8 vf_id;
 748         u8 rsv2[19];
 749 };
 750
 751 struct hclge_vlan_filter_pf_cfg_cmd {
 752         u8 vlan_offset;
 753         u8 vlan_cfg;
 754         u8 rsv[2];
 755         u8 vlan_offset_bitmap[20];
 756 };
 757
 758 struct hclge_vlan_filter_vf_cfg_cmd {
 759         __le16 vlan_id;
 760         u8  resp_code;
 761         u8  rsv;
 762         u8  vlan_cfg;
 763         u8  rsv1[3];
 764         u8  vf_bitmap[16];
 765 };
 766
 767 #define HCLGE_ACCEPT_TAG1_B             0
 768 #define HCLGE_ACCEPT_UNTAG1_B           1
 769 #define HCLGE_PORT_INS_TAG1_EN_B        2
 770 #define HCLGE_PORT_INS_TAG2_EN_B        3
 771 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
 772 #define HCLGE_ACCEPT_TAG2_B             5
 773 #define HCLGE_ACCEPT_UNTAG2_B           6
 774
 775 struct hclge_vport_vtag_tx_cfg_cmd {
 776         u8 vport_vlan_cfg;
 777         u8 vf_offset;
 778         u8 rsv1[2];
 779         __le16 def_vlan_tag1;
 780         __le16 def_vlan_tag2;
 781         u8 vf_bitmap[8];
 782         u8 rsv2[8];
 783 };
 784
 785 #define HCLGE_REM_TAG1_EN_B             0
 786 #define HCLGE_REM_TAG2_EN_B             1
 787 #define HCLGE_SHOW_TAG1_EN_B            2
 788 #define HCLGE_SHOW_TAG2_EN_B            3
 789 struct hclge_vport_vtag_rx_cfg_cmd {
 790         u8 vport_vlan_cfg;
 791         u8 vf_offset;
 792         u8 rsv1[6];
 793         u8 vf_bitmap[8];
 794         u8 rsv2[8];
 795 };
 796
 797 struct hclge_tx_vlan_type_cfg_cmd {
 798         __le16 ot_vlan_type;
 799         __le16 in_vlan_type;
 800         u8 rsv[20];
 801 };
 802
 803 struct hclge_rx_vlan_type_cfg_cmd {
 804         __le16 ot_fst_vlan_type;
 805         __le16 ot_sec_vlan_type;
 806         __le16 in_fst_vlan_type;
 807         __le16 in_sec_vlan_type;
 808         u8 rsv[16];
 809 };
 810
 811 struct hclge_cfg_com_tqp_queue_cmd {
 812         __le16 tqp_id;
 813         __le16 stream_id;
 814         u8 enable;
 815         u8 rsv[19];
 816 };
 817
 818 struct hclge_cfg_tx_queue_pointer_cmd {
 819         __le16 tqp_id;
 820         __le16 tx_tail;
 821         __le16 tx_head;
 822         __le16 fbd_num;
 823         __le16 ring_offset;
 824         u8 rsv[14];
 825 };
 826
 827 #pragma pack(1)
 828 struct hclge_mac_ethertype_idx_rd_cmd {
 829         u8      flags;
 830         u8      resp_code;
 831         __le16  vlan_tag;
 832         u8      mac_addr[6];
 833         __le16  index;
 834         __le16  ethter_type;
 835         __le16  egress_port;
 836         __le16  egress_queue;
 837         __le16  rev0;
 838         u8      i_port_bitmap;
 839         u8      i_port_direction;
 840         u8      rev1[2];
 841 };
 842
 843 #pragma pack()
 844
 845 #define HCLGE_TSO_MSS_MIN_S     0
 846 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 847
 848 #define HCLGE_TSO_MSS_MAX_S     16
 849 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 850
 851 struct hclge_cfg_tso_status_cmd {
 852         __le16 tso_mss_min;
 853         __le16 tso_mss_max;
 854         u8 rsv[20];
 855 };
 856
 857 #define HCLGE_GRO_EN_B          0
 858 struct hclge_cfg_gro_status_cmd {
 859         __le16 gro_en;
 860         u8 rsv[22];
 861 };
 862
 863 #define HCLGE_TSO_MSS_MIN       256
 864 #define HCLGE_TSO_MSS_MAX       9668
 865
 866 #define HCLGE_TQP_RESET_B       0
 867 struct hclge_reset_tqp_queue_cmd {
 868         __le16 tqp_id;
 869         u8 reset_req;
 870         u8 ready_to_reset;
 871         u8 rsv[20];
 872 };
 873
 874 #define HCLGE_CFG_RESET_MAC_B           3
 875 #define HCLGE_CFG_RESET_FUNC_B          7
 876 struct hclge_reset_cmd {
 877         u8 mac_func_reset;
 878         u8 fun_reset_vfid;
 879         u8 rsv[22];
 880 };
 881
 882 #define HCLGE_PF_RESET_DONE_BIT         BIT(0)
 883
 884 struct hclge_pf_rst_done_cmd {
 885         u8 pf_rst_done;
 886         u8 rsv[23];
 887 };
 888
 889 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 890 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
 891 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
 892 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
 893 struct hclge_serdes_lb_cmd {
 894         u8 mask;
 895         u8 enable;
 896         u8 result;
 897         u8 rsv[21];
 898 };
 899
 900 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
 901 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
 902 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
 903 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
 904 #define HCLGE_NON_DCB_ADDITIONAL_BUF    0x1400  /* 5120 byte */
 905
 906 #define HCLGE_TYPE_CRQ                  0
 907 #define HCLGE_TYPE_CSQ                  1
 908 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
 909 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
 910 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
 911 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
 912 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
 913 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
 914 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
 915 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
 916 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
 917 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
 918
 919 /* this bit indicates that the driver is ready for hardware reset */
 920 #define HCLGE_NIC_SW_RST_RDY_B          16
 921 #define HCLGE_NIC_SW_RST_RDY            BIT(HCLGE_NIC_SW_RST_RDY_B)
 922
 923 #define HCLGE_NIC_CMQ_DESC_NUM          1024
 924 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
 925
 926 #define HCLGE_LED_LOCATE_STATE_S        0
 927 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
 928
 929 struct hclge_set_led_state_cmd {
 930         u8 rsv1[3];
 931         u8 locate_led_config;
 932         u8 rsv2[20];
 933 };
 934
 935 struct hclge_get_fd_mode_cmd {
 936         u8 mode;
 937         u8 enable;
 938         u8 rsv[22];
 939 };
 940
 941 struct hclge_get_fd_allocation_cmd {
 942         __le32 stage1_entry_num;
 943         __le32 stage2_entry_num;
 944         __le16 stage1_counter_num;
 945         __le16 stage2_counter_num;
 946         u8 rsv[12];
 947 };
 948
 949 struct hclge_set_fd_key_config_cmd {
 950         u8 stage;
 951         u8 key_select;
 952         u8 inner_sipv6_word_en;
 953         u8 inner_dipv6_word_en;
 954         u8 outer_sipv6_word_en;
 955         u8 outer_dipv6_word_en;
 956         u8 rsv1[2];
 957         __le32 tuple_mask;
 958         __le32 meta_data_mask;
 959         u8 rsv2[8];
 960 };
 961
 962 #define HCLGE_FD_EPORT_SW_EN_B          0
 963 struct hclge_fd_tcam_config_1_cmd {
 964         u8 stage;
 965         u8 xy_sel;
 966         u8 port_info;
 967         u8 rsv1[1];
 968         __le32 index;
 969         u8 entry_vld;
 970         u8 rsv2[7];
 971         u8 tcam_data[8];
 972 };
 973
 974 struct hclge_fd_tcam_config_2_cmd {
 975         u8 tcam_data[24];
 976 };
 977
 978 struct hclge_fd_tcam_config_3_cmd {
 979         u8 tcam_data[20];
 980         u8 rsv[4];
 981 };
 982
 983 #define HCLGE_FD_AD_DROP_B              0
 984 #define HCLGE_FD_AD_DIRECT_QID_B        1
 985 #define HCLGE_FD_AD_QID_S               2
 986 #define HCLGE_FD_AD_QID_M               GENMASK(12, 2)
 987 #define HCLGE_FD_AD_USE_COUNTER_B       12
 988 #define HCLGE_FD_AD_COUNTER_NUM_S       13
 989 #define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
 990 #define HCLGE_FD_AD_NXT_STEP_B          20
 991 #define HCLGE_FD_AD_NXT_KEY_S           21
 992 #define HCLGE_FD_AD_NXT_KEY_M           GENMASK(26, 21)
 993 #define HCLGE_FD_AD_WR_RULE_ID_B        0
 994 #define HCLGE_FD_AD_RULE_ID_S           1
 995 #define HCLGE_FD_AD_RULE_ID_M           GENMASK(13, 1)
 996
 997 struct hclge_fd_ad_config_cmd {
 998         u8 stage;
 999         u8 rsv1[3];
1000         __le32 index;
1001         __le64 ad_data;
1002         u8 rsv2[8];
1003 };
1004
1005 struct hclge_get_m7_bd_cmd {
1006         __le32 bd_num;
1007         u8 rsv[20];
1008 };
1009
1010 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1011         __le16 over_8bd_no_fe_qid;
1012         __le16 over_8bd_no_fe_vf_id;
1013         __le16 tso_mss_cmp_min_err_qid;
1014         __le16 tso_mss_cmp_min_err_vf_id;
1015         __le16 tso_mss_cmp_max_err_qid;
1016         __le16 tso_mss_cmp_max_err_vf_id;
1017         __le16 tx_rd_fbd_poison_qid;
1018         __le16 tx_rd_fbd_poison_vf_id;
1019         __le16 rx_rd_fbd_poison_qid;
1020         __le16 rx_rd_fbd_poison_vf_id;
1021         u8 rsv[4];
1022 };
1023
1024 #define HCLGE_LINK_EVENT_REPORT_EN_B    0
1025 #define HCLGE_NCSI_ERROR_REPORT_EN_B    1
1026 struct hclge_firmware_compat_cmd {
1027         __le32 compat;
1028         u8 rsv[20];
1029 };
1030
1031 int hclge_cmd_init(struct hclge_dev *hdev);
1032 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1033 {
1034         writel(value, base + reg);
1035 }
1036
1037 #define hclge_write_dev(a, reg, value) \
1038         hclge_write_reg((a)->io_base, (reg), (value))
1039 #define hclge_read_dev(a, reg) \
1040         hclge_read_reg((a)->io_base, (reg))
1041
1042 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1043 {
1044         u8 __iomem *reg_addr = READ_ONCE(base);
1045
1046         return readl(reg_addr + reg);
1047 }
1048
1049 #define HCLGE_SEND_SYNC(flag) \
1050         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1051
1052 struct hclge_hw;
1053 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1054 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1055                                 enum hclge_opcode_type opcode, bool is_read);
1056 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1057
1058 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
1059                                struct hclge_promisc_param *param);
1060
1061 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1062                                            struct hclge_desc *desc);
1063 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1064                                           struct hclge_desc *desc);
1065
1066 void hclge_cmd_uninit(struct hclge_dev *hdev);
1067 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1068 #endif