1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
6 #include <linux/types.h>
9 #define HCLGE_CMDQ_TX_TIMEOUT 30000
15 #define HCLGE_CMDQ_RX_INVLD_B 0
16 #define HCLGE_CMDQ_RX_OUTVLD_B 1
24 struct hclge_cmq_ring {
25 dma_addr_t desc_dma_addr;
26 struct hclge_desc *desc;
27 struct hclge_dev *dev;
35 u8 ring_type; /* cmq ring type */
36 spinlock_t lock; /* Command queue lock */
39 enum hclge_cmd_return_status {
40 HCLGE_CMD_EXEC_SUCCESS = 0,
41 HCLGE_CMD_NO_AUTH = 1,
42 HCLGE_CMD_NOT_SUPPORTED = 2,
43 HCLGE_CMD_QUEUE_FULL = 3,
46 enum hclge_cmd_status {
47 HCLGE_STATUS_SUCCESS = 0,
48 HCLGE_ERR_CSQ_FULL = -1,
49 HCLGE_ERR_CSQ_TIMEOUT = -2,
50 HCLGE_ERR_CSQ_ERROR = -3,
53 struct hclge_misc_vector {
59 struct hclge_cmq_ring csq;
60 struct hclge_cmq_ring crq;
62 enum hclge_cmd_status last_status;
65 #define HCLGE_CMD_FLAG_IN BIT(0)
66 #define HCLGE_CMD_FLAG_OUT BIT(1)
67 #define HCLGE_CMD_FLAG_NEXT BIT(2)
68 #define HCLGE_CMD_FLAG_WR BIT(3)
69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
72 enum hclge_opcode_type {
73 /* Generic commands */
74 HCLGE_OPC_QUERY_FW_VER = 0x0001,
75 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
76 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
77 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
78 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
79 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
80 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
82 HCLGE_OPC_STATS_64_BIT = 0x0030,
83 HCLGE_OPC_STATS_32_BIT = 0x0031,
84 HCLGE_OPC_STATS_MAC = 0x0032,
85 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
86 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
88 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
89 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
90 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
91 HCLGE_OPC_DFX_BD_NUM = 0x0043,
92 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
93 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
94 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
95 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
96 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
97 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
98 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
99 HCLGE_OPC_DFX_RTC_REG = 0x004B,
100 HCLGE_OPC_DFX_PPP_REG = 0x004C,
101 HCLGE_OPC_DFX_RCB_REG = 0x004D,
102 HCLGE_OPC_DFX_TQP_REG = 0x004E,
103 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
104 HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050,
107 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
108 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
109 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
110 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
111 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
112 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
113 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
114 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
115 HCLGE_OPC_SERDES_LOOPBACK = 0x0315,
117 /* PFC/Pause commands */
118 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
119 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
120 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
121 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
122 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
123 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
124 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
125 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
126 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
127 HCLGE_OPC_QOS_MAP = 0x070A,
129 /* ETS/scheduler commands */
130 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
131 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
132 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
133 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
134 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
135 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
136 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
137 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
138 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
139 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
140 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
141 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
142 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
143 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
144 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
145 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
146 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
147 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
148 HCLGE_OPC_QSET_DFX_STS = 0x0844,
149 HCLGE_OPC_PRI_DFX_STS = 0x0845,
150 HCLGE_OPC_PG_DFX_STS = 0x0846,
151 HCLGE_OPC_PORT_DFX_STS = 0x0847,
152 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
153 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
154 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
155 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
156 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
158 /* Packet buffer allocate commands */
159 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
160 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
161 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
162 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
163 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
164 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
166 /* TQP management command */
167 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
170 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
171 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
172 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03,
173 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
174 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
175 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
176 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13,
177 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
178 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
179 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
180 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
183 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
184 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
187 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
188 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
189 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
190 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
192 /* Promisuous mode command */
193 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
195 /* Vlan offload commands */
196 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
197 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
199 /* Interrupts commands */
200 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
201 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
204 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
205 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
206 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
207 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
208 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
209 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
210 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
213 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
214 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
215 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
217 /* Flow Director commands */
218 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
219 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
220 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
221 HCLGE_OPC_FD_TCAM_OP = 0x1203,
222 HCLGE_OPC_FD_AD_OP = 0x1204,
225 HCLGE_OPC_MDIO_CONFIG = 0x1900,
228 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
229 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
230 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03,
231 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
232 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
233 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
234 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
235 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
237 /* Mailbox command */
238 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
241 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
243 /* NCL config command */
244 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
247 HCLGE_OPC_GET_SFP_INFO = 0x7104,
249 /* Error INT commands */
250 HCLGE_MAC_COMMON_INT_EN = 0x030E,
251 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
252 HCLGE_SSU_ECC_INT_CMD = 0x0989,
253 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
254 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
255 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
256 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
257 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
258 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
259 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
260 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
261 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
262 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
263 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
264 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
265 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
266 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
267 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
268 HCLGE_IGU_COMMON_INT_EN = 0x1806,
269 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
270 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
271 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
272 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
273 HCLGE_NCSI_INT_EN = 0x2401,
276 #define HCLGE_TQP_REG_OFFSET 0x80000
277 #define HCLGE_TQP_REG_SIZE 0x200
279 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
280 #define HCLGE_RCB_INIT_FLAG_EN_B 0
281 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
282 struct hclge_config_rcb_init_cmd {
283 __le16 rcb_init_flag;
287 struct hclge_tqp_map_cmd {
288 __le16 tqp_id; /* Absolute tqp id for in this pf */
289 u8 tqp_vf; /* VF id */
290 #define HCLGE_TQP_MAP_TYPE_PF 0
291 #define HCLGE_TQP_MAP_TYPE_VF 1
292 #define HCLGE_TQP_MAP_TYPE_B 0
293 #define HCLGE_TQP_MAP_EN_B 1
294 u8 tqp_flag; /* Indicate it's pf or vf tqp */
295 __le16 tqp_vid; /* Virtual id in this pf/vf */
299 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
301 enum hclge_int_type {
307 struct hclge_ctrl_vector_chain_cmd {
310 #define HCLGE_INT_TYPE_S 0
311 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
312 #define HCLGE_TQP_ID_S 2
313 #define HCLGE_TQP_ID_M GENMASK(12, 2)
314 #define HCLGE_INT_GL_IDX_S 13
315 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
316 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
321 #define HCLGE_MAX_TC_NUM 8
322 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
323 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
324 struct hclge_tx_buff_alloc_cmd {
325 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
329 struct hclge_rx_priv_buff_cmd {
330 __le16 buf_num[HCLGE_MAX_TC_NUM];
335 struct hclge_query_version_cmd {
337 __le32 firmware_rsv[5];
340 #define HCLGE_RX_PRIV_EN_B 15
341 #define HCLGE_TC_NUM_ONE_DESC 4
342 struct hclge_priv_wl {
347 struct hclge_rx_priv_wl_buf {
348 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
351 struct hclge_rx_com_thrd {
352 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
355 struct hclge_rx_com_wl {
356 struct hclge_priv_wl com_wl;
359 struct hclge_waterline {
364 struct hclge_tc_thrd {
369 struct hclge_priv_buf {
370 struct hclge_waterline wl; /* Waterline for low and high*/
371 u32 buf_size; /* TC private buffer size */
373 u32 enable; /* Enable TC private buffer or not */
376 struct hclge_shared_buf {
377 struct hclge_waterline self;
378 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
382 struct hclge_pkt_buf_alloc {
383 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
384 struct hclge_shared_buf s_buf;
387 #define HCLGE_RX_COM_WL_EN_B 15
388 struct hclge_rx_com_wl_buf_cmd {
394 #define HCLGE_RX_PKT_EN_B 15
395 struct hclge_rx_pkt_buf_cmd {
401 #define HCLGE_PF_STATE_DONE_B 0
402 #define HCLGE_PF_STATE_MAIN_B 1
403 #define HCLGE_PF_STATE_BOND_B 2
404 #define HCLGE_PF_STATE_MAC_N_B 6
405 #define HCLGE_PF_MAC_NUM_MASK 0x3
406 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
407 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
408 struct hclge_func_status_cmd {
409 __le32 vf_rst_state[4];
419 struct hclge_pf_res_cmd {
422 __le16 msixcap_localid_ba_nic;
423 __le16 msixcap_localid_ba_rocee;
424 #define HCLGE_MSIX_OFT_ROCEE_S 0
425 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0)
426 #define HCLGE_PF_VEC_NUM_S 0
427 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
428 __le16 pf_intr_vector_number;
429 __le16 pf_own_fun_number;
435 #define HCLGE_CFG_OFFSET_S 0
436 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
437 #define HCLGE_CFG_RD_LEN_S 24
438 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
439 #define HCLGE_CFG_RD_LEN_BYTES 16
440 #define HCLGE_CFG_RD_LEN_UNIT 4
442 #define HCLGE_CFG_VMDQ_S 0
443 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
444 #define HCLGE_CFG_TC_NUM_S 8
445 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
446 #define HCLGE_CFG_TQP_DESC_N_S 16
447 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
448 #define HCLGE_CFG_PHY_ADDR_S 0
449 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
450 #define HCLGE_CFG_MEDIA_TP_S 8
451 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
452 #define HCLGE_CFG_RX_BUF_LEN_S 16
453 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
454 #define HCLGE_CFG_MAC_ADDR_H_S 0
455 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
456 #define HCLGE_CFG_DEFAULT_SPEED_S 16
457 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
458 #define HCLGE_CFG_RSS_SIZE_S 24
459 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
460 #define HCLGE_CFG_SPEED_ABILITY_S 0
461 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
462 #define HCLGE_CFG_UMV_TBL_SPACE_S 16
463 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
465 struct hclge_cfg_param_cmd {
471 #define HCLGE_MAC_MODE 0x0
472 #define HCLGE_DESC_NUM 0x40
474 #define HCLGE_ALLOC_VALID_B 0
475 struct hclge_vf_num_cmd {
480 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
481 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
482 #define HCLGE_RSS_HASH_KEY_NUM 16
483 struct hclge_rss_config_cmd {
486 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
489 struct hclge_rss_input_tuple_cmd {
501 #define HCLGE_RSS_CFG_TBL_SIZE 16
503 struct hclge_rss_indirection_table_cmd {
504 __le16 start_table_index;
505 __le16 rss_set_bitmap;
507 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
510 #define HCLGE_RSS_TC_OFFSET_S 0
511 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0)
512 #define HCLGE_RSS_TC_SIZE_S 12
513 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
514 #define HCLGE_RSS_TC_VALID_B 15
515 struct hclge_rss_tc_mode_cmd {
516 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
520 #define HCLGE_LINK_STATUS_UP_B 0
521 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
522 struct hclge_link_status_cmd {
527 struct hclge_promisc_param {
532 #define HCLGE_PROMISC_TX_EN_B BIT(4)
533 #define HCLGE_PROMISC_RX_EN_B BIT(5)
534 #define HCLGE_PROMISC_EN_B 1
535 #define HCLGE_PROMISC_EN_ALL 0x7
536 #define HCLGE_PROMISC_EN_UC 0x1
537 #define HCLGE_PROMISC_EN_MC 0x2
538 #define HCLGE_PROMISC_EN_BC 0x4
539 struct hclge_promisc_cfg_cmd {
546 enum hclge_promisc_type {
552 #define HCLGE_MAC_TX_EN_B 6
553 #define HCLGE_MAC_RX_EN_B 7
554 #define HCLGE_MAC_PAD_TX_B 11
555 #define HCLGE_MAC_PAD_RX_B 12
556 #define HCLGE_MAC_1588_TX_B 13
557 #define HCLGE_MAC_1588_RX_B 14
558 #define HCLGE_MAC_APP_LP_B 15
559 #define HCLGE_MAC_LINE_LP_B 16
560 #define HCLGE_MAC_FCS_TX_B 17
561 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
562 #define HCLGE_MAC_RX_FCS_STRIP_B 19
563 #define HCLGE_MAC_RX_FCS_B 20
564 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
565 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
567 struct hclge_config_mac_mode_cmd {
568 __le32 txrx_pad_fcs_loop_en;
572 #define HCLGE_CFG_SPEED_S 0
573 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
575 #define HCLGE_CFG_DUPLEX_B 7
576 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
578 struct hclge_config_mac_speed_dup_cmd {
581 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
582 u8 mac_change_fec_en;
586 #define HCLGE_RING_ID_MASK GENMASK(9, 0)
587 #define HCLGE_TQP_ENABLE_B 0
589 #define HCLGE_MAC_CFG_AN_EN_B 0
590 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
591 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
592 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
593 #define HCLGE_MAC_CFG_AN_RST_B 4
595 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
597 struct hclge_config_auto_neg_cmd {
598 __le32 cfg_an_cmd_flag;
602 struct hclge_sfp_info_cmd {
604 u8 query_type; /* 0: sfp speed, 1: active speed */
606 u8 autoneg; /* autoneg state */
607 u8 autoneg_ability; /* whether support autoneg */
608 __le32 speed_ability; /* speed ability for current media */
613 #define HCLGE_MAC_UPLINK_PORT 0x100
615 struct hclge_config_max_frm_size_cmd {
621 enum hclge_mac_vlan_tbl_opcode {
622 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
623 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */
624 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
625 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
628 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
629 #define HCLGE_MAC_VLAN_BIT1_EN_B 1
630 #define HCLGE_MAC_EPORT_SW_EN_B 12
631 #define HCLGE_MAC_EPORT_TYPE_B 11
632 #define HCLGE_MAC_EPORT_VFID_S 3
633 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
634 #define HCLGE_MAC_EPORT_PFID_S 0
635 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
636 struct hclge_mac_vlan_tbl_entry_cmd {
640 __le32 mac_addr_hi32;
641 __le16 mac_addr_lo16;
650 #define HCLGE_UMV_SPC_ALC_B 0
651 struct hclge_umv_spc_alc_cmd {
658 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
659 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
660 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
661 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc
663 struct hclge_mac_mgr_tbl_entry_cmd {
667 __le32 mac_addr_hi32;
668 __le16 mac_addr_lo16;
680 struct hclge_mac_vlan_add_cmd {
682 __le16 mac_addr_hi16;
683 __le32 mac_addr_lo32;
684 __le32 mac_addr_msk_hi32;
685 __le16 mac_addr_msk_lo16;
692 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
693 struct hclge_mac_vlan_remove_cmd {
695 __le16 mac_addr_hi16;
696 __le32 mac_addr_lo32;
697 __le32 mac_addr_msk_hi32;
698 __le16 mac_addr_msk_lo16;
705 struct hclge_vlan_filter_ctrl_cmd {
713 struct hclge_vlan_filter_pf_cfg_cmd {
717 u8 vlan_offset_bitmap[20];
720 struct hclge_vlan_filter_vf_cfg_cmd {
729 #define HCLGE_ACCEPT_TAG1_B 0
730 #define HCLGE_ACCEPT_UNTAG1_B 1
731 #define HCLGE_PORT_INS_TAG1_EN_B 2
732 #define HCLGE_PORT_INS_TAG2_EN_B 3
733 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
734 #define HCLGE_ACCEPT_TAG2_B 5
735 #define HCLGE_ACCEPT_UNTAG2_B 6
737 struct hclge_vport_vtag_tx_cfg_cmd {
741 __le16 def_vlan_tag1;
742 __le16 def_vlan_tag2;
747 #define HCLGE_REM_TAG1_EN_B 0
748 #define HCLGE_REM_TAG2_EN_B 1
749 #define HCLGE_SHOW_TAG1_EN_B 2
750 #define HCLGE_SHOW_TAG2_EN_B 3
751 struct hclge_vport_vtag_rx_cfg_cmd {
759 struct hclge_tx_vlan_type_cfg_cmd {
765 struct hclge_rx_vlan_type_cfg_cmd {
766 __le16 ot_fst_vlan_type;
767 __le16 ot_sec_vlan_type;
768 __le16 in_fst_vlan_type;
769 __le16 in_sec_vlan_type;
773 struct hclge_cfg_com_tqp_queue_cmd {
780 struct hclge_cfg_tx_queue_pointer_cmd {
790 struct hclge_mac_ethertype_idx_rd_cmd {
807 #define HCLGE_TSO_MSS_MIN_S 0
808 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
810 #define HCLGE_TSO_MSS_MAX_S 16
811 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
813 struct hclge_cfg_tso_status_cmd {
819 #define HCLGE_GRO_EN_B 0
820 struct hclge_cfg_gro_status_cmd {
825 #define HCLGE_TSO_MSS_MIN 256
826 #define HCLGE_TSO_MSS_MAX 9668
828 #define HCLGE_TQP_RESET_B 0
829 struct hclge_reset_tqp_queue_cmd {
836 #define HCLGE_CFG_RESET_MAC_B 3
837 #define HCLGE_CFG_RESET_FUNC_B 7
838 struct hclge_reset_cmd {
844 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
845 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
846 #define HCLGE_CMD_SERDES_DONE_B BIT(0)
847 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1)
848 struct hclge_serdes_lb_cmd {
855 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
856 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
857 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
858 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
859 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */
861 #define HCLGE_TYPE_CRQ 0
862 #define HCLGE_TYPE_CSQ 1
863 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
864 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
865 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
866 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
867 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
868 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
869 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
870 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
871 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
872 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
873 #define HCLGE_NIC_CMQ_EN_B 16
874 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B)
875 #define HCLGE_NIC_CMQ_DESC_NUM 1024
876 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
878 #define HCLGE_LED_LOCATE_STATE_S 0
879 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
881 struct hclge_set_led_state_cmd {
883 u8 locate_led_config;
887 struct hclge_get_fd_mode_cmd {
893 struct hclge_get_fd_allocation_cmd {
894 __le32 stage1_entry_num;
895 __le32 stage2_entry_num;
896 __le16 stage1_counter_num;
897 __le16 stage2_counter_num;
901 struct hclge_set_fd_key_config_cmd {
904 u8 inner_sipv6_word_en;
905 u8 inner_dipv6_word_en;
906 u8 outer_sipv6_word_en;
907 u8 outer_dipv6_word_en;
910 __le32 meta_data_mask;
914 #define HCLGE_FD_EPORT_SW_EN_B 0
915 struct hclge_fd_tcam_config_1_cmd {
926 struct hclge_fd_tcam_config_2_cmd {
930 struct hclge_fd_tcam_config_3_cmd {
935 #define HCLGE_FD_AD_DROP_B 0
936 #define HCLGE_FD_AD_DIRECT_QID_B 1
937 #define HCLGE_FD_AD_QID_S 2
938 #define HCLGE_FD_AD_QID_M GENMASK(12, 2)
939 #define HCLGE_FD_AD_USE_COUNTER_B 12
940 #define HCLGE_FD_AD_COUNTER_NUM_S 13
941 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
942 #define HCLGE_FD_AD_NXT_STEP_B 20
943 #define HCLGE_FD_AD_NXT_KEY_S 21
944 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21)
945 #define HCLGE_FD_AD_WR_RULE_ID_B 0
946 #define HCLGE_FD_AD_RULE_ID_S 1
947 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1)
949 struct hclge_fd_ad_config_cmd {
957 int hclge_cmd_init(struct hclge_dev *hdev);
958 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
960 writel(value, base + reg);
963 #define hclge_write_dev(a, reg, value) \
964 hclge_write_reg((a)->io_base, (reg), (value))
965 #define hclge_read_dev(a, reg) \
966 hclge_read_reg((a)->io_base, (reg))
968 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
970 u8 __iomem *reg_addr = READ_ONCE(base);
972 return readl(reg_addr + reg);
975 #define HCLGE_SEND_SYNC(flag) \
976 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
979 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
980 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
981 enum hclge_opcode_type opcode, bool is_read);
982 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
984 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
985 struct hclge_promisc_param *param);
987 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
988 struct hclge_desc *desc);
989 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
990 struct hclge_desc *desc);
992 void hclge_cmd_uninit(struct hclge_dev *hdev);
993 int hclge_cmd_queue_init(struct hclge_dev *hdev);