1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
7 #include <linux/if_vlan.h>
12 HNS3_NIC_STATE_TESTING,
13 HNS3_NIC_STATE_RESETTING,
14 HNS3_NIC_STATE_INITED,
16 HNS3_NIC_STATE_DISABLED,
17 HNS3_NIC_STATE_REMOVING,
18 HNS3_NIC_STATE_SERVICE_INITED,
19 HNS3_NIC_STATE_SERVICE_SCHED,
20 HNS3_NIC_STATE2_RESET_REQUESTED,
24 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
25 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
26 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
27 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
28 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
29 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
30 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
31 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
33 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
34 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
35 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
36 #define HNS3_RING_TX_RING_TC_REG 0x00050
37 #define HNS3_RING_TX_RING_TAIL_REG 0x00058
38 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C
39 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
40 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064
41 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068
42 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
43 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070
44 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074
45 #define HNS3_RING_EN_REG 0x00090
47 #define HNS3_RX_HEAD_SIZE 256
49 #define HNS3_TX_TIMEOUT (5 * HZ)
50 #define HNS3_RING_NAME_LEN 16
51 #define HNS3_BUFFER_SIZE_2048 2048
52 #define HNS3_RING_MAX_PENDING 32760
53 #define HNS3_RING_MIN_PENDING 72
54 #define HNS3_RING_BD_MULTIPLE 8
55 /* max frame size of mac */
56 #define HNS3_MAC_MAX_FRAME 9728
57 #define HNS3_MAX_MTU \
58 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
60 #define HNS3_BD_SIZE_512_TYPE 0
61 #define HNS3_BD_SIZE_1024_TYPE 1
62 #define HNS3_BD_SIZE_2048_TYPE 2
63 #define HNS3_BD_SIZE_4096_TYPE 3
65 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
66 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
67 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
68 #define HNS3_RX_FLAG_L4ID_UDP 0x0
69 #define HNS3_RX_FLAG_L4ID_TCP 0x1
71 #define HNS3_RXD_DMAC_S 0
72 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
73 #define HNS3_RXD_VLAN_S 2
74 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
75 #define HNS3_RXD_L3ID_S 4
76 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
77 #define HNS3_RXD_L4ID_S 8
78 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
79 #define HNS3_RXD_FRAG_B 12
80 #define HNS3_RXD_STRP_TAGP_S 13
81 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
83 #define HNS3_RXD_L2E_B 16
84 #define HNS3_RXD_L3E_B 17
85 #define HNS3_RXD_L4E_B 18
86 #define HNS3_RXD_TRUNCAT_B 19
87 #define HNS3_RXD_HOI_B 20
88 #define HNS3_RXD_DOI_B 21
89 #define HNS3_RXD_OL3E_B 22
90 #define HNS3_RXD_OL4E_B 23
91 #define HNS3_RXD_GRO_COUNT_S 24
92 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
93 #define HNS3_RXD_GRO_FIXID_B 30
94 #define HNS3_RXD_GRO_ECN_B 31
96 #define HNS3_RXD_ODMAC_S 0
97 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
98 #define HNS3_RXD_OVLAN_S 2
99 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
100 #define HNS3_RXD_OL3ID_S 4
101 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
102 #define HNS3_RXD_OL4ID_S 8
103 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
104 #define HNS3_RXD_FBHI_S 12
105 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
106 #define HNS3_RXD_FBLI_S 14
107 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
109 #define HNS3_RXD_BDTYPE_S 0
110 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
111 #define HNS3_RXD_VLD_B 4
112 #define HNS3_RXD_UDP0_B 5
113 #define HNS3_RXD_EXTEND_B 7
114 #define HNS3_RXD_FE_B 8
115 #define HNS3_RXD_LUM_B 9
116 #define HNS3_RXD_CRCP_B 10
117 #define HNS3_RXD_L3L4P_B 11
118 #define HNS3_RXD_TSIND_S 12
119 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
120 #define HNS3_RXD_LKBK_B 15
121 #define HNS3_RXD_GRO_SIZE_S 16
122 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
124 #define HNS3_TXD_L3T_S 0
125 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
126 #define HNS3_TXD_L4T_S 2
127 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
128 #define HNS3_TXD_L3CS_B 4
129 #define HNS3_TXD_L4CS_B 5
130 #define HNS3_TXD_VLAN_B 6
131 #define HNS3_TXD_TSO_B 7
133 #define HNS3_TXD_L2LEN_S 8
134 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
135 #define HNS3_TXD_L3LEN_S 16
136 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
137 #define HNS3_TXD_L4LEN_S 24
138 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
140 #define HNS3_TXD_OL3T_S 0
141 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
142 #define HNS3_TXD_OVLAN_B 2
143 #define HNS3_TXD_MACSEC_B 3
144 #define HNS3_TXD_TUNTYPE_S 4
145 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
147 #define HNS3_TXD_BDTYPE_S 0
148 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
149 #define HNS3_TXD_FE_B 4
150 #define HNS3_TXD_SC_S 5
151 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
152 #define HNS3_TXD_EXTEND_B 7
153 #define HNS3_TXD_VLD_B 8
154 #define HNS3_TXD_RI_B 9
155 #define HNS3_TXD_RA_B 10
156 #define HNS3_TXD_TSYN_B 11
157 #define HNS3_TXD_DECTTL_S 12
158 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
160 #define HNS3_TXD_MSS_S 0
161 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
163 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
164 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
166 #define HNS3_VECTOR_NOT_INITED 0
167 #define HNS3_VECTOR_INITED 1
169 #define HNS3_MAX_BD_SIZE 65535
170 #define HNS3_MAX_NON_TSO_BD_NUM 8U
171 #define HNS3_MAX_TSO_BD_NUM 63U
172 #define HNS3_MAX_TSO_SIZE \
173 (HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM)
175 #define HNS3_MAX_NON_TSO_SIZE \
176 (HNS3_MAX_BD_SIZE * HNS3_MAX_NON_TSO_BD_NUM)
178 #define HNS3_VECTOR_GL0_OFFSET 0x100
179 #define HNS3_VECTOR_GL1_OFFSET 0x200
180 #define HNS3_VECTOR_GL2_OFFSET 0x300
181 #define HNS3_VECTOR_RL_OFFSET 0x900
182 #define HNS3_VECTOR_RL_EN_B 6
184 #define HNS3_RING_EN_B 0
186 enum hns3_pkt_l2t_type {
187 HNS3_L2_TYPE_UNICAST,
188 HNS3_L2_TYPE_MULTICAST,
189 HNS3_L2_TYPE_BROADCAST,
190 HNS3_L2_TYPE_INVALID,
193 enum hns3_pkt_l3t_type {
200 enum hns3_pkt_l4t_type {
207 enum hns3_pkt_ol3t_type {
210 HNS3_OL3T_IPV4_NO_CSUM,
214 enum hns3_pkt_tun_type {
221 /* hardware spec ring buffer format */
222 struct __packed hns3_desc {
229 __le32 type_cs_vlan_tso_len;
231 __u8 type_cs_vlan_tso;
237 __le16 outer_vlan_tag;
241 __le32 ol_type_vlan_len_msec;
243 __u8 ol_type_vlan_msec;
251 __le16 bdtp_fe_sc_vld_ra_ri;
267 __le16 o_dm_vlan_id_fb;
277 struct hns3_desc_cb {
278 dma_addr_t dma; /* dma address of this desc */
279 void *buf; /* cpu addr for a desc */
281 /* priv data for the desc, e.g. skb when use with ip stack */
284 u32 length; /* length of the buffer */
288 /* desc type, used by the ring user to mark the type of the priv data */
292 enum hns3_pkt_l3type {
297 HNS3_L3_TYPE_IPV4_OPT,
298 HNS3_L3_TYPE_IPV6_EXT,
301 HNS3_L3_TYPE_MAC_PAUSE,
302 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
304 /* reserved for 0xA~0xB */
306 HNS3_L3_TYPE_CNM = 0xc,
308 /* reserved for 0xD~0xE */
310 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
313 enum hns3_pkt_l4type {
321 /* reserved for 0x6~0xE */
323 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
326 enum hns3_pkt_ol3type {
327 HNS3_OL3_TYPE_IPV4 = 0,
329 /* reserved for 0x2~0x3 */
330 HNS3_OL3_TYPE_IPV4_OPT = 4,
331 HNS3_OL3_TYPE_IPV6_EXT,
333 /* reserved for 0x6~0xE */
335 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
338 enum hns3_pkt_ol4type {
339 HNS3_OL4_TYPE_NO_TUN,
340 HNS3_OL4_TYPE_MAC_IN_UDP,
342 HNS3_OL4_TYPE_UNKNOWN
377 struct hns3_enet_ring {
378 struct hns3_desc *desc; /* dma map address space */
379 struct hns3_desc_cb *desc_cb;
380 struct hns3_enet_ring *next;
381 struct hns3_enet_tqp_vector *tqp_vector;
382 struct hnae3_queue *tqp;
384 struct device *dev; /* will be used for DMA mapping of descriptors */
387 struct ring_stats stats;
388 struct u64_stats_sync syncp;
390 dma_addr_t desc_dma_addr;
391 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
392 u16 desc_num; /* total number of desc */
393 int next_to_use; /* idx of next spare desc */
395 /* idx of lastest sent desc, the ring is empty when equal to
400 u32 pull_len; /* head length for current packet */
402 void *va; /* first buffer address for current packet */
404 u32 flag; /* ring attribute */
408 struct sk_buff *tail_skb;
409 } ____cacheline_internodealigned_in_smp;
411 enum hns3_flow_level_range {
418 #define HNS3_INT_GL_MAX 0x1FE0
419 #define HNS3_INT_GL_50K 0x0014
420 #define HNS3_INT_GL_20K 0x0032
421 #define HNS3_INT_GL_18K 0x0036
422 #define HNS3_INT_GL_8K 0x007C
424 #define HNS3_INT_RL_MAX 0x00EC
425 #define HNS3_INT_RL_ENABLE_MASK 0x40
427 struct hns3_enet_coalesce {
430 enum hns3_flow_level_range flow_level;
433 struct hns3_enet_ring_group {
434 /* array of pointers to rings */
435 struct hns3_enet_ring *ring;
436 u64 total_bytes; /* total bytes processed this group */
437 u64 total_packets; /* total packets processed this group */
439 struct hns3_enet_coalesce coal;
442 struct hns3_enet_tqp_vector {
443 struct hnae3_handle *handle;
444 u8 __iomem *mask_addr;
448 u16 idx; /* index in the TQP vector array per handle. */
450 struct napi_struct napi;
452 struct hns3_enet_ring_group rx_group;
453 struct hns3_enet_ring_group tx_group;
455 cpumask_t affinity_mask;
456 u16 num_tqps; /* total number of tqps in TQP vector */
457 struct irq_affinity_notify affinity_notify;
459 char name[HNAE3_INT_NAME_LEN];
461 unsigned long last_jiffies;
462 } ____cacheline_internodealigned_in_smp;
464 struct hns3_nic_priv {
465 struct hnae3_handle *ae_handle;
466 struct net_device *netdev;
470 * the cb for nic to manage the ring buffer, the first half of the
471 * array is for tx_ring and vice versa for the second half
473 struct hns3_enet_ring *ring;
474 struct hns3_enet_tqp_vector *tqp_vector;
477 u64 tx_timeout_count;
481 struct hns3_enet_coalesce tx_coal;
482 struct hns3_enet_coalesce rx_coal;
494 struct gre_base_hdr *gre;
498 struct hns3_hw_error_info {
499 enum hnae3_hw_error_type type;
503 static inline int ring_space(struct hns3_enet_ring *ring)
505 /* This smp_load_acquire() pairs with smp_store_release() in
506 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring.
508 int begin = smp_load_acquire(&ring->next_to_clean);
509 int end = READ_ONCE(ring->next_to_use);
511 return ((end >= begin) ? (ring->desc_num - end + begin) :
515 static inline int is_ring_empty(struct hns3_enet_ring *ring)
517 return ring->next_to_use == ring->next_to_clean;
520 static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
522 return readl(base + reg);
525 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
527 u8 __iomem *reg_addr = READ_ONCE(base);
529 writel(value, reg_addr + reg);
532 #define hns3_read_dev(a, reg) \
533 hns3_read_reg((a)->io_base, (reg))
535 static inline bool hns3_nic_resetting(struct net_device *netdev)
537 struct hns3_nic_priv *priv = netdev_priv(netdev);
539 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
542 #define hns3_write_dev(a, reg, value) \
543 hns3_write_reg((a)->io_base, (reg), (value))
545 #define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
546 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
548 #define ring_to_dev(ring) ((ring)->dev)
550 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev)
552 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
553 DMA_TO_DEVICE : DMA_FROM_DEVICE)
555 #define hns3_buf_size(_ring) ((_ring)->buf_size)
557 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
559 #if (PAGE_SIZE < 8192)
560 if (ring->buf_size > (PAGE_SIZE / 2))
566 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))
568 /* iterator for handling rings in ring group */
569 #define hns3_for_each_ring(pos, head) \
570 for (pos = (head).ring; pos; pos = pos->next)
572 #define hns3_get_handle(ndev) \
573 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
575 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
576 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
578 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
579 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
581 void hns3_ethtool_set_ops(struct net_device *netdev);
582 int hns3_set_channels(struct net_device *netdev,
583 struct ethtool_channels *ch);
585 void hns3_clean_tx_ring(struct hns3_enet_ring *ring);
586 int hns3_init_all_ring(struct hns3_nic_priv *priv);
587 int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
588 int hns3_nic_reset_all_ring(struct hnae3_handle *h);
589 void hns3_fini_ring(struct hns3_enet_ring *ring);
590 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
591 bool hns3_is_phys_func(struct pci_dev *pdev);
592 int hns3_clean_rx_ring(
593 struct hns3_enet_ring *ring, int budget,
594 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
596 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
598 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
600 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
603 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
604 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags);
605 void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
607 #ifdef CONFIG_HNS3_DCB
608 void hns3_dcbnl_setup(struct hnae3_handle *handle);
610 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
613 void hns3_dbg_init(struct hnae3_handle *handle);
614 void hns3_dbg_uninit(struct hnae3_handle *handle);
615 void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
616 void hns3_dbg_unregister_debugfs(void);
617 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size);