1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #include <linux/if_vlan.h>
9 #include <linux/ipv6.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/aer.h>
13 #include <linux/skbuff.h>
14 #include <linux/sctp.h>
15 #include <linux/vermagic.h>
17 #include <net/pkt_cls.h>
19 #include <net/vxlan.h>
22 #include "hns3_enet.h"
24 static void hns3_clear_all_ring(struct hnae3_handle *h);
25 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
26 static void hns3_remove_hw_addr(struct net_device *netdev);
28 static const char hns3_driver_name[] = "hns3";
29 const char hns3_driver_version[] = VERMAGIC_STRING;
30 static const char hns3_driver_string[] =
31 "Hisilicon Ethernet Network Driver for Hip08 Family";
32 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
33 static struct hnae3_client client;
35 /* hns3_pci_tbl - PCI Device ID Table
37 * Last entry must be all 0s
39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
40 * Class, Class Mask, private data (not used) }
42 static const struct pci_device_id hns3_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
58 /* required last entry */
61 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
63 static irqreturn_t hns3_irq_handle(int irq, void *vector)
65 struct hns3_enet_tqp_vector *tqp_vector = vector;
67 napi_schedule(&tqp_vector->napi);
72 /* This callback function is used to set affinity changes to the irq affinity
73 * masks when the irq_set_affinity_notifier function is used.
75 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
76 const cpumask_t *mask)
78 struct hns3_enet_tqp_vector *tqp_vectors =
79 container_of(notify, struct hns3_enet_tqp_vector,
82 tqp_vectors->affinity_mask = *mask;
85 static void hns3_nic_irq_affinity_release(struct kref *ref)
89 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
91 struct hns3_enet_tqp_vector *tqp_vectors;
94 for (i = 0; i < priv->vector_num; i++) {
95 tqp_vectors = &priv->tqp_vector[i];
97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
100 /* clear the affinity notifier and affinity mask */
101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
104 /* release the irq resource */
105 free_irq(tqp_vectors->vector_irq, tqp_vectors);
106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
110 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
112 struct hns3_enet_tqp_vector *tqp_vectors;
113 int txrx_int_idx = 0;
119 for (i = 0; i < priv->vector_num; i++) {
120 tqp_vectors = &priv->tqp_vector[i];
122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "TxRx",
130 } else if (tqp_vectors->rx_group.ring) {
131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
132 "%s-%s-%d", priv->netdev->name, "Rx",
134 } else if (tqp_vectors->tx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Tx",
139 /* Skip this unused q_vector */
143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
149 netdev_err(priv->netdev, "request irq(%d) fail\n",
150 tqp_vectors->vector_irq);
154 tqp_vectors->affinity_notify.notify =
155 hns3_nic_irq_affinity_notify;
156 tqp_vectors->affinity_notify.release =
157 hns3_nic_irq_affinity_release;
158 irq_set_affinity_notifier(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_notify);
160 irq_set_affinity_hint(tqp_vectors->vector_irq,
161 &tqp_vectors->affinity_mask);
163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
169 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
172 writel(mask_en, tqp_vector->mask_addr);
175 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
177 napi_enable(&tqp_vector->napi);
180 hns3_mask_vector_irq(tqp_vector, 1);
183 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
186 hns3_mask_vector_irq(tqp_vector, 0);
188 disable_irq(tqp_vector->vector_irq);
189 napi_disable(&tqp_vector->napi);
192 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
197 /* this defines the configuration for RL (Interrupt Rate Limiter).
198 * Rl defines rate of interrupts i.e. number of interrupts-per-second
199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
203 !tqp_vector->rx_group.coal.gl_adapt_enable)
204 /* According to the hardware, the range of rl_reg is
205 * 0-59 and the unit is 4.
207 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
212 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
220 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
228 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
229 struct hns3_nic_priv *priv)
231 /* initialize the configuration for interrupt coalescing.
232 * 1. GL (Interrupt Gap Limiter)
233 * 2. RL (Interrupt Rate Limiter)
236 /* Default: enable interrupt coalescing self-adaptive and GL */
237 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
247 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
248 struct hns3_nic_priv *priv)
250 struct hnae3_handle *h = priv->ae_handle;
252 hns3_set_vector_coalesce_tx_gl(tqp_vector,
253 tqp_vector->tx_group.coal.int_gl);
254 hns3_set_vector_coalesce_rx_gl(tqp_vector,
255 tqp_vector->rx_group.coal.int_gl);
256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
259 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
261 struct hnae3_handle *h = hns3_get_handle(netdev);
262 struct hnae3_knic_private_info *kinfo = &h->kinfo;
263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
266 if (kinfo->num_tc <= 1) {
267 netdev_reset_tc(netdev);
269 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
272 "netdev_set_num_tc fail, ret=%d!\n", ret);
276 for (i = 0; i < HNAE3_MAX_TC; i++) {
277 if (!kinfo->tc_info[i].enable)
280 netdev_set_tc_queue(netdev,
281 kinfo->tc_info[i].tc,
282 kinfo->tc_info[i].tqp_count,
283 kinfo->tc_info[i].tqp_offset);
287 ret = netif_set_real_num_tx_queues(netdev, queue_size);
290 "netif_set_real_num_tx_queues fail, ret=%d!\n",
295 ret = netif_set_real_num_rx_queues(netdev, queue_size);
298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
305 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
307 u16 alloc_tqps, max_rss_size, rss_size;
309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
310 rss_size = alloc_tqps / h->kinfo.num_tc;
312 return min_t(u16, rss_size, max_rss_size);
315 static void hns3_tqp_enable(struct hnae3_queue *tqp)
319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
320 rcb_reg |= BIT(HNS3_RING_EN_B);
321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
324 static void hns3_tqp_disable(struct hnae3_queue *tqp)
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg &= ~BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
333 static int hns3_nic_net_up(struct net_device *netdev)
335 struct hns3_nic_priv *priv = netdev_priv(netdev);
336 struct hnae3_handle *h = priv->ae_handle;
340 ret = hns3_nic_reset_all_ring(h);
344 /* get irq resource for all vectors */
345 ret = hns3_nic_init_irq(priv);
347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
351 /* enable the vectors */
352 for (i = 0; i < priv->vector_num; i++)
353 hns3_vector_enable(&priv->tqp_vector[i]);
356 for (j = 0; j < h->kinfo.num_tqps; j++)
357 hns3_tqp_enable(h->kinfo.tqp[j]);
359 /* start the ae_dev */
360 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
364 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
370 hns3_tqp_disable(h->kinfo.tqp[j]);
372 for (j = i - 1; j >= 0; j--)
373 hns3_vector_disable(&priv->tqp_vector[j]);
375 hns3_nic_uninit_irq(priv);
380 static int hns3_nic_net_open(struct net_device *netdev)
382 struct hns3_nic_priv *priv = netdev_priv(netdev);
383 struct hnae3_handle *h = hns3_get_handle(netdev);
384 struct hnae3_knic_private_info *kinfo;
387 if (hns3_nic_resetting(netdev))
390 netif_carrier_off(netdev);
392 ret = hns3_nic_set_real_num_queue(netdev);
396 ret = hns3_nic_net_up(netdev);
399 "hns net up fail, ret=%d!\n", ret);
404 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
405 netdev_set_prio_tc_map(netdev, i,
409 if (h->ae_algo->ops->set_timer_task)
410 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
415 static void hns3_nic_net_down(struct net_device *netdev)
417 struct hns3_nic_priv *priv = netdev_priv(netdev);
418 struct hnae3_handle *h = hns3_get_handle(netdev);
419 const struct hnae3_ae_ops *ops;
422 /* disable vectors */
423 for (i = 0; i < priv->vector_num; i++)
424 hns3_vector_disable(&priv->tqp_vector[i]);
427 for (i = 0; i < h->kinfo.num_tqps; i++)
428 hns3_tqp_disable(h->kinfo.tqp[i]);
431 ops = priv->ae_handle->ae_algo->ops;
433 ops->stop(priv->ae_handle);
435 /* free irq resources */
436 hns3_nic_uninit_irq(priv);
438 hns3_clear_all_ring(priv->ae_handle);
441 static int hns3_nic_net_stop(struct net_device *netdev)
443 struct hns3_nic_priv *priv = netdev_priv(netdev);
444 struct hnae3_handle *h = hns3_get_handle(netdev);
446 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
449 if (h->ae_algo->ops->set_timer_task)
450 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
452 netif_tx_stop_all_queues(netdev);
453 netif_carrier_off(netdev);
455 hns3_nic_net_down(netdev);
460 static int hns3_nic_uc_sync(struct net_device *netdev,
461 const unsigned char *addr)
463 struct hnae3_handle *h = hns3_get_handle(netdev);
465 if (h->ae_algo->ops->add_uc_addr)
466 return h->ae_algo->ops->add_uc_addr(h, addr);
471 static int hns3_nic_uc_unsync(struct net_device *netdev,
472 const unsigned char *addr)
474 struct hnae3_handle *h = hns3_get_handle(netdev);
476 if (h->ae_algo->ops->rm_uc_addr)
477 return h->ae_algo->ops->rm_uc_addr(h, addr);
482 static int hns3_nic_mc_sync(struct net_device *netdev,
483 const unsigned char *addr)
485 struct hnae3_handle *h = hns3_get_handle(netdev);
487 if (h->ae_algo->ops->add_mc_addr)
488 return h->ae_algo->ops->add_mc_addr(h, addr);
493 static int hns3_nic_mc_unsync(struct net_device *netdev,
494 const unsigned char *addr)
496 struct hnae3_handle *h = hns3_get_handle(netdev);
498 if (h->ae_algo->ops->rm_mc_addr)
499 return h->ae_algo->ops->rm_mc_addr(h, addr);
504 static u8 hns3_get_netdev_flags(struct net_device *netdev)
508 if (netdev->flags & IFF_PROMISC) {
509 flags = HNAE3_USER_UPE | HNAE3_USER_MPE;
511 flags |= HNAE3_VLAN_FLTR;
512 if (netdev->flags & IFF_ALLMULTI)
513 flags |= HNAE3_USER_MPE;
519 static void hns3_nic_set_rx_mode(struct net_device *netdev)
521 struct hnae3_handle *h = hns3_get_handle(netdev);
525 new_flags = hns3_get_netdev_flags(netdev);
527 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
529 netdev_err(netdev, "sync uc address fail\n");
531 new_flags |= HNAE3_OVERFLOW_UPE;
534 if (netdev->flags & IFF_MULTICAST) {
535 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
538 netdev_err(netdev, "sync mc address fail\n");
540 new_flags |= HNAE3_OVERFLOW_MPE;
544 hns3_update_promisc_mode(netdev, new_flags);
545 /* User mode Promisc mode enable and vlan filtering is disabled to
546 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
547 * vlan fitering is enabled
549 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
550 h->netdev_flags = new_flags;
553 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
555 struct hns3_nic_priv *priv = netdev_priv(netdev);
556 struct hnae3_handle *h = priv->ae_handle;
558 if (h->ae_algo->ops->set_promisc_mode) {
559 return h->ae_algo->ops->set_promisc_mode(h,
560 promisc_flags & HNAE3_UPE,
561 promisc_flags & HNAE3_MPE);
567 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
569 struct hns3_nic_priv *priv = netdev_priv(netdev);
570 struct hnae3_handle *h = priv->ae_handle;
573 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
574 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
575 if (enable != last_state) {
578 enable ? "enable" : "disable");
579 h->ae_algo->ops->enable_vlan_filter(h, enable);
584 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
585 u16 *mss, u32 *type_cs_vlan_tso)
587 u32 l4_offset, hdr_len;
588 union l3_hdr_info l3;
589 union l4_hdr_info l4;
593 if (!skb_is_gso(skb))
596 ret = skb_cow_head(skb, 0);
600 l3.hdr = skb_network_header(skb);
601 l4.hdr = skb_transport_header(skb);
603 /* Software should clear the IPv4's checksum field when tso is
606 if (l3.v4->version == 4)
610 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
613 SKB_GSO_UDP_TUNNEL_CSUM)) {
614 if ((!(skb_shinfo(skb)->gso_type &
616 (skb_shinfo(skb)->gso_type &
617 SKB_GSO_UDP_TUNNEL_CSUM)) {
618 /* Software should clear the udp's checksum
619 * field when tso is needed.
623 /* reset l3&l4 pointers from outer to inner headers */
624 l3.hdr = skb_inner_network_header(skb);
625 l4.hdr = skb_inner_transport_header(skb);
627 /* Software should clear the IPv4's checksum field when
630 if (l3.v4->version == 4)
634 /* normal or tunnel packet*/
635 l4_offset = l4.hdr - skb->data;
636 hdr_len = (l4.tcp->doff * 4) + l4_offset;
638 /* remove payload length from inner pseudo checksum when tso*/
639 l4_paylen = skb->len - l4_offset;
640 csum_replace_by_diff(&l4.tcp->check,
641 (__force __wsum)htonl(l4_paylen));
643 /* find the txbd field values */
644 *paylen = skb->len - hdr_len;
645 hnae3_set_bit(*type_cs_vlan_tso,
648 /* get MSS for TSO */
649 *mss = skb_shinfo(skb)->gso_size;
654 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
662 unsigned char *l4_hdr;
663 unsigned char *exthdr;
667 /* find outer header point */
668 l3.hdr = skb_network_header(skb);
669 l4_hdr = skb_transport_header(skb);
671 if (skb->protocol == htons(ETH_P_IPV6)) {
672 exthdr = l3.hdr + sizeof(*l3.v6);
673 l4_proto_tmp = l3.v6->nexthdr;
674 if (l4_hdr != exthdr)
675 ipv6_skip_exthdr(skb, exthdr - skb->data,
676 &l4_proto_tmp, &frag_off);
677 } else if (skb->protocol == htons(ETH_P_IP)) {
678 l4_proto_tmp = l3.v4->protocol;
683 *ol4_proto = l4_proto_tmp;
686 if (!skb->encapsulation) {
691 /* find inner header point */
692 l3.hdr = skb_inner_network_header(skb);
693 l4_hdr = skb_inner_transport_header(skb);
695 if (l3.v6->version == 6) {
696 exthdr = l3.hdr + sizeof(*l3.v6);
697 l4_proto_tmp = l3.v6->nexthdr;
698 if (l4_hdr != exthdr)
699 ipv6_skip_exthdr(skb, exthdr - skb->data,
700 &l4_proto_tmp, &frag_off);
701 } else if (l3.v4->version == 4) {
702 l4_proto_tmp = l3.v4->protocol;
705 *il4_proto = l4_proto_tmp;
710 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
711 u8 il4_proto, u32 *type_cs_vlan_tso,
712 u32 *ol_type_vlan_len_msec)
722 struct gre_base_hdr *gre;
725 unsigned char *l2_hdr;
726 u8 l4_proto = ol4_proto;
733 l3.hdr = skb_network_header(skb);
734 l4.hdr = skb_transport_header(skb);
736 /* compute L2 header size for normal packet, defined in 2 Bytes */
737 l2_len = l3.hdr - skb->data;
738 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
739 HNS3_TXD_L2LEN_S, l2_len >> 1);
742 if (skb->encapsulation) {
743 /* compute OL2 header size, defined in 2 Bytes */
745 hnae3_set_field(*ol_type_vlan_len_msec,
747 HNS3_TXD_L2LEN_S, ol2_len >> 1);
749 /* compute OL3 header size, defined in 4 Bytes */
750 ol3_len = l4.hdr - l3.hdr;
751 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
752 HNS3_TXD_L3LEN_S, ol3_len >> 2);
754 /* MAC in UDP, MAC in GRE (0x6558)*/
755 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
756 /* switch MAC header ptr from outer to inner header.*/
757 l2_hdr = skb_inner_mac_header(skb);
759 /* compute OL4 header size, defined in 4 Bytes. */
760 ol4_len = l2_hdr - l4.hdr;
761 hnae3_set_field(*ol_type_vlan_len_msec,
762 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
765 /* switch IP header ptr from outer to inner header */
766 l3.hdr = skb_inner_network_header(skb);
768 /* compute inner l2 header size, defined in 2 Bytes. */
769 l2_len = l3.hdr - l2_hdr;
770 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
771 HNS3_TXD_L2LEN_S, l2_len >> 1);
773 /* skb packet types not supported by hardware,
774 * txbd len fild doesn't be filled.
779 /* switch L4 header pointer from outer to inner */
780 l4.hdr = skb_inner_transport_header(skb);
782 l4_proto = il4_proto;
785 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
786 l3_len = l4.hdr - l3.hdr;
787 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
788 HNS3_TXD_L3LEN_S, l3_len >> 2);
790 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
793 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
794 HNS3_TXD_L4LEN_S, l4.tcp->doff);
797 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
799 (sizeof(struct sctphdr) >> 2));
802 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
804 (sizeof(struct udphdr) >> 2));
807 /* skb packet types not supported by hardware,
808 * txbd len fild doesn't be filled.
814 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
815 * and it is udp packet, which has a dest port as the IANA assigned.
816 * the hardware is expected to do the checksum offload, but the
817 * hardware will not do the checksum offload when udp dest port is
820 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
822 #define IANA_VXLAN_PORT 4789
826 struct gre_base_hdr *gre;
830 l4.hdr = skb_transport_header(skb);
832 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
835 skb_checksum_help(skb);
840 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
841 u8 il4_proto, u32 *type_cs_vlan_tso,
842 u32 *ol_type_vlan_len_msec)
849 u32 l4_proto = ol4_proto;
851 l3.hdr = skb_network_header(skb);
853 /* define OL3 type and tunnel type(OL4).*/
854 if (skb->encapsulation) {
855 /* define outer network header type.*/
856 if (skb->protocol == htons(ETH_P_IP)) {
858 hnae3_set_field(*ol_type_vlan_len_msec,
861 HNS3_OL3T_IPV4_CSUM);
863 hnae3_set_field(*ol_type_vlan_len_msec,
866 HNS3_OL3T_IPV4_NO_CSUM);
868 } else if (skb->protocol == htons(ETH_P_IPV6)) {
869 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
870 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
873 /* define tunnel type(OL4).*/
876 hnae3_set_field(*ol_type_vlan_len_msec,
879 HNS3_TUN_MAC_IN_UDP);
882 hnae3_set_field(*ol_type_vlan_len_msec,
888 /* drop the skb tunnel packet if hardware don't support,
889 * because hardware can't calculate csum when TSO.
894 /* the stack computes the IP header already,
895 * driver calculate l4 checksum when not TSO.
897 skb_checksum_help(skb);
901 l3.hdr = skb_inner_network_header(skb);
902 l4_proto = il4_proto;
905 if (l3.v4->version == 4) {
906 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
907 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
909 /* the stack computes the IP header already, the only time we
910 * need the hardware to recompute it is in the case of TSO.
913 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
914 } else if (l3.v6->version == 6) {
915 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
916 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
921 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
922 hnae3_set_field(*type_cs_vlan_tso,
928 if (hns3_tunnel_csum_bug(skb))
931 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
932 hnae3_set_field(*type_cs_vlan_tso,
938 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
939 hnae3_set_field(*type_cs_vlan_tso,
945 /* drop the skb tunnel packet if hardware don't support,
946 * because hardware can't calculate csum when TSO.
951 /* the stack computes the IP header already,
952 * driver calculate l4 checksum when not TSO.
954 skb_checksum_help(skb);
961 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
963 /* Config bd buffer end */
964 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
965 HNS3_TXD_BDTYPE_S, 0);
966 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
967 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
968 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
971 static int hns3_fill_desc_vtags(struct sk_buff *skb,
972 struct hns3_enet_ring *tx_ring,
973 u32 *inner_vlan_flag,
978 #define HNS3_TX_VLAN_PRIO_SHIFT 13
980 if (skb->protocol == htons(ETH_P_8021Q) &&
981 !(tx_ring->tqp->handle->kinfo.netdev->features &
982 NETIF_F_HW_VLAN_CTAG_TX)) {
983 /* When HW VLAN acceleration is turned off, and the stack
984 * sets the protocol to 802.1q, the driver just need to
985 * set the protocol to the encapsulated ethertype.
987 skb->protocol = vlan_get_protocol(skb);
991 if (skb_vlan_tag_present(skb)) {
994 vlan_tag = skb_vlan_tag_get(skb);
995 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
997 /* Based on hw strategy, use out_vtag in two layer tag case,
998 * and use inner_vtag in one tag case.
1000 if (skb->protocol == htons(ETH_P_8021Q)) {
1001 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
1002 *out_vtag = vlan_tag;
1004 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
1005 *inner_vtag = vlan_tag;
1007 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1008 struct vlan_ethhdr *vhdr;
1011 rc = skb_cow_head(skb, 0);
1014 vhdr = (struct vlan_ethhdr *)skb->data;
1015 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1016 << HNS3_TX_VLAN_PRIO_SHIFT);
1019 skb->protocol = vlan_get_protocol(skb);
1023 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1024 int size, int frag_end, enum hns_desc_type type)
1026 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1027 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1028 struct device *dev = ring_to_dev(ring);
1029 u32 ol_type_vlan_len_msec = 0;
1030 u16 bdtp_fe_sc_vld_ra_ri = 0;
1031 struct skb_frag_struct *frag;
1032 unsigned int frag_buf_num;
1033 u32 type_cs_vlan_tso = 0;
1034 struct sk_buff *skb;
1046 if (type == DESC_TYPE_SKB) {
1047 skb = (struct sk_buff *)priv;
1050 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1051 &ol_type_vlan_len_msec,
1052 &inner_vtag, &out_vtag);
1056 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1057 skb_reset_mac_len(skb);
1059 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1062 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
1064 &ol_type_vlan_len_msec);
1065 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
1067 &ol_type_vlan_len_msec);
1071 ret = hns3_set_tso(skb, &paylen, &mss,
1078 desc->tx.ol_type_vlan_len_msec =
1079 cpu_to_le32(ol_type_vlan_len_msec);
1080 desc->tx.type_cs_vlan_tso_len =
1081 cpu_to_le32(type_cs_vlan_tso);
1082 desc->tx.paylen = cpu_to_le32(paylen);
1083 desc->tx.mss = cpu_to_le16(mss);
1084 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1085 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1087 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1089 frag = (struct skb_frag_struct *)priv;
1090 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1093 if (dma_mapping_error(ring->dev, dma)) {
1094 ring->stats.sw_err_cnt++;
1098 desc_cb->length = size;
1100 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1101 sizeoflast = size % HNS3_MAX_BD_SIZE;
1102 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1104 /* When frag size is bigger than hardware limit, split this frag */
1105 for (k = 0; k < frag_buf_num; k++) {
1106 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1107 desc_cb->priv = priv;
1108 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1109 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1110 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1112 /* now, fill the descriptor */
1113 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1114 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1115 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1116 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1117 frag_end && (k == frag_buf_num - 1) ?
1119 desc->tx.bdtp_fe_sc_vld_ra_ri =
1120 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1122 /* move ring pointer to next.*/
1123 ring_ptr_move_fw(ring, next_to_use);
1125 desc_cb = &ring->desc_cb[ring->next_to_use];
1126 desc = &ring->desc[ring->next_to_use];
1132 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1133 struct hns3_enet_ring *ring)
1135 struct sk_buff *skb = *out_skb;
1136 struct skb_frag_struct *frag;
1143 size = skb_headlen(skb);
1144 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1146 frag_num = skb_shinfo(skb)->nr_frags;
1147 for (i = 0; i < frag_num; i++) {
1148 frag = &skb_shinfo(skb)->frags[i];
1149 size = skb_frag_size(frag);
1151 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1152 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1155 buf_num += bdnum_for_frag;
1158 if (buf_num > ring_space(ring))
1165 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1166 struct hns3_enet_ring *ring)
1168 struct sk_buff *skb = *out_skb;
1171 /* No. of segments (plus a header) */
1172 buf_num = skb_shinfo(skb)->nr_frags + 1;
1174 if (unlikely(ring_space(ring) < buf_num))
1182 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1184 struct device *dev = ring_to_dev(ring);
1187 for (i = 0; i < ring->desc_num; i++) {
1188 /* check if this is where we started */
1189 if (ring->next_to_use == next_to_use_orig)
1192 /* unmap the descriptor dma address */
1193 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1194 dma_unmap_single(dev,
1195 ring->desc_cb[ring->next_to_use].dma,
1196 ring->desc_cb[ring->next_to_use].length,
1198 else if (ring->desc_cb[ring->next_to_use].length)
1200 ring->desc_cb[ring->next_to_use].dma,
1201 ring->desc_cb[ring->next_to_use].length,
1204 ring->desc_cb[ring->next_to_use].length = 0;
1207 ring_ptr_move_bw(ring, next_to_use);
1211 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1213 struct hns3_nic_priv *priv = netdev_priv(netdev);
1214 struct hns3_nic_ring_data *ring_data =
1215 &tx_ring_data(priv, skb->queue_mapping);
1216 struct hns3_enet_ring *ring = ring_data->ring;
1217 struct netdev_queue *dev_queue;
1218 struct skb_frag_struct *frag;
1219 int next_to_use_head;
1220 int next_to_use_frag;
1227 /* Prefetch the data used later */
1228 prefetch(skb->data);
1230 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1232 u64_stats_update_begin(&ring->syncp);
1233 ring->stats.tx_busy++;
1234 u64_stats_update_end(&ring->syncp);
1236 goto out_net_tx_busy;
1238 u64_stats_update_begin(&ring->syncp);
1239 ring->stats.sw_err_cnt++;
1240 u64_stats_update_end(&ring->syncp);
1241 netdev_err(netdev, "no memory to xmit!\n");
1248 /* No. of segments (plus a header) */
1249 seg_num = skb_shinfo(skb)->nr_frags + 1;
1250 /* Fill the first part */
1251 size = skb_headlen(skb);
1253 next_to_use_head = ring->next_to_use;
1255 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1260 next_to_use_frag = ring->next_to_use;
1261 /* Fill the fragments */
1262 for (i = 1; i < seg_num; i++) {
1263 frag = &skb_shinfo(skb)->frags[i - 1];
1264 size = skb_frag_size(frag);
1266 ret = priv->ops.fill_desc(ring, frag, size,
1267 seg_num - 1 == i ? 1 : 0,
1274 /* Complete translate all packets */
1275 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1276 netdev_tx_sent_queue(dev_queue, skb->len);
1278 wmb(); /* Commit all data before submit */
1280 hnae3_queue_xmit(ring->tqp, buf_num);
1282 return NETDEV_TX_OK;
1285 hns3_clear_desc(ring, next_to_use_frag);
1288 hns3_clear_desc(ring, next_to_use_head);
1291 dev_kfree_skb_any(skb);
1292 return NETDEV_TX_OK;
1295 netif_stop_subqueue(netdev, ring_data->queue_index);
1296 smp_mb(); /* Commit all data before submit */
1298 return NETDEV_TX_BUSY;
1301 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1303 struct hnae3_handle *h = hns3_get_handle(netdev);
1304 struct sockaddr *mac_addr = p;
1307 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1308 return -EADDRNOTAVAIL;
1310 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1311 netdev_info(netdev, "already using mac address %pM\n",
1316 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1318 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1322 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1327 static int hns3_nic_do_ioctl(struct net_device *netdev,
1328 struct ifreq *ifr, int cmd)
1330 struct hnae3_handle *h = hns3_get_handle(netdev);
1332 if (!netif_running(netdev))
1335 if (!h->ae_algo->ops->do_ioctl)
1338 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1341 static int hns3_nic_set_features(struct net_device *netdev,
1342 netdev_features_t features)
1344 netdev_features_t changed = netdev->features ^ features;
1345 struct hns3_nic_priv *priv = netdev_priv(netdev);
1346 struct hnae3_handle *h = priv->ae_handle;
1349 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1350 if (features & (NETIF_F_TSO | NETIF_F_TSO6))
1351 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1353 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1356 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1357 if (features & NETIF_F_GRO_HW)
1358 ret = h->ae_algo->ops->set_gro_en(h, true);
1360 ret = h->ae_algo->ops->set_gro_en(h, false);
1365 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1366 h->ae_algo->ops->enable_vlan_filter) {
1367 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1368 h->ae_algo->ops->enable_vlan_filter(h, true);
1370 h->ae_algo->ops->enable_vlan_filter(h, false);
1373 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1374 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1375 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1376 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1378 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1384 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1385 if (features & NETIF_F_NTUPLE)
1386 h->ae_algo->ops->enable_fd(h, true);
1388 h->ae_algo->ops->enable_fd(h, false);
1391 netdev->features = features;
1395 static void hns3_nic_get_stats64(struct net_device *netdev,
1396 struct rtnl_link_stats64 *stats)
1398 struct hns3_nic_priv *priv = netdev_priv(netdev);
1399 int queue_num = priv->ae_handle->kinfo.num_tqps;
1400 struct hnae3_handle *handle = priv->ae_handle;
1401 struct hns3_enet_ring *ring;
1411 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1414 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1416 for (idx = 0; idx < queue_num; idx++) {
1417 /* fetch the tx stats */
1418 ring = priv->ring_data[idx].ring;
1420 start = u64_stats_fetch_begin_irq(&ring->syncp);
1421 tx_bytes += ring->stats.tx_bytes;
1422 tx_pkts += ring->stats.tx_pkts;
1423 tx_drop += ring->stats.tx_busy;
1424 tx_drop += ring->stats.sw_err_cnt;
1425 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1427 /* fetch the rx stats */
1428 ring = priv->ring_data[idx + queue_num].ring;
1430 start = u64_stats_fetch_begin_irq(&ring->syncp);
1431 rx_bytes += ring->stats.rx_bytes;
1432 rx_pkts += ring->stats.rx_pkts;
1433 rx_drop += ring->stats.non_vld_descs;
1434 rx_drop += ring->stats.err_pkt_len;
1435 rx_drop += ring->stats.l2_err;
1436 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1439 stats->tx_bytes = tx_bytes;
1440 stats->tx_packets = tx_pkts;
1441 stats->rx_bytes = rx_bytes;
1442 stats->rx_packets = rx_pkts;
1444 stats->rx_errors = netdev->stats.rx_errors;
1445 stats->multicast = netdev->stats.multicast;
1446 stats->rx_length_errors = netdev->stats.rx_length_errors;
1447 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1448 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1450 stats->tx_errors = netdev->stats.tx_errors;
1451 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1452 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
1453 stats->collisions = netdev->stats.collisions;
1454 stats->rx_over_errors = netdev->stats.rx_over_errors;
1455 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1456 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1457 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1458 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1459 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1460 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1461 stats->tx_window_errors = netdev->stats.tx_window_errors;
1462 stats->rx_compressed = netdev->stats.rx_compressed;
1463 stats->tx_compressed = netdev->stats.tx_compressed;
1466 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1468 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1469 struct hnae3_handle *h = hns3_get_handle(netdev);
1470 struct hnae3_knic_private_info *kinfo = &h->kinfo;
1471 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1472 u8 tc = mqprio_qopt->qopt.num_tc;
1473 u16 mode = mqprio_qopt->mode;
1474 u8 hw = mqprio_qopt->qopt.hw;
1478 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1479 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1482 if (tc > HNAE3_MAX_TC)
1488 if_running = netif_running(netdev);
1490 hns3_nic_net_stop(netdev);
1494 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1495 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
1499 ret = hns3_nic_set_real_num_queue(netdev);
1503 hns3_nic_net_open(netdev);
1508 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1511 if (type != TC_SETUP_QDISC_MQPRIO)
1514 return hns3_setup_tc(dev, type_data);
1517 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1518 __be16 proto, u16 vid)
1520 struct hnae3_handle *h = hns3_get_handle(netdev);
1521 struct hns3_nic_priv *priv = netdev_priv(netdev);
1524 if (h->ae_algo->ops->set_vlan_filter)
1525 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1528 set_bit(vid, priv->active_vlans);
1533 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1534 __be16 proto, u16 vid)
1536 struct hnae3_handle *h = hns3_get_handle(netdev);
1537 struct hns3_nic_priv *priv = netdev_priv(netdev);
1540 if (h->ae_algo->ops->set_vlan_filter)
1541 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1544 clear_bit(vid, priv->active_vlans);
1549 static int hns3_restore_vlan(struct net_device *netdev)
1551 struct hns3_nic_priv *priv = netdev_priv(netdev);
1555 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1556 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1558 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1567 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1568 u8 qos, __be16 vlan_proto)
1570 struct hnae3_handle *h = hns3_get_handle(netdev);
1573 if (h->ae_algo->ops->set_vf_vlan_filter)
1574 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1580 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1582 struct hnae3_handle *h = hns3_get_handle(netdev);
1585 if (!h->ae_algo->ops->set_mtu)
1588 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1590 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1593 netdev->mtu = new_mtu;
1598 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1600 struct hns3_nic_priv *priv = netdev_priv(ndev);
1601 struct hns3_enet_ring *tx_ring = NULL;
1602 int timeout_queue = 0;
1603 int hw_head, hw_tail;
1606 /* Find the stopped queue the same way the stack does */
1607 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1608 struct netdev_queue *q;
1609 unsigned long trans_start;
1611 q = netdev_get_tx_queue(ndev, i);
1612 trans_start = q->trans_start;
1613 if (netif_xmit_stopped(q) &&
1615 (trans_start + ndev->watchdog_timeo))) {
1621 if (i == ndev->num_tx_queues) {
1623 "no netdev TX timeout queue found, timeout count: %llu\n",
1624 priv->tx_timeout_count);
1628 tx_ring = priv->ring_data[timeout_queue].ring;
1630 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1631 HNS3_RING_TX_RING_HEAD_REG);
1632 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1633 HNS3_RING_TX_RING_TAIL_REG);
1635 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1636 priv->tx_timeout_count,
1638 tx_ring->next_to_use,
1639 tx_ring->next_to_clean,
1642 readl(tx_ring->tqp_vector->mask_addr));
1647 static void hns3_nic_net_timeout(struct net_device *ndev)
1649 struct hns3_nic_priv *priv = netdev_priv(ndev);
1650 struct hnae3_handle *h = priv->ae_handle;
1652 if (!hns3_get_tx_timeo_queue_info(ndev))
1655 priv->tx_timeout_count++;
1657 /* request the reset, and let the hclge to determine
1658 * which reset level should be done
1660 if (h->ae_algo->ops->reset_event)
1661 h->ae_algo->ops->reset_event(h->pdev, h);
1664 static const struct net_device_ops hns3_nic_netdev_ops = {
1665 .ndo_open = hns3_nic_net_open,
1666 .ndo_stop = hns3_nic_net_stop,
1667 .ndo_start_xmit = hns3_nic_net_xmit,
1668 .ndo_tx_timeout = hns3_nic_net_timeout,
1669 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
1670 .ndo_do_ioctl = hns3_nic_do_ioctl,
1671 .ndo_change_mtu = hns3_nic_change_mtu,
1672 .ndo_set_features = hns3_nic_set_features,
1673 .ndo_get_stats64 = hns3_nic_get_stats64,
1674 .ndo_setup_tc = hns3_nic_setup_tc,
1675 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
1676 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1677 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1678 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1681 static bool hns3_is_phys_func(struct pci_dev *pdev)
1683 u32 dev_id = pdev->device;
1686 case HNAE3_DEV_ID_GE:
1687 case HNAE3_DEV_ID_25GE:
1688 case HNAE3_DEV_ID_25GE_RDMA:
1689 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1690 case HNAE3_DEV_ID_50GE_RDMA:
1691 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1692 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1694 case HNAE3_DEV_ID_100G_VF:
1695 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1698 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1705 static void hns3_disable_sriov(struct pci_dev *pdev)
1707 /* If our VFs are assigned we cannot shut down SR-IOV
1708 * without causing issues, so just leave the hardware
1709 * available but disabled
1711 if (pci_vfs_assigned(pdev)) {
1712 dev_warn(&pdev->dev,
1713 "disabling driver while VFs are assigned\n");
1717 pci_disable_sriov(pdev);
1720 static void hns3_get_dev_capability(struct pci_dev *pdev,
1721 struct hnae3_ae_dev *ae_dev)
1723 if (pdev->revision >= 0x21) {
1724 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
1725 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1729 /* hns3_probe - Device initialization routine
1730 * @pdev: PCI device information struct
1731 * @ent: entry in hns3_pci_tbl
1733 * hns3_probe initializes a PF identified by a pci_dev structure.
1734 * The OS initialization, configuring of the PF private structure,
1735 * and a hardware reset occur.
1737 * Returns 0 on success, negative on failure
1739 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1741 struct hnae3_ae_dev *ae_dev;
1744 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1751 ae_dev->pdev = pdev;
1752 ae_dev->flag = ent->driver_data;
1753 ae_dev->dev_type = HNAE3_DEV_KNIC;
1754 ae_dev->reset_type = HNAE3_NONE_RESET;
1755 hns3_get_dev_capability(pdev, ae_dev);
1756 pci_set_drvdata(pdev, ae_dev);
1758 hnae3_register_ae_dev(ae_dev);
1763 /* hns3_remove - Device removal routine
1764 * @pdev: PCI device information struct
1766 static void hns3_remove(struct pci_dev *pdev)
1768 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1770 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1771 hns3_disable_sriov(pdev);
1773 hnae3_unregister_ae_dev(ae_dev);
1777 * hns3_pci_sriov_configure
1778 * @pdev: pointer to a pci_dev structure
1779 * @num_vfs: number of VFs to allocate
1781 * Enable or change the number of VFs. Called when the user updates the number
1784 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
1788 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1789 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1794 ret = pci_enable_sriov(pdev, num_vfs);
1796 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
1799 } else if (!pci_vfs_assigned(pdev)) {
1800 pci_disable_sriov(pdev);
1802 dev_warn(&pdev->dev,
1803 "Unable to free VFs because some are assigned to VMs.\n");
1809 static void hns3_shutdown(struct pci_dev *pdev)
1811 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1813 hnae3_unregister_ae_dev(ae_dev);
1814 devm_kfree(&pdev->dev, ae_dev);
1815 pci_set_drvdata(pdev, NULL);
1817 if (system_state == SYSTEM_POWER_OFF)
1818 pci_set_power_state(pdev, PCI_D3hot);
1821 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1822 pci_channel_state_t state)
1824 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1825 pci_ers_result_t ret;
1827 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1829 if (state == pci_channel_io_perm_failure)
1830 return PCI_ERS_RESULT_DISCONNECT;
1834 "Can't recover - error happened during device init\n");
1835 return PCI_ERS_RESULT_NONE;
1838 if (ae_dev->ops->handle_hw_ras_error)
1839 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
1841 return PCI_ERS_RESULT_NONE;
1846 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1848 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1849 struct device *dev = &pdev->dev;
1851 dev_info(dev, "requesting reset due to PCI error\n");
1853 /* request the reset */
1854 if (ae_dev->ops->reset_event) {
1855 ae_dev->ops->reset_event(pdev, NULL);
1856 return PCI_ERS_RESULT_RECOVERED;
1859 return PCI_ERS_RESULT_DISCONNECT;
1862 static void hns3_reset_prepare(struct pci_dev *pdev)
1864 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1866 dev_info(&pdev->dev, "hns3 flr prepare\n");
1867 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1868 ae_dev->ops->flr_prepare(ae_dev);
1871 static void hns3_reset_done(struct pci_dev *pdev)
1873 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1875 dev_info(&pdev->dev, "hns3 flr done\n");
1876 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1877 ae_dev->ops->flr_done(ae_dev);
1880 static const struct pci_error_handlers hns3_err_handler = {
1881 .error_detected = hns3_error_detected,
1882 .slot_reset = hns3_slot_reset,
1883 .reset_prepare = hns3_reset_prepare,
1884 .reset_done = hns3_reset_done,
1887 static struct pci_driver hns3_driver = {
1888 .name = hns3_driver_name,
1889 .id_table = hns3_pci_tbl,
1890 .probe = hns3_probe,
1891 .remove = hns3_remove,
1892 .shutdown = hns3_shutdown,
1893 .sriov_configure = hns3_pci_sriov_configure,
1894 .err_handler = &hns3_err_handler,
1897 /* set default feature to hns3 */
1898 static void hns3_set_default_feature(struct net_device *netdev)
1900 struct hnae3_handle *h = hns3_get_handle(netdev);
1901 struct pci_dev *pdev = h->pdev;
1903 netdev->priv_flags |= IFF_UNICAST_FLT;
1905 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1906 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1907 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1908 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1909 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1911 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1913 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1915 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1916 NETIF_F_HW_VLAN_CTAG_FILTER |
1917 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1918 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1919 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1920 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1921 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1923 netdev->vlan_features |=
1924 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1925 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1926 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1927 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1928 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1930 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1931 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1932 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1933 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1934 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1935 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1937 if (pdev->revision >= 0x21) {
1938 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER |
1940 netdev->features |= NETIF_F_GRO_HW;
1942 if (!(h->flags & HNAE3_SUPPORT_VF)) {
1943 netdev->hw_features |= NETIF_F_NTUPLE;
1944 netdev->features |= NETIF_F_NTUPLE;
1949 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1950 struct hns3_desc_cb *cb)
1952 unsigned int order = hnae3_page_order(ring);
1955 p = dev_alloc_pages(order);
1960 cb->page_offset = 0;
1962 cb->buf = page_address(p);
1963 cb->length = hnae3_page_size(ring);
1964 cb->type = DESC_TYPE_PAGE;
1969 static void hns3_free_buffer(struct hns3_enet_ring *ring,
1970 struct hns3_desc_cb *cb)
1972 if (cb->type == DESC_TYPE_SKB)
1973 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1974 else if (!HNAE3_IS_TX_RING(ring))
1975 put_page((struct page *)cb->priv);
1976 memset(cb, 0, sizeof(*cb));
1979 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1981 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1982 cb->length, ring_to_dma_dir(ring));
1984 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
1990 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1991 struct hns3_desc_cb *cb)
1993 if (cb->type == DESC_TYPE_SKB)
1994 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1995 ring_to_dma_dir(ring));
1996 else if (cb->length)
1997 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1998 ring_to_dma_dir(ring));
2001 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2003 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2004 ring->desc[i].addr = 0;
2007 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2009 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2011 if (!ring->desc_cb[i].dma)
2014 hns3_buffer_detach(ring, i);
2015 hns3_free_buffer(ring, cb);
2018 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2022 for (i = 0; i < ring->desc_num; i++)
2023 hns3_free_buffer_detach(ring, i);
2026 /* free desc along with its attached buffer */
2027 static void hns3_free_desc(struct hns3_enet_ring *ring)
2029 int size = ring->desc_num * sizeof(ring->desc[0]);
2031 hns3_free_buffers(ring);
2034 dma_free_coherent(ring_to_dev(ring), size,
2035 ring->desc, ring->desc_dma_addr);
2040 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2042 int size = ring->desc_num * sizeof(ring->desc[0]);
2044 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2045 &ring->desc_dma_addr, GFP_KERNEL);
2052 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2053 struct hns3_desc_cb *cb)
2057 ret = hns3_alloc_buffer(ring, cb);
2061 ret = hns3_map_buffer(ring, cb);
2068 hns3_free_buffer(ring, cb);
2073 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2075 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2080 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2085 /* Allocate memory for raw pkg, and map with dma */
2086 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2090 for (i = 0; i < ring->desc_num; i++) {
2091 ret = hns3_alloc_buffer_attach(ring, i);
2093 goto out_buffer_fail;
2099 for (j = i - 1; j >= 0; j--)
2100 hns3_free_buffer_detach(ring, j);
2104 /* detach a in-used buffer and replace with a reserved one */
2105 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2106 struct hns3_desc_cb *res_cb)
2108 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2109 ring->desc_cb[i] = *res_cb;
2110 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2111 ring->desc[i].rx.bd_base_info = 0;
2114 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2116 ring->desc_cb[i].reuse_flag = 0;
2117 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2118 + ring->desc_cb[i].page_offset);
2119 ring->desc[i].rx.bd_base_info = 0;
2122 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
2125 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2127 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2128 (*bytes) += desc_cb->length;
2129 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
2130 hns3_free_buffer_detach(ring, ring->next_to_clean);
2132 ring_ptr_move_fw(ring, next_to_clean);
2135 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2137 int u = ring->next_to_use;
2138 int c = ring->next_to_clean;
2140 if (unlikely(h > ring->desc_num))
2143 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2146 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2148 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2149 struct hns3_nic_priv *priv = netdev_priv(netdev);
2150 struct netdev_queue *dev_queue;
2154 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2155 rmb(); /* Make sure head is ready before touch any data */
2157 if (is_ring_empty(ring) || head == ring->next_to_clean)
2158 return; /* no data to poll */
2160 if (unlikely(!is_valid_clean_head(ring, head))) {
2161 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2162 ring->next_to_use, ring->next_to_clean);
2164 u64_stats_update_begin(&ring->syncp);
2165 ring->stats.io_err_cnt++;
2166 u64_stats_update_end(&ring->syncp);
2172 while (head != ring->next_to_clean) {
2173 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
2174 /* Issue prefetch for next Tx descriptor */
2175 prefetch(&ring->desc_cb[ring->next_to_clean]);
2178 ring->tqp_vector->tx_group.total_bytes += bytes;
2179 ring->tqp_vector->tx_group.total_packets += pkts;
2181 u64_stats_update_begin(&ring->syncp);
2182 ring->stats.tx_bytes += bytes;
2183 ring->stats.tx_pkts += pkts;
2184 u64_stats_update_end(&ring->syncp);
2186 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2187 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2189 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2190 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2191 /* Make sure that anybody stopping the queue after this
2192 * sees the new next_to_clean.
2195 if (netif_tx_queue_stopped(dev_queue) &&
2196 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2197 netif_tx_wake_queue(dev_queue);
2198 ring->stats.restart_queue++;
2203 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2205 int ntc = ring->next_to_clean;
2206 int ntu = ring->next_to_use;
2208 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2212 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2214 struct hns3_desc_cb *desc_cb;
2215 struct hns3_desc_cb res_cbs;
2218 for (i = 0; i < cleand_count; i++) {
2219 desc_cb = &ring->desc_cb[ring->next_to_use];
2220 if (desc_cb->reuse_flag) {
2221 u64_stats_update_begin(&ring->syncp);
2222 ring->stats.reuse_pg_cnt++;
2223 u64_stats_update_end(&ring->syncp);
2225 hns3_reuse_buffer(ring, ring->next_to_use);
2227 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2229 u64_stats_update_begin(&ring->syncp);
2230 ring->stats.sw_err_cnt++;
2231 u64_stats_update_end(&ring->syncp);
2233 netdev_err(ring->tqp->handle->kinfo.netdev,
2234 "hnae reserve buffer map failed.\n");
2237 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2240 ring_ptr_move_fw(ring, next_to_use);
2243 wmb(); /* Make all data has been write before submit */
2244 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2247 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2248 struct hns3_enet_ring *ring, int pull_len,
2249 struct hns3_desc_cb *desc_cb)
2251 struct hns3_desc *desc;
2257 twobufs = ((PAGE_SIZE < 8192) &&
2258 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
2260 desc = &ring->desc[ring->next_to_clean];
2261 size = le16_to_cpu(desc->rx.size);
2263 truesize = hnae3_buf_size(ring);
2266 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
2268 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2269 size - pull_len, truesize);
2271 /* Avoid re-using remote pages,flag default unreuse */
2272 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2276 /* If we are only owner of page we can reuse it */
2277 if (likely(page_count(desc_cb->priv) == 1)) {
2278 /* Flip page offset to other buffer */
2279 desc_cb->page_offset ^= truesize;
2281 desc_cb->reuse_flag = 1;
2282 /* bump ref count on page before it is given*/
2283 get_page(desc_cb->priv);
2288 /* Move offset up to the next cache line */
2289 desc_cb->page_offset += truesize;
2291 if (desc_cb->page_offset <= last_offset) {
2292 desc_cb->reuse_flag = 1;
2293 /* Bump ref count on page before it is given*/
2294 get_page(desc_cb->priv);
2298 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2299 struct hns3_desc *desc)
2301 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2302 int l3_type, l4_type;
2307 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2308 l234info = le32_to_cpu(desc->rx.l234_info);
2310 skb->ip_summed = CHECKSUM_NONE;
2312 skb_checksum_none_assert(skb);
2314 if (!(netdev->features & NETIF_F_RXCSUM))
2317 /* We MUST enable hardware checksum before enabling hardware GRO */
2318 if (skb_shinfo(skb)->gso_size) {
2319 skb->ip_summed = CHECKSUM_UNNECESSARY;
2323 /* check if hardware has done checksum */
2324 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
2327 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2328 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2329 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2330 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
2331 u64_stats_update_begin(&ring->syncp);
2332 ring->stats.l3l4_csum_err++;
2333 u64_stats_update_end(&ring->syncp);
2338 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2340 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2343 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2346 case HNS3_OL4_TYPE_MAC_IN_UDP:
2347 case HNS3_OL4_TYPE_NVGRE:
2348 skb->csum_level = 1;
2350 case HNS3_OL4_TYPE_NO_TUN:
2351 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2352 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2353 l3_type == HNS3_L3_TYPE_IPV6) &&
2354 (l4_type == HNS3_L4_TYPE_UDP ||
2355 l4_type == HNS3_L4_TYPE_TCP ||
2356 l4_type == HNS3_L4_TYPE_SCTP))
2357 skb->ip_summed = CHECKSUM_UNNECESSARY;
2364 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2366 if (skb_has_frag_list(skb))
2367 napi_gro_flush(&ring->tqp_vector->napi, false);
2369 napi_gro_receive(&ring->tqp_vector->napi, skb);
2372 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2373 struct hns3_desc *desc, u32 l234info,
2376 struct pci_dev *pdev = ring->tqp->handle->pdev;
2378 if (pdev->revision == 0x20) {
2379 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2380 if (!(*vlan_tag & VLAN_VID_MASK))
2381 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2383 return (*vlan_tag != 0);
2386 #define HNS3_STRP_OUTER_VLAN 0x1
2387 #define HNS3_STRP_INNER_VLAN 0x2
2389 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2390 HNS3_RXD_STRP_TAGP_S)) {
2391 case HNS3_STRP_OUTER_VLAN:
2392 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2394 case HNS3_STRP_INNER_VLAN:
2395 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2402 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2405 #define HNS3_NEED_ADD_FRAG 1
2406 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2407 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2408 struct sk_buff *skb;
2410 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2412 if (unlikely(!skb)) {
2413 netdev_err(netdev, "alloc rx skb fail\n");
2415 u64_stats_update_begin(&ring->syncp);
2416 ring->stats.sw_err_cnt++;
2417 u64_stats_update_end(&ring->syncp);
2422 prefetchw(skb->data);
2424 ring->pending_buf = 1;
2426 ring->tail_skb = NULL;
2427 if (length <= HNS3_RX_HEAD_SIZE) {
2428 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2430 /* We can reuse buffer as-is, just make sure it is local */
2431 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2432 desc_cb->reuse_flag = 1;
2433 else /* This page cannot be reused so discard it */
2434 put_page(desc_cb->priv);
2436 ring_ptr_move_fw(ring, next_to_clean);
2439 u64_stats_update_begin(&ring->syncp);
2440 ring->stats.seg_pkt_cnt++;
2441 u64_stats_update_end(&ring->syncp);
2443 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2444 __skb_put(skb, ring->pull_len);
2445 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2447 ring_ptr_move_fw(ring, next_to_clean);
2449 return HNS3_NEED_ADD_FRAG;
2452 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2453 struct sk_buff **out_skb, bool pending)
2455 struct sk_buff *skb = *out_skb;
2456 struct sk_buff *head_skb = *out_skb;
2457 struct sk_buff *new_skb;
2458 struct hns3_desc_cb *desc_cb;
2459 struct hns3_desc *pre_desc;
2463 /* if there is pending bd, the SW param next_to_clean has moved
2464 * to next and the next is NULL
2467 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2469 pre_desc = &ring->desc[pre_bd];
2470 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2472 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2475 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2476 desc = &ring->desc[ring->next_to_clean];
2477 desc_cb = &ring->desc_cb[ring->next_to_clean];
2478 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2479 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2482 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2483 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2485 if (unlikely(!new_skb)) {
2486 netdev_err(ring->tqp->handle->kinfo.netdev,
2487 "alloc rx skb frag fail\n");
2492 if (ring->tail_skb) {
2493 ring->tail_skb->next = new_skb;
2494 ring->tail_skb = new_skb;
2496 skb_shinfo(skb)->frag_list = new_skb;
2497 ring->tail_skb = new_skb;
2501 if (ring->tail_skb) {
2502 head_skb->truesize += hnae3_buf_size(ring);
2503 head_skb->data_len += le16_to_cpu(desc->rx.size);
2504 head_skb->len += le16_to_cpu(desc->rx.size);
2505 skb = ring->tail_skb;
2508 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2509 ring_ptr_move_fw(ring, next_to_clean);
2510 ring->pending_buf++;
2516 static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info,
2522 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2523 HNS3_RXD_GRO_COUNT_S);
2524 /* if there is no HW GRO, do not set gro params */
2528 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
2529 * to skb_shinfo(skb)->gso_segs
2531 NAPI_GRO_CB(skb)->count = gro_count;
2533 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2535 if (l3_type == HNS3_L3_TYPE_IPV4)
2536 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2537 else if (l3_type == HNS3_L3_TYPE_IPV6)
2538 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2542 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2543 HNS3_RXD_GRO_SIZE_M,
2544 HNS3_RXD_GRO_SIZE_S);
2545 if (skb_shinfo(skb)->gso_size)
2546 tcp_gro_complete(skb);
2549 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2550 struct sk_buff *skb)
2552 struct hnae3_handle *handle = ring->tqp->handle;
2553 enum pkt_hash_types rss_type;
2554 struct hns3_desc *desc;
2557 /* When driver handle the rss type, ring->next_to_clean indicates the
2558 * first descriptor of next packet, need -1 here.
2560 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num;
2561 desc = &ring->desc[last_bd];
2563 if (le32_to_cpu(desc->rx.rss_hash))
2564 rss_type = handle->kinfo.rss_type;
2566 rss_type = PKT_HASH_TYPE_NONE;
2568 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type);
2571 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2572 struct sk_buff **out_skb)
2574 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2575 struct sk_buff *skb = ring->skb;
2576 struct hns3_desc_cb *desc_cb;
2577 struct hns3_desc *desc;
2583 desc = &ring->desc[ring->next_to_clean];
2584 desc_cb = &ring->desc_cb[ring->next_to_clean];
2588 length = le16_to_cpu(desc->rx.size);
2589 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2591 /* Check valid BD */
2592 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
2596 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2598 /* Prefetch first cache line of first page
2599 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2600 * line size is 64B so need to prefetch twice to make it 128B. But in
2601 * actual we can have greater size of caches with 128B Level 1 cache
2602 * lines. In such a case, single fetch would suffice to cache in the
2603 * relevant part of the header.
2606 #if L1_CACHE_BYTES < 128
2607 prefetch(ring->va + L1_CACHE_BYTES);
2611 ret = hns3_alloc_skb(ring, length, ring->va);
2612 *out_skb = skb = ring->skb;
2614 if (ret < 0) /* alloc buffer fail */
2616 if (ret > 0) { /* need add frag */
2617 ret = hns3_add_frag(ring, desc, &skb, false);
2621 /* As the head data may be changed when GRO enable, copy
2622 * the head data in after other data rx completed
2624 memcpy(skb->data, ring->va,
2625 ALIGN(ring->pull_len, sizeof(long)));
2628 ret = hns3_add_frag(ring, desc, &skb, true);
2632 /* As the head data may be changed when GRO enable, copy
2633 * the head data in after other data rx completed
2635 memcpy(skb->data, ring->va,
2636 ALIGN(ring->pull_len, sizeof(long)));
2639 l234info = le32_to_cpu(desc->rx.l234_info);
2640 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2642 /* Based on hw strategy, the tag offloaded will be stored at
2643 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2644 * in one layer tag case.
2646 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2649 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2650 __vlan_hwaccel_put_tag(skb,
2655 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
2656 u64_stats_update_begin(&ring->syncp);
2657 ring->stats.non_vld_descs++;
2658 u64_stats_update_end(&ring->syncp);
2660 dev_kfree_skb_any(skb);
2664 if (unlikely((!desc->rx.pkt_len) ||
2665 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
2666 u64_stats_update_begin(&ring->syncp);
2667 ring->stats.err_pkt_len++;
2668 u64_stats_update_end(&ring->syncp);
2670 dev_kfree_skb_any(skb);
2674 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
2675 u64_stats_update_begin(&ring->syncp);
2676 ring->stats.l2_err++;
2677 u64_stats_update_end(&ring->syncp);
2679 dev_kfree_skb_any(skb);
2683 u64_stats_update_begin(&ring->syncp);
2684 ring->stats.rx_pkts++;
2685 ring->stats.rx_bytes += skb->len;
2686 u64_stats_update_end(&ring->syncp);
2688 ring->tqp_vector->rx_group.total_bytes += skb->len;
2690 /* This is needed in order to enable forwarding support */
2691 hns3_set_gro_param(skb, l234info, bd_base_info);
2693 hns3_rx_checksum(ring, skb, desc);
2695 hns3_set_rx_skb_rss_type(ring, skb);
2700 int hns3_clean_rx_ring(
2701 struct hns3_enet_ring *ring, int budget,
2702 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
2704 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2705 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2706 int recv_pkts, recv_bds, clean_count, err;
2707 int unused_count = hns3_desc_unused(ring) - ring->pending_buf;
2708 struct sk_buff *skb = ring->skb;
2711 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2712 rmb(); /* Make sure num taken effect before the other data is touched */
2714 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2715 num -= unused_count;
2717 while (recv_pkts < budget && recv_bds < num) {
2718 /* Reuse or realloc buffers */
2719 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2720 hns3_nic_alloc_rx_buffers(ring,
2721 clean_count + unused_count);
2723 unused_count = hns3_desc_unused(ring) -
2728 err = hns3_handle_rx_bd(ring, &skb);
2729 if (unlikely(!skb)) /* This fault cannot be repaired */
2732 if (err == -ENXIO) { /* Do not get FE for the packet */
2734 } else if (unlikely(err)) { /* Do jump the err */
2735 recv_bds += ring->pending_buf;
2736 clean_count += ring->pending_buf;
2738 ring->pending_buf = 0;
2742 /* Do update ip stack process */
2743 skb->protocol = eth_type_trans(skb, netdev);
2745 recv_bds += ring->pending_buf;
2746 clean_count += ring->pending_buf;
2748 ring->pending_buf = 0;
2754 /* Make all data has been write before submit */
2755 if (clean_count + unused_count > 0)
2756 hns3_nic_alloc_rx_buffers(ring,
2757 clean_count + unused_count);
2762 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2764 struct hns3_enet_tqp_vector *tqp_vector =
2765 ring_group->ring->tqp_vector;
2766 enum hns3_flow_level_range new_flow_level;
2767 int packets_per_msecs;
2768 int bytes_per_msecs;
2772 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
2775 if (ring_group->total_packets == 0) {
2776 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2777 ring_group->coal.flow_level = HNS3_FLOW_LOW;
2781 /* Simple throttlerate management
2782 * 0-10MB/s lower (50000 ints/s)
2783 * 10-20MB/s middle (20000 ints/s)
2784 * 20-1249MB/s high (18000 ints/s)
2785 * > 40000pps ultra (8000 ints/s)
2787 new_flow_level = ring_group->coal.flow_level;
2788 new_int_gl = ring_group->coal.int_gl;
2790 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2792 if (!time_passed_ms)
2795 do_div(ring_group->total_packets, time_passed_ms);
2796 packets_per_msecs = ring_group->total_packets;
2798 do_div(ring_group->total_bytes, time_passed_ms);
2799 bytes_per_msecs = ring_group->total_bytes;
2801 #define HNS3_RX_LOW_BYTE_RATE 10000
2802 #define HNS3_RX_MID_BYTE_RATE 20000
2804 switch (new_flow_level) {
2806 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
2807 new_flow_level = HNS3_FLOW_MID;
2810 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
2811 new_flow_level = HNS3_FLOW_HIGH;
2812 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
2813 new_flow_level = HNS3_FLOW_LOW;
2815 case HNS3_FLOW_HIGH:
2816 case HNS3_FLOW_ULTRA:
2818 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
2819 new_flow_level = HNS3_FLOW_MID;
2823 #define HNS3_RX_ULTRA_PACKET_RATE 40
2825 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2826 &tqp_vector->rx_group == ring_group)
2827 new_flow_level = HNS3_FLOW_ULTRA;
2829 switch (new_flow_level) {
2831 new_int_gl = HNS3_INT_GL_50K;
2834 new_int_gl = HNS3_INT_GL_20K;
2836 case HNS3_FLOW_HIGH:
2837 new_int_gl = HNS3_INT_GL_18K;
2839 case HNS3_FLOW_ULTRA:
2840 new_int_gl = HNS3_INT_GL_8K;
2846 ring_group->total_bytes = 0;
2847 ring_group->total_packets = 0;
2848 ring_group->coal.flow_level = new_flow_level;
2849 if (new_int_gl != ring_group->coal.int_gl) {
2850 ring_group->coal.int_gl = new_int_gl;
2856 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2858 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2859 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2860 bool rx_update, tx_update;
2862 /* update param every 1000ms */
2863 if (time_before(jiffies,
2864 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
2867 if (rx_group->coal.gl_adapt_enable) {
2868 rx_update = hns3_get_new_int_gl(rx_group);
2870 hns3_set_vector_coalesce_rx_gl(tqp_vector,
2871 rx_group->coal.int_gl);
2874 if (tx_group->coal.gl_adapt_enable) {
2875 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2877 hns3_set_vector_coalesce_tx_gl(tqp_vector,
2878 tx_group->coal.int_gl);
2881 tqp_vector->last_jiffies = jiffies;
2884 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2886 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
2887 struct hns3_enet_ring *ring;
2888 int rx_pkt_total = 0;
2890 struct hns3_enet_tqp_vector *tqp_vector =
2891 container_of(napi, struct hns3_enet_tqp_vector, napi);
2892 bool clean_complete = true;
2895 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2896 napi_complete(napi);
2900 /* Since the actual Tx work is minimal, we can give the Tx a larger
2901 * budget and be more aggressive about cleaning up the Tx descriptors.
2903 hns3_for_each_ring(ring, tqp_vector->tx_group)
2904 hns3_clean_tx_ring(ring);
2906 /* make sure rx ring budget not smaller than 1 */
2907 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2909 hns3_for_each_ring(ring, tqp_vector->rx_group) {
2910 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2913 if (rx_cleaned >= rx_budget)
2914 clean_complete = false;
2916 rx_pkt_total += rx_cleaned;
2919 tqp_vector->rx_group.total_packets += rx_pkt_total;
2921 if (!clean_complete)
2924 if (napi_complete(napi) &&
2925 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2926 hns3_update_new_int_gl(tqp_vector);
2927 hns3_mask_vector_irq(tqp_vector, 1);
2930 return rx_pkt_total;
2933 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2934 struct hnae3_ring_chain_node *head)
2936 struct pci_dev *pdev = tqp_vector->handle->pdev;
2937 struct hnae3_ring_chain_node *cur_chain = head;
2938 struct hnae3_ring_chain_node *chain;
2939 struct hns3_enet_ring *tx_ring;
2940 struct hns3_enet_ring *rx_ring;
2942 tx_ring = tqp_vector->tx_group.ring;
2944 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
2945 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2946 HNAE3_RING_TYPE_TX);
2947 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2948 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
2950 cur_chain->next = NULL;
2952 while (tx_ring->next) {
2953 tx_ring = tx_ring->next;
2955 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2958 goto err_free_chain;
2960 cur_chain->next = chain;
2961 chain->tqp_index = tx_ring->tqp->tqp_index;
2962 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2963 HNAE3_RING_TYPE_TX);
2964 hnae3_set_field(chain->int_gl_idx,
2965 HNAE3_RING_GL_IDX_M,
2966 HNAE3_RING_GL_IDX_S,
2973 rx_ring = tqp_vector->rx_group.ring;
2974 if (!tx_ring && rx_ring) {
2975 cur_chain->next = NULL;
2976 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
2977 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2978 HNAE3_RING_TYPE_RX);
2979 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2980 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2982 rx_ring = rx_ring->next;
2986 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2988 goto err_free_chain;
2990 cur_chain->next = chain;
2991 chain->tqp_index = rx_ring->tqp->tqp_index;
2992 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2993 HNAE3_RING_TYPE_RX);
2994 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2995 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2999 rx_ring = rx_ring->next;
3005 cur_chain = head->next;
3007 chain = cur_chain->next;
3008 devm_kfree(&pdev->dev, cur_chain);
3016 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3017 struct hnae3_ring_chain_node *head)
3019 struct pci_dev *pdev = tqp_vector->handle->pdev;
3020 struct hnae3_ring_chain_node *chain_tmp, *chain;
3025 chain_tmp = chain->next;
3026 devm_kfree(&pdev->dev, chain);
3031 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3032 struct hns3_enet_ring *ring)
3034 ring->next = group->ring;
3040 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3042 struct pci_dev *pdev = priv->ae_handle->pdev;
3043 struct hns3_enet_tqp_vector *tqp_vector;
3044 int num_vectors = priv->vector_num;
3048 numa_node = dev_to_node(&pdev->dev);
3050 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3051 tqp_vector = &priv->tqp_vector[vector_i];
3052 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3053 &tqp_vector->affinity_mask);
3057 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3059 struct hnae3_ring_chain_node vector_ring_chain;
3060 struct hnae3_handle *h = priv->ae_handle;
3061 struct hns3_enet_tqp_vector *tqp_vector;
3065 hns3_nic_set_cpumask(priv);
3067 for (i = 0; i < priv->vector_num; i++) {
3068 tqp_vector = &priv->tqp_vector[i];
3069 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3070 tqp_vector->num_tqps = 0;
3073 for (i = 0; i < h->kinfo.num_tqps; i++) {
3074 u16 vector_i = i % priv->vector_num;
3075 u16 tqp_num = h->kinfo.num_tqps;
3077 tqp_vector = &priv->tqp_vector[vector_i];
3079 hns3_add_ring_to_group(&tqp_vector->tx_group,
3080 priv->ring_data[i].ring);
3082 hns3_add_ring_to_group(&tqp_vector->rx_group,
3083 priv->ring_data[i + tqp_num].ring);
3085 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3086 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
3087 tqp_vector->num_tqps++;
3090 for (i = 0; i < priv->vector_num; i++) {
3091 tqp_vector = &priv->tqp_vector[i];
3093 tqp_vector->rx_group.total_bytes = 0;
3094 tqp_vector->rx_group.total_packets = 0;
3095 tqp_vector->tx_group.total_bytes = 0;
3096 tqp_vector->tx_group.total_packets = 0;
3097 tqp_vector->handle = h;
3099 ret = hns3_get_vector_ring_chain(tqp_vector,
3100 &vector_ring_chain);
3104 ret = h->ae_algo->ops->map_ring_to_vector(h,
3105 tqp_vector->vector_irq, &vector_ring_chain);
3107 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3112 netif_napi_add(priv->netdev, &tqp_vector->napi,
3113 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3120 netif_napi_del(&priv->tqp_vector[i].napi);
3125 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3127 #define HNS3_VECTOR_PF_MAX_NUM 64
3129 struct hnae3_handle *h = priv->ae_handle;
3130 struct hns3_enet_tqp_vector *tqp_vector;
3131 struct hnae3_vector_info *vector;
3132 struct pci_dev *pdev = h->pdev;
3133 u16 tqp_num = h->kinfo.num_tqps;
3138 /* RSS size, cpu online and vector_num should be the same */
3139 /* Should consider 2p/4p later */
3140 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3141 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3143 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3148 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3150 priv->vector_num = vector_num;
3151 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3152 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3154 if (!priv->tqp_vector) {
3159 for (i = 0; i < priv->vector_num; i++) {
3160 tqp_vector = &priv->tqp_vector[i];
3161 tqp_vector->idx = i;
3162 tqp_vector->mask_addr = vector[i].io_addr;
3163 tqp_vector->vector_irq = vector[i].vector;
3164 hns3_vector_gl_rl_init(tqp_vector, priv);
3168 devm_kfree(&pdev->dev, vector);
3172 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3178 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3180 struct hnae3_ring_chain_node vector_ring_chain;
3181 struct hnae3_handle *h = priv->ae_handle;
3182 struct hns3_enet_tqp_vector *tqp_vector;
3185 for (i = 0; i < priv->vector_num; i++) {
3186 tqp_vector = &priv->tqp_vector[i];
3188 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3191 ret = hns3_get_vector_ring_chain(tqp_vector,
3192 &vector_ring_chain);
3196 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
3197 tqp_vector->vector_irq, &vector_ring_chain);
3201 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3203 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3204 irq_set_affinity_notifier(tqp_vector->vector_irq,
3206 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3207 free_irq(tqp_vector->vector_irq, tqp_vector);
3208 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
3211 hns3_clear_ring_group(&tqp_vector->rx_group);
3212 hns3_clear_ring_group(&tqp_vector->tx_group);
3213 netif_napi_del(&priv->tqp_vector[i].napi);
3219 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3221 struct hnae3_handle *h = priv->ae_handle;
3222 struct pci_dev *pdev = h->pdev;
3225 for (i = 0; i < priv->vector_num; i++) {
3226 struct hns3_enet_tqp_vector *tqp_vector;
3228 tqp_vector = &priv->tqp_vector[i];
3229 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3234 devm_kfree(&pdev->dev, priv->tqp_vector);
3238 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3241 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3242 int queue_num = priv->ae_handle->kinfo.num_tqps;
3243 int desc_num = priv->ae_handle->kinfo.num_desc;
3244 struct pci_dev *pdev = priv->ae_handle->pdev;
3245 struct hns3_enet_ring *ring;
3247 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3251 if (ring_type == HNAE3_RING_TYPE_TX) {
3252 ring_data[q->tqp_index].ring = ring;
3253 ring_data[q->tqp_index].queue_index = q->tqp_index;
3254 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3256 ring_data[q->tqp_index + queue_num].ring = ring;
3257 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
3258 ring->io_base = q->io_base;
3261 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3265 ring->desc_cb = NULL;
3266 ring->dev = priv->dev;
3267 ring->desc_dma_addr = 0;
3268 ring->buf_size = q->buf_size;
3269 ring->desc_num = desc_num;
3270 ring->next_to_use = 0;
3271 ring->next_to_clean = 0;
3276 static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3277 struct hns3_nic_priv *priv)
3281 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3285 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3287 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
3294 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3296 struct hnae3_handle *h = priv->ae_handle;
3297 struct pci_dev *pdev = h->pdev;
3300 priv->ring_data = devm_kzalloc(&pdev->dev,
3301 array3_size(h->kinfo.num_tqps,
3302 sizeof(*priv->ring_data),
3305 if (!priv->ring_data)
3308 for (i = 0; i < h->kinfo.num_tqps; i++) {
3309 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3317 devm_kfree(priv->dev, priv->ring_data[i].ring);
3318 devm_kfree(priv->dev,
3319 priv->ring_data[i + h->kinfo.num_tqps].ring);
3322 devm_kfree(&pdev->dev, priv->ring_data);
3326 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3328 struct hnae3_handle *h = priv->ae_handle;
3331 for (i = 0; i < h->kinfo.num_tqps; i++) {
3332 devm_kfree(priv->dev, priv->ring_data[i].ring);
3333 devm_kfree(priv->dev,
3334 priv->ring_data[i + h->kinfo.num_tqps].ring);
3336 devm_kfree(priv->dev, priv->ring_data);
3339 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3343 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3346 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
3348 if (!ring->desc_cb) {
3353 ret = hns3_alloc_desc(ring);
3355 goto out_with_desc_cb;
3357 if (!HNAE3_IS_TX_RING(ring)) {
3358 ret = hns3_alloc_ring_buffers(ring);
3366 hns3_free_desc(ring);
3368 kfree(ring->desc_cb);
3369 ring->desc_cb = NULL;
3374 static void hns3_fini_ring(struct hns3_enet_ring *ring)
3376 hns3_free_desc(ring);
3377 kfree(ring->desc_cb);
3378 ring->desc_cb = NULL;
3379 ring->next_to_clean = 0;
3380 ring->next_to_use = 0;
3383 static int hns3_buf_size2type(u32 buf_size)
3389 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3392 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3395 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3398 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3401 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3404 return bd_size_type;
3407 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3409 dma_addr_t dma = ring->desc_dma_addr;
3410 struct hnae3_queue *q = ring->tqp;
3412 if (!HNAE3_IS_TX_RING(ring)) {
3413 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3415 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3416 (u32)((dma >> 31) >> 1));
3418 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3419 hns3_buf_size2type(ring->buf_size));
3420 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3421 ring->desc_num / 8 - 1);
3424 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3426 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3427 (u32)((dma >> 31) >> 1));
3429 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3430 ring->desc_num / 8 - 1);
3434 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3436 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3439 for (i = 0; i < HNAE3_MAX_TC; i++) {
3440 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3443 if (!tc_info->enable)
3446 for (j = 0; j < tc_info->tqp_count; j++) {
3447 struct hnae3_queue *q;
3449 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3450 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3456 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3458 struct hnae3_handle *h = priv->ae_handle;
3459 int ring_num = h->kinfo.num_tqps * 2;
3463 for (i = 0; i < ring_num; i++) {
3464 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3467 "Alloc ring memory fail! ret=%d\n", ret);
3468 goto out_when_alloc_ring_memory;
3471 u64_stats_init(&priv->ring_data[i].ring->syncp);
3476 out_when_alloc_ring_memory:
3477 for (j = i - 1; j >= 0; j--)
3478 hns3_fini_ring(priv->ring_data[j].ring);
3483 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3485 struct hnae3_handle *h = priv->ae_handle;
3488 for (i = 0; i < h->kinfo.num_tqps; i++) {
3489 hns3_fini_ring(priv->ring_data[i].ring);
3490 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3495 /* Set mac addr if it is configured. or leave it to the AE driver */
3496 static int hns3_init_mac_addr(struct net_device *netdev, bool init)
3498 struct hns3_nic_priv *priv = netdev_priv(netdev);
3499 struct hnae3_handle *h = priv->ae_handle;
3500 u8 mac_addr_temp[ETH_ALEN];
3503 if (h->ae_algo->ops->get_mac_addr && init) {
3504 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3505 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3508 /* Check if the MAC address is valid, if not get a random one */
3509 if (!is_valid_ether_addr(netdev->dev_addr)) {
3510 eth_hw_addr_random(netdev);
3511 dev_warn(priv->dev, "using random MAC address %pM\n",
3515 if (h->ae_algo->ops->set_mac_addr)
3516 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3521 static int hns3_restore_fd_rules(struct net_device *netdev)
3523 struct hnae3_handle *h = hns3_get_handle(netdev);
3526 if (h->ae_algo->ops->restore_fd_rules)
3527 ret = h->ae_algo->ops->restore_fd_rules(h);
3532 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3534 struct hnae3_handle *h = hns3_get_handle(netdev);
3536 if (h->ae_algo->ops->del_all_fd_entries)
3537 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3540 static void hns3_nic_set_priv_ops(struct net_device *netdev)
3542 struct hns3_nic_priv *priv = netdev_priv(netdev);
3544 priv->ops.fill_desc = hns3_fill_desc;
3545 if ((netdev->features & NETIF_F_TSO) ||
3546 (netdev->features & NETIF_F_TSO6))
3547 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
3549 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
3552 static int hns3_client_start(struct hnae3_handle *handle)
3554 if (!handle->ae_algo->ops->client_start)
3557 return handle->ae_algo->ops->client_start(handle);
3560 static void hns3_client_stop(struct hnae3_handle *handle)
3562 if (!handle->ae_algo->ops->client_stop)
3565 handle->ae_algo->ops->client_stop(handle);
3568 static int hns3_client_init(struct hnae3_handle *handle)
3570 struct pci_dev *pdev = handle->pdev;
3571 u16 alloc_tqps, max_rss_size;
3572 struct hns3_nic_priv *priv;
3573 struct net_device *netdev;
3576 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3578 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3582 priv = netdev_priv(netdev);
3583 priv->dev = &pdev->dev;
3584 priv->netdev = netdev;
3585 priv->ae_handle = handle;
3586 priv->tx_timeout_count = 0;
3588 handle->kinfo.netdev = netdev;
3589 handle->priv = (void *)priv;
3591 hns3_init_mac_addr(netdev, true);
3593 hns3_set_default_feature(netdev);
3595 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3596 netdev->priv_flags |= IFF_UNICAST_FLT;
3597 netdev->netdev_ops = &hns3_nic_netdev_ops;
3598 SET_NETDEV_DEV(netdev, &pdev->dev);
3599 hns3_ethtool_set_ops(netdev);
3600 hns3_nic_set_priv_ops(netdev);
3602 /* Carrier off reporting is important to ethtool even BEFORE open */
3603 netif_carrier_off(netdev);
3605 ret = hns3_get_ring_config(priv);
3608 goto out_get_ring_cfg;
3611 ret = hns3_nic_alloc_vector_data(priv);
3614 goto out_alloc_vector_data;
3617 ret = hns3_nic_init_vector_data(priv);
3620 goto out_init_vector_data;
3623 ret = hns3_init_all_ring(priv);
3626 goto out_init_ring_data;
3629 ret = register_netdev(netdev);
3631 dev_err(priv->dev, "probe register netdev fail!\n");
3632 goto out_reg_netdev_fail;
3635 ret = hns3_client_start(handle);
3637 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
3638 goto out_reg_netdev_fail;
3641 hns3_dcbnl_setup(handle);
3643 hns3_dbg_init(handle);
3645 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
3646 netdev->max_mtu = HNS3_MAX_MTU;
3648 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3652 out_reg_netdev_fail:
3654 (void)hns3_nic_uninit_vector_data(priv);
3655 out_init_vector_data:
3656 hns3_nic_dealloc_vector_data(priv);
3657 out_alloc_vector_data:
3658 priv->ring_data = NULL;
3660 priv->ae_handle = NULL;
3661 free_netdev(netdev);
3665 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3667 struct net_device *netdev = handle->kinfo.netdev;
3668 struct hns3_nic_priv *priv = netdev_priv(netdev);
3671 hns3_client_stop(handle);
3673 hns3_remove_hw_addr(netdev);
3675 if (netdev->reg_state != NETREG_UNINITIALIZED)
3676 unregister_netdev(netdev);
3678 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3679 netdev_warn(netdev, "already uninitialized\n");
3680 goto out_netdev_free;
3683 hns3_del_all_fd_rules(netdev, true);
3685 hns3_force_clear_all_rx_ring(handle);
3687 ret = hns3_nic_uninit_vector_data(priv);
3689 netdev_err(netdev, "uninit vector error\n");
3691 ret = hns3_nic_dealloc_vector_data(priv);
3693 netdev_err(netdev, "dealloc vector error\n");
3695 ret = hns3_uninit_all_ring(priv);
3697 netdev_err(netdev, "uninit ring error\n");
3699 hns3_put_ring_config(priv);
3701 hns3_dbg_uninit(handle);
3703 priv->ring_data = NULL;
3706 free_netdev(netdev);
3709 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3711 struct net_device *netdev = handle->kinfo.netdev;
3717 netif_carrier_on(netdev);
3718 netif_tx_wake_all_queues(netdev);
3719 netdev_info(netdev, "link up\n");
3721 netif_carrier_off(netdev);
3722 netif_tx_stop_all_queues(netdev);
3723 netdev_info(netdev, "link down\n");
3727 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3729 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3730 struct net_device *ndev = kinfo->netdev;
3733 if (tc > HNAE3_MAX_TC)
3739 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3740 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3744 ret = hns3_nic_set_real_num_queue(ndev);
3749 static int hns3_recover_hw_addr(struct net_device *ndev)
3751 struct netdev_hw_addr_list *list;
3752 struct netdev_hw_addr *ha, *tmp;
3755 /* go through and sync uc_addr entries to the device */
3757 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3758 ret = hns3_nic_uc_sync(ndev, ha->addr);
3763 /* go through and sync mc_addr entries to the device */
3765 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3766 ret = hns3_nic_mc_sync(ndev, ha->addr);
3774 static void hns3_remove_hw_addr(struct net_device *netdev)
3776 struct netdev_hw_addr_list *list;
3777 struct netdev_hw_addr *ha, *tmp;
3779 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3781 /* go through and unsync uc_addr entries to the device */
3783 list_for_each_entry_safe(ha, tmp, &list->list, list)
3784 hns3_nic_uc_unsync(netdev, ha->addr);
3786 /* go through and unsync mc_addr entries to the device */
3788 list_for_each_entry_safe(ha, tmp, &list->list, list)
3789 if (ha->refcount > 1)
3790 hns3_nic_mc_unsync(netdev, ha->addr);
3793 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
3795 while (ring->next_to_clean != ring->next_to_use) {
3796 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
3797 hns3_free_buffer_detach(ring, ring->next_to_clean);
3798 ring_ptr_move_fw(ring, next_to_clean);
3802 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3804 struct hns3_desc_cb res_cbs;
3807 while (ring->next_to_use != ring->next_to_clean) {
3808 /* When a buffer is not reused, it's memory has been
3809 * freed in hns3_handle_rx_bd or will be freed by
3810 * stack, so we need to replace the buffer here.
3812 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3813 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3815 u64_stats_update_begin(&ring->syncp);
3816 ring->stats.sw_err_cnt++;
3817 u64_stats_update_end(&ring->syncp);
3818 /* if alloc new buffer fail, exit directly
3819 * and reclear in up flow.
3821 netdev_warn(ring->tqp->handle->kinfo.netdev,
3822 "reserve buffer map failed, ret = %d\n",
3826 hns3_replace_buffer(ring, ring->next_to_use,
3829 ring_ptr_move_fw(ring, next_to_use);
3835 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
3837 while (ring->next_to_use != ring->next_to_clean) {
3838 /* When a buffer is not reused, it's memory has been
3839 * freed in hns3_handle_rx_bd or will be freed by
3840 * stack, so only need to unmap the buffer here.
3842 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3843 hns3_unmap_buffer(ring,
3844 &ring->desc_cb[ring->next_to_use]);
3845 ring->desc_cb[ring->next_to_use].dma = 0;
3848 ring_ptr_move_fw(ring, next_to_use);
3852 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3854 struct net_device *ndev = h->kinfo.netdev;
3855 struct hns3_nic_priv *priv = netdev_priv(ndev);
3856 struct hns3_enet_ring *ring;
3859 for (i = 0; i < h->kinfo.num_tqps; i++) {
3860 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3861 hns3_force_clear_rx_ring(ring);
3865 static void hns3_clear_all_ring(struct hnae3_handle *h)
3867 struct net_device *ndev = h->kinfo.netdev;
3868 struct hns3_nic_priv *priv = netdev_priv(ndev);
3871 for (i = 0; i < h->kinfo.num_tqps; i++) {
3872 struct netdev_queue *dev_queue;
3873 struct hns3_enet_ring *ring;
3875 ring = priv->ring_data[i].ring;
3876 hns3_clear_tx_ring(ring);
3877 dev_queue = netdev_get_tx_queue(ndev,
3878 priv->ring_data[i].queue_index);
3879 netdev_tx_reset_queue(dev_queue);
3881 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3882 /* Continue to clear other rings even if clearing some
3885 hns3_clear_rx_ring(ring);
3889 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3891 struct net_device *ndev = h->kinfo.netdev;
3892 struct hns3_nic_priv *priv = netdev_priv(ndev);
3893 struct hns3_enet_ring *rx_ring;
3897 for (i = 0; i < h->kinfo.num_tqps; i++) {
3898 ret = h->ae_algo->ops->reset_queue(h, i);
3902 hns3_init_ring_hw(priv->ring_data[i].ring);
3904 /* We need to clear tx ring here because self test will
3905 * use the ring and will not run down before up
3907 hns3_clear_tx_ring(priv->ring_data[i].ring);
3908 priv->ring_data[i].ring->next_to_clean = 0;
3909 priv->ring_data[i].ring->next_to_use = 0;
3911 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3912 hns3_init_ring_hw(rx_ring);
3913 ret = hns3_clear_rx_ring(rx_ring);
3917 /* We can not know the hardware head and tail when this
3918 * function is called in reset flow, so we reuse all desc.
3920 for (j = 0; j < rx_ring->desc_num; j++)
3921 hns3_reuse_buffer(rx_ring, j);
3923 rx_ring->next_to_clean = 0;
3924 rx_ring->next_to_use = 0;
3927 hns3_init_tx_ring_tc(priv);
3932 static void hns3_store_coal(struct hns3_nic_priv *priv)
3934 /* ethtool only support setting and querying one coal
3935 * configuation for now, so save the vector 0' coal
3936 * configuation here in order to restore it.
3938 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
3939 sizeof(struct hns3_enet_coalesce));
3940 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
3941 sizeof(struct hns3_enet_coalesce));
3944 static void hns3_restore_coal(struct hns3_nic_priv *priv)
3946 u16 vector_num = priv->vector_num;
3949 for (i = 0; i < vector_num; i++) {
3950 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
3951 sizeof(struct hns3_enet_coalesce));
3952 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
3953 sizeof(struct hns3_enet_coalesce));
3957 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3959 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
3960 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3961 struct net_device *ndev = kinfo->netdev;
3962 struct hns3_nic_priv *priv = netdev_priv(ndev);
3964 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
3967 /* it is cumbersome for hardware to pick-and-choose entries for deletion
3968 * from table space. Hence, for function reset software intervention is
3969 * required to delete the entries
3971 if (hns3_dev_ongoing_func_reset(ae_dev)) {
3972 hns3_remove_hw_addr(ndev);
3973 hns3_del_all_fd_rules(ndev, false);
3976 if (!netif_running(ndev))
3979 return hns3_nic_net_stop(ndev);
3982 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3984 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3985 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
3988 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
3990 if (netif_running(kinfo->netdev)) {
3991 ret = hns3_nic_net_open(kinfo->netdev);
3993 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
3994 netdev_err(kinfo->netdev,
3995 "hns net up fail, ret=%d!\n", ret);
4003 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4005 struct net_device *netdev = handle->kinfo.netdev;
4006 struct hns3_nic_priv *priv = netdev_priv(netdev);
4009 /* Carrier off reporting is important to ethtool even BEFORE open */
4010 netif_carrier_off(netdev);
4012 ret = hns3_get_ring_config(priv);
4016 ret = hns3_nic_alloc_vector_data(priv);
4020 hns3_restore_coal(priv);
4022 ret = hns3_nic_init_vector_data(priv);
4024 goto err_dealloc_vector;
4026 ret = hns3_init_all_ring(priv);
4028 goto err_uninit_vector;
4030 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4035 hns3_nic_uninit_vector_data(priv);
4036 priv->ring_data = NULL;
4038 hns3_nic_dealloc_vector_data(priv);
4040 hns3_put_ring_config(priv);
4041 priv->ring_data = NULL;
4046 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4048 struct net_device *netdev = handle->kinfo.netdev;
4049 bool vlan_filter_enable;
4052 ret = hns3_init_mac_addr(netdev, false);
4056 ret = hns3_recover_hw_addr(netdev);
4060 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4064 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4065 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4067 /* Hardware table is only clear when pf resets */
4068 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4069 ret = hns3_restore_vlan(netdev);
4074 return hns3_restore_fd_rules(netdev);
4077 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4079 struct net_device *netdev = handle->kinfo.netdev;
4080 struct hns3_nic_priv *priv = netdev_priv(netdev);
4083 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4084 netdev_warn(netdev, "already uninitialized\n");
4088 hns3_force_clear_all_rx_ring(handle);
4090 ret = hns3_nic_uninit_vector_data(priv);
4092 netdev_err(netdev, "uninit vector error\n");
4096 hns3_store_coal(priv);
4098 ret = hns3_nic_dealloc_vector_data(priv);
4100 netdev_err(netdev, "dealloc vector error\n");
4102 ret = hns3_uninit_all_ring(priv);
4104 netdev_err(netdev, "uninit ring error\n");
4106 hns3_put_ring_config(priv);
4107 priv->ring_data = NULL;
4109 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
4114 static int hns3_reset_notify(struct hnae3_handle *handle,
4115 enum hnae3_reset_notify_type type)
4120 case HNAE3_UP_CLIENT:
4121 ret = hns3_reset_notify_up_enet(handle);
4123 case HNAE3_DOWN_CLIENT:
4124 ret = hns3_reset_notify_down_enet(handle);
4126 case HNAE3_INIT_CLIENT:
4127 ret = hns3_reset_notify_init_enet(handle);
4129 case HNAE3_UNINIT_CLIENT:
4130 ret = hns3_reset_notify_uninit_enet(handle);
4132 case HNAE3_RESTORE_CLIENT:
4133 ret = hns3_reset_notify_restore_enet(handle);
4142 int hns3_set_channels(struct net_device *netdev,
4143 struct ethtool_channels *ch)
4145 struct hnae3_handle *h = hns3_get_handle(netdev);
4146 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4147 u32 new_tqp_num = ch->combined_count;
4151 if (ch->rx_count || ch->tx_count)
4154 if (new_tqp_num > hns3_get_max_available_channels(h) ||
4156 dev_err(&netdev->dev,
4157 "Change tqps fail, the tqp range is from 1 to %d",
4158 hns3_get_max_available_channels(h));
4162 if (kinfo->rss_size == new_tqp_num)
4165 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4169 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4173 org_tqp_num = h->kinfo.num_tqps;
4174 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
4176 ret = h->ae_algo->ops->set_channels(h, org_tqp_num);
4178 /* If revert to old tqp failed, fatal error occurred */
4179 dev_err(&netdev->dev,
4180 "Revert to old tqp num fail, ret=%d", ret);
4183 dev_info(&netdev->dev,
4184 "Change tqp num fail, Revert to old tqp num");
4186 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT);
4190 return hns3_reset_notify(h, HNAE3_UP_CLIENT);
4193 static const struct hnae3_client_ops client_ops = {
4194 .init_instance = hns3_client_init,
4195 .uninit_instance = hns3_client_uninit,
4196 .link_status_change = hns3_link_status_change,
4197 .setup_tc = hns3_client_setup_tc,
4198 .reset_notify = hns3_reset_notify,
4201 /* hns3_init_module - Driver registration routine
4202 * hns3_init_module is the first routine called when the driver is
4203 * loaded. All it does is register with the PCI subsystem.
4205 static int __init hns3_init_module(void)
4209 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4210 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4212 client.type = HNAE3_CLIENT_KNIC;
4213 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4216 client.ops = &client_ops;
4218 INIT_LIST_HEAD(&client.node);
4220 hns3_dbg_register_debugfs(hns3_driver_name);
4222 ret = hnae3_register_client(&client);
4224 goto err_reg_client;
4226 ret = pci_register_driver(&hns3_driver);
4228 goto err_reg_driver;
4233 hnae3_unregister_client(&client);
4235 hns3_dbg_unregister_debugfs();
4238 module_init(hns3_init_module);
4240 /* hns3_exit_module - Driver exit cleanup routine
4241 * hns3_exit_module is called just before the driver is removed
4244 static void __exit hns3_exit_module(void)
4246 pci_unregister_driver(&hns3_driver);
4247 hnae3_unregister_client(&client);
4248 hns3_dbg_unregister_debugfs();
4250 module_exit(hns3_exit_module);
4252 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4253 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4254 MODULE_LICENSE("GPL");
4255 MODULE_ALIAS("pci:hns-nic");
4256 MODULE_VERSION(HNS3_MOD_VERSION);