1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
10 #include <linux/if_vlan.h>
12 #include <linux/ipv6.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/aer.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
19 #include <net/ip6_checksum.h>
20 #include <net/pkt_cls.h>
22 #include <net/vxlan.h>
25 #include "hns3_enet.h"
26 /* All hns3 tracepoints are defined by the include below, which
27 * must be included exactly once across the whole kernel with
28 * CREATE_TRACE_POINTS defined
30 #define CREATE_TRACE_POINTS
31 #include "hns3_trace.h"
33 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
34 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
36 #define hns3_rl_err(fmt, ...) \
38 if (net_ratelimit()) \
39 netdev_err(fmt, ##__VA_ARGS__); \
42 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
44 static const char hns3_driver_name[] = "hns3";
45 static const char hns3_driver_string[] =
46 "Hisilicon Ethernet Network Driver for Hip08 Family";
47 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
48 static struct hnae3_client client;
50 static int debug = -1;
51 module_param(debug, int, 0);
52 MODULE_PARM_DESC(debug, " Network interface message level setting");
54 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
55 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
57 #define HNS3_INNER_VLAN_TAG 1
58 #define HNS3_OUTER_VLAN_TAG 2
60 #define HNS3_MIN_TX_LEN 33U
62 /* hns3_pci_tbl - PCI Device ID Table
64 * Last entry must be all 0s
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
69 static const struct pci_device_id hns3_pci_tbl[] = {
70 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
73 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
84 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
85 /* required last entry */
88 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
90 static irqreturn_t hns3_irq_handle(int irq, void *vector)
92 struct hns3_enet_tqp_vector *tqp_vector = vector;
94 napi_schedule_irqoff(&tqp_vector->napi);
99 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
101 struct hns3_enet_tqp_vector *tqp_vectors;
104 for (i = 0; i < priv->vector_num; i++) {
105 tqp_vectors = &priv->tqp_vector[i];
107 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
110 /* clear the affinity mask */
111 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
113 /* release the irq resource */
114 free_irq(tqp_vectors->vector_irq, tqp_vectors);
115 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
119 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
121 struct hns3_enet_tqp_vector *tqp_vectors;
122 int txrx_int_idx = 0;
128 for (i = 0; i < priv->vector_num; i++) {
129 tqp_vectors = &priv->tqp_vector[i];
131 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
134 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
136 "%s-%s-%s-%d", hns3_driver_name,
137 pci_name(priv->ae_handle->pdev),
138 "TxRx", txrx_int_idx++);
140 } else if (tqp_vectors->rx_group.ring) {
141 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
142 "%s-%s-%s-%d", hns3_driver_name,
143 pci_name(priv->ae_handle->pdev),
145 } else if (tqp_vectors->tx_group.ring) {
146 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
147 "%s-%s-%s-%d", hns3_driver_name,
148 pci_name(priv->ae_handle->pdev),
151 /* Skip this unused q_vector */
155 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
157 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
158 tqp_vectors->name, tqp_vectors);
160 netdev_err(priv->netdev, "request irq(%d) fail\n",
161 tqp_vectors->vector_irq);
162 hns3_nic_uninit_irq(priv);
166 disable_irq(tqp_vectors->vector_irq);
168 irq_set_affinity_hint(tqp_vectors->vector_irq,
169 &tqp_vectors->affinity_mask);
171 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
177 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
180 writel(mask_en, tqp_vector->mask_addr);
183 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
185 napi_enable(&tqp_vector->napi);
186 enable_irq(tqp_vector->vector_irq);
189 hns3_mask_vector_irq(tqp_vector, 1);
192 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
195 hns3_mask_vector_irq(tqp_vector, 0);
197 disable_irq(tqp_vector->vector_irq);
198 napi_disable(&tqp_vector->napi);
201 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
204 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
206 /* this defines the configuration for RL (Interrupt Rate Limiter).
207 * Rl defines rate of interrupts i.e. number of interrupts-per-second
208 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
211 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
212 !tqp_vector->rx_group.coal.gl_adapt_enable)
213 /* According to the hardware, the range of rl_reg is
214 * 0-59 and the unit is 4.
216 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
218 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
221 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
224 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
226 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
229 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
232 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
234 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
237 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
238 struct hns3_nic_priv *priv)
240 /* initialize the configuration for interrupt coalescing.
241 * 1. GL (Interrupt Gap Limiter)
242 * 2. RL (Interrupt Rate Limiter)
244 * Default: enable interrupt coalescing self-adaptive and GL
246 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
247 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
249 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
250 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
252 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
253 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
256 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
257 struct hns3_nic_priv *priv)
259 struct hnae3_handle *h = priv->ae_handle;
261 hns3_set_vector_coalesce_tx_gl(tqp_vector,
262 tqp_vector->tx_group.coal.int_gl);
263 hns3_set_vector_coalesce_rx_gl(tqp_vector,
264 tqp_vector->rx_group.coal.int_gl);
265 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
268 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
270 struct hnae3_handle *h = hns3_get_handle(netdev);
271 struct hnae3_knic_private_info *kinfo = &h->kinfo;
272 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
275 if (kinfo->num_tc <= 1) {
276 netdev_reset_tc(netdev);
278 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
281 "netdev_set_num_tc fail, ret=%d!\n", ret);
285 for (i = 0; i < HNAE3_MAX_TC; i++) {
286 if (!kinfo->tc_info[i].enable)
289 netdev_set_tc_queue(netdev,
290 kinfo->tc_info[i].tc,
291 kinfo->tc_info[i].tqp_count,
292 kinfo->tc_info[i].tqp_offset);
296 ret = netif_set_real_num_tx_queues(netdev, queue_size);
299 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
303 ret = netif_set_real_num_rx_queues(netdev, queue_size);
306 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
313 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
315 u16 alloc_tqps, max_rss_size, rss_size;
317 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
318 rss_size = alloc_tqps / h->kinfo.num_tc;
320 return min_t(u16, rss_size, max_rss_size);
323 static void hns3_tqp_enable(struct hnae3_queue *tqp)
327 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
328 rcb_reg |= BIT(HNS3_RING_EN_B);
329 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
332 static void hns3_tqp_disable(struct hnae3_queue *tqp)
336 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
337 rcb_reg &= ~BIT(HNS3_RING_EN_B);
338 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
341 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
343 #ifdef CONFIG_RFS_ACCEL
344 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
345 netdev->rx_cpu_rmap = NULL;
349 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
351 #ifdef CONFIG_RFS_ACCEL
352 struct hns3_nic_priv *priv = netdev_priv(netdev);
353 struct hns3_enet_tqp_vector *tqp_vector;
356 if (!netdev->rx_cpu_rmap) {
357 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
358 if (!netdev->rx_cpu_rmap)
362 for (i = 0; i < priv->vector_num; i++) {
363 tqp_vector = &priv->tqp_vector[i];
364 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
365 tqp_vector->vector_irq);
367 hns3_free_rx_cpu_rmap(netdev);
375 static int hns3_nic_net_up(struct net_device *netdev)
377 struct hns3_nic_priv *priv = netdev_priv(netdev);
378 struct hnae3_handle *h = priv->ae_handle;
382 ret = hns3_nic_reset_all_ring(h);
386 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
388 /* enable the vectors */
389 for (i = 0; i < priv->vector_num; i++)
390 hns3_vector_enable(&priv->tqp_vector[i]);
393 for (j = 0; j < h->kinfo.num_tqps; j++)
394 hns3_tqp_enable(h->kinfo.tqp[j]);
396 /* start the ae_dev */
397 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
399 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
401 hns3_tqp_disable(h->kinfo.tqp[j]);
403 for (j = i - 1; j >= 0; j--)
404 hns3_vector_disable(&priv->tqp_vector[j]);
410 static void hns3_config_xps(struct hns3_nic_priv *priv)
414 for (i = 0; i < priv->vector_num; i++) {
415 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
416 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
421 ret = netif_set_xps_queue(priv->netdev,
422 &tqp_vector->affinity_mask,
423 ring->tqp->tqp_index);
425 netdev_warn(priv->netdev,
426 "set xps queue failed: %d", ret);
433 static int hns3_nic_net_open(struct net_device *netdev)
435 struct hns3_nic_priv *priv = netdev_priv(netdev);
436 struct hnae3_handle *h = hns3_get_handle(netdev);
437 struct hnae3_knic_private_info *kinfo;
440 if (hns3_nic_resetting(netdev))
443 netif_carrier_off(netdev);
445 ret = hns3_nic_set_real_num_queue(netdev);
449 ret = hns3_nic_net_up(netdev);
451 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
456 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
457 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
459 if (h->ae_algo->ops->set_timer_task)
460 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
462 hns3_config_xps(priv);
464 netif_dbg(h, drv, netdev, "net open\n");
469 static void hns3_reset_tx_queue(struct hnae3_handle *h)
471 struct net_device *ndev = h->kinfo.netdev;
472 struct hns3_nic_priv *priv = netdev_priv(ndev);
473 struct netdev_queue *dev_queue;
476 for (i = 0; i < h->kinfo.num_tqps; i++) {
477 dev_queue = netdev_get_tx_queue(ndev,
478 priv->ring[i].queue_index);
479 netdev_tx_reset_queue(dev_queue);
483 static void hns3_nic_net_down(struct net_device *netdev)
485 struct hns3_nic_priv *priv = netdev_priv(netdev);
486 struct hnae3_handle *h = hns3_get_handle(netdev);
487 const struct hnae3_ae_ops *ops;
490 /* disable vectors */
491 for (i = 0; i < priv->vector_num; i++)
492 hns3_vector_disable(&priv->tqp_vector[i]);
495 for (i = 0; i < h->kinfo.num_tqps; i++)
496 hns3_tqp_disable(h->kinfo.tqp[i]);
499 ops = priv->ae_handle->ae_algo->ops;
501 ops->stop(priv->ae_handle);
503 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
504 * during reset process, because driver may not be able
505 * to disable the ring through firmware when downing the netdev.
507 if (!hns3_nic_resetting(netdev))
508 hns3_clear_all_ring(priv->ae_handle, false);
510 hns3_reset_tx_queue(priv->ae_handle);
513 static int hns3_nic_net_stop(struct net_device *netdev)
515 struct hns3_nic_priv *priv = netdev_priv(netdev);
516 struct hnae3_handle *h = hns3_get_handle(netdev);
518 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
521 netif_dbg(h, drv, netdev, "net stop\n");
523 if (h->ae_algo->ops->set_timer_task)
524 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
526 netif_tx_stop_all_queues(netdev);
527 netif_carrier_off(netdev);
529 hns3_nic_net_down(netdev);
534 static int hns3_nic_uc_sync(struct net_device *netdev,
535 const unsigned char *addr)
537 struct hnae3_handle *h = hns3_get_handle(netdev);
539 if (h->ae_algo->ops->add_uc_addr)
540 return h->ae_algo->ops->add_uc_addr(h, addr);
545 static int hns3_nic_uc_unsync(struct net_device *netdev,
546 const unsigned char *addr)
548 struct hnae3_handle *h = hns3_get_handle(netdev);
550 /* need ignore the request of removing device address, because
551 * we store the device address and other addresses of uc list
552 * in the function's mac filter list.
554 if (ether_addr_equal(addr, netdev->dev_addr))
557 if (h->ae_algo->ops->rm_uc_addr)
558 return h->ae_algo->ops->rm_uc_addr(h, addr);
563 static int hns3_nic_mc_sync(struct net_device *netdev,
564 const unsigned char *addr)
566 struct hnae3_handle *h = hns3_get_handle(netdev);
568 if (h->ae_algo->ops->add_mc_addr)
569 return h->ae_algo->ops->add_mc_addr(h, addr);
574 static int hns3_nic_mc_unsync(struct net_device *netdev,
575 const unsigned char *addr)
577 struct hnae3_handle *h = hns3_get_handle(netdev);
579 if (h->ae_algo->ops->rm_mc_addr)
580 return h->ae_algo->ops->rm_mc_addr(h, addr);
585 static u8 hns3_get_netdev_flags(struct net_device *netdev)
589 if (netdev->flags & IFF_PROMISC) {
590 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
592 flags |= HNAE3_VLAN_FLTR;
593 if (netdev->flags & IFF_ALLMULTI)
594 flags |= HNAE3_USER_MPE;
600 static void hns3_nic_set_rx_mode(struct net_device *netdev)
602 struct hnae3_handle *h = hns3_get_handle(netdev);
605 new_flags = hns3_get_netdev_flags(netdev);
607 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
608 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
610 /* User mode Promisc mode enable and vlan filtering is disabled to
611 * let all packets in.
613 h->netdev_flags = new_flags;
614 hns3_request_update_promisc_mode(h);
617 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
619 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
621 if (ops->request_update_promisc_mode)
622 ops->request_update_promisc_mode(handle);
625 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
627 struct hns3_nic_priv *priv = netdev_priv(netdev);
628 struct hnae3_handle *h = priv->ae_handle;
630 if (h->ae_algo->ops->set_promisc_mode) {
631 return h->ae_algo->ops->set_promisc_mode(h,
632 promisc_flags & HNAE3_UPE,
633 promisc_flags & HNAE3_MPE);
639 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
641 struct hns3_nic_priv *priv = netdev_priv(netdev);
642 struct hnae3_handle *h = priv->ae_handle;
645 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
646 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
647 if (enable != last_state) {
650 enable ? "enable" : "disable");
651 h->ae_algo->ops->enable_vlan_filter(h, enable);
656 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
657 u16 *mss, u32 *type_cs_vlan_tso)
659 u32 l4_offset, hdr_len;
660 union l3_hdr_info l3;
661 union l4_hdr_info l4;
665 if (!skb_is_gso(skb))
668 ret = skb_cow_head(skb, 0);
669 if (unlikely(ret < 0))
672 l3.hdr = skb_network_header(skb);
673 l4.hdr = skb_transport_header(skb);
675 /* Software should clear the IPv4's checksum field when tso is
678 if (l3.v4->version == 4)
682 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
685 SKB_GSO_UDP_TUNNEL_CSUM)) {
686 if ((!(skb_shinfo(skb)->gso_type &
688 (skb_shinfo(skb)->gso_type &
689 SKB_GSO_UDP_TUNNEL_CSUM)) {
690 /* Software should clear the udp's checksum
691 * field when tso is needed.
695 /* reset l3&l4 pointers from outer to inner headers */
696 l3.hdr = skb_inner_network_header(skb);
697 l4.hdr = skb_inner_transport_header(skb);
699 /* Software should clear the IPv4's checksum field when
702 if (l3.v4->version == 4)
706 /* normal or tunnel packet */
707 l4_offset = l4.hdr - skb->data;
708 hdr_len = (l4.tcp->doff << 2) + l4_offset;
710 /* remove payload length from inner pseudo checksum when tso */
711 l4_paylen = skb->len - l4_offset;
712 csum_replace_by_diff(&l4.tcp->check,
713 (__force __wsum)htonl(l4_paylen));
715 /* find the txbd field values */
716 *paylen = skb->len - hdr_len;
717 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
719 /* get MSS for TSO */
720 *mss = skb_shinfo(skb)->gso_size;
727 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
730 union l3_hdr_info l3;
731 unsigned char *l4_hdr;
732 unsigned char *exthdr;
736 /* find outer header point */
737 l3.hdr = skb_network_header(skb);
738 l4_hdr = skb_transport_header(skb);
740 if (skb->protocol == htons(ETH_P_IPV6)) {
741 exthdr = l3.hdr + sizeof(*l3.v6);
742 l4_proto_tmp = l3.v6->nexthdr;
743 if (l4_hdr != exthdr)
744 ipv6_skip_exthdr(skb, exthdr - skb->data,
745 &l4_proto_tmp, &frag_off);
746 } else if (skb->protocol == htons(ETH_P_IP)) {
747 l4_proto_tmp = l3.v4->protocol;
752 *ol4_proto = l4_proto_tmp;
755 if (!skb->encapsulation) {
760 /* find inner header point */
761 l3.hdr = skb_inner_network_header(skb);
762 l4_hdr = skb_inner_transport_header(skb);
764 if (l3.v6->version == 6) {
765 exthdr = l3.hdr + sizeof(*l3.v6);
766 l4_proto_tmp = l3.v6->nexthdr;
767 if (l4_hdr != exthdr)
768 ipv6_skip_exthdr(skb, exthdr - skb->data,
769 &l4_proto_tmp, &frag_off);
770 } else if (l3.v4->version == 4) {
771 l4_proto_tmp = l3.v4->protocol;
774 *il4_proto = l4_proto_tmp;
779 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
780 * and it is udp packet, which has a dest port as the IANA assigned.
781 * the hardware is expected to do the checksum offload, but the
782 * hardware will not do the checksum offload when udp dest port is
785 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
787 union l4_hdr_info l4;
789 l4.hdr = skb_transport_header(skb);
791 if (!(!skb->encapsulation &&
792 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
795 skb_checksum_help(skb);
800 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
801 u32 *ol_type_vlan_len_msec)
803 u32 l2_len, l3_len, l4_len;
804 unsigned char *il2_hdr;
805 union l3_hdr_info l3;
806 union l4_hdr_info l4;
808 l3.hdr = skb_network_header(skb);
809 l4.hdr = skb_transport_header(skb);
811 /* compute OL2 header size, defined in 2 Bytes */
812 l2_len = l3.hdr - skb->data;
813 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
815 /* compute OL3 header size, defined in 4 Bytes */
816 l3_len = l4.hdr - l3.hdr;
817 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
819 il2_hdr = skb_inner_mac_header(skb);
820 /* compute OL4 header size, defined in 4 Bytes */
821 l4_len = il2_hdr - l4.hdr;
822 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
824 /* define outer network header type */
825 if (skb->protocol == htons(ETH_P_IP)) {
827 hns3_set_field(*ol_type_vlan_len_msec,
829 HNS3_OL3T_IPV4_CSUM);
831 hns3_set_field(*ol_type_vlan_len_msec,
833 HNS3_OL3T_IPV4_NO_CSUM);
835 } else if (skb->protocol == htons(ETH_P_IPV6)) {
836 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
840 if (ol4_proto == IPPROTO_UDP)
841 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
842 HNS3_TUN_MAC_IN_UDP);
843 else if (ol4_proto == IPPROTO_GRE)
844 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
848 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
849 u8 il4_proto, u32 *type_cs_vlan_tso,
850 u32 *ol_type_vlan_len_msec)
852 unsigned char *l2_hdr = skb->data;
853 u32 l4_proto = ol4_proto;
854 union l4_hdr_info l4;
855 union l3_hdr_info l3;
858 l4.hdr = skb_transport_header(skb);
859 l3.hdr = skb_network_header(skb);
861 /* handle encapsulation skb */
862 if (skb->encapsulation) {
863 /* If this is a not UDP/GRE encapsulation skb */
864 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
865 /* drop the skb tunnel packet if hardware don't support,
866 * because hardware can't calculate csum when TSO.
871 /* the stack computes the IP header already,
872 * driver calculate l4 checksum when not TSO.
874 skb_checksum_help(skb);
878 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
880 /* switch to inner header */
881 l2_hdr = skb_inner_mac_header(skb);
882 l3.hdr = skb_inner_network_header(skb);
883 l4.hdr = skb_inner_transport_header(skb);
884 l4_proto = il4_proto;
887 if (l3.v4->version == 4) {
888 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
891 /* the stack computes the IP header already, the only time we
892 * need the hardware to recompute it is in the case of TSO.
895 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
896 } else if (l3.v6->version == 6) {
897 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
901 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
902 l2_len = l3.hdr - l2_hdr;
903 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
905 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
906 l3_len = l4.hdr - l3.hdr;
907 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
909 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
913 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
915 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
919 if (hns3_tunnel_csum_bug(skb))
922 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
923 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
926 (sizeof(struct udphdr) >> 2));
929 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
932 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
933 (sizeof(struct sctphdr) >> 2));
936 /* drop the skb tunnel packet if hardware don't support,
937 * because hardware can't calculate csum when TSO.
942 /* the stack computes the IP header already,
943 * driver calculate l4 checksum when not TSO.
945 skb_checksum_help(skb);
952 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
955 struct hnae3_handle *handle = tx_ring->tqp->handle;
956 struct vlan_ethhdr *vhdr;
959 if (!(skb->protocol == htons(ETH_P_8021Q) ||
960 skb_vlan_tag_present(skb)))
963 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
964 * header is allowed in skb, otherwise it will cause RAS error.
966 if (unlikely(skb_vlan_tagged_multi(skb) &&
967 handle->port_base_vlan_state ==
968 HNAE3_PORT_BASE_VLAN_ENABLE))
971 if (skb->protocol == htons(ETH_P_8021Q) &&
972 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
973 /* When HW VLAN acceleration is turned off, and the stack
974 * sets the protocol to 802.1q, the driver just need to
975 * set the protocol to the encapsulated ethertype.
977 skb->protocol = vlan_get_protocol(skb);
981 if (skb_vlan_tag_present(skb)) {
982 /* Based on hw strategy, use out_vtag in two layer tag case,
983 * and use inner_vtag in one tag case.
985 if (skb->protocol == htons(ETH_P_8021Q) &&
986 handle->port_base_vlan_state ==
987 HNAE3_PORT_BASE_VLAN_DISABLE)
988 rc = HNS3_OUTER_VLAN_TAG;
990 rc = HNS3_INNER_VLAN_TAG;
992 skb->protocol = vlan_get_protocol(skb);
996 rc = skb_cow_head(skb, 0);
997 if (unlikely(rc < 0))
1000 vhdr = (struct vlan_ethhdr *)skb->data;
1001 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1004 skb->protocol = vlan_get_protocol(skb);
1008 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1009 struct sk_buff *skb, struct hns3_desc *desc)
1011 u32 ol_type_vlan_len_msec = 0;
1012 u32 type_cs_vlan_tso = 0;
1013 u32 paylen = skb->len;
1019 ret = hns3_handle_vtags(ring, skb);
1020 if (unlikely(ret < 0)) {
1021 u64_stats_update_begin(&ring->syncp);
1022 ring->stats.tx_vlan_err++;
1023 u64_stats_update_end(&ring->syncp);
1025 } else if (ret == HNS3_INNER_VLAN_TAG) {
1026 inner_vtag = skb_vlan_tag_get(skb);
1027 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1029 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1030 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1031 out_vtag = skb_vlan_tag_get(skb);
1032 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1034 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1038 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1039 u8 ol4_proto, il4_proto;
1041 skb_reset_mac_len(skb);
1043 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1044 if (unlikely(ret < 0)) {
1045 u64_stats_update_begin(&ring->syncp);
1046 ring->stats.tx_l4_proto_err++;
1047 u64_stats_update_end(&ring->syncp);
1051 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1053 &ol_type_vlan_len_msec);
1054 if (unlikely(ret < 0)) {
1055 u64_stats_update_begin(&ring->syncp);
1056 ring->stats.tx_l2l3l4_err++;
1057 u64_stats_update_end(&ring->syncp);
1061 ret = hns3_set_tso(skb, &paylen, &mss,
1063 if (unlikely(ret < 0)) {
1064 u64_stats_update_begin(&ring->syncp);
1065 ring->stats.tx_tso_err++;
1066 u64_stats_update_end(&ring->syncp);
1072 desc->tx.ol_type_vlan_len_msec =
1073 cpu_to_le32(ol_type_vlan_len_msec);
1074 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1075 desc->tx.paylen = cpu_to_le32(paylen);
1076 desc->tx.mss = cpu_to_le16(mss);
1077 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1078 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1083 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1084 unsigned int size, enum hns_desc_type type)
1086 #define HNS3_LIKELY_BD_NUM 1
1088 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1089 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1090 struct device *dev = ring_to_dev(ring);
1092 unsigned int frag_buf_num;
1096 if (type == DESC_TYPE_SKB) {
1097 struct sk_buff *skb = (struct sk_buff *)priv;
1100 ret = hns3_fill_skb_desc(ring, skb, desc);
1101 if (unlikely(ret < 0))
1104 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1105 } else if (type == DESC_TYPE_FRAGLIST_SKB) {
1106 struct sk_buff *skb = (struct sk_buff *)priv;
1108 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1110 frag = (skb_frag_t *)priv;
1111 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1114 if (unlikely(dma_mapping_error(dev, dma))) {
1115 u64_stats_update_begin(&ring->syncp);
1116 ring->stats.sw_err_cnt++;
1117 u64_stats_update_end(&ring->syncp);
1121 desc_cb->length = size;
1123 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1124 desc_cb->priv = priv;
1126 desc_cb->type = type;
1127 desc->addr = cpu_to_le64(dma);
1128 desc->tx.send_size = cpu_to_le16(size);
1129 desc->tx.bdtp_fe_sc_vld_ra_ri =
1130 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1132 trace_hns3_tx_desc(ring, ring->next_to_use);
1133 ring_ptr_move_fw(ring, next_to_use);
1134 return HNS3_LIKELY_BD_NUM;
1137 frag_buf_num = hns3_tx_bd_count(size);
1138 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1139 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1141 /* When frag size is bigger than hardware limit, split this frag */
1142 for (k = 0; k < frag_buf_num; k++) {
1143 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1144 desc_cb->priv = priv;
1145 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1146 desc_cb->type = ((type == DESC_TYPE_FRAGLIST_SKB ||
1147 type == DESC_TYPE_SKB) && !k) ?
1148 type : DESC_TYPE_PAGE;
1150 /* now, fill the descriptor */
1151 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1152 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1153 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1154 desc->tx.bdtp_fe_sc_vld_ra_ri =
1155 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1157 trace_hns3_tx_desc(ring, ring->next_to_use);
1158 /* move ring pointer to next */
1159 ring_ptr_move_fw(ring, next_to_use);
1161 desc_cb = &ring->desc_cb[ring->next_to_use];
1162 desc = &ring->desc[ring->next_to_use];
1165 return frag_buf_num;
1168 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1169 unsigned int bd_num)
1174 size = skb_headlen(skb);
1175 while (size > HNS3_MAX_BD_SIZE) {
1176 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1177 size -= HNS3_MAX_BD_SIZE;
1179 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1184 bd_size[bd_num++] = size;
1185 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1189 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1190 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1191 size = skb_frag_size(frag);
1195 while (size > HNS3_MAX_BD_SIZE) {
1196 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1197 size -= HNS3_MAX_BD_SIZE;
1199 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1203 bd_size[bd_num++] = size;
1204 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1211 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1213 struct sk_buff *frag_skb;
1214 unsigned int bd_num = 0;
1216 /* If the total len is within the max bd limit */
1217 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1218 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1219 return skb_shinfo(skb)->nr_frags + 1U;
1221 /* The below case will always be linearized, return
1222 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1224 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1225 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1226 return HNS3_MAX_TSO_BD_NUM + 1U;
1228 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1230 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1233 skb_walk_frags(skb, frag_skb) {
1234 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1235 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1242 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1244 if (!skb->encapsulation)
1245 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1247 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1250 /* HW need every continuous 8 buffer data to be larger than MSS,
1251 * we simplify it by ensuring skb_headlen + the first continuous
1252 * 7 frags to to be larger than gso header len + mss, and the remaining
1253 * continuous 7 frags to be larger than MSS except the last 7 frags.
1255 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1256 unsigned int bd_num)
1258 unsigned int tot_len = 0;
1261 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1262 tot_len += bd_size[i];
1264 /* ensure the first 8 frags is greater than mss + header */
1265 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1266 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1269 /* ensure every continuous 7 buffer is greater than mss
1270 * except the last one.
1272 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1273 tot_len -= bd_size[i];
1274 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
1276 if (tot_len < skb_shinfo(skb)->gso_size)
1283 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1287 for (i = 0; i < MAX_SKB_FRAGS; i++)
1288 size[i] = skb_frag_size(&shinfo->frags[i]);
1291 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1292 struct net_device *netdev,
1293 struct sk_buff *skb)
1295 struct hns3_nic_priv *priv = netdev_priv(netdev);
1296 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1297 unsigned int bd_num;
1299 bd_num = hns3_tx_bd_num(skb, bd_size);
1300 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1301 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1302 !hns3_skb_need_linearized(skb, bd_size, bd_num)) {
1303 trace_hns3_over_8bd(skb);
1307 if (__skb_linearize(skb))
1310 bd_num = hns3_tx_bd_count(skb->len);
1311 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1312 (!skb_is_gso(skb) &&
1313 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1314 trace_hns3_over_8bd(skb);
1318 u64_stats_update_begin(&ring->syncp);
1319 ring->stats.tx_copy++;
1320 u64_stats_update_end(&ring->syncp);
1324 if (likely(ring_space(ring) >= bd_num))
1327 netif_stop_subqueue(netdev, ring->queue_index);
1328 smp_mb(); /* Memory barrier before checking ring_space */
1330 /* Start queue in case hns3_clean_tx_ring has just made room
1331 * available and has not seen the queue stopped state performed
1332 * by netif_stop_subqueue above.
1334 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1335 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1336 netif_start_subqueue(netdev, ring->queue_index);
1343 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1345 struct device *dev = ring_to_dev(ring);
1348 for (i = 0; i < ring->desc_num; i++) {
1349 /* check if this is where we started */
1350 if (ring->next_to_use == next_to_use_orig)
1354 ring_ptr_move_bw(ring, next_to_use);
1356 /* unmap the descriptor dma address */
1357 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
1358 ring->desc_cb[ring->next_to_use].type ==
1359 DESC_TYPE_FRAGLIST_SKB)
1360 dma_unmap_single(dev,
1361 ring->desc_cb[ring->next_to_use].dma,
1362 ring->desc_cb[ring->next_to_use].length,
1364 else if (ring->desc_cb[ring->next_to_use].length)
1366 ring->desc_cb[ring->next_to_use].dma,
1367 ring->desc_cb[ring->next_to_use].length,
1370 ring->desc_cb[ring->next_to_use].length = 0;
1371 ring->desc_cb[ring->next_to_use].dma = 0;
1375 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1376 struct sk_buff *skb, enum hns_desc_type type)
1378 unsigned int size = skb_headlen(skb);
1379 int i, ret, bd_num = 0;
1382 ret = hns3_fill_desc(ring, skb, size, type);
1383 if (unlikely(ret < 0))
1389 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1390 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1392 size = skb_frag_size(frag);
1396 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1397 if (unlikely(ret < 0))
1406 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1408 struct hns3_nic_priv *priv = netdev_priv(netdev);
1409 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
1410 struct netdev_queue *dev_queue;
1411 int pre_ntu, next_to_use_head;
1412 struct sk_buff *frag_skb;
1416 /* Hardware can only handle short frames above 32 bytes */
1417 if (skb_put_padto(skb, HNS3_MIN_TX_LEN))
1418 return NETDEV_TX_OK;
1420 /* Prefetch the data used later */
1421 prefetch(skb->data);
1423 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
1424 if (unlikely(ret <= 0)) {
1425 if (ret == -EBUSY) {
1426 u64_stats_update_begin(&ring->syncp);
1427 ring->stats.tx_busy++;
1428 u64_stats_update_end(&ring->syncp);
1429 return NETDEV_TX_BUSY;
1430 } else if (ret == -ENOMEM) {
1431 u64_stats_update_begin(&ring->syncp);
1432 ring->stats.sw_err_cnt++;
1433 u64_stats_update_end(&ring->syncp);
1436 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
1440 next_to_use_head = ring->next_to_use;
1442 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1443 if (unlikely(ret < 0))
1448 skb_walk_frags(skb, frag_skb) {
1449 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1450 DESC_TYPE_FRAGLIST_SKB);
1451 if (unlikely(ret < 0))
1457 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1458 (ring->desc_num - 1);
1459 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1460 cpu_to_le16(BIT(HNS3_TXD_FE_B));
1461 trace_hns3_tx_desc(ring, pre_ntu);
1463 /* Complete translate all packets */
1464 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
1465 netdev_tx_sent_queue(dev_queue, skb->len);
1467 wmb(); /* Commit all data before submit */
1469 hnae3_queue_xmit(ring->tqp, bd_num);
1471 return NETDEV_TX_OK;
1474 hns3_clear_desc(ring, next_to_use_head);
1477 dev_kfree_skb_any(skb);
1478 return NETDEV_TX_OK;
1481 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1483 struct hnae3_handle *h = hns3_get_handle(netdev);
1484 struct sockaddr *mac_addr = p;
1487 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1488 return -EADDRNOTAVAIL;
1490 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1491 netdev_info(netdev, "already using mac address %pM\n",
1496 /* For VF device, if there is a perm_addr, then the user will not
1497 * be allowed to change the address.
1499 if (!hns3_is_phys_func(h->pdev) &&
1500 !is_zero_ether_addr(netdev->perm_addr)) {
1501 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1502 netdev->perm_addr, mac_addr->sa_data);
1506 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1508 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1512 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1517 static int hns3_nic_do_ioctl(struct net_device *netdev,
1518 struct ifreq *ifr, int cmd)
1520 struct hnae3_handle *h = hns3_get_handle(netdev);
1522 if (!netif_running(netdev))
1525 if (!h->ae_algo->ops->do_ioctl)
1528 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1531 static int hns3_nic_set_features(struct net_device *netdev,
1532 netdev_features_t features)
1534 netdev_features_t changed = netdev->features ^ features;
1535 struct hns3_nic_priv *priv = netdev_priv(netdev);
1536 struct hnae3_handle *h = priv->ae_handle;
1540 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1541 enable = !!(features & NETIF_F_GRO_HW);
1542 ret = h->ae_algo->ops->set_gro_en(h, enable);
1547 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1548 h->ae_algo->ops->enable_vlan_filter) {
1549 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1550 h->ae_algo->ops->enable_vlan_filter(h, enable);
1553 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1554 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1555 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1556 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
1561 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1562 enable = !!(features & NETIF_F_NTUPLE);
1563 h->ae_algo->ops->enable_fd(h, enable);
1566 netdev->features = features;
1570 static netdev_features_t hns3_features_check(struct sk_buff *skb,
1571 struct net_device *dev,
1572 netdev_features_t features)
1574 #define HNS3_MAX_HDR_LEN 480U
1575 #define HNS3_MAX_L4_HDR_LEN 60U
1579 if (skb->ip_summed != CHECKSUM_PARTIAL)
1582 if (skb->encapsulation)
1583 len = skb_inner_transport_header(skb) - skb->data;
1585 len = skb_transport_header(skb) - skb->data;
1587 /* Assume L4 is 60 byte as TCP is the only protocol with a
1588 * a flexible value, and it's max len is 60 bytes.
1590 len += HNS3_MAX_L4_HDR_LEN;
1592 /* Hardware only supports checksum on the skb with a max header
1595 if (len > HNS3_MAX_HDR_LEN)
1596 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1601 static void hns3_nic_get_stats64(struct net_device *netdev,
1602 struct rtnl_link_stats64 *stats)
1604 struct hns3_nic_priv *priv = netdev_priv(netdev);
1605 int queue_num = priv->ae_handle->kinfo.num_tqps;
1606 struct hnae3_handle *handle = priv->ae_handle;
1607 struct hns3_enet_ring *ring;
1608 u64 rx_length_errors = 0;
1609 u64 rx_crc_errors = 0;
1610 u64 rx_multicast = 0;
1622 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1625 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1627 for (idx = 0; idx < queue_num; idx++) {
1628 /* fetch the tx stats */
1629 ring = &priv->ring[idx];
1631 start = u64_stats_fetch_begin_irq(&ring->syncp);
1632 tx_bytes += ring->stats.tx_bytes;
1633 tx_pkts += ring->stats.tx_pkts;
1634 tx_drop += ring->stats.sw_err_cnt;
1635 tx_drop += ring->stats.tx_vlan_err;
1636 tx_drop += ring->stats.tx_l4_proto_err;
1637 tx_drop += ring->stats.tx_l2l3l4_err;
1638 tx_drop += ring->stats.tx_tso_err;
1639 tx_errors += ring->stats.sw_err_cnt;
1640 tx_errors += ring->stats.tx_vlan_err;
1641 tx_errors += ring->stats.tx_l4_proto_err;
1642 tx_errors += ring->stats.tx_l2l3l4_err;
1643 tx_errors += ring->stats.tx_tso_err;
1644 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1646 /* fetch the rx stats */
1647 ring = &priv->ring[idx + queue_num];
1649 start = u64_stats_fetch_begin_irq(&ring->syncp);
1650 rx_bytes += ring->stats.rx_bytes;
1651 rx_pkts += ring->stats.rx_pkts;
1652 rx_drop += ring->stats.l2_err;
1653 rx_errors += ring->stats.l2_err;
1654 rx_errors += ring->stats.l3l4_csum_err;
1655 rx_crc_errors += ring->stats.l2_err;
1656 rx_multicast += ring->stats.rx_multicast;
1657 rx_length_errors += ring->stats.err_pkt_len;
1658 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1661 stats->tx_bytes = tx_bytes;
1662 stats->tx_packets = tx_pkts;
1663 stats->rx_bytes = rx_bytes;
1664 stats->rx_packets = rx_pkts;
1666 stats->rx_errors = rx_errors;
1667 stats->multicast = rx_multicast;
1668 stats->rx_length_errors = rx_length_errors;
1669 stats->rx_crc_errors = rx_crc_errors;
1670 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1672 stats->tx_errors = tx_errors;
1673 stats->rx_dropped = rx_drop;
1674 stats->tx_dropped = tx_drop;
1675 stats->collisions = netdev->stats.collisions;
1676 stats->rx_over_errors = netdev->stats.rx_over_errors;
1677 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1678 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1679 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1680 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1681 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1682 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1683 stats->tx_window_errors = netdev->stats.tx_window_errors;
1684 stats->rx_compressed = netdev->stats.rx_compressed;
1685 stats->tx_compressed = netdev->stats.tx_compressed;
1688 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1690 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1691 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1692 struct hnae3_knic_private_info *kinfo;
1693 u8 tc = mqprio_qopt->qopt.num_tc;
1694 u16 mode = mqprio_qopt->mode;
1695 u8 hw = mqprio_qopt->qopt.hw;
1696 struct hnae3_handle *h;
1698 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1699 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1702 if (tc > HNAE3_MAX_TC)
1708 h = hns3_get_handle(netdev);
1711 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1713 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1714 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
1717 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1720 if (type != TC_SETUP_QDISC_MQPRIO)
1723 return hns3_setup_tc(dev, type_data);
1726 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1727 __be16 proto, u16 vid)
1729 struct hnae3_handle *h = hns3_get_handle(netdev);
1732 if (h->ae_algo->ops->set_vlan_filter)
1733 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1738 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1739 __be16 proto, u16 vid)
1741 struct hnae3_handle *h = hns3_get_handle(netdev);
1744 if (h->ae_algo->ops->set_vlan_filter)
1745 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1750 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1751 u8 qos, __be16 vlan_proto)
1753 struct hnae3_handle *h = hns3_get_handle(netdev);
1756 netif_dbg(h, drv, netdev,
1757 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1758 vf, vlan, qos, ntohs(vlan_proto));
1760 if (h->ae_algo->ops->set_vf_vlan_filter)
1761 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1767 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1769 struct hnae3_handle *handle = hns3_get_handle(netdev);
1771 if (hns3_nic_resetting(netdev))
1774 if (!handle->ae_algo->ops->set_vf_spoofchk)
1777 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1780 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1782 struct hnae3_handle *handle = hns3_get_handle(netdev);
1784 if (!handle->ae_algo->ops->set_vf_trust)
1787 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1790 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1792 struct hnae3_handle *h = hns3_get_handle(netdev);
1795 if (hns3_nic_resetting(netdev))
1798 if (!h->ae_algo->ops->set_mtu)
1801 netif_dbg(h, drv, netdev,
1802 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1804 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1806 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1809 netdev->mtu = new_mtu;
1814 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1816 struct hns3_nic_priv *priv = netdev_priv(ndev);
1817 struct hnae3_handle *h = hns3_get_handle(ndev);
1818 struct hns3_enet_ring *tx_ring;
1819 struct napi_struct *napi;
1820 int timeout_queue = 0;
1821 int hw_head, hw_tail;
1822 int fbd_num, fbd_oft;
1823 int ebd_num, ebd_oft;
1828 /* Find the stopped queue the same way the stack does */
1829 for (i = 0; i < ndev->num_tx_queues; i++) {
1830 struct netdev_queue *q;
1831 unsigned long trans_start;
1833 q = netdev_get_tx_queue(ndev, i);
1834 trans_start = q->trans_start;
1835 if (netif_xmit_stopped(q) &&
1837 (trans_start + ndev->watchdog_timeo))) {
1839 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1841 jiffies_to_msecs(jiffies - trans_start));
1846 if (i == ndev->num_tx_queues) {
1848 "no netdev TX timeout queue found, timeout count: %llu\n",
1849 priv->tx_timeout_count);
1853 priv->tx_timeout_count++;
1855 tx_ring = &priv->ring[timeout_queue];
1856 napi = &tx_ring->tqp_vector->napi;
1859 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1860 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1861 tx_ring->next_to_clean, napi->state);
1864 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1865 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1866 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1869 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1870 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1871 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1873 /* When mac received many pause frames continuous, it's unable to send
1874 * packets, which may cause tx timeout
1876 if (h->ae_algo->ops->get_mac_stats) {
1877 struct hns3_mac_stats mac_stats;
1879 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
1880 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1881 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
1884 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1885 HNS3_RING_TX_RING_HEAD_REG);
1886 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1887 HNS3_RING_TX_RING_TAIL_REG);
1888 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1889 HNS3_RING_TX_RING_FBDNUM_REG);
1890 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1891 HNS3_RING_TX_RING_OFFSET_REG);
1892 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1893 HNS3_RING_TX_RING_EBDNUM_REG);
1894 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1895 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1896 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1897 HNS3_RING_TX_RING_BD_NUM_REG);
1898 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1899 HNS3_RING_TX_RING_BD_ERR_REG);
1900 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1901 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1904 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1905 bd_num, hw_head, hw_tail, bd_err,
1906 readl(tx_ring->tqp_vector->mask_addr));
1908 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1909 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
1914 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
1916 struct hns3_nic_priv *priv = netdev_priv(ndev);
1917 struct hnae3_handle *h = priv->ae_handle;
1919 if (!hns3_get_tx_timeo_queue_info(ndev))
1922 /* request the reset, and let the hclge to determine
1923 * which reset level should be done
1925 if (h->ae_algo->ops->reset_event)
1926 h->ae_algo->ops->reset_event(h->pdev, h);
1929 #ifdef CONFIG_RFS_ACCEL
1930 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1931 u16 rxq_index, u32 flow_id)
1933 struct hnae3_handle *h = hns3_get_handle(dev);
1934 struct flow_keys fkeys;
1936 if (!h->ae_algo->ops->add_arfs_entry)
1939 if (skb->encapsulation)
1940 return -EPROTONOSUPPORT;
1942 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1943 return -EPROTONOSUPPORT;
1945 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1946 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1947 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1948 fkeys.basic.ip_proto != IPPROTO_UDP))
1949 return -EPROTONOSUPPORT;
1951 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1955 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1956 struct ifla_vf_info *ivf)
1958 struct hnae3_handle *h = hns3_get_handle(ndev);
1960 if (!h->ae_algo->ops->get_vf_config)
1963 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1966 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1969 struct hnae3_handle *h = hns3_get_handle(ndev);
1971 if (!h->ae_algo->ops->set_vf_link_state)
1974 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1977 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1978 int min_tx_rate, int max_tx_rate)
1980 struct hnae3_handle *h = hns3_get_handle(ndev);
1982 if (!h->ae_algo->ops->set_vf_rate)
1985 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1989 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1991 struct hnae3_handle *h = hns3_get_handle(netdev);
1993 if (!h->ae_algo->ops->set_vf_mac)
1996 if (is_multicast_ether_addr(mac)) {
1998 "Invalid MAC:%pM specified. Could not set MAC\n",
2003 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2006 static const struct net_device_ops hns3_nic_netdev_ops = {
2007 .ndo_open = hns3_nic_net_open,
2008 .ndo_stop = hns3_nic_net_stop,
2009 .ndo_start_xmit = hns3_nic_net_xmit,
2010 .ndo_tx_timeout = hns3_nic_net_timeout,
2011 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
2012 .ndo_do_ioctl = hns3_nic_do_ioctl,
2013 .ndo_change_mtu = hns3_nic_change_mtu,
2014 .ndo_set_features = hns3_nic_set_features,
2015 .ndo_features_check = hns3_features_check,
2016 .ndo_get_stats64 = hns3_nic_get_stats64,
2017 .ndo_setup_tc = hns3_nic_setup_tc,
2018 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
2019 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2020 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2021 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
2022 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
2023 .ndo_set_vf_trust = hns3_set_vf_trust,
2024 #ifdef CONFIG_RFS_ACCEL
2025 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2027 .ndo_get_vf_config = hns3_nic_get_vf_config,
2028 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
2029 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
2030 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
2033 bool hns3_is_phys_func(struct pci_dev *pdev)
2035 u32 dev_id = pdev->device;
2038 case HNAE3_DEV_ID_GE:
2039 case HNAE3_DEV_ID_25GE:
2040 case HNAE3_DEV_ID_25GE_RDMA:
2041 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2042 case HNAE3_DEV_ID_50GE_RDMA:
2043 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2044 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2046 case HNAE3_DEV_ID_100G_VF:
2047 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2050 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2057 static void hns3_disable_sriov(struct pci_dev *pdev)
2059 /* If our VFs are assigned we cannot shut down SR-IOV
2060 * without causing issues, so just leave the hardware
2061 * available but disabled
2063 if (pci_vfs_assigned(pdev)) {
2064 dev_warn(&pdev->dev,
2065 "disabling driver while VFs are assigned\n");
2069 pci_disable_sriov(pdev);
2072 static void hns3_get_dev_capability(struct pci_dev *pdev,
2073 struct hnae3_ae_dev *ae_dev)
2075 if (pdev->revision >= 0x21) {
2076 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
2077 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2081 /* hns3_probe - Device initialization routine
2082 * @pdev: PCI device information struct
2083 * @ent: entry in hns3_pci_tbl
2085 * hns3_probe initializes a PF identified by a pci_dev structure.
2086 * The OS initialization, configuring of the PF private structure,
2087 * and a hardware reset occur.
2089 * Returns 0 on success, negative on failure
2091 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2093 struct hnae3_ae_dev *ae_dev;
2096 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2100 ae_dev->pdev = pdev;
2101 ae_dev->flag = ent->driver_data;
2102 hns3_get_dev_capability(pdev, ae_dev);
2103 pci_set_drvdata(pdev, ae_dev);
2105 ret = hnae3_register_ae_dev(ae_dev);
2107 devm_kfree(&pdev->dev, ae_dev);
2108 pci_set_drvdata(pdev, NULL);
2114 /* hns3_remove - Device removal routine
2115 * @pdev: PCI device information struct
2117 static void hns3_remove(struct pci_dev *pdev)
2119 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2121 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2122 hns3_disable_sriov(pdev);
2124 hnae3_unregister_ae_dev(ae_dev);
2125 pci_set_drvdata(pdev, NULL);
2129 * hns3_pci_sriov_configure
2130 * @pdev: pointer to a pci_dev structure
2131 * @num_vfs: number of VFs to allocate
2133 * Enable or change the number of VFs. Called when the user updates the number
2136 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2140 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2141 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2146 ret = pci_enable_sriov(pdev, num_vfs);
2148 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2151 } else if (!pci_vfs_assigned(pdev)) {
2152 pci_disable_sriov(pdev);
2154 dev_warn(&pdev->dev,
2155 "Unable to free VFs because some are assigned to VMs.\n");
2161 static void hns3_shutdown(struct pci_dev *pdev)
2163 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2165 hnae3_unregister_ae_dev(ae_dev);
2166 devm_kfree(&pdev->dev, ae_dev);
2167 pci_set_drvdata(pdev, NULL);
2169 if (system_state == SYSTEM_POWER_OFF)
2170 pci_set_power_state(pdev, PCI_D3hot);
2173 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2174 pci_channel_state_t state)
2176 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2177 pci_ers_result_t ret;
2179 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2181 if (state == pci_channel_io_perm_failure)
2182 return PCI_ERS_RESULT_DISCONNECT;
2184 if (!ae_dev || !ae_dev->ops) {
2186 "Can't recover - error happened before device initialized\n");
2187 return PCI_ERS_RESULT_NONE;
2190 if (ae_dev->ops->handle_hw_ras_error)
2191 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
2193 return PCI_ERS_RESULT_NONE;
2198 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2200 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2201 const struct hnae3_ae_ops *ops;
2202 enum hnae3_reset_type reset_type;
2203 struct device *dev = &pdev->dev;
2205 if (!ae_dev || !ae_dev->ops)
2206 return PCI_ERS_RESULT_NONE;
2209 /* request the reset */
2210 if (ops->reset_event && ops->get_reset_level &&
2211 ops->set_default_reset_request) {
2212 if (ae_dev->hw_err_reset_req) {
2213 reset_type = ops->get_reset_level(ae_dev,
2214 &ae_dev->hw_err_reset_req);
2215 ops->set_default_reset_request(ae_dev, reset_type);
2216 dev_info(dev, "requesting reset due to PCI error\n");
2217 ops->reset_event(pdev, NULL);
2220 return PCI_ERS_RESULT_RECOVERED;
2223 return PCI_ERS_RESULT_DISCONNECT;
2226 static void hns3_reset_prepare(struct pci_dev *pdev)
2228 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2230 dev_info(&pdev->dev, "FLR prepare\n");
2231 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2232 ae_dev->ops->flr_prepare(ae_dev);
2235 static void hns3_reset_done(struct pci_dev *pdev)
2237 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2239 dev_info(&pdev->dev, "FLR done\n");
2240 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2241 ae_dev->ops->flr_done(ae_dev);
2244 static const struct pci_error_handlers hns3_err_handler = {
2245 .error_detected = hns3_error_detected,
2246 .slot_reset = hns3_slot_reset,
2247 .reset_prepare = hns3_reset_prepare,
2248 .reset_done = hns3_reset_done,
2251 static struct pci_driver hns3_driver = {
2252 .name = hns3_driver_name,
2253 .id_table = hns3_pci_tbl,
2254 .probe = hns3_probe,
2255 .remove = hns3_remove,
2256 .shutdown = hns3_shutdown,
2257 .sriov_configure = hns3_pci_sriov_configure,
2258 .err_handler = &hns3_err_handler,
2261 /* set default feature to hns3 */
2262 static void hns3_set_default_feature(struct net_device *netdev)
2264 struct hnae3_handle *h = hns3_get_handle(netdev);
2265 struct pci_dev *pdev = h->pdev;
2267 netdev->priv_flags |= IFF_UNICAST_FLT;
2269 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2270 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2271 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2272 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2273 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2274 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
2276 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2278 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2279 NETIF_F_HW_VLAN_CTAG_FILTER |
2280 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2281 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2282 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2283 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2284 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2287 netdev->vlan_features |=
2288 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2289 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2290 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2291 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2292 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2295 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2296 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2297 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2298 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2299 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2300 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2303 if (pdev->revision >= 0x21) {
2304 netdev->hw_features |= NETIF_F_GRO_HW;
2305 netdev->features |= NETIF_F_GRO_HW;
2307 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2308 netdev->hw_features |= NETIF_F_NTUPLE;
2309 netdev->features |= NETIF_F_NTUPLE;
2314 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2315 struct hns3_desc_cb *cb)
2317 unsigned int order = hns3_page_order(ring);
2320 p = dev_alloc_pages(order);
2325 cb->page_offset = 0;
2327 cb->buf = page_address(p);
2328 cb->length = hns3_page_size(ring);
2329 cb->type = DESC_TYPE_PAGE;
2334 static void hns3_free_buffer(struct hns3_enet_ring *ring,
2335 struct hns3_desc_cb *cb)
2337 if (cb->type == DESC_TYPE_SKB)
2338 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2339 else if (!HNAE3_IS_TX_RING(ring))
2340 put_page((struct page *)cb->priv);
2341 memset(cb, 0, sizeof(*cb));
2344 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2346 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2347 cb->length, ring_to_dma_dir(ring));
2349 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2355 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2356 struct hns3_desc_cb *cb)
2358 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
2359 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2360 ring_to_dma_dir(ring));
2361 else if (cb->length)
2362 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2363 ring_to_dma_dir(ring));
2366 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2368 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2369 ring->desc[i].addr = 0;
2372 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2374 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2376 if (!ring->desc_cb[i].dma)
2379 hns3_buffer_detach(ring, i);
2380 hns3_free_buffer(ring, cb);
2383 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2387 for (i = 0; i < ring->desc_num; i++)
2388 hns3_free_buffer_detach(ring, i);
2391 /* free desc along with its attached buffer */
2392 static void hns3_free_desc(struct hns3_enet_ring *ring)
2394 int size = ring->desc_num * sizeof(ring->desc[0]);
2396 hns3_free_buffers(ring);
2399 dma_free_coherent(ring_to_dev(ring), size,
2400 ring->desc, ring->desc_dma_addr);
2405 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2407 int size = ring->desc_num * sizeof(ring->desc[0]);
2409 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2410 &ring->desc_dma_addr, GFP_KERNEL);
2417 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2418 struct hns3_desc_cb *cb)
2422 ret = hns3_alloc_buffer(ring, cb);
2426 ret = hns3_map_buffer(ring, cb);
2433 hns3_free_buffer(ring, cb);
2438 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2440 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2445 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2450 /* Allocate memory for raw pkg, and map with dma */
2451 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2455 for (i = 0; i < ring->desc_num; i++) {
2456 ret = hns3_alloc_buffer_attach(ring, i);
2458 goto out_buffer_fail;
2464 for (j = i - 1; j >= 0; j--)
2465 hns3_free_buffer_detach(ring, j);
2469 /* detach a in-used buffer and replace with a reserved one */
2470 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2471 struct hns3_desc_cb *res_cb)
2473 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2474 ring->desc_cb[i] = *res_cb;
2475 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2476 ring->desc[i].rx.bd_base_info = 0;
2479 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2481 ring->desc_cb[i].reuse_flag = 0;
2482 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2483 ring->desc_cb[i].page_offset);
2484 ring->desc[i].rx.bd_base_info = 0;
2487 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2488 int *bytes, int *pkts)
2490 int ntc = ring->next_to_clean;
2491 struct hns3_desc_cb *desc_cb;
2493 while (head != ntc) {
2494 desc_cb = &ring->desc_cb[ntc];
2495 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2496 (*bytes) += desc_cb->length;
2497 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2498 hns3_free_buffer_detach(ring, ntc);
2500 if (++ntc == ring->desc_num)
2503 /* Issue prefetch for next Tx descriptor */
2504 prefetch(&ring->desc_cb[ntc]);
2507 /* This smp_store_release() pairs with smp_load_acquire() in
2508 * ring_space called by hns3_nic_net_xmit.
2510 smp_store_release(&ring->next_to_clean, ntc);
2513 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2515 int u = ring->next_to_use;
2516 int c = ring->next_to_clean;
2518 if (unlikely(h > ring->desc_num))
2521 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2524 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2526 struct net_device *netdev = ring_to_netdev(ring);
2527 struct hns3_nic_priv *priv = netdev_priv(netdev);
2528 struct netdev_queue *dev_queue;
2532 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2534 if (is_ring_empty(ring) || head == ring->next_to_clean)
2535 return; /* no data to poll */
2537 rmb(); /* Make sure head is ready before touch any data */
2539 if (unlikely(!is_valid_clean_head(ring, head))) {
2540 hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head,
2541 ring->next_to_use, ring->next_to_clean);
2543 u64_stats_update_begin(&ring->syncp);
2544 ring->stats.io_err_cnt++;
2545 u64_stats_update_end(&ring->syncp);
2551 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
2553 ring->tqp_vector->tx_group.total_bytes += bytes;
2554 ring->tqp_vector->tx_group.total_packets += pkts;
2556 u64_stats_update_begin(&ring->syncp);
2557 ring->stats.tx_bytes += bytes;
2558 ring->stats.tx_pkts += pkts;
2559 u64_stats_update_end(&ring->syncp);
2561 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2562 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2564 if (unlikely(netif_carrier_ok(netdev) &&
2565 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
2566 /* Make sure that anybody stopping the queue after this
2567 * sees the new next_to_clean.
2570 if (netif_tx_queue_stopped(dev_queue) &&
2571 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2572 netif_tx_wake_queue(dev_queue);
2573 ring->stats.restart_queue++;
2578 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2580 int ntc = ring->next_to_clean;
2581 int ntu = ring->next_to_use;
2583 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2586 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2589 struct hns3_desc_cb *desc_cb;
2590 struct hns3_desc_cb res_cbs;
2593 for (i = 0; i < cleand_count; i++) {
2594 desc_cb = &ring->desc_cb[ring->next_to_use];
2595 if (desc_cb->reuse_flag) {
2596 u64_stats_update_begin(&ring->syncp);
2597 ring->stats.reuse_pg_cnt++;
2598 u64_stats_update_end(&ring->syncp);
2600 hns3_reuse_buffer(ring, ring->next_to_use);
2602 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2604 u64_stats_update_begin(&ring->syncp);
2605 ring->stats.sw_err_cnt++;
2606 u64_stats_update_end(&ring->syncp);
2608 hns3_rl_err(ring_to_netdev(ring),
2609 "alloc rx buffer failed: %d\n",
2613 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2615 u64_stats_update_begin(&ring->syncp);
2616 ring->stats.non_reuse_pg++;
2617 u64_stats_update_end(&ring->syncp);
2620 ring_ptr_move_fw(ring, next_to_use);
2623 wmb(); /* Make all data has been write before submit */
2624 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2627 static bool hns3_page_is_reusable(struct page *page)
2629 return page_to_nid(page) == numa_mem_id() &&
2630 !page_is_pfmemalloc(page);
2633 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2634 struct hns3_enet_ring *ring, int pull_len,
2635 struct hns3_desc_cb *desc_cb)
2637 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2638 int size = le16_to_cpu(desc->rx.size);
2639 u32 truesize = hns3_buf_size(ring);
2641 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2642 size - pull_len, truesize);
2644 /* Avoid re-using remote pages, or the stack is still using the page
2645 * when page_offset rollback to zero, flag default unreuse
2647 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
2648 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
2651 /* Move offset up to the next cache line */
2652 desc_cb->page_offset += truesize;
2654 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
2655 desc_cb->reuse_flag = 1;
2656 /* Bump ref count on page before it is given */
2657 get_page(desc_cb->priv);
2658 } else if (page_count(desc_cb->priv) == 1) {
2659 desc_cb->reuse_flag = 1;
2660 desc_cb->page_offset = 0;
2661 get_page(desc_cb->priv);
2665 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
2667 __be16 type = skb->protocol;
2671 while (eth_type_vlan(type)) {
2672 struct vlan_hdr *vh;
2674 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2677 vh = (struct vlan_hdr *)(skb->data + depth);
2678 type = vh->h_vlan_encapsulated_proto;
2682 skb_set_network_header(skb, depth);
2684 if (type == htons(ETH_P_IP)) {
2685 const struct iphdr *iph = ip_hdr(skb);
2687 depth += sizeof(struct iphdr);
2688 skb_set_transport_header(skb, depth);
2690 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2692 } else if (type == htons(ETH_P_IPV6)) {
2693 const struct ipv6hdr *iph = ipv6_hdr(skb);
2695 depth += sizeof(struct ipv6hdr);
2696 skb_set_transport_header(skb, depth);
2698 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2701 hns3_rl_err(skb->dev,
2702 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2703 be16_to_cpu(type), depth);
2707 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2709 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2711 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2712 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
2714 skb->csum_start = (unsigned char *)th - skb->head;
2715 skb->csum_offset = offsetof(struct tcphdr, check);
2716 skb->ip_summed = CHECKSUM_PARTIAL;
2718 trace_hns3_gro(skb);
2723 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2724 u32 l234info, u32 bd_base_info, u32 ol_info)
2726 struct net_device *netdev = ring_to_netdev(ring);
2727 int l3_type, l4_type;
2730 skb->ip_summed = CHECKSUM_NONE;
2732 skb_checksum_none_assert(skb);
2734 if (!(netdev->features & NETIF_F_RXCSUM))
2737 /* check if hardware has done checksum */
2738 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2741 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2742 BIT(HNS3_RXD_OL3E_B) |
2743 BIT(HNS3_RXD_OL4E_B)))) {
2744 u64_stats_update_begin(&ring->syncp);
2745 ring->stats.l3l4_csum_err++;
2746 u64_stats_update_end(&ring->syncp);
2751 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
2754 case HNS3_OL4_TYPE_MAC_IN_UDP:
2755 case HNS3_OL4_TYPE_NVGRE:
2756 skb->csum_level = 1;
2758 case HNS3_OL4_TYPE_NO_TUN:
2759 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2761 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2764 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2765 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2766 l3_type == HNS3_L3_TYPE_IPV6) &&
2767 (l4_type == HNS3_L4_TYPE_UDP ||
2768 l4_type == HNS3_L4_TYPE_TCP ||
2769 l4_type == HNS3_L4_TYPE_SCTP))
2770 skb->ip_summed = CHECKSUM_UNNECESSARY;
2777 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2779 if (skb_has_frag_list(skb))
2780 napi_gro_flush(&ring->tqp_vector->napi, false);
2782 napi_gro_receive(&ring->tqp_vector->napi, skb);
2785 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2786 struct hns3_desc *desc, u32 l234info,
2789 struct hnae3_handle *handle = ring->tqp->handle;
2790 struct pci_dev *pdev = ring->tqp->handle->pdev;
2792 if (pdev->revision == 0x20) {
2793 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2794 if (!(*vlan_tag & VLAN_VID_MASK))
2795 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2797 return (*vlan_tag != 0);
2800 #define HNS3_STRP_OUTER_VLAN 0x1
2801 #define HNS3_STRP_INNER_VLAN 0x2
2802 #define HNS3_STRP_BOTH 0x3
2804 /* Hardware always insert VLAN tag into RX descriptor when
2805 * remove the tag from packet, driver needs to determine
2806 * reporting which tag to stack.
2808 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2809 HNS3_RXD_STRP_TAGP_S)) {
2810 case HNS3_STRP_OUTER_VLAN:
2811 if (handle->port_base_vlan_state !=
2812 HNAE3_PORT_BASE_VLAN_DISABLE)
2815 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2817 case HNS3_STRP_INNER_VLAN:
2818 if (handle->port_base_vlan_state !=
2819 HNAE3_PORT_BASE_VLAN_DISABLE)
2822 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2824 case HNS3_STRP_BOTH:
2825 if (handle->port_base_vlan_state ==
2826 HNAE3_PORT_BASE_VLAN_DISABLE)
2827 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2829 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2837 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
2840 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2841 struct net_device *netdev = ring_to_netdev(ring);
2842 struct sk_buff *skb;
2844 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2846 if (unlikely(!skb)) {
2847 hns3_rl_err(netdev, "alloc rx skb fail\n");
2849 u64_stats_update_begin(&ring->syncp);
2850 ring->stats.sw_err_cnt++;
2851 u64_stats_update_end(&ring->syncp);
2856 trace_hns3_rx_desc(ring);
2857 prefetchw(skb->data);
2859 ring->pending_buf = 1;
2861 ring->tail_skb = NULL;
2862 if (length <= HNS3_RX_HEAD_SIZE) {
2863 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2865 /* We can reuse buffer as-is, just make sure it is local */
2866 if (likely(hns3_page_is_reusable(desc_cb->priv)))
2867 desc_cb->reuse_flag = 1;
2868 else /* This page cannot be reused so discard it */
2869 put_page(desc_cb->priv);
2871 ring_ptr_move_fw(ring, next_to_clean);
2874 u64_stats_update_begin(&ring->syncp);
2875 ring->stats.seg_pkt_cnt++;
2876 u64_stats_update_end(&ring->syncp);
2878 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
2879 __skb_put(skb, ring->pull_len);
2880 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2882 ring_ptr_move_fw(ring, next_to_clean);
2887 static int hns3_add_frag(struct hns3_enet_ring *ring)
2889 struct sk_buff *skb = ring->skb;
2890 struct sk_buff *head_skb = skb;
2891 struct sk_buff *new_skb;
2892 struct hns3_desc_cb *desc_cb;
2893 struct hns3_desc *desc;
2897 desc = &ring->desc[ring->next_to_clean];
2898 desc_cb = &ring->desc_cb[ring->next_to_clean];
2899 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2900 /* make sure HW write desc complete */
2902 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
2905 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2906 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
2907 if (unlikely(!new_skb)) {
2908 hns3_rl_err(ring_to_netdev(ring),
2909 "alloc rx fraglist skb fail\n");
2914 if (ring->tail_skb) {
2915 ring->tail_skb->next = new_skb;
2916 ring->tail_skb = new_skb;
2918 skb_shinfo(skb)->frag_list = new_skb;
2919 ring->tail_skb = new_skb;
2923 if (ring->tail_skb) {
2924 head_skb->truesize += hns3_buf_size(ring);
2925 head_skb->data_len += le16_to_cpu(desc->rx.size);
2926 head_skb->len += le16_to_cpu(desc->rx.size);
2927 skb = ring->tail_skb;
2930 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2931 trace_hns3_rx_desc(ring);
2932 ring_ptr_move_fw(ring, next_to_clean);
2933 ring->pending_buf++;
2934 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
2939 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2940 struct sk_buff *skb, u32 l234info,
2941 u32 bd_base_info, u32 ol_info)
2945 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2946 HNS3_RXD_GRO_SIZE_M,
2947 HNS3_RXD_GRO_SIZE_S);
2948 /* if there is no HW GRO, do not set gro params */
2949 if (!skb_shinfo(skb)->gso_size) {
2950 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
2954 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2955 HNS3_RXD_GRO_COUNT_M,
2956 HNS3_RXD_GRO_COUNT_S);
2958 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
2959 if (l3_type == HNS3_L3_TYPE_IPV4)
2960 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2961 else if (l3_type == HNS3_L3_TYPE_IPV6)
2962 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2966 return hns3_gro_complete(skb, l234info);
2969 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2970 struct sk_buff *skb, u32 rss_hash)
2972 struct hnae3_handle *handle = ring->tqp->handle;
2973 enum pkt_hash_types rss_type;
2976 rss_type = handle->kinfo.rss_type;
2978 rss_type = PKT_HASH_TYPE_NONE;
2980 skb_set_hash(skb, rss_hash, rss_type);
2983 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
2985 struct net_device *netdev = ring_to_netdev(ring);
2986 enum hns3_pkt_l2t_type l2_frame_type;
2987 u32 bd_base_info, l234info, ol_info;
2988 struct hns3_desc *desc;
2992 /* bdinfo handled below is only valid on the last BD of the
2993 * current packet, and ring->next_to_clean indicates the first
2994 * descriptor of next packet, so need - 1 below.
2996 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2997 (ring->desc_num - 1);
2998 desc = &ring->desc[pre_ntc];
2999 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3000 l234info = le32_to_cpu(desc->rx.l234_info);
3001 ol_info = le32_to_cpu(desc->rx.ol_info);
3003 /* Based on hw strategy, the tag offloaded will be stored at
3004 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
3005 * in one layer tag case.
3007 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3010 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
3011 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3015 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3016 BIT(HNS3_RXD_L2E_B))))) {
3017 u64_stats_update_begin(&ring->syncp);
3018 if (l234info & BIT(HNS3_RXD_L2E_B))
3019 ring->stats.l2_err++;
3021 ring->stats.err_pkt_len++;
3022 u64_stats_update_end(&ring->syncp);
3029 /* Do update ip stack process */
3030 skb->protocol = eth_type_trans(skb, netdev);
3032 /* This is needed in order to enable forwarding support */
3033 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3034 bd_base_info, ol_info);
3035 if (unlikely(ret)) {
3036 u64_stats_update_begin(&ring->syncp);
3037 ring->stats.rx_err_cnt++;
3038 u64_stats_update_end(&ring->syncp);
3042 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3045 u64_stats_update_begin(&ring->syncp);
3046 ring->stats.rx_pkts++;
3047 ring->stats.rx_bytes += len;
3049 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3050 ring->stats.rx_multicast++;
3052 u64_stats_update_end(&ring->syncp);
3054 ring->tqp_vector->rx_group.total_bytes += len;
3056 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
3060 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
3062 struct sk_buff *skb = ring->skb;
3063 struct hns3_desc_cb *desc_cb;
3064 struct hns3_desc *desc;
3065 unsigned int length;
3069 desc = &ring->desc[ring->next_to_clean];
3070 desc_cb = &ring->desc_cb[ring->next_to_clean];
3074 length = le16_to_cpu(desc->rx.size);
3075 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3077 /* Check valid BD */
3078 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3082 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
3084 /* Prefetch first cache line of first page
3085 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3086 * line size is 64B so need to prefetch twice to make it 128B. But in
3087 * actual we can have greater size of caches with 128B Level 1 cache
3088 * lines. In such a case, single fetch would suffice to cache in the
3089 * relevant part of the header.
3092 #if L1_CACHE_BYTES < 128
3093 prefetch(ring->va + L1_CACHE_BYTES);
3097 ret = hns3_alloc_skb(ring, length, ring->va);
3100 if (ret < 0) /* alloc buffer fail */
3102 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3103 ret = hns3_add_frag(ring);
3108 ret = hns3_add_frag(ring);
3113 /* As the head data may be changed when GRO enable, copy
3114 * the head data in after other data rx completed
3116 if (skb->len > HNS3_RX_HEAD_SIZE)
3117 memcpy(skb->data, ring->va,
3118 ALIGN(ring->pull_len, sizeof(long)));
3120 ret = hns3_handle_bdinfo(ring, skb);
3121 if (unlikely(ret)) {
3122 dev_kfree_skb_any(skb);
3126 skb_record_rx_queue(skb, ring->tqp->tqp_index);
3130 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3131 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
3133 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
3134 int unused_count = hns3_desc_unused(ring);
3139 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
3140 num -= unused_count;
3141 unused_count -= ring->pending_buf;
3146 rmb(); /* Make sure num taken effect before the other data is touched */
3148 while (recv_pkts < budget && recv_bds < num) {
3149 /* Reuse or realloc buffers */
3150 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3151 hns3_nic_alloc_rx_buffers(ring, unused_count);
3152 unused_count = hns3_desc_unused(ring) -
3157 err = hns3_handle_rx_bd(ring);
3158 /* Do not get FE for the packet or failed to alloc skb */
3159 if (unlikely(!ring->skb || err == -ENXIO)) {
3161 } else if (likely(!err)) {
3162 rx_fn(ring, ring->skb);
3166 recv_bds += ring->pending_buf;
3167 unused_count += ring->pending_buf;
3169 ring->pending_buf = 0;
3173 /* Make all data has been write before submit */
3174 if (unused_count > 0)
3175 hns3_nic_alloc_rx_buffers(ring, unused_count);
3180 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
3182 #define HNS3_RX_LOW_BYTE_RATE 10000
3183 #define HNS3_RX_MID_BYTE_RATE 20000
3184 #define HNS3_RX_ULTRA_PACKET_RATE 40
3186 enum hns3_flow_level_range new_flow_level;
3187 struct hns3_enet_tqp_vector *tqp_vector;
3188 int packets_per_msecs, bytes_per_msecs;
3191 tqp_vector = ring_group->ring->tqp_vector;
3193 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
3194 if (!time_passed_ms)
3197 do_div(ring_group->total_packets, time_passed_ms);
3198 packets_per_msecs = ring_group->total_packets;
3200 do_div(ring_group->total_bytes, time_passed_ms);
3201 bytes_per_msecs = ring_group->total_bytes;
3203 new_flow_level = ring_group->coal.flow_level;
3205 /* Simple throttlerate management
3206 * 0-10MB/s lower (50000 ints/s)
3207 * 10-20MB/s middle (20000 ints/s)
3208 * 20-1249MB/s high (18000 ints/s)
3209 * > 40000pps ultra (8000 ints/s)
3211 switch (new_flow_level) {
3213 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
3214 new_flow_level = HNS3_FLOW_MID;
3217 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
3218 new_flow_level = HNS3_FLOW_HIGH;
3219 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
3220 new_flow_level = HNS3_FLOW_LOW;
3222 case HNS3_FLOW_HIGH:
3223 case HNS3_FLOW_ULTRA:
3225 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
3226 new_flow_level = HNS3_FLOW_MID;
3230 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3231 &tqp_vector->rx_group == ring_group)
3232 new_flow_level = HNS3_FLOW_ULTRA;
3234 ring_group->total_bytes = 0;
3235 ring_group->total_packets = 0;
3236 ring_group->coal.flow_level = new_flow_level;
3241 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3243 struct hns3_enet_tqp_vector *tqp_vector;
3246 if (!ring_group->ring)
3249 tqp_vector = ring_group->ring->tqp_vector;
3250 if (!tqp_vector->last_jiffies)
3253 if (ring_group->total_packets == 0) {
3254 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3255 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3259 if (!hns3_get_new_flow_lvl(ring_group))
3262 new_int_gl = ring_group->coal.int_gl;
3263 switch (ring_group->coal.flow_level) {
3265 new_int_gl = HNS3_INT_GL_50K;
3268 new_int_gl = HNS3_INT_GL_20K;
3270 case HNS3_FLOW_HIGH:
3271 new_int_gl = HNS3_INT_GL_18K;
3273 case HNS3_FLOW_ULTRA:
3274 new_int_gl = HNS3_INT_GL_8K;
3280 if (new_int_gl != ring_group->coal.int_gl) {
3281 ring_group->coal.int_gl = new_int_gl;
3287 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3289 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3290 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3291 bool rx_update, tx_update;
3293 /* update param every 1000ms */
3294 if (time_before(jiffies,
3295 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3298 if (rx_group->coal.gl_adapt_enable) {
3299 rx_update = hns3_get_new_int_gl(rx_group);
3301 hns3_set_vector_coalesce_rx_gl(tqp_vector,
3302 rx_group->coal.int_gl);
3305 if (tx_group->coal.gl_adapt_enable) {
3306 tx_update = hns3_get_new_int_gl(tx_group);
3308 hns3_set_vector_coalesce_tx_gl(tqp_vector,
3309 tx_group->coal.int_gl);
3312 tqp_vector->last_jiffies = jiffies;
3315 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3317 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
3318 struct hns3_enet_ring *ring;
3319 int rx_pkt_total = 0;
3321 struct hns3_enet_tqp_vector *tqp_vector =
3322 container_of(napi, struct hns3_enet_tqp_vector, napi);
3323 bool clean_complete = true;
3324 int rx_budget = budget;
3326 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3327 napi_complete(napi);
3331 /* Since the actual Tx work is minimal, we can give the Tx a larger
3332 * budget and be more aggressive about cleaning up the Tx descriptors.
3334 hns3_for_each_ring(ring, tqp_vector->tx_group)
3335 hns3_clean_tx_ring(ring);
3337 /* make sure rx ring budget not smaller than 1 */
3338 if (tqp_vector->num_tqps > 1)
3339 rx_budget = max(budget / tqp_vector->num_tqps, 1);
3341 hns3_for_each_ring(ring, tqp_vector->rx_group) {
3342 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3345 if (rx_cleaned >= rx_budget)
3346 clean_complete = false;
3348 rx_pkt_total += rx_cleaned;
3351 tqp_vector->rx_group.total_packets += rx_pkt_total;
3353 if (!clean_complete)
3356 if (napi_complete(napi) &&
3357 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3358 hns3_update_new_int_gl(tqp_vector);
3359 hns3_mask_vector_irq(tqp_vector, 1);
3362 return rx_pkt_total;
3365 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3366 struct hnae3_ring_chain_node *head)
3368 struct pci_dev *pdev = tqp_vector->handle->pdev;
3369 struct hnae3_ring_chain_node *cur_chain = head;
3370 struct hnae3_ring_chain_node *chain;
3371 struct hns3_enet_ring *tx_ring;
3372 struct hns3_enet_ring *rx_ring;
3374 tx_ring = tqp_vector->tx_group.ring;
3376 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
3377 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3378 HNAE3_RING_TYPE_TX);
3379 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3380 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
3382 cur_chain->next = NULL;
3384 while (tx_ring->next) {
3385 tx_ring = tx_ring->next;
3387 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3390 goto err_free_chain;
3392 cur_chain->next = chain;
3393 chain->tqp_index = tx_ring->tqp->tqp_index;
3394 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3395 HNAE3_RING_TYPE_TX);
3396 hnae3_set_field(chain->int_gl_idx,
3397 HNAE3_RING_GL_IDX_M,
3398 HNAE3_RING_GL_IDX_S,
3405 rx_ring = tqp_vector->rx_group.ring;
3406 if (!tx_ring && rx_ring) {
3407 cur_chain->next = NULL;
3408 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3409 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3410 HNAE3_RING_TYPE_RX);
3411 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3412 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3414 rx_ring = rx_ring->next;
3418 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3420 goto err_free_chain;
3422 cur_chain->next = chain;
3423 chain->tqp_index = rx_ring->tqp->tqp_index;
3424 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3425 HNAE3_RING_TYPE_RX);
3426 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3427 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3431 rx_ring = rx_ring->next;
3437 cur_chain = head->next;
3439 chain = cur_chain->next;
3440 devm_kfree(&pdev->dev, cur_chain);
3448 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3449 struct hnae3_ring_chain_node *head)
3451 struct pci_dev *pdev = tqp_vector->handle->pdev;
3452 struct hnae3_ring_chain_node *chain_tmp, *chain;
3457 chain_tmp = chain->next;
3458 devm_kfree(&pdev->dev, chain);
3463 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3464 struct hns3_enet_ring *ring)
3466 ring->next = group->ring;
3472 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3474 struct pci_dev *pdev = priv->ae_handle->pdev;
3475 struct hns3_enet_tqp_vector *tqp_vector;
3476 int num_vectors = priv->vector_num;
3480 numa_node = dev_to_node(&pdev->dev);
3482 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3483 tqp_vector = &priv->tqp_vector[vector_i];
3484 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3485 &tqp_vector->affinity_mask);
3489 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3491 struct hnae3_ring_chain_node vector_ring_chain;
3492 struct hnae3_handle *h = priv->ae_handle;
3493 struct hns3_enet_tqp_vector *tqp_vector;
3497 hns3_nic_set_cpumask(priv);
3499 for (i = 0; i < priv->vector_num; i++) {
3500 tqp_vector = &priv->tqp_vector[i];
3501 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3502 tqp_vector->num_tqps = 0;
3505 for (i = 0; i < h->kinfo.num_tqps; i++) {
3506 u16 vector_i = i % priv->vector_num;
3507 u16 tqp_num = h->kinfo.num_tqps;
3509 tqp_vector = &priv->tqp_vector[vector_i];
3511 hns3_add_ring_to_group(&tqp_vector->tx_group,
3514 hns3_add_ring_to_group(&tqp_vector->rx_group,
3515 &priv->ring[i + tqp_num]);
3517 priv->ring[i].tqp_vector = tqp_vector;
3518 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
3519 tqp_vector->num_tqps++;
3522 for (i = 0; i < priv->vector_num; i++) {
3523 tqp_vector = &priv->tqp_vector[i];
3525 tqp_vector->rx_group.total_bytes = 0;
3526 tqp_vector->rx_group.total_packets = 0;
3527 tqp_vector->tx_group.total_bytes = 0;
3528 tqp_vector->tx_group.total_packets = 0;
3529 tqp_vector->handle = h;
3531 ret = hns3_get_vector_ring_chain(tqp_vector,
3532 &vector_ring_chain);
3536 ret = h->ae_algo->ops->map_ring_to_vector(h,
3537 tqp_vector->vector_irq, &vector_ring_chain);
3539 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3544 netif_napi_add(priv->netdev, &tqp_vector->napi,
3545 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3552 netif_napi_del(&priv->tqp_vector[i].napi);
3557 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3559 #define HNS3_VECTOR_PF_MAX_NUM 64
3561 struct hnae3_handle *h = priv->ae_handle;
3562 struct hns3_enet_tqp_vector *tqp_vector;
3563 struct hnae3_vector_info *vector;
3564 struct pci_dev *pdev = h->pdev;
3565 u16 tqp_num = h->kinfo.num_tqps;
3570 /* RSS size, cpu online and vector_num should be the same */
3571 /* Should consider 2p/4p later */
3572 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3573 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3575 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3580 /* save the actual available vector number */
3581 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3583 priv->vector_num = vector_num;
3584 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3585 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3587 if (!priv->tqp_vector) {
3592 for (i = 0; i < priv->vector_num; i++) {
3593 tqp_vector = &priv->tqp_vector[i];
3594 tqp_vector->idx = i;
3595 tqp_vector->mask_addr = vector[i].io_addr;
3596 tqp_vector->vector_irq = vector[i].vector;
3597 hns3_vector_gl_rl_init(tqp_vector, priv);
3601 devm_kfree(&pdev->dev, vector);
3605 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3611 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3613 struct hnae3_ring_chain_node vector_ring_chain;
3614 struct hnae3_handle *h = priv->ae_handle;
3615 struct hns3_enet_tqp_vector *tqp_vector;
3618 for (i = 0; i < priv->vector_num; i++) {
3619 tqp_vector = &priv->tqp_vector[i];
3621 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3624 /* Since the mapping can be overwritten, when fail to get the
3625 * chain between vector and ring, we should go on to deal with
3626 * the remaining options.
3628 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3629 dev_warn(priv->dev, "failed to get ring chain\n");
3631 h->ae_algo->ops->unmap_ring_from_vector(h,
3632 tqp_vector->vector_irq, &vector_ring_chain);
3634 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3636 hns3_clear_ring_group(&tqp_vector->rx_group);
3637 hns3_clear_ring_group(&tqp_vector->tx_group);
3638 netif_napi_del(&priv->tqp_vector[i].napi);
3642 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3644 struct hnae3_handle *h = priv->ae_handle;
3645 struct pci_dev *pdev = h->pdev;
3648 for (i = 0; i < priv->vector_num; i++) {
3649 struct hns3_enet_tqp_vector *tqp_vector;
3651 tqp_vector = &priv->tqp_vector[i];
3652 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3657 devm_kfree(&pdev->dev, priv->tqp_vector);
3660 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3661 unsigned int ring_type)
3663 int queue_num = priv->ae_handle->kinfo.num_tqps;
3664 struct hns3_enet_ring *ring;
3667 if (ring_type == HNAE3_RING_TYPE_TX) {
3668 ring = &priv->ring[q->tqp_index];
3669 desc_num = priv->ae_handle->kinfo.num_tx_desc;
3670 ring->queue_index = q->tqp_index;
3671 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3673 ring = &priv->ring[q->tqp_index + queue_num];
3674 desc_num = priv->ae_handle->kinfo.num_rx_desc;
3675 ring->queue_index = q->tqp_index;
3676 ring->io_base = q->io_base;
3679 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3683 ring->desc_cb = NULL;
3684 ring->dev = priv->dev;
3685 ring->desc_dma_addr = 0;
3686 ring->buf_size = q->buf_size;
3687 ring->desc_num = desc_num;
3688 ring->next_to_use = 0;
3689 ring->next_to_clean = 0;
3692 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3693 struct hns3_nic_priv *priv)
3695 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3696 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3699 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3701 struct hnae3_handle *h = priv->ae_handle;
3702 struct pci_dev *pdev = h->pdev;
3705 priv->ring = devm_kzalloc(&pdev->dev,
3706 array3_size(h->kinfo.num_tqps,
3707 sizeof(*priv->ring), 2),
3712 for (i = 0; i < h->kinfo.num_tqps; i++)
3713 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3718 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3723 devm_kfree(priv->dev, priv->ring);
3727 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3731 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3734 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3735 sizeof(ring->desc_cb[0]), GFP_KERNEL);
3736 if (!ring->desc_cb) {
3741 ret = hns3_alloc_desc(ring);
3743 goto out_with_desc_cb;
3745 if (!HNAE3_IS_TX_RING(ring)) {
3746 ret = hns3_alloc_ring_buffers(ring);
3754 hns3_free_desc(ring);
3756 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3757 ring->desc_cb = NULL;
3762 void hns3_fini_ring(struct hns3_enet_ring *ring)
3764 hns3_free_desc(ring);
3765 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3766 ring->desc_cb = NULL;
3767 ring->next_to_clean = 0;
3768 ring->next_to_use = 0;
3769 ring->pending_buf = 0;
3771 dev_kfree_skb_any(ring->skb);
3776 static int hns3_buf_size2type(u32 buf_size)
3782 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3785 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3788 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3791 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3794 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3797 return bd_size_type;
3800 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3802 dma_addr_t dma = ring->desc_dma_addr;
3803 struct hnae3_queue *q = ring->tqp;
3805 if (!HNAE3_IS_TX_RING(ring)) {
3806 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
3807 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3808 (u32)((dma >> 31) >> 1));
3810 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3811 hns3_buf_size2type(ring->buf_size));
3812 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3813 ring->desc_num / 8 - 1);
3816 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3818 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3819 (u32)((dma >> 31) >> 1));
3821 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3822 ring->desc_num / 8 - 1);
3826 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3828 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3831 for (i = 0; i < HNAE3_MAX_TC; i++) {
3832 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3835 if (!tc_info->enable)
3838 for (j = 0; j < tc_info->tqp_count; j++) {
3839 struct hnae3_queue *q;
3841 q = priv->ring[tc_info->tqp_offset + j].tqp;
3842 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3848 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3850 struct hnae3_handle *h = priv->ae_handle;
3851 int ring_num = h->kinfo.num_tqps * 2;
3855 for (i = 0; i < ring_num; i++) {
3856 ret = hns3_alloc_ring_memory(&priv->ring[i]);
3859 "Alloc ring memory fail! ret=%d\n", ret);
3860 goto out_when_alloc_ring_memory;
3863 u64_stats_init(&priv->ring[i].syncp);
3868 out_when_alloc_ring_memory:
3869 for (j = i - 1; j >= 0; j--)
3870 hns3_fini_ring(&priv->ring[j]);
3875 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3877 struct hnae3_handle *h = priv->ae_handle;
3880 for (i = 0; i < h->kinfo.num_tqps; i++) {
3881 hns3_fini_ring(&priv->ring[i]);
3882 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
3887 /* Set mac addr if it is configured. or leave it to the AE driver */
3888 static int hns3_init_mac_addr(struct net_device *netdev)
3890 struct hns3_nic_priv *priv = netdev_priv(netdev);
3891 struct hnae3_handle *h = priv->ae_handle;
3892 u8 mac_addr_temp[ETH_ALEN];
3895 if (h->ae_algo->ops->get_mac_addr)
3896 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3898 /* Check if the MAC address is valid, if not get a random one */
3899 if (!is_valid_ether_addr(mac_addr_temp)) {
3900 eth_hw_addr_random(netdev);
3901 dev_warn(priv->dev, "using random MAC address %pM\n",
3903 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
3904 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3905 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
3910 if (h->ae_algo->ops->set_mac_addr)
3911 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3916 static int hns3_init_phy(struct net_device *netdev)
3918 struct hnae3_handle *h = hns3_get_handle(netdev);
3921 if (h->ae_algo->ops->mac_connect_phy)
3922 ret = h->ae_algo->ops->mac_connect_phy(h);
3927 static void hns3_uninit_phy(struct net_device *netdev)
3929 struct hnae3_handle *h = hns3_get_handle(netdev);
3931 if (h->ae_algo->ops->mac_disconnect_phy)
3932 h->ae_algo->ops->mac_disconnect_phy(h);
3935 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3937 struct hnae3_handle *h = hns3_get_handle(netdev);
3939 if (h->ae_algo->ops->del_all_fd_entries)
3940 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3943 static int hns3_client_start(struct hnae3_handle *handle)
3945 if (!handle->ae_algo->ops->client_start)
3948 return handle->ae_algo->ops->client_start(handle);
3951 static void hns3_client_stop(struct hnae3_handle *handle)
3953 if (!handle->ae_algo->ops->client_stop)
3956 handle->ae_algo->ops->client_stop(handle);
3959 static void hns3_info_show(struct hns3_nic_priv *priv)
3961 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3963 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3964 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3965 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3966 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3967 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3968 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3969 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3970 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3971 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
3974 static int hns3_client_init(struct hnae3_handle *handle)
3976 struct pci_dev *pdev = handle->pdev;
3977 u16 alloc_tqps, max_rss_size;
3978 struct hns3_nic_priv *priv;
3979 struct net_device *netdev;
3982 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3984 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3988 priv = netdev_priv(netdev);
3989 priv->dev = &pdev->dev;
3990 priv->netdev = netdev;
3991 priv->ae_handle = handle;
3992 priv->tx_timeout_count = 0;
3993 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
3995 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3997 handle->kinfo.netdev = netdev;
3998 handle->priv = (void *)priv;
4000 hns3_init_mac_addr(netdev);
4002 hns3_set_default_feature(netdev);
4004 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
4005 netdev->priv_flags |= IFF_UNICAST_FLT;
4006 netdev->netdev_ops = &hns3_nic_netdev_ops;
4007 SET_NETDEV_DEV(netdev, &pdev->dev);
4008 hns3_ethtool_set_ops(netdev);
4010 /* Carrier off reporting is important to ethtool even BEFORE open */
4011 netif_carrier_off(netdev);
4013 ret = hns3_get_ring_config(priv);
4016 goto out_get_ring_cfg;
4019 ret = hns3_nic_alloc_vector_data(priv);
4022 goto out_alloc_vector_data;
4025 ret = hns3_nic_init_vector_data(priv);
4028 goto out_init_vector_data;
4031 ret = hns3_init_all_ring(priv);
4037 ret = hns3_init_phy(netdev);
4041 ret = register_netdev(netdev);
4043 dev_err(priv->dev, "probe register netdev fail!\n");
4044 goto out_reg_netdev_fail;
4047 /* the device can work without cpu rmap, only aRFS needs it */
4048 ret = hns3_set_rx_cpu_rmap(netdev);
4050 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4052 ret = hns3_nic_init_irq(priv);
4054 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4055 hns3_free_rx_cpu_rmap(netdev);
4056 goto out_init_irq_fail;
4059 ret = hns3_client_start(handle);
4061 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4062 goto out_client_start;
4065 hns3_dcbnl_setup(handle);
4067 hns3_dbg_init(handle);
4069 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4070 netdev->max_mtu = HNS3_MAX_MTU;
4072 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4074 if (netif_msg_drv(handle))
4075 hns3_info_show(priv);
4080 hns3_free_rx_cpu_rmap(netdev);
4081 hns3_nic_uninit_irq(priv);
4083 unregister_netdev(netdev);
4084 out_reg_netdev_fail:
4085 hns3_uninit_phy(netdev);
4087 hns3_uninit_all_ring(priv);
4089 hns3_nic_uninit_vector_data(priv);
4090 out_init_vector_data:
4091 hns3_nic_dealloc_vector_data(priv);
4092 out_alloc_vector_data:
4095 priv->ae_handle = NULL;
4096 free_netdev(netdev);
4100 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4102 struct net_device *netdev = handle->kinfo.netdev;
4103 struct hns3_nic_priv *priv = netdev_priv(netdev);
4106 if (netdev->reg_state != NETREG_UNINITIALIZED)
4107 unregister_netdev(netdev);
4109 hns3_client_stop(handle);
4111 hns3_uninit_phy(netdev);
4113 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4114 netdev_warn(netdev, "already uninitialized\n");
4115 goto out_netdev_free;
4118 hns3_free_rx_cpu_rmap(netdev);
4120 hns3_nic_uninit_irq(priv);
4122 hns3_del_all_fd_rules(netdev, true);
4124 hns3_clear_all_ring(handle, true);
4126 hns3_nic_uninit_vector_data(priv);
4128 hns3_nic_dealloc_vector_data(priv);
4130 ret = hns3_uninit_all_ring(priv);
4132 netdev_err(netdev, "uninit ring error\n");
4134 hns3_put_ring_config(priv);
4136 hns3_dbg_uninit(handle);
4139 free_netdev(netdev);
4142 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4144 struct net_device *netdev = handle->kinfo.netdev;
4150 netif_carrier_on(netdev);
4151 netif_tx_wake_all_queues(netdev);
4152 if (netif_msg_link(handle))
4153 netdev_info(netdev, "link up\n");
4155 netif_carrier_off(netdev);
4156 netif_tx_stop_all_queues(netdev);
4157 if (netif_msg_link(handle))
4158 netdev_info(netdev, "link down\n");
4162 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4164 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4165 struct net_device *ndev = kinfo->netdev;
4167 if (tc > HNAE3_MAX_TC)
4173 return hns3_nic_set_real_num_queue(ndev);
4176 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
4178 while (ring->next_to_clean != ring->next_to_use) {
4179 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
4180 hns3_free_buffer_detach(ring, ring->next_to_clean);
4181 ring_ptr_move_fw(ring, next_to_clean);
4185 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4187 struct hns3_desc_cb res_cbs;
4190 while (ring->next_to_use != ring->next_to_clean) {
4191 /* When a buffer is not reused, it's memory has been
4192 * freed in hns3_handle_rx_bd or will be freed by
4193 * stack, so we need to replace the buffer here.
4195 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4196 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4198 u64_stats_update_begin(&ring->syncp);
4199 ring->stats.sw_err_cnt++;
4200 u64_stats_update_end(&ring->syncp);
4201 /* if alloc new buffer fail, exit directly
4202 * and reclear in up flow.
4204 netdev_warn(ring_to_netdev(ring),
4205 "reserve buffer map failed, ret = %d\n",
4209 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
4211 ring_ptr_move_fw(ring, next_to_use);
4214 /* Free the pending skb in rx ring */
4216 dev_kfree_skb_any(ring->skb);
4218 ring->pending_buf = 0;
4224 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
4226 while (ring->next_to_use != ring->next_to_clean) {
4227 /* When a buffer is not reused, it's memory has been
4228 * freed in hns3_handle_rx_bd or will be freed by
4229 * stack, so only need to unmap the buffer here.
4231 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4232 hns3_unmap_buffer(ring,
4233 &ring->desc_cb[ring->next_to_use]);
4234 ring->desc_cb[ring->next_to_use].dma = 0;
4237 ring_ptr_move_fw(ring, next_to_use);
4241 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
4243 struct net_device *ndev = h->kinfo.netdev;
4244 struct hns3_nic_priv *priv = netdev_priv(ndev);
4247 for (i = 0; i < h->kinfo.num_tqps; i++) {
4248 struct hns3_enet_ring *ring;
4250 ring = &priv->ring[i];
4251 hns3_clear_tx_ring(ring);
4253 ring = &priv->ring[i + h->kinfo.num_tqps];
4254 /* Continue to clear other rings even if clearing some
4258 hns3_force_clear_rx_ring(ring);
4260 hns3_clear_rx_ring(ring);
4264 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4266 struct net_device *ndev = h->kinfo.netdev;
4267 struct hns3_nic_priv *priv = netdev_priv(ndev);
4268 struct hns3_enet_ring *rx_ring;
4272 for (i = 0; i < h->kinfo.num_tqps; i++) {
4273 ret = h->ae_algo->ops->reset_queue(h, i);
4277 hns3_init_ring_hw(&priv->ring[i]);
4279 /* We need to clear tx ring here because self test will
4280 * use the ring and will not run down before up
4282 hns3_clear_tx_ring(&priv->ring[i]);
4283 priv->ring[i].next_to_clean = 0;
4284 priv->ring[i].next_to_use = 0;
4286 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
4287 hns3_init_ring_hw(rx_ring);
4288 ret = hns3_clear_rx_ring(rx_ring);
4292 /* We can not know the hardware head and tail when this
4293 * function is called in reset flow, so we reuse all desc.
4295 for (j = 0; j < rx_ring->desc_num; j++)
4296 hns3_reuse_buffer(rx_ring, j);
4298 rx_ring->next_to_clean = 0;
4299 rx_ring->next_to_use = 0;
4302 hns3_init_tx_ring_tc(priv);
4307 static void hns3_store_coal(struct hns3_nic_priv *priv)
4309 /* ethtool only support setting and querying one coal
4310 * configuration for now, so save the vector 0' coal
4311 * configuration here in order to restore it.
4313 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4314 sizeof(struct hns3_enet_coalesce));
4315 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4316 sizeof(struct hns3_enet_coalesce));
4319 static void hns3_restore_coal(struct hns3_nic_priv *priv)
4321 u16 vector_num = priv->vector_num;
4324 for (i = 0; i < vector_num; i++) {
4325 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4326 sizeof(struct hns3_enet_coalesce));
4327 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4328 sizeof(struct hns3_enet_coalesce));
4332 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4334 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4335 struct net_device *ndev = kinfo->netdev;
4336 struct hns3_nic_priv *priv = netdev_priv(ndev);
4338 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4341 if (!netif_running(ndev))
4344 return hns3_nic_net_stop(ndev);
4347 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4349 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4350 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4353 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4355 if (netif_running(kinfo->netdev)) {
4356 ret = hns3_nic_net_open(kinfo->netdev);
4358 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4359 netdev_err(kinfo->netdev,
4360 "net up fail, ret=%d!\n", ret);
4368 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4370 struct net_device *netdev = handle->kinfo.netdev;
4371 struct hns3_nic_priv *priv = netdev_priv(netdev);
4374 /* Carrier off reporting is important to ethtool even BEFORE open */
4375 netif_carrier_off(netdev);
4377 ret = hns3_get_ring_config(priv);
4381 ret = hns3_nic_alloc_vector_data(priv);
4385 hns3_restore_coal(priv);
4387 ret = hns3_nic_init_vector_data(priv);
4389 goto err_dealloc_vector;
4391 ret = hns3_init_all_ring(priv);
4393 goto err_uninit_vector;
4395 /* the device can work without cpu rmap, only aRFS needs it */
4396 ret = hns3_set_rx_cpu_rmap(netdev);
4398 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4400 ret = hns3_nic_init_irq(priv);
4402 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4403 hns3_free_rx_cpu_rmap(netdev);
4404 goto err_init_irq_fail;
4407 if (!hns3_is_phys_func(handle->pdev))
4408 hns3_init_mac_addr(netdev);
4410 ret = hns3_client_start(handle);
4412 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4413 goto err_client_start_fail;
4416 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4420 err_client_start_fail:
4421 hns3_free_rx_cpu_rmap(netdev);
4422 hns3_nic_uninit_irq(priv);
4424 hns3_uninit_all_ring(priv);
4426 hns3_nic_uninit_vector_data(priv);
4428 hns3_nic_dealloc_vector_data(priv);
4430 hns3_put_ring_config(priv);
4435 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4437 struct net_device *netdev = handle->kinfo.netdev;
4438 struct hns3_nic_priv *priv = netdev_priv(netdev);
4441 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4442 netdev_warn(netdev, "already uninitialized\n");
4446 hns3_free_rx_cpu_rmap(netdev);
4447 hns3_nic_uninit_irq(priv);
4448 hns3_clear_all_ring(handle, true);
4449 hns3_reset_tx_queue(priv->ae_handle);
4451 hns3_nic_uninit_vector_data(priv);
4453 hns3_store_coal(priv);
4455 hns3_nic_dealloc_vector_data(priv);
4457 ret = hns3_uninit_all_ring(priv);
4459 netdev_err(netdev, "uninit ring error\n");
4461 hns3_put_ring_config(priv);
4466 static int hns3_reset_notify(struct hnae3_handle *handle,
4467 enum hnae3_reset_notify_type type)
4472 case HNAE3_UP_CLIENT:
4473 ret = hns3_reset_notify_up_enet(handle);
4475 case HNAE3_DOWN_CLIENT:
4476 ret = hns3_reset_notify_down_enet(handle);
4478 case HNAE3_INIT_CLIENT:
4479 ret = hns3_reset_notify_init_enet(handle);
4481 case HNAE3_UNINIT_CLIENT:
4482 ret = hns3_reset_notify_uninit_enet(handle);
4491 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4492 bool rxfh_configured)
4496 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4499 dev_err(&handle->pdev->dev,
4500 "Change tqp num(%u) fail.\n", new_tqp_num);
4504 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4508 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4510 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4515 int hns3_set_channels(struct net_device *netdev,
4516 struct ethtool_channels *ch)
4518 struct hnae3_handle *h = hns3_get_handle(netdev);
4519 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4520 bool rxfh_configured = netif_is_rxfh_configured(netdev);
4521 u32 new_tqp_num = ch->combined_count;
4525 if (hns3_nic_resetting(netdev))
4528 if (ch->rx_count || ch->tx_count)
4531 if (new_tqp_num > hns3_get_max_available_channels(h) ||
4533 dev_err(&netdev->dev,
4534 "Change tqps fail, the tqp range is from 1 to %u",
4535 hns3_get_max_available_channels(h));
4539 if (kinfo->rss_size == new_tqp_num)
4542 netif_dbg(h, drv, netdev,
4543 "set channels: tqp_num=%u, rxfh=%d\n",
4544 new_tqp_num, rxfh_configured);
4546 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4550 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4554 org_tqp_num = h->kinfo.num_tqps;
4555 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
4560 "Change channels fail, revert to old value\n");
4561 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4564 "revert to old channel fail\n");
4574 static const struct hns3_hw_error_info hns3_hw_err[] = {
4575 { .type = HNAE3_PPU_POISON_ERROR,
4576 .msg = "PPU poison" },
4577 { .type = HNAE3_CMDQ_ECC_ERROR,
4578 .msg = "IMP CMDQ error" },
4579 { .type = HNAE3_IMP_RD_POISON_ERROR,
4580 .msg = "IMP RD poison" },
4583 static void hns3_process_hw_error(struct hnae3_handle *handle,
4584 enum hnae3_hw_error_type type)
4588 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4589 if (hns3_hw_err[i].type == type) {
4590 dev_err(&handle->pdev->dev, "Detected %s!\n",
4591 hns3_hw_err[i].msg);
4597 static const struct hnae3_client_ops client_ops = {
4598 .init_instance = hns3_client_init,
4599 .uninit_instance = hns3_client_uninit,
4600 .link_status_change = hns3_link_status_change,
4601 .setup_tc = hns3_client_setup_tc,
4602 .reset_notify = hns3_reset_notify,
4603 .process_hw_error = hns3_process_hw_error,
4606 /* hns3_init_module - Driver registration routine
4607 * hns3_init_module is the first routine called when the driver is
4608 * loaded. All it does is register with the PCI subsystem.
4610 static int __init hns3_init_module(void)
4614 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4615 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4617 client.type = HNAE3_CLIENT_KNIC;
4618 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
4621 client.ops = &client_ops;
4623 INIT_LIST_HEAD(&client.node);
4625 hns3_dbg_register_debugfs(hns3_driver_name);
4627 ret = hnae3_register_client(&client);
4629 goto err_reg_client;
4631 ret = pci_register_driver(&hns3_driver);
4633 goto err_reg_driver;
4638 hnae3_unregister_client(&client);
4640 hns3_dbg_unregister_debugfs();
4643 module_init(hns3_init_module);
4645 /* hns3_exit_module - Driver exit cleanup routine
4646 * hns3_exit_module is called just before the driver is removed
4649 static void __exit hns3_exit_module(void)
4651 pci_unregister_driver(&hns3_driver);
4652 hnae3_unregister_client(&client);
4653 hns3_dbg_unregister_debugfs();
4655 module_exit(hns3_exit_module);
4657 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4658 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4659 MODULE_LICENSE("GPL");
4660 MODULE_ALIAS("pci:hns-nic");