drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/dma-mapping.h>
   5 #include <linux/etherdevice.h>
   6 #include <linux/interrupt.h>
   7 #ifdef CONFIG_RFS_ACCEL
   8 #include <linux/cpu_rmap.h>
   9 #endif
  10 #include <linux/if_vlan.h>
  11 #include <linux/irq.h>
  12 #include <linux/ip.h>
  13 #include <linux/ipv6.h>
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/aer.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/sctp.h>
  19 #include <net/gre.h>
  20 #include <net/ip6_checksum.h>
  21 #include <net/pkt_cls.h>
  22 #include <net/tcp.h>
  23 #include <net/vxlan.h>
  24 #include <net/geneve.h>
  25
  26 #include "hnae3.h"
  27 #include "hns3_enet.h"
  28 /* All hns3 tracepoints are defined by the include below, which
  29  * must be included exactly once across the whole kernel with
  30  * CREATE_TRACE_POINTS defined
  31  */
  32 #define CREATE_TRACE_POINTS
  33 #include "hns3_trace.h"
  34
  35 #define hns3_set_field(origin, shift, val)      ((origin) |= (val) << (shift))
  36 #define hns3_tx_bd_count(S)     DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
  37
  38 #define hns3_rl_err(fmt, ...)                                           \
  39         do {                                                            \
  40                 if (net_ratelimit())                                    \
  41                         netdev_err(fmt, ##__VA_ARGS__);                 \
  42         } while (0)
  43
  44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
  45
  46 static const char hns3_driver_name[] = "hns3";
  47 static const char hns3_driver_string[] =
  48                         "Hisilicon Ethernet Network Driver for Hip08 Family";
  49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
  50 static struct hnae3_client client;
  51
  52 static int debug = -1;
  53 module_param(debug, int, 0);
  54 MODULE_PARM_DESC(debug, " Network interface message level setting");
  55
  56 static unsigned int tx_spare_buf_size;
  57 module_param(tx_spare_buf_size, uint, 0400);
  58 MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer");
  59
  60 static unsigned int tx_sgl = 1;
  61 module_param(tx_sgl, uint, 0600);
  62 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
  63
  64 #define HNS3_SGL_SIZE(nfrag)    (sizeof(struct scatterlist) * (nfrag) + \
  65                                  sizeof(struct sg_table))
  66 #define HNS3_MAX_SGL_SIZE       ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
  67                                       dma_get_cache_alignment())
  68
  69 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  70                            NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
  71
  72 #define HNS3_INNER_VLAN_TAG     1
  73 #define HNS3_OUTER_VLAN_TAG     2
  74
  75 #define HNS3_MIN_TX_LEN         33U
  76
  77 /* hns3_pci_tbl - PCI Device ID Table
  78  *
  79  * Last entry must be all 0s
  80  *
  81  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  82  *   Class, Class Mask, private data (not used) }
  83  */
  84 static const struct pci_device_id hns3_pci_tbl[] = {
  85         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  86         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  87         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
  88          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  89         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
  90          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  91         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
  92          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  93         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
  94          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  95         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
  96          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  97         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
  98          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  99         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
 100         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
 101          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
 102         /* required last entry */
 103         {0,}
 104 };
 105 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
 106
 107 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \
 108         {       ptype, \
 109                 l, \
 110                 CHECKSUM_##s, \
 111                 HNS3_L3_TYPE_##t, \
 112                 1 }
 113
 114 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
 115                 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 }
 116
 117 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
 118         HNS3_RX_PTYPE_UNUSED_ENTRY(0),
 119         HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP),
 120         HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP),
 121         HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP),
 122         HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL),
 123         HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL),
 124         HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL),
 125         HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM),
 126         HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL),
 127         HNS3_RX_PTYPE_UNUSED_ENTRY(9),
 128         HNS3_RX_PTYPE_UNUSED_ENTRY(10),
 129         HNS3_RX_PTYPE_UNUSED_ENTRY(11),
 130         HNS3_RX_PTYPE_UNUSED_ENTRY(12),
 131         HNS3_RX_PTYPE_UNUSED_ENTRY(13),
 132         HNS3_RX_PTYPE_UNUSED_ENTRY(14),
 133         HNS3_RX_PTYPE_UNUSED_ENTRY(15),
 134         HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL),
 135         HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4),
 136         HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4),
 137         HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4),
 138         HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4),
 139         HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4),
 140         HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4),
 141         HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4),
 142         HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4),
 143         HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4),
 144         HNS3_RX_PTYPE_UNUSED_ENTRY(26),
 145         HNS3_RX_PTYPE_UNUSED_ENTRY(27),
 146         HNS3_RX_PTYPE_UNUSED_ENTRY(28),
 147         HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL),
 148         HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL),
 149         HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4),
 150         HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4),
 151         HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4),
 152         HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4),
 153         HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4),
 154         HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4),
 155         HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4),
 156         HNS3_RX_PTYPE_UNUSED_ENTRY(38),
 157         HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6),
 158         HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6),
 159         HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6),
 160         HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6),
 161         HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6),
 162         HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6),
 163         HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6),
 164         HNS3_RX_PTYPE_UNUSED_ENTRY(46),
 165         HNS3_RX_PTYPE_UNUSED_ENTRY(47),
 166         HNS3_RX_PTYPE_UNUSED_ENTRY(48),
 167         HNS3_RX_PTYPE_UNUSED_ENTRY(49),
 168         HNS3_RX_PTYPE_UNUSED_ENTRY(50),
 169         HNS3_RX_PTYPE_UNUSED_ENTRY(51),
 170         HNS3_RX_PTYPE_UNUSED_ENTRY(52),
 171         HNS3_RX_PTYPE_UNUSED_ENTRY(53),
 172         HNS3_RX_PTYPE_UNUSED_ENTRY(54),
 173         HNS3_RX_PTYPE_UNUSED_ENTRY(55),
 174         HNS3_RX_PTYPE_UNUSED_ENTRY(56),
 175         HNS3_RX_PTYPE_UNUSED_ENTRY(57),
 176         HNS3_RX_PTYPE_UNUSED_ENTRY(58),
 177         HNS3_RX_PTYPE_UNUSED_ENTRY(59),
 178         HNS3_RX_PTYPE_UNUSED_ENTRY(60),
 179         HNS3_RX_PTYPE_UNUSED_ENTRY(61),
 180         HNS3_RX_PTYPE_UNUSED_ENTRY(62),
 181         HNS3_RX_PTYPE_UNUSED_ENTRY(63),
 182         HNS3_RX_PTYPE_UNUSED_ENTRY(64),
 183         HNS3_RX_PTYPE_UNUSED_ENTRY(65),
 184         HNS3_RX_PTYPE_UNUSED_ENTRY(66),
 185         HNS3_RX_PTYPE_UNUSED_ENTRY(67),
 186         HNS3_RX_PTYPE_UNUSED_ENTRY(68),
 187         HNS3_RX_PTYPE_UNUSED_ENTRY(69),
 188         HNS3_RX_PTYPE_UNUSED_ENTRY(70),
 189         HNS3_RX_PTYPE_UNUSED_ENTRY(71),
 190         HNS3_RX_PTYPE_UNUSED_ENTRY(72),
 191         HNS3_RX_PTYPE_UNUSED_ENTRY(73),
 192         HNS3_RX_PTYPE_UNUSED_ENTRY(74),
 193         HNS3_RX_PTYPE_UNUSED_ENTRY(75),
 194         HNS3_RX_PTYPE_UNUSED_ENTRY(76),
 195         HNS3_RX_PTYPE_UNUSED_ENTRY(77),
 196         HNS3_RX_PTYPE_UNUSED_ENTRY(78),
 197         HNS3_RX_PTYPE_UNUSED_ENTRY(79),
 198         HNS3_RX_PTYPE_UNUSED_ENTRY(80),
 199         HNS3_RX_PTYPE_UNUSED_ENTRY(81),
 200         HNS3_RX_PTYPE_UNUSED_ENTRY(82),
 201         HNS3_RX_PTYPE_UNUSED_ENTRY(83),
 202         HNS3_RX_PTYPE_UNUSED_ENTRY(84),
 203         HNS3_RX_PTYPE_UNUSED_ENTRY(85),
 204         HNS3_RX_PTYPE_UNUSED_ENTRY(86),
 205         HNS3_RX_PTYPE_UNUSED_ENTRY(87),
 206         HNS3_RX_PTYPE_UNUSED_ENTRY(88),
 207         HNS3_RX_PTYPE_UNUSED_ENTRY(89),
 208         HNS3_RX_PTYPE_UNUSED_ENTRY(90),
 209         HNS3_RX_PTYPE_UNUSED_ENTRY(91),
 210         HNS3_RX_PTYPE_UNUSED_ENTRY(92),
 211         HNS3_RX_PTYPE_UNUSED_ENTRY(93),
 212         HNS3_RX_PTYPE_UNUSED_ENTRY(94),
 213         HNS3_RX_PTYPE_UNUSED_ENTRY(95),
 214         HNS3_RX_PTYPE_UNUSED_ENTRY(96),
 215         HNS3_RX_PTYPE_UNUSED_ENTRY(97),
 216         HNS3_RX_PTYPE_UNUSED_ENTRY(98),
 217         HNS3_RX_PTYPE_UNUSED_ENTRY(99),
 218         HNS3_RX_PTYPE_UNUSED_ENTRY(100),
 219         HNS3_RX_PTYPE_UNUSED_ENTRY(101),
 220         HNS3_RX_PTYPE_UNUSED_ENTRY(102),
 221         HNS3_RX_PTYPE_UNUSED_ENTRY(103),
 222         HNS3_RX_PTYPE_UNUSED_ENTRY(104),
 223         HNS3_RX_PTYPE_UNUSED_ENTRY(105),
 224         HNS3_RX_PTYPE_UNUSED_ENTRY(106),
 225         HNS3_RX_PTYPE_UNUSED_ENTRY(107),
 226         HNS3_RX_PTYPE_UNUSED_ENTRY(108),
 227         HNS3_RX_PTYPE_UNUSED_ENTRY(109),
 228         HNS3_RX_PTYPE_UNUSED_ENTRY(110),
 229         HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6),
 230         HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6),
 231         HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6),
 232         HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6),
 233         HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6),
 234         HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6),
 235         HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6),
 236         HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6),
 237         HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6),
 238         HNS3_RX_PTYPE_UNUSED_ENTRY(120),
 239         HNS3_RX_PTYPE_UNUSED_ENTRY(121),
 240         HNS3_RX_PTYPE_UNUSED_ENTRY(122),
 241         HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL),
 242         HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL),
 243         HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4),
 244         HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4),
 245         HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4),
 246         HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4),
 247         HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4),
 248         HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4),
 249         HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4),
 250         HNS3_RX_PTYPE_UNUSED_ENTRY(132),
 251         HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6),
 252         HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6),
 253         HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6),
 254         HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6),
 255         HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6),
 256         HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6),
 257         HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6),
 258         HNS3_RX_PTYPE_UNUSED_ENTRY(140),
 259         HNS3_RX_PTYPE_UNUSED_ENTRY(141),
 260         HNS3_RX_PTYPE_UNUSED_ENTRY(142),
 261         HNS3_RX_PTYPE_UNUSED_ENTRY(143),
 262         HNS3_RX_PTYPE_UNUSED_ENTRY(144),
 263         HNS3_RX_PTYPE_UNUSED_ENTRY(145),
 264         HNS3_RX_PTYPE_UNUSED_ENTRY(146),
 265         HNS3_RX_PTYPE_UNUSED_ENTRY(147),
 266         HNS3_RX_PTYPE_UNUSED_ENTRY(148),
 267         HNS3_RX_PTYPE_UNUSED_ENTRY(149),
 268         HNS3_RX_PTYPE_UNUSED_ENTRY(150),
 269         HNS3_RX_PTYPE_UNUSED_ENTRY(151),
 270         HNS3_RX_PTYPE_UNUSED_ENTRY(152),
 271         HNS3_RX_PTYPE_UNUSED_ENTRY(153),
 272         HNS3_RX_PTYPE_UNUSED_ENTRY(154),
 273         HNS3_RX_PTYPE_UNUSED_ENTRY(155),
 274         HNS3_RX_PTYPE_UNUSED_ENTRY(156),
 275         HNS3_RX_PTYPE_UNUSED_ENTRY(157),
 276         HNS3_RX_PTYPE_UNUSED_ENTRY(158),
 277         HNS3_RX_PTYPE_UNUSED_ENTRY(159),
 278         HNS3_RX_PTYPE_UNUSED_ENTRY(160),
 279         HNS3_RX_PTYPE_UNUSED_ENTRY(161),
 280         HNS3_RX_PTYPE_UNUSED_ENTRY(162),
 281         HNS3_RX_PTYPE_UNUSED_ENTRY(163),
 282         HNS3_RX_PTYPE_UNUSED_ENTRY(164),
 283         HNS3_RX_PTYPE_UNUSED_ENTRY(165),
 284         HNS3_RX_PTYPE_UNUSED_ENTRY(166),
 285         HNS3_RX_PTYPE_UNUSED_ENTRY(167),
 286         HNS3_RX_PTYPE_UNUSED_ENTRY(168),
 287         HNS3_RX_PTYPE_UNUSED_ENTRY(169),
 288         HNS3_RX_PTYPE_UNUSED_ENTRY(170),
 289         HNS3_RX_PTYPE_UNUSED_ENTRY(171),
 290         HNS3_RX_PTYPE_UNUSED_ENTRY(172),
 291         HNS3_RX_PTYPE_UNUSED_ENTRY(173),
 292         HNS3_RX_PTYPE_UNUSED_ENTRY(174),
 293         HNS3_RX_PTYPE_UNUSED_ENTRY(175),
 294         HNS3_RX_PTYPE_UNUSED_ENTRY(176),
 295         HNS3_RX_PTYPE_UNUSED_ENTRY(177),
 296         HNS3_RX_PTYPE_UNUSED_ENTRY(178),
 297         HNS3_RX_PTYPE_UNUSED_ENTRY(179),
 298         HNS3_RX_PTYPE_UNUSED_ENTRY(180),
 299         HNS3_RX_PTYPE_UNUSED_ENTRY(181),
 300         HNS3_RX_PTYPE_UNUSED_ENTRY(182),
 301         HNS3_RX_PTYPE_UNUSED_ENTRY(183),
 302         HNS3_RX_PTYPE_UNUSED_ENTRY(184),
 303         HNS3_RX_PTYPE_UNUSED_ENTRY(185),
 304         HNS3_RX_PTYPE_UNUSED_ENTRY(186),
 305         HNS3_RX_PTYPE_UNUSED_ENTRY(187),
 306         HNS3_RX_PTYPE_UNUSED_ENTRY(188),
 307         HNS3_RX_PTYPE_UNUSED_ENTRY(189),
 308         HNS3_RX_PTYPE_UNUSED_ENTRY(190),
 309         HNS3_RX_PTYPE_UNUSED_ENTRY(191),
 310         HNS3_RX_PTYPE_UNUSED_ENTRY(192),
 311         HNS3_RX_PTYPE_UNUSED_ENTRY(193),
 312         HNS3_RX_PTYPE_UNUSED_ENTRY(194),
 313         HNS3_RX_PTYPE_UNUSED_ENTRY(195),
 314         HNS3_RX_PTYPE_UNUSED_ENTRY(196),
 315         HNS3_RX_PTYPE_UNUSED_ENTRY(197),
 316         HNS3_RX_PTYPE_UNUSED_ENTRY(198),
 317         HNS3_RX_PTYPE_UNUSED_ENTRY(199),
 318         HNS3_RX_PTYPE_UNUSED_ENTRY(200),
 319         HNS3_RX_PTYPE_UNUSED_ENTRY(201),
 320         HNS3_RX_PTYPE_UNUSED_ENTRY(202),
 321         HNS3_RX_PTYPE_UNUSED_ENTRY(203),
 322         HNS3_RX_PTYPE_UNUSED_ENTRY(204),
 323         HNS3_RX_PTYPE_UNUSED_ENTRY(205),
 324         HNS3_RX_PTYPE_UNUSED_ENTRY(206),
 325         HNS3_RX_PTYPE_UNUSED_ENTRY(207),
 326         HNS3_RX_PTYPE_UNUSED_ENTRY(208),
 327         HNS3_RX_PTYPE_UNUSED_ENTRY(209),
 328         HNS3_RX_PTYPE_UNUSED_ENTRY(210),
 329         HNS3_RX_PTYPE_UNUSED_ENTRY(211),
 330         HNS3_RX_PTYPE_UNUSED_ENTRY(212),
 331         HNS3_RX_PTYPE_UNUSED_ENTRY(213),
 332         HNS3_RX_PTYPE_UNUSED_ENTRY(214),
 333         HNS3_RX_PTYPE_UNUSED_ENTRY(215),
 334         HNS3_RX_PTYPE_UNUSED_ENTRY(216),
 335         HNS3_RX_PTYPE_UNUSED_ENTRY(217),
 336         HNS3_RX_PTYPE_UNUSED_ENTRY(218),
 337         HNS3_RX_PTYPE_UNUSED_ENTRY(219),
 338         HNS3_RX_PTYPE_UNUSED_ENTRY(220),
 339         HNS3_RX_PTYPE_UNUSED_ENTRY(221),
 340         HNS3_RX_PTYPE_UNUSED_ENTRY(222),
 341         HNS3_RX_PTYPE_UNUSED_ENTRY(223),
 342         HNS3_RX_PTYPE_UNUSED_ENTRY(224),
 343         HNS3_RX_PTYPE_UNUSED_ENTRY(225),
 344         HNS3_RX_PTYPE_UNUSED_ENTRY(226),
 345         HNS3_RX_PTYPE_UNUSED_ENTRY(227),
 346         HNS3_RX_PTYPE_UNUSED_ENTRY(228),
 347         HNS3_RX_PTYPE_UNUSED_ENTRY(229),
 348         HNS3_RX_PTYPE_UNUSED_ENTRY(230),
 349         HNS3_RX_PTYPE_UNUSED_ENTRY(231),
 350         HNS3_RX_PTYPE_UNUSED_ENTRY(232),
 351         HNS3_RX_PTYPE_UNUSED_ENTRY(233),
 352         HNS3_RX_PTYPE_UNUSED_ENTRY(234),
 353         HNS3_RX_PTYPE_UNUSED_ENTRY(235),
 354         HNS3_RX_PTYPE_UNUSED_ENTRY(236),
 355         HNS3_RX_PTYPE_UNUSED_ENTRY(237),
 356         HNS3_RX_PTYPE_UNUSED_ENTRY(238),
 357         HNS3_RX_PTYPE_UNUSED_ENTRY(239),
 358         HNS3_RX_PTYPE_UNUSED_ENTRY(240),
 359         HNS3_RX_PTYPE_UNUSED_ENTRY(241),
 360         HNS3_RX_PTYPE_UNUSED_ENTRY(242),
 361         HNS3_RX_PTYPE_UNUSED_ENTRY(243),
 362         HNS3_RX_PTYPE_UNUSED_ENTRY(244),
 363         HNS3_RX_PTYPE_UNUSED_ENTRY(245),
 364         HNS3_RX_PTYPE_UNUSED_ENTRY(246),
 365         HNS3_RX_PTYPE_UNUSED_ENTRY(247),
 366         HNS3_RX_PTYPE_UNUSED_ENTRY(248),
 367         HNS3_RX_PTYPE_UNUSED_ENTRY(249),
 368         HNS3_RX_PTYPE_UNUSED_ENTRY(250),
 369         HNS3_RX_PTYPE_UNUSED_ENTRY(251),
 370         HNS3_RX_PTYPE_UNUSED_ENTRY(252),
 371         HNS3_RX_PTYPE_UNUSED_ENTRY(253),
 372         HNS3_RX_PTYPE_UNUSED_ENTRY(254),
 373         HNS3_RX_PTYPE_UNUSED_ENTRY(255),
 374 };
 375
 376 #define HNS3_INVALID_PTYPE \
 377                 ARRAY_SIZE(hns3_rx_ptype_tbl)
 378
 379 static irqreturn_t hns3_irq_handle(int irq, void *vector)
 380 {
 381         struct hns3_enet_tqp_vector *tqp_vector = vector;
 382
 383         napi_schedule_irqoff(&tqp_vector->napi);
 384         tqp_vector->event_cnt++;
 385
 386         return IRQ_HANDLED;
 387 }
 388
 389 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
 390 {
 391         struct hns3_enet_tqp_vector *tqp_vectors;
 392         unsigned int i;
 393
 394         for (i = 0; i < priv->vector_num; i++) {
 395                 tqp_vectors = &priv->tqp_vector[i];
 396
 397                 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
 398                         continue;
 399
 400                 /* clear the affinity mask */
 401                 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
 402
 403                 /* release the irq resource */
 404                 free_irq(tqp_vectors->vector_irq, tqp_vectors);
 405                 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
 406         }
 407 }
 408
 409 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
 410 {
 411         struct hns3_enet_tqp_vector *tqp_vectors;
 412         int txrx_int_idx = 0;
 413         int rx_int_idx = 0;
 414         int tx_int_idx = 0;
 415         unsigned int i;
 416         int ret;
 417
 418         for (i = 0; i < priv->vector_num; i++) {
 419                 tqp_vectors = &priv->tqp_vector[i];
 420
 421                 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
 422                         continue;
 423
 424                 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
 425                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 426                                  "%s-%s-%s-%d", hns3_driver_name,
 427                                  pci_name(priv->ae_handle->pdev),
 428                                  "TxRx", txrx_int_idx++);
 429                         txrx_int_idx++;
 430                 } else if (tqp_vectors->rx_group.ring) {
 431                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 432                                  "%s-%s-%s-%d", hns3_driver_name,
 433                                  pci_name(priv->ae_handle->pdev),
 434                                  "Rx", rx_int_idx++);
 435                 } else if (tqp_vectors->tx_group.ring) {
 436                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 437                                  "%s-%s-%s-%d", hns3_driver_name,
 438                                  pci_name(priv->ae_handle->pdev),
 439                                  "Tx", tx_int_idx++);
 440                 } else {
 441                         /* Skip this unused q_vector */
 442                         continue;
 443                 }
 444
 445                 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
 446
 447                 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
 448                 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
 449                                   tqp_vectors->name, tqp_vectors);
 450                 if (ret) {
 451                         netdev_err(priv->netdev, "request irq(%d) fail\n",
 452                                    tqp_vectors->vector_irq);
 453                         hns3_nic_uninit_irq(priv);
 454                         return ret;
 455                 }
 456
 457                 irq_set_affinity_hint(tqp_vectors->vector_irq,
 458                                       &tqp_vectors->affinity_mask);
 459
 460                 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
 461         }
 462
 463         return 0;
 464 }
 465
 466 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
 467                                  u32 mask_en)
 468 {
 469         writel(mask_en, tqp_vector->mask_addr);
 470 }
 471
 472 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
 473 {
 474         napi_enable(&tqp_vector->napi);
 475         enable_irq(tqp_vector->vector_irq);
 476
 477         /* enable vector */
 478         hns3_mask_vector_irq(tqp_vector, 1);
 479 }
 480
 481 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
 482 {
 483         /* disable vector */
 484         hns3_mask_vector_irq(tqp_vector, 0);
 485
 486         disable_irq(tqp_vector->vector_irq);
 487         napi_disable(&tqp_vector->napi);
 488         cancel_work_sync(&tqp_vector->rx_group.dim.work);
 489         cancel_work_sync(&tqp_vector->tx_group.dim.work);
 490 }
 491
 492 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
 493                                  u32 rl_value)
 494 {
 495         u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
 496
 497         /* this defines the configuration for RL (Interrupt Rate Limiter).
 498          * Rl defines rate of interrupts i.e. number of interrupts-per-second
 499          * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
 500          */
 501         if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
 502             !tqp_vector->rx_group.coal.adapt_enable)
 503                 /* According to the hardware, the range of rl_reg is
 504                  * 0-59 and the unit is 4.
 505                  */
 506                 rl_reg |=  HNS3_INT_RL_ENABLE_MASK;
 507
 508         writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
 509 }
 510
 511 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
 512                                     u32 gl_value)
 513 {
 514         u32 new_val;
 515
 516         if (tqp_vector->rx_group.coal.unit_1us)
 517                 new_val = gl_value | HNS3_INT_GL_1US;
 518         else
 519                 new_val = hns3_gl_usec_to_reg(gl_value);
 520
 521         writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
 522 }
 523
 524 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
 525                                     u32 gl_value)
 526 {
 527         u32 new_val;
 528
 529         if (tqp_vector->tx_group.coal.unit_1us)
 530                 new_val = gl_value | HNS3_INT_GL_1US;
 531         else
 532                 new_val = hns3_gl_usec_to_reg(gl_value);
 533
 534         writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
 535 }
 536
 537 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
 538                                     u32 ql_value)
 539 {
 540         writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
 541 }
 542
 543 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
 544                                     u32 ql_value)
 545 {
 546         writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
 547 }
 548
 549 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
 550                                       struct hns3_nic_priv *priv)
 551 {
 552         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
 553         struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
 554         struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
 555         struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
 556         struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
 557
 558         tx_coal->adapt_enable = ptx_coal->adapt_enable;
 559         rx_coal->adapt_enable = prx_coal->adapt_enable;
 560
 561         tx_coal->int_gl = ptx_coal->int_gl;
 562         rx_coal->int_gl = prx_coal->int_gl;
 563
 564         rx_coal->flow_level = prx_coal->flow_level;
 565         tx_coal->flow_level = ptx_coal->flow_level;
 566
 567         /* device version above V3(include V3), GL can configure 1us
 568          * unit, so uses 1us unit.
 569          */
 570         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
 571                 tx_coal->unit_1us = 1;
 572                 rx_coal->unit_1us = 1;
 573         }
 574
 575         if (ae_dev->dev_specs.int_ql_max) {
 576                 tx_coal->ql_enable = 1;
 577                 rx_coal->ql_enable = 1;
 578                 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
 579                 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
 580                 tx_coal->int_ql = ptx_coal->int_ql;
 581                 rx_coal->int_ql = prx_coal->int_ql;
 582         }
 583 }
 584
 585 static void
 586 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
 587                              struct hns3_nic_priv *priv)
 588 {
 589         struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
 590         struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
 591         struct hnae3_handle *h = priv->ae_handle;
 592
 593         hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
 594         hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
 595         hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
 596
 597         if (tx_coal->ql_enable)
 598                 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
 599
 600         if (rx_coal->ql_enable)
 601                 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
 602 }
 603
 604 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
 605 {
 606         struct hnae3_handle *h = hns3_get_handle(netdev);
 607         struct hnae3_knic_private_info *kinfo = &h->kinfo;
 608         struct hnae3_tc_info *tc_info = &kinfo->tc_info;
 609         unsigned int queue_size = kinfo->num_tqps;
 610         int i, ret;
 611
 612         if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
 613                 netdev_reset_tc(netdev);
 614         } else {
 615                 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
 616                 if (ret) {
 617                         netdev_err(netdev,
 618                                    "netdev_set_num_tc fail, ret=%d!\n", ret);
 619                         return ret;
 620                 }
 621
 622                 for (i = 0; i < HNAE3_MAX_TC; i++) {
 623                         if (!test_bit(i, &tc_info->tc_en))
 624                                 continue;
 625
 626                         netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
 627                                             tc_info->tqp_offset[i]);
 628                 }
 629         }
 630
 631         ret = netif_set_real_num_tx_queues(netdev, queue_size);
 632         if (ret) {
 633                 netdev_err(netdev,
 634                            "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
 635                 return ret;
 636         }
 637
 638         ret = netif_set_real_num_rx_queues(netdev, queue_size);
 639         if (ret) {
 640                 netdev_err(netdev,
 641                            "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
 642                 return ret;
 643         }
 644
 645         return 0;
 646 }
 647
 648 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
 649 {
 650         u16 alloc_tqps, max_rss_size, rss_size;
 651
 652         h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
 653         rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
 654
 655         return min_t(u16, rss_size, max_rss_size);
 656 }
 657
 658 static void hns3_tqp_enable(struct hnae3_queue *tqp)
 659 {
 660         u32 rcb_reg;
 661
 662         rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
 663         rcb_reg |= BIT(HNS3_RING_EN_B);
 664         hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
 665 }
 666
 667 static void hns3_tqp_disable(struct hnae3_queue *tqp)
 668 {
 669         u32 rcb_reg;
 670
 671         rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
 672         rcb_reg &= ~BIT(HNS3_RING_EN_B);
 673         hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
 674 }
 675
 676 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
 677 {
 678 #ifdef CONFIG_RFS_ACCEL
 679         free_irq_cpu_rmap(netdev->rx_cpu_rmap);
 680         netdev->rx_cpu_rmap = NULL;
 681 #endif
 682 }
 683
 684 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
 685 {
 686 #ifdef CONFIG_RFS_ACCEL
 687         struct hns3_nic_priv *priv = netdev_priv(netdev);
 688         struct hns3_enet_tqp_vector *tqp_vector;
 689         int i, ret;
 690
 691         if (!netdev->rx_cpu_rmap) {
 692                 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
 693                 if (!netdev->rx_cpu_rmap)
 694                         return -ENOMEM;
 695         }
 696
 697         for (i = 0; i < priv->vector_num; i++) {
 698                 tqp_vector = &priv->tqp_vector[i];
 699                 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
 700                                        tqp_vector->vector_irq);
 701                 if (ret) {
 702                         hns3_free_rx_cpu_rmap(netdev);
 703                         return ret;
 704                 }
 705         }
 706 #endif
 707         return 0;
 708 }
 709
 710 static int hns3_nic_net_up(struct net_device *netdev)
 711 {
 712         struct hns3_nic_priv *priv = netdev_priv(netdev);
 713         struct hnae3_handle *h = priv->ae_handle;
 714         int i, j;
 715         int ret;
 716
 717         ret = hns3_nic_reset_all_ring(h);
 718         if (ret)
 719                 return ret;
 720
 721         clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
 722
 723         /* enable the vectors */
 724         for (i = 0; i < priv->vector_num; i++)
 725                 hns3_vector_enable(&priv->tqp_vector[i]);
 726
 727         /* enable rcb */
 728         for (j = 0; j < h->kinfo.num_tqps; j++)
 729                 hns3_tqp_enable(h->kinfo.tqp[j]);
 730
 731         /* start the ae_dev */
 732         ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
 733         if (ret) {
 734                 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
 735                 while (j--)
 736                         hns3_tqp_disable(h->kinfo.tqp[j]);
 737
 738                 for (j = i - 1; j >= 0; j--)
 739                         hns3_vector_disable(&priv->tqp_vector[j]);
 740         }
 741
 742         return ret;
 743 }
 744
 745 static void hns3_config_xps(struct hns3_nic_priv *priv)
 746 {
 747         int i;
 748
 749         for (i = 0; i < priv->vector_num; i++) {
 750                 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
 751                 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
 752
 753                 while (ring) {
 754                         int ret;
 755
 756                         ret = netif_set_xps_queue(priv->netdev,
 757                                                   &tqp_vector->affinity_mask,
 758                                                   ring->tqp->tqp_index);
 759                         if (ret)
 760                                 netdev_warn(priv->netdev,
 761                                             "set xps queue failed: %d", ret);
 762
 763                         ring = ring->next;
 764                 }
 765         }
 766 }
 767
 768 static int hns3_nic_net_open(struct net_device *netdev)
 769 {
 770         struct hns3_nic_priv *priv = netdev_priv(netdev);
 771         struct hnae3_handle *h = hns3_get_handle(netdev);
 772         struct hnae3_knic_private_info *kinfo;
 773         int i, ret;
 774
 775         if (hns3_nic_resetting(netdev))
 776                 return -EBUSY;
 777
 778         netif_carrier_off(netdev);
 779
 780         ret = hns3_nic_set_real_num_queue(netdev);
 781         if (ret)
 782                 return ret;
 783
 784         ret = hns3_nic_net_up(netdev);
 785         if (ret) {
 786                 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
 787                 return ret;
 788         }
 789
 790         kinfo = &h->kinfo;
 791         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
 792                 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
 793
 794         if (h->ae_algo->ops->set_timer_task)
 795                 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
 796
 797         hns3_config_xps(priv);
 798
 799         netif_dbg(h, drv, netdev, "net open\n");
 800
 801         return 0;
 802 }
 803
 804 static void hns3_reset_tx_queue(struct hnae3_handle *h)
 805 {
 806         struct net_device *ndev = h->kinfo.netdev;
 807         struct hns3_nic_priv *priv = netdev_priv(ndev);
 808         struct netdev_queue *dev_queue;
 809         u32 i;
 810
 811         for (i = 0; i < h->kinfo.num_tqps; i++) {
 812                 dev_queue = netdev_get_tx_queue(ndev,
 813                                                 priv->ring[i].queue_index);
 814                 netdev_tx_reset_queue(dev_queue);
 815         }
 816 }
 817
 818 static void hns3_nic_net_down(struct net_device *netdev)
 819 {
 820         struct hns3_nic_priv *priv = netdev_priv(netdev);
 821         struct hnae3_handle *h = hns3_get_handle(netdev);
 822         const struct hnae3_ae_ops *ops;
 823         int i;
 824
 825         /* disable vectors */
 826         for (i = 0; i < priv->vector_num; i++)
 827                 hns3_vector_disable(&priv->tqp_vector[i]);
 828
 829         /* disable rcb */
 830         for (i = 0; i < h->kinfo.num_tqps; i++)
 831                 hns3_tqp_disable(h->kinfo.tqp[i]);
 832
 833         /* stop ae_dev */
 834         ops = priv->ae_handle->ae_algo->ops;
 835         if (ops->stop)
 836                 ops->stop(priv->ae_handle);
 837
 838         /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
 839          * during reset process, because driver may not be able
 840          * to disable the ring through firmware when downing the netdev.
 841          */
 842         if (!hns3_nic_resetting(netdev))
 843                 hns3_clear_all_ring(priv->ae_handle, false);
 844
 845         hns3_reset_tx_queue(priv->ae_handle);
 846 }
 847
 848 static int hns3_nic_net_stop(struct net_device *netdev)
 849 {
 850         struct hns3_nic_priv *priv = netdev_priv(netdev);
 851         struct hnae3_handle *h = hns3_get_handle(netdev);
 852
 853         if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
 854                 return 0;
 855
 856         netif_dbg(h, drv, netdev, "net stop\n");
 857
 858         if (h->ae_algo->ops->set_timer_task)
 859                 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
 860
 861         netif_carrier_off(netdev);
 862         netif_tx_disable(netdev);
 863
 864         hns3_nic_net_down(netdev);
 865
 866         return 0;
 867 }
 868
 869 static int hns3_nic_uc_sync(struct net_device *netdev,
 870                             const unsigned char *addr)
 871 {
 872         struct hnae3_handle *h = hns3_get_handle(netdev);
 873
 874         if (h->ae_algo->ops->add_uc_addr)
 875                 return h->ae_algo->ops->add_uc_addr(h, addr);
 876
 877         return 0;
 878 }
 879
 880 static int hns3_nic_uc_unsync(struct net_device *netdev,
 881                               const unsigned char *addr)
 882 {
 883         struct hnae3_handle *h = hns3_get_handle(netdev);
 884
 885         /* need ignore the request of removing device address, because
 886          * we store the device address and other addresses of uc list
 887          * in the function's mac filter list.
 888          */
 889         if (ether_addr_equal(addr, netdev->dev_addr))
 890                 return 0;
 891
 892         if (h->ae_algo->ops->rm_uc_addr)
 893                 return h->ae_algo->ops->rm_uc_addr(h, addr);
 894
 895         return 0;
 896 }
 897
 898 static int hns3_nic_mc_sync(struct net_device *netdev,
 899                             const unsigned char *addr)
 900 {
 901         struct hnae3_handle *h = hns3_get_handle(netdev);
 902
 903         if (h->ae_algo->ops->add_mc_addr)
 904                 return h->ae_algo->ops->add_mc_addr(h, addr);
 905
 906         return 0;
 907 }
 908
 909 static int hns3_nic_mc_unsync(struct net_device *netdev,
 910                               const unsigned char *addr)
 911 {
 912         struct hnae3_handle *h = hns3_get_handle(netdev);
 913
 914         if (h->ae_algo->ops->rm_mc_addr)
 915                 return h->ae_algo->ops->rm_mc_addr(h, addr);
 916
 917         return 0;
 918 }
 919
 920 static u8 hns3_get_netdev_flags(struct net_device *netdev)
 921 {
 922         u8 flags = 0;
 923
 924         if (netdev->flags & IFF_PROMISC)
 925                 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
 926         else if (netdev->flags & IFF_ALLMULTI)
 927                 flags = HNAE3_USER_MPE;
 928
 929         return flags;
 930 }
 931
 932 static void hns3_nic_set_rx_mode(struct net_device *netdev)
 933 {
 934         struct hnae3_handle *h = hns3_get_handle(netdev);
 935         u8 new_flags;
 936
 937         new_flags = hns3_get_netdev_flags(netdev);
 938
 939         __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
 940         __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
 941
 942         /* User mode Promisc mode enable and vlan filtering is disabled to
 943          * let all packets in.
 944          */
 945         h->netdev_flags = new_flags;
 946         hns3_request_update_promisc_mode(h);
 947 }
 948
 949 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
 950 {
 951         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
 952
 953         if (ops->request_update_promisc_mode)
 954                 ops->request_update_promisc_mode(handle);
 955 }
 956
 957 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
 958 {
 959         struct hns3_tx_spare *tx_spare = ring->tx_spare;
 960         u32 ntc, ntu;
 961
 962         /* This smp_load_acquire() pairs with smp_store_release() in
 963          * hns3_tx_spare_update() called in tx desc cleaning process.
 964          */
 965         ntc = smp_load_acquire(&tx_spare->last_to_clean);
 966         ntu = tx_spare->next_to_use;
 967
 968         if (ntc > ntu)
 969                 return ntc - ntu - 1;
 970
 971         /* The free tx buffer is divided into two part, so pick the
 972          * larger one.
 973          */
 974         return max(ntc, tx_spare->len - ntu) - 1;
 975 }
 976
 977 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
 978 {
 979         struct hns3_tx_spare *tx_spare = ring->tx_spare;
 980
 981         if (!tx_spare ||
 982             tx_spare->last_to_clean == tx_spare->next_to_clean)
 983                 return;
 984
 985         /* This smp_store_release() pairs with smp_load_acquire() in
 986          * hns3_tx_spare_space() called in xmit process.
 987          */
 988         smp_store_release(&tx_spare->last_to_clean,
 989                           tx_spare->next_to_clean);
 990 }
 991
 992 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
 993                                    struct sk_buff *skb,
 994                                    u32 space)
 995 {
 996         u32 len = skb->len <= ring->tx_copybreak ? skb->len :
 997                                 skb_headlen(skb);
 998
 999         if (len > ring->tx_copybreak)
1000                 return false;
1001
1002         if (ALIGN(len, dma_get_cache_alignment()) > space) {
1003                 u64_stats_update_begin(&ring->syncp);
1004                 ring->stats.tx_spare_full++;
1005                 u64_stats_update_end(&ring->syncp);
1006                 return false;
1007         }
1008
1009         return true;
1010 }
1011
1012 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1013                                 struct sk_buff *skb,
1014                                 u32 space)
1015 {
1016         if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1017             (!skb_has_frag_list(skb) &&
1018              skb_shinfo(skb)->nr_frags < tx_sgl))
1019                 return false;
1020
1021         if (space < HNS3_MAX_SGL_SIZE) {
1022                 u64_stats_update_begin(&ring->syncp);
1023                 ring->stats.tx_spare_full++;
1024                 u64_stats_update_end(&ring->syncp);
1025                 return false;
1026         }
1027
1028         return true;
1029 }
1030
1031 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1032 {
1033         struct hns3_tx_spare *tx_spare;
1034         struct page *page;
1035         u32 alloc_size;
1036         dma_addr_t dma;
1037         int order;
1038
1039         alloc_size = tx_spare_buf_size ? tx_spare_buf_size :
1040                      ring->tqp->handle->kinfo.tx_spare_buf_size;
1041         if (!alloc_size)
1042                 return;
1043
1044         order = get_order(alloc_size);
1045         tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1046                                 GFP_KERNEL);
1047         if (!tx_spare) {
1048                 /* The driver still work without the tx spare buffer */
1049                 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1050                 return;
1051         }
1052
1053         page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1054                                 GFP_KERNEL, order);
1055         if (!page) {
1056                 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1057                 devm_kfree(ring_to_dev(ring), tx_spare);
1058                 return;
1059         }
1060
1061         dma = dma_map_page(ring_to_dev(ring), page, 0,
1062                            PAGE_SIZE << order, DMA_TO_DEVICE);
1063         if (dma_mapping_error(ring_to_dev(ring), dma)) {
1064                 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1065                 put_page(page);
1066                 devm_kfree(ring_to_dev(ring), tx_spare);
1067                 return;
1068         }
1069
1070         tx_spare->dma = dma;
1071         tx_spare->buf = page_address(page);
1072         tx_spare->len = PAGE_SIZE << order;
1073         ring->tx_spare = tx_spare;
1074 }
1075
1076 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1077  * before calling below function to allocate tx buffer.
1078  */
1079 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1080                                  unsigned int size, dma_addr_t *dma,
1081                                  u32 *cb_len)
1082 {
1083         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1084         u32 ntu = tx_spare->next_to_use;
1085
1086         size = ALIGN(size, dma_get_cache_alignment());
1087         *cb_len = size;
1088
1089         /* Tx spare buffer wraps back here because the end of
1090          * freed tx buffer is not enough.
1091          */
1092         if (ntu + size > tx_spare->len) {
1093                 *cb_len += (tx_spare->len - ntu);
1094                 ntu = 0;
1095         }
1096
1097         tx_spare->next_to_use = ntu + size;
1098         if (tx_spare->next_to_use == tx_spare->len)
1099                 tx_spare->next_to_use = 0;
1100
1101         *dma = tx_spare->dma + ntu;
1102
1103         return tx_spare->buf + ntu;
1104 }
1105
1106 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1107 {
1108         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1109
1110         if (len > tx_spare->next_to_use) {
1111                 len -= tx_spare->next_to_use;
1112                 tx_spare->next_to_use = tx_spare->len - len;
1113         } else {
1114                 tx_spare->next_to_use -= len;
1115         }
1116 }
1117
1118 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1119                                      struct hns3_desc_cb *cb)
1120 {
1121         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1122         u32 ntc = tx_spare->next_to_clean;
1123         u32 len = cb->length;
1124
1125         tx_spare->next_to_clean += len;
1126
1127         if (tx_spare->next_to_clean >= tx_spare->len) {
1128                 tx_spare->next_to_clean -= tx_spare->len;
1129
1130                 if (tx_spare->next_to_clean) {
1131                         ntc = 0;
1132                         len = tx_spare->next_to_clean;
1133                 }
1134         }
1135
1136         /* This tx spare buffer is only really reclaimed after calling
1137          * hns3_tx_spare_update(), so it is still safe to use the info in
1138          * the tx buffer to do the dma sync or sg unmapping after
1139          * tx_spare->next_to_clean is moved forword.
1140          */
1141         if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1142                 dma_addr_t dma = tx_spare->dma + ntc;
1143
1144                 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1145                                         DMA_TO_DEVICE);
1146         } else {
1147                 struct sg_table *sgt = tx_spare->buf + ntc;
1148
1149                 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1150                              DMA_TO_DEVICE);
1151         }
1152 }
1153
1154 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1155                         u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1156 {
1157         u32 l4_offset, hdr_len;
1158         union l3_hdr_info l3;
1159         union l4_hdr_info l4;
1160         u32 l4_paylen;
1161         int ret;
1162
1163         if (!skb_is_gso(skb))
1164                 return 0;
1165
1166         ret = skb_cow_head(skb, 0);
1167         if (unlikely(ret < 0))
1168                 return ret;
1169
1170         l3.hdr = skb_network_header(skb);
1171         l4.hdr = skb_transport_header(skb);
1172
1173         /* Software should clear the IPv4's checksum field when tso is
1174          * needed.
1175          */
1176         if (l3.v4->version == 4)
1177                 l3.v4->check = 0;
1178
1179         /* tunnel packet */
1180         if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1181                                          SKB_GSO_GRE_CSUM |
1182                                          SKB_GSO_UDP_TUNNEL |
1183                                          SKB_GSO_UDP_TUNNEL_CSUM)) {
1184                 /* reset l3&l4 pointers from outer to inner headers */
1185                 l3.hdr = skb_inner_network_header(skb);
1186                 l4.hdr = skb_inner_transport_header(skb);
1187
1188                 /* Software should clear the IPv4's checksum field when
1189                  * tso is needed.
1190                  */
1191                 if (l3.v4->version == 4)
1192                         l3.v4->check = 0;
1193         }
1194
1195         /* normal or tunnel packet */
1196         l4_offset = l4.hdr - skb->data;
1197
1198         /* remove payload length from inner pseudo checksum when tso */
1199         l4_paylen = skb->len - l4_offset;
1200
1201         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1202                 hdr_len = sizeof(*l4.udp) + l4_offset;
1203                 csum_replace_by_diff(&l4.udp->check,
1204                                      (__force __wsum)htonl(l4_paylen));
1205         } else {
1206                 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1207                 csum_replace_by_diff(&l4.tcp->check,
1208                                      (__force __wsum)htonl(l4_paylen));
1209         }
1210
1211         *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1212
1213         /* find the txbd field values */
1214         *paylen_fdop_ol4cs = skb->len - hdr_len;
1215         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1216
1217         /* offload outer UDP header checksum */
1218         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1219                 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1220
1221         /* get MSS for TSO */
1222         *mss = skb_shinfo(skb)->gso_size;
1223
1224         trace_hns3_tso(skb);
1225
1226         return 0;
1227 }
1228
1229 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1230                                 u8 *il4_proto)
1231 {
1232         union l3_hdr_info l3;
1233         unsigned char *l4_hdr;
1234         unsigned char *exthdr;
1235         u8 l4_proto_tmp;
1236         __be16 frag_off;
1237
1238         /* find outer header point */
1239         l3.hdr = skb_network_header(skb);
1240         l4_hdr = skb_transport_header(skb);
1241
1242         if (skb->protocol == htons(ETH_P_IPV6)) {
1243                 exthdr = l3.hdr + sizeof(*l3.v6);
1244                 l4_proto_tmp = l3.v6->nexthdr;
1245                 if (l4_hdr != exthdr)
1246                         ipv6_skip_exthdr(skb, exthdr - skb->data,
1247                                          &l4_proto_tmp, &frag_off);
1248         } else if (skb->protocol == htons(ETH_P_IP)) {
1249                 l4_proto_tmp = l3.v4->protocol;
1250         } else {
1251                 return -EINVAL;
1252         }
1253
1254         *ol4_proto = l4_proto_tmp;
1255
1256         /* tunnel packet */
1257         if (!skb->encapsulation) {
1258                 *il4_proto = 0;
1259                 return 0;
1260         }
1261
1262         /* find inner header point */
1263         l3.hdr = skb_inner_network_header(skb);
1264         l4_hdr = skb_inner_transport_header(skb);
1265
1266         if (l3.v6->version == 6) {
1267                 exthdr = l3.hdr + sizeof(*l3.v6);
1268                 l4_proto_tmp = l3.v6->nexthdr;
1269                 if (l4_hdr != exthdr)
1270                         ipv6_skip_exthdr(skb, exthdr - skb->data,
1271                                          &l4_proto_tmp, &frag_off);
1272         } else if (l3.v4->version == 4) {
1273                 l4_proto_tmp = l3.v4->protocol;
1274         }
1275
1276         *il4_proto = l4_proto_tmp;
1277
1278         return 0;
1279 }
1280
1281 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1282  * and it is udp packet, which has a dest port as the IANA assigned.
1283  * the hardware is expected to do the checksum offload, but the
1284  * hardware will not do the checksum offload when udp dest port is
1285  * 4789, 4790 or 6081.
1286  */
1287 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1288 {
1289         struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1290         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1291         union l4_hdr_info l4;
1292
1293         /* device version above V3(include V3), the hardware can
1294          * do this checksum offload.
1295          */
1296         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1297                 return false;
1298
1299         l4.hdr = skb_transport_header(skb);
1300
1301         if (!(!skb->encapsulation &&
1302               (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1303               l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1304               l4.udp->dest == htons(4790))))
1305                 return false;
1306
1307         return true;
1308 }
1309
1310 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1311                                   u32 *ol_type_vlan_len_msec)
1312 {
1313         u32 l2_len, l3_len, l4_len;
1314         unsigned char *il2_hdr;
1315         union l3_hdr_info l3;
1316         union l4_hdr_info l4;
1317
1318         l3.hdr = skb_network_header(skb);
1319         l4.hdr = skb_transport_header(skb);
1320
1321         /* compute OL2 header size, defined in 2 Bytes */
1322         l2_len = l3.hdr - skb->data;
1323         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1324
1325         /* compute OL3 header size, defined in 4 Bytes */
1326         l3_len = l4.hdr - l3.hdr;
1327         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1328
1329         il2_hdr = skb_inner_mac_header(skb);
1330         /* compute OL4 header size, defined in 4 Bytes */
1331         l4_len = il2_hdr - l4.hdr;
1332         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1333
1334         /* define outer network header type */
1335         if (skb->protocol == htons(ETH_P_IP)) {
1336                 if (skb_is_gso(skb))
1337                         hns3_set_field(*ol_type_vlan_len_msec,
1338                                        HNS3_TXD_OL3T_S,
1339                                        HNS3_OL3T_IPV4_CSUM);
1340                 else
1341                         hns3_set_field(*ol_type_vlan_len_msec,
1342                                        HNS3_TXD_OL3T_S,
1343                                        HNS3_OL3T_IPV4_NO_CSUM);
1344         } else if (skb->protocol == htons(ETH_P_IPV6)) {
1345                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1346                                HNS3_OL3T_IPV6);
1347         }
1348
1349         if (ol4_proto == IPPROTO_UDP)
1350                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1351                                HNS3_TUN_MAC_IN_UDP);
1352         else if (ol4_proto == IPPROTO_GRE)
1353                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1354                                HNS3_TUN_NVGRE);
1355 }
1356
1357 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1358                            u8 il4_proto, u32 *type_cs_vlan_tso,
1359                            u32 *ol_type_vlan_len_msec)
1360 {
1361         unsigned char *l2_hdr = skb->data;
1362         u32 l4_proto = ol4_proto;
1363         union l4_hdr_info l4;
1364         union l3_hdr_info l3;
1365         u32 l2_len, l3_len;
1366
1367         l4.hdr = skb_transport_header(skb);
1368         l3.hdr = skb_network_header(skb);
1369
1370         /* handle encapsulation skb */
1371         if (skb->encapsulation) {
1372                 /* If this is a not UDP/GRE encapsulation skb */
1373                 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1374                         /* drop the skb tunnel packet if hardware don't support,
1375                          * because hardware can't calculate csum when TSO.
1376                          */
1377                         if (skb_is_gso(skb))
1378                                 return -EDOM;
1379
1380                         /* the stack computes the IP header already,
1381                          * driver calculate l4 checksum when not TSO.
1382                          */
1383                         return skb_checksum_help(skb);
1384                 }
1385
1386                 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1387
1388                 /* switch to inner header */
1389                 l2_hdr = skb_inner_mac_header(skb);
1390                 l3.hdr = skb_inner_network_header(skb);
1391                 l4.hdr = skb_inner_transport_header(skb);
1392                 l4_proto = il4_proto;
1393         }
1394
1395         if (l3.v4->version == 4) {
1396                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1397                                HNS3_L3T_IPV4);
1398
1399                 /* the stack computes the IP header already, the only time we
1400                  * need the hardware to recompute it is in the case of TSO.
1401                  */
1402                 if (skb_is_gso(skb))
1403                         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1404         } else if (l3.v6->version == 6) {
1405                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1406                                HNS3_L3T_IPV6);
1407         }
1408
1409         /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1410         l2_len = l3.hdr - l2_hdr;
1411         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1412
1413         /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1414         l3_len = l4.hdr - l3.hdr;
1415         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1416
1417         /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1418         switch (l4_proto) {
1419         case IPPROTO_TCP:
1420                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1421                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1422                                HNS3_L4T_TCP);
1423                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1424                                l4.tcp->doff);
1425                 break;
1426         case IPPROTO_UDP:
1427                 if (hns3_tunnel_csum_bug(skb))
1428                         return skb_checksum_help(skb);
1429
1430                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1431                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1432                                HNS3_L4T_UDP);
1433                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1434                                (sizeof(struct udphdr) >> 2));
1435                 break;
1436         case IPPROTO_SCTP:
1437                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1438                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1439                                HNS3_L4T_SCTP);
1440                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1441                                (sizeof(struct sctphdr) >> 2));
1442                 break;
1443         default:
1444                 /* drop the skb tunnel packet if hardware don't support,
1445                  * because hardware can't calculate csum when TSO.
1446                  */
1447                 if (skb_is_gso(skb))
1448                         return -EDOM;
1449
1450                 /* the stack computes the IP header already,
1451                  * driver calculate l4 checksum when not TSO.
1452                  */
1453                 return skb_checksum_help(skb);
1454         }
1455
1456         return 0;
1457 }
1458
1459 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1460                              struct sk_buff *skb)
1461 {
1462         struct hnae3_handle *handle = tx_ring->tqp->handle;
1463         struct hnae3_ae_dev *ae_dev;
1464         struct vlan_ethhdr *vhdr;
1465         int rc;
1466
1467         if (!(skb->protocol == htons(ETH_P_8021Q) ||
1468               skb_vlan_tag_present(skb)))
1469                 return 0;
1470
1471         /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1472          * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1473          * will cause RAS error.
1474          */
1475         ae_dev = pci_get_drvdata(handle->pdev);
1476         if (unlikely(skb_vlan_tagged_multi(skb) &&
1477                      ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1478                      handle->port_base_vlan_state ==
1479                      HNAE3_PORT_BASE_VLAN_ENABLE))
1480                 return -EINVAL;
1481
1482         if (skb->protocol == htons(ETH_P_8021Q) &&
1483             !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1484                 /* When HW VLAN acceleration is turned off, and the stack
1485                  * sets the protocol to 802.1q, the driver just need to
1486                  * set the protocol to the encapsulated ethertype.
1487                  */
1488                 skb->protocol = vlan_get_protocol(skb);
1489                 return 0;
1490         }
1491
1492         if (skb_vlan_tag_present(skb)) {
1493                 /* Based on hw strategy, use out_vtag in two layer tag case,
1494                  * and use inner_vtag in one tag case.
1495                  */
1496                 if (skb->protocol == htons(ETH_P_8021Q) &&
1497                     handle->port_base_vlan_state ==
1498                     HNAE3_PORT_BASE_VLAN_DISABLE)
1499                         rc = HNS3_OUTER_VLAN_TAG;
1500                 else
1501                         rc = HNS3_INNER_VLAN_TAG;
1502
1503                 skb->protocol = vlan_get_protocol(skb);
1504                 return rc;
1505         }
1506
1507         rc = skb_cow_head(skb, 0);
1508         if (unlikely(rc < 0))
1509                 return rc;
1510
1511         vhdr = (struct vlan_ethhdr *)skb->data;
1512         vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1513                                          & VLAN_PRIO_MASK);
1514
1515         skb->protocol = vlan_get_protocol(skb);
1516         return 0;
1517 }
1518
1519 /* check if the hardware is capable of checksum offloading */
1520 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1521 {
1522         struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1523
1524         /* Kindly note, due to backward compatibility of the TX descriptor,
1525          * HW checksum of the non-IP packets and GSO packets is handled at
1526          * different place in the following code
1527          */
1528         if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1529             !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1530                 return false;
1531
1532         return true;
1533 }
1534
1535 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1536                               struct sk_buff *skb, struct hns3_desc *desc,
1537                               struct hns3_desc_cb *desc_cb)
1538 {
1539         u32 ol_type_vlan_len_msec = 0;
1540         u32 paylen_ol4cs = skb->len;
1541         u32 type_cs_vlan_tso = 0;
1542         u16 mss_hw_csum = 0;
1543         u16 inner_vtag = 0;
1544         u16 out_vtag = 0;
1545         int ret;
1546
1547         ret = hns3_handle_vtags(ring, skb);
1548         if (unlikely(ret < 0)) {
1549                 u64_stats_update_begin(&ring->syncp);
1550                 ring->stats.tx_vlan_err++;
1551                 u64_stats_update_end(&ring->syncp);
1552                 return ret;
1553         } else if (ret == HNS3_INNER_VLAN_TAG) {
1554                 inner_vtag = skb_vlan_tag_get(skb);
1555                 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1556                                 VLAN_PRIO_MASK;
1557                 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1558         } else if (ret == HNS3_OUTER_VLAN_TAG) {
1559                 out_vtag = skb_vlan_tag_get(skb);
1560                 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1561                                 VLAN_PRIO_MASK;
1562                 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1563                                1);
1564         }
1565
1566         desc_cb->send_bytes = skb->len;
1567
1568         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1569                 u8 ol4_proto, il4_proto;
1570
1571                 if (hns3_check_hw_tx_csum(skb)) {
1572                         /* set checksum start and offset, defined in 2 Bytes */
1573                         hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1574                                        skb_checksum_start_offset(skb) >> 1);
1575                         hns3_set_field(ol_type_vlan_len_msec,
1576                                        HNS3_TXD_CSUM_OFFSET_S,
1577                                        skb->csum_offset >> 1);
1578                         mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1579                         goto out_hw_tx_csum;
1580                 }
1581
1582                 skb_reset_mac_len(skb);
1583
1584                 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1585                 if (unlikely(ret < 0)) {
1586                         u64_stats_update_begin(&ring->syncp);
1587                         ring->stats.tx_l4_proto_err++;
1588                         u64_stats_update_end(&ring->syncp);
1589                         return ret;
1590                 }
1591
1592                 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1593                                       &type_cs_vlan_tso,
1594                                       &ol_type_vlan_len_msec);
1595                 if (unlikely(ret < 0)) {
1596                         u64_stats_update_begin(&ring->syncp);
1597                         ring->stats.tx_l2l3l4_err++;
1598                         u64_stats_update_end(&ring->syncp);
1599                         return ret;
1600                 }
1601
1602                 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum,
1603                                    &type_cs_vlan_tso, &desc_cb->send_bytes);
1604                 if (unlikely(ret < 0)) {
1605                         u64_stats_update_begin(&ring->syncp);
1606                         ring->stats.tx_tso_err++;
1607                         u64_stats_update_end(&ring->syncp);
1608                         return ret;
1609                 }
1610         }
1611
1612 out_hw_tx_csum:
1613         /* Set txbd */
1614         desc->tx.ol_type_vlan_len_msec =
1615                 cpu_to_le32(ol_type_vlan_len_msec);
1616         desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1617         desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs);
1618         desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum);
1619         desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1620         desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1621
1622         return 0;
1623 }
1624
1625 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1626                           unsigned int size)
1627 {
1628 #define HNS3_LIKELY_BD_NUM      1
1629
1630         struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1631         unsigned int frag_buf_num;
1632         int k, sizeoflast;
1633
1634         if (likely(size <= HNS3_MAX_BD_SIZE)) {
1635                 desc->addr = cpu_to_le64(dma);
1636                 desc->tx.send_size = cpu_to_le16(size);
1637                 desc->tx.bdtp_fe_sc_vld_ra_ri =
1638                         cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1639
1640                 trace_hns3_tx_desc(ring, ring->next_to_use);
1641                 ring_ptr_move_fw(ring, next_to_use);
1642                 return HNS3_LIKELY_BD_NUM;
1643         }
1644
1645         frag_buf_num = hns3_tx_bd_count(size);
1646         sizeoflast = size % HNS3_MAX_BD_SIZE;
1647         sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1648
1649         /* When frag size is bigger than hardware limit, split this frag */
1650         for (k = 0; k < frag_buf_num; k++) {
1651                 /* now, fill the descriptor */
1652                 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1653                 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1654                                      (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1655                 desc->tx.bdtp_fe_sc_vld_ra_ri =
1656                                 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1657
1658                 trace_hns3_tx_desc(ring, ring->next_to_use);
1659                 /* move ring pointer to next */
1660                 ring_ptr_move_fw(ring, next_to_use);
1661
1662                 desc = &ring->desc[ring->next_to_use];
1663         }
1664
1665         return frag_buf_num;
1666 }
1667
1668 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1669                                   unsigned int type)
1670 {
1671         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1672         struct device *dev = ring_to_dev(ring);
1673         unsigned int size;
1674         dma_addr_t dma;
1675
1676         if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1677                 struct sk_buff *skb = (struct sk_buff *)priv;
1678
1679                 size = skb_headlen(skb);
1680                 if (!size)
1681                         return 0;
1682
1683                 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1684         } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1685                 /* Head data has been filled in hns3_handle_tx_bounce(),
1686                  * just return 0 here.
1687                  */
1688                 return 0;
1689         } else {
1690                 skb_frag_t *frag = (skb_frag_t *)priv;
1691
1692                 size = skb_frag_size(frag);
1693                 if (!size)
1694                         return 0;
1695
1696                 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1697         }
1698
1699         if (unlikely(dma_mapping_error(dev, dma))) {
1700                 u64_stats_update_begin(&ring->syncp);
1701                 ring->stats.sw_err_cnt++;
1702                 u64_stats_update_end(&ring->syncp);
1703                 return -ENOMEM;
1704         }
1705
1706         desc_cb->priv = priv;
1707         desc_cb->length = size;
1708         desc_cb->dma = dma;
1709         desc_cb->type = type;
1710
1711         return hns3_fill_desc(ring, dma, size);
1712 }
1713
1714 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1715                                     unsigned int bd_num)
1716 {
1717         unsigned int size;
1718         int i;
1719
1720         size = skb_headlen(skb);
1721         while (size > HNS3_MAX_BD_SIZE) {
1722                 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1723                 size -= HNS3_MAX_BD_SIZE;
1724
1725                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1726                         return bd_num;
1727         }
1728
1729         if (size) {
1730                 bd_size[bd_num++] = size;
1731                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1732                         return bd_num;
1733         }
1734
1735         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1736                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1737                 size = skb_frag_size(frag);
1738                 if (!size)
1739                         continue;
1740
1741                 while (size > HNS3_MAX_BD_SIZE) {
1742                         bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1743                         size -= HNS3_MAX_BD_SIZE;
1744
1745                         if (bd_num > HNS3_MAX_TSO_BD_NUM)
1746                                 return bd_num;
1747                 }
1748
1749                 bd_size[bd_num++] = size;
1750                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1751                         return bd_num;
1752         }
1753
1754         return bd_num;
1755 }
1756
1757 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1758                                    u8 max_non_tso_bd_num, unsigned int bd_num,
1759                                    unsigned int recursion_level)
1760 {
1761 #define HNS3_MAX_RECURSION_LEVEL        24
1762
1763         struct sk_buff *frag_skb;
1764
1765         /* If the total len is within the max bd limit */
1766         if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1767                    !skb_has_frag_list(skb) &&
1768                    skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1769                 return skb_shinfo(skb)->nr_frags + 1U;
1770
1771         if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1772                 return UINT_MAX;
1773
1774         bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1775         if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1776                 return bd_num;
1777
1778         skb_walk_frags(skb, frag_skb) {
1779                 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1780                                         bd_num, recursion_level + 1);
1781                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1782                         return bd_num;
1783         }
1784
1785         return bd_num;
1786 }
1787
1788 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1789 {
1790         if (!skb->encapsulation)
1791                 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1792
1793         return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1794 }
1795
1796 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1797  * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1798  * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1799  * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1800  * than MSS except the last max_non_tso_bd_num - 1 frags.
1801  */
1802 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1803                                      unsigned int bd_num, u8 max_non_tso_bd_num)
1804 {
1805         unsigned int tot_len = 0;
1806         int i;
1807
1808         for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1809                 tot_len += bd_size[i];
1810
1811         /* ensure the first max_non_tso_bd_num frags is greater than
1812          * mss + header
1813          */
1814         if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1815             skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1816                 return true;
1817
1818         /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1819          * than mss except the last one.
1820          */
1821         for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1822                 tot_len -= bd_size[i];
1823                 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1824
1825                 if (tot_len < skb_shinfo(skb)->gso_size)
1826                         return true;
1827         }
1828
1829         return false;
1830 }
1831
1832 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1833 {
1834         int i;
1835
1836         for (i = 0; i < MAX_SKB_FRAGS; i++)
1837                 size[i] = skb_frag_size(&shinfo->frags[i]);
1838 }
1839
1840 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1841                               struct sk_buff *skb,
1842                               u8 max_non_tso_bd_num,
1843                               unsigned int bd_num)
1844 {
1845         /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1846          * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1847          */
1848         if (bd_num == UINT_MAX) {
1849                 u64_stats_update_begin(&ring->syncp);
1850                 ring->stats.over_max_recursion++;
1851                 u64_stats_update_end(&ring->syncp);
1852                 return -ENOMEM;
1853         }
1854
1855         /* The skb->len has exceeded the hw limitation, linearization
1856          * will not help.
1857          */
1858         if (skb->len > HNS3_MAX_TSO_SIZE ||
1859             (!skb_is_gso(skb) && skb->len >
1860              HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) {
1861                 u64_stats_update_begin(&ring->syncp);
1862                 ring->stats.hw_limitation++;
1863                 u64_stats_update_end(&ring->syncp);
1864                 return -ENOMEM;
1865         }
1866
1867         if (__skb_linearize(skb)) {
1868                 u64_stats_update_begin(&ring->syncp);
1869                 ring->stats.sw_err_cnt++;
1870                 u64_stats_update_end(&ring->syncp);
1871                 return -ENOMEM;
1872         }
1873
1874         return 0;
1875 }
1876
1877 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1878                                   struct net_device *netdev,
1879                                   struct sk_buff *skb)
1880 {
1881         struct hns3_nic_priv *priv = netdev_priv(netdev);
1882         u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1883         unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1884         unsigned int bd_num;
1885
1886         bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1887         if (unlikely(bd_num > max_non_tso_bd_num)) {
1888                 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1889                     !hns3_skb_need_linearized(skb, bd_size, bd_num,
1890                                               max_non_tso_bd_num)) {
1891                         trace_hns3_over_max_bd(skb);
1892                         goto out;
1893                 }
1894
1895                 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num,
1896                                        bd_num))
1897                         return -ENOMEM;
1898
1899                 bd_num = hns3_tx_bd_count(skb->len);
1900
1901                 u64_stats_update_begin(&ring->syncp);
1902                 ring->stats.tx_copy++;
1903                 u64_stats_update_end(&ring->syncp);
1904         }
1905
1906 out:
1907         if (likely(ring_space(ring) >= bd_num))
1908                 return bd_num;
1909
1910         netif_stop_subqueue(netdev, ring->queue_index);
1911         smp_mb(); /* Memory barrier before checking ring_space */
1912
1913         /* Start queue in case hns3_clean_tx_ring has just made room
1914          * available and has not seen the queue stopped state performed
1915          * by netif_stop_subqueue above.
1916          */
1917         if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1918             !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1919                 netif_start_subqueue(netdev, ring->queue_index);
1920                 return bd_num;
1921         }
1922
1923         u64_stats_update_begin(&ring->syncp);
1924         ring->stats.tx_busy++;
1925         u64_stats_update_end(&ring->syncp);
1926
1927         return -EBUSY;
1928 }
1929
1930 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1931 {
1932         struct device *dev = ring_to_dev(ring);
1933         unsigned int i;
1934
1935         for (i = 0; i < ring->desc_num; i++) {
1936                 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1937                 struct hns3_desc_cb *desc_cb;
1938
1939                 memset(desc, 0, sizeof(*desc));
1940
1941                 /* check if this is where we started */
1942                 if (ring->next_to_use == next_to_use_orig)
1943                         break;
1944
1945                 /* rollback one */
1946                 ring_ptr_move_bw(ring, next_to_use);
1947
1948                 desc_cb = &ring->desc_cb[ring->next_to_use];
1949
1950                 if (!desc_cb->dma)
1951                         continue;
1952
1953                 /* unmap the descriptor dma address */
1954                 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
1955                         dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
1956                                          DMA_TO_DEVICE);
1957                 else if (desc_cb->type &
1958                          (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
1959                         hns3_tx_spare_rollback(ring, desc_cb->length);
1960                 else if (desc_cb->length)
1961                         dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
1962                                        DMA_TO_DEVICE);
1963
1964                 desc_cb->length = 0;
1965                 desc_cb->dma = 0;
1966                 desc_cb->type = DESC_TYPE_UNKNOWN;
1967         }
1968 }
1969
1970 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1971                                  struct sk_buff *skb, unsigned int type)
1972 {
1973         struct sk_buff *frag_skb;
1974         int i, ret, bd_num = 0;
1975
1976         ret = hns3_map_and_fill_desc(ring, skb, type);
1977         if (unlikely(ret < 0))
1978                 return ret;
1979
1980         bd_num += ret;
1981
1982         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1983                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1984
1985                 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
1986                 if (unlikely(ret < 0))
1987                         return ret;
1988
1989                 bd_num += ret;
1990         }
1991
1992         skb_walk_frags(skb, frag_skb) {
1993                 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1994                                             DESC_TYPE_FRAGLIST_SKB);
1995                 if (unlikely(ret < 0))
1996                         return ret;
1997
1998                 bd_num += ret;
1999         }
2000
2001         return bd_num;
2002 }
2003
2004 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2005                              bool doorbell)
2006 {
2007         ring->pending_buf += num;
2008
2009         if (!doorbell) {
2010                 u64_stats_update_begin(&ring->syncp);
2011                 ring->stats.tx_more++;
2012                 u64_stats_update_end(&ring->syncp);
2013                 return;
2014         }
2015
2016         if (!ring->pending_buf)
2017                 return;
2018
2019         writel(ring->pending_buf,
2020                ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2021         ring->pending_buf = 0;
2022         WRITE_ONCE(ring->last_to_use, ring->next_to_use);
2023 }
2024
2025 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2026                       struct hns3_desc *desc)
2027 {
2028         struct hnae3_handle *h = hns3_get_handle(netdev);
2029
2030         if (!(h->ae_algo->ops->set_tx_hwts_info &&
2031               h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2032                 return;
2033
2034         desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2035 }
2036
2037 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2038                                  struct sk_buff *skb)
2039 {
2040         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2041         unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2042         unsigned int size = skb_headlen(skb);
2043         dma_addr_t dma;
2044         int bd_num = 0;
2045         u32 cb_len;
2046         void *buf;
2047         int ret;
2048
2049         if (skb->len <= ring->tx_copybreak) {
2050                 size = skb->len;
2051                 type = DESC_TYPE_BOUNCE_ALL;
2052         }
2053
2054         /* hns3_can_use_tx_bounce() is called to ensure the below
2055          * function can always return the tx buffer.
2056          */
2057         buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2058
2059         ret = skb_copy_bits(skb, 0, buf, size);
2060         if (unlikely(ret < 0)) {
2061                 hns3_tx_spare_rollback(ring, cb_len);
2062                 u64_stats_update_begin(&ring->syncp);
2063                 ring->stats.copy_bits_err++;
2064                 u64_stats_update_end(&ring->syncp);
2065                 return ret;
2066         }
2067
2068         desc_cb->priv = skb;
2069         desc_cb->length = cb_len;
2070         desc_cb->dma = dma;
2071         desc_cb->type = type;
2072
2073         bd_num += hns3_fill_desc(ring, dma, size);
2074
2075         if (type == DESC_TYPE_BOUNCE_HEAD) {
2076                 ret = hns3_fill_skb_to_desc(ring, skb,
2077                                             DESC_TYPE_BOUNCE_HEAD);
2078                 if (unlikely(ret < 0))
2079                         return ret;
2080
2081                 bd_num += ret;
2082         }
2083
2084         dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2085                                    DMA_TO_DEVICE);
2086
2087         u64_stats_update_begin(&ring->syncp);
2088         ring->stats.tx_bounce++;
2089         u64_stats_update_end(&ring->syncp);
2090         return bd_num;
2091 }
2092
2093 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2094                               struct sk_buff *skb)
2095 {
2096         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2097         u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2098         struct sg_table *sgt;
2099         int i, bd_num = 0;
2100         dma_addr_t dma;
2101         u32 cb_len;
2102         int nents;
2103
2104         if (skb_has_frag_list(skb))
2105                 nfrag = HNS3_MAX_TSO_BD_NUM;
2106
2107         /* hns3_can_use_tx_sgl() is called to ensure the below
2108          * function can always return the tx buffer.
2109          */
2110         sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2111                                   &dma, &cb_len);
2112
2113         /* scatterlist follows by the sg table */
2114         sgt->sgl = (struct scatterlist *)(sgt + 1);
2115         sg_init_table(sgt->sgl, nfrag);
2116         nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2117         if (unlikely(nents < 0)) {
2118                 hns3_tx_spare_rollback(ring, cb_len);
2119                 u64_stats_update_begin(&ring->syncp);
2120                 ring->stats.skb2sgl_err++;
2121                 u64_stats_update_end(&ring->syncp);
2122                 return -ENOMEM;
2123         }
2124
2125         sgt->orig_nents = nents;
2126         sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2127                                 DMA_TO_DEVICE);
2128         if (unlikely(!sgt->nents)) {
2129                 hns3_tx_spare_rollback(ring, cb_len);
2130                 u64_stats_update_begin(&ring->syncp);
2131                 ring->stats.map_sg_err++;
2132                 u64_stats_update_end(&ring->syncp);
2133                 return -ENOMEM;
2134         }
2135
2136         desc_cb->priv = skb;
2137         desc_cb->length = cb_len;
2138         desc_cb->dma = dma;
2139         desc_cb->type = DESC_TYPE_SGL_SKB;
2140
2141         for (i = 0; i < sgt->nents; i++)
2142                 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2143                                          sg_dma_len(sgt->sgl + i));
2144
2145         u64_stats_update_begin(&ring->syncp);
2146         ring->stats.tx_sgl++;
2147         u64_stats_update_end(&ring->syncp);
2148
2149         return bd_num;
2150 }
2151
2152 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2153                                     struct sk_buff *skb)
2154 {
2155         u32 space;
2156
2157         if (!ring->tx_spare)
2158                 goto out;
2159
2160         space = hns3_tx_spare_space(ring);
2161
2162         if (hns3_can_use_tx_sgl(ring, skb, space))
2163                 return hns3_handle_tx_sgl(ring, skb);
2164
2165         if (hns3_can_use_tx_bounce(ring, skb, space))
2166                 return hns3_handle_tx_bounce(ring, skb);
2167
2168 out:
2169         return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2170 }
2171
2172 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2173 {
2174         struct hns3_nic_priv *priv = netdev_priv(netdev);
2175         struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2176         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2177         struct netdev_queue *dev_queue;
2178         int pre_ntu, next_to_use_head;
2179         bool doorbell;
2180         int ret;
2181
2182         /* Hardware can only handle short frames above 32 bytes */
2183         if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2184                 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2185
2186                 u64_stats_update_begin(&ring->syncp);
2187                 ring->stats.sw_err_cnt++;
2188                 u64_stats_update_end(&ring->syncp);
2189
2190                 return NETDEV_TX_OK;
2191         }
2192
2193         /* Prefetch the data used later */
2194         prefetch(skb->data);
2195
2196         ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2197         if (unlikely(ret <= 0)) {
2198                 if (ret == -EBUSY) {
2199                         hns3_tx_doorbell(ring, 0, true);
2200                         return NETDEV_TX_BUSY;
2201                 }
2202
2203                 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2204                 goto out_err_tx_ok;
2205         }
2206
2207         next_to_use_head = ring->next_to_use;
2208
2209         ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2210                                  desc_cb);
2211         if (unlikely(ret < 0))
2212                 goto fill_err;
2213
2214         /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2215          * zero, which is unlikely, and 'ret > 0' means how many tx desc
2216          * need to be notified to the hw.
2217          */
2218         ret = hns3_handle_desc_filling(ring, skb);
2219         if (unlikely(ret <= 0))
2220                 goto fill_err;
2221
2222         pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2223                                         (ring->desc_num - 1);
2224
2225         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2226                 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2227
2228         ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2229                                 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2230         trace_hns3_tx_desc(ring, pre_ntu);
2231
2232         skb_tx_timestamp(skb);
2233
2234         /* Complete translate all packets */
2235         dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2236         doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2237                                           netdev_xmit_more());
2238         hns3_tx_doorbell(ring, ret, doorbell);
2239
2240         return NETDEV_TX_OK;
2241
2242 fill_err:
2243         hns3_clear_desc(ring, next_to_use_head);
2244
2245 out_err_tx_ok:
2246         dev_kfree_skb_any(skb);
2247         hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2248         return NETDEV_TX_OK;
2249 }
2250
2251 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2252 {
2253         struct hnae3_handle *h = hns3_get_handle(netdev);
2254         struct sockaddr *mac_addr = p;
2255         int ret;
2256
2257         if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2258                 return -EADDRNOTAVAIL;
2259
2260         if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2261                 netdev_info(netdev, "already using mac address %pM\n",
2262                             mac_addr->sa_data);
2263                 return 0;
2264         }
2265
2266         /* For VF device, if there is a perm_addr, then the user will not
2267          * be allowed to change the address.
2268          */
2269         if (!hns3_is_phys_func(h->pdev) &&
2270             !is_zero_ether_addr(netdev->perm_addr)) {
2271                 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
2272                            netdev->perm_addr, mac_addr->sa_data);
2273                 return -EPERM;
2274         }
2275
2276         ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2277         if (ret) {
2278                 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2279                 return ret;
2280         }
2281
2282         ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
2283
2284         return 0;
2285 }
2286
2287 static int hns3_nic_do_ioctl(struct net_device *netdev,
2288                              struct ifreq *ifr, int cmd)
2289 {
2290         struct hnae3_handle *h = hns3_get_handle(netdev);
2291
2292         if (!netif_running(netdev))
2293                 return -EINVAL;
2294
2295         if (!h->ae_algo->ops->do_ioctl)
2296                 return -EOPNOTSUPP;
2297
2298         return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2299 }
2300
2301 static int hns3_nic_set_features(struct net_device *netdev,
2302                                  netdev_features_t features)
2303 {
2304         netdev_features_t changed = netdev->features ^ features;
2305         struct hns3_nic_priv *priv = netdev_priv(netdev);
2306         struct hnae3_handle *h = priv->ae_handle;
2307         bool enable;
2308         int ret;
2309
2310         if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2311                 enable = !!(features & NETIF_F_GRO_HW);
2312                 ret = h->ae_algo->ops->set_gro_en(h, enable);
2313                 if (ret)
2314                         return ret;
2315         }
2316
2317         if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2318             h->ae_algo->ops->enable_hw_strip_rxvtag) {
2319                 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2320                 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2321                 if (ret)
2322                         return ret;
2323         }
2324
2325         if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2326                 enable = !!(features & NETIF_F_NTUPLE);
2327                 h->ae_algo->ops->enable_fd(h, enable);
2328         }
2329
2330         if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2331             h->ae_algo->ops->cls_flower_active(h)) {
2332                 netdev_err(netdev,
2333                            "there are offloaded TC filters active, cannot disable HW TC offload");
2334                 return -EINVAL;
2335         }
2336
2337         if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2338             h->ae_algo->ops->enable_vlan_filter) {
2339                 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2340                 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2341                 if (ret)
2342                         return ret;
2343         }
2344
2345         netdev->features = features;
2346         return 0;
2347 }
2348
2349 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2350                                              struct net_device *dev,
2351                                              netdev_features_t features)
2352 {
2353 #define HNS3_MAX_HDR_LEN        480U
2354 #define HNS3_MAX_L4_HDR_LEN     60U
2355
2356         size_t len;
2357
2358         if (skb->ip_summed != CHECKSUM_PARTIAL)
2359                 return features;
2360
2361         if (skb->encapsulation)
2362                 len = skb_inner_transport_header(skb) - skb->data;
2363         else
2364                 len = skb_transport_header(skb) - skb->data;
2365
2366         /* Assume L4 is 60 byte as TCP is the only protocol with a
2367          * a flexible value, and it's max len is 60 bytes.
2368          */
2369         len += HNS3_MAX_L4_HDR_LEN;
2370
2371         /* Hardware only supports checksum on the skb with a max header
2372          * len of 480 bytes.
2373          */
2374         if (len > HNS3_MAX_HDR_LEN)
2375                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2376
2377         return features;
2378 }
2379
2380 static void hns3_nic_get_stats64(struct net_device *netdev,
2381                                  struct rtnl_link_stats64 *stats)
2382 {
2383         struct hns3_nic_priv *priv = netdev_priv(netdev);
2384         int queue_num = priv->ae_handle->kinfo.num_tqps;
2385         struct hnae3_handle *handle = priv->ae_handle;
2386         struct hns3_enet_ring *ring;
2387         u64 rx_length_errors = 0;
2388         u64 rx_crc_errors = 0;
2389         u64 rx_multicast = 0;
2390         unsigned int start;
2391         u64 tx_errors = 0;
2392         u64 rx_errors = 0;
2393         unsigned int idx;
2394         u64 tx_bytes = 0;
2395         u64 rx_bytes = 0;
2396         u64 tx_pkts = 0;
2397         u64 rx_pkts = 0;
2398         u64 tx_drop = 0;
2399         u64 rx_drop = 0;
2400
2401         if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2402                 return;
2403
2404         handle->ae_algo->ops->update_stats(handle, &netdev->stats);
2405
2406         for (idx = 0; idx < queue_num; idx++) {
2407                 /* fetch the tx stats */
2408                 ring = &priv->ring[idx];
2409                 do {
2410                         start = u64_stats_fetch_begin_irq(&ring->syncp);
2411                         tx_bytes += ring->stats.tx_bytes;
2412                         tx_pkts += ring->stats.tx_pkts;
2413                         tx_drop += ring->stats.sw_err_cnt;
2414                         tx_drop += ring->stats.tx_vlan_err;
2415                         tx_drop += ring->stats.tx_l4_proto_err;
2416                         tx_drop += ring->stats.tx_l2l3l4_err;
2417                         tx_drop += ring->stats.tx_tso_err;
2418                         tx_drop += ring->stats.over_max_recursion;
2419                         tx_drop += ring->stats.hw_limitation;
2420                         tx_drop += ring->stats.copy_bits_err;
2421                         tx_drop += ring->stats.skb2sgl_err;
2422                         tx_drop += ring->stats.map_sg_err;
2423                         tx_errors += ring->stats.sw_err_cnt;
2424                         tx_errors += ring->stats.tx_vlan_err;
2425                         tx_errors += ring->stats.tx_l4_proto_err;
2426                         tx_errors += ring->stats.tx_l2l3l4_err;
2427                         tx_errors += ring->stats.tx_tso_err;
2428                         tx_errors += ring->stats.over_max_recursion;
2429                         tx_errors += ring->stats.hw_limitation;
2430                         tx_errors += ring->stats.copy_bits_err;
2431                         tx_errors += ring->stats.skb2sgl_err;
2432                         tx_errors += ring->stats.map_sg_err;
2433                 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2434
2435                 /* fetch the rx stats */
2436                 ring = &priv->ring[idx + queue_num];
2437                 do {
2438                         start = u64_stats_fetch_begin_irq(&ring->syncp);
2439                         rx_bytes += ring->stats.rx_bytes;
2440                         rx_pkts += ring->stats.rx_pkts;
2441                         rx_drop += ring->stats.l2_err;
2442                         rx_errors += ring->stats.l2_err;
2443                         rx_errors += ring->stats.l3l4_csum_err;
2444                         rx_crc_errors += ring->stats.l2_err;
2445                         rx_multicast += ring->stats.rx_multicast;
2446                         rx_length_errors += ring->stats.err_pkt_len;
2447                 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2448         }
2449
2450         stats->tx_bytes = tx_bytes;
2451         stats->tx_packets = tx_pkts;
2452         stats->rx_bytes = rx_bytes;
2453         stats->rx_packets = rx_pkts;
2454
2455         stats->rx_errors = rx_errors;
2456         stats->multicast = rx_multicast;
2457         stats->rx_length_errors = rx_length_errors;
2458         stats->rx_crc_errors = rx_crc_errors;
2459         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2460
2461         stats->tx_errors = tx_errors;
2462         stats->rx_dropped = rx_drop;
2463         stats->tx_dropped = tx_drop;
2464         stats->collisions = netdev->stats.collisions;
2465         stats->rx_over_errors = netdev->stats.rx_over_errors;
2466         stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2467         stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2468         stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2469         stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2470         stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2471         stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2472         stats->tx_window_errors = netdev->stats.tx_window_errors;
2473         stats->rx_compressed = netdev->stats.rx_compressed;
2474         stats->tx_compressed = netdev->stats.tx_compressed;
2475 }
2476
2477 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2478 {
2479         struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2480         struct hnae3_knic_private_info *kinfo;
2481         u8 tc = mqprio_qopt->qopt.num_tc;
2482         u16 mode = mqprio_qopt->mode;
2483         u8 hw = mqprio_qopt->qopt.hw;
2484         struct hnae3_handle *h;
2485
2486         if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2487                mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2488                 return -EOPNOTSUPP;
2489
2490         if (tc > HNAE3_MAX_TC)
2491                 return -EINVAL;
2492
2493         if (!netdev)
2494                 return -EINVAL;
2495
2496         h = hns3_get_handle(netdev);
2497         kinfo = &h->kinfo;
2498
2499         netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2500
2501         return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2502                 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2503 }
2504
2505 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2506                                     struct flow_cls_offload *flow)
2507 {
2508         int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2509         struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2510
2511         switch (flow->command) {
2512         case FLOW_CLS_REPLACE:
2513                 if (h->ae_algo->ops->add_cls_flower)
2514                         return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2515                 break;
2516         case FLOW_CLS_DESTROY:
2517                 if (h->ae_algo->ops->del_cls_flower)
2518                         return h->ae_algo->ops->del_cls_flower(h, flow);
2519                 break;
2520         default:
2521                 break;
2522         }
2523
2524         return -EOPNOTSUPP;
2525 }
2526
2527 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2528                                   void *cb_priv)
2529 {
2530         struct hns3_nic_priv *priv = cb_priv;
2531
2532         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2533                 return -EOPNOTSUPP;
2534
2535         switch (type) {
2536         case TC_SETUP_CLSFLOWER:
2537                 return hns3_setup_tc_cls_flower(priv, type_data);
2538         default:
2539                 return -EOPNOTSUPP;
2540         }
2541 }
2542
2543 static LIST_HEAD(hns3_block_cb_list);
2544
2545 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2546                              void *type_data)
2547 {
2548         struct hns3_nic_priv *priv = netdev_priv(dev);
2549         int ret;
2550
2551         switch (type) {
2552         case TC_SETUP_QDISC_MQPRIO:
2553                 ret = hns3_setup_tc(dev, type_data);
2554                 break;
2555         case TC_SETUP_BLOCK:
2556                 ret = flow_block_cb_setup_simple(type_data,
2557                                                  &hns3_block_cb_list,
2558                                                  hns3_setup_tc_block_cb,
2559                                                  priv, priv, true);
2560                 break;
2561         default:
2562                 return -EOPNOTSUPP;
2563         }
2564
2565         return ret;
2566 }
2567
2568 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2569                                 __be16 proto, u16 vid)
2570 {
2571         struct hnae3_handle *h = hns3_get_handle(netdev);
2572         int ret = -EIO;
2573
2574         if (h->ae_algo->ops->set_vlan_filter)
2575                 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2576
2577         return ret;
2578 }
2579
2580 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2581                                  __be16 proto, u16 vid)
2582 {
2583         struct hnae3_handle *h = hns3_get_handle(netdev);
2584         int ret = -EIO;
2585
2586         if (h->ae_algo->ops->set_vlan_filter)
2587                 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2588
2589         return ret;
2590 }
2591
2592 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2593                                 u8 qos, __be16 vlan_proto)
2594 {
2595         struct hnae3_handle *h = hns3_get_handle(netdev);
2596         int ret = -EIO;
2597
2598         netif_dbg(h, drv, netdev,
2599                   "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2600                   vf, vlan, qos, ntohs(vlan_proto));
2601
2602         if (h->ae_algo->ops->set_vf_vlan_filter)
2603                 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2604                                                           qos, vlan_proto);
2605
2606         return ret;
2607 }
2608
2609 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2610 {
2611         struct hnae3_handle *handle = hns3_get_handle(netdev);
2612
2613         if (hns3_nic_resetting(netdev))
2614                 return -EBUSY;
2615
2616         if (!handle->ae_algo->ops->set_vf_spoofchk)
2617                 return -EOPNOTSUPP;
2618
2619         return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2620 }
2621
2622 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2623 {
2624         struct hnae3_handle *handle = hns3_get_handle(netdev);
2625
2626         if (!handle->ae_algo->ops->set_vf_trust)
2627                 return -EOPNOTSUPP;
2628
2629         return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2630 }
2631
2632 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2633 {
2634         struct hnae3_handle *h = hns3_get_handle(netdev);
2635         int ret;
2636
2637         if (hns3_nic_resetting(netdev))
2638                 return -EBUSY;
2639
2640         if (!h->ae_algo->ops->set_mtu)
2641                 return -EOPNOTSUPP;
2642
2643         netif_dbg(h, drv, netdev,
2644                   "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2645
2646         ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2647         if (ret)
2648                 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2649                            ret);
2650         else
2651                 netdev->mtu = new_mtu;
2652
2653         return ret;
2654 }
2655
2656 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2657 {
2658         struct hns3_nic_priv *priv = netdev_priv(ndev);
2659         struct hnae3_handle *h = hns3_get_handle(ndev);
2660         struct hns3_enet_ring *tx_ring;
2661         struct napi_struct *napi;
2662         int timeout_queue = 0;
2663         int hw_head, hw_tail;
2664         int fbd_num, fbd_oft;
2665         int ebd_num, ebd_oft;
2666         int bd_num, bd_err;
2667         int ring_en, tc;
2668         int i;
2669
2670         /* Find the stopped queue the same way the stack does */
2671         for (i = 0; i < ndev->num_tx_queues; i++) {
2672                 struct netdev_queue *q;
2673                 unsigned long trans_start;
2674
2675                 q = netdev_get_tx_queue(ndev, i);
2676                 trans_start = q->trans_start;
2677                 if (netif_xmit_stopped(q) &&
2678                     time_after(jiffies,
2679                                (trans_start + ndev->watchdog_timeo))) {
2680                         timeout_queue = i;
2681                         netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2682                                     q->state,
2683                                     jiffies_to_msecs(jiffies - trans_start));
2684                         break;
2685                 }
2686         }
2687
2688         if (i == ndev->num_tx_queues) {
2689                 netdev_info(ndev,
2690                             "no netdev TX timeout queue found, timeout count: %llu\n",
2691                             priv->tx_timeout_count);
2692                 return false;
2693         }
2694
2695         priv->tx_timeout_count++;
2696
2697         tx_ring = &priv->ring[timeout_queue];
2698         napi = &tx_ring->tqp_vector->napi;
2699
2700         netdev_info(ndev,
2701                     "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2702                     priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2703                     tx_ring->next_to_clean, napi->state);
2704
2705         netdev_info(ndev,
2706                     "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2707                     tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2708                     tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2709
2710         netdev_info(ndev,
2711                     "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2712                     tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2713                     tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2714
2715         /* When mac received many pause frames continuous, it's unable to send
2716          * packets, which may cause tx timeout
2717          */
2718         if (h->ae_algo->ops->get_mac_stats) {
2719                 struct hns3_mac_stats mac_stats;
2720
2721                 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2722                 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2723                             mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2724         }
2725
2726         hw_head = readl_relaxed(tx_ring->tqp->io_base +
2727                                 HNS3_RING_TX_RING_HEAD_REG);
2728         hw_tail = readl_relaxed(tx_ring->tqp->io_base +
2729                                 HNS3_RING_TX_RING_TAIL_REG);
2730         fbd_num = readl_relaxed(tx_ring->tqp->io_base +
2731                                 HNS3_RING_TX_RING_FBDNUM_REG);
2732         fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
2733                                 HNS3_RING_TX_RING_OFFSET_REG);
2734         ebd_num = readl_relaxed(tx_ring->tqp->io_base +
2735                                 HNS3_RING_TX_RING_EBDNUM_REG);
2736         ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
2737                                 HNS3_RING_TX_RING_EBD_OFFSET_REG);
2738         bd_num = readl_relaxed(tx_ring->tqp->io_base +
2739                                HNS3_RING_TX_RING_BD_NUM_REG);
2740         bd_err = readl_relaxed(tx_ring->tqp->io_base +
2741                                HNS3_RING_TX_RING_BD_ERR_REG);
2742         ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
2743         tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
2744
2745         netdev_info(ndev,
2746                     "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2747                     bd_num, hw_head, hw_tail, bd_err,
2748                     readl(tx_ring->tqp_vector->mask_addr));
2749         netdev_info(ndev,
2750                     "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2751                     ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
2752
2753         return true;
2754 }
2755
2756 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2757 {
2758         struct hns3_nic_priv *priv = netdev_priv(ndev);
2759         struct hnae3_handle *h = priv->ae_handle;
2760
2761         if (!hns3_get_tx_timeo_queue_info(ndev))
2762                 return;
2763
2764         /* request the reset, and let the hclge to determine
2765          * which reset level should be done
2766          */
2767         if (h->ae_algo->ops->reset_event)
2768                 h->ae_algo->ops->reset_event(h->pdev, h);
2769 }
2770
2771 #ifdef CONFIG_RFS_ACCEL
2772 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2773                               u16 rxq_index, u32 flow_id)
2774 {
2775         struct hnae3_handle *h = hns3_get_handle(dev);
2776         struct flow_keys fkeys;
2777
2778         if (!h->ae_algo->ops->add_arfs_entry)
2779                 return -EOPNOTSUPP;
2780
2781         if (skb->encapsulation)
2782                 return -EPROTONOSUPPORT;
2783
2784         if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2785                 return -EPROTONOSUPPORT;
2786
2787         if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2788              fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2789             (fkeys.basic.ip_proto != IPPROTO_TCP &&
2790              fkeys.basic.ip_proto != IPPROTO_UDP))
2791                 return -EPROTONOSUPPORT;
2792
2793         return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2794 }
2795 #endif
2796
2797 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2798                                   struct ifla_vf_info *ivf)
2799 {
2800         struct hnae3_handle *h = hns3_get_handle(ndev);
2801
2802         if (!h->ae_algo->ops->get_vf_config)
2803                 return -EOPNOTSUPP;
2804
2805         return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2806 }
2807
2808 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2809                                       int link_state)
2810 {
2811         struct hnae3_handle *h = hns3_get_handle(ndev);
2812
2813         if (!h->ae_algo->ops->set_vf_link_state)
2814                 return -EOPNOTSUPP;
2815
2816         return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2817 }
2818
2819 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2820                                 int min_tx_rate, int max_tx_rate)
2821 {
2822         struct hnae3_handle *h = hns3_get_handle(ndev);
2823
2824         if (!h->ae_algo->ops->set_vf_rate)
2825                 return -EOPNOTSUPP;
2826
2827         return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2828                                             false);
2829 }
2830
2831 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2832 {
2833         struct hnae3_handle *h = hns3_get_handle(netdev);
2834
2835         if (!h->ae_algo->ops->set_vf_mac)
2836                 return -EOPNOTSUPP;
2837
2838         if (is_multicast_ether_addr(mac)) {
2839                 netdev_err(netdev,
2840                            "Invalid MAC:%pM specified. Could not set MAC\n",
2841                            mac);
2842                 return -EINVAL;
2843         }
2844
2845         return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2846 }
2847
2848 static const struct net_device_ops hns3_nic_netdev_ops = {
2849         .ndo_open               = hns3_nic_net_open,
2850         .ndo_stop               = hns3_nic_net_stop,
2851         .ndo_start_xmit         = hns3_nic_net_xmit,
2852         .ndo_tx_timeout         = hns3_nic_net_timeout,
2853         .ndo_set_mac_address    = hns3_nic_net_set_mac_address,
2854         .ndo_eth_ioctl          = hns3_nic_do_ioctl,
2855         .ndo_change_mtu         = hns3_nic_change_mtu,
2856         .ndo_set_features       = hns3_nic_set_features,
2857         .ndo_features_check     = hns3_features_check,
2858         .ndo_get_stats64        = hns3_nic_get_stats64,
2859         .ndo_setup_tc           = hns3_nic_setup_tc,
2860         .ndo_set_rx_mode        = hns3_nic_set_rx_mode,
2861         .ndo_vlan_rx_add_vid    = hns3_vlan_rx_add_vid,
2862         .ndo_vlan_rx_kill_vid   = hns3_vlan_rx_kill_vid,
2863         .ndo_set_vf_vlan        = hns3_ndo_set_vf_vlan,
2864         .ndo_set_vf_spoofchk    = hns3_set_vf_spoofchk,
2865         .ndo_set_vf_trust       = hns3_set_vf_trust,
2866 #ifdef CONFIG_RFS_ACCEL
2867         .ndo_rx_flow_steer      = hns3_rx_flow_steer,
2868 #endif
2869         .ndo_get_vf_config      = hns3_nic_get_vf_config,
2870         .ndo_set_vf_link_state  = hns3_nic_set_vf_link_state,
2871         .ndo_set_vf_rate        = hns3_nic_set_vf_rate,
2872         .ndo_set_vf_mac         = hns3_nic_set_vf_mac,
2873 };
2874
2875 bool hns3_is_phys_func(struct pci_dev *pdev)
2876 {
2877         u32 dev_id = pdev->device;
2878
2879         switch (dev_id) {
2880         case HNAE3_DEV_ID_GE:
2881         case HNAE3_DEV_ID_25GE:
2882         case HNAE3_DEV_ID_25GE_RDMA:
2883         case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2884         case HNAE3_DEV_ID_50GE_RDMA:
2885         case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2886         case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2887         case HNAE3_DEV_ID_200G_RDMA:
2888                 return true;
2889         case HNAE3_DEV_ID_VF:
2890         case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
2891                 return false;
2892         default:
2893                 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2894                          dev_id);
2895         }
2896
2897         return false;
2898 }
2899
2900 static void hns3_disable_sriov(struct pci_dev *pdev)
2901 {
2902         /* If our VFs are assigned we cannot shut down SR-IOV
2903          * without causing issues, so just leave the hardware
2904          * available but disabled
2905          */
2906         if (pci_vfs_assigned(pdev)) {
2907                 dev_warn(&pdev->dev,
2908                          "disabling driver while VFs are assigned\n");
2909                 return;
2910         }
2911
2912         pci_disable_sriov(pdev);
2913 }
2914
2915 /* hns3_probe - Device initialization routine
2916  * @pdev: PCI device information struct
2917  * @ent: entry in hns3_pci_tbl
2918  *
2919  * hns3_probe initializes a PF identified by a pci_dev structure.
2920  * The OS initialization, configuring of the PF private structure,
2921  * and a hardware reset occur.
2922  *
2923  * Returns 0 on success, negative on failure
2924  */
2925 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2926 {
2927         struct hnae3_ae_dev *ae_dev;
2928         int ret;
2929
2930         ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2931         if (!ae_dev)
2932                 return -ENOMEM;
2933
2934         ae_dev->pdev = pdev;
2935         ae_dev->flag = ent->driver_data;
2936         pci_set_drvdata(pdev, ae_dev);
2937
2938         ret = hnae3_register_ae_dev(ae_dev);
2939         if (ret)
2940                 pci_set_drvdata(pdev, NULL);
2941
2942         return ret;
2943 }
2944
2945 /* hns3_remove - Device removal routine
2946  * @pdev: PCI device information struct
2947  */
2948 static void hns3_remove(struct pci_dev *pdev)
2949 {
2950         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2951
2952         if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2953                 hns3_disable_sriov(pdev);
2954
2955         hnae3_unregister_ae_dev(ae_dev);
2956         pci_set_drvdata(pdev, NULL);
2957 }
2958
2959 /**
2960  * hns3_pci_sriov_configure
2961  * @pdev: pointer to a pci_dev structure
2962  * @num_vfs: number of VFs to allocate
2963  *
2964  * Enable or change the number of VFs. Called when the user updates the number
2965  * of VFs in sysfs.
2966  **/
2967 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2968 {
2969         int ret;
2970
2971         if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2972                 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2973                 return -EINVAL;
2974         }
2975
2976         if (num_vfs) {
2977                 ret = pci_enable_sriov(pdev, num_vfs);
2978                 if (ret)
2979                         dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2980                 else
2981                         return num_vfs;
2982         } else if (!pci_vfs_assigned(pdev)) {
2983                 pci_disable_sriov(pdev);
2984         } else {
2985                 dev_warn(&pdev->dev,
2986                          "Unable to free VFs because some are assigned to VMs.\n");
2987         }
2988
2989         return 0;
2990 }
2991
2992 static void hns3_shutdown(struct pci_dev *pdev)
2993 {
2994         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2995
2996         hnae3_unregister_ae_dev(ae_dev);
2997         pci_set_drvdata(pdev, NULL);
2998
2999         if (system_state == SYSTEM_POWER_OFF)
3000                 pci_set_power_state(pdev, PCI_D3hot);
3001 }
3002
3003 static int __maybe_unused hns3_suspend(struct device *dev)
3004 {
3005         struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3006
3007         if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3008                 dev_info(dev, "Begin to suspend.\n");
3009                 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3010                         ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3011         }
3012
3013         return 0;
3014 }
3015
3016 static int __maybe_unused hns3_resume(struct device *dev)
3017 {
3018         struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3019
3020         if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3021                 dev_info(dev, "Begin to resume.\n");
3022                 if (ae_dev->ops && ae_dev->ops->reset_done)
3023                         ae_dev->ops->reset_done(ae_dev);
3024         }
3025
3026         return 0;
3027 }
3028
3029 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3030                                             pci_channel_state_t state)
3031 {
3032         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3033         pci_ers_result_t ret;
3034
3035         dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3036
3037         if (state == pci_channel_io_perm_failure)
3038                 return PCI_ERS_RESULT_DISCONNECT;
3039
3040         if (!ae_dev || !ae_dev->ops) {
3041                 dev_err(&pdev->dev,
3042                         "Can't recover - error happened before device initialized\n");
3043                 return PCI_ERS_RESULT_NONE;
3044         }
3045
3046         if (ae_dev->ops->handle_hw_ras_error)
3047                 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3048         else
3049                 return PCI_ERS_RESULT_NONE;
3050
3051         return ret;
3052 }
3053
3054 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3055 {
3056         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3057         const struct hnae3_ae_ops *ops;
3058         enum hnae3_reset_type reset_type;
3059         struct device *dev = &pdev->dev;
3060
3061         if (!ae_dev || !ae_dev->ops)
3062                 return PCI_ERS_RESULT_NONE;
3063
3064         ops = ae_dev->ops;
3065         /* request the reset */
3066         if (ops->reset_event && ops->get_reset_level &&
3067             ops->set_default_reset_request) {
3068                 if (ae_dev->hw_err_reset_req) {
3069                         reset_type = ops->get_reset_level(ae_dev,
3070                                                 &ae_dev->hw_err_reset_req);
3071                         ops->set_default_reset_request(ae_dev, reset_type);
3072                         dev_info(dev, "requesting reset due to PCI error\n");
3073                         ops->reset_event(pdev, NULL);
3074                 }
3075
3076                 return PCI_ERS_RESULT_RECOVERED;
3077         }
3078
3079         return PCI_ERS_RESULT_DISCONNECT;
3080 }
3081
3082 static void hns3_reset_prepare(struct pci_dev *pdev)
3083 {
3084         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3085
3086         dev_info(&pdev->dev, "FLR prepare\n");
3087         if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3088                 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3089 }
3090
3091 static void hns3_reset_done(struct pci_dev *pdev)
3092 {
3093         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3094
3095         dev_info(&pdev->dev, "FLR done\n");
3096         if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3097                 ae_dev->ops->reset_done(ae_dev);
3098 }
3099
3100 static const struct pci_error_handlers hns3_err_handler = {
3101         .error_detected = hns3_error_detected,
3102         .slot_reset     = hns3_slot_reset,
3103         .reset_prepare  = hns3_reset_prepare,
3104         .reset_done     = hns3_reset_done,
3105 };
3106
3107 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3108
3109 static struct pci_driver hns3_driver = {
3110         .name     = hns3_driver_name,
3111         .id_table = hns3_pci_tbl,
3112         .probe    = hns3_probe,
3113         .remove   = hns3_remove,
3114         .shutdown = hns3_shutdown,
3115         .driver.pm  = &hns3_pm_ops,
3116         .sriov_configure = hns3_pci_sriov_configure,
3117         .err_handler    = &hns3_err_handler,
3118 };
3119
3120 /* set default feature to hns3 */
3121 static void hns3_set_default_feature(struct net_device *netdev)
3122 {
3123         struct hnae3_handle *h = hns3_get_handle(netdev);
3124         struct pci_dev *pdev = h->pdev;
3125         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3126
3127         netdev->priv_flags |= IFF_UNICAST_FLT;
3128
3129         netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
3130
3131         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3132                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3133                 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3134                 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3135                 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3136                 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3137
3138         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3139                 netdev->features |= NETIF_F_GRO_HW;
3140
3141                 if (!(h->flags & HNAE3_SUPPORT_VF))
3142                         netdev->features |= NETIF_F_NTUPLE;
3143         }
3144
3145         if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3146                 netdev->features |= NETIF_F_GSO_UDP_L4;
3147
3148         if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3149                 netdev->features |= NETIF_F_HW_CSUM;
3150         else
3151                 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3152
3153         if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3154                 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3155
3156         if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3157                 netdev->features |= NETIF_F_HW_TC;
3158
3159         netdev->hw_features |= netdev->features;
3160         if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3161                 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3162
3163         netdev->vlan_features |= netdev->features &
3164                 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3165                   NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3166                   NETIF_F_HW_TC);
3167
3168         netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3169 }
3170
3171 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3172                              struct hns3_desc_cb *cb)
3173 {
3174         unsigned int order = hns3_page_order(ring);
3175         struct page *p;
3176
3177         if (ring->page_pool) {
3178                 p = page_pool_dev_alloc_frag(ring->page_pool,
3179                                              &cb->page_offset,
3180                                              hns3_buf_size(ring));
3181                 if (unlikely(!p))
3182                         return -ENOMEM;
3183
3184                 cb->priv = p;
3185                 cb->buf = page_address(p);
3186                 cb->dma = page_pool_get_dma_addr(p);
3187                 cb->type = DESC_TYPE_PP_FRAG;
3188                 cb->reuse_flag = 0;
3189                 return 0;
3190         }
3191
3192         p = dev_alloc_pages(order);
3193         if (!p)
3194                 return -ENOMEM;
3195
3196         cb->priv = p;
3197         cb->page_offset = 0;
3198         cb->reuse_flag = 0;
3199         cb->buf  = page_address(p);
3200         cb->length = hns3_page_size(ring);
3201         cb->type = DESC_TYPE_PAGE;
3202         page_ref_add(p, USHRT_MAX - 1);
3203         cb->pagecnt_bias = USHRT_MAX;
3204
3205         return 0;
3206 }
3207
3208 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3209                              struct hns3_desc_cb *cb, int budget)
3210 {
3211         if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3212                         DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3213                 napi_consume_skb(cb->priv, budget);
3214         else if (!HNAE3_IS_TX_RING(ring)) {
3215                 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3216                         __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3217                 else if (cb->type & DESC_TYPE_PP_FRAG)
3218                         page_pool_put_full_page(ring->page_pool, cb->priv,
3219                                                 false);
3220         }
3221         memset(cb, 0, sizeof(*cb));
3222 }
3223
3224 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3225 {
3226         cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3227                                cb->length, ring_to_dma_dir(ring));
3228
3229         if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3230                 return -EIO;
3231
3232         return 0;
3233 }
3234
3235 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3236                               struct hns3_desc_cb *cb)
3237 {
3238         if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3239                 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3240                                  ring_to_dma_dir(ring));
3241         else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3242                 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3243                                ring_to_dma_dir(ring));
3244         else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3245                              DESC_TYPE_SGL_SKB))
3246                 hns3_tx_spare_reclaim_cb(ring, cb);
3247 }
3248
3249 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3250 {
3251         hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3252         ring->desc[i].addr = 0;
3253 }
3254
3255 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3256                                     int budget)
3257 {
3258         struct hns3_desc_cb *cb = &ring->desc_cb[i];
3259
3260         if (!ring->desc_cb[i].dma)
3261                 return;
3262
3263         hns3_buffer_detach(ring, i);
3264         hns3_free_buffer(ring, cb, budget);
3265 }
3266
3267 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3268 {
3269         int i;
3270
3271         for (i = 0; i < ring->desc_num; i++)
3272                 hns3_free_buffer_detach(ring, i, 0);
3273 }
3274
3275 /* free desc along with its attached buffer */
3276 static void hns3_free_desc(struct hns3_enet_ring *ring)
3277 {
3278         int size = ring->desc_num * sizeof(ring->desc[0]);
3279
3280         hns3_free_buffers(ring);
3281
3282         if (ring->desc) {
3283                 dma_free_coherent(ring_to_dev(ring), size,
3284                                   ring->desc, ring->desc_dma_addr);
3285                 ring->desc = NULL;
3286         }
3287 }
3288
3289 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3290 {
3291         int size = ring->desc_num * sizeof(ring->desc[0]);
3292
3293         ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3294                                         &ring->desc_dma_addr, GFP_KERNEL);
3295         if (!ring->desc)
3296                 return -ENOMEM;
3297
3298         return 0;
3299 }
3300
3301 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3302                                    struct hns3_desc_cb *cb)
3303 {
3304         int ret;
3305
3306         ret = hns3_alloc_buffer(ring, cb);
3307         if (ret || ring->page_pool)
3308                 goto out;
3309
3310         ret = hns3_map_buffer(ring, cb);
3311         if (ret)
3312                 goto out_with_buf;
3313
3314         return 0;
3315
3316 out_with_buf:
3317         hns3_free_buffer(ring, cb, 0);
3318 out:
3319         return ret;
3320 }
3321
3322 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3323 {
3324         int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3325
3326         if (ret)
3327                 return ret;
3328
3329         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3330                                          ring->desc_cb[i].page_offset);
3331
3332         return 0;
3333 }
3334
3335 /* Allocate memory for raw pkg, and map with dma */
3336 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3337 {
3338         int i, j, ret;
3339
3340         for (i = 0; i < ring->desc_num; i++) {
3341                 ret = hns3_alloc_and_attach_buffer(ring, i);
3342                 if (ret)
3343                         goto out_buffer_fail;
3344         }
3345
3346         return 0;
3347
3348 out_buffer_fail:
3349         for (j = i - 1; j >= 0; j--)
3350                 hns3_free_buffer_detach(ring, j, 0);
3351         return ret;
3352 }
3353
3354 /* detach a in-used buffer and replace with a reserved one */
3355 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3356                                 struct hns3_desc_cb *res_cb)
3357 {
3358         hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3359         ring->desc_cb[i] = *res_cb;
3360         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3361                                          ring->desc_cb[i].page_offset);
3362         ring->desc[i].rx.bd_base_info = 0;
3363 }
3364
3365 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3366 {
3367         ring->desc_cb[i].reuse_flag = 0;
3368         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3369                                          ring->desc_cb[i].page_offset);
3370         ring->desc[i].rx.bd_base_info = 0;
3371
3372         dma_sync_single_for_device(ring_to_dev(ring),
3373                         ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3374                         hns3_buf_size(ring),
3375                         DMA_FROM_DEVICE);
3376 }
3377
3378 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3379                                   int *bytes, int *pkts, int budget)
3380 {
3381         /* pair with ring->last_to_use update in hns3_tx_doorbell(),
3382          * smp_store_release() is not used in hns3_tx_doorbell() because
3383          * the doorbell operation already have the needed barrier operation.
3384          */
3385         int ltu = smp_load_acquire(&ring->last_to_use);
3386         int ntc = ring->next_to_clean;
3387         struct hns3_desc_cb *desc_cb;
3388         bool reclaimed = false;
3389         struct hns3_desc *desc;
3390
3391         while (ltu != ntc) {
3392                 desc = &ring->desc[ntc];
3393
3394                 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3395                                 BIT(HNS3_TXD_VLD_B))
3396                         break;
3397
3398                 desc_cb = &ring->desc_cb[ntc];
3399
3400                 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3401                                      DESC_TYPE_BOUNCE_HEAD |
3402                                      DESC_TYPE_SGL_SKB)) {
3403                         (*pkts)++;
3404                         (*bytes) += desc_cb->send_bytes;
3405                 }
3406
3407                 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3408                 hns3_free_buffer_detach(ring, ntc, budget);
3409
3410                 if (++ntc == ring->desc_num)
3411                         ntc = 0;
3412
3413                 /* Issue prefetch for next Tx descriptor */
3414                 prefetch(&ring->desc_cb[ntc]);
3415                 reclaimed = true;
3416         }
3417
3418         if (unlikely(!reclaimed))
3419                 return false;
3420
3421         /* This smp_store_release() pairs with smp_load_acquire() in
3422          * ring_space called by hns3_nic_net_xmit.
3423          */
3424         smp_store_release(&ring->next_to_clean, ntc);
3425
3426         hns3_tx_spare_update(ring);
3427
3428         return true;
3429 }
3430
3431 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3432 {
3433         struct net_device *netdev = ring_to_netdev(ring);
3434         struct hns3_nic_priv *priv = netdev_priv(netdev);
3435         struct netdev_queue *dev_queue;
3436         int bytes, pkts;
3437
3438         bytes = 0;
3439         pkts = 0;
3440
3441         if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3442                 return;
3443
3444         ring->tqp_vector->tx_group.total_bytes += bytes;
3445         ring->tqp_vector->tx_group.total_packets += pkts;
3446
3447         u64_stats_update_begin(&ring->syncp);
3448         ring->stats.tx_bytes += bytes;
3449         ring->stats.tx_pkts += pkts;
3450         u64_stats_update_end(&ring->syncp);
3451
3452         dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3453         netdev_tx_completed_queue(dev_queue, pkts, bytes);
3454
3455         if (unlikely(netif_carrier_ok(netdev) &&
3456                      ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3457                 /* Make sure that anybody stopping the queue after this
3458                  * sees the new next_to_clean.
3459                  */
3460                 smp_mb();
3461                 if (netif_tx_queue_stopped(dev_queue) &&
3462                     !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3463                         netif_tx_wake_queue(dev_queue);
3464                         ring->stats.restart_queue++;
3465                 }
3466         }
3467 }
3468
3469 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3470 {
3471         int ntc = ring->next_to_clean;
3472         int ntu = ring->next_to_use;
3473
3474         return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3475 }
3476
3477 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3478                                       int cleand_count)
3479 {
3480         struct hns3_desc_cb *desc_cb;
3481         struct hns3_desc_cb res_cbs;
3482         int i, ret;
3483
3484         for (i = 0; i < cleand_count; i++) {
3485                 desc_cb = &ring->desc_cb[ring->next_to_use];
3486                 if (desc_cb->reuse_flag) {
3487                         u64_stats_update_begin(&ring->syncp);
3488                         ring->stats.reuse_pg_cnt++;
3489                         u64_stats_update_end(&ring->syncp);
3490
3491                         hns3_reuse_buffer(ring, ring->next_to_use);
3492                 } else {
3493                         ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3494                         if (ret) {
3495                                 u64_stats_update_begin(&ring->syncp);
3496                                 ring->stats.sw_err_cnt++;
3497                                 u64_stats_update_end(&ring->syncp);
3498
3499                                 hns3_rl_err(ring_to_netdev(ring),
3500                                             "alloc rx buffer failed: %d\n",
3501                                             ret);
3502                                 break;
3503                         }
3504                         hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3505
3506                         u64_stats_update_begin(&ring->syncp);
3507                         ring->stats.non_reuse_pg++;
3508                         u64_stats_update_end(&ring->syncp);
3509                 }
3510
3511                 ring_ptr_move_fw(ring, next_to_use);
3512         }
3513
3514         writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3515 }
3516
3517 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3518 {
3519         return page_count(cb->priv) == cb->pagecnt_bias;
3520 }
3521
3522 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3523                                 struct hns3_enet_ring *ring, int pull_len,
3524                                 struct hns3_desc_cb *desc_cb)
3525 {
3526         struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3527         u32 frag_offset = desc_cb->page_offset + pull_len;
3528         int size = le16_to_cpu(desc->rx.size);
3529         u32 truesize = hns3_buf_size(ring);
3530         u32 frag_size = size - pull_len;
3531         bool reused;
3532
3533         if (ring->page_pool) {
3534                 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3535                                 frag_size, truesize);
3536                 return;
3537         }
3538
3539         /* Avoid re-using remote or pfmem page */
3540         if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3541                 goto out;
3542
3543         reused = hns3_can_reuse_page(desc_cb);
3544
3545         /* Rx page can be reused when:
3546          * 1. Rx page is only owned by the driver when page_offset
3547          *    is zero, which means 0 @ truesize will be used by
3548          *    stack after skb_add_rx_frag() is called, and the rest
3549          *    of rx page can be reused by driver.
3550          * Or
3551          * 2. Rx page is only owned by the driver when page_offset
3552          *    is non-zero, which means page_offset @ truesize will
3553          *    be used by stack after skb_add_rx_frag() is called,
3554          *    and 0 @ truesize can be reused by driver.
3555          */
3556         if ((!desc_cb->page_offset && reused) ||
3557             ((desc_cb->page_offset + truesize + truesize) <=
3558              hns3_page_size(ring) && desc_cb->page_offset)) {
3559                 desc_cb->page_offset += truesize;
3560                 desc_cb->reuse_flag = 1;
3561         } else if (desc_cb->page_offset && reused) {
3562                 desc_cb->page_offset = 0;
3563                 desc_cb->reuse_flag = 1;
3564         } else if (frag_size <= ring->rx_copybreak) {
3565                 void *frag = napi_alloc_frag(frag_size);
3566
3567                 if (unlikely(!frag)) {
3568                         u64_stats_update_begin(&ring->syncp);
3569                         ring->stats.frag_alloc_err++;
3570                         u64_stats_update_end(&ring->syncp);
3571
3572                         hns3_rl_err(ring_to_netdev(ring),
3573                                     "failed to allocate rx frag\n");
3574                         goto out;
3575                 }
3576
3577                 desc_cb->reuse_flag = 1;
3578                 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3579                 skb_add_rx_frag(skb, i, virt_to_page(frag),
3580                                 offset_in_page(frag), frag_size, frag_size);
3581
3582                 u64_stats_update_begin(&ring->syncp);
3583                 ring->stats.frag_alloc++;
3584                 u64_stats_update_end(&ring->syncp);
3585                 return;
3586         }
3587
3588 out:
3589         desc_cb->pagecnt_bias--;
3590
3591         if (unlikely(!desc_cb->pagecnt_bias)) {
3592                 page_ref_add(desc_cb->priv, USHRT_MAX);
3593                 desc_cb->pagecnt_bias = USHRT_MAX;
3594         }
3595
3596         skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3597                         frag_size, truesize);
3598
3599         if (unlikely(!desc_cb->reuse_flag))
3600                 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3601 }
3602
3603 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3604 {
3605         __be16 type = skb->protocol;
3606         struct tcphdr *th;
3607         int depth = 0;
3608
3609         while (eth_type_vlan(type)) {
3610                 struct vlan_hdr *vh;
3611
3612                 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3613                         return -EFAULT;
3614
3615                 vh = (struct vlan_hdr *)(skb->data + depth);
3616                 type = vh->h_vlan_encapsulated_proto;
3617                 depth += VLAN_HLEN;
3618         }
3619
3620         skb_set_network_header(skb, depth);
3621
3622         if (type == htons(ETH_P_IP)) {
3623                 const struct iphdr *iph = ip_hdr(skb);
3624
3625                 depth += sizeof(struct iphdr);
3626                 skb_set_transport_header(skb, depth);
3627                 th = tcp_hdr(skb);
3628                 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3629                                           iph->daddr, 0);
3630         } else if (type == htons(ETH_P_IPV6)) {
3631                 const struct ipv6hdr *iph = ipv6_hdr(skb);
3632
3633                 depth += sizeof(struct ipv6hdr);
3634                 skb_set_transport_header(skb, depth);
3635                 th = tcp_hdr(skb);
3636                 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3637                                           &iph->daddr, 0);
3638         } else {
3639                 hns3_rl_err(skb->dev,
3640                             "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3641                             be16_to_cpu(type), depth);
3642                 return -EFAULT;
3643         }
3644
3645         skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3646         if (th->cwr)
3647                 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3648
3649         if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3650                 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3651
3652         skb->csum_start = (unsigned char *)th - skb->head;
3653         skb->csum_offset = offsetof(struct tcphdr, check);
3654         skb->ip_summed = CHECKSUM_PARTIAL;
3655
3656         trace_hns3_gro(skb);
3657
3658         return 0;
3659 }
3660
3661 static bool hns3_checksum_complete(struct hns3_enet_ring *ring,
3662                                    struct sk_buff *skb, u32 ptype, u16 csum)
3663 {
3664         if (ptype == HNS3_INVALID_PTYPE ||
3665             hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3666                 return false;
3667
3668         u64_stats_update_begin(&ring->syncp);
3669         ring->stats.csum_complete++;
3670         u64_stats_update_end(&ring->syncp);
3671         skb->ip_summed = CHECKSUM_COMPLETE;
3672         skb->csum = csum_unfold((__force __sum16)csum);
3673
3674         return true;
3675 }
3676
3677 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3678                                 u32 ol_info, u32 ptype)
3679 {
3680         int l3_type, l4_type;
3681         int ol4_type;
3682
3683         if (ptype != HNS3_INVALID_PTYPE) {
3684                 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3685                 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3686
3687                 return;
3688         }
3689
3690         ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3691                                    HNS3_RXD_OL4ID_S);
3692         switch (ol4_type) {
3693         case HNS3_OL4_TYPE_MAC_IN_UDP:
3694         case HNS3_OL4_TYPE_NVGRE:
3695                 skb->csum_level = 1;
3696                 fallthrough;
3697         case HNS3_OL4_TYPE_NO_TUN:
3698                 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3699                                           HNS3_RXD_L3ID_S);
3700                 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3701                                           HNS3_RXD_L4ID_S);
3702                 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3703                 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3704                      l3_type == HNS3_L3_TYPE_IPV6) &&
3705                     (l4_type == HNS3_L4_TYPE_UDP ||
3706                      l4_type == HNS3_L4_TYPE_TCP ||
3707                      l4_type == HNS3_L4_TYPE_SCTP))
3708                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3709                 break;
3710         default:
3711                 break;
3712         }
3713 }
3714
3715 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3716                              u32 l234info, u32 bd_base_info, u32 ol_info,
3717                              u16 csum)
3718 {
3719         struct net_device *netdev = ring_to_netdev(ring);
3720         struct hns3_nic_priv *priv = netdev_priv(netdev);
3721         u32 ptype = HNS3_INVALID_PTYPE;
3722
3723         skb->ip_summed = CHECKSUM_NONE;
3724
3725         skb_checksum_none_assert(skb);
3726
3727         if (!(netdev->features & NETIF_F_RXCSUM))
3728                 return;
3729
3730         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3731                 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3732                                         HNS3_RXD_PTYPE_S);
3733
3734         if (hns3_checksum_complete(ring, skb, ptype, csum))
3735                 return;
3736
3737         /* check if hardware has done checksum */
3738         if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3739                 return;
3740
3741         if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3742                                  BIT(HNS3_RXD_OL3E_B) |
3743                                  BIT(HNS3_RXD_OL4E_B)))) {
3744                 u64_stats_update_begin(&ring->syncp);
3745                 ring->stats.l3l4_csum_err++;
3746                 u64_stats_update_end(&ring->syncp);
3747
3748                 return;
3749         }
3750
3751         hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3752 }
3753
3754 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3755 {
3756         if (skb_has_frag_list(skb))
3757                 napi_gro_flush(&ring->tqp_vector->napi, false);
3758
3759         napi_gro_receive(&ring->tqp_vector->napi, skb);
3760 }
3761
3762 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3763                                 struct hns3_desc *desc, u32 l234info,
3764                                 u16 *vlan_tag)
3765 {
3766         struct hnae3_handle *handle = ring->tqp->handle;
3767         struct pci_dev *pdev = ring->tqp->handle->pdev;
3768         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3769
3770         if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3771                 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3772                 if (!(*vlan_tag & VLAN_VID_MASK))
3773                         *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3774
3775                 return (*vlan_tag != 0);
3776         }
3777
3778 #define HNS3_STRP_OUTER_VLAN    0x1
3779 #define HNS3_STRP_INNER_VLAN    0x2
3780 #define HNS3_STRP_BOTH          0x3
3781
3782         /* Hardware always insert VLAN tag into RX descriptor when
3783          * remove the tag from packet, driver needs to determine
3784          * reporting which tag to stack.
3785          */
3786         switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3787                                 HNS3_RXD_STRP_TAGP_S)) {
3788         case HNS3_STRP_OUTER_VLAN:
3789                 if (handle->port_base_vlan_state !=
3790                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3791                         return false;
3792
3793                 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3794                 return true;
3795         case HNS3_STRP_INNER_VLAN:
3796                 if (handle->port_base_vlan_state !=
3797                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3798                         return false;
3799
3800                 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3801                 return true;
3802         case HNS3_STRP_BOTH:
3803                 if (handle->port_base_vlan_state ==
3804                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3805                         *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3806                 else
3807                         *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3808
3809                 return true;
3810         default:
3811                 return false;
3812         }
3813 }
3814
3815 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
3816 {
3817         ring->desc[ring->next_to_clean].rx.bd_base_info &=
3818                 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
3819         ring->next_to_clean += 1;
3820
3821         if (unlikely(ring->next_to_clean == ring->desc_num))
3822                 ring->next_to_clean = 0;
3823 }
3824
3825 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
3826                           unsigned char *va)
3827 {
3828         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
3829         struct net_device *netdev = ring_to_netdev(ring);
3830         struct sk_buff *skb;
3831
3832         ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
3833         skb = ring->skb;
3834         if (unlikely(!skb)) {
3835                 hns3_rl_err(netdev, "alloc rx skb fail\n");
3836
3837                 u64_stats_update_begin(&ring->syncp);
3838                 ring->stats.sw_err_cnt++;
3839                 u64_stats_update_end(&ring->syncp);
3840
3841                 return -ENOMEM;
3842         }
3843
3844         trace_hns3_rx_desc(ring);
3845         prefetchw(skb->data);
3846
3847         ring->pending_buf = 1;
3848         ring->frag_num = 0;
3849         ring->tail_skb = NULL;
3850         if (length <= HNS3_RX_HEAD_SIZE) {
3851                 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
3852
3853                 /* We can reuse buffer as-is, just make sure it is reusable */
3854                 if (dev_page_is_reusable(desc_cb->priv))
3855                         desc_cb->reuse_flag = 1;
3856                 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
3857                         page_pool_put_full_page(ring->page_pool, desc_cb->priv,
3858                                                 false);
3859                 else /* This page cannot be reused so discard it */
3860                         __page_frag_cache_drain(desc_cb->priv,
3861                                                 desc_cb->pagecnt_bias);
3862
3863                 hns3_rx_ring_move_fw(ring);
3864                 return 0;
3865         }
3866
3867         if (ring->page_pool)
3868                 skb_mark_for_recycle(skb);
3869
3870         u64_stats_update_begin(&ring->syncp);
3871         ring->stats.seg_pkt_cnt++;
3872         u64_stats_update_end(&ring->syncp);
3873
3874         ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
3875         __skb_put(skb, ring->pull_len);
3876         hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
3877                             desc_cb);
3878         hns3_rx_ring_move_fw(ring);
3879
3880         return 0;
3881 }
3882
3883 static int hns3_add_frag(struct hns3_enet_ring *ring)
3884 {
3885         struct sk_buff *skb = ring->skb;
3886         struct sk_buff *head_skb = skb;
3887         struct sk_buff *new_skb;
3888         struct hns3_desc_cb *desc_cb;
3889         struct hns3_desc *desc;
3890         u32 bd_base_info;
3891
3892         do {
3893                 desc = &ring->desc[ring->next_to_clean];
3894                 desc_cb = &ring->desc_cb[ring->next_to_clean];
3895                 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3896                 /* make sure HW write desc complete */
3897                 dma_rmb();
3898                 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
3899                         return -ENXIO;
3900
3901                 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
3902                         new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
3903                         if (unlikely(!new_skb)) {
3904                                 hns3_rl_err(ring_to_netdev(ring),
3905                                             "alloc rx fraglist skb fail\n");
3906                                 return -ENXIO;
3907                         }
3908
3909                         if (ring->page_pool)
3910                                 skb_mark_for_recycle(new_skb);
3911
3912                         ring->frag_num = 0;
3913
3914                         if (ring->tail_skb) {
3915                                 ring->tail_skb->next = new_skb;
3916                                 ring->tail_skb = new_skb;
3917                         } else {
3918                                 skb_shinfo(skb)->frag_list = new_skb;
3919                                 ring->tail_skb = new_skb;
3920                         }
3921                 }
3922
3923                 if (ring->tail_skb) {
3924                         head_skb->truesize += hns3_buf_size(ring);
3925                         head_skb->data_len += le16_to_cpu(desc->rx.size);
3926                         head_skb->len += le16_to_cpu(desc->rx.size);
3927                         skb = ring->tail_skb;
3928                 }
3929
3930                 dma_sync_single_for_cpu(ring_to_dev(ring),
3931                                 desc_cb->dma + desc_cb->page_offset,
3932                                 hns3_buf_size(ring),
3933                                 DMA_FROM_DEVICE);
3934
3935                 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
3936                 trace_hns3_rx_desc(ring);
3937                 hns3_rx_ring_move_fw(ring);
3938                 ring->pending_buf++;
3939         } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
3940
3941         return 0;
3942 }
3943
3944 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
3945                                      struct sk_buff *skb, u32 l234info,
3946                                      u32 bd_base_info, u32 ol_info, u16 csum)
3947 {
3948         struct net_device *netdev = ring_to_netdev(ring);
3949         struct hns3_nic_priv *priv = netdev_priv(netdev);
3950         u32 l3_type;
3951
3952         skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
3953                                                     HNS3_RXD_GRO_SIZE_M,
3954                                                     HNS3_RXD_GRO_SIZE_S);
3955         /* if there is no HW GRO, do not set gro params */
3956         if (!skb_shinfo(skb)->gso_size) {
3957                 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
3958                                  csum);
3959                 return 0;
3960         }
3961
3962         NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
3963                                                   HNS3_RXD_GRO_COUNT_M,
3964                                                   HNS3_RXD_GRO_COUNT_S);
3965
3966         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
3967                 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3968                                             HNS3_RXD_PTYPE_S);
3969
3970                 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
3971         } else {
3972                 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3973                                           HNS3_RXD_L3ID_S);
3974         }
3975
3976         if (l3_type == HNS3_L3_TYPE_IPV4)
3977                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
3978         else if (l3_type == HNS3_L3_TYPE_IPV6)
3979                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
3980         else
3981                 return -EFAULT;
3982
3983         return  hns3_gro_complete(skb, l234info);
3984 }
3985
3986 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
3987                                      struct sk_buff *skb, u32 rss_hash)
3988 {
3989         struct hnae3_handle *handle = ring->tqp->handle;
3990         enum pkt_hash_types rss_type;
3991
3992         if (rss_hash)
3993                 rss_type = handle->kinfo.rss_type;
3994         else
3995                 rss_type = PKT_HASH_TYPE_NONE;
3996
3997         skb_set_hash(skb, rss_hash, rss_type);
3998 }
3999
4000 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4001 {
4002         struct net_device *netdev = ring_to_netdev(ring);
4003         enum hns3_pkt_l2t_type l2_frame_type;
4004         u32 bd_base_info, l234info, ol_info;
4005         struct hns3_desc *desc;
4006         unsigned int len;
4007         int pre_ntc, ret;
4008         u16 csum;
4009
4010         /* bdinfo handled below is only valid on the last BD of the
4011          * current packet, and ring->next_to_clean indicates the first
4012          * descriptor of next packet, so need - 1 below.
4013          */
4014         pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4015                                         (ring->desc_num - 1);
4016         desc = &ring->desc[pre_ntc];
4017         bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4018         l234info = le32_to_cpu(desc->rx.l234_info);
4019         ol_info = le32_to_cpu(desc->rx.ol_info);
4020         csum = le16_to_cpu(desc->csum);
4021
4022         if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4023                 struct hnae3_handle *h = hns3_get_handle(netdev);
4024                 u32 nsec = le32_to_cpu(desc->ts_nsec);
4025                 u32 sec = le32_to_cpu(desc->ts_sec);
4026
4027                 if (h->ae_algo->ops->get_rx_hwts)
4028                         h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4029         }
4030
4031         /* Based on hw strategy, the tag offloaded will be stored at
4032          * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4033          * in one layer tag case.
4034          */
4035         if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4036                 u16 vlan_tag;
4037
4038                 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4039                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4040                                                vlan_tag);
4041         }
4042
4043         if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4044                                   BIT(HNS3_RXD_L2E_B))))) {
4045                 u64_stats_update_begin(&ring->syncp);
4046                 if (l234info & BIT(HNS3_RXD_L2E_B))
4047                         ring->stats.l2_err++;
4048                 else
4049                         ring->stats.err_pkt_len++;
4050                 u64_stats_update_end(&ring->syncp);
4051
4052                 return -EFAULT;
4053         }
4054
4055         len = skb->len;
4056
4057         /* Do update ip stack process */
4058         skb->protocol = eth_type_trans(skb, netdev);
4059
4060         /* This is needed in order to enable forwarding support */
4061         ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4062                                         bd_base_info, ol_info, csum);
4063         if (unlikely(ret)) {
4064                 u64_stats_update_begin(&ring->syncp);
4065                 ring->stats.rx_err_cnt++;
4066                 u64_stats_update_end(&ring->syncp);
4067                 return ret;
4068         }
4069
4070         l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4071                                         HNS3_RXD_DMAC_S);
4072
4073         u64_stats_update_begin(&ring->syncp);
4074         ring->stats.rx_pkts++;
4075         ring->stats.rx_bytes += len;
4076
4077         if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4078                 ring->stats.rx_multicast++;
4079
4080         u64_stats_update_end(&ring->syncp);
4081
4082         ring->tqp_vector->rx_group.total_bytes += len;
4083
4084         hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
4085         return 0;
4086 }
4087
4088 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4089 {
4090         struct sk_buff *skb = ring->skb;
4091         struct hns3_desc_cb *desc_cb;
4092         struct hns3_desc *desc;
4093         unsigned int length;
4094         u32 bd_base_info;
4095         int ret;
4096
4097         desc = &ring->desc[ring->next_to_clean];
4098         desc_cb = &ring->desc_cb[ring->next_to_clean];
4099
4100         prefetch(desc);
4101
4102         if (!skb) {
4103                 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4104                 /* Check valid BD */
4105                 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4106                         return -ENXIO;
4107
4108                 dma_rmb();
4109                 length = le16_to_cpu(desc->rx.size);
4110
4111                 ring->va = desc_cb->buf + desc_cb->page_offset;
4112
4113                 dma_sync_single_for_cpu(ring_to_dev(ring),
4114                                 desc_cb->dma + desc_cb->page_offset,
4115                                 hns3_buf_size(ring),
4116                                 DMA_FROM_DEVICE);
4117
4118                 /* Prefetch first cache line of first page.
4119                  * Idea is to cache few bytes of the header of the packet.
4120                  * Our L1 Cache line size is 64B so need to prefetch twice to make
4121                  * it 128B. But in actual we can have greater size of caches with
4122                  * 128B Level 1 cache lines. In such a case, single fetch would
4123                  * suffice to cache in the relevant part of the header.
4124                  */
4125                 net_prefetch(ring->va);
4126
4127                 ret = hns3_alloc_skb(ring, length, ring->va);
4128                 skb = ring->skb;
4129
4130                 if (ret < 0) /* alloc buffer fail */
4131                         return ret;
4132                 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4133                         ret = hns3_add_frag(ring);
4134                         if (ret)
4135                                 return ret;
4136                 }
4137         } else {
4138                 ret = hns3_add_frag(ring);
4139                 if (ret)
4140                         return ret;
4141         }
4142
4143         /* As the head data may be changed when GRO enable, copy
4144          * the head data in after other data rx completed
4145          */
4146         if (skb->len > HNS3_RX_HEAD_SIZE)
4147                 memcpy(skb->data, ring->va,
4148                        ALIGN(ring->pull_len, sizeof(long)));
4149
4150         ret = hns3_handle_bdinfo(ring, skb);
4151         if (unlikely(ret)) {
4152                 dev_kfree_skb_any(skb);
4153                 return ret;
4154         }
4155
4156         skb_record_rx_queue(skb, ring->tqp->tqp_index);
4157         return 0;
4158 }
4159
4160 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4161                        void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4162 {
4163 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4164         int unused_count = hns3_desc_unused(ring);
4165         int recv_pkts = 0;
4166         int err;
4167
4168         unused_count -= ring->pending_buf;
4169
4170         while (recv_pkts < budget) {
4171                 /* Reuse or realloc buffers */
4172                 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4173                         hns3_nic_alloc_rx_buffers(ring, unused_count);
4174                         unused_count = hns3_desc_unused(ring) -
4175                                         ring->pending_buf;
4176                 }
4177
4178                 /* Poll one pkt */
4179                 err = hns3_handle_rx_bd(ring);
4180                 /* Do not get FE for the packet or failed to alloc skb */
4181                 if (unlikely(!ring->skb || err == -ENXIO)) {
4182                         goto out;
4183                 } else if (likely(!err)) {
4184                         rx_fn(ring, ring->skb);
4185                         recv_pkts++;
4186                 }
4187
4188                 unused_count += ring->pending_buf;
4189                 ring->skb = NULL;
4190                 ring->pending_buf = 0;
4191         }
4192
4193 out:
4194         /* Make all data has been write before submit */
4195         if (unused_count > 0)
4196                 hns3_nic_alloc_rx_buffers(ring, unused_count);
4197
4198         return recv_pkts;
4199 }
4200
4201 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4202 {
4203         struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4204         struct dim_sample sample = {};
4205
4206         if (!rx_group->coal.adapt_enable)
4207                 return;
4208
4209         dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4210                           rx_group->total_bytes, &sample);
4211         net_dim(&rx_group->dim, sample);
4212 }
4213
4214 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4215 {
4216         struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4217         struct dim_sample sample = {};
4218
4219         if (!tx_group->coal.adapt_enable)
4220                 return;
4221
4222         dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4223                           tx_group->total_bytes, &sample);
4224         net_dim(&tx_group->dim, sample);
4225 }
4226
4227 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4228 {
4229         struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4230         struct hns3_enet_ring *ring;
4231         int rx_pkt_total = 0;
4232
4233         struct hns3_enet_tqp_vector *tqp_vector =
4234                 container_of(napi, struct hns3_enet_tqp_vector, napi);
4235         bool clean_complete = true;
4236         int rx_budget = budget;
4237
4238         if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4239                 napi_complete(napi);
4240                 return 0;
4241         }
4242
4243         /* Since the actual Tx work is minimal, we can give the Tx a larger
4244          * budget and be more aggressive about cleaning up the Tx descriptors.
4245          */
4246         hns3_for_each_ring(ring, tqp_vector->tx_group)
4247                 hns3_clean_tx_ring(ring, budget);
4248
4249         /* make sure rx ring budget not smaller than 1 */
4250         if (tqp_vector->num_tqps > 1)
4251                 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4252
4253         hns3_for_each_ring(ring, tqp_vector->rx_group) {
4254                 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4255                                                     hns3_rx_skb);
4256                 if (rx_cleaned >= rx_budget)
4257                         clean_complete = false;
4258
4259                 rx_pkt_total += rx_cleaned;
4260         }
4261
4262         tqp_vector->rx_group.total_packets += rx_pkt_total;
4263
4264         if (!clean_complete)
4265                 return budget;
4266
4267         if (napi_complete(napi) &&
4268             likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4269                 hns3_update_rx_int_coalesce(tqp_vector);
4270                 hns3_update_tx_int_coalesce(tqp_vector);
4271
4272                 hns3_mask_vector_irq(tqp_vector, 1);
4273         }
4274
4275         return rx_pkt_total;
4276 }
4277
4278 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4279                                       struct hnae3_ring_chain_node *head)
4280 {
4281         struct pci_dev *pdev = tqp_vector->handle->pdev;
4282         struct hnae3_ring_chain_node *cur_chain = head;
4283         struct hnae3_ring_chain_node *chain;
4284         struct hns3_enet_ring *tx_ring;
4285         struct hns3_enet_ring *rx_ring;
4286
4287         tx_ring = tqp_vector->tx_group.ring;
4288         if (tx_ring) {
4289                 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
4290                 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4291                               HNAE3_RING_TYPE_TX);
4292                 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4293                                 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
4294
4295                 cur_chain->next = NULL;
4296
4297                 while (tx_ring->next) {
4298                         tx_ring = tx_ring->next;
4299
4300                         chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
4301                                              GFP_KERNEL);
4302                         if (!chain)
4303                                 goto err_free_chain;
4304
4305                         cur_chain->next = chain;
4306                         chain->tqp_index = tx_ring->tqp->tqp_index;
4307                         hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4308                                       HNAE3_RING_TYPE_TX);
4309                         hnae3_set_field(chain->int_gl_idx,
4310                                         HNAE3_RING_GL_IDX_M,
4311                                         HNAE3_RING_GL_IDX_S,
4312                                         HNAE3_RING_GL_TX);
4313
4314                         cur_chain = chain;
4315                 }
4316         }
4317
4318         rx_ring = tqp_vector->rx_group.ring;
4319         if (!tx_ring && rx_ring) {
4320                 cur_chain->next = NULL;
4321                 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
4322                 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4323                               HNAE3_RING_TYPE_RX);
4324                 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4325                                 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
4326
4327                 rx_ring = rx_ring->next;
4328         }
4329
4330         while (rx_ring) {
4331                 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4332                 if (!chain)
4333                         goto err_free_chain;
4334
4335                 cur_chain->next = chain;
4336                 chain->tqp_index = rx_ring->tqp->tqp_index;
4337                 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4338                               HNAE3_RING_TYPE_RX);
4339                 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4340                                 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
4341
4342                 cur_chain = chain;
4343
4344                 rx_ring = rx_ring->next;
4345         }
4346
4347         return 0;
4348
4349 err_free_chain:
4350         cur_chain = head->next;
4351         while (cur_chain) {
4352                 chain = cur_chain->next;
4353                 devm_kfree(&pdev->dev, cur_chain);
4354                 cur_chain = chain;
4355         }
4356         head->next = NULL;
4357
4358         return -ENOMEM;
4359 }
4360
4361 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4362                                         struct hnae3_ring_chain_node *head)
4363 {
4364         struct pci_dev *pdev = tqp_vector->handle->pdev;
4365         struct hnae3_ring_chain_node *chain_tmp, *chain;
4366
4367         chain = head->next;
4368
4369         while (chain) {
4370                 chain_tmp = chain->next;
4371                 devm_kfree(&pdev->dev, chain);
4372                 chain = chain_tmp;
4373         }
4374 }
4375
4376 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4377                                    struct hns3_enet_ring *ring)
4378 {
4379         ring->next = group->ring;
4380         group->ring = ring;
4381
4382         group->count++;
4383 }
4384
4385 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4386 {
4387         struct pci_dev *pdev = priv->ae_handle->pdev;
4388         struct hns3_enet_tqp_vector *tqp_vector;
4389         int num_vectors = priv->vector_num;
4390         int numa_node;
4391         int vector_i;
4392
4393         numa_node = dev_to_node(&pdev->dev);
4394
4395         for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4396                 tqp_vector = &priv->tqp_vector[vector_i];
4397                 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4398                                 &tqp_vector->affinity_mask);
4399         }
4400 }
4401
4402 static void hns3_rx_dim_work(struct work_struct *work)
4403 {
4404         struct dim *dim = container_of(work, struct dim, work);
4405         struct hns3_enet_ring_group *group = container_of(dim,
4406                 struct hns3_enet_ring_group, dim);
4407         struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4408         struct dim_cq_moder cur_moder =
4409                 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4410
4411         hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4412         tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4413
4414         if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4415                 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4416                 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4417         }
4418
4419         dim->state = DIM_START_MEASURE;
4420 }
4421
4422 static void hns3_tx_dim_work(struct work_struct *work)
4423 {
4424         struct dim *dim = container_of(work, struct dim, work);
4425         struct hns3_enet_ring_group *group = container_of(dim,
4426                 struct hns3_enet_ring_group, dim);
4427         struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4428         struct dim_cq_moder cur_moder =
4429                 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4430
4431         hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4432         tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4433
4434         if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4435                 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4436                 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4437         }
4438
4439         dim->state = DIM_START_MEASURE;
4440 }
4441
4442 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4443 {
4444         INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4445         INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4446 }
4447
4448 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4449 {
4450         struct hnae3_handle *h = priv->ae_handle;
4451         struct hns3_enet_tqp_vector *tqp_vector;
4452         int ret;
4453         int i;
4454
4455         hns3_nic_set_cpumask(priv);
4456
4457         for (i = 0; i < priv->vector_num; i++) {
4458                 tqp_vector = &priv->tqp_vector[i];
4459                 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4460                 tqp_vector->num_tqps = 0;
4461                 hns3_nic_init_dim(tqp_vector);
4462         }
4463
4464         for (i = 0; i < h->kinfo.num_tqps; i++) {
4465                 u16 vector_i = i % priv->vector_num;
4466                 u16 tqp_num = h->kinfo.num_tqps;
4467
4468                 tqp_vector = &priv->tqp_vector[vector_i];
4469
4470                 hns3_add_ring_to_group(&tqp_vector->tx_group,
4471                                        &priv->ring[i]);
4472
4473                 hns3_add_ring_to_group(&tqp_vector->rx_group,
4474                                        &priv->ring[i + tqp_num]);
4475
4476                 priv->ring[i].tqp_vector = tqp_vector;
4477                 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4478                 tqp_vector->num_tqps++;
4479         }
4480
4481         for (i = 0; i < priv->vector_num; i++) {
4482                 struct hnae3_ring_chain_node vector_ring_chain;
4483
4484                 tqp_vector = &priv->tqp_vector[i];
4485
4486                 tqp_vector->rx_group.total_bytes = 0;
4487                 tqp_vector->rx_group.total_packets = 0;
4488                 tqp_vector->tx_group.total_bytes = 0;
4489                 tqp_vector->tx_group.total_packets = 0;
4490                 tqp_vector->handle = h;
4491
4492                 ret = hns3_get_vector_ring_chain(tqp_vector,
4493                                                  &vector_ring_chain);
4494                 if (ret)
4495                         goto map_ring_fail;
4496
4497                 ret = h->ae_algo->ops->map_ring_to_vector(h,
4498                         tqp_vector->vector_irq, &vector_ring_chain);
4499
4500                 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4501
4502                 if (ret)
4503                         goto map_ring_fail;
4504
4505                 netif_napi_add(priv->netdev, &tqp_vector->napi,
4506                                hns3_nic_common_poll, NAPI_POLL_WEIGHT);
4507         }
4508
4509         return 0;
4510
4511 map_ring_fail:
4512         while (i--)
4513                 netif_napi_del(&priv->tqp_vector[i].napi);
4514
4515         return ret;
4516 }
4517
4518 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4519 {
4520         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4521         struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4522         struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4523
4524         /* initialize the configuration for interrupt coalescing.
4525          * 1. GL (Interrupt Gap Limiter)
4526          * 2. RL (Interrupt Rate Limiter)
4527          * 3. QL (Interrupt Quantity Limiter)
4528          *
4529          * Default: enable interrupt coalescing self-adaptive and GL
4530          */
4531         tx_coal->adapt_enable = 1;
4532         rx_coal->adapt_enable = 1;
4533
4534         tx_coal->int_gl = HNS3_INT_GL_50K;
4535         rx_coal->int_gl = HNS3_INT_GL_50K;
4536
4537         rx_coal->flow_level = HNS3_FLOW_LOW;
4538         tx_coal->flow_level = HNS3_FLOW_LOW;
4539
4540         if (ae_dev->dev_specs.int_ql_max) {
4541                 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4542                 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4543         }
4544 }
4545
4546 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4547 {
4548         struct hnae3_handle *h = priv->ae_handle;
4549         struct hns3_enet_tqp_vector *tqp_vector;
4550         struct hnae3_vector_info *vector;
4551         struct pci_dev *pdev = h->pdev;
4552         u16 tqp_num = h->kinfo.num_tqps;
4553         u16 vector_num;
4554         int ret = 0;
4555         u16 i;
4556
4557         /* RSS size, cpu online and vector_num should be the same */
4558         /* Should consider 2p/4p later */
4559         vector_num = min_t(u16, num_online_cpus(), tqp_num);
4560
4561         vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4562                               GFP_KERNEL);
4563         if (!vector)
4564                 return -ENOMEM;
4565
4566         /* save the actual available vector number */
4567         vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4568
4569         priv->vector_num = vector_num;
4570         priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4571                 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4572                              GFP_KERNEL);
4573         if (!priv->tqp_vector) {
4574                 ret = -ENOMEM;
4575                 goto out;
4576         }
4577
4578         for (i = 0; i < priv->vector_num; i++) {
4579                 tqp_vector = &priv->tqp_vector[i];
4580                 tqp_vector->idx = i;
4581                 tqp_vector->mask_addr = vector[i].io_addr;
4582                 tqp_vector->vector_irq = vector[i].vector;
4583                 hns3_vector_coalesce_init(tqp_vector, priv);
4584         }
4585
4586 out:
4587         devm_kfree(&pdev->dev, vector);
4588         return ret;
4589 }
4590
4591 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4592 {
4593         group->ring = NULL;
4594         group->count = 0;
4595 }
4596
4597 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4598 {
4599         struct hnae3_ring_chain_node vector_ring_chain;
4600         struct hnae3_handle *h = priv->ae_handle;
4601         struct hns3_enet_tqp_vector *tqp_vector;
4602         int i;
4603
4604         for (i = 0; i < priv->vector_num; i++) {
4605                 tqp_vector = &priv->tqp_vector[i];
4606
4607                 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4608                         continue;
4609
4610                 /* Since the mapping can be overwritten, when fail to get the
4611                  * chain between vector and ring, we should go on to deal with
4612                  * the remaining options.
4613                  */
4614                 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
4615                         dev_warn(priv->dev, "failed to get ring chain\n");
4616
4617                 h->ae_algo->ops->unmap_ring_from_vector(h,
4618                         tqp_vector->vector_irq, &vector_ring_chain);
4619
4620                 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4621
4622                 hns3_clear_ring_group(&tqp_vector->rx_group);
4623                 hns3_clear_ring_group(&tqp_vector->tx_group);
4624                 netif_napi_del(&priv->tqp_vector[i].napi);
4625         }
4626 }
4627
4628 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4629 {
4630         struct hnae3_handle *h = priv->ae_handle;
4631         struct pci_dev *pdev = h->pdev;
4632         int i, ret;
4633
4634         for (i = 0; i < priv->vector_num; i++) {
4635                 struct hns3_enet_tqp_vector *tqp_vector;
4636
4637                 tqp_vector = &priv->tqp_vector[i];
4638                 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4639                 if (ret)
4640                         return;
4641         }
4642
4643         devm_kfree(&pdev->dev, priv->tqp_vector);
4644 }
4645
4646 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4647                               unsigned int ring_type)
4648 {
4649         int queue_num = priv->ae_handle->kinfo.num_tqps;
4650         struct hns3_enet_ring *ring;
4651         int desc_num;
4652
4653         if (ring_type == HNAE3_RING_TYPE_TX) {
4654                 ring = &priv->ring[q->tqp_index];
4655                 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4656                 ring->queue_index = q->tqp_index;
4657                 ring->tx_copybreak = priv->tx_copybreak;
4658                 ring->last_to_use = 0;
4659         } else {
4660                 ring = &priv->ring[q->tqp_index + queue_num];
4661                 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4662                 ring->queue_index = q->tqp_index;
4663                 ring->rx_copybreak = priv->rx_copybreak;
4664         }
4665
4666         hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4667
4668         ring->tqp = q;
4669         ring->desc = NULL;
4670         ring->desc_cb = NULL;
4671         ring->dev = priv->dev;
4672         ring->desc_dma_addr = 0;
4673         ring->buf_size = q->buf_size;
4674         ring->desc_num = desc_num;
4675         ring->next_to_use = 0;
4676         ring->next_to_clean = 0;
4677 }
4678
4679 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4680                                struct hns3_nic_priv *priv)
4681 {
4682         hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4683         hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4684 }
4685
4686 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4687 {
4688         struct hnae3_handle *h = priv->ae_handle;
4689         struct pci_dev *pdev = h->pdev;
4690         int i;
4691
4692         priv->ring = devm_kzalloc(&pdev->dev,
4693                                   array3_size(h->kinfo.num_tqps,
4694                                               sizeof(*priv->ring), 2),
4695                                   GFP_KERNEL);
4696         if (!priv->ring)
4697                 return -ENOMEM;
4698
4699         for (i = 0; i < h->kinfo.num_tqps; i++)
4700                 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4701
4702         return 0;
4703 }
4704
4705 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4706 {
4707         if (!priv->ring)
4708                 return;
4709
4710         devm_kfree(priv->dev, priv->ring);
4711         priv->ring = NULL;
4712 }
4713
4714 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4715 {
4716         struct page_pool_params pp_params = {
4717                 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4718                                 PP_FLAG_DMA_SYNC_DEV,
4719                 .order = hns3_page_order(ring),
4720                 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4721                                 (PAGE_SIZE << hns3_page_order(ring)),
4722                 .nid = dev_to_node(ring_to_dev(ring)),
4723                 .dev = ring_to_dev(ring),
4724                 .dma_dir = DMA_FROM_DEVICE,
4725                 .offset = 0,
4726                 .max_len = PAGE_SIZE << hns3_page_order(ring),
4727         };
4728
4729         ring->page_pool = page_pool_create(&pp_params);
4730         if (IS_ERR(ring->page_pool)) {
4731                 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4732                          PTR_ERR(ring->page_pool));
4733                 ring->page_pool = NULL;
4734         }
4735 }
4736
4737 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4738 {
4739         int ret;
4740
4741         if (ring->desc_num <= 0 || ring->buf_size <= 0)
4742                 return -EINVAL;
4743
4744         ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4745                                      sizeof(ring->desc_cb[0]), GFP_KERNEL);
4746         if (!ring->desc_cb) {
4747                 ret = -ENOMEM;
4748                 goto out;
4749         }
4750
4751         ret = hns3_alloc_desc(ring);
4752         if (ret)
4753                 goto out_with_desc_cb;
4754
4755         if (!HNAE3_IS_TX_RING(ring)) {
4756                 hns3_alloc_page_pool(ring);
4757
4758                 ret = hns3_alloc_ring_buffers(ring);
4759                 if (ret)
4760                         goto out_with_desc;
4761         } else {
4762                 hns3_init_tx_spare_buffer(ring);
4763         }
4764
4765         return 0;
4766
4767 out_with_desc:
4768         hns3_free_desc(ring);
4769 out_with_desc_cb:
4770         devm_kfree(ring_to_dev(ring), ring->desc_cb);
4771         ring->desc_cb = NULL;
4772 out:
4773         return ret;
4774 }
4775
4776 void hns3_fini_ring(struct hns3_enet_ring *ring)
4777 {
4778         hns3_free_desc(ring);
4779         devm_kfree(ring_to_dev(ring), ring->desc_cb);
4780         ring->desc_cb = NULL;
4781         ring->next_to_clean = 0;
4782         ring->next_to_use = 0;
4783         ring->last_to_use = 0;
4784         ring->pending_buf = 0;
4785         if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
4786                 dev_kfree_skb_any(ring->skb);
4787                 ring->skb = NULL;
4788         } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
4789                 struct hns3_tx_spare *tx_spare = ring->tx_spare;
4790
4791                 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
4792                                DMA_TO_DEVICE);
4793                 free_pages((unsigned long)tx_spare->buf,
4794                            get_order(tx_spare->len));
4795                 devm_kfree(ring_to_dev(ring), tx_spare);
4796                 ring->tx_spare = NULL;
4797         }
4798
4799         if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
4800                 page_pool_destroy(ring->page_pool);
4801                 ring->page_pool = NULL;
4802         }
4803 }
4804
4805 static int hns3_buf_size2type(u32 buf_size)
4806 {
4807         int bd_size_type;
4808
4809         switch (buf_size) {
4810         case 512:
4811                 bd_size_type = HNS3_BD_SIZE_512_TYPE;
4812                 break;
4813         case 1024:
4814                 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
4815                 break;
4816         case 2048:
4817                 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4818                 break;
4819         case 4096:
4820                 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
4821                 break;
4822         default:
4823                 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4824         }
4825
4826         return bd_size_type;
4827 }
4828
4829 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
4830 {
4831         dma_addr_t dma = ring->desc_dma_addr;
4832         struct hnae3_queue *q = ring->tqp;
4833
4834         if (!HNAE3_IS_TX_RING(ring)) {
4835                 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
4836                 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
4837                                (u32)((dma >> 31) >> 1));
4838
4839                 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
4840                                hns3_buf_size2type(ring->buf_size));
4841                 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
4842                                ring->desc_num / 8 - 1);
4843         } else {
4844                 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
4845                                (u32)dma);
4846                 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
4847                                (u32)((dma >> 31) >> 1));
4848
4849                 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
4850                                ring->desc_num / 8 - 1);
4851         }
4852 }
4853
4854 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
4855 {
4856         struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
4857         struct hnae3_tc_info *tc_info = &kinfo->tc_info;
4858         int i;
4859
4860         for (i = 0; i < HNAE3_MAX_TC; i++) {
4861                 int j;
4862
4863                 if (!test_bit(i, &tc_info->tc_en))
4864                         continue;
4865
4866                 for (j = 0; j < tc_info->tqp_count[i]; j++) {
4867                         struct hnae3_queue *q;
4868
4869                         q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
4870                         hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
4871                 }
4872         }
4873 }
4874
4875 int hns3_init_all_ring(struct hns3_nic_priv *priv)
4876 {
4877         struct hnae3_handle *h = priv->ae_handle;
4878         int ring_num = h->kinfo.num_tqps * 2;
4879         int i, j;
4880         int ret;
4881
4882         for (i = 0; i < ring_num; i++) {
4883                 ret = hns3_alloc_ring_memory(&priv->ring[i]);
4884                 if (ret) {
4885                         dev_err(priv->dev,
4886                                 "Alloc ring memory fail! ret=%d\n", ret);
4887                         goto out_when_alloc_ring_memory;
4888                 }
4889
4890                 u64_stats_init(&priv->ring[i].syncp);
4891         }
4892
4893         return 0;
4894
4895 out_when_alloc_ring_memory:
4896         for (j = i - 1; j >= 0; j--)
4897                 hns3_fini_ring(&priv->ring[j]);
4898
4899         return -ENOMEM;
4900 }
4901
4902 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
4903 {
4904         struct hnae3_handle *h = priv->ae_handle;
4905         int i;
4906
4907         for (i = 0; i < h->kinfo.num_tqps; i++) {
4908                 hns3_fini_ring(&priv->ring[i]);
4909                 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
4910         }
4911 }
4912
4913 /* Set mac addr if it is configured. or leave it to the AE driver */
4914 static int hns3_init_mac_addr(struct net_device *netdev)
4915 {
4916         struct hns3_nic_priv *priv = netdev_priv(netdev);
4917         struct hnae3_handle *h = priv->ae_handle;
4918         u8 mac_addr_temp[ETH_ALEN];
4919         int ret = 0;
4920
4921         if (h->ae_algo->ops->get_mac_addr)
4922                 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
4923
4924         /* Check if the MAC address is valid, if not get a random one */
4925         if (!is_valid_ether_addr(mac_addr_temp)) {
4926                 eth_hw_addr_random(netdev);
4927                 dev_warn(priv->dev, "using random MAC address %pM\n",
4928                          netdev->dev_addr);
4929         } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
4930                 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
4931                 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
4932         } else {
4933                 return 0;
4934         }
4935
4936         if (h->ae_algo->ops->set_mac_addr)
4937                 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
4938
4939         return ret;
4940 }
4941
4942 static int hns3_init_phy(struct net_device *netdev)
4943 {
4944         struct hnae3_handle *h = hns3_get_handle(netdev);
4945         int ret = 0;
4946
4947         if (h->ae_algo->ops->mac_connect_phy)
4948                 ret = h->ae_algo->ops->mac_connect_phy(h);
4949
4950         return ret;
4951 }
4952
4953 static void hns3_uninit_phy(struct net_device *netdev)
4954 {
4955         struct hnae3_handle *h = hns3_get_handle(netdev);
4956
4957         if (h->ae_algo->ops->mac_disconnect_phy)
4958                 h->ae_algo->ops->mac_disconnect_phy(h);
4959 }
4960
4961 static int hns3_client_start(struct hnae3_handle *handle)
4962 {
4963         if (!handle->ae_algo->ops->client_start)
4964                 return 0;
4965
4966         return handle->ae_algo->ops->client_start(handle);
4967 }
4968
4969 static void hns3_client_stop(struct hnae3_handle *handle)
4970 {
4971         if (!handle->ae_algo->ops->client_stop)
4972                 return;
4973
4974         handle->ae_algo->ops->client_stop(handle);
4975 }
4976
4977 static void hns3_info_show(struct hns3_nic_priv *priv)
4978 {
4979         struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
4980
4981         dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
4982         dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
4983         dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
4984         dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
4985         dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
4986         dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
4987         dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
4988         dev_info(priv->dev, "Total number of enabled TCs: %u\n",
4989                  kinfo->tc_info.num_tc);
4990         dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
4991 }
4992
4993 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
4994                                     enum dim_cq_period_mode mode, bool is_tx)
4995 {
4996         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4997         struct hnae3_handle *handle = priv->ae_handle;
4998         int i;
4999
5000         if (is_tx) {
5001                 priv->tx_cqe_mode = mode;
5002
5003                 for (i = 0; i < priv->vector_num; i++)
5004                         priv->tqp_vector[i].tx_group.dim.mode = mode;
5005         } else {
5006                 priv->rx_cqe_mode = mode;
5007
5008                 for (i = 0; i < priv->vector_num; i++)
5009                         priv->tqp_vector[i].rx_group.dim.mode = mode;
5010         }
5011
5012         /* only device version above V3(include V3), GL can switch CQ/EQ
5013          * period mode.
5014          */
5015         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
5016                 u32 new_mode;
5017                 u64 reg;
5018
5019                 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5020                         HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5021                 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5022
5023                 writel(new_mode, handle->kinfo.io_base + reg);
5024         }
5025 }
5026
5027 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5028                               enum dim_cq_period_mode tx_mode,
5029                               enum dim_cq_period_mode rx_mode)
5030 {
5031         hns3_set_cq_period_mode(priv, tx_mode, true);
5032         hns3_set_cq_period_mode(priv, rx_mode, false);
5033 }
5034
5035 static void hns3_state_init(struct hnae3_handle *handle)
5036 {
5037         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5038         struct net_device *netdev = handle->kinfo.netdev;
5039         struct hns3_nic_priv *priv = netdev_priv(netdev);
5040
5041         set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5042
5043         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5044                 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5045
5046         if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5047                 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5048
5049         if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5050                 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5051 }
5052
5053 static int hns3_client_init(struct hnae3_handle *handle)
5054 {
5055         struct pci_dev *pdev = handle->pdev;
5056         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5057         u16 alloc_tqps, max_rss_size;
5058         struct hns3_nic_priv *priv;
5059         struct net_device *netdev;
5060         int ret;
5061
5062         handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5063                                                     &max_rss_size);
5064         netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5065         if (!netdev)
5066                 return -ENOMEM;
5067
5068         priv = netdev_priv(netdev);
5069         priv->dev = &pdev->dev;
5070         priv->netdev = netdev;
5071         priv->ae_handle = handle;
5072         priv->tx_timeout_count = 0;
5073         priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5074         set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5075
5076         handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5077
5078         handle->kinfo.netdev = netdev;
5079         handle->priv = (void *)priv;
5080
5081         hns3_init_mac_addr(netdev);
5082
5083         hns3_set_default_feature(netdev);
5084
5085         netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5086         netdev->priv_flags |= IFF_UNICAST_FLT;
5087         netdev->netdev_ops = &hns3_nic_netdev_ops;
5088         SET_NETDEV_DEV(netdev, &pdev->dev);
5089         hns3_ethtool_set_ops(netdev);
5090
5091         /* Carrier off reporting is important to ethtool even BEFORE open */
5092         netif_carrier_off(netdev);
5093
5094         ret = hns3_get_ring_config(priv);
5095         if (ret) {
5096                 ret = -ENOMEM;
5097                 goto out_get_ring_cfg;
5098         }
5099
5100         hns3_nic_init_coal_cfg(priv);
5101
5102         ret = hns3_nic_alloc_vector_data(priv);
5103         if (ret) {
5104                 ret = -ENOMEM;
5105                 goto out_alloc_vector_data;
5106         }
5107
5108         ret = hns3_nic_init_vector_data(priv);
5109         if (ret) {
5110                 ret = -ENOMEM;
5111                 goto out_init_vector_data;
5112         }
5113
5114         ret = hns3_init_all_ring(priv);
5115         if (ret) {
5116                 ret = -ENOMEM;
5117                 goto out_init_ring;
5118         }
5119
5120         hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5121                                  DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5122
5123         ret = hns3_init_phy(netdev);
5124         if (ret)
5125                 goto out_init_phy;
5126
5127         /* the device can work without cpu rmap, only aRFS needs it */
5128         ret = hns3_set_rx_cpu_rmap(netdev);
5129         if (ret)
5130                 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5131
5132         ret = hns3_nic_init_irq(priv);
5133         if (ret) {
5134                 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5135                 hns3_free_rx_cpu_rmap(netdev);
5136                 goto out_init_irq_fail;
5137         }
5138
5139         ret = hns3_client_start(handle);
5140         if (ret) {
5141                 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5142                 goto out_client_start;
5143         }
5144
5145         hns3_dcbnl_setup(handle);
5146
5147         ret = hns3_dbg_init(handle);
5148         if (ret) {
5149                 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5150                         ret);
5151                 goto out_client_start;
5152         }
5153
5154         netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5155
5156         hns3_state_init(handle);
5157
5158         ret = register_netdev(netdev);
5159         if (ret) {
5160                 dev_err(priv->dev, "probe register netdev fail!\n");
5161                 goto out_reg_netdev_fail;
5162         }
5163
5164         if (netif_msg_drv(handle))
5165                 hns3_info_show(priv);
5166
5167         return ret;
5168
5169 out_reg_netdev_fail:
5170         hns3_dbg_uninit(handle);
5171 out_client_start:
5172         hns3_free_rx_cpu_rmap(netdev);
5173         hns3_nic_uninit_irq(priv);
5174 out_init_irq_fail:
5175         hns3_uninit_phy(netdev);
5176 out_init_phy:
5177         hns3_uninit_all_ring(priv);
5178 out_init_ring:
5179         hns3_nic_uninit_vector_data(priv);
5180 out_init_vector_data:
5181         hns3_nic_dealloc_vector_data(priv);
5182 out_alloc_vector_data:
5183         priv->ring = NULL;
5184 out_get_ring_cfg:
5185         priv->ae_handle = NULL;
5186         free_netdev(netdev);
5187         return ret;
5188 }
5189
5190 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5191 {
5192         struct net_device *netdev = handle->kinfo.netdev;
5193         struct hns3_nic_priv *priv = netdev_priv(netdev);
5194
5195         if (netdev->reg_state != NETREG_UNINITIALIZED)
5196                 unregister_netdev(netdev);
5197
5198         hns3_client_stop(handle);
5199
5200         hns3_uninit_phy(netdev);
5201
5202         if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5203                 netdev_warn(netdev, "already uninitialized\n");
5204                 goto out_netdev_free;
5205         }
5206
5207         hns3_free_rx_cpu_rmap(netdev);
5208
5209         hns3_nic_uninit_irq(priv);
5210
5211         hns3_clear_all_ring(handle, true);
5212
5213         hns3_nic_uninit_vector_data(priv);
5214
5215         hns3_nic_dealloc_vector_data(priv);
5216
5217         hns3_uninit_all_ring(priv);
5218
5219         hns3_put_ring_config(priv);
5220
5221 out_netdev_free:
5222         hns3_dbg_uninit(handle);
5223         free_netdev(netdev);
5224 }
5225
5226 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5227 {
5228         struct net_device *netdev = handle->kinfo.netdev;
5229
5230         if (!netdev)
5231                 return;
5232
5233         if (linkup) {
5234                 netif_tx_wake_all_queues(netdev);
5235                 netif_carrier_on(netdev);
5236                 if (netif_msg_link(handle))
5237                         netdev_info(netdev, "link up\n");
5238         } else {
5239                 netif_carrier_off(netdev);
5240                 netif_tx_stop_all_queues(netdev);
5241                 if (netif_msg_link(handle))
5242                         netdev_info(netdev, "link down\n");
5243         }
5244 }
5245
5246 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5247 {
5248         while (ring->next_to_clean != ring->next_to_use) {
5249                 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5250                 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5251                 ring_ptr_move_fw(ring, next_to_clean);
5252         }
5253
5254         ring->pending_buf = 0;
5255 }
5256
5257 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5258 {
5259         struct hns3_desc_cb res_cbs;
5260         int ret;
5261
5262         while (ring->next_to_use != ring->next_to_clean) {
5263                 /* When a buffer is not reused, it's memory has been
5264                  * freed in hns3_handle_rx_bd or will be freed by
5265                  * stack, so we need to replace the buffer here.
5266                  */
5267                 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5268                         ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5269                         if (ret) {
5270                                 u64_stats_update_begin(&ring->syncp);
5271                                 ring->stats.sw_err_cnt++;
5272                                 u64_stats_update_end(&ring->syncp);
5273                                 /* if alloc new buffer fail, exit directly
5274                                  * and reclear in up flow.
5275                                  */
5276                                 netdev_warn(ring_to_netdev(ring),
5277                                             "reserve buffer map failed, ret = %d\n",
5278                                             ret);
5279                                 return ret;
5280                         }
5281                         hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5282                 }
5283                 ring_ptr_move_fw(ring, next_to_use);
5284         }
5285
5286         /* Free the pending skb in rx ring */
5287         if (ring->skb) {
5288                 dev_kfree_skb_any(ring->skb);
5289                 ring->skb = NULL;
5290                 ring->pending_buf = 0;
5291         }
5292
5293         return 0;
5294 }
5295
5296 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5297 {
5298         while (ring->next_to_use != ring->next_to_clean) {
5299                 /* When a buffer is not reused, it's memory has been
5300                  * freed in hns3_handle_rx_bd or will be freed by
5301                  * stack, so only need to unmap the buffer here.
5302                  */
5303                 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5304                         hns3_unmap_buffer(ring,
5305                                           &ring->desc_cb[ring->next_to_use]);
5306                         ring->desc_cb[ring->next_to_use].dma = 0;
5307                 }
5308
5309                 ring_ptr_move_fw(ring, next_to_use);
5310         }
5311 }
5312
5313 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5314 {
5315         struct net_device *ndev = h->kinfo.netdev;
5316         struct hns3_nic_priv *priv = netdev_priv(ndev);
5317         u32 i;
5318
5319         for (i = 0; i < h->kinfo.num_tqps; i++) {
5320                 struct hns3_enet_ring *ring;
5321
5322                 ring = &priv->ring[i];
5323                 hns3_clear_tx_ring(ring);
5324
5325                 ring = &priv->ring[i + h->kinfo.num_tqps];
5326                 /* Continue to clear other rings even if clearing some
5327                  * rings failed.
5328                  */
5329                 if (force)
5330                         hns3_force_clear_rx_ring(ring);
5331                 else
5332                         hns3_clear_rx_ring(ring);
5333         }
5334 }
5335
5336 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5337 {
5338         struct net_device *ndev = h->kinfo.netdev;
5339         struct hns3_nic_priv *priv = netdev_priv(ndev);
5340         struct hns3_enet_ring *rx_ring;
5341         int i, j;
5342         int ret;
5343
5344         ret = h->ae_algo->ops->reset_queue(h);
5345         if (ret)
5346                 return ret;
5347
5348         for (i = 0; i < h->kinfo.num_tqps; i++) {
5349                 hns3_init_ring_hw(&priv->ring[i]);
5350
5351                 /* We need to clear tx ring here because self test will
5352                  * use the ring and will not run down before up
5353                  */
5354                 hns3_clear_tx_ring(&priv->ring[i]);
5355                 priv->ring[i].next_to_clean = 0;
5356                 priv->ring[i].next_to_use = 0;
5357                 priv->ring[i].last_to_use = 0;
5358
5359                 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5360                 hns3_init_ring_hw(rx_ring);
5361                 ret = hns3_clear_rx_ring(rx_ring);
5362                 if (ret)
5363                         return ret;
5364
5365                 /* We can not know the hardware head and tail when this
5366                  * function is called in reset flow, so we reuse all desc.
5367                  */
5368                 for (j = 0; j < rx_ring->desc_num; j++)
5369                         hns3_reuse_buffer(rx_ring, j);
5370
5371                 rx_ring->next_to_clean = 0;
5372                 rx_ring->next_to_use = 0;
5373         }
5374
5375         hns3_init_tx_ring_tc(priv);
5376
5377         return 0;
5378 }
5379
5380 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5381 {
5382         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5383         struct net_device *ndev = kinfo->netdev;
5384         struct hns3_nic_priv *priv = netdev_priv(ndev);
5385
5386         if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5387                 return 0;
5388
5389         if (!netif_running(ndev))
5390                 return 0;
5391
5392         return hns3_nic_net_stop(ndev);
5393 }
5394
5395 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5396 {
5397         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5398         struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5399         int ret = 0;
5400
5401         if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5402                 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5403                 return -EFAULT;
5404         }
5405
5406         clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5407
5408         if (netif_running(kinfo->netdev)) {
5409                 ret = hns3_nic_net_open(kinfo->netdev);
5410                 if (ret) {
5411                         set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5412                         netdev_err(kinfo->netdev,
5413                                    "net up fail, ret=%d!\n", ret);
5414                         return ret;
5415                 }
5416         }
5417
5418         return ret;
5419 }
5420
5421 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5422 {
5423         struct net_device *netdev = handle->kinfo.netdev;
5424         struct hns3_nic_priv *priv = netdev_priv(netdev);
5425         int ret;
5426
5427         /* Carrier off reporting is important to ethtool even BEFORE open */
5428         netif_carrier_off(netdev);
5429
5430         ret = hns3_get_ring_config(priv);
5431         if (ret)
5432                 return ret;
5433
5434         ret = hns3_nic_alloc_vector_data(priv);
5435         if (ret)
5436                 goto err_put_ring;
5437
5438         ret = hns3_nic_init_vector_data(priv);
5439         if (ret)
5440                 goto err_dealloc_vector;
5441
5442         ret = hns3_init_all_ring(priv);
5443         if (ret)
5444                 goto err_uninit_vector;
5445
5446         hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5447
5448         /* the device can work without cpu rmap, only aRFS needs it */
5449         ret = hns3_set_rx_cpu_rmap(netdev);
5450         if (ret)
5451                 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5452
5453         ret = hns3_nic_init_irq(priv);
5454         if (ret) {
5455                 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5456                 hns3_free_rx_cpu_rmap(netdev);
5457                 goto err_init_irq_fail;
5458         }
5459
5460         if (!hns3_is_phys_func(handle->pdev))
5461                 hns3_init_mac_addr(netdev);
5462
5463         ret = hns3_client_start(handle);
5464         if (ret) {
5465                 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5466                 goto err_client_start_fail;
5467         }
5468
5469         set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5470
5471         return ret;
5472
5473 err_client_start_fail:
5474         hns3_free_rx_cpu_rmap(netdev);
5475         hns3_nic_uninit_irq(priv);
5476 err_init_irq_fail:
5477         hns3_uninit_all_ring(priv);
5478 err_uninit_vector:
5479         hns3_nic_uninit_vector_data(priv);
5480 err_dealloc_vector:
5481         hns3_nic_dealloc_vector_data(priv);
5482 err_put_ring:
5483         hns3_put_ring_config(priv);
5484
5485         return ret;
5486 }
5487
5488 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5489 {
5490         struct net_device *netdev = handle->kinfo.netdev;
5491         struct hns3_nic_priv *priv = netdev_priv(netdev);
5492
5493         if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5494                 netdev_warn(netdev, "already uninitialized\n");
5495                 return 0;
5496         }
5497
5498         hns3_free_rx_cpu_rmap(netdev);
5499         hns3_nic_uninit_irq(priv);
5500         hns3_clear_all_ring(handle, true);
5501         hns3_reset_tx_queue(priv->ae_handle);
5502
5503         hns3_nic_uninit_vector_data(priv);
5504
5505         hns3_nic_dealloc_vector_data(priv);
5506
5507         hns3_uninit_all_ring(priv);
5508
5509         hns3_put_ring_config(priv);
5510
5511         return 0;
5512 }
5513
5514 static int hns3_reset_notify(struct hnae3_handle *handle,
5515                              enum hnae3_reset_notify_type type)
5516 {
5517         int ret = 0;
5518
5519         switch (type) {
5520         case HNAE3_UP_CLIENT:
5521                 ret = hns3_reset_notify_up_enet(handle);
5522                 break;
5523         case HNAE3_DOWN_CLIENT:
5524                 ret = hns3_reset_notify_down_enet(handle);
5525                 break;
5526         case HNAE3_INIT_CLIENT:
5527                 ret = hns3_reset_notify_init_enet(handle);
5528                 break;
5529         case HNAE3_UNINIT_CLIENT:
5530                 ret = hns3_reset_notify_uninit_enet(handle);
5531                 break;
5532         default:
5533                 break;
5534         }
5535
5536         return ret;
5537 }
5538
5539 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5540                                 bool rxfh_configured)
5541 {
5542         int ret;
5543
5544         ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5545                                                  rxfh_configured);
5546         if (ret) {
5547                 dev_err(&handle->pdev->dev,
5548                         "Change tqp num(%u) fail.\n", new_tqp_num);
5549                 return ret;
5550         }
5551
5552         ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5553         if (ret)
5554                 return ret;
5555
5556         ret =  hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5557         if (ret)
5558                 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5559
5560         return ret;
5561 }
5562
5563 int hns3_set_channels(struct net_device *netdev,
5564                       struct ethtool_channels *ch)
5565 {
5566         struct hnae3_handle *h = hns3_get_handle(netdev);
5567         struct hnae3_knic_private_info *kinfo = &h->kinfo;
5568         bool rxfh_configured = netif_is_rxfh_configured(netdev);
5569         u32 new_tqp_num = ch->combined_count;
5570         u16 org_tqp_num;
5571         int ret;
5572
5573         if (hns3_nic_resetting(netdev))
5574                 return -EBUSY;
5575
5576         if (ch->rx_count || ch->tx_count)
5577                 return -EINVAL;
5578
5579         if (kinfo->tc_info.mqprio_active) {
5580                 dev_err(&netdev->dev,
5581                         "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5582                 return -EINVAL;
5583         }
5584
5585         if (new_tqp_num > hns3_get_max_available_channels(h) ||
5586             new_tqp_num < 1) {
5587                 dev_err(&netdev->dev,
5588                         "Change tqps fail, the tqp range is from 1 to %u",
5589                         hns3_get_max_available_channels(h));
5590                 return -EINVAL;
5591         }
5592
5593         if (kinfo->rss_size == new_tqp_num)
5594                 return 0;
5595
5596         netif_dbg(h, drv, netdev,
5597                   "set channels: tqp_num=%u, rxfh=%d\n",
5598                   new_tqp_num, rxfh_configured);
5599
5600         ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5601         if (ret)
5602                 return ret;
5603
5604         ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5605         if (ret)
5606                 return ret;
5607
5608         org_tqp_num = h->kinfo.num_tqps;
5609         ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5610         if (ret) {
5611                 int ret1;
5612
5613                 netdev_warn(netdev,
5614                             "Change channels fail, revert to old value\n");
5615                 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5616                 if (ret1) {
5617                         netdev_err(netdev,
5618                                    "revert to old channel fail\n");
5619                         return ret1;
5620                 }
5621
5622                 return ret;
5623         }
5624
5625         return 0;
5626 }
5627
5628 static const struct hns3_hw_error_info hns3_hw_err[] = {
5629         { .type = HNAE3_PPU_POISON_ERROR,
5630           .msg = "PPU poison" },
5631         { .type = HNAE3_CMDQ_ECC_ERROR,
5632           .msg = "IMP CMDQ error" },
5633         { .type = HNAE3_IMP_RD_POISON_ERROR,
5634           .msg = "IMP RD poison" },
5635         { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5636           .msg = "ROCEE AXI RESP error" },
5637 };
5638
5639 static void hns3_process_hw_error(struct hnae3_handle *handle,
5640                                   enum hnae3_hw_error_type type)
5641 {
5642         int i;
5643
5644         for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5645                 if (hns3_hw_err[i].type == type) {
5646                         dev_err(&handle->pdev->dev, "Detected %s!\n",
5647                                 hns3_hw_err[i].msg);
5648                         break;
5649                 }
5650         }
5651 }
5652
5653 static const struct hnae3_client_ops client_ops = {
5654         .init_instance = hns3_client_init,
5655         .uninit_instance = hns3_client_uninit,
5656         .link_status_change = hns3_link_status_change,
5657         .reset_notify = hns3_reset_notify,
5658         .process_hw_error = hns3_process_hw_error,
5659 };
5660
5661 /* hns3_init_module - Driver registration routine
5662  * hns3_init_module is the first routine called when the driver is
5663  * loaded. All it does is register with the PCI subsystem.
5664  */
5665 static int __init hns3_init_module(void)
5666 {
5667         int ret;
5668
5669         pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5670         pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5671
5672         client.type = HNAE3_CLIENT_KNIC;
5673         snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
5674                  hns3_driver_name);
5675
5676         client.ops = &client_ops;
5677
5678         INIT_LIST_HEAD(&client.node);
5679
5680         hns3_dbg_register_debugfs(hns3_driver_name);
5681
5682         ret = hnae3_register_client(&client);
5683         if (ret)
5684                 goto err_reg_client;
5685
5686         ret = pci_register_driver(&hns3_driver);
5687         if (ret)
5688                 goto err_reg_driver;
5689
5690         return ret;
5691
5692 err_reg_driver:
5693         hnae3_unregister_client(&client);
5694 err_reg_client:
5695         hns3_dbg_unregister_debugfs();
5696         return ret;
5697 }
5698 module_init(hns3_init_module);
5699
5700 /* hns3_exit_module - Driver exit cleanup routine
5701  * hns3_exit_module is called just before the driver is removed
5702  * from memory.
5703  */
5704 static void __exit hns3_exit_module(void)
5705 {
5706         pci_unregister_driver(&hns3_driver);
5707         hnae3_unregister_client(&client);
5708         hns3_dbg_unregister_debugfs();
5709 }
5710 module_exit(hns3_exit_module);
5711
5712 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
5713 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5714 MODULE_LICENSE("GPL");
5715 MODULE_ALIAS("pci:hns-nic");