1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
10 #include <linux/if_vlan.h>
12 #include <linux/ipv6.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/aer.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
18 #include <linux/vermagic.h>
20 #include <net/ip6_checksum.h>
21 #include <net/pkt_cls.h>
23 #include <net/vxlan.h>
26 #include "hns3_enet.h"
27 /* All hns3 tracepoints are defined by the include below, which
28 * must be included exactly once across the whole kernel with
29 * CREATE_TRACE_POINTS defined
31 #define CREATE_TRACE_POINTS
32 #include "hns3_trace.h"
34 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
35 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
37 #define hns3_rl_err(fmt, ...) \
39 if (net_ratelimit()) \
40 netdev_err(fmt, ##__VA_ARGS__); \
43 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
44 static void hns3_remove_hw_addr(struct net_device *netdev);
46 static const char hns3_driver_name[] = "hns3";
47 const char hns3_driver_version[] = VERMAGIC_STRING;
48 static const char hns3_driver_string[] =
49 "Hisilicon Ethernet Network Driver for Hip08 Family";
50 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
51 static struct hnae3_client client;
53 static int debug = -1;
54 module_param(debug, int, 0);
55 MODULE_PARM_DESC(debug, " Network interface message level setting");
57 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
58 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
60 #define HNS3_INNER_VLAN_TAG 1
61 #define HNS3_OUTER_VLAN_TAG 2
63 #define HNS3_MIN_TX_LEN 33U
65 /* hns3_pci_tbl - PCI Device ID Table
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static const struct pci_device_id hns3_pci_tbl[] = {
73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
78 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
80 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
82 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
84 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
87 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
88 /* required last entry */
91 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
93 static irqreturn_t hns3_irq_handle(int irq, void *vector)
95 struct hns3_enet_tqp_vector *tqp_vector = vector;
97 napi_schedule_irqoff(&tqp_vector->napi);
102 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
104 struct hns3_enet_tqp_vector *tqp_vectors;
107 for (i = 0; i < priv->vector_num; i++) {
108 tqp_vectors = &priv->tqp_vector[i];
110 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
113 /* clear the affinity mask */
114 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
116 /* release the irq resource */
117 free_irq(tqp_vectors->vector_irq, tqp_vectors);
118 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
122 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
124 struct hns3_enet_tqp_vector *tqp_vectors;
125 int txrx_int_idx = 0;
131 for (i = 0; i < priv->vector_num; i++) {
132 tqp_vectors = &priv->tqp_vector[i];
134 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
137 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
138 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
139 "%s-%s-%s-%d", hns3_driver_name,
140 pci_name(priv->ae_handle->pdev),
141 "TxRx", txrx_int_idx++);
143 } else if (tqp_vectors->rx_group.ring) {
144 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
145 "%s-%s-%s-%d", hns3_driver_name,
146 pci_name(priv->ae_handle->pdev),
148 } else if (tqp_vectors->tx_group.ring) {
149 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
150 "%s-%s-%s-%d", hns3_driver_name,
151 pci_name(priv->ae_handle->pdev),
154 /* Skip this unused q_vector */
158 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
160 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
161 tqp_vectors->name, tqp_vectors);
163 netdev_err(priv->netdev, "request irq(%d) fail\n",
164 tqp_vectors->vector_irq);
165 hns3_nic_uninit_irq(priv);
169 disable_irq(tqp_vectors->vector_irq);
171 irq_set_affinity_hint(tqp_vectors->vector_irq,
172 &tqp_vectors->affinity_mask);
174 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
180 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
183 writel(mask_en, tqp_vector->mask_addr);
186 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
188 napi_enable(&tqp_vector->napi);
189 enable_irq(tqp_vector->vector_irq);
192 hns3_mask_vector_irq(tqp_vector, 1);
195 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
198 hns3_mask_vector_irq(tqp_vector, 0);
200 disable_irq(tqp_vector->vector_irq);
201 napi_disable(&tqp_vector->napi);
204 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
207 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
209 /* this defines the configuration for RL (Interrupt Rate Limiter).
210 * Rl defines rate of interrupts i.e. number of interrupts-per-second
211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
214 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
215 !tqp_vector->rx_group.coal.gl_adapt_enable)
216 /* According to the hardware, the range of rl_reg is
217 * 0-59 and the unit is 4.
219 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
221 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
224 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
227 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
229 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
232 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
235 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
237 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
240 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
241 struct hns3_nic_priv *priv)
243 /* initialize the configuration for interrupt coalescing.
244 * 1. GL (Interrupt Gap Limiter)
245 * 2. RL (Interrupt Rate Limiter)
247 * Default: enable interrupt coalescing self-adaptive and GL
249 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
250 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
252 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
253 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
255 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
256 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
259 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
260 struct hns3_nic_priv *priv)
262 struct hnae3_handle *h = priv->ae_handle;
264 hns3_set_vector_coalesce_tx_gl(tqp_vector,
265 tqp_vector->tx_group.coal.int_gl);
266 hns3_set_vector_coalesce_rx_gl(tqp_vector,
267 tqp_vector->rx_group.coal.int_gl);
268 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
271 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
273 struct hnae3_handle *h = hns3_get_handle(netdev);
274 struct hnae3_knic_private_info *kinfo = &h->kinfo;
275 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
278 if (kinfo->num_tc <= 1) {
279 netdev_reset_tc(netdev);
281 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
284 "netdev_set_num_tc fail, ret=%d!\n", ret);
288 for (i = 0; i < HNAE3_MAX_TC; i++) {
289 if (!kinfo->tc_info[i].enable)
292 netdev_set_tc_queue(netdev,
293 kinfo->tc_info[i].tc,
294 kinfo->tc_info[i].tqp_count,
295 kinfo->tc_info[i].tqp_offset);
299 ret = netif_set_real_num_tx_queues(netdev, queue_size);
302 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
306 ret = netif_set_real_num_rx_queues(netdev, queue_size);
309 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
316 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
318 u16 alloc_tqps, max_rss_size, rss_size;
320 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
321 rss_size = alloc_tqps / h->kinfo.num_tc;
323 return min_t(u16, rss_size, max_rss_size);
326 static void hns3_tqp_enable(struct hnae3_queue *tqp)
330 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
331 rcb_reg |= BIT(HNS3_RING_EN_B);
332 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
335 static void hns3_tqp_disable(struct hnae3_queue *tqp)
339 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
340 rcb_reg &= ~BIT(HNS3_RING_EN_B);
341 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
344 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
346 #ifdef CONFIG_RFS_ACCEL
347 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
348 netdev->rx_cpu_rmap = NULL;
352 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
354 #ifdef CONFIG_RFS_ACCEL
355 struct hns3_nic_priv *priv = netdev_priv(netdev);
356 struct hns3_enet_tqp_vector *tqp_vector;
359 if (!netdev->rx_cpu_rmap) {
360 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
361 if (!netdev->rx_cpu_rmap)
365 for (i = 0; i < priv->vector_num; i++) {
366 tqp_vector = &priv->tqp_vector[i];
367 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
368 tqp_vector->vector_irq);
370 hns3_free_rx_cpu_rmap(netdev);
378 static int hns3_nic_net_up(struct net_device *netdev)
380 struct hns3_nic_priv *priv = netdev_priv(netdev);
381 struct hnae3_handle *h = priv->ae_handle;
385 ret = hns3_nic_reset_all_ring(h);
389 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
391 /* enable the vectors */
392 for (i = 0; i < priv->vector_num; i++)
393 hns3_vector_enable(&priv->tqp_vector[i]);
396 for (j = 0; j < h->kinfo.num_tqps; j++)
397 hns3_tqp_enable(h->kinfo.tqp[j]);
399 /* start the ae_dev */
400 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
402 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
404 hns3_tqp_disable(h->kinfo.tqp[j]);
406 for (j = i - 1; j >= 0; j--)
407 hns3_vector_disable(&priv->tqp_vector[j]);
413 static void hns3_config_xps(struct hns3_nic_priv *priv)
417 for (i = 0; i < priv->vector_num; i++) {
418 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
419 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
424 ret = netif_set_xps_queue(priv->netdev,
425 &tqp_vector->affinity_mask,
426 ring->tqp->tqp_index);
428 netdev_warn(priv->netdev,
429 "set xps queue failed: %d", ret);
436 static int hns3_nic_net_open(struct net_device *netdev)
438 struct hns3_nic_priv *priv = netdev_priv(netdev);
439 struct hnae3_handle *h = hns3_get_handle(netdev);
440 struct hnae3_knic_private_info *kinfo;
443 if (hns3_nic_resetting(netdev))
446 netif_carrier_off(netdev);
448 ret = hns3_nic_set_real_num_queue(netdev);
452 ret = hns3_nic_net_up(netdev);
454 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
459 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
460 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
462 if (h->ae_algo->ops->set_timer_task)
463 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
465 hns3_config_xps(priv);
467 netif_dbg(h, drv, netdev, "net open\n");
472 static void hns3_reset_tx_queue(struct hnae3_handle *h)
474 struct net_device *ndev = h->kinfo.netdev;
475 struct hns3_nic_priv *priv = netdev_priv(ndev);
476 struct netdev_queue *dev_queue;
479 for (i = 0; i < h->kinfo.num_tqps; i++) {
480 dev_queue = netdev_get_tx_queue(ndev,
481 priv->ring[i].queue_index);
482 netdev_tx_reset_queue(dev_queue);
486 static void hns3_nic_net_down(struct net_device *netdev)
488 struct hns3_nic_priv *priv = netdev_priv(netdev);
489 struct hnae3_handle *h = hns3_get_handle(netdev);
490 const struct hnae3_ae_ops *ops;
493 /* disable vectors */
494 for (i = 0; i < priv->vector_num; i++)
495 hns3_vector_disable(&priv->tqp_vector[i]);
498 for (i = 0; i < h->kinfo.num_tqps; i++)
499 hns3_tqp_disable(h->kinfo.tqp[i]);
502 ops = priv->ae_handle->ae_algo->ops;
504 ops->stop(priv->ae_handle);
506 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
507 * during reset process, because driver may not be able
508 * to disable the ring through firmware when downing the netdev.
510 if (!hns3_nic_resetting(netdev))
511 hns3_clear_all_ring(priv->ae_handle, false);
513 hns3_reset_tx_queue(priv->ae_handle);
516 static int hns3_nic_net_stop(struct net_device *netdev)
518 struct hns3_nic_priv *priv = netdev_priv(netdev);
519 struct hnae3_handle *h = hns3_get_handle(netdev);
521 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
524 netif_dbg(h, drv, netdev, "net stop\n");
526 if (h->ae_algo->ops->set_timer_task)
527 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
529 netif_tx_stop_all_queues(netdev);
530 netif_carrier_off(netdev);
532 hns3_nic_net_down(netdev);
537 static int hns3_nic_uc_sync(struct net_device *netdev,
538 const unsigned char *addr)
540 struct hnae3_handle *h = hns3_get_handle(netdev);
542 if (h->ae_algo->ops->add_uc_addr)
543 return h->ae_algo->ops->add_uc_addr(h, addr);
548 static int hns3_nic_uc_unsync(struct net_device *netdev,
549 const unsigned char *addr)
551 struct hnae3_handle *h = hns3_get_handle(netdev);
553 if (h->ae_algo->ops->rm_uc_addr)
554 return h->ae_algo->ops->rm_uc_addr(h, addr);
559 static int hns3_nic_mc_sync(struct net_device *netdev,
560 const unsigned char *addr)
562 struct hnae3_handle *h = hns3_get_handle(netdev);
564 if (h->ae_algo->ops->add_mc_addr)
565 return h->ae_algo->ops->add_mc_addr(h, addr);
570 static int hns3_nic_mc_unsync(struct net_device *netdev,
571 const unsigned char *addr)
573 struct hnae3_handle *h = hns3_get_handle(netdev);
575 if (h->ae_algo->ops->rm_mc_addr)
576 return h->ae_algo->ops->rm_mc_addr(h, addr);
581 static u8 hns3_get_netdev_flags(struct net_device *netdev)
585 if (netdev->flags & IFF_PROMISC) {
586 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
588 flags |= HNAE3_VLAN_FLTR;
589 if (netdev->flags & IFF_ALLMULTI)
590 flags |= HNAE3_USER_MPE;
596 static void hns3_nic_set_rx_mode(struct net_device *netdev)
598 struct hnae3_handle *h = hns3_get_handle(netdev);
602 new_flags = hns3_get_netdev_flags(netdev);
604 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
606 netdev_err(netdev, "sync uc address fail\n");
608 new_flags |= HNAE3_OVERFLOW_UPE;
611 if (netdev->flags & IFF_MULTICAST) {
612 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
615 netdev_err(netdev, "sync mc address fail\n");
617 new_flags |= HNAE3_OVERFLOW_MPE;
621 /* User mode Promisc mode enable and vlan filtering is disabled to
622 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
623 * vlan fitering is enabled
625 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
626 h->netdev_flags = new_flags;
627 hns3_update_promisc_mode(netdev, new_flags);
630 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
632 struct hns3_nic_priv *priv = netdev_priv(netdev);
633 struct hnae3_handle *h = priv->ae_handle;
635 if (h->ae_algo->ops->set_promisc_mode) {
636 return h->ae_algo->ops->set_promisc_mode(h,
637 promisc_flags & HNAE3_UPE,
638 promisc_flags & HNAE3_MPE);
644 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
646 struct hns3_nic_priv *priv = netdev_priv(netdev);
647 struct hnae3_handle *h = priv->ae_handle;
650 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
651 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
652 if (enable != last_state) {
655 enable ? "enable" : "disable");
656 h->ae_algo->ops->enable_vlan_filter(h, enable);
661 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
662 u16 *mss, u32 *type_cs_vlan_tso)
664 u32 l4_offset, hdr_len;
665 union l3_hdr_info l3;
666 union l4_hdr_info l4;
670 if (!skb_is_gso(skb))
673 ret = skb_cow_head(skb, 0);
674 if (unlikely(ret < 0))
677 l3.hdr = skb_network_header(skb);
678 l4.hdr = skb_transport_header(skb);
680 /* Software should clear the IPv4's checksum field when tso is
683 if (l3.v4->version == 4)
687 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
690 SKB_GSO_UDP_TUNNEL_CSUM)) {
691 if ((!(skb_shinfo(skb)->gso_type &
693 (skb_shinfo(skb)->gso_type &
694 SKB_GSO_UDP_TUNNEL_CSUM)) {
695 /* Software should clear the udp's checksum
696 * field when tso is needed.
700 /* reset l3&l4 pointers from outer to inner headers */
701 l3.hdr = skb_inner_network_header(skb);
702 l4.hdr = skb_inner_transport_header(skb);
704 /* Software should clear the IPv4's checksum field when
707 if (l3.v4->version == 4)
711 /* normal or tunnel packet */
712 l4_offset = l4.hdr - skb->data;
713 hdr_len = (l4.tcp->doff << 2) + l4_offset;
715 /* remove payload length from inner pseudo checksum when tso */
716 l4_paylen = skb->len - l4_offset;
717 csum_replace_by_diff(&l4.tcp->check,
718 (__force __wsum)htonl(l4_paylen));
720 /* find the txbd field values */
721 *paylen = skb->len - hdr_len;
722 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
724 /* get MSS for TSO */
725 *mss = skb_shinfo(skb)->gso_size;
732 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
735 union l3_hdr_info l3;
736 unsigned char *l4_hdr;
737 unsigned char *exthdr;
741 /* find outer header point */
742 l3.hdr = skb_network_header(skb);
743 l4_hdr = skb_transport_header(skb);
745 if (skb->protocol == htons(ETH_P_IPV6)) {
746 exthdr = l3.hdr + sizeof(*l3.v6);
747 l4_proto_tmp = l3.v6->nexthdr;
748 if (l4_hdr != exthdr)
749 ipv6_skip_exthdr(skb, exthdr - skb->data,
750 &l4_proto_tmp, &frag_off);
751 } else if (skb->protocol == htons(ETH_P_IP)) {
752 l4_proto_tmp = l3.v4->protocol;
757 *ol4_proto = l4_proto_tmp;
760 if (!skb->encapsulation) {
765 /* find inner header point */
766 l3.hdr = skb_inner_network_header(skb);
767 l4_hdr = skb_inner_transport_header(skb);
769 if (l3.v6->version == 6) {
770 exthdr = l3.hdr + sizeof(*l3.v6);
771 l4_proto_tmp = l3.v6->nexthdr;
772 if (l4_hdr != exthdr)
773 ipv6_skip_exthdr(skb, exthdr - skb->data,
774 &l4_proto_tmp, &frag_off);
775 } else if (l3.v4->version == 4) {
776 l4_proto_tmp = l3.v4->protocol;
779 *il4_proto = l4_proto_tmp;
784 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
785 * and it is udp packet, which has a dest port as the IANA assigned.
786 * the hardware is expected to do the checksum offload, but the
787 * hardware will not do the checksum offload when udp dest port is
790 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
792 union l4_hdr_info l4;
794 l4.hdr = skb_transport_header(skb);
796 if (!(!skb->encapsulation &&
797 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
800 skb_checksum_help(skb);
805 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
806 u32 *ol_type_vlan_len_msec)
808 u32 l2_len, l3_len, l4_len;
809 unsigned char *il2_hdr;
810 union l3_hdr_info l3;
811 union l4_hdr_info l4;
813 l3.hdr = skb_network_header(skb);
814 l4.hdr = skb_transport_header(skb);
816 /* compute OL2 header size, defined in 2 Bytes */
817 l2_len = l3.hdr - skb->data;
818 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
820 /* compute OL3 header size, defined in 4 Bytes */
821 l3_len = l4.hdr - l3.hdr;
822 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
824 il2_hdr = skb_inner_mac_header(skb);
825 /* compute OL4 header size, defined in 4 Bytes */
826 l4_len = il2_hdr - l4.hdr;
827 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
829 /* define outer network header type */
830 if (skb->protocol == htons(ETH_P_IP)) {
832 hns3_set_field(*ol_type_vlan_len_msec,
834 HNS3_OL3T_IPV4_CSUM);
836 hns3_set_field(*ol_type_vlan_len_msec,
838 HNS3_OL3T_IPV4_NO_CSUM);
840 } else if (skb->protocol == htons(ETH_P_IPV6)) {
841 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
845 if (ol4_proto == IPPROTO_UDP)
846 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
847 HNS3_TUN_MAC_IN_UDP);
848 else if (ol4_proto == IPPROTO_GRE)
849 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
853 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
854 u8 il4_proto, u32 *type_cs_vlan_tso,
855 u32 *ol_type_vlan_len_msec)
857 unsigned char *l2_hdr = skb->data;
858 u32 l4_proto = ol4_proto;
859 union l4_hdr_info l4;
860 union l3_hdr_info l3;
863 l4.hdr = skb_transport_header(skb);
864 l3.hdr = skb_network_header(skb);
866 /* handle encapsulation skb */
867 if (skb->encapsulation) {
868 /* If this is a not UDP/GRE encapsulation skb */
869 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
870 /* drop the skb tunnel packet if hardware don't support,
871 * because hardware can't calculate csum when TSO.
876 /* the stack computes the IP header already,
877 * driver calculate l4 checksum when not TSO.
879 skb_checksum_help(skb);
883 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
885 /* switch to inner header */
886 l2_hdr = skb_inner_mac_header(skb);
887 l3.hdr = skb_inner_network_header(skb);
888 l4.hdr = skb_inner_transport_header(skb);
889 l4_proto = il4_proto;
892 if (l3.v4->version == 4) {
893 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
896 /* the stack computes the IP header already, the only time we
897 * need the hardware to recompute it is in the case of TSO.
900 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
901 } else if (l3.v6->version == 6) {
902 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
906 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
907 l2_len = l3.hdr - l2_hdr;
908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
910 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
911 l3_len = l4.hdr - l3.hdr;
912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
914 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
917 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
918 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
924 if (hns3_tunnel_csum_bug(skb))
927 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
931 (sizeof(struct udphdr) >> 2));
934 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
935 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
937 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
938 (sizeof(struct sctphdr) >> 2));
941 /* drop the skb tunnel packet if hardware don't support,
942 * because hardware can't calculate csum when TSO.
947 /* the stack computes the IP header already,
948 * driver calculate l4 checksum when not TSO.
950 skb_checksum_help(skb);
957 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
960 struct hnae3_handle *handle = tx_ring->tqp->handle;
961 struct vlan_ethhdr *vhdr;
964 if (!(skb->protocol == htons(ETH_P_8021Q) ||
965 skb_vlan_tag_present(skb)))
968 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
969 * header is allowed in skb, otherwise it will cause RAS error.
971 if (unlikely(skb_vlan_tagged_multi(skb) &&
972 handle->port_base_vlan_state ==
973 HNAE3_PORT_BASE_VLAN_ENABLE))
976 if (skb->protocol == htons(ETH_P_8021Q) &&
977 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
978 /* When HW VLAN acceleration is turned off, and the stack
979 * sets the protocol to 802.1q, the driver just need to
980 * set the protocol to the encapsulated ethertype.
982 skb->protocol = vlan_get_protocol(skb);
986 if (skb_vlan_tag_present(skb)) {
987 /* Based on hw strategy, use out_vtag in two layer tag case,
988 * and use inner_vtag in one tag case.
990 if (skb->protocol == htons(ETH_P_8021Q) &&
991 handle->port_base_vlan_state ==
992 HNAE3_PORT_BASE_VLAN_DISABLE)
993 rc = HNS3_OUTER_VLAN_TAG;
995 rc = HNS3_INNER_VLAN_TAG;
997 skb->protocol = vlan_get_protocol(skb);
1001 rc = skb_cow_head(skb, 0);
1002 if (unlikely(rc < 0))
1005 vhdr = (struct vlan_ethhdr *)skb->data;
1006 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1009 skb->protocol = vlan_get_protocol(skb);
1013 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1014 struct sk_buff *skb, struct hns3_desc *desc)
1016 u32 ol_type_vlan_len_msec = 0;
1017 u32 type_cs_vlan_tso = 0;
1018 u32 paylen = skb->len;
1024 ret = hns3_handle_vtags(ring, skb);
1025 if (unlikely(ret < 0)) {
1026 u64_stats_update_begin(&ring->syncp);
1027 ring->stats.tx_vlan_err++;
1028 u64_stats_update_end(&ring->syncp);
1030 } else if (ret == HNS3_INNER_VLAN_TAG) {
1031 inner_vtag = skb_vlan_tag_get(skb);
1032 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1034 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1035 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1036 out_vtag = skb_vlan_tag_get(skb);
1037 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1039 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1043 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1044 u8 ol4_proto, il4_proto;
1046 skb_reset_mac_len(skb);
1048 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1049 if (unlikely(ret < 0)) {
1050 u64_stats_update_begin(&ring->syncp);
1051 ring->stats.tx_l4_proto_err++;
1052 u64_stats_update_end(&ring->syncp);
1056 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1058 &ol_type_vlan_len_msec);
1059 if (unlikely(ret < 0)) {
1060 u64_stats_update_begin(&ring->syncp);
1061 ring->stats.tx_l2l3l4_err++;
1062 u64_stats_update_end(&ring->syncp);
1066 ret = hns3_set_tso(skb, &paylen, &mss,
1068 if (unlikely(ret < 0)) {
1069 u64_stats_update_begin(&ring->syncp);
1070 ring->stats.tx_tso_err++;
1071 u64_stats_update_end(&ring->syncp);
1077 desc->tx.ol_type_vlan_len_msec =
1078 cpu_to_le32(ol_type_vlan_len_msec);
1079 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1080 desc->tx.paylen = cpu_to_le32(paylen);
1081 desc->tx.mss = cpu_to_le16(mss);
1082 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1083 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1088 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1089 unsigned int size, enum hns_desc_type type)
1091 #define HNS3_LIKELY_BD_NUM 1
1093 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1094 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1095 struct device *dev = ring_to_dev(ring);
1097 unsigned int frag_buf_num;
1101 if (type == DESC_TYPE_SKB) {
1102 struct sk_buff *skb = (struct sk_buff *)priv;
1105 ret = hns3_fill_skb_desc(ring, skb, desc);
1106 if (unlikely(ret < 0))
1109 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1111 frag = (skb_frag_t *)priv;
1112 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1115 if (unlikely(dma_mapping_error(dev, dma))) {
1116 u64_stats_update_begin(&ring->syncp);
1117 ring->stats.sw_err_cnt++;
1118 u64_stats_update_end(&ring->syncp);
1122 desc_cb->length = size;
1124 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1125 desc_cb->priv = priv;
1127 desc_cb->type = type;
1128 desc->addr = cpu_to_le64(dma);
1129 desc->tx.send_size = cpu_to_le16(size);
1130 desc->tx.bdtp_fe_sc_vld_ra_ri =
1131 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1133 trace_hns3_tx_desc(ring, ring->next_to_use);
1134 ring_ptr_move_fw(ring, next_to_use);
1135 return HNS3_LIKELY_BD_NUM;
1138 frag_buf_num = hns3_tx_bd_count(size);
1139 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1140 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1142 /* When frag size is bigger than hardware limit, split this frag */
1143 for (k = 0; k < frag_buf_num; k++) {
1144 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1145 desc_cb->priv = priv;
1146 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1147 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1148 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1150 /* now, fill the descriptor */
1151 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1152 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1153 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1154 desc->tx.bdtp_fe_sc_vld_ra_ri =
1155 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1157 trace_hns3_tx_desc(ring, ring->next_to_use);
1158 /* move ring pointer to next */
1159 ring_ptr_move_fw(ring, next_to_use);
1161 desc_cb = &ring->desc_cb[ring->next_to_use];
1162 desc = &ring->desc[ring->next_to_use];
1165 return frag_buf_num;
1168 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1169 unsigned int bd_num)
1174 size = skb_headlen(skb);
1175 while (size > HNS3_MAX_BD_SIZE) {
1176 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1177 size -= HNS3_MAX_BD_SIZE;
1179 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1184 bd_size[bd_num++] = size;
1185 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1189 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1190 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1191 size = skb_frag_size(frag);
1195 while (size > HNS3_MAX_BD_SIZE) {
1196 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1197 size -= HNS3_MAX_BD_SIZE;
1199 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1203 bd_size[bd_num++] = size;
1204 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1211 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1213 struct sk_buff *frag_skb;
1214 unsigned int bd_num = 0;
1216 /* If the total len is within the max bd limit */
1217 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1218 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1219 return skb_shinfo(skb)->nr_frags + 1U;
1221 /* The below case will always be linearized, return
1222 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1224 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1225 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1226 return HNS3_MAX_TSO_BD_NUM + 1U;
1228 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1230 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1233 skb_walk_frags(skb, frag_skb) {
1234 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1235 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1242 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1244 if (!skb->encapsulation)
1245 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1247 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1250 /* HW need every continuous 8 buffer data to be larger than MSS,
1251 * we simplify it by ensuring skb_headlen + the first continuous
1252 * 7 frags to to be larger than gso header len + mss, and the remaining
1253 * continuous 7 frags to be larger than MSS except the last 7 frags.
1255 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1256 unsigned int bd_num)
1258 unsigned int tot_len = 0;
1261 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1262 tot_len += bd_size[i];
1264 /* ensure the first 8 frags is greater than mss + header */
1265 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1266 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1269 /* ensure every continuous 7 buffer is greater than mss
1270 * except the last one.
1272 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1273 tot_len -= bd_size[i];
1274 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
1276 if (tot_len < skb_shinfo(skb)->gso_size)
1283 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1287 for (i = 0; i < MAX_SKB_FRAGS; i++)
1288 size[i] = skb_frag_size(&shinfo->frags[i]);
1291 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1292 struct net_device *netdev,
1293 struct sk_buff *skb)
1295 struct hns3_nic_priv *priv = netdev_priv(netdev);
1296 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1297 unsigned int bd_num;
1299 bd_num = hns3_tx_bd_num(skb, bd_size);
1300 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1301 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1302 !hns3_skb_need_linearized(skb, bd_size, bd_num)) {
1303 trace_hns3_over_8bd(skb);
1307 if (__skb_linearize(skb))
1310 bd_num = hns3_tx_bd_count(skb->len);
1311 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1312 (!skb_is_gso(skb) &&
1313 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1314 trace_hns3_over_8bd(skb);
1318 u64_stats_update_begin(&ring->syncp);
1319 ring->stats.tx_copy++;
1320 u64_stats_update_end(&ring->syncp);
1324 if (likely(ring_space(ring) >= bd_num))
1327 netif_stop_subqueue(netdev, ring->queue_index);
1328 smp_mb(); /* Memory barrier before checking ring_space */
1330 /* Start queue in case hns3_clean_tx_ring has just made room
1331 * available and has not seen the queue stopped state performed
1332 * by netif_stop_subqueue above.
1334 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1335 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1336 netif_start_subqueue(netdev, ring->queue_index);
1343 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1345 struct device *dev = ring_to_dev(ring);
1348 for (i = 0; i < ring->desc_num; i++) {
1349 /* check if this is where we started */
1350 if (ring->next_to_use == next_to_use_orig)
1354 ring_ptr_move_bw(ring, next_to_use);
1356 /* unmap the descriptor dma address */
1357 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1358 dma_unmap_single(dev,
1359 ring->desc_cb[ring->next_to_use].dma,
1360 ring->desc_cb[ring->next_to_use].length,
1362 else if (ring->desc_cb[ring->next_to_use].length)
1364 ring->desc_cb[ring->next_to_use].dma,
1365 ring->desc_cb[ring->next_to_use].length,
1368 ring->desc_cb[ring->next_to_use].length = 0;
1369 ring->desc_cb[ring->next_to_use].dma = 0;
1373 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1374 struct sk_buff *skb, enum hns_desc_type type)
1376 unsigned int size = skb_headlen(skb);
1377 int i, ret, bd_num = 0;
1380 ret = hns3_fill_desc(ring, skb, size, type);
1381 if (unlikely(ret < 0))
1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1388 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1390 size = skb_frag_size(frag);
1394 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1395 if (unlikely(ret < 0))
1404 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1406 struct hns3_nic_priv *priv = netdev_priv(netdev);
1407 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
1408 struct netdev_queue *dev_queue;
1409 int pre_ntu, next_to_use_head;
1410 struct sk_buff *frag_skb;
1414 /* Hardware can only handle short frames above 32 bytes */
1415 if (skb_put_padto(skb, HNS3_MIN_TX_LEN))
1416 return NETDEV_TX_OK;
1418 /* Prefetch the data used later */
1419 prefetch(skb->data);
1421 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
1422 if (unlikely(ret <= 0)) {
1423 if (ret == -EBUSY) {
1424 u64_stats_update_begin(&ring->syncp);
1425 ring->stats.tx_busy++;
1426 u64_stats_update_end(&ring->syncp);
1427 return NETDEV_TX_BUSY;
1428 } else if (ret == -ENOMEM) {
1429 u64_stats_update_begin(&ring->syncp);
1430 ring->stats.sw_err_cnt++;
1431 u64_stats_update_end(&ring->syncp);
1434 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
1438 next_to_use_head = ring->next_to_use;
1440 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1441 if (unlikely(ret < 0))
1446 if (!skb_has_frag_list(skb))
1449 skb_walk_frags(skb, frag_skb) {
1450 ret = hns3_fill_skb_to_desc(ring, frag_skb, DESC_TYPE_PAGE);
1451 if (unlikely(ret < 0))
1457 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1458 (ring->desc_num - 1);
1459 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1460 cpu_to_le16(BIT(HNS3_TXD_FE_B));
1461 trace_hns3_tx_desc(ring, pre_ntu);
1463 /* Complete translate all packets */
1464 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
1465 netdev_tx_sent_queue(dev_queue, skb->len);
1467 wmb(); /* Commit all data before submit */
1469 hnae3_queue_xmit(ring->tqp, bd_num);
1471 return NETDEV_TX_OK;
1474 hns3_clear_desc(ring, next_to_use_head);
1477 dev_kfree_skb_any(skb);
1478 return NETDEV_TX_OK;
1481 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1483 struct hnae3_handle *h = hns3_get_handle(netdev);
1484 struct sockaddr *mac_addr = p;
1487 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1488 return -EADDRNOTAVAIL;
1490 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1491 netdev_info(netdev, "already using mac address %pM\n",
1496 /* For VF device, if there is a perm_addr, then the user will not
1497 * be allowed to change the address.
1499 if (!hns3_is_phys_func(h->pdev) &&
1500 !is_zero_ether_addr(netdev->perm_addr)) {
1501 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1502 netdev->perm_addr, mac_addr->sa_data);
1506 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1508 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1512 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1517 static int hns3_nic_do_ioctl(struct net_device *netdev,
1518 struct ifreq *ifr, int cmd)
1520 struct hnae3_handle *h = hns3_get_handle(netdev);
1522 if (!netif_running(netdev))
1525 if (!h->ae_algo->ops->do_ioctl)
1528 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1531 static int hns3_nic_set_features(struct net_device *netdev,
1532 netdev_features_t features)
1534 netdev_features_t changed = netdev->features ^ features;
1535 struct hns3_nic_priv *priv = netdev_priv(netdev);
1536 struct hnae3_handle *h = priv->ae_handle;
1540 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1541 enable = !!(features & NETIF_F_GRO_HW);
1542 ret = h->ae_algo->ops->set_gro_en(h, enable);
1547 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1548 h->ae_algo->ops->enable_vlan_filter) {
1549 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1550 h->ae_algo->ops->enable_vlan_filter(h, enable);
1553 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1554 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1555 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1556 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
1561 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1562 enable = !!(features & NETIF_F_NTUPLE);
1563 h->ae_algo->ops->enable_fd(h, enable);
1566 netdev->features = features;
1570 static netdev_features_t hns3_features_check(struct sk_buff *skb,
1571 struct net_device *dev,
1572 netdev_features_t features)
1574 #define HNS3_MAX_HDR_LEN 480U
1575 #define HNS3_MAX_L4_HDR_LEN 60U
1579 if (skb->ip_summed != CHECKSUM_PARTIAL)
1582 if (skb->encapsulation)
1583 len = skb_inner_transport_header(skb) - skb->data;
1585 len = skb_transport_header(skb) - skb->data;
1587 /* Assume L4 is 60 byte as TCP is the only protocol with a
1588 * a flexible value, and it's max len is 60 bytes.
1590 len += HNS3_MAX_L4_HDR_LEN;
1592 /* Hardware only supports checksum on the skb with a max header
1595 if (len > HNS3_MAX_HDR_LEN)
1596 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1601 static void hns3_nic_get_stats64(struct net_device *netdev,
1602 struct rtnl_link_stats64 *stats)
1604 struct hns3_nic_priv *priv = netdev_priv(netdev);
1605 int queue_num = priv->ae_handle->kinfo.num_tqps;
1606 struct hnae3_handle *handle = priv->ae_handle;
1607 struct hns3_enet_ring *ring;
1608 u64 rx_length_errors = 0;
1609 u64 rx_crc_errors = 0;
1610 u64 rx_multicast = 0;
1622 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1625 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1627 for (idx = 0; idx < queue_num; idx++) {
1628 /* fetch the tx stats */
1629 ring = &priv->ring[idx];
1631 start = u64_stats_fetch_begin_irq(&ring->syncp);
1632 tx_bytes += ring->stats.tx_bytes;
1633 tx_pkts += ring->stats.tx_pkts;
1634 tx_drop += ring->stats.sw_err_cnt;
1635 tx_drop += ring->stats.tx_vlan_err;
1636 tx_drop += ring->stats.tx_l4_proto_err;
1637 tx_drop += ring->stats.tx_l2l3l4_err;
1638 tx_drop += ring->stats.tx_tso_err;
1639 tx_errors += ring->stats.sw_err_cnt;
1640 tx_errors += ring->stats.tx_vlan_err;
1641 tx_errors += ring->stats.tx_l4_proto_err;
1642 tx_errors += ring->stats.tx_l2l3l4_err;
1643 tx_errors += ring->stats.tx_tso_err;
1644 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1646 /* fetch the rx stats */
1647 ring = &priv->ring[idx + queue_num];
1649 start = u64_stats_fetch_begin_irq(&ring->syncp);
1650 rx_bytes += ring->stats.rx_bytes;
1651 rx_pkts += ring->stats.rx_pkts;
1652 rx_drop += ring->stats.l2_err;
1653 rx_errors += ring->stats.l2_err;
1654 rx_errors += ring->stats.l3l4_csum_err;
1655 rx_crc_errors += ring->stats.l2_err;
1656 rx_multicast += ring->stats.rx_multicast;
1657 rx_length_errors += ring->stats.err_pkt_len;
1658 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1661 stats->tx_bytes = tx_bytes;
1662 stats->tx_packets = tx_pkts;
1663 stats->rx_bytes = rx_bytes;
1664 stats->rx_packets = rx_pkts;
1666 stats->rx_errors = rx_errors;
1667 stats->multicast = rx_multicast;
1668 stats->rx_length_errors = rx_length_errors;
1669 stats->rx_crc_errors = rx_crc_errors;
1670 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1672 stats->tx_errors = tx_errors;
1673 stats->rx_dropped = rx_drop;
1674 stats->tx_dropped = tx_drop;
1675 stats->collisions = netdev->stats.collisions;
1676 stats->rx_over_errors = netdev->stats.rx_over_errors;
1677 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1678 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1679 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1680 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1681 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1682 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1683 stats->tx_window_errors = netdev->stats.tx_window_errors;
1684 stats->rx_compressed = netdev->stats.rx_compressed;
1685 stats->tx_compressed = netdev->stats.tx_compressed;
1688 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1690 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1691 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1692 struct hnae3_knic_private_info *kinfo;
1693 u8 tc = mqprio_qopt->qopt.num_tc;
1694 u16 mode = mqprio_qopt->mode;
1695 u8 hw = mqprio_qopt->qopt.hw;
1696 struct hnae3_handle *h;
1698 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1699 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1702 if (tc > HNAE3_MAX_TC)
1708 h = hns3_get_handle(netdev);
1711 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1713 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1714 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
1717 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1720 if (type != TC_SETUP_QDISC_MQPRIO)
1723 return hns3_setup_tc(dev, type_data);
1726 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1727 __be16 proto, u16 vid)
1729 struct hnae3_handle *h = hns3_get_handle(netdev);
1732 if (h->ae_algo->ops->set_vlan_filter)
1733 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1738 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1739 __be16 proto, u16 vid)
1741 struct hnae3_handle *h = hns3_get_handle(netdev);
1744 if (h->ae_algo->ops->set_vlan_filter)
1745 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1750 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1751 u8 qos, __be16 vlan_proto)
1753 struct hnae3_handle *h = hns3_get_handle(netdev);
1756 netif_dbg(h, drv, netdev,
1757 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1758 vf, vlan, qos, ntohs(vlan_proto));
1760 if (h->ae_algo->ops->set_vf_vlan_filter)
1761 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1767 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1769 struct hnae3_handle *handle = hns3_get_handle(netdev);
1771 if (hns3_nic_resetting(netdev))
1774 if (!handle->ae_algo->ops->set_vf_spoofchk)
1777 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1780 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1782 struct hnae3_handle *handle = hns3_get_handle(netdev);
1784 if (!handle->ae_algo->ops->set_vf_trust)
1787 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1790 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1792 struct hnae3_handle *h = hns3_get_handle(netdev);
1795 if (hns3_nic_resetting(netdev))
1798 if (!h->ae_algo->ops->set_mtu)
1801 netif_dbg(h, drv, netdev,
1802 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1804 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1806 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1809 netdev->mtu = new_mtu;
1814 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1816 struct hns3_nic_priv *priv = netdev_priv(ndev);
1817 struct hnae3_handle *h = hns3_get_handle(ndev);
1818 struct hns3_enet_ring *tx_ring;
1819 struct napi_struct *napi;
1820 int timeout_queue = 0;
1821 int hw_head, hw_tail;
1822 int fbd_num, fbd_oft;
1823 int ebd_num, ebd_oft;
1828 /* Find the stopped queue the same way the stack does */
1829 for (i = 0; i < ndev->num_tx_queues; i++) {
1830 struct netdev_queue *q;
1831 unsigned long trans_start;
1833 q = netdev_get_tx_queue(ndev, i);
1834 trans_start = q->trans_start;
1835 if (netif_xmit_stopped(q) &&
1837 (trans_start + ndev->watchdog_timeo))) {
1839 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1841 jiffies_to_msecs(jiffies - trans_start));
1846 if (i == ndev->num_tx_queues) {
1848 "no netdev TX timeout queue found, timeout count: %llu\n",
1849 priv->tx_timeout_count);
1853 priv->tx_timeout_count++;
1855 tx_ring = &priv->ring[timeout_queue];
1856 napi = &tx_ring->tqp_vector->napi;
1859 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1860 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1861 tx_ring->next_to_clean, napi->state);
1864 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1865 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1866 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1869 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1870 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1871 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1873 /* When mac received many pause frames continuous, it's unable to send
1874 * packets, which may cause tx timeout
1876 if (h->ae_algo->ops->get_mac_stats) {
1877 struct hns3_mac_stats mac_stats;
1879 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
1880 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1881 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
1884 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1885 HNS3_RING_TX_RING_HEAD_REG);
1886 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1887 HNS3_RING_TX_RING_TAIL_REG);
1888 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1889 HNS3_RING_TX_RING_FBDNUM_REG);
1890 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1891 HNS3_RING_TX_RING_OFFSET_REG);
1892 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1893 HNS3_RING_TX_RING_EBDNUM_REG);
1894 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1895 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1896 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1897 HNS3_RING_TX_RING_BD_NUM_REG);
1898 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1899 HNS3_RING_TX_RING_BD_ERR_REG);
1900 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1901 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1904 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1905 bd_num, hw_head, hw_tail, bd_err,
1906 readl(tx_ring->tqp_vector->mask_addr));
1908 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1909 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
1914 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
1916 struct hns3_nic_priv *priv = netdev_priv(ndev);
1917 struct hnae3_handle *h = priv->ae_handle;
1919 if (!hns3_get_tx_timeo_queue_info(ndev))
1922 /* request the reset, and let the hclge to determine
1923 * which reset level should be done
1925 if (h->ae_algo->ops->reset_event)
1926 h->ae_algo->ops->reset_event(h->pdev, h);
1929 #ifdef CONFIG_RFS_ACCEL
1930 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1931 u16 rxq_index, u32 flow_id)
1933 struct hnae3_handle *h = hns3_get_handle(dev);
1934 struct flow_keys fkeys;
1936 if (!h->ae_algo->ops->add_arfs_entry)
1939 if (skb->encapsulation)
1940 return -EPROTONOSUPPORT;
1942 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1943 return -EPROTONOSUPPORT;
1945 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1946 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1947 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1948 fkeys.basic.ip_proto != IPPROTO_UDP))
1949 return -EPROTONOSUPPORT;
1951 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1955 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1956 struct ifla_vf_info *ivf)
1958 struct hnae3_handle *h = hns3_get_handle(ndev);
1960 if (!h->ae_algo->ops->get_vf_config)
1963 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1966 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1969 struct hnae3_handle *h = hns3_get_handle(ndev);
1971 if (!h->ae_algo->ops->set_vf_link_state)
1974 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1977 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1978 int min_tx_rate, int max_tx_rate)
1980 struct hnae3_handle *h = hns3_get_handle(ndev);
1982 if (!h->ae_algo->ops->set_vf_rate)
1985 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1989 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1991 struct hnae3_handle *h = hns3_get_handle(netdev);
1993 if (!h->ae_algo->ops->set_vf_mac)
1996 if (is_multicast_ether_addr(mac)) {
1998 "Invalid MAC:%pM specified. Could not set MAC\n",
2003 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2006 static const struct net_device_ops hns3_nic_netdev_ops = {
2007 .ndo_open = hns3_nic_net_open,
2008 .ndo_stop = hns3_nic_net_stop,
2009 .ndo_start_xmit = hns3_nic_net_xmit,
2010 .ndo_tx_timeout = hns3_nic_net_timeout,
2011 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
2012 .ndo_do_ioctl = hns3_nic_do_ioctl,
2013 .ndo_change_mtu = hns3_nic_change_mtu,
2014 .ndo_set_features = hns3_nic_set_features,
2015 .ndo_features_check = hns3_features_check,
2016 .ndo_get_stats64 = hns3_nic_get_stats64,
2017 .ndo_setup_tc = hns3_nic_setup_tc,
2018 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
2019 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2020 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2021 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
2022 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
2023 .ndo_set_vf_trust = hns3_set_vf_trust,
2024 #ifdef CONFIG_RFS_ACCEL
2025 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2027 .ndo_get_vf_config = hns3_nic_get_vf_config,
2028 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
2029 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
2030 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
2033 bool hns3_is_phys_func(struct pci_dev *pdev)
2035 u32 dev_id = pdev->device;
2038 case HNAE3_DEV_ID_GE:
2039 case HNAE3_DEV_ID_25GE:
2040 case HNAE3_DEV_ID_25GE_RDMA:
2041 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2042 case HNAE3_DEV_ID_50GE_RDMA:
2043 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2044 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2046 case HNAE3_DEV_ID_100G_VF:
2047 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2050 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2057 static void hns3_disable_sriov(struct pci_dev *pdev)
2059 /* If our VFs are assigned we cannot shut down SR-IOV
2060 * without causing issues, so just leave the hardware
2061 * available but disabled
2063 if (pci_vfs_assigned(pdev)) {
2064 dev_warn(&pdev->dev,
2065 "disabling driver while VFs are assigned\n");
2069 pci_disable_sriov(pdev);
2072 static void hns3_get_dev_capability(struct pci_dev *pdev,
2073 struct hnae3_ae_dev *ae_dev)
2075 if (pdev->revision >= 0x21) {
2076 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
2077 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2081 /* hns3_probe - Device initialization routine
2082 * @pdev: PCI device information struct
2083 * @ent: entry in hns3_pci_tbl
2085 * hns3_probe initializes a PF identified by a pci_dev structure.
2086 * The OS initialization, configuring of the PF private structure,
2087 * and a hardware reset occur.
2089 * Returns 0 on success, negative on failure
2091 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2093 struct hnae3_ae_dev *ae_dev;
2096 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2100 ae_dev->pdev = pdev;
2101 ae_dev->flag = ent->driver_data;
2102 ae_dev->reset_type = HNAE3_NONE_RESET;
2103 hns3_get_dev_capability(pdev, ae_dev);
2104 pci_set_drvdata(pdev, ae_dev);
2106 ret = hnae3_register_ae_dev(ae_dev);
2108 devm_kfree(&pdev->dev, ae_dev);
2109 pci_set_drvdata(pdev, NULL);
2115 /* hns3_remove - Device removal routine
2116 * @pdev: PCI device information struct
2118 static void hns3_remove(struct pci_dev *pdev)
2120 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2122 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2123 hns3_disable_sriov(pdev);
2125 hnae3_unregister_ae_dev(ae_dev);
2126 pci_set_drvdata(pdev, NULL);
2130 * hns3_pci_sriov_configure
2131 * @pdev: pointer to a pci_dev structure
2132 * @num_vfs: number of VFs to allocate
2134 * Enable or change the number of VFs. Called when the user updates the number
2137 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2141 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2142 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2147 ret = pci_enable_sriov(pdev, num_vfs);
2149 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2152 } else if (!pci_vfs_assigned(pdev)) {
2153 pci_disable_sriov(pdev);
2155 dev_warn(&pdev->dev,
2156 "Unable to free VFs because some are assigned to VMs.\n");
2162 static void hns3_shutdown(struct pci_dev *pdev)
2164 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2166 hnae3_unregister_ae_dev(ae_dev);
2167 devm_kfree(&pdev->dev, ae_dev);
2168 pci_set_drvdata(pdev, NULL);
2170 if (system_state == SYSTEM_POWER_OFF)
2171 pci_set_power_state(pdev, PCI_D3hot);
2174 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2175 pci_channel_state_t state)
2177 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2178 pci_ers_result_t ret;
2180 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2182 if (state == pci_channel_io_perm_failure)
2183 return PCI_ERS_RESULT_DISCONNECT;
2185 if (!ae_dev || !ae_dev->ops) {
2187 "Can't recover - error happened before device initialized\n");
2188 return PCI_ERS_RESULT_NONE;
2191 if (ae_dev->ops->handle_hw_ras_error)
2192 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
2194 return PCI_ERS_RESULT_NONE;
2199 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2201 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2202 const struct hnae3_ae_ops *ops;
2203 enum hnae3_reset_type reset_type;
2204 struct device *dev = &pdev->dev;
2206 if (!ae_dev || !ae_dev->ops)
2207 return PCI_ERS_RESULT_NONE;
2210 /* request the reset */
2211 if (ops->reset_event && ops->get_reset_level &&
2212 ops->set_default_reset_request) {
2213 if (ae_dev->hw_err_reset_req) {
2214 reset_type = ops->get_reset_level(ae_dev,
2215 &ae_dev->hw_err_reset_req);
2216 ops->set_default_reset_request(ae_dev, reset_type);
2217 dev_info(dev, "requesting reset due to PCI error\n");
2218 ops->reset_event(pdev, NULL);
2221 return PCI_ERS_RESULT_RECOVERED;
2224 return PCI_ERS_RESULT_DISCONNECT;
2227 static void hns3_reset_prepare(struct pci_dev *pdev)
2229 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2231 dev_info(&pdev->dev, "hns3 flr prepare\n");
2232 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2233 ae_dev->ops->flr_prepare(ae_dev);
2236 static void hns3_reset_done(struct pci_dev *pdev)
2238 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2240 dev_info(&pdev->dev, "hns3 flr done\n");
2241 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2242 ae_dev->ops->flr_done(ae_dev);
2245 static const struct pci_error_handlers hns3_err_handler = {
2246 .error_detected = hns3_error_detected,
2247 .slot_reset = hns3_slot_reset,
2248 .reset_prepare = hns3_reset_prepare,
2249 .reset_done = hns3_reset_done,
2252 static struct pci_driver hns3_driver = {
2253 .name = hns3_driver_name,
2254 .id_table = hns3_pci_tbl,
2255 .probe = hns3_probe,
2256 .remove = hns3_remove,
2257 .shutdown = hns3_shutdown,
2258 .sriov_configure = hns3_pci_sriov_configure,
2259 .err_handler = &hns3_err_handler,
2262 /* set default feature to hns3 */
2263 static void hns3_set_default_feature(struct net_device *netdev)
2265 struct hnae3_handle *h = hns3_get_handle(netdev);
2266 struct pci_dev *pdev = h->pdev;
2268 netdev->priv_flags |= IFF_UNICAST_FLT;
2270 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2271 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2272 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2273 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2274 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2275 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
2277 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2279 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2280 NETIF_F_HW_VLAN_CTAG_FILTER |
2281 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2282 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2283 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2284 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2285 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2288 netdev->vlan_features |=
2289 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2290 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2291 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2292 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2293 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2296 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2297 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2298 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2299 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2300 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2301 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2304 if (pdev->revision >= 0x21) {
2305 netdev->hw_features |= NETIF_F_GRO_HW;
2306 netdev->features |= NETIF_F_GRO_HW;
2308 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2309 netdev->hw_features |= NETIF_F_NTUPLE;
2310 netdev->features |= NETIF_F_NTUPLE;
2315 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2316 struct hns3_desc_cb *cb)
2318 unsigned int order = hns3_page_order(ring);
2321 p = dev_alloc_pages(order);
2326 cb->page_offset = 0;
2328 cb->buf = page_address(p);
2329 cb->length = hns3_page_size(ring);
2330 cb->type = DESC_TYPE_PAGE;
2335 static void hns3_free_buffer(struct hns3_enet_ring *ring,
2336 struct hns3_desc_cb *cb)
2338 if (cb->type == DESC_TYPE_SKB)
2339 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2340 else if (!HNAE3_IS_TX_RING(ring))
2341 put_page((struct page *)cb->priv);
2342 memset(cb, 0, sizeof(*cb));
2345 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2347 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2348 cb->length, ring_to_dma_dir(ring));
2350 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2356 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2357 struct hns3_desc_cb *cb)
2359 if (cb->type == DESC_TYPE_SKB)
2360 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2361 ring_to_dma_dir(ring));
2362 else if (cb->length)
2363 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2364 ring_to_dma_dir(ring));
2367 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2369 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2370 ring->desc[i].addr = 0;
2373 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2375 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2377 if (!ring->desc_cb[i].dma)
2380 hns3_buffer_detach(ring, i);
2381 hns3_free_buffer(ring, cb);
2384 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2388 for (i = 0; i < ring->desc_num; i++)
2389 hns3_free_buffer_detach(ring, i);
2392 /* free desc along with its attached buffer */
2393 static void hns3_free_desc(struct hns3_enet_ring *ring)
2395 int size = ring->desc_num * sizeof(ring->desc[0]);
2397 hns3_free_buffers(ring);
2400 dma_free_coherent(ring_to_dev(ring), size,
2401 ring->desc, ring->desc_dma_addr);
2406 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2408 int size = ring->desc_num * sizeof(ring->desc[0]);
2410 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2411 &ring->desc_dma_addr, GFP_KERNEL);
2418 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2419 struct hns3_desc_cb *cb)
2423 ret = hns3_alloc_buffer(ring, cb);
2427 ret = hns3_map_buffer(ring, cb);
2434 hns3_free_buffer(ring, cb);
2439 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2441 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2446 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2451 /* Allocate memory for raw pkg, and map with dma */
2452 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2456 for (i = 0; i < ring->desc_num; i++) {
2457 ret = hns3_alloc_buffer_attach(ring, i);
2459 goto out_buffer_fail;
2465 for (j = i - 1; j >= 0; j--)
2466 hns3_free_buffer_detach(ring, j);
2470 /* detach a in-used buffer and replace with a reserved one */
2471 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2472 struct hns3_desc_cb *res_cb)
2474 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2475 ring->desc_cb[i] = *res_cb;
2476 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2477 ring->desc[i].rx.bd_base_info = 0;
2480 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2482 ring->desc_cb[i].reuse_flag = 0;
2483 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2484 ring->desc_cb[i].page_offset);
2485 ring->desc[i].rx.bd_base_info = 0;
2488 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2489 int *bytes, int *pkts)
2491 int ntc = ring->next_to_clean;
2492 struct hns3_desc_cb *desc_cb;
2494 while (head != ntc) {
2495 desc_cb = &ring->desc_cb[ntc];
2496 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2497 (*bytes) += desc_cb->length;
2498 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2499 hns3_free_buffer_detach(ring, ntc);
2501 if (++ntc == ring->desc_num)
2504 /* Issue prefetch for next Tx descriptor */
2505 prefetch(&ring->desc_cb[ntc]);
2508 /* This smp_store_release() pairs with smp_load_acquire() in
2509 * ring_space called by hns3_nic_net_xmit.
2511 smp_store_release(&ring->next_to_clean, ntc);
2514 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2516 int u = ring->next_to_use;
2517 int c = ring->next_to_clean;
2519 if (unlikely(h > ring->desc_num))
2522 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2525 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2527 struct net_device *netdev = ring_to_netdev(ring);
2528 struct hns3_nic_priv *priv = netdev_priv(netdev);
2529 struct netdev_queue *dev_queue;
2533 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2535 if (is_ring_empty(ring) || head == ring->next_to_clean)
2536 return; /* no data to poll */
2538 rmb(); /* Make sure head is ready before touch any data */
2540 if (unlikely(!is_valid_clean_head(ring, head))) {
2541 hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head,
2542 ring->next_to_use, ring->next_to_clean);
2544 u64_stats_update_begin(&ring->syncp);
2545 ring->stats.io_err_cnt++;
2546 u64_stats_update_end(&ring->syncp);
2552 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
2554 ring->tqp_vector->tx_group.total_bytes += bytes;
2555 ring->tqp_vector->tx_group.total_packets += pkts;
2557 u64_stats_update_begin(&ring->syncp);
2558 ring->stats.tx_bytes += bytes;
2559 ring->stats.tx_pkts += pkts;
2560 u64_stats_update_end(&ring->syncp);
2562 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2563 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2565 if (unlikely(netif_carrier_ok(netdev) &&
2566 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
2567 /* Make sure that anybody stopping the queue after this
2568 * sees the new next_to_clean.
2571 if (netif_tx_queue_stopped(dev_queue) &&
2572 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2573 netif_tx_wake_queue(dev_queue);
2574 ring->stats.restart_queue++;
2579 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2581 int ntc = ring->next_to_clean;
2582 int ntu = ring->next_to_use;
2584 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2587 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2590 struct hns3_desc_cb *desc_cb;
2591 struct hns3_desc_cb res_cbs;
2594 for (i = 0; i < cleand_count; i++) {
2595 desc_cb = &ring->desc_cb[ring->next_to_use];
2596 if (desc_cb->reuse_flag) {
2597 u64_stats_update_begin(&ring->syncp);
2598 ring->stats.reuse_pg_cnt++;
2599 u64_stats_update_end(&ring->syncp);
2601 hns3_reuse_buffer(ring, ring->next_to_use);
2603 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2605 u64_stats_update_begin(&ring->syncp);
2606 ring->stats.sw_err_cnt++;
2607 u64_stats_update_end(&ring->syncp);
2609 hns3_rl_err(ring_to_netdev(ring),
2610 "alloc rx buffer failed: %d\n",
2614 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2616 u64_stats_update_begin(&ring->syncp);
2617 ring->stats.non_reuse_pg++;
2618 u64_stats_update_end(&ring->syncp);
2621 ring_ptr_move_fw(ring, next_to_use);
2624 wmb(); /* Make all data has been write before submit */
2625 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2628 static bool hns3_page_is_reusable(struct page *page)
2630 return page_to_nid(page) == numa_mem_id() &&
2631 !page_is_pfmemalloc(page);
2634 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2635 struct hns3_enet_ring *ring, int pull_len,
2636 struct hns3_desc_cb *desc_cb)
2638 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2639 int size = le16_to_cpu(desc->rx.size);
2640 u32 truesize = hns3_buf_size(ring);
2642 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2643 size - pull_len, truesize);
2645 /* Avoid re-using remote pages, or the stack is still using the page
2646 * when page_offset rollback to zero, flag default unreuse
2648 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
2649 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
2652 /* Move offset up to the next cache line */
2653 desc_cb->page_offset += truesize;
2655 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
2656 desc_cb->reuse_flag = 1;
2657 /* Bump ref count on page before it is given */
2658 get_page(desc_cb->priv);
2659 } else if (page_count(desc_cb->priv) == 1) {
2660 desc_cb->reuse_flag = 1;
2661 desc_cb->page_offset = 0;
2662 get_page(desc_cb->priv);
2666 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
2668 __be16 type = skb->protocol;
2672 while (eth_type_vlan(type)) {
2673 struct vlan_hdr *vh;
2675 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2678 vh = (struct vlan_hdr *)(skb->data + depth);
2679 type = vh->h_vlan_encapsulated_proto;
2683 skb_set_network_header(skb, depth);
2685 if (type == htons(ETH_P_IP)) {
2686 const struct iphdr *iph = ip_hdr(skb);
2688 depth += sizeof(struct iphdr);
2689 skb_set_transport_header(skb, depth);
2691 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2693 } else if (type == htons(ETH_P_IPV6)) {
2694 const struct ipv6hdr *iph = ipv6_hdr(skb);
2696 depth += sizeof(struct ipv6hdr);
2697 skb_set_transport_header(skb, depth);
2699 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2702 hns3_rl_err(skb->dev,
2703 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2704 be16_to_cpu(type), depth);
2708 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2710 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2712 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2713 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
2715 skb->csum_start = (unsigned char *)th - skb->head;
2716 skb->csum_offset = offsetof(struct tcphdr, check);
2717 skb->ip_summed = CHECKSUM_PARTIAL;
2719 trace_hns3_gro(skb);
2724 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2725 u32 l234info, u32 bd_base_info, u32 ol_info)
2727 struct net_device *netdev = ring_to_netdev(ring);
2728 int l3_type, l4_type;
2731 skb->ip_summed = CHECKSUM_NONE;
2733 skb_checksum_none_assert(skb);
2735 if (!(netdev->features & NETIF_F_RXCSUM))
2738 /* check if hardware has done checksum */
2739 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2742 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2743 BIT(HNS3_RXD_OL3E_B) |
2744 BIT(HNS3_RXD_OL4E_B)))) {
2745 u64_stats_update_begin(&ring->syncp);
2746 ring->stats.l3l4_csum_err++;
2747 u64_stats_update_end(&ring->syncp);
2752 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
2755 case HNS3_OL4_TYPE_MAC_IN_UDP:
2756 case HNS3_OL4_TYPE_NVGRE:
2757 skb->csum_level = 1;
2759 case HNS3_OL4_TYPE_NO_TUN:
2760 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2762 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2765 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2766 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2767 l3_type == HNS3_L3_TYPE_IPV6) &&
2768 (l4_type == HNS3_L4_TYPE_UDP ||
2769 l4_type == HNS3_L4_TYPE_TCP ||
2770 l4_type == HNS3_L4_TYPE_SCTP))
2771 skb->ip_summed = CHECKSUM_UNNECESSARY;
2778 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2780 if (skb_has_frag_list(skb))
2781 napi_gro_flush(&ring->tqp_vector->napi, false);
2783 napi_gro_receive(&ring->tqp_vector->napi, skb);
2786 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2787 struct hns3_desc *desc, u32 l234info,
2790 struct hnae3_handle *handle = ring->tqp->handle;
2791 struct pci_dev *pdev = ring->tqp->handle->pdev;
2793 if (pdev->revision == 0x20) {
2794 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2795 if (!(*vlan_tag & VLAN_VID_MASK))
2796 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2798 return (*vlan_tag != 0);
2801 #define HNS3_STRP_OUTER_VLAN 0x1
2802 #define HNS3_STRP_INNER_VLAN 0x2
2803 #define HNS3_STRP_BOTH 0x3
2805 /* Hardware always insert VLAN tag into RX descriptor when
2806 * remove the tag from packet, driver needs to determine
2807 * reporting which tag to stack.
2809 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2810 HNS3_RXD_STRP_TAGP_S)) {
2811 case HNS3_STRP_OUTER_VLAN:
2812 if (handle->port_base_vlan_state !=
2813 HNAE3_PORT_BASE_VLAN_DISABLE)
2816 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2818 case HNS3_STRP_INNER_VLAN:
2819 if (handle->port_base_vlan_state !=
2820 HNAE3_PORT_BASE_VLAN_DISABLE)
2823 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2825 case HNS3_STRP_BOTH:
2826 if (handle->port_base_vlan_state ==
2827 HNAE3_PORT_BASE_VLAN_DISABLE)
2828 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2830 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2838 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
2841 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2842 struct net_device *netdev = ring_to_netdev(ring);
2843 struct sk_buff *skb;
2845 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2847 if (unlikely(!skb)) {
2848 hns3_rl_err(netdev, "alloc rx skb fail\n");
2850 u64_stats_update_begin(&ring->syncp);
2851 ring->stats.sw_err_cnt++;
2852 u64_stats_update_end(&ring->syncp);
2857 trace_hns3_rx_desc(ring);
2858 prefetchw(skb->data);
2860 ring->pending_buf = 1;
2862 ring->tail_skb = NULL;
2863 if (length <= HNS3_RX_HEAD_SIZE) {
2864 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2866 /* We can reuse buffer as-is, just make sure it is local */
2867 if (likely(hns3_page_is_reusable(desc_cb->priv)))
2868 desc_cb->reuse_flag = 1;
2869 else /* This page cannot be reused so discard it */
2870 put_page(desc_cb->priv);
2872 ring_ptr_move_fw(ring, next_to_clean);
2875 u64_stats_update_begin(&ring->syncp);
2876 ring->stats.seg_pkt_cnt++;
2877 u64_stats_update_end(&ring->syncp);
2879 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
2880 __skb_put(skb, ring->pull_len);
2881 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2883 ring_ptr_move_fw(ring, next_to_clean);
2888 static int hns3_add_frag(struct hns3_enet_ring *ring)
2890 struct sk_buff *skb = ring->skb;
2891 struct sk_buff *head_skb = skb;
2892 struct sk_buff *new_skb;
2893 struct hns3_desc_cb *desc_cb;
2894 struct hns3_desc *desc;
2898 desc = &ring->desc[ring->next_to_clean];
2899 desc_cb = &ring->desc_cb[ring->next_to_clean];
2900 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2901 /* make sure HW write desc complete */
2903 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
2906 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2907 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
2908 if (unlikely(!new_skb)) {
2909 hns3_rl_err(ring_to_netdev(ring),
2910 "alloc rx fraglist skb fail\n");
2915 if (ring->tail_skb) {
2916 ring->tail_skb->next = new_skb;
2917 ring->tail_skb = new_skb;
2919 skb_shinfo(skb)->frag_list = new_skb;
2920 ring->tail_skb = new_skb;
2924 if (ring->tail_skb) {
2925 head_skb->truesize += hns3_buf_size(ring);
2926 head_skb->data_len += le16_to_cpu(desc->rx.size);
2927 head_skb->len += le16_to_cpu(desc->rx.size);
2928 skb = ring->tail_skb;
2931 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2932 trace_hns3_rx_desc(ring);
2933 ring_ptr_move_fw(ring, next_to_clean);
2934 ring->pending_buf++;
2935 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
2940 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2941 struct sk_buff *skb, u32 l234info,
2942 u32 bd_base_info, u32 ol_info)
2946 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2947 HNS3_RXD_GRO_SIZE_M,
2948 HNS3_RXD_GRO_SIZE_S);
2949 /* if there is no HW GRO, do not set gro params */
2950 if (!skb_shinfo(skb)->gso_size) {
2951 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
2955 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2956 HNS3_RXD_GRO_COUNT_M,
2957 HNS3_RXD_GRO_COUNT_S);
2959 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
2960 if (l3_type == HNS3_L3_TYPE_IPV4)
2961 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2962 else if (l3_type == HNS3_L3_TYPE_IPV6)
2963 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2967 return hns3_gro_complete(skb, l234info);
2970 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2971 struct sk_buff *skb, u32 rss_hash)
2973 struct hnae3_handle *handle = ring->tqp->handle;
2974 enum pkt_hash_types rss_type;
2977 rss_type = handle->kinfo.rss_type;
2979 rss_type = PKT_HASH_TYPE_NONE;
2981 skb_set_hash(skb, rss_hash, rss_type);
2984 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
2986 struct net_device *netdev = ring_to_netdev(ring);
2987 enum hns3_pkt_l2t_type l2_frame_type;
2988 u32 bd_base_info, l234info, ol_info;
2989 struct hns3_desc *desc;
2993 /* bdinfo handled below is only valid on the last BD of the
2994 * current packet, and ring->next_to_clean indicates the first
2995 * descriptor of next packet, so need - 1 below.
2997 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2998 (ring->desc_num - 1);
2999 desc = &ring->desc[pre_ntc];
3000 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3001 l234info = le32_to_cpu(desc->rx.l234_info);
3002 ol_info = le32_to_cpu(desc->rx.ol_info);
3004 /* Based on hw strategy, the tag offloaded will be stored at
3005 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
3006 * in one layer tag case.
3008 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3011 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
3012 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3016 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3017 BIT(HNS3_RXD_L2E_B))))) {
3018 u64_stats_update_begin(&ring->syncp);
3019 if (l234info & BIT(HNS3_RXD_L2E_B))
3020 ring->stats.l2_err++;
3022 ring->stats.err_pkt_len++;
3023 u64_stats_update_end(&ring->syncp);
3030 /* Do update ip stack process */
3031 skb->protocol = eth_type_trans(skb, netdev);
3033 /* This is needed in order to enable forwarding support */
3034 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3035 bd_base_info, ol_info);
3036 if (unlikely(ret)) {
3037 u64_stats_update_begin(&ring->syncp);
3038 ring->stats.rx_err_cnt++;
3039 u64_stats_update_end(&ring->syncp);
3043 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3046 u64_stats_update_begin(&ring->syncp);
3047 ring->stats.rx_pkts++;
3048 ring->stats.rx_bytes += len;
3050 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3051 ring->stats.rx_multicast++;
3053 u64_stats_update_end(&ring->syncp);
3055 ring->tqp_vector->rx_group.total_bytes += len;
3057 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
3061 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
3063 struct sk_buff *skb = ring->skb;
3064 struct hns3_desc_cb *desc_cb;
3065 struct hns3_desc *desc;
3066 unsigned int length;
3070 desc = &ring->desc[ring->next_to_clean];
3071 desc_cb = &ring->desc_cb[ring->next_to_clean];
3075 length = le16_to_cpu(desc->rx.size);
3076 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3078 /* Check valid BD */
3079 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3083 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
3085 /* Prefetch first cache line of first page
3086 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3087 * line size is 64B so need to prefetch twice to make it 128B. But in
3088 * actual we can have greater size of caches with 128B Level 1 cache
3089 * lines. In such a case, single fetch would suffice to cache in the
3090 * relevant part of the header.
3093 #if L1_CACHE_BYTES < 128
3094 prefetch(ring->va + L1_CACHE_BYTES);
3098 ret = hns3_alloc_skb(ring, length, ring->va);
3101 if (ret < 0) /* alloc buffer fail */
3103 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3104 ret = hns3_add_frag(ring);
3109 ret = hns3_add_frag(ring);
3114 /* As the head data may be changed when GRO enable, copy
3115 * the head data in after other data rx completed
3117 if (skb->len > HNS3_RX_HEAD_SIZE)
3118 memcpy(skb->data, ring->va,
3119 ALIGN(ring->pull_len, sizeof(long)));
3121 ret = hns3_handle_bdinfo(ring, skb);
3122 if (unlikely(ret)) {
3123 dev_kfree_skb_any(skb);
3127 skb_record_rx_queue(skb, ring->tqp->tqp_index);
3131 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3132 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
3134 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
3135 int unused_count = hns3_desc_unused(ring);
3140 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
3141 num -= unused_count;
3142 unused_count -= ring->pending_buf;
3147 rmb(); /* Make sure num taken effect before the other data is touched */
3149 while (recv_pkts < budget && recv_bds < num) {
3150 /* Reuse or realloc buffers */
3151 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3152 hns3_nic_alloc_rx_buffers(ring, unused_count);
3153 unused_count = hns3_desc_unused(ring) -
3158 err = hns3_handle_rx_bd(ring);
3159 /* Do not get FE for the packet or failed to alloc skb */
3160 if (unlikely(!ring->skb || err == -ENXIO)) {
3162 } else if (likely(!err)) {
3163 rx_fn(ring, ring->skb);
3167 recv_bds += ring->pending_buf;
3168 unused_count += ring->pending_buf;
3170 ring->pending_buf = 0;
3174 /* Make all data has been write before submit */
3175 if (unused_count > 0)
3176 hns3_nic_alloc_rx_buffers(ring, unused_count);
3181 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
3183 #define HNS3_RX_LOW_BYTE_RATE 10000
3184 #define HNS3_RX_MID_BYTE_RATE 20000
3185 #define HNS3_RX_ULTRA_PACKET_RATE 40
3187 enum hns3_flow_level_range new_flow_level;
3188 struct hns3_enet_tqp_vector *tqp_vector;
3189 int packets_per_msecs, bytes_per_msecs;
3192 tqp_vector = ring_group->ring->tqp_vector;
3194 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
3195 if (!time_passed_ms)
3198 do_div(ring_group->total_packets, time_passed_ms);
3199 packets_per_msecs = ring_group->total_packets;
3201 do_div(ring_group->total_bytes, time_passed_ms);
3202 bytes_per_msecs = ring_group->total_bytes;
3204 new_flow_level = ring_group->coal.flow_level;
3206 /* Simple throttlerate management
3207 * 0-10MB/s lower (50000 ints/s)
3208 * 10-20MB/s middle (20000 ints/s)
3209 * 20-1249MB/s high (18000 ints/s)
3210 * > 40000pps ultra (8000 ints/s)
3212 switch (new_flow_level) {
3214 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
3215 new_flow_level = HNS3_FLOW_MID;
3218 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
3219 new_flow_level = HNS3_FLOW_HIGH;
3220 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
3221 new_flow_level = HNS3_FLOW_LOW;
3223 case HNS3_FLOW_HIGH:
3224 case HNS3_FLOW_ULTRA:
3226 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
3227 new_flow_level = HNS3_FLOW_MID;
3231 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3232 &tqp_vector->rx_group == ring_group)
3233 new_flow_level = HNS3_FLOW_ULTRA;
3235 ring_group->total_bytes = 0;
3236 ring_group->total_packets = 0;
3237 ring_group->coal.flow_level = new_flow_level;
3242 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3244 struct hns3_enet_tqp_vector *tqp_vector;
3247 if (!ring_group->ring)
3250 tqp_vector = ring_group->ring->tqp_vector;
3251 if (!tqp_vector->last_jiffies)
3254 if (ring_group->total_packets == 0) {
3255 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3256 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3260 if (!hns3_get_new_flow_lvl(ring_group))
3263 new_int_gl = ring_group->coal.int_gl;
3264 switch (ring_group->coal.flow_level) {
3266 new_int_gl = HNS3_INT_GL_50K;
3269 new_int_gl = HNS3_INT_GL_20K;
3271 case HNS3_FLOW_HIGH:
3272 new_int_gl = HNS3_INT_GL_18K;
3274 case HNS3_FLOW_ULTRA:
3275 new_int_gl = HNS3_INT_GL_8K;
3281 if (new_int_gl != ring_group->coal.int_gl) {
3282 ring_group->coal.int_gl = new_int_gl;
3288 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3290 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3291 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3292 bool rx_update, tx_update;
3294 /* update param every 1000ms */
3295 if (time_before(jiffies,
3296 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3299 if (rx_group->coal.gl_adapt_enable) {
3300 rx_update = hns3_get_new_int_gl(rx_group);
3302 hns3_set_vector_coalesce_rx_gl(tqp_vector,
3303 rx_group->coal.int_gl);
3306 if (tx_group->coal.gl_adapt_enable) {
3307 tx_update = hns3_get_new_int_gl(tx_group);
3309 hns3_set_vector_coalesce_tx_gl(tqp_vector,
3310 tx_group->coal.int_gl);
3313 tqp_vector->last_jiffies = jiffies;
3316 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3318 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
3319 struct hns3_enet_ring *ring;
3320 int rx_pkt_total = 0;
3322 struct hns3_enet_tqp_vector *tqp_vector =
3323 container_of(napi, struct hns3_enet_tqp_vector, napi);
3324 bool clean_complete = true;
3325 int rx_budget = budget;
3327 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3328 napi_complete(napi);
3332 /* Since the actual Tx work is minimal, we can give the Tx a larger
3333 * budget and be more aggressive about cleaning up the Tx descriptors.
3335 hns3_for_each_ring(ring, tqp_vector->tx_group)
3336 hns3_clean_tx_ring(ring);
3338 /* make sure rx ring budget not smaller than 1 */
3339 if (tqp_vector->num_tqps > 1)
3340 rx_budget = max(budget / tqp_vector->num_tqps, 1);
3342 hns3_for_each_ring(ring, tqp_vector->rx_group) {
3343 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3346 if (rx_cleaned >= rx_budget)
3347 clean_complete = false;
3349 rx_pkt_total += rx_cleaned;
3352 tqp_vector->rx_group.total_packets += rx_pkt_total;
3354 if (!clean_complete)
3357 if (napi_complete(napi) &&
3358 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3359 hns3_update_new_int_gl(tqp_vector);
3360 hns3_mask_vector_irq(tqp_vector, 1);
3363 return rx_pkt_total;
3366 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3367 struct hnae3_ring_chain_node *head)
3369 struct pci_dev *pdev = tqp_vector->handle->pdev;
3370 struct hnae3_ring_chain_node *cur_chain = head;
3371 struct hnae3_ring_chain_node *chain;
3372 struct hns3_enet_ring *tx_ring;
3373 struct hns3_enet_ring *rx_ring;
3375 tx_ring = tqp_vector->tx_group.ring;
3377 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
3378 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3379 HNAE3_RING_TYPE_TX);
3380 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3381 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
3383 cur_chain->next = NULL;
3385 while (tx_ring->next) {
3386 tx_ring = tx_ring->next;
3388 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3391 goto err_free_chain;
3393 cur_chain->next = chain;
3394 chain->tqp_index = tx_ring->tqp->tqp_index;
3395 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3396 HNAE3_RING_TYPE_TX);
3397 hnae3_set_field(chain->int_gl_idx,
3398 HNAE3_RING_GL_IDX_M,
3399 HNAE3_RING_GL_IDX_S,
3406 rx_ring = tqp_vector->rx_group.ring;
3407 if (!tx_ring && rx_ring) {
3408 cur_chain->next = NULL;
3409 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3410 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3411 HNAE3_RING_TYPE_RX);
3412 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3413 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3415 rx_ring = rx_ring->next;
3419 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3421 goto err_free_chain;
3423 cur_chain->next = chain;
3424 chain->tqp_index = rx_ring->tqp->tqp_index;
3425 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3426 HNAE3_RING_TYPE_RX);
3427 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3428 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3432 rx_ring = rx_ring->next;
3438 cur_chain = head->next;
3440 chain = cur_chain->next;
3441 devm_kfree(&pdev->dev, cur_chain);
3449 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3450 struct hnae3_ring_chain_node *head)
3452 struct pci_dev *pdev = tqp_vector->handle->pdev;
3453 struct hnae3_ring_chain_node *chain_tmp, *chain;
3458 chain_tmp = chain->next;
3459 devm_kfree(&pdev->dev, chain);
3464 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3465 struct hns3_enet_ring *ring)
3467 ring->next = group->ring;
3473 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3475 struct pci_dev *pdev = priv->ae_handle->pdev;
3476 struct hns3_enet_tqp_vector *tqp_vector;
3477 int num_vectors = priv->vector_num;
3481 numa_node = dev_to_node(&pdev->dev);
3483 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3484 tqp_vector = &priv->tqp_vector[vector_i];
3485 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3486 &tqp_vector->affinity_mask);
3490 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3492 struct hnae3_ring_chain_node vector_ring_chain;
3493 struct hnae3_handle *h = priv->ae_handle;
3494 struct hns3_enet_tqp_vector *tqp_vector;
3498 hns3_nic_set_cpumask(priv);
3500 for (i = 0; i < priv->vector_num; i++) {
3501 tqp_vector = &priv->tqp_vector[i];
3502 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3503 tqp_vector->num_tqps = 0;
3506 for (i = 0; i < h->kinfo.num_tqps; i++) {
3507 u16 vector_i = i % priv->vector_num;
3508 u16 tqp_num = h->kinfo.num_tqps;
3510 tqp_vector = &priv->tqp_vector[vector_i];
3512 hns3_add_ring_to_group(&tqp_vector->tx_group,
3515 hns3_add_ring_to_group(&tqp_vector->rx_group,
3516 &priv->ring[i + tqp_num]);
3518 priv->ring[i].tqp_vector = tqp_vector;
3519 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
3520 tqp_vector->num_tqps++;
3523 for (i = 0; i < priv->vector_num; i++) {
3524 tqp_vector = &priv->tqp_vector[i];
3526 tqp_vector->rx_group.total_bytes = 0;
3527 tqp_vector->rx_group.total_packets = 0;
3528 tqp_vector->tx_group.total_bytes = 0;
3529 tqp_vector->tx_group.total_packets = 0;
3530 tqp_vector->handle = h;
3532 ret = hns3_get_vector_ring_chain(tqp_vector,
3533 &vector_ring_chain);
3537 ret = h->ae_algo->ops->map_ring_to_vector(h,
3538 tqp_vector->vector_irq, &vector_ring_chain);
3540 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3545 netif_napi_add(priv->netdev, &tqp_vector->napi,
3546 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3553 netif_napi_del(&priv->tqp_vector[i].napi);
3558 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3560 #define HNS3_VECTOR_PF_MAX_NUM 64
3562 struct hnae3_handle *h = priv->ae_handle;
3563 struct hns3_enet_tqp_vector *tqp_vector;
3564 struct hnae3_vector_info *vector;
3565 struct pci_dev *pdev = h->pdev;
3566 u16 tqp_num = h->kinfo.num_tqps;
3571 /* RSS size, cpu online and vector_num should be the same */
3572 /* Should consider 2p/4p later */
3573 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3574 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3576 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3581 /* save the actual available vector number */
3582 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3584 priv->vector_num = vector_num;
3585 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3586 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3588 if (!priv->tqp_vector) {
3593 for (i = 0; i < priv->vector_num; i++) {
3594 tqp_vector = &priv->tqp_vector[i];
3595 tqp_vector->idx = i;
3596 tqp_vector->mask_addr = vector[i].io_addr;
3597 tqp_vector->vector_irq = vector[i].vector;
3598 hns3_vector_gl_rl_init(tqp_vector, priv);
3602 devm_kfree(&pdev->dev, vector);
3606 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3612 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3614 struct hnae3_ring_chain_node vector_ring_chain;
3615 struct hnae3_handle *h = priv->ae_handle;
3616 struct hns3_enet_tqp_vector *tqp_vector;
3619 for (i = 0; i < priv->vector_num; i++) {
3620 tqp_vector = &priv->tqp_vector[i];
3622 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3625 /* Since the mapping can be overwritten, when fail to get the
3626 * chain between vector and ring, we should go on to deal with
3627 * the remaining options.
3629 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3630 dev_warn(priv->dev, "failed to get ring chain\n");
3632 h->ae_algo->ops->unmap_ring_from_vector(h,
3633 tqp_vector->vector_irq, &vector_ring_chain);
3635 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3637 hns3_clear_ring_group(&tqp_vector->rx_group);
3638 hns3_clear_ring_group(&tqp_vector->tx_group);
3639 netif_napi_del(&priv->tqp_vector[i].napi);
3643 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3645 struct hnae3_handle *h = priv->ae_handle;
3646 struct pci_dev *pdev = h->pdev;
3649 for (i = 0; i < priv->vector_num; i++) {
3650 struct hns3_enet_tqp_vector *tqp_vector;
3652 tqp_vector = &priv->tqp_vector[i];
3653 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3658 devm_kfree(&pdev->dev, priv->tqp_vector);
3661 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3662 unsigned int ring_type)
3664 int queue_num = priv->ae_handle->kinfo.num_tqps;
3665 struct hns3_enet_ring *ring;
3668 if (ring_type == HNAE3_RING_TYPE_TX) {
3669 ring = &priv->ring[q->tqp_index];
3670 desc_num = priv->ae_handle->kinfo.num_tx_desc;
3671 ring->queue_index = q->tqp_index;
3672 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3674 ring = &priv->ring[q->tqp_index + queue_num];
3675 desc_num = priv->ae_handle->kinfo.num_rx_desc;
3676 ring->queue_index = q->tqp_index;
3677 ring->io_base = q->io_base;
3680 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3684 ring->desc_cb = NULL;
3685 ring->dev = priv->dev;
3686 ring->desc_dma_addr = 0;
3687 ring->buf_size = q->buf_size;
3688 ring->desc_num = desc_num;
3689 ring->next_to_use = 0;
3690 ring->next_to_clean = 0;
3693 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3694 struct hns3_nic_priv *priv)
3696 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3697 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3700 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3702 struct hnae3_handle *h = priv->ae_handle;
3703 struct pci_dev *pdev = h->pdev;
3706 priv->ring = devm_kzalloc(&pdev->dev,
3707 array3_size(h->kinfo.num_tqps,
3708 sizeof(*priv->ring), 2),
3713 for (i = 0; i < h->kinfo.num_tqps; i++)
3714 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3719 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3724 devm_kfree(priv->dev, priv->ring);
3728 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3732 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3735 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3736 sizeof(ring->desc_cb[0]), GFP_KERNEL);
3737 if (!ring->desc_cb) {
3742 ret = hns3_alloc_desc(ring);
3744 goto out_with_desc_cb;
3746 if (!HNAE3_IS_TX_RING(ring)) {
3747 ret = hns3_alloc_ring_buffers(ring);
3755 hns3_free_desc(ring);
3757 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3758 ring->desc_cb = NULL;
3763 void hns3_fini_ring(struct hns3_enet_ring *ring)
3765 hns3_free_desc(ring);
3766 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3767 ring->desc_cb = NULL;
3768 ring->next_to_clean = 0;
3769 ring->next_to_use = 0;
3770 ring->pending_buf = 0;
3772 dev_kfree_skb_any(ring->skb);
3777 static int hns3_buf_size2type(u32 buf_size)
3783 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3786 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3789 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3792 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3795 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3798 return bd_size_type;
3801 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3803 dma_addr_t dma = ring->desc_dma_addr;
3804 struct hnae3_queue *q = ring->tqp;
3806 if (!HNAE3_IS_TX_RING(ring)) {
3807 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
3808 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3809 (u32)((dma >> 31) >> 1));
3811 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3812 hns3_buf_size2type(ring->buf_size));
3813 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3814 ring->desc_num / 8 - 1);
3817 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3819 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3820 (u32)((dma >> 31) >> 1));
3822 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3823 ring->desc_num / 8 - 1);
3827 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3829 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3832 for (i = 0; i < HNAE3_MAX_TC; i++) {
3833 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3836 if (!tc_info->enable)
3839 for (j = 0; j < tc_info->tqp_count; j++) {
3840 struct hnae3_queue *q;
3842 q = priv->ring[tc_info->tqp_offset + j].tqp;
3843 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3849 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3851 struct hnae3_handle *h = priv->ae_handle;
3852 int ring_num = h->kinfo.num_tqps * 2;
3856 for (i = 0; i < ring_num; i++) {
3857 ret = hns3_alloc_ring_memory(&priv->ring[i]);
3860 "Alloc ring memory fail! ret=%d\n", ret);
3861 goto out_when_alloc_ring_memory;
3864 u64_stats_init(&priv->ring[i].syncp);
3869 out_when_alloc_ring_memory:
3870 for (j = i - 1; j >= 0; j--)
3871 hns3_fini_ring(&priv->ring[j]);
3876 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3878 struct hnae3_handle *h = priv->ae_handle;
3881 for (i = 0; i < h->kinfo.num_tqps; i++) {
3882 hns3_fini_ring(&priv->ring[i]);
3883 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
3888 /* Set mac addr if it is configured. or leave it to the AE driver */
3889 static int hns3_init_mac_addr(struct net_device *netdev)
3891 struct hns3_nic_priv *priv = netdev_priv(netdev);
3892 struct hnae3_handle *h = priv->ae_handle;
3893 u8 mac_addr_temp[ETH_ALEN];
3896 if (h->ae_algo->ops->get_mac_addr)
3897 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3899 /* Check if the MAC address is valid, if not get a random one */
3900 if (!is_valid_ether_addr(mac_addr_temp)) {
3901 eth_hw_addr_random(netdev);
3902 dev_warn(priv->dev, "using random MAC address %pM\n",
3905 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3906 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
3909 if (h->ae_algo->ops->set_mac_addr)
3910 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3915 static int hns3_init_phy(struct net_device *netdev)
3917 struct hnae3_handle *h = hns3_get_handle(netdev);
3920 if (h->ae_algo->ops->mac_connect_phy)
3921 ret = h->ae_algo->ops->mac_connect_phy(h);
3926 static void hns3_uninit_phy(struct net_device *netdev)
3928 struct hnae3_handle *h = hns3_get_handle(netdev);
3930 if (h->ae_algo->ops->mac_disconnect_phy)
3931 h->ae_algo->ops->mac_disconnect_phy(h);
3934 static int hns3_restore_fd_rules(struct net_device *netdev)
3936 struct hnae3_handle *h = hns3_get_handle(netdev);
3939 if (h->ae_algo->ops->restore_fd_rules)
3940 ret = h->ae_algo->ops->restore_fd_rules(h);
3945 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3947 struct hnae3_handle *h = hns3_get_handle(netdev);
3949 if (h->ae_algo->ops->del_all_fd_entries)
3950 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3953 static int hns3_client_start(struct hnae3_handle *handle)
3955 if (!handle->ae_algo->ops->client_start)
3958 return handle->ae_algo->ops->client_start(handle);
3961 static void hns3_client_stop(struct hnae3_handle *handle)
3963 if (!handle->ae_algo->ops->client_stop)
3966 handle->ae_algo->ops->client_stop(handle);
3969 static void hns3_info_show(struct hns3_nic_priv *priv)
3971 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3973 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3974 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3975 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3976 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3977 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3978 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3979 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3980 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3981 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
3984 static int hns3_client_init(struct hnae3_handle *handle)
3986 struct pci_dev *pdev = handle->pdev;
3987 u16 alloc_tqps, max_rss_size;
3988 struct hns3_nic_priv *priv;
3989 struct net_device *netdev;
3992 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3994 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3998 priv = netdev_priv(netdev);
3999 priv->dev = &pdev->dev;
4000 priv->netdev = netdev;
4001 priv->ae_handle = handle;
4002 priv->tx_timeout_count = 0;
4003 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
4005 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
4007 handle->kinfo.netdev = netdev;
4008 handle->priv = (void *)priv;
4010 hns3_init_mac_addr(netdev);
4012 hns3_set_default_feature(netdev);
4014 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
4015 netdev->priv_flags |= IFF_UNICAST_FLT;
4016 netdev->netdev_ops = &hns3_nic_netdev_ops;
4017 SET_NETDEV_DEV(netdev, &pdev->dev);
4018 hns3_ethtool_set_ops(netdev);
4020 /* Carrier off reporting is important to ethtool even BEFORE open */
4021 netif_carrier_off(netdev);
4023 ret = hns3_get_ring_config(priv);
4026 goto out_get_ring_cfg;
4029 ret = hns3_nic_alloc_vector_data(priv);
4032 goto out_alloc_vector_data;
4035 ret = hns3_nic_init_vector_data(priv);
4038 goto out_init_vector_data;
4041 ret = hns3_init_all_ring(priv);
4047 ret = hns3_init_phy(netdev);
4051 ret = register_netdev(netdev);
4053 dev_err(priv->dev, "probe register netdev fail!\n");
4054 goto out_reg_netdev_fail;
4057 /* the device can work without cpu rmap, only aRFS needs it */
4058 ret = hns3_set_rx_cpu_rmap(netdev);
4060 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4062 ret = hns3_nic_init_irq(priv);
4064 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4065 hns3_free_rx_cpu_rmap(netdev);
4066 goto out_init_irq_fail;
4069 ret = hns3_client_start(handle);
4071 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4072 goto out_client_start;
4075 hns3_dcbnl_setup(handle);
4077 hns3_dbg_init(handle);
4079 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4080 netdev->max_mtu = HNS3_MAX_MTU;
4082 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4084 if (netif_msg_drv(handle))
4085 hns3_info_show(priv);
4090 hns3_free_rx_cpu_rmap(netdev);
4091 hns3_nic_uninit_irq(priv);
4093 unregister_netdev(netdev);
4094 out_reg_netdev_fail:
4095 hns3_uninit_phy(netdev);
4097 hns3_uninit_all_ring(priv);
4099 hns3_nic_uninit_vector_data(priv);
4100 out_init_vector_data:
4101 hns3_nic_dealloc_vector_data(priv);
4102 out_alloc_vector_data:
4105 priv->ae_handle = NULL;
4106 free_netdev(netdev);
4110 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4112 struct net_device *netdev = handle->kinfo.netdev;
4113 struct hns3_nic_priv *priv = netdev_priv(netdev);
4116 hns3_remove_hw_addr(netdev);
4118 if (netdev->reg_state != NETREG_UNINITIALIZED)
4119 unregister_netdev(netdev);
4121 hns3_client_stop(handle);
4123 hns3_uninit_phy(netdev);
4125 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4126 netdev_warn(netdev, "already uninitialized\n");
4127 goto out_netdev_free;
4130 hns3_free_rx_cpu_rmap(netdev);
4132 hns3_nic_uninit_irq(priv);
4134 hns3_del_all_fd_rules(netdev, true);
4136 hns3_clear_all_ring(handle, true);
4138 hns3_nic_uninit_vector_data(priv);
4140 hns3_nic_dealloc_vector_data(priv);
4142 ret = hns3_uninit_all_ring(priv);
4144 netdev_err(netdev, "uninit ring error\n");
4146 hns3_put_ring_config(priv);
4148 hns3_dbg_uninit(handle);
4151 free_netdev(netdev);
4154 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4156 struct net_device *netdev = handle->kinfo.netdev;
4162 netif_carrier_on(netdev);
4163 netif_tx_wake_all_queues(netdev);
4164 if (netif_msg_link(handle))
4165 netdev_info(netdev, "link up\n");
4167 netif_carrier_off(netdev);
4168 netif_tx_stop_all_queues(netdev);
4169 if (netif_msg_link(handle))
4170 netdev_info(netdev, "link down\n");
4174 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4176 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4177 struct net_device *ndev = kinfo->netdev;
4179 if (tc > HNAE3_MAX_TC)
4185 return hns3_nic_set_real_num_queue(ndev);
4188 static int hns3_recover_hw_addr(struct net_device *ndev)
4190 struct netdev_hw_addr_list *list;
4191 struct netdev_hw_addr *ha, *tmp;
4194 netif_addr_lock_bh(ndev);
4195 /* go through and sync uc_addr entries to the device */
4197 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4198 ret = hns3_nic_uc_sync(ndev, ha->addr);
4203 /* go through and sync mc_addr entries to the device */
4205 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4206 ret = hns3_nic_mc_sync(ndev, ha->addr);
4212 netif_addr_unlock_bh(ndev);
4216 static void hns3_remove_hw_addr(struct net_device *netdev)
4218 struct netdev_hw_addr_list *list;
4219 struct netdev_hw_addr *ha, *tmp;
4221 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
4223 netif_addr_lock_bh(netdev);
4224 /* go through and unsync uc_addr entries to the device */
4226 list_for_each_entry_safe(ha, tmp, &list->list, list)
4227 hns3_nic_uc_unsync(netdev, ha->addr);
4229 /* go through and unsync mc_addr entries to the device */
4231 list_for_each_entry_safe(ha, tmp, &list->list, list)
4232 if (ha->refcount > 1)
4233 hns3_nic_mc_unsync(netdev, ha->addr);
4235 netif_addr_unlock_bh(netdev);
4238 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
4240 while (ring->next_to_clean != ring->next_to_use) {
4241 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
4242 hns3_free_buffer_detach(ring, ring->next_to_clean);
4243 ring_ptr_move_fw(ring, next_to_clean);
4247 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4249 struct hns3_desc_cb res_cbs;
4252 while (ring->next_to_use != ring->next_to_clean) {
4253 /* When a buffer is not reused, it's memory has been
4254 * freed in hns3_handle_rx_bd or will be freed by
4255 * stack, so we need to replace the buffer here.
4257 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4258 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4260 u64_stats_update_begin(&ring->syncp);
4261 ring->stats.sw_err_cnt++;
4262 u64_stats_update_end(&ring->syncp);
4263 /* if alloc new buffer fail, exit directly
4264 * and reclear in up flow.
4266 netdev_warn(ring_to_netdev(ring),
4267 "reserve buffer map failed, ret = %d\n",
4271 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
4273 ring_ptr_move_fw(ring, next_to_use);
4276 /* Free the pending skb in rx ring */
4278 dev_kfree_skb_any(ring->skb);
4280 ring->pending_buf = 0;
4286 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
4288 while (ring->next_to_use != ring->next_to_clean) {
4289 /* When a buffer is not reused, it's memory has been
4290 * freed in hns3_handle_rx_bd or will be freed by
4291 * stack, so only need to unmap the buffer here.
4293 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4294 hns3_unmap_buffer(ring,
4295 &ring->desc_cb[ring->next_to_use]);
4296 ring->desc_cb[ring->next_to_use].dma = 0;
4299 ring_ptr_move_fw(ring, next_to_use);
4303 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
4305 struct net_device *ndev = h->kinfo.netdev;
4306 struct hns3_nic_priv *priv = netdev_priv(ndev);
4309 for (i = 0; i < h->kinfo.num_tqps; i++) {
4310 struct hns3_enet_ring *ring;
4312 ring = &priv->ring[i];
4313 hns3_clear_tx_ring(ring);
4315 ring = &priv->ring[i + h->kinfo.num_tqps];
4316 /* Continue to clear other rings even if clearing some
4320 hns3_force_clear_rx_ring(ring);
4322 hns3_clear_rx_ring(ring);
4326 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4328 struct net_device *ndev = h->kinfo.netdev;
4329 struct hns3_nic_priv *priv = netdev_priv(ndev);
4330 struct hns3_enet_ring *rx_ring;
4334 for (i = 0; i < h->kinfo.num_tqps; i++) {
4335 ret = h->ae_algo->ops->reset_queue(h, i);
4339 hns3_init_ring_hw(&priv->ring[i]);
4341 /* We need to clear tx ring here because self test will
4342 * use the ring and will not run down before up
4344 hns3_clear_tx_ring(&priv->ring[i]);
4345 priv->ring[i].next_to_clean = 0;
4346 priv->ring[i].next_to_use = 0;
4348 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
4349 hns3_init_ring_hw(rx_ring);
4350 ret = hns3_clear_rx_ring(rx_ring);
4354 /* We can not know the hardware head and tail when this
4355 * function is called in reset flow, so we reuse all desc.
4357 for (j = 0; j < rx_ring->desc_num; j++)
4358 hns3_reuse_buffer(rx_ring, j);
4360 rx_ring->next_to_clean = 0;
4361 rx_ring->next_to_use = 0;
4364 hns3_init_tx_ring_tc(priv);
4369 static void hns3_store_coal(struct hns3_nic_priv *priv)
4371 /* ethtool only support setting and querying one coal
4372 * configuration for now, so save the vector 0' coal
4373 * configuration here in order to restore it.
4375 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4376 sizeof(struct hns3_enet_coalesce));
4377 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4378 sizeof(struct hns3_enet_coalesce));
4381 static void hns3_restore_coal(struct hns3_nic_priv *priv)
4383 u16 vector_num = priv->vector_num;
4386 for (i = 0; i < vector_num; i++) {
4387 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4388 sizeof(struct hns3_enet_coalesce));
4389 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4390 sizeof(struct hns3_enet_coalesce));
4394 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4396 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4397 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4398 struct net_device *ndev = kinfo->netdev;
4399 struct hns3_nic_priv *priv = netdev_priv(ndev);
4401 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4404 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4405 * from table space. Hence, for function reset software intervention is
4406 * required to delete the entries
4408 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4409 hns3_remove_hw_addr(ndev);
4410 hns3_del_all_fd_rules(ndev, false);
4413 if (!netif_running(ndev))
4416 return hns3_nic_net_stop(ndev);
4419 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4421 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4422 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4425 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4427 if (netif_running(kinfo->netdev)) {
4428 ret = hns3_nic_net_open(kinfo->netdev);
4430 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4431 netdev_err(kinfo->netdev,
4432 "net up fail, ret=%d!\n", ret);
4440 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4442 struct net_device *netdev = handle->kinfo.netdev;
4443 struct hns3_nic_priv *priv = netdev_priv(netdev);
4446 /* Carrier off reporting is important to ethtool even BEFORE open */
4447 netif_carrier_off(netdev);
4449 ret = hns3_get_ring_config(priv);
4453 ret = hns3_nic_alloc_vector_data(priv);
4457 hns3_restore_coal(priv);
4459 ret = hns3_nic_init_vector_data(priv);
4461 goto err_dealloc_vector;
4463 ret = hns3_init_all_ring(priv);
4465 goto err_uninit_vector;
4467 /* the device can work without cpu rmap, only aRFS needs it */
4468 ret = hns3_set_rx_cpu_rmap(netdev);
4470 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4472 ret = hns3_nic_init_irq(priv);
4474 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4475 hns3_free_rx_cpu_rmap(netdev);
4476 goto err_init_irq_fail;
4479 ret = hns3_client_start(handle);
4481 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4482 goto err_client_start_fail;
4485 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4489 err_client_start_fail:
4490 hns3_free_rx_cpu_rmap(netdev);
4491 hns3_nic_uninit_irq(priv);
4493 hns3_uninit_all_ring(priv);
4495 hns3_nic_uninit_vector_data(priv);
4497 hns3_nic_dealloc_vector_data(priv);
4499 hns3_put_ring_config(priv);
4504 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4506 struct net_device *netdev = handle->kinfo.netdev;
4507 bool vlan_filter_enable;
4510 ret = hns3_init_mac_addr(netdev);
4514 ret = hns3_recover_hw_addr(netdev);
4518 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4522 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4523 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4525 if (handle->ae_algo->ops->restore_vlan_table)
4526 handle->ae_algo->ops->restore_vlan_table(handle);
4528 return hns3_restore_fd_rules(netdev);
4531 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4533 struct net_device *netdev = handle->kinfo.netdev;
4534 struct hns3_nic_priv *priv = netdev_priv(netdev);
4537 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4538 netdev_warn(netdev, "already uninitialized\n");
4542 hns3_free_rx_cpu_rmap(netdev);
4543 hns3_nic_uninit_irq(priv);
4544 hns3_clear_all_ring(handle, true);
4545 hns3_reset_tx_queue(priv->ae_handle);
4547 hns3_nic_uninit_vector_data(priv);
4549 hns3_store_coal(priv);
4551 hns3_nic_dealloc_vector_data(priv);
4553 ret = hns3_uninit_all_ring(priv);
4555 netdev_err(netdev, "uninit ring error\n");
4557 hns3_put_ring_config(priv);
4562 static int hns3_reset_notify(struct hnae3_handle *handle,
4563 enum hnae3_reset_notify_type type)
4568 case HNAE3_UP_CLIENT:
4569 ret = hns3_reset_notify_up_enet(handle);
4571 case HNAE3_DOWN_CLIENT:
4572 ret = hns3_reset_notify_down_enet(handle);
4574 case HNAE3_INIT_CLIENT:
4575 ret = hns3_reset_notify_init_enet(handle);
4577 case HNAE3_UNINIT_CLIENT:
4578 ret = hns3_reset_notify_uninit_enet(handle);
4580 case HNAE3_RESTORE_CLIENT:
4581 ret = hns3_reset_notify_restore_enet(handle);
4590 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4591 bool rxfh_configured)
4595 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4598 dev_err(&handle->pdev->dev,
4599 "Change tqp num(%u) fail.\n", new_tqp_num);
4603 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4607 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4609 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4614 int hns3_set_channels(struct net_device *netdev,
4615 struct ethtool_channels *ch)
4617 struct hnae3_handle *h = hns3_get_handle(netdev);
4618 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4619 bool rxfh_configured = netif_is_rxfh_configured(netdev);
4620 u32 new_tqp_num = ch->combined_count;
4624 if (hns3_nic_resetting(netdev))
4627 if (ch->rx_count || ch->tx_count)
4630 if (new_tqp_num > hns3_get_max_available_channels(h) ||
4632 dev_err(&netdev->dev,
4633 "Change tqps fail, the tqp range is from 1 to %u",
4634 hns3_get_max_available_channels(h));
4638 if (kinfo->rss_size == new_tqp_num)
4641 netif_dbg(h, drv, netdev,
4642 "set channels: tqp_num=%u, rxfh=%d\n",
4643 new_tqp_num, rxfh_configured);
4645 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4649 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4653 org_tqp_num = h->kinfo.num_tqps;
4654 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
4659 "Change channels fail, revert to old value\n");
4660 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4663 "revert to old channel fail\n");
4673 static const struct hns3_hw_error_info hns3_hw_err[] = {
4674 { .type = HNAE3_PPU_POISON_ERROR,
4675 .msg = "PPU poison" },
4676 { .type = HNAE3_CMDQ_ECC_ERROR,
4677 .msg = "IMP CMDQ error" },
4678 { .type = HNAE3_IMP_RD_POISON_ERROR,
4679 .msg = "IMP RD poison" },
4682 static void hns3_process_hw_error(struct hnae3_handle *handle,
4683 enum hnae3_hw_error_type type)
4687 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4688 if (hns3_hw_err[i].type == type) {
4689 dev_err(&handle->pdev->dev, "Detected %s!\n",
4690 hns3_hw_err[i].msg);
4696 static const struct hnae3_client_ops client_ops = {
4697 .init_instance = hns3_client_init,
4698 .uninit_instance = hns3_client_uninit,
4699 .link_status_change = hns3_link_status_change,
4700 .setup_tc = hns3_client_setup_tc,
4701 .reset_notify = hns3_reset_notify,
4702 .process_hw_error = hns3_process_hw_error,
4705 /* hns3_init_module - Driver registration routine
4706 * hns3_init_module is the first routine called when the driver is
4707 * loaded. All it does is register with the PCI subsystem.
4709 static int __init hns3_init_module(void)
4713 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4714 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4716 client.type = HNAE3_CLIENT_KNIC;
4717 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
4720 client.ops = &client_ops;
4722 INIT_LIST_HEAD(&client.node);
4724 hns3_dbg_register_debugfs(hns3_driver_name);
4726 ret = hnae3_register_client(&client);
4728 goto err_reg_client;
4730 ret = pci_register_driver(&hns3_driver);
4732 goto err_reg_driver;
4737 hnae3_unregister_client(&client);
4739 hns3_dbg_unregister_debugfs();
4742 module_init(hns3_init_module);
4744 /* hns3_exit_module - Driver exit cleanup routine
4745 * hns3_exit_module is called just before the driver is removed
4748 static void __exit hns3_exit_module(void)
4750 pci_unregister_driver(&hns3_driver);
4751 hnae3_unregister_client(&client);
4752 hns3_dbg_unregister_debugfs();
4754 module_exit(hns3_exit_module);
4756 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4757 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4758 MODULE_LICENSE("GPL");
4759 MODULE_ALIAS("pci:hns-nic");
4760 MODULE_VERSION(HNS3_MOD_VERSION);