1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #include <linux/if_vlan.h>
9 #include <linux/ipv6.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/aer.h>
13 #include <linux/skbuff.h>
14 #include <linux/sctp.h>
15 #include <linux/vermagic.h>
17 #include <net/pkt_cls.h>
19 #include <net/vxlan.h>
22 #include "hns3_enet.h"
24 static void hns3_clear_all_ring(struct hnae3_handle *h);
25 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
26 static void hns3_remove_hw_addr(struct net_device *netdev);
28 static const char hns3_driver_name[] = "hns3";
29 const char hns3_driver_version[] = VERMAGIC_STRING;
30 static const char hns3_driver_string[] =
31 "Hisilicon Ethernet Network Driver for Hip08 Family";
32 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
33 static struct hnae3_client client;
35 /* hns3_pci_tbl - PCI Device ID Table
37 * Last entry must be all 0s
39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
40 * Class, Class Mask, private data (not used) }
42 static const struct pci_device_id hns3_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
58 /* required last entry */
61 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
63 static irqreturn_t hns3_irq_handle(int irq, void *vector)
65 struct hns3_enet_tqp_vector *tqp_vector = vector;
67 napi_schedule(&tqp_vector->napi);
72 /* This callback function is used to set affinity changes to the irq affinity
73 * masks when the irq_set_affinity_notifier function is used.
75 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
76 const cpumask_t *mask)
78 struct hns3_enet_tqp_vector *tqp_vectors =
79 container_of(notify, struct hns3_enet_tqp_vector,
82 tqp_vectors->affinity_mask = *mask;
85 static void hns3_nic_irq_affinity_release(struct kref *ref)
89 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
91 struct hns3_enet_tqp_vector *tqp_vectors;
94 for (i = 0; i < priv->vector_num; i++) {
95 tqp_vectors = &priv->tqp_vector[i];
97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
100 /* clear the affinity notifier and affinity mask */
101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
104 /* release the irq resource */
105 free_irq(tqp_vectors->vector_irq, tqp_vectors);
106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
110 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
112 struct hns3_enet_tqp_vector *tqp_vectors;
113 int txrx_int_idx = 0;
119 for (i = 0; i < priv->vector_num; i++) {
120 tqp_vectors = &priv->tqp_vector[i];
122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "TxRx",
130 } else if (tqp_vectors->rx_group.ring) {
131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
132 "%s-%s-%d", priv->netdev->name, "Rx",
134 } else if (tqp_vectors->tx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Tx",
139 /* Skip this unused q_vector */
143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
149 netdev_err(priv->netdev, "request irq(%d) fail\n",
150 tqp_vectors->vector_irq);
154 tqp_vectors->affinity_notify.notify =
155 hns3_nic_irq_affinity_notify;
156 tqp_vectors->affinity_notify.release =
157 hns3_nic_irq_affinity_release;
158 irq_set_affinity_notifier(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_notify);
160 irq_set_affinity_hint(tqp_vectors->vector_irq,
161 &tqp_vectors->affinity_mask);
163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
169 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
172 writel(mask_en, tqp_vector->mask_addr);
175 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
177 napi_enable(&tqp_vector->napi);
180 hns3_mask_vector_irq(tqp_vector, 1);
183 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
186 hns3_mask_vector_irq(tqp_vector, 0);
188 disable_irq(tqp_vector->vector_irq);
189 napi_disable(&tqp_vector->napi);
192 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
197 /* this defines the configuration for RL (Interrupt Rate Limiter).
198 * Rl defines rate of interrupts i.e. number of interrupts-per-second
199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
203 !tqp_vector->rx_group.coal.gl_adapt_enable)
204 /* According to the hardware, the range of rl_reg is
205 * 0-59 and the unit is 4.
207 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
212 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
220 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
228 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
229 struct hns3_nic_priv *priv)
231 /* initialize the configuration for interrupt coalescing.
232 * 1. GL (Interrupt Gap Limiter)
233 * 2. RL (Interrupt Rate Limiter)
236 /* Default: enable interrupt coalescing self-adaptive and GL */
237 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
247 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
248 struct hns3_nic_priv *priv)
250 struct hnae3_handle *h = priv->ae_handle;
252 hns3_set_vector_coalesce_tx_gl(tqp_vector,
253 tqp_vector->tx_group.coal.int_gl);
254 hns3_set_vector_coalesce_rx_gl(tqp_vector,
255 tqp_vector->rx_group.coal.int_gl);
256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
259 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
261 struct hnae3_handle *h = hns3_get_handle(netdev);
262 struct hnae3_knic_private_info *kinfo = &h->kinfo;
263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
266 if (kinfo->num_tc <= 1) {
267 netdev_reset_tc(netdev);
269 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
272 "netdev_set_num_tc fail, ret=%d!\n", ret);
276 for (i = 0; i < HNAE3_MAX_TC; i++) {
277 if (!kinfo->tc_info[i].enable)
280 netdev_set_tc_queue(netdev,
281 kinfo->tc_info[i].tc,
282 kinfo->tc_info[i].tqp_count,
283 kinfo->tc_info[i].tqp_offset);
287 ret = netif_set_real_num_tx_queues(netdev, queue_size);
290 "netif_set_real_num_tx_queues fail, ret=%d!\n",
295 ret = netif_set_real_num_rx_queues(netdev, queue_size);
298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
305 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
307 u16 alloc_tqps, max_rss_size, rss_size;
309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
310 rss_size = alloc_tqps / h->kinfo.num_tc;
312 return min_t(u16, rss_size, max_rss_size);
315 static void hns3_tqp_enable(struct hnae3_queue *tqp)
319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
320 rcb_reg |= BIT(HNS3_RING_EN_B);
321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
324 static void hns3_tqp_disable(struct hnae3_queue *tqp)
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg &= ~BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
333 static int hns3_nic_net_up(struct net_device *netdev)
335 struct hns3_nic_priv *priv = netdev_priv(netdev);
336 struct hnae3_handle *h = priv->ae_handle;
340 ret = hns3_nic_reset_all_ring(h);
344 /* get irq resource for all vectors */
345 ret = hns3_nic_init_irq(priv);
347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
351 /* enable the vectors */
352 for (i = 0; i < priv->vector_num; i++)
353 hns3_vector_enable(&priv->tqp_vector[i]);
356 for (j = 0; j < h->kinfo.num_tqps; j++)
357 hns3_tqp_enable(h->kinfo.tqp[j]);
359 /* start the ae_dev */
360 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
364 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
370 hns3_tqp_disable(h->kinfo.tqp[j]);
372 for (j = i - 1; j >= 0; j--)
373 hns3_vector_disable(&priv->tqp_vector[j]);
375 hns3_nic_uninit_irq(priv);
380 static int hns3_nic_net_open(struct net_device *netdev)
382 struct hns3_nic_priv *priv = netdev_priv(netdev);
383 struct hnae3_handle *h = hns3_get_handle(netdev);
384 struct hnae3_knic_private_info *kinfo;
387 if (hns3_nic_resetting(netdev))
390 netif_carrier_off(netdev);
392 ret = hns3_nic_set_real_num_queue(netdev);
396 ret = hns3_nic_net_up(netdev);
399 "hns net up fail, ret=%d!\n", ret);
404 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
405 netdev_set_prio_tc_map(netdev, i,
409 if (h->ae_algo->ops->set_timer_task)
410 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
415 static void hns3_nic_net_down(struct net_device *netdev)
417 struct hns3_nic_priv *priv = netdev_priv(netdev);
418 struct hnae3_handle *h = hns3_get_handle(netdev);
419 const struct hnae3_ae_ops *ops;
422 /* disable vectors */
423 for (i = 0; i < priv->vector_num; i++)
424 hns3_vector_disable(&priv->tqp_vector[i]);
427 for (i = 0; i < h->kinfo.num_tqps; i++)
428 hns3_tqp_disable(h->kinfo.tqp[i]);
431 ops = priv->ae_handle->ae_algo->ops;
433 ops->stop(priv->ae_handle);
435 /* free irq resources */
436 hns3_nic_uninit_irq(priv);
438 hns3_clear_all_ring(priv->ae_handle);
441 static int hns3_nic_net_stop(struct net_device *netdev)
443 struct hns3_nic_priv *priv = netdev_priv(netdev);
444 struct hnae3_handle *h = hns3_get_handle(netdev);
446 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
449 if (h->ae_algo->ops->set_timer_task)
450 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
452 netif_tx_stop_all_queues(netdev);
453 netif_carrier_off(netdev);
455 hns3_nic_net_down(netdev);
460 static int hns3_nic_uc_sync(struct net_device *netdev,
461 const unsigned char *addr)
463 struct hnae3_handle *h = hns3_get_handle(netdev);
465 if (h->ae_algo->ops->add_uc_addr)
466 return h->ae_algo->ops->add_uc_addr(h, addr);
471 static int hns3_nic_uc_unsync(struct net_device *netdev,
472 const unsigned char *addr)
474 struct hnae3_handle *h = hns3_get_handle(netdev);
476 if (h->ae_algo->ops->rm_uc_addr)
477 return h->ae_algo->ops->rm_uc_addr(h, addr);
482 static int hns3_nic_mc_sync(struct net_device *netdev,
483 const unsigned char *addr)
485 struct hnae3_handle *h = hns3_get_handle(netdev);
487 if (h->ae_algo->ops->add_mc_addr)
488 return h->ae_algo->ops->add_mc_addr(h, addr);
493 static int hns3_nic_mc_unsync(struct net_device *netdev,
494 const unsigned char *addr)
496 struct hnae3_handle *h = hns3_get_handle(netdev);
498 if (h->ae_algo->ops->rm_mc_addr)
499 return h->ae_algo->ops->rm_mc_addr(h, addr);
504 static u8 hns3_get_netdev_flags(struct net_device *netdev)
508 if (netdev->flags & IFF_PROMISC) {
509 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
511 flags |= HNAE3_VLAN_FLTR;
512 if (netdev->flags & IFF_ALLMULTI)
513 flags |= HNAE3_USER_MPE;
519 static void hns3_nic_set_rx_mode(struct net_device *netdev)
521 struct hnae3_handle *h = hns3_get_handle(netdev);
525 new_flags = hns3_get_netdev_flags(netdev);
527 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
529 netdev_err(netdev, "sync uc address fail\n");
531 new_flags |= HNAE3_OVERFLOW_UPE;
534 if (netdev->flags & IFF_MULTICAST) {
535 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
538 netdev_err(netdev, "sync mc address fail\n");
540 new_flags |= HNAE3_OVERFLOW_MPE;
544 /* User mode Promisc mode enable and vlan filtering is disabled to
545 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
546 * vlan fitering is enabled
548 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
549 h->netdev_flags = new_flags;
550 hns3_update_promisc_mode(netdev, new_flags);
553 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
555 struct hns3_nic_priv *priv = netdev_priv(netdev);
556 struct hnae3_handle *h = priv->ae_handle;
558 if (h->ae_algo->ops->set_promisc_mode) {
559 return h->ae_algo->ops->set_promisc_mode(h,
560 promisc_flags & HNAE3_UPE,
561 promisc_flags & HNAE3_MPE);
567 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
569 struct hns3_nic_priv *priv = netdev_priv(netdev);
570 struct hnae3_handle *h = priv->ae_handle;
573 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
574 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
575 if (enable != last_state) {
578 enable ? "enable" : "disable");
579 h->ae_algo->ops->enable_vlan_filter(h, enable);
584 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
585 u16 *mss, u32 *type_cs_vlan_tso)
587 u32 l4_offset, hdr_len;
588 union l3_hdr_info l3;
589 union l4_hdr_info l4;
593 if (!skb_is_gso(skb))
596 ret = skb_cow_head(skb, 0);
600 l3.hdr = skb_network_header(skb);
601 l4.hdr = skb_transport_header(skb);
603 /* Software should clear the IPv4's checksum field when tso is
606 if (l3.v4->version == 4)
610 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
613 SKB_GSO_UDP_TUNNEL_CSUM)) {
614 if ((!(skb_shinfo(skb)->gso_type &
616 (skb_shinfo(skb)->gso_type &
617 SKB_GSO_UDP_TUNNEL_CSUM)) {
618 /* Software should clear the udp's checksum
619 * field when tso is needed.
623 /* reset l3&l4 pointers from outer to inner headers */
624 l3.hdr = skb_inner_network_header(skb);
625 l4.hdr = skb_inner_transport_header(skb);
627 /* Software should clear the IPv4's checksum field when
630 if (l3.v4->version == 4)
634 /* normal or tunnel packet*/
635 l4_offset = l4.hdr - skb->data;
636 hdr_len = (l4.tcp->doff * 4) + l4_offset;
638 /* remove payload length from inner pseudo checksum when tso*/
639 l4_paylen = skb->len - l4_offset;
640 csum_replace_by_diff(&l4.tcp->check,
641 (__force __wsum)htonl(l4_paylen));
643 /* find the txbd field values */
644 *paylen = skb->len - hdr_len;
645 hnae3_set_bit(*type_cs_vlan_tso,
648 /* get MSS for TSO */
649 *mss = skb_shinfo(skb)->gso_size;
654 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
662 unsigned char *l4_hdr;
663 unsigned char *exthdr;
667 /* find outer header point */
668 l3.hdr = skb_network_header(skb);
669 l4_hdr = skb_transport_header(skb);
671 if (skb->protocol == htons(ETH_P_IPV6)) {
672 exthdr = l3.hdr + sizeof(*l3.v6);
673 l4_proto_tmp = l3.v6->nexthdr;
674 if (l4_hdr != exthdr)
675 ipv6_skip_exthdr(skb, exthdr - skb->data,
676 &l4_proto_tmp, &frag_off);
677 } else if (skb->protocol == htons(ETH_P_IP)) {
678 l4_proto_tmp = l3.v4->protocol;
683 *ol4_proto = l4_proto_tmp;
686 if (!skb->encapsulation) {
691 /* find inner header point */
692 l3.hdr = skb_inner_network_header(skb);
693 l4_hdr = skb_inner_transport_header(skb);
695 if (l3.v6->version == 6) {
696 exthdr = l3.hdr + sizeof(*l3.v6);
697 l4_proto_tmp = l3.v6->nexthdr;
698 if (l4_hdr != exthdr)
699 ipv6_skip_exthdr(skb, exthdr - skb->data,
700 &l4_proto_tmp, &frag_off);
701 } else if (l3.v4->version == 4) {
702 l4_proto_tmp = l3.v4->protocol;
705 *il4_proto = l4_proto_tmp;
710 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
711 u8 il4_proto, u32 *type_cs_vlan_tso,
712 u32 *ol_type_vlan_len_msec)
722 struct gre_base_hdr *gre;
725 unsigned char *l2_hdr;
726 u8 l4_proto = ol4_proto;
733 l3.hdr = skb_network_header(skb);
734 l4.hdr = skb_transport_header(skb);
736 /* compute L2 header size for normal packet, defined in 2 Bytes */
737 l2_len = l3.hdr - skb->data;
738 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
739 HNS3_TXD_L2LEN_S, l2_len >> 1);
742 if (skb->encapsulation) {
743 /* compute OL2 header size, defined in 2 Bytes */
745 hnae3_set_field(*ol_type_vlan_len_msec,
747 HNS3_TXD_L2LEN_S, ol2_len >> 1);
749 /* compute OL3 header size, defined in 4 Bytes */
750 ol3_len = l4.hdr - l3.hdr;
751 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
752 HNS3_TXD_L3LEN_S, ol3_len >> 2);
754 /* MAC in UDP, MAC in GRE (0x6558)*/
755 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
756 /* switch MAC header ptr from outer to inner header.*/
757 l2_hdr = skb_inner_mac_header(skb);
759 /* compute OL4 header size, defined in 4 Bytes. */
760 ol4_len = l2_hdr - l4.hdr;
761 hnae3_set_field(*ol_type_vlan_len_msec,
762 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
765 /* switch IP header ptr from outer to inner header */
766 l3.hdr = skb_inner_network_header(skb);
768 /* compute inner l2 header size, defined in 2 Bytes. */
769 l2_len = l3.hdr - l2_hdr;
770 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
771 HNS3_TXD_L2LEN_S, l2_len >> 1);
773 /* skb packet types not supported by hardware,
774 * txbd len fild doesn't be filled.
779 /* switch L4 header pointer from outer to inner */
780 l4.hdr = skb_inner_transport_header(skb);
782 l4_proto = il4_proto;
785 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
786 l3_len = l4.hdr - l3.hdr;
787 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
788 HNS3_TXD_L3LEN_S, l3_len >> 2);
790 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
793 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
794 HNS3_TXD_L4LEN_S, l4.tcp->doff);
797 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
799 (sizeof(struct sctphdr) >> 2));
802 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
804 (sizeof(struct udphdr) >> 2));
807 /* skb packet types not supported by hardware,
808 * txbd len fild doesn't be filled.
814 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
815 * and it is udp packet, which has a dest port as the IANA assigned.
816 * the hardware is expected to do the checksum offload, but the
817 * hardware will not do the checksum offload when udp dest port is
820 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
822 #define IANA_VXLAN_PORT 4789
826 struct gre_base_hdr *gre;
830 l4.hdr = skb_transport_header(skb);
832 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
835 skb_checksum_help(skb);
840 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
841 u8 il4_proto, u32 *type_cs_vlan_tso,
842 u32 *ol_type_vlan_len_msec)
849 u32 l4_proto = ol4_proto;
851 l3.hdr = skb_network_header(skb);
853 /* define OL3 type and tunnel type(OL4).*/
854 if (skb->encapsulation) {
855 /* define outer network header type.*/
856 if (skb->protocol == htons(ETH_P_IP)) {
858 hnae3_set_field(*ol_type_vlan_len_msec,
861 HNS3_OL3T_IPV4_CSUM);
863 hnae3_set_field(*ol_type_vlan_len_msec,
866 HNS3_OL3T_IPV4_NO_CSUM);
868 } else if (skb->protocol == htons(ETH_P_IPV6)) {
869 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
870 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
873 /* define tunnel type(OL4).*/
876 hnae3_set_field(*ol_type_vlan_len_msec,
879 HNS3_TUN_MAC_IN_UDP);
882 hnae3_set_field(*ol_type_vlan_len_msec,
888 /* drop the skb tunnel packet if hardware don't support,
889 * because hardware can't calculate csum when TSO.
894 /* the stack computes the IP header already,
895 * driver calculate l4 checksum when not TSO.
897 skb_checksum_help(skb);
901 l3.hdr = skb_inner_network_header(skb);
902 l4_proto = il4_proto;
905 if (l3.v4->version == 4) {
906 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
907 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
909 /* the stack computes the IP header already, the only time we
910 * need the hardware to recompute it is in the case of TSO.
913 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
914 } else if (l3.v6->version == 6) {
915 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
916 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
921 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
922 hnae3_set_field(*type_cs_vlan_tso,
928 if (hns3_tunnel_csum_bug(skb))
931 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
932 hnae3_set_field(*type_cs_vlan_tso,
938 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
939 hnae3_set_field(*type_cs_vlan_tso,
945 /* drop the skb tunnel packet if hardware don't support,
946 * because hardware can't calculate csum when TSO.
951 /* the stack computes the IP header already,
952 * driver calculate l4 checksum when not TSO.
954 skb_checksum_help(skb);
961 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
963 /* Config bd buffer end */
964 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
965 HNS3_TXD_BDTYPE_S, 0);
966 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
967 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
968 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
971 static int hns3_fill_desc_vtags(struct sk_buff *skb,
972 struct hns3_enet_ring *tx_ring,
973 u32 *inner_vlan_flag,
978 #define HNS3_TX_VLAN_PRIO_SHIFT 13
980 if (skb->protocol == htons(ETH_P_8021Q) &&
981 !(tx_ring->tqp->handle->kinfo.netdev->features &
982 NETIF_F_HW_VLAN_CTAG_TX)) {
983 /* When HW VLAN acceleration is turned off, and the stack
984 * sets the protocol to 802.1q, the driver just need to
985 * set the protocol to the encapsulated ethertype.
987 skb->protocol = vlan_get_protocol(skb);
991 if (skb_vlan_tag_present(skb)) {
994 vlan_tag = skb_vlan_tag_get(skb);
995 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
997 /* Based on hw strategy, use out_vtag in two layer tag case,
998 * and use inner_vtag in one tag case.
1000 if (skb->protocol == htons(ETH_P_8021Q)) {
1001 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
1002 *out_vtag = vlan_tag;
1004 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
1005 *inner_vtag = vlan_tag;
1007 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1008 struct vlan_ethhdr *vhdr;
1011 rc = skb_cow_head(skb, 0);
1014 vhdr = (struct vlan_ethhdr *)skb->data;
1015 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1016 << HNS3_TX_VLAN_PRIO_SHIFT);
1019 skb->protocol = vlan_get_protocol(skb);
1023 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1024 int size, int frag_end, enum hns_desc_type type)
1026 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1027 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1028 struct device *dev = ring_to_dev(ring);
1029 u32 ol_type_vlan_len_msec = 0;
1030 u16 bdtp_fe_sc_vld_ra_ri = 0;
1031 struct skb_frag_struct *frag;
1032 unsigned int frag_buf_num;
1033 u32 type_cs_vlan_tso = 0;
1034 struct sk_buff *skb;
1046 if (type == DESC_TYPE_SKB) {
1047 skb = (struct sk_buff *)priv;
1050 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1051 &ol_type_vlan_len_msec,
1052 &inner_vtag, &out_vtag);
1056 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1057 skb_reset_mac_len(skb);
1059 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1062 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
1064 &ol_type_vlan_len_msec);
1065 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
1067 &ol_type_vlan_len_msec);
1071 ret = hns3_set_tso(skb, &paylen, &mss,
1078 desc->tx.ol_type_vlan_len_msec =
1079 cpu_to_le32(ol_type_vlan_len_msec);
1080 desc->tx.type_cs_vlan_tso_len =
1081 cpu_to_le32(type_cs_vlan_tso);
1082 desc->tx.paylen = cpu_to_le32(paylen);
1083 desc->tx.mss = cpu_to_le16(mss);
1084 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1085 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1087 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1089 frag = (struct skb_frag_struct *)priv;
1090 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1093 if (dma_mapping_error(ring->dev, dma)) {
1094 ring->stats.sw_err_cnt++;
1098 desc_cb->length = size;
1100 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1101 sizeoflast = size % HNS3_MAX_BD_SIZE;
1102 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1104 /* When frag size is bigger than hardware limit, split this frag */
1105 for (k = 0; k < frag_buf_num; k++) {
1106 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1107 desc_cb->priv = priv;
1108 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1109 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1110 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1112 /* now, fill the descriptor */
1113 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1114 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1115 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1116 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1117 frag_end && (k == frag_buf_num - 1) ?
1119 desc->tx.bdtp_fe_sc_vld_ra_ri =
1120 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1122 /* move ring pointer to next.*/
1123 ring_ptr_move_fw(ring, next_to_use);
1125 desc_cb = &ring->desc_cb[ring->next_to_use];
1126 desc = &ring->desc[ring->next_to_use];
1132 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1133 struct hns3_enet_ring *ring)
1135 struct sk_buff *skb = *out_skb;
1136 struct sk_buff *new_skb = NULL;
1137 struct skb_frag_struct *frag;
1144 size = skb_headlen(skb);
1145 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1147 frag_num = skb_shinfo(skb)->nr_frags;
1148 for (i = 0; i < frag_num; i++) {
1149 frag = &skb_shinfo(skb)->frags[i];
1150 size = skb_frag_size(frag);
1152 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1153 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1156 buf_num += bdnum_for_frag;
1159 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) {
1160 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1161 if (ring_space(ring) < buf_num)
1163 /* manual split the send packet */
1164 new_skb = skb_copy(skb, GFP_ATOMIC);
1167 dev_kfree_skb_any(skb);
1171 if (unlikely(ring_space(ring) < buf_num))
1178 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1179 struct hns3_enet_ring *ring)
1181 struct sk_buff *skb = *out_skb;
1182 struct sk_buff *new_skb = NULL;
1185 /* No. of segments (plus a header) */
1186 buf_num = skb_shinfo(skb)->nr_frags + 1;
1188 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) {
1189 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1190 if (ring_space(ring) < buf_num)
1192 /* manual split the send packet */
1193 new_skb = skb_copy(skb, GFP_ATOMIC);
1196 dev_kfree_skb_any(skb);
1200 if (unlikely(ring_space(ring) < buf_num))
1208 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1210 struct device *dev = ring_to_dev(ring);
1213 for (i = 0; i < ring->desc_num; i++) {
1214 /* check if this is where we started */
1215 if (ring->next_to_use == next_to_use_orig)
1218 /* unmap the descriptor dma address */
1219 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1220 dma_unmap_single(dev,
1221 ring->desc_cb[ring->next_to_use].dma,
1222 ring->desc_cb[ring->next_to_use].length,
1224 else if (ring->desc_cb[ring->next_to_use].length)
1226 ring->desc_cb[ring->next_to_use].dma,
1227 ring->desc_cb[ring->next_to_use].length,
1230 ring->desc_cb[ring->next_to_use].length = 0;
1233 ring_ptr_move_bw(ring, next_to_use);
1237 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1239 struct hns3_nic_priv *priv = netdev_priv(netdev);
1240 struct hns3_nic_ring_data *ring_data =
1241 &tx_ring_data(priv, skb->queue_mapping);
1242 struct hns3_enet_ring *ring = ring_data->ring;
1243 struct netdev_queue *dev_queue;
1244 struct skb_frag_struct *frag;
1245 int next_to_use_head;
1246 int next_to_use_frag;
1253 /* Prefetch the data used later */
1254 prefetch(skb->data);
1256 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1258 u64_stats_update_begin(&ring->syncp);
1259 ring->stats.tx_busy++;
1260 u64_stats_update_end(&ring->syncp);
1262 goto out_net_tx_busy;
1264 u64_stats_update_begin(&ring->syncp);
1265 ring->stats.sw_err_cnt++;
1266 u64_stats_update_end(&ring->syncp);
1267 netdev_err(netdev, "no memory to xmit!\n");
1274 /* No. of segments (plus a header) */
1275 seg_num = skb_shinfo(skb)->nr_frags + 1;
1276 /* Fill the first part */
1277 size = skb_headlen(skb);
1279 next_to_use_head = ring->next_to_use;
1281 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1286 next_to_use_frag = ring->next_to_use;
1287 /* Fill the fragments */
1288 for (i = 1; i < seg_num; i++) {
1289 frag = &skb_shinfo(skb)->frags[i - 1];
1290 size = skb_frag_size(frag);
1292 ret = priv->ops.fill_desc(ring, frag, size,
1293 seg_num - 1 == i ? 1 : 0,
1300 /* Complete translate all packets */
1301 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1302 netdev_tx_sent_queue(dev_queue, skb->len);
1304 wmb(); /* Commit all data before submit */
1306 hnae3_queue_xmit(ring->tqp, buf_num);
1308 return NETDEV_TX_OK;
1311 hns3_clear_desc(ring, next_to_use_frag);
1314 hns3_clear_desc(ring, next_to_use_head);
1317 dev_kfree_skb_any(skb);
1318 return NETDEV_TX_OK;
1321 netif_stop_subqueue(netdev, ring_data->queue_index);
1322 smp_mb(); /* Commit all data before submit */
1324 return NETDEV_TX_BUSY;
1327 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1329 struct hnae3_handle *h = hns3_get_handle(netdev);
1330 struct sockaddr *mac_addr = p;
1333 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1334 return -EADDRNOTAVAIL;
1336 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1337 netdev_info(netdev, "already using mac address %pM\n",
1342 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1344 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1348 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1353 static int hns3_nic_do_ioctl(struct net_device *netdev,
1354 struct ifreq *ifr, int cmd)
1356 struct hnae3_handle *h = hns3_get_handle(netdev);
1358 if (!netif_running(netdev))
1361 if (!h->ae_algo->ops->do_ioctl)
1364 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1367 static int hns3_nic_set_features(struct net_device *netdev,
1368 netdev_features_t features)
1370 netdev_features_t changed = netdev->features ^ features;
1371 struct hns3_nic_priv *priv = netdev_priv(netdev);
1372 struct hnae3_handle *h = priv->ae_handle;
1375 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1376 if (features & (NETIF_F_TSO | NETIF_F_TSO6))
1377 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1379 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1382 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1383 if (features & NETIF_F_GRO_HW)
1384 ret = h->ae_algo->ops->set_gro_en(h, true);
1386 ret = h->ae_algo->ops->set_gro_en(h, false);
1391 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1392 h->ae_algo->ops->enable_vlan_filter) {
1393 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1394 h->ae_algo->ops->enable_vlan_filter(h, true);
1396 h->ae_algo->ops->enable_vlan_filter(h, false);
1399 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1400 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1401 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1402 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1404 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1410 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1411 if (features & NETIF_F_NTUPLE)
1412 h->ae_algo->ops->enable_fd(h, true);
1414 h->ae_algo->ops->enable_fd(h, false);
1417 netdev->features = features;
1421 static void hns3_nic_get_stats64(struct net_device *netdev,
1422 struct rtnl_link_stats64 *stats)
1424 struct hns3_nic_priv *priv = netdev_priv(netdev);
1425 int queue_num = priv->ae_handle->kinfo.num_tqps;
1426 struct hnae3_handle *handle = priv->ae_handle;
1427 struct hns3_enet_ring *ring;
1428 u64 rx_length_errors = 0;
1429 u64 rx_crc_errors = 0;
1430 u64 rx_multicast = 0;
1442 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1445 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1447 for (idx = 0; idx < queue_num; idx++) {
1448 /* fetch the tx stats */
1449 ring = priv->ring_data[idx].ring;
1451 start = u64_stats_fetch_begin_irq(&ring->syncp);
1452 tx_bytes += ring->stats.tx_bytes;
1453 tx_pkts += ring->stats.tx_pkts;
1454 tx_drop += ring->stats.sw_err_cnt;
1455 tx_errors += ring->stats.sw_err_cnt;
1456 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1458 /* fetch the rx stats */
1459 ring = priv->ring_data[idx + queue_num].ring;
1461 start = u64_stats_fetch_begin_irq(&ring->syncp);
1462 rx_bytes += ring->stats.rx_bytes;
1463 rx_pkts += ring->stats.rx_pkts;
1464 rx_drop += ring->stats.non_vld_descs;
1465 rx_drop += ring->stats.l2_err;
1466 rx_errors += ring->stats.non_vld_descs;
1467 rx_errors += ring->stats.l2_err;
1468 rx_crc_errors += ring->stats.l2_err;
1469 rx_crc_errors += ring->stats.l3l4_csum_err;
1470 rx_multicast += ring->stats.rx_multicast;
1471 rx_length_errors += ring->stats.err_pkt_len;
1472 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1475 stats->tx_bytes = tx_bytes;
1476 stats->tx_packets = tx_pkts;
1477 stats->rx_bytes = rx_bytes;
1478 stats->rx_packets = rx_pkts;
1480 stats->rx_errors = rx_errors;
1481 stats->multicast = rx_multicast;
1482 stats->rx_length_errors = rx_length_errors;
1483 stats->rx_crc_errors = rx_crc_errors;
1484 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1486 stats->tx_errors = tx_errors;
1487 stats->rx_dropped = rx_drop;
1488 stats->tx_dropped = tx_drop;
1489 stats->collisions = netdev->stats.collisions;
1490 stats->rx_over_errors = netdev->stats.rx_over_errors;
1491 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1492 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1493 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1494 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1495 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1496 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1497 stats->tx_window_errors = netdev->stats.tx_window_errors;
1498 stats->rx_compressed = netdev->stats.rx_compressed;
1499 stats->tx_compressed = netdev->stats.tx_compressed;
1502 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1504 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1505 struct hnae3_handle *h = hns3_get_handle(netdev);
1506 struct hnae3_knic_private_info *kinfo = &h->kinfo;
1507 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1508 u8 tc = mqprio_qopt->qopt.num_tc;
1509 u16 mode = mqprio_qopt->mode;
1510 u8 hw = mqprio_qopt->qopt.hw;
1512 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1513 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1516 if (tc > HNAE3_MAX_TC)
1522 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1523 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
1526 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1529 if (type != TC_SETUP_QDISC_MQPRIO)
1532 return hns3_setup_tc(dev, type_data);
1535 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1536 __be16 proto, u16 vid)
1538 struct hnae3_handle *h = hns3_get_handle(netdev);
1539 struct hns3_nic_priv *priv = netdev_priv(netdev);
1542 if (h->ae_algo->ops->set_vlan_filter)
1543 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1546 set_bit(vid, priv->active_vlans);
1551 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1552 __be16 proto, u16 vid)
1554 struct hnae3_handle *h = hns3_get_handle(netdev);
1555 struct hns3_nic_priv *priv = netdev_priv(netdev);
1558 if (h->ae_algo->ops->set_vlan_filter)
1559 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1562 clear_bit(vid, priv->active_vlans);
1567 static int hns3_restore_vlan(struct net_device *netdev)
1569 struct hns3_nic_priv *priv = netdev_priv(netdev);
1573 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1574 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1576 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1585 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1586 u8 qos, __be16 vlan_proto)
1588 struct hnae3_handle *h = hns3_get_handle(netdev);
1591 if (h->ae_algo->ops->set_vf_vlan_filter)
1592 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1598 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1600 struct hnae3_handle *h = hns3_get_handle(netdev);
1603 if (!h->ae_algo->ops->set_mtu)
1606 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1608 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1611 netdev->mtu = new_mtu;
1616 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1618 struct hns3_nic_priv *priv = netdev_priv(ndev);
1619 struct hns3_enet_ring *tx_ring = NULL;
1620 int timeout_queue = 0;
1621 int hw_head, hw_tail;
1624 /* Find the stopped queue the same way the stack does */
1625 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1626 struct netdev_queue *q;
1627 unsigned long trans_start;
1629 q = netdev_get_tx_queue(ndev, i);
1630 trans_start = q->trans_start;
1631 if (netif_xmit_stopped(q) &&
1633 (trans_start + ndev->watchdog_timeo))) {
1639 if (i == ndev->num_tx_queues) {
1641 "no netdev TX timeout queue found, timeout count: %llu\n",
1642 priv->tx_timeout_count);
1646 tx_ring = priv->ring_data[timeout_queue].ring;
1648 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1649 HNS3_RING_TX_RING_HEAD_REG);
1650 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1651 HNS3_RING_TX_RING_TAIL_REG);
1653 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1654 priv->tx_timeout_count,
1656 tx_ring->next_to_use,
1657 tx_ring->next_to_clean,
1660 readl(tx_ring->tqp_vector->mask_addr));
1665 static void hns3_nic_net_timeout(struct net_device *ndev)
1667 struct hns3_nic_priv *priv = netdev_priv(ndev);
1668 struct hnae3_handle *h = priv->ae_handle;
1670 if (!hns3_get_tx_timeo_queue_info(ndev))
1673 priv->tx_timeout_count++;
1675 /* request the reset, and let the hclge to determine
1676 * which reset level should be done
1678 if (h->ae_algo->ops->reset_event)
1679 h->ae_algo->ops->reset_event(h->pdev, h);
1682 static const struct net_device_ops hns3_nic_netdev_ops = {
1683 .ndo_open = hns3_nic_net_open,
1684 .ndo_stop = hns3_nic_net_stop,
1685 .ndo_start_xmit = hns3_nic_net_xmit,
1686 .ndo_tx_timeout = hns3_nic_net_timeout,
1687 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
1688 .ndo_do_ioctl = hns3_nic_do_ioctl,
1689 .ndo_change_mtu = hns3_nic_change_mtu,
1690 .ndo_set_features = hns3_nic_set_features,
1691 .ndo_get_stats64 = hns3_nic_get_stats64,
1692 .ndo_setup_tc = hns3_nic_setup_tc,
1693 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
1694 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1695 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1696 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1699 static bool hns3_is_phys_func(struct pci_dev *pdev)
1701 u32 dev_id = pdev->device;
1704 case HNAE3_DEV_ID_GE:
1705 case HNAE3_DEV_ID_25GE:
1706 case HNAE3_DEV_ID_25GE_RDMA:
1707 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1708 case HNAE3_DEV_ID_50GE_RDMA:
1709 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1710 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1712 case HNAE3_DEV_ID_100G_VF:
1713 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1716 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1723 static void hns3_disable_sriov(struct pci_dev *pdev)
1725 /* If our VFs are assigned we cannot shut down SR-IOV
1726 * without causing issues, so just leave the hardware
1727 * available but disabled
1729 if (pci_vfs_assigned(pdev)) {
1730 dev_warn(&pdev->dev,
1731 "disabling driver while VFs are assigned\n");
1735 pci_disable_sriov(pdev);
1738 static void hns3_get_dev_capability(struct pci_dev *pdev,
1739 struct hnae3_ae_dev *ae_dev)
1741 if (pdev->revision >= 0x21) {
1742 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
1743 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1747 /* hns3_probe - Device initialization routine
1748 * @pdev: PCI device information struct
1749 * @ent: entry in hns3_pci_tbl
1751 * hns3_probe initializes a PF identified by a pci_dev structure.
1752 * The OS initialization, configuring of the PF private structure,
1753 * and a hardware reset occur.
1755 * Returns 0 on success, negative on failure
1757 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1759 struct hnae3_ae_dev *ae_dev;
1762 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1769 ae_dev->pdev = pdev;
1770 ae_dev->flag = ent->driver_data;
1771 ae_dev->dev_type = HNAE3_DEV_KNIC;
1772 ae_dev->reset_type = HNAE3_NONE_RESET;
1773 hns3_get_dev_capability(pdev, ae_dev);
1774 pci_set_drvdata(pdev, ae_dev);
1776 hnae3_register_ae_dev(ae_dev);
1781 /* hns3_remove - Device removal routine
1782 * @pdev: PCI device information struct
1784 static void hns3_remove(struct pci_dev *pdev)
1786 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1788 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1789 hns3_disable_sriov(pdev);
1791 hnae3_unregister_ae_dev(ae_dev);
1792 pci_set_drvdata(pdev, NULL);
1796 * hns3_pci_sriov_configure
1797 * @pdev: pointer to a pci_dev structure
1798 * @num_vfs: number of VFs to allocate
1800 * Enable or change the number of VFs. Called when the user updates the number
1803 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
1807 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1808 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1813 ret = pci_enable_sriov(pdev, num_vfs);
1815 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
1818 } else if (!pci_vfs_assigned(pdev)) {
1819 pci_disable_sriov(pdev);
1821 dev_warn(&pdev->dev,
1822 "Unable to free VFs because some are assigned to VMs.\n");
1828 static void hns3_shutdown(struct pci_dev *pdev)
1830 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1832 hnae3_unregister_ae_dev(ae_dev);
1833 devm_kfree(&pdev->dev, ae_dev);
1834 pci_set_drvdata(pdev, NULL);
1836 if (system_state == SYSTEM_POWER_OFF)
1837 pci_set_power_state(pdev, PCI_D3hot);
1840 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1841 pci_channel_state_t state)
1843 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1844 pci_ers_result_t ret;
1846 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1848 if (state == pci_channel_io_perm_failure)
1849 return PCI_ERS_RESULT_DISCONNECT;
1853 "Can't recover - error happened during device init\n");
1854 return PCI_ERS_RESULT_NONE;
1857 if (ae_dev->ops->handle_hw_ras_error)
1858 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
1860 return PCI_ERS_RESULT_NONE;
1865 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1867 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1868 struct device *dev = &pdev->dev;
1870 dev_info(dev, "requesting reset due to PCI error\n");
1872 /* request the reset */
1873 if (ae_dev->ops->reset_event) {
1874 ae_dev->ops->reset_event(pdev, NULL);
1875 return PCI_ERS_RESULT_RECOVERED;
1878 return PCI_ERS_RESULT_DISCONNECT;
1881 static void hns3_reset_prepare(struct pci_dev *pdev)
1883 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1885 dev_info(&pdev->dev, "hns3 flr prepare\n");
1886 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1887 ae_dev->ops->flr_prepare(ae_dev);
1890 static void hns3_reset_done(struct pci_dev *pdev)
1892 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1894 dev_info(&pdev->dev, "hns3 flr done\n");
1895 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1896 ae_dev->ops->flr_done(ae_dev);
1899 static const struct pci_error_handlers hns3_err_handler = {
1900 .error_detected = hns3_error_detected,
1901 .slot_reset = hns3_slot_reset,
1902 .reset_prepare = hns3_reset_prepare,
1903 .reset_done = hns3_reset_done,
1906 static struct pci_driver hns3_driver = {
1907 .name = hns3_driver_name,
1908 .id_table = hns3_pci_tbl,
1909 .probe = hns3_probe,
1910 .remove = hns3_remove,
1911 .shutdown = hns3_shutdown,
1912 .sriov_configure = hns3_pci_sriov_configure,
1913 .err_handler = &hns3_err_handler,
1916 /* set default feature to hns3 */
1917 static void hns3_set_default_feature(struct net_device *netdev)
1919 struct hnae3_handle *h = hns3_get_handle(netdev);
1920 struct pci_dev *pdev = h->pdev;
1922 netdev->priv_flags |= IFF_UNICAST_FLT;
1924 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1925 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1926 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1927 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1928 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1930 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1932 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1934 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1935 NETIF_F_HW_VLAN_CTAG_FILTER |
1936 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1937 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1938 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1939 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1940 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1942 netdev->vlan_features |=
1943 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1944 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1945 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1946 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1947 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1949 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1950 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1951 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1952 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1953 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1954 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1956 if (pdev->revision >= 0x21) {
1957 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER |
1959 netdev->features |= NETIF_F_GRO_HW;
1961 if (!(h->flags & HNAE3_SUPPORT_VF)) {
1962 netdev->hw_features |= NETIF_F_NTUPLE;
1963 netdev->features |= NETIF_F_NTUPLE;
1968 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1969 struct hns3_desc_cb *cb)
1971 unsigned int order = hnae3_page_order(ring);
1974 p = dev_alloc_pages(order);
1979 cb->page_offset = 0;
1981 cb->buf = page_address(p);
1982 cb->length = hnae3_page_size(ring);
1983 cb->type = DESC_TYPE_PAGE;
1988 static void hns3_free_buffer(struct hns3_enet_ring *ring,
1989 struct hns3_desc_cb *cb)
1991 if (cb->type == DESC_TYPE_SKB)
1992 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1993 else if (!HNAE3_IS_TX_RING(ring))
1994 put_page((struct page *)cb->priv);
1995 memset(cb, 0, sizeof(*cb));
1998 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2000 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2001 cb->length, ring_to_dma_dir(ring));
2003 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2009 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2010 struct hns3_desc_cb *cb)
2012 if (cb->type == DESC_TYPE_SKB)
2013 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2014 ring_to_dma_dir(ring));
2015 else if (cb->length)
2016 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2017 ring_to_dma_dir(ring));
2020 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2022 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2023 ring->desc[i].addr = 0;
2026 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2028 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2030 if (!ring->desc_cb[i].dma)
2033 hns3_buffer_detach(ring, i);
2034 hns3_free_buffer(ring, cb);
2037 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2041 for (i = 0; i < ring->desc_num; i++)
2042 hns3_free_buffer_detach(ring, i);
2045 /* free desc along with its attached buffer */
2046 static void hns3_free_desc(struct hns3_enet_ring *ring)
2048 int size = ring->desc_num * sizeof(ring->desc[0]);
2050 hns3_free_buffers(ring);
2053 dma_free_coherent(ring_to_dev(ring), size,
2054 ring->desc, ring->desc_dma_addr);
2059 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2061 int size = ring->desc_num * sizeof(ring->desc[0]);
2063 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2064 &ring->desc_dma_addr, GFP_KERNEL);
2071 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2072 struct hns3_desc_cb *cb)
2076 ret = hns3_alloc_buffer(ring, cb);
2080 ret = hns3_map_buffer(ring, cb);
2087 hns3_free_buffer(ring, cb);
2092 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2094 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2099 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2104 /* Allocate memory for raw pkg, and map with dma */
2105 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2109 for (i = 0; i < ring->desc_num; i++) {
2110 ret = hns3_alloc_buffer_attach(ring, i);
2112 goto out_buffer_fail;
2118 for (j = i - 1; j >= 0; j--)
2119 hns3_free_buffer_detach(ring, j);
2123 /* detach a in-used buffer and replace with a reserved one */
2124 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2125 struct hns3_desc_cb *res_cb)
2127 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2128 ring->desc_cb[i] = *res_cb;
2129 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2130 ring->desc[i].rx.bd_base_info = 0;
2133 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2135 ring->desc_cb[i].reuse_flag = 0;
2136 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2137 + ring->desc_cb[i].page_offset);
2138 ring->desc[i].rx.bd_base_info = 0;
2141 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
2144 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2146 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2147 (*bytes) += desc_cb->length;
2148 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
2149 hns3_free_buffer_detach(ring, ring->next_to_clean);
2151 ring_ptr_move_fw(ring, next_to_clean);
2154 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2156 int u = ring->next_to_use;
2157 int c = ring->next_to_clean;
2159 if (unlikely(h > ring->desc_num))
2162 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2165 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2167 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2168 struct hns3_nic_priv *priv = netdev_priv(netdev);
2169 struct netdev_queue *dev_queue;
2173 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2174 rmb(); /* Make sure head is ready before touch any data */
2176 if (is_ring_empty(ring) || head == ring->next_to_clean)
2177 return; /* no data to poll */
2179 if (unlikely(!is_valid_clean_head(ring, head))) {
2180 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2181 ring->next_to_use, ring->next_to_clean);
2183 u64_stats_update_begin(&ring->syncp);
2184 ring->stats.io_err_cnt++;
2185 u64_stats_update_end(&ring->syncp);
2191 while (head != ring->next_to_clean) {
2192 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
2193 /* Issue prefetch for next Tx descriptor */
2194 prefetch(&ring->desc_cb[ring->next_to_clean]);
2197 ring->tqp_vector->tx_group.total_bytes += bytes;
2198 ring->tqp_vector->tx_group.total_packets += pkts;
2200 u64_stats_update_begin(&ring->syncp);
2201 ring->stats.tx_bytes += bytes;
2202 ring->stats.tx_pkts += pkts;
2203 u64_stats_update_end(&ring->syncp);
2205 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2206 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2208 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2209 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2210 /* Make sure that anybody stopping the queue after this
2211 * sees the new next_to_clean.
2214 if (netif_tx_queue_stopped(dev_queue) &&
2215 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2216 netif_tx_wake_queue(dev_queue);
2217 ring->stats.restart_queue++;
2222 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2224 int ntc = ring->next_to_clean;
2225 int ntu = ring->next_to_use;
2227 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2231 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2233 struct hns3_desc_cb *desc_cb;
2234 struct hns3_desc_cb res_cbs;
2237 for (i = 0; i < cleand_count; i++) {
2238 desc_cb = &ring->desc_cb[ring->next_to_use];
2239 if (desc_cb->reuse_flag) {
2240 u64_stats_update_begin(&ring->syncp);
2241 ring->stats.reuse_pg_cnt++;
2242 u64_stats_update_end(&ring->syncp);
2244 hns3_reuse_buffer(ring, ring->next_to_use);
2246 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2248 u64_stats_update_begin(&ring->syncp);
2249 ring->stats.sw_err_cnt++;
2250 u64_stats_update_end(&ring->syncp);
2252 netdev_err(ring->tqp->handle->kinfo.netdev,
2253 "hnae reserve buffer map failed.\n");
2256 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2259 ring_ptr_move_fw(ring, next_to_use);
2262 wmb(); /* Make all data has been write before submit */
2263 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2266 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2267 struct hns3_enet_ring *ring, int pull_len,
2268 struct hns3_desc_cb *desc_cb)
2270 struct hns3_desc *desc;
2276 twobufs = ((PAGE_SIZE < 8192) &&
2277 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
2279 desc = &ring->desc[ring->next_to_clean];
2280 size = le16_to_cpu(desc->rx.size);
2282 truesize = hnae3_buf_size(ring);
2285 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
2287 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2288 size - pull_len, truesize);
2290 /* Avoid re-using remote pages,flag default unreuse */
2291 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2295 /* If we are only owner of page we can reuse it */
2296 if (likely(page_count(desc_cb->priv) == 1)) {
2297 /* Flip page offset to other buffer */
2298 desc_cb->page_offset ^= truesize;
2300 desc_cb->reuse_flag = 1;
2301 /* bump ref count on page before it is given*/
2302 get_page(desc_cb->priv);
2307 /* Move offset up to the next cache line */
2308 desc_cb->page_offset += truesize;
2310 if (desc_cb->page_offset <= last_offset) {
2311 desc_cb->reuse_flag = 1;
2312 /* Bump ref count on page before it is given*/
2313 get_page(desc_cb->priv);
2317 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2318 struct hns3_desc *desc)
2320 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2321 int l3_type, l4_type;
2326 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2327 l234info = le32_to_cpu(desc->rx.l234_info);
2329 skb->ip_summed = CHECKSUM_NONE;
2331 skb_checksum_none_assert(skb);
2333 if (!(netdev->features & NETIF_F_RXCSUM))
2336 /* We MUST enable hardware checksum before enabling hardware GRO */
2337 if (skb_shinfo(skb)->gso_size) {
2338 skb->ip_summed = CHECKSUM_UNNECESSARY;
2342 /* check if hardware has done checksum */
2343 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
2346 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2347 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2348 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2349 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
2350 u64_stats_update_begin(&ring->syncp);
2351 ring->stats.l3l4_csum_err++;
2352 u64_stats_update_end(&ring->syncp);
2357 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2359 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2362 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2365 case HNS3_OL4_TYPE_MAC_IN_UDP:
2366 case HNS3_OL4_TYPE_NVGRE:
2367 skb->csum_level = 1;
2369 case HNS3_OL4_TYPE_NO_TUN:
2370 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2371 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2372 l3_type == HNS3_L3_TYPE_IPV6) &&
2373 (l4_type == HNS3_L4_TYPE_UDP ||
2374 l4_type == HNS3_L4_TYPE_TCP ||
2375 l4_type == HNS3_L4_TYPE_SCTP))
2376 skb->ip_summed = CHECKSUM_UNNECESSARY;
2383 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2385 if (skb_has_frag_list(skb))
2386 napi_gro_flush(&ring->tqp_vector->napi, false);
2388 napi_gro_receive(&ring->tqp_vector->napi, skb);
2391 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2392 struct hns3_desc *desc, u32 l234info,
2395 struct pci_dev *pdev = ring->tqp->handle->pdev;
2397 if (pdev->revision == 0x20) {
2398 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2399 if (!(*vlan_tag & VLAN_VID_MASK))
2400 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2402 return (*vlan_tag != 0);
2405 #define HNS3_STRP_OUTER_VLAN 0x1
2406 #define HNS3_STRP_INNER_VLAN 0x2
2408 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2409 HNS3_RXD_STRP_TAGP_S)) {
2410 case HNS3_STRP_OUTER_VLAN:
2411 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2413 case HNS3_STRP_INNER_VLAN:
2414 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2421 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2424 #define HNS3_NEED_ADD_FRAG 1
2425 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2426 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2427 struct sk_buff *skb;
2429 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2431 if (unlikely(!skb)) {
2432 netdev_err(netdev, "alloc rx skb fail\n");
2434 u64_stats_update_begin(&ring->syncp);
2435 ring->stats.sw_err_cnt++;
2436 u64_stats_update_end(&ring->syncp);
2441 prefetchw(skb->data);
2443 ring->pending_buf = 1;
2445 ring->tail_skb = NULL;
2446 if (length <= HNS3_RX_HEAD_SIZE) {
2447 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2449 /* We can reuse buffer as-is, just make sure it is local */
2450 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2451 desc_cb->reuse_flag = 1;
2452 else /* This page cannot be reused so discard it */
2453 put_page(desc_cb->priv);
2455 ring_ptr_move_fw(ring, next_to_clean);
2458 u64_stats_update_begin(&ring->syncp);
2459 ring->stats.seg_pkt_cnt++;
2460 u64_stats_update_end(&ring->syncp);
2462 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2463 __skb_put(skb, ring->pull_len);
2464 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2466 ring_ptr_move_fw(ring, next_to_clean);
2468 return HNS3_NEED_ADD_FRAG;
2471 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2472 struct sk_buff **out_skb, bool pending)
2474 struct sk_buff *skb = *out_skb;
2475 struct sk_buff *head_skb = *out_skb;
2476 struct sk_buff *new_skb;
2477 struct hns3_desc_cb *desc_cb;
2478 struct hns3_desc *pre_desc;
2482 /* if there is pending bd, the SW param next_to_clean has moved
2483 * to next and the next is NULL
2486 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2488 pre_desc = &ring->desc[pre_bd];
2489 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2491 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2494 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2495 desc = &ring->desc[ring->next_to_clean];
2496 desc_cb = &ring->desc_cb[ring->next_to_clean];
2497 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2498 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2501 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2502 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2504 if (unlikely(!new_skb)) {
2505 netdev_err(ring->tqp->handle->kinfo.netdev,
2506 "alloc rx skb frag fail\n");
2511 if (ring->tail_skb) {
2512 ring->tail_skb->next = new_skb;
2513 ring->tail_skb = new_skb;
2515 skb_shinfo(skb)->frag_list = new_skb;
2516 ring->tail_skb = new_skb;
2520 if (ring->tail_skb) {
2521 head_skb->truesize += hnae3_buf_size(ring);
2522 head_skb->data_len += le16_to_cpu(desc->rx.size);
2523 head_skb->len += le16_to_cpu(desc->rx.size);
2524 skb = ring->tail_skb;
2527 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2528 ring_ptr_move_fw(ring, next_to_clean);
2529 ring->pending_buf++;
2535 static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info,
2541 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2542 HNS3_RXD_GRO_COUNT_S);
2543 /* if there is no HW GRO, do not set gro params */
2547 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
2548 * to skb_shinfo(skb)->gso_segs
2550 NAPI_GRO_CB(skb)->count = gro_count;
2552 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2554 if (l3_type == HNS3_L3_TYPE_IPV4)
2555 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2556 else if (l3_type == HNS3_L3_TYPE_IPV6)
2557 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2561 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2562 HNS3_RXD_GRO_SIZE_M,
2563 HNS3_RXD_GRO_SIZE_S);
2564 if (skb_shinfo(skb)->gso_size)
2565 tcp_gro_complete(skb);
2568 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2569 struct sk_buff *skb)
2571 struct hnae3_handle *handle = ring->tqp->handle;
2572 enum pkt_hash_types rss_type;
2573 struct hns3_desc *desc;
2576 /* When driver handle the rss type, ring->next_to_clean indicates the
2577 * first descriptor of next packet, need -1 here.
2579 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num;
2580 desc = &ring->desc[last_bd];
2582 if (le32_to_cpu(desc->rx.rss_hash))
2583 rss_type = handle->kinfo.rss_type;
2585 rss_type = PKT_HASH_TYPE_NONE;
2587 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type);
2590 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2591 struct sk_buff **out_skb)
2593 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2594 enum hns3_pkt_l2t_type l2_frame_type;
2595 struct sk_buff *skb = ring->skb;
2596 struct hns3_desc_cb *desc_cb;
2597 struct hns3_desc *desc;
2603 desc = &ring->desc[ring->next_to_clean];
2604 desc_cb = &ring->desc_cb[ring->next_to_clean];
2608 length = le16_to_cpu(desc->rx.size);
2609 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2611 /* Check valid BD */
2612 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
2616 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2618 /* Prefetch first cache line of first page
2619 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2620 * line size is 64B so need to prefetch twice to make it 128B. But in
2621 * actual we can have greater size of caches with 128B Level 1 cache
2622 * lines. In such a case, single fetch would suffice to cache in the
2623 * relevant part of the header.
2626 #if L1_CACHE_BYTES < 128
2627 prefetch(ring->va + L1_CACHE_BYTES);
2631 ret = hns3_alloc_skb(ring, length, ring->va);
2632 *out_skb = skb = ring->skb;
2634 if (ret < 0) /* alloc buffer fail */
2636 if (ret > 0) { /* need add frag */
2637 ret = hns3_add_frag(ring, desc, &skb, false);
2641 /* As the head data may be changed when GRO enable, copy
2642 * the head data in after other data rx completed
2644 memcpy(skb->data, ring->va,
2645 ALIGN(ring->pull_len, sizeof(long)));
2648 ret = hns3_add_frag(ring, desc, &skb, true);
2652 /* As the head data may be changed when GRO enable, copy
2653 * the head data in after other data rx completed
2655 memcpy(skb->data, ring->va,
2656 ALIGN(ring->pull_len, sizeof(long)));
2659 l234info = le32_to_cpu(desc->rx.l234_info);
2660 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2662 /* Based on hw strategy, the tag offloaded will be stored at
2663 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2664 * in one layer tag case.
2666 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2669 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2670 __vlan_hwaccel_put_tag(skb,
2675 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
2676 u64_stats_update_begin(&ring->syncp);
2677 ring->stats.non_vld_descs++;
2678 u64_stats_update_end(&ring->syncp);
2680 dev_kfree_skb_any(skb);
2684 if (unlikely((!desc->rx.pkt_len) ||
2685 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
2686 u64_stats_update_begin(&ring->syncp);
2687 ring->stats.err_pkt_len++;
2688 u64_stats_update_end(&ring->syncp);
2690 dev_kfree_skb_any(skb);
2694 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
2695 u64_stats_update_begin(&ring->syncp);
2696 ring->stats.l2_err++;
2697 u64_stats_update_end(&ring->syncp);
2699 dev_kfree_skb_any(skb);
2703 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
2705 u64_stats_update_begin(&ring->syncp);
2706 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
2707 ring->stats.rx_multicast++;
2709 ring->stats.rx_pkts++;
2710 ring->stats.rx_bytes += skb->len;
2711 u64_stats_update_end(&ring->syncp);
2713 ring->tqp_vector->rx_group.total_bytes += skb->len;
2715 /* This is needed in order to enable forwarding support */
2716 hns3_set_gro_param(skb, l234info, bd_base_info);
2718 hns3_rx_checksum(ring, skb, desc);
2720 hns3_set_rx_skb_rss_type(ring, skb);
2725 int hns3_clean_rx_ring(
2726 struct hns3_enet_ring *ring, int budget,
2727 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
2729 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2730 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2731 int recv_pkts, recv_bds, clean_count, err;
2732 int unused_count = hns3_desc_unused(ring) - ring->pending_buf;
2733 struct sk_buff *skb = ring->skb;
2736 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2737 rmb(); /* Make sure num taken effect before the other data is touched */
2739 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2740 num -= unused_count;
2742 while (recv_pkts < budget && recv_bds < num) {
2743 /* Reuse or realloc buffers */
2744 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2745 hns3_nic_alloc_rx_buffers(ring,
2746 clean_count + unused_count);
2748 unused_count = hns3_desc_unused(ring) -
2753 err = hns3_handle_rx_bd(ring, &skb);
2754 if (unlikely(!skb)) /* This fault cannot be repaired */
2757 if (err == -ENXIO) { /* Do not get FE for the packet */
2759 } else if (unlikely(err)) { /* Do jump the err */
2760 recv_bds += ring->pending_buf;
2761 clean_count += ring->pending_buf;
2763 ring->pending_buf = 0;
2767 /* Do update ip stack process */
2768 skb->protocol = eth_type_trans(skb, netdev);
2770 recv_bds += ring->pending_buf;
2771 clean_count += ring->pending_buf;
2773 ring->pending_buf = 0;
2779 /* Make all data has been write before submit */
2780 if (clean_count + unused_count > 0)
2781 hns3_nic_alloc_rx_buffers(ring,
2782 clean_count + unused_count);
2787 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2789 struct hns3_enet_tqp_vector *tqp_vector =
2790 ring_group->ring->tqp_vector;
2791 enum hns3_flow_level_range new_flow_level;
2792 int packets_per_msecs;
2793 int bytes_per_msecs;
2797 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
2800 if (ring_group->total_packets == 0) {
2801 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2802 ring_group->coal.flow_level = HNS3_FLOW_LOW;
2806 /* Simple throttlerate management
2807 * 0-10MB/s lower (50000 ints/s)
2808 * 10-20MB/s middle (20000 ints/s)
2809 * 20-1249MB/s high (18000 ints/s)
2810 * > 40000pps ultra (8000 ints/s)
2812 new_flow_level = ring_group->coal.flow_level;
2813 new_int_gl = ring_group->coal.int_gl;
2815 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2817 if (!time_passed_ms)
2820 do_div(ring_group->total_packets, time_passed_ms);
2821 packets_per_msecs = ring_group->total_packets;
2823 do_div(ring_group->total_bytes, time_passed_ms);
2824 bytes_per_msecs = ring_group->total_bytes;
2826 #define HNS3_RX_LOW_BYTE_RATE 10000
2827 #define HNS3_RX_MID_BYTE_RATE 20000
2829 switch (new_flow_level) {
2831 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
2832 new_flow_level = HNS3_FLOW_MID;
2835 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
2836 new_flow_level = HNS3_FLOW_HIGH;
2837 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
2838 new_flow_level = HNS3_FLOW_LOW;
2840 case HNS3_FLOW_HIGH:
2841 case HNS3_FLOW_ULTRA:
2843 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
2844 new_flow_level = HNS3_FLOW_MID;
2848 #define HNS3_RX_ULTRA_PACKET_RATE 40
2850 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2851 &tqp_vector->rx_group == ring_group)
2852 new_flow_level = HNS3_FLOW_ULTRA;
2854 switch (new_flow_level) {
2856 new_int_gl = HNS3_INT_GL_50K;
2859 new_int_gl = HNS3_INT_GL_20K;
2861 case HNS3_FLOW_HIGH:
2862 new_int_gl = HNS3_INT_GL_18K;
2864 case HNS3_FLOW_ULTRA:
2865 new_int_gl = HNS3_INT_GL_8K;
2871 ring_group->total_bytes = 0;
2872 ring_group->total_packets = 0;
2873 ring_group->coal.flow_level = new_flow_level;
2874 if (new_int_gl != ring_group->coal.int_gl) {
2875 ring_group->coal.int_gl = new_int_gl;
2881 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2883 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2884 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2885 bool rx_update, tx_update;
2887 /* update param every 1000ms */
2888 if (time_before(jiffies,
2889 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
2892 if (rx_group->coal.gl_adapt_enable) {
2893 rx_update = hns3_get_new_int_gl(rx_group);
2895 hns3_set_vector_coalesce_rx_gl(tqp_vector,
2896 rx_group->coal.int_gl);
2899 if (tx_group->coal.gl_adapt_enable) {
2900 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2902 hns3_set_vector_coalesce_tx_gl(tqp_vector,
2903 tx_group->coal.int_gl);
2906 tqp_vector->last_jiffies = jiffies;
2909 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2911 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
2912 struct hns3_enet_ring *ring;
2913 int rx_pkt_total = 0;
2915 struct hns3_enet_tqp_vector *tqp_vector =
2916 container_of(napi, struct hns3_enet_tqp_vector, napi);
2917 bool clean_complete = true;
2920 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2921 napi_complete(napi);
2925 /* Since the actual Tx work is minimal, we can give the Tx a larger
2926 * budget and be more aggressive about cleaning up the Tx descriptors.
2928 hns3_for_each_ring(ring, tqp_vector->tx_group)
2929 hns3_clean_tx_ring(ring);
2931 /* make sure rx ring budget not smaller than 1 */
2932 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2934 hns3_for_each_ring(ring, tqp_vector->rx_group) {
2935 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2938 if (rx_cleaned >= rx_budget)
2939 clean_complete = false;
2941 rx_pkt_total += rx_cleaned;
2944 tqp_vector->rx_group.total_packets += rx_pkt_total;
2946 if (!clean_complete)
2949 if (napi_complete(napi) &&
2950 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2951 hns3_update_new_int_gl(tqp_vector);
2952 hns3_mask_vector_irq(tqp_vector, 1);
2955 return rx_pkt_total;
2958 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2959 struct hnae3_ring_chain_node *head)
2961 struct pci_dev *pdev = tqp_vector->handle->pdev;
2962 struct hnae3_ring_chain_node *cur_chain = head;
2963 struct hnae3_ring_chain_node *chain;
2964 struct hns3_enet_ring *tx_ring;
2965 struct hns3_enet_ring *rx_ring;
2967 tx_ring = tqp_vector->tx_group.ring;
2969 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
2970 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2971 HNAE3_RING_TYPE_TX);
2972 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2973 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
2975 cur_chain->next = NULL;
2977 while (tx_ring->next) {
2978 tx_ring = tx_ring->next;
2980 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2983 goto err_free_chain;
2985 cur_chain->next = chain;
2986 chain->tqp_index = tx_ring->tqp->tqp_index;
2987 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2988 HNAE3_RING_TYPE_TX);
2989 hnae3_set_field(chain->int_gl_idx,
2990 HNAE3_RING_GL_IDX_M,
2991 HNAE3_RING_GL_IDX_S,
2998 rx_ring = tqp_vector->rx_group.ring;
2999 if (!tx_ring && rx_ring) {
3000 cur_chain->next = NULL;
3001 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3002 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3003 HNAE3_RING_TYPE_RX);
3004 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3005 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3007 rx_ring = rx_ring->next;
3011 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3013 goto err_free_chain;
3015 cur_chain->next = chain;
3016 chain->tqp_index = rx_ring->tqp->tqp_index;
3017 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3018 HNAE3_RING_TYPE_RX);
3019 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3020 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3024 rx_ring = rx_ring->next;
3030 cur_chain = head->next;
3032 chain = cur_chain->next;
3033 devm_kfree(&pdev->dev, cur_chain);
3041 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3042 struct hnae3_ring_chain_node *head)
3044 struct pci_dev *pdev = tqp_vector->handle->pdev;
3045 struct hnae3_ring_chain_node *chain_tmp, *chain;
3050 chain_tmp = chain->next;
3051 devm_kfree(&pdev->dev, chain);
3056 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3057 struct hns3_enet_ring *ring)
3059 ring->next = group->ring;
3065 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3067 struct pci_dev *pdev = priv->ae_handle->pdev;
3068 struct hns3_enet_tqp_vector *tqp_vector;
3069 int num_vectors = priv->vector_num;
3073 numa_node = dev_to_node(&pdev->dev);
3075 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3076 tqp_vector = &priv->tqp_vector[vector_i];
3077 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3078 &tqp_vector->affinity_mask);
3082 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3084 struct hnae3_ring_chain_node vector_ring_chain;
3085 struct hnae3_handle *h = priv->ae_handle;
3086 struct hns3_enet_tqp_vector *tqp_vector;
3090 hns3_nic_set_cpumask(priv);
3092 for (i = 0; i < priv->vector_num; i++) {
3093 tqp_vector = &priv->tqp_vector[i];
3094 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3095 tqp_vector->num_tqps = 0;
3098 for (i = 0; i < h->kinfo.num_tqps; i++) {
3099 u16 vector_i = i % priv->vector_num;
3100 u16 tqp_num = h->kinfo.num_tqps;
3102 tqp_vector = &priv->tqp_vector[vector_i];
3104 hns3_add_ring_to_group(&tqp_vector->tx_group,
3105 priv->ring_data[i].ring);
3107 hns3_add_ring_to_group(&tqp_vector->rx_group,
3108 priv->ring_data[i + tqp_num].ring);
3110 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3111 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
3112 tqp_vector->num_tqps++;
3115 for (i = 0; i < priv->vector_num; i++) {
3116 tqp_vector = &priv->tqp_vector[i];
3118 tqp_vector->rx_group.total_bytes = 0;
3119 tqp_vector->rx_group.total_packets = 0;
3120 tqp_vector->tx_group.total_bytes = 0;
3121 tqp_vector->tx_group.total_packets = 0;
3122 tqp_vector->handle = h;
3124 ret = hns3_get_vector_ring_chain(tqp_vector,
3125 &vector_ring_chain);
3129 ret = h->ae_algo->ops->map_ring_to_vector(h,
3130 tqp_vector->vector_irq, &vector_ring_chain);
3132 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3137 netif_napi_add(priv->netdev, &tqp_vector->napi,
3138 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3145 netif_napi_del(&priv->tqp_vector[i].napi);
3150 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3152 #define HNS3_VECTOR_PF_MAX_NUM 64
3154 struct hnae3_handle *h = priv->ae_handle;
3155 struct hns3_enet_tqp_vector *tqp_vector;
3156 struct hnae3_vector_info *vector;
3157 struct pci_dev *pdev = h->pdev;
3158 u16 tqp_num = h->kinfo.num_tqps;
3163 /* RSS size, cpu online and vector_num should be the same */
3164 /* Should consider 2p/4p later */
3165 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3166 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3168 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3173 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3175 priv->vector_num = vector_num;
3176 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3177 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3179 if (!priv->tqp_vector) {
3184 for (i = 0; i < priv->vector_num; i++) {
3185 tqp_vector = &priv->tqp_vector[i];
3186 tqp_vector->idx = i;
3187 tqp_vector->mask_addr = vector[i].io_addr;
3188 tqp_vector->vector_irq = vector[i].vector;
3189 hns3_vector_gl_rl_init(tqp_vector, priv);
3193 devm_kfree(&pdev->dev, vector);
3197 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3203 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3205 struct hnae3_ring_chain_node vector_ring_chain;
3206 struct hnae3_handle *h = priv->ae_handle;
3207 struct hns3_enet_tqp_vector *tqp_vector;
3210 for (i = 0; i < priv->vector_num; i++) {
3211 tqp_vector = &priv->tqp_vector[i];
3213 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3216 ret = hns3_get_vector_ring_chain(tqp_vector,
3217 &vector_ring_chain);
3221 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
3222 tqp_vector->vector_irq, &vector_ring_chain);
3226 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3228 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3229 irq_set_affinity_notifier(tqp_vector->vector_irq,
3231 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3232 free_irq(tqp_vector->vector_irq, tqp_vector);
3233 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
3236 hns3_clear_ring_group(&tqp_vector->rx_group);
3237 hns3_clear_ring_group(&tqp_vector->tx_group);
3238 netif_napi_del(&priv->tqp_vector[i].napi);
3244 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3246 struct hnae3_handle *h = priv->ae_handle;
3247 struct pci_dev *pdev = h->pdev;
3250 for (i = 0; i < priv->vector_num; i++) {
3251 struct hns3_enet_tqp_vector *tqp_vector;
3253 tqp_vector = &priv->tqp_vector[i];
3254 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3259 devm_kfree(&pdev->dev, priv->tqp_vector);
3263 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3266 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3267 int queue_num = priv->ae_handle->kinfo.num_tqps;
3268 int desc_num = priv->ae_handle->kinfo.num_desc;
3269 struct pci_dev *pdev = priv->ae_handle->pdev;
3270 struct hns3_enet_ring *ring;
3272 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3276 if (ring_type == HNAE3_RING_TYPE_TX) {
3277 ring_data[q->tqp_index].ring = ring;
3278 ring_data[q->tqp_index].queue_index = q->tqp_index;
3279 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3281 ring_data[q->tqp_index + queue_num].ring = ring;
3282 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
3283 ring->io_base = q->io_base;
3286 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3290 ring->desc_cb = NULL;
3291 ring->dev = priv->dev;
3292 ring->desc_dma_addr = 0;
3293 ring->buf_size = q->buf_size;
3294 ring->desc_num = desc_num;
3295 ring->next_to_use = 0;
3296 ring->next_to_clean = 0;
3301 static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3302 struct hns3_nic_priv *priv)
3306 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3310 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3312 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
3319 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3321 struct hnae3_handle *h = priv->ae_handle;
3322 struct pci_dev *pdev = h->pdev;
3325 priv->ring_data = devm_kzalloc(&pdev->dev,
3326 array3_size(h->kinfo.num_tqps,
3327 sizeof(*priv->ring_data),
3330 if (!priv->ring_data)
3333 for (i = 0; i < h->kinfo.num_tqps; i++) {
3334 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3342 devm_kfree(priv->dev, priv->ring_data[i].ring);
3343 devm_kfree(priv->dev,
3344 priv->ring_data[i + h->kinfo.num_tqps].ring);
3347 devm_kfree(&pdev->dev, priv->ring_data);
3351 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3353 struct hnae3_handle *h = priv->ae_handle;
3356 for (i = 0; i < h->kinfo.num_tqps; i++) {
3357 devm_kfree(priv->dev, priv->ring_data[i].ring);
3358 devm_kfree(priv->dev,
3359 priv->ring_data[i + h->kinfo.num_tqps].ring);
3361 devm_kfree(priv->dev, priv->ring_data);
3364 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3368 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3371 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
3373 if (!ring->desc_cb) {
3378 ret = hns3_alloc_desc(ring);
3380 goto out_with_desc_cb;
3382 if (!HNAE3_IS_TX_RING(ring)) {
3383 ret = hns3_alloc_ring_buffers(ring);
3391 hns3_free_desc(ring);
3393 kfree(ring->desc_cb);
3394 ring->desc_cb = NULL;
3399 static void hns3_fini_ring(struct hns3_enet_ring *ring)
3401 hns3_free_desc(ring);
3402 kfree(ring->desc_cb);
3403 ring->desc_cb = NULL;
3404 ring->next_to_clean = 0;
3405 ring->next_to_use = 0;
3406 ring->pending_buf = 0;
3408 dev_kfree_skb_any(ring->skb);
3413 static int hns3_buf_size2type(u32 buf_size)
3419 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3422 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3425 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3428 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3431 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3434 return bd_size_type;
3437 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3439 dma_addr_t dma = ring->desc_dma_addr;
3440 struct hnae3_queue *q = ring->tqp;
3442 if (!HNAE3_IS_TX_RING(ring)) {
3443 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3445 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3446 (u32)((dma >> 31) >> 1));
3448 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3449 hns3_buf_size2type(ring->buf_size));
3450 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3451 ring->desc_num / 8 - 1);
3454 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3456 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3457 (u32)((dma >> 31) >> 1));
3459 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3460 ring->desc_num / 8 - 1);
3464 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3466 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3469 for (i = 0; i < HNAE3_MAX_TC; i++) {
3470 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3473 if (!tc_info->enable)
3476 for (j = 0; j < tc_info->tqp_count; j++) {
3477 struct hnae3_queue *q;
3479 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3480 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3486 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3488 struct hnae3_handle *h = priv->ae_handle;
3489 int ring_num = h->kinfo.num_tqps * 2;
3493 for (i = 0; i < ring_num; i++) {
3494 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3497 "Alloc ring memory fail! ret=%d\n", ret);
3498 goto out_when_alloc_ring_memory;
3501 u64_stats_init(&priv->ring_data[i].ring->syncp);
3506 out_when_alloc_ring_memory:
3507 for (j = i - 1; j >= 0; j--)
3508 hns3_fini_ring(priv->ring_data[j].ring);
3513 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3515 struct hnae3_handle *h = priv->ae_handle;
3518 for (i = 0; i < h->kinfo.num_tqps; i++) {
3519 hns3_fini_ring(priv->ring_data[i].ring);
3520 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3525 /* Set mac addr if it is configured. or leave it to the AE driver */
3526 static int hns3_init_mac_addr(struct net_device *netdev, bool init)
3528 struct hns3_nic_priv *priv = netdev_priv(netdev);
3529 struct hnae3_handle *h = priv->ae_handle;
3530 u8 mac_addr_temp[ETH_ALEN];
3533 if (h->ae_algo->ops->get_mac_addr && init) {
3534 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3535 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3538 /* Check if the MAC address is valid, if not get a random one */
3539 if (!is_valid_ether_addr(netdev->dev_addr)) {
3540 eth_hw_addr_random(netdev);
3541 dev_warn(priv->dev, "using random MAC address %pM\n",
3545 if (h->ae_algo->ops->set_mac_addr)
3546 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3551 static int hns3_restore_fd_rules(struct net_device *netdev)
3553 struct hnae3_handle *h = hns3_get_handle(netdev);
3556 if (h->ae_algo->ops->restore_fd_rules)
3557 ret = h->ae_algo->ops->restore_fd_rules(h);
3562 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3564 struct hnae3_handle *h = hns3_get_handle(netdev);
3566 if (h->ae_algo->ops->del_all_fd_entries)
3567 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3570 static void hns3_nic_set_priv_ops(struct net_device *netdev)
3572 struct hns3_nic_priv *priv = netdev_priv(netdev);
3574 priv->ops.fill_desc = hns3_fill_desc;
3575 if ((netdev->features & NETIF_F_TSO) ||
3576 (netdev->features & NETIF_F_TSO6))
3577 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
3579 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
3582 static int hns3_client_start(struct hnae3_handle *handle)
3584 if (!handle->ae_algo->ops->client_start)
3587 return handle->ae_algo->ops->client_start(handle);
3590 static void hns3_client_stop(struct hnae3_handle *handle)
3592 if (!handle->ae_algo->ops->client_stop)
3595 handle->ae_algo->ops->client_stop(handle);
3598 static int hns3_client_init(struct hnae3_handle *handle)
3600 struct pci_dev *pdev = handle->pdev;
3601 u16 alloc_tqps, max_rss_size;
3602 struct hns3_nic_priv *priv;
3603 struct net_device *netdev;
3606 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3608 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3612 priv = netdev_priv(netdev);
3613 priv->dev = &pdev->dev;
3614 priv->netdev = netdev;
3615 priv->ae_handle = handle;
3616 priv->tx_timeout_count = 0;
3618 handle->kinfo.netdev = netdev;
3619 handle->priv = (void *)priv;
3621 hns3_init_mac_addr(netdev, true);
3623 hns3_set_default_feature(netdev);
3625 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3626 netdev->priv_flags |= IFF_UNICAST_FLT;
3627 netdev->netdev_ops = &hns3_nic_netdev_ops;
3628 SET_NETDEV_DEV(netdev, &pdev->dev);
3629 hns3_ethtool_set_ops(netdev);
3630 hns3_nic_set_priv_ops(netdev);
3632 /* Carrier off reporting is important to ethtool even BEFORE open */
3633 netif_carrier_off(netdev);
3635 ret = hns3_get_ring_config(priv);
3638 goto out_get_ring_cfg;
3641 ret = hns3_nic_alloc_vector_data(priv);
3644 goto out_alloc_vector_data;
3647 ret = hns3_nic_init_vector_data(priv);
3650 goto out_init_vector_data;
3653 ret = hns3_init_all_ring(priv);
3656 goto out_init_ring_data;
3659 ret = register_netdev(netdev);
3661 dev_err(priv->dev, "probe register netdev fail!\n");
3662 goto out_reg_netdev_fail;
3665 ret = hns3_client_start(handle);
3667 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
3668 goto out_reg_netdev_fail;
3671 hns3_dcbnl_setup(handle);
3673 hns3_dbg_init(handle);
3675 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
3676 netdev->max_mtu = HNS3_MAX_MTU;
3678 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3682 out_reg_netdev_fail:
3684 (void)hns3_nic_uninit_vector_data(priv);
3685 out_init_vector_data:
3686 hns3_nic_dealloc_vector_data(priv);
3687 out_alloc_vector_data:
3688 priv->ring_data = NULL;
3690 priv->ae_handle = NULL;
3691 free_netdev(netdev);
3695 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3697 struct net_device *netdev = handle->kinfo.netdev;
3698 struct hns3_nic_priv *priv = netdev_priv(netdev);
3701 hns3_client_stop(handle);
3703 hns3_remove_hw_addr(netdev);
3705 if (netdev->reg_state != NETREG_UNINITIALIZED)
3706 unregister_netdev(netdev);
3708 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3709 netdev_warn(netdev, "already uninitialized\n");
3710 goto out_netdev_free;
3713 hns3_del_all_fd_rules(netdev, true);
3715 hns3_force_clear_all_rx_ring(handle);
3717 ret = hns3_nic_uninit_vector_data(priv);
3719 netdev_err(netdev, "uninit vector error\n");
3721 ret = hns3_nic_dealloc_vector_data(priv);
3723 netdev_err(netdev, "dealloc vector error\n");
3725 ret = hns3_uninit_all_ring(priv);
3727 netdev_err(netdev, "uninit ring error\n");
3729 hns3_put_ring_config(priv);
3731 hns3_dbg_uninit(handle);
3733 priv->ring_data = NULL;
3736 free_netdev(netdev);
3739 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3741 struct net_device *netdev = handle->kinfo.netdev;
3747 netif_carrier_on(netdev);
3748 netif_tx_wake_all_queues(netdev);
3749 netdev_info(netdev, "link up\n");
3751 netif_carrier_off(netdev);
3752 netif_tx_stop_all_queues(netdev);
3753 netdev_info(netdev, "link down\n");
3757 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3759 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3760 struct net_device *ndev = kinfo->netdev;
3762 if (tc > HNAE3_MAX_TC)
3768 return hns3_nic_set_real_num_queue(ndev);
3771 static int hns3_recover_hw_addr(struct net_device *ndev)
3773 struct netdev_hw_addr_list *list;
3774 struct netdev_hw_addr *ha, *tmp;
3777 /* go through and sync uc_addr entries to the device */
3779 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3780 ret = hns3_nic_uc_sync(ndev, ha->addr);
3785 /* go through and sync mc_addr entries to the device */
3787 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3788 ret = hns3_nic_mc_sync(ndev, ha->addr);
3796 static void hns3_remove_hw_addr(struct net_device *netdev)
3798 struct netdev_hw_addr_list *list;
3799 struct netdev_hw_addr *ha, *tmp;
3801 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3803 /* go through and unsync uc_addr entries to the device */
3805 list_for_each_entry_safe(ha, tmp, &list->list, list)
3806 hns3_nic_uc_unsync(netdev, ha->addr);
3808 /* go through and unsync mc_addr entries to the device */
3810 list_for_each_entry_safe(ha, tmp, &list->list, list)
3811 if (ha->refcount > 1)
3812 hns3_nic_mc_unsync(netdev, ha->addr);
3815 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
3817 while (ring->next_to_clean != ring->next_to_use) {
3818 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
3819 hns3_free_buffer_detach(ring, ring->next_to_clean);
3820 ring_ptr_move_fw(ring, next_to_clean);
3824 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3826 struct hns3_desc_cb res_cbs;
3829 while (ring->next_to_use != ring->next_to_clean) {
3830 /* When a buffer is not reused, it's memory has been
3831 * freed in hns3_handle_rx_bd or will be freed by
3832 * stack, so we need to replace the buffer here.
3834 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3835 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3837 u64_stats_update_begin(&ring->syncp);
3838 ring->stats.sw_err_cnt++;
3839 u64_stats_update_end(&ring->syncp);
3840 /* if alloc new buffer fail, exit directly
3841 * and reclear in up flow.
3843 netdev_warn(ring->tqp->handle->kinfo.netdev,
3844 "reserve buffer map failed, ret = %d\n",
3848 hns3_replace_buffer(ring, ring->next_to_use,
3851 ring_ptr_move_fw(ring, next_to_use);
3857 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
3859 while (ring->next_to_use != ring->next_to_clean) {
3860 /* When a buffer is not reused, it's memory has been
3861 * freed in hns3_handle_rx_bd or will be freed by
3862 * stack, so only need to unmap the buffer here.
3864 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3865 hns3_unmap_buffer(ring,
3866 &ring->desc_cb[ring->next_to_use]);
3867 ring->desc_cb[ring->next_to_use].dma = 0;
3870 ring_ptr_move_fw(ring, next_to_use);
3874 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3876 struct net_device *ndev = h->kinfo.netdev;
3877 struct hns3_nic_priv *priv = netdev_priv(ndev);
3878 struct hns3_enet_ring *ring;
3881 for (i = 0; i < h->kinfo.num_tqps; i++) {
3882 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3883 hns3_force_clear_rx_ring(ring);
3887 static void hns3_clear_all_ring(struct hnae3_handle *h)
3889 struct net_device *ndev = h->kinfo.netdev;
3890 struct hns3_nic_priv *priv = netdev_priv(ndev);
3893 for (i = 0; i < h->kinfo.num_tqps; i++) {
3894 struct netdev_queue *dev_queue;
3895 struct hns3_enet_ring *ring;
3897 ring = priv->ring_data[i].ring;
3898 hns3_clear_tx_ring(ring);
3899 dev_queue = netdev_get_tx_queue(ndev,
3900 priv->ring_data[i].queue_index);
3901 netdev_tx_reset_queue(dev_queue);
3903 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3904 /* Continue to clear other rings even if clearing some
3907 hns3_clear_rx_ring(ring);
3911 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3913 struct net_device *ndev = h->kinfo.netdev;
3914 struct hns3_nic_priv *priv = netdev_priv(ndev);
3915 struct hns3_enet_ring *rx_ring;
3919 for (i = 0; i < h->kinfo.num_tqps; i++) {
3920 ret = h->ae_algo->ops->reset_queue(h, i);
3924 hns3_init_ring_hw(priv->ring_data[i].ring);
3926 /* We need to clear tx ring here because self test will
3927 * use the ring and will not run down before up
3929 hns3_clear_tx_ring(priv->ring_data[i].ring);
3930 priv->ring_data[i].ring->next_to_clean = 0;
3931 priv->ring_data[i].ring->next_to_use = 0;
3933 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3934 hns3_init_ring_hw(rx_ring);
3935 ret = hns3_clear_rx_ring(rx_ring);
3939 /* We can not know the hardware head and tail when this
3940 * function is called in reset flow, so we reuse all desc.
3942 for (j = 0; j < rx_ring->desc_num; j++)
3943 hns3_reuse_buffer(rx_ring, j);
3945 rx_ring->next_to_clean = 0;
3946 rx_ring->next_to_use = 0;
3949 hns3_init_tx_ring_tc(priv);
3954 static void hns3_store_coal(struct hns3_nic_priv *priv)
3956 /* ethtool only support setting and querying one coal
3957 * configuation for now, so save the vector 0' coal
3958 * configuation here in order to restore it.
3960 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
3961 sizeof(struct hns3_enet_coalesce));
3962 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
3963 sizeof(struct hns3_enet_coalesce));
3966 static void hns3_restore_coal(struct hns3_nic_priv *priv)
3968 u16 vector_num = priv->vector_num;
3971 for (i = 0; i < vector_num; i++) {
3972 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
3973 sizeof(struct hns3_enet_coalesce));
3974 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
3975 sizeof(struct hns3_enet_coalesce));
3979 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3981 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
3982 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3983 struct net_device *ndev = kinfo->netdev;
3984 struct hns3_nic_priv *priv = netdev_priv(ndev);
3986 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
3989 /* it is cumbersome for hardware to pick-and-choose entries for deletion
3990 * from table space. Hence, for function reset software intervention is
3991 * required to delete the entries
3993 if (hns3_dev_ongoing_func_reset(ae_dev)) {
3994 hns3_remove_hw_addr(ndev);
3995 hns3_del_all_fd_rules(ndev, false);
3998 if (!netif_running(ndev))
4001 return hns3_nic_net_stop(ndev);
4004 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4006 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4007 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4010 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4012 if (netif_running(kinfo->netdev)) {
4013 ret = hns3_nic_net_open(kinfo->netdev);
4015 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4016 netdev_err(kinfo->netdev,
4017 "hns net up fail, ret=%d!\n", ret);
4025 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4027 struct net_device *netdev = handle->kinfo.netdev;
4028 struct hns3_nic_priv *priv = netdev_priv(netdev);
4031 /* Carrier off reporting is important to ethtool even BEFORE open */
4032 netif_carrier_off(netdev);
4034 ret = hns3_get_ring_config(priv);
4038 ret = hns3_nic_alloc_vector_data(priv);
4042 hns3_restore_coal(priv);
4044 ret = hns3_nic_init_vector_data(priv);
4046 goto err_dealloc_vector;
4048 ret = hns3_init_all_ring(priv);
4050 goto err_uninit_vector;
4052 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4057 hns3_nic_uninit_vector_data(priv);
4058 priv->ring_data = NULL;
4060 hns3_nic_dealloc_vector_data(priv);
4062 hns3_put_ring_config(priv);
4063 priv->ring_data = NULL;
4068 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4070 struct net_device *netdev = handle->kinfo.netdev;
4071 bool vlan_filter_enable;
4074 ret = hns3_init_mac_addr(netdev, false);
4078 ret = hns3_recover_hw_addr(netdev);
4082 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4086 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4087 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4089 /* Hardware table is only clear when pf resets */
4090 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4091 ret = hns3_restore_vlan(netdev);
4096 return hns3_restore_fd_rules(netdev);
4099 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4101 struct net_device *netdev = handle->kinfo.netdev;
4102 struct hns3_nic_priv *priv = netdev_priv(netdev);
4105 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4106 netdev_warn(netdev, "already uninitialized\n");
4110 hns3_force_clear_all_rx_ring(handle);
4112 ret = hns3_nic_uninit_vector_data(priv);
4114 netdev_err(netdev, "uninit vector error\n");
4118 hns3_store_coal(priv);
4120 ret = hns3_nic_dealloc_vector_data(priv);
4122 netdev_err(netdev, "dealloc vector error\n");
4124 ret = hns3_uninit_all_ring(priv);
4126 netdev_err(netdev, "uninit ring error\n");
4128 hns3_put_ring_config(priv);
4129 priv->ring_data = NULL;
4131 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
4136 static int hns3_reset_notify(struct hnae3_handle *handle,
4137 enum hnae3_reset_notify_type type)
4142 case HNAE3_UP_CLIENT:
4143 ret = hns3_reset_notify_up_enet(handle);
4145 case HNAE3_DOWN_CLIENT:
4146 ret = hns3_reset_notify_down_enet(handle);
4148 case HNAE3_INIT_CLIENT:
4149 ret = hns3_reset_notify_init_enet(handle);
4151 case HNAE3_UNINIT_CLIENT:
4152 ret = hns3_reset_notify_uninit_enet(handle);
4154 case HNAE3_RESTORE_CLIENT:
4155 ret = hns3_reset_notify_restore_enet(handle);
4164 int hns3_set_channels(struct net_device *netdev,
4165 struct ethtool_channels *ch)
4167 struct hnae3_handle *h = hns3_get_handle(netdev);
4168 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4169 bool rxfh_configured = netif_is_rxfh_configured(netdev);
4170 u32 new_tqp_num = ch->combined_count;
4174 if (ch->rx_count || ch->tx_count)
4177 if (new_tqp_num > hns3_get_max_available_channels(h) ||
4179 dev_err(&netdev->dev,
4180 "Change tqps fail, the tqp range is from 1 to %d",
4181 hns3_get_max_available_channels(h));
4185 if (kinfo->rss_size == new_tqp_num)
4188 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4192 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4196 org_tqp_num = h->kinfo.num_tqps;
4197 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured);
4199 ret = h->ae_algo->ops->set_channels(h, org_tqp_num,
4202 /* If revert to old tqp failed, fatal error occurred */
4203 dev_err(&netdev->dev,
4204 "Revert to old tqp num fail, ret=%d", ret);
4207 dev_info(&netdev->dev,
4208 "Change tqp num fail, Revert to old tqp num");
4210 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT);
4214 return hns3_reset_notify(h, HNAE3_UP_CLIENT);
4217 static const struct hnae3_client_ops client_ops = {
4218 .init_instance = hns3_client_init,
4219 .uninit_instance = hns3_client_uninit,
4220 .link_status_change = hns3_link_status_change,
4221 .setup_tc = hns3_client_setup_tc,
4222 .reset_notify = hns3_reset_notify,
4225 /* hns3_init_module - Driver registration routine
4226 * hns3_init_module is the first routine called when the driver is
4227 * loaded. All it does is register with the PCI subsystem.
4229 static int __init hns3_init_module(void)
4233 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4234 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4236 client.type = HNAE3_CLIENT_KNIC;
4237 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4240 client.ops = &client_ops;
4242 INIT_LIST_HEAD(&client.node);
4244 hns3_dbg_register_debugfs(hns3_driver_name);
4246 ret = hnae3_register_client(&client);
4248 goto err_reg_client;
4250 ret = pci_register_driver(&hns3_driver);
4252 goto err_reg_driver;
4257 hnae3_unregister_client(&client);
4259 hns3_dbg_unregister_debugfs();
4262 module_init(hns3_init_module);
4264 /* hns3_exit_module - Driver exit cleanup routine
4265 * hns3_exit_module is called just before the driver is removed
4268 static void __exit hns3_exit_module(void)
4270 pci_unregister_driver(&hns3_driver);
4271 hnae3_unregister_client(&client);
4272 hns3_dbg_unregister_debugfs();
4274 module_exit(hns3_exit_module);
4276 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4277 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4278 MODULE_LICENSE("GPL");
4279 MODULE_ALIAS("pci:hns-nic");
4280 MODULE_VERSION(HNS3_MOD_VERSION);