1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 * Google virtual Ethernet (gve) driver
4 * Copyright (C) 2015-2019 Google, Inc.
10 #include <linux/dma-mapping.h>
11 #include <linux/netdevice.h>
12 #include <linux/pci.h>
13 #include <linux/u64_stats_sync.h>
16 #ifndef PCI_VENDOR_ID_GOOGLE
17 #define PCI_VENDOR_ID_GOOGLE 0x1ae0
20 #define PCI_DEV_ID_GVNIC 0x0042
22 #define GVE_REGISTER_BAR 0
23 #define GVE_DOORBELL_BAR 2
25 /* Driver can alloc up to 2 segments for the header and 2 for the payload. */
26 #define GVE_TX_MAX_IOVEC 4
27 /* 1 for management, 1 for rx, 1 for tx */
28 #define GVE_MIN_MSIX 3
30 /* Numbers of gve tx/rx stats in stats report. */
31 #define GVE_TX_STATS_REPORT_NUM 5
32 #define GVE_RX_STATS_REPORT_NUM 2
34 /* Interval to schedule a stats report update, 20000ms. */
35 #define GVE_STATS_REPORT_TIMER_PERIOD 20000
37 /* Numbers of NIC tx/rx stats in stats report. */
38 #define NIC_TX_STATS_REPORT_NUM 0
39 #define NIC_RX_STATS_REPORT_NUM 4
41 #define GVE_DATA_SLOT_ADDR_PAGE_MASK (~(PAGE_SIZE - 1))
43 /* Each slot in the desc ring has a 1:1 mapping to a slot in the data ring */
44 struct gve_rx_desc_queue {
45 struct gve_rx_desc *desc_ring; /* the descriptor ring */
46 dma_addr_t bus; /* the bus for the desc_ring */
47 u8 seqno; /* the next expected seqno for this desc*/
50 /* The page info for a single slot in the RX data queue */
51 struct gve_rx_slot_page_info {
54 u8 page_offset; /* flipped to second half? */
58 /* A list of pages registered with the device during setup and used by a queue
61 struct gve_queue_page_list {
62 u32 id; /* unique id */
64 struct page **pages; /* list of num_entries pages */
65 dma_addr_t *page_buses; /* the dma addrs of the pages */
68 /* Each slot in the data ring has a 1:1 mapping to a slot in the desc ring */
69 struct gve_rx_data_queue {
70 union gve_rx_data_slot *data_ring; /* read by NIC */
71 dma_addr_t data_bus; /* dma mapping of the slots */
72 struct gve_rx_slot_page_info *page_info; /* page info of the buffers */
73 struct gve_queue_page_list *qpl; /* qpl assigned to this queue */
74 u8 raw_addressing; /* use raw_addressing? */
79 /* An RX ring that contains a power-of-two sized desc and data ring. */
82 struct gve_rx_desc_queue desc;
83 struct gve_rx_data_queue data;
84 u64 rbytes; /* free-running bytes received */
85 u64 rpackets; /* free-running packets received */
86 u32 cnt; /* free-running total number of completed packets */
87 u32 fill_cnt; /* free-running total number of descs and buffs posted */
88 u32 mask; /* masks the cnt and fill_cnt to the size of the ring */
89 u32 db_threshold; /* threshold for posting new buffs and descs */
90 u64 rx_copybreak_pkt; /* free-running count of copybreak packets */
91 u64 rx_copied_pkt; /* free-running total number of copied packets */
92 u64 rx_skb_alloc_fail; /* free-running count of skb alloc fails */
93 u64 rx_buf_alloc_fail; /* free-running count of buffer alloc fails */
94 u64 rx_desc_err_dropped_pkt; /* free-running count of packets dropped by descriptor error */
95 u32 q_num; /* queue index */
96 u32 ntfy_id; /* notification block index */
97 struct gve_queue_resources *q_resources; /* head and tail pointer idx */
98 dma_addr_t q_resources_bus; /* dma address for the queue resources */
99 struct u64_stats_sync statss; /* sync stats for 32bit archs */
102 /* A TX desc ring entry */
104 struct gve_tx_pkt_desc pkt; /* first desc for a packet */
105 struct gve_tx_seg_desc seg; /* subsequent descs for a packet */
108 /* Tracks the memory in the fifo occupied by a segment of a packet */
109 struct gve_tx_iovec {
110 u32 iov_offset; /* offset into this segment */
111 u32 iov_len; /* length */
112 u32 iov_padding; /* padding associated with this segment */
115 /* Tracks the memory in the fifo occupied by the skb. Mapped 1:1 to a desc
116 * ring entry but only used for a pkt_desc not a seg_desc
118 struct gve_tx_buffer_state {
119 struct sk_buff *skb; /* skb for this pkt */
120 struct gve_tx_iovec iov[GVE_TX_MAX_IOVEC]; /* segments of this pkt */
123 /* A TX buffer - each queue has one */
125 void *base; /* address of base of FIFO */
126 u32 size; /* total size */
127 atomic_t available; /* how much space is still available */
128 u32 head; /* offset to write at */
129 struct gve_queue_page_list *qpl; /* QPL mapped into this FIFO */
132 /* A TX ring that contains a power-of-two sized desc ring and a FIFO buffer */
134 /* Cacheline 0 -- Accessed & dirtied during transmit */
135 struct gve_tx_fifo tx_fifo;
136 u32 req; /* driver tracked head pointer */
137 u32 done; /* driver tracked tail pointer */
139 /* Cacheline 1 -- Accessed & dirtied during gve_clean_tx_done */
140 __be32 last_nic_done ____cacheline_aligned; /* NIC tail pointer */
141 u64 pkt_done; /* free-running - total packets completed */
142 u64 bytes_done; /* free-running - total bytes completed */
144 /* Cacheline 2 -- Read-mostly fields */
145 union gve_tx_desc *desc ____cacheline_aligned;
146 struct gve_tx_buffer_state *info; /* Maps 1:1 to a desc */
147 struct netdev_queue *netdev_txq;
148 struct gve_queue_resources *q_resources; /* head and tail pointer idx */
149 u32 mask; /* masks req and done down to queue size */
151 /* Slow-path fields */
152 u32 q_num ____cacheline_aligned; /* queue idx */
153 u32 stop_queue; /* count of queue stops */
154 u32 wake_queue; /* count of queue wakes */
155 u32 ntfy_id; /* notification block index */
156 dma_addr_t bus; /* dma address of the descr ring */
157 dma_addr_t q_resources_bus; /* dma address of the queue resources */
158 struct u64_stats_sync statss; /* sync stats for 32bit archs */
159 } ____cacheline_aligned;
161 /* Wraps the info for one irq including the napi struct and the queues
162 * associated with that irq.
164 struct gve_notify_block {
165 __be32 irq_db_index; /* idx into Bar2 - set by device, must be 1st */
166 char name[IFNAMSIZ + 16]; /* name registered with the kernel */
167 struct napi_struct napi; /* kernel napi struct for this block */
168 struct gve_priv *priv;
169 struct gve_tx_ring *tx; /* tx rings on this block */
170 struct gve_rx_ring *rx; /* rx rings on this block */
171 } ____cacheline_aligned;
173 /* Tracks allowed and current queue settings */
174 struct gve_queue_config {
176 u16 num_queues; /* current */
179 /* Tracks the available and used qpl IDs */
180 struct gve_qpl_config {
181 u32 qpl_map_size; /* map memory size */
182 unsigned long *qpl_id_map; /* bitmap of used qpl ids */
186 struct net_device *dev;
187 struct gve_tx_ring *tx; /* array of tx_cfg.num_queues */
188 struct gve_rx_ring *rx; /* array of rx_cfg.num_queues */
189 struct gve_queue_page_list *qpls; /* array of num qpls */
190 struct gve_notify_block *ntfy_blocks; /* array of num_ntfy_blks */
191 dma_addr_t ntfy_block_bus;
192 struct msix_entry *msix_vectors; /* array of num_ntfy_blks + 1 */
193 char mgmt_msix_name[IFNAMSIZ + 16];
195 __be32 *counter_array; /* array of num_event_counters */
196 dma_addr_t counter_array_bus;
198 u16 num_event_counters;
199 u16 tx_desc_cnt; /* num desc per ring */
200 u16 rx_desc_cnt; /* num desc per ring */
201 u16 tx_pages_per_qpl; /* tx buffer length */
202 u16 rx_data_slot_cnt; /* rx buffer length */
203 u64 max_registered_pages;
204 u64 num_registered_pages; /* num pages registered with NIC */
205 u32 rx_copybreak; /* copy packets smaller than this */
206 u16 default_num_queues; /* default num queues to set up */
207 u8 raw_addressing; /* 1 if this dev supports raw addressing, 0 otherwise */
209 struct gve_queue_config tx_cfg;
210 struct gve_queue_config rx_cfg;
211 struct gve_qpl_config qpl_cfg; /* map used QPL ids */
212 u32 num_ntfy_blks; /* spilt between TX and RX so must be even */
214 struct gve_registers __iomem *reg_bar0; /* see gve_register.h */
215 __be32 __iomem *db_bar2; /* "array" of doorbells */
216 u32 msg_enable; /* level for netif* netdev print macros */
217 struct pci_dev *pdev;
222 /* Admin queue - see gve_adminq.h*/
223 union gve_adminq_command *adminq;
224 dma_addr_t adminq_bus_addr;
225 u32 adminq_mask; /* masks prod_cnt to adminq size */
226 u32 adminq_prod_cnt; /* free-running count of AQ cmds executed */
227 u32 adminq_cmd_fail; /* free-running count of AQ cmds failed */
228 u32 adminq_timeouts; /* free-running count of AQ cmds timeouts */
229 /* free-running count of per AQ cmd executed */
230 u32 adminq_describe_device_cnt;
231 u32 adminq_cfg_device_resources_cnt;
232 u32 adminq_register_page_list_cnt;
233 u32 adminq_unregister_page_list_cnt;
234 u32 adminq_create_tx_queue_cnt;
235 u32 adminq_create_rx_queue_cnt;
236 u32 adminq_destroy_tx_queue_cnt;
237 u32 adminq_destroy_rx_queue_cnt;
238 u32 adminq_dcfg_device_resources_cnt;
239 u32 adminq_set_driver_parameter_cnt;
240 u32 adminq_report_stats_cnt;
241 u32 adminq_report_link_speed_cnt;
244 u32 interface_up_cnt; /* count of times interface turned up since last reset */
245 u32 interface_down_cnt; /* count of times interface turned down since last reset */
246 u32 reset_cnt; /* count of reset */
247 u32 page_alloc_fail; /* count of page alloc fails */
248 u32 dma_mapping_error; /* count of dma mapping errors */
249 u32 stats_report_trigger_cnt; /* count of device-requested stats-reports since last reset */
250 struct workqueue_struct *gve_wq;
251 struct work_struct service_task;
252 struct work_struct stats_report_task;
253 unsigned long service_task_flags;
254 unsigned long state_flags;
256 struct gve_stats_report *stats_report;
257 u64 stats_report_len;
258 dma_addr_t stats_report_bus; /* dma address for the stats report */
259 unsigned long ethtool_flags;
261 unsigned long stats_report_timer_period;
262 struct timer_list stats_report_timer;
264 /* Gvnic device link speed from hypervisor. */
268 enum gve_service_task_flags_bit {
269 GVE_PRIV_FLAGS_DO_RESET = 1,
270 GVE_PRIV_FLAGS_RESET_IN_PROGRESS = 2,
271 GVE_PRIV_FLAGS_PROBE_IN_PROGRESS = 3,
272 GVE_PRIV_FLAGS_DO_REPORT_STATS = 4,
275 enum gve_state_flags_bit {
276 GVE_PRIV_FLAGS_ADMIN_QUEUE_OK = 1,
277 GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK = 2,
278 GVE_PRIV_FLAGS_DEVICE_RINGS_OK = 3,
279 GVE_PRIV_FLAGS_NAPI_ENABLED = 4,
282 enum gve_ethtool_flags_bit {
283 GVE_PRIV_FLAGS_REPORT_STATS = 0,
286 static inline bool gve_get_do_reset(struct gve_priv *priv)
288 return test_bit(GVE_PRIV_FLAGS_DO_RESET, &priv->service_task_flags);
291 static inline void gve_set_do_reset(struct gve_priv *priv)
293 set_bit(GVE_PRIV_FLAGS_DO_RESET, &priv->service_task_flags);
296 static inline void gve_clear_do_reset(struct gve_priv *priv)
298 clear_bit(GVE_PRIV_FLAGS_DO_RESET, &priv->service_task_flags);
301 static inline bool gve_get_reset_in_progress(struct gve_priv *priv)
303 return test_bit(GVE_PRIV_FLAGS_RESET_IN_PROGRESS,
304 &priv->service_task_flags);
307 static inline void gve_set_reset_in_progress(struct gve_priv *priv)
309 set_bit(GVE_PRIV_FLAGS_RESET_IN_PROGRESS, &priv->service_task_flags);
312 static inline void gve_clear_reset_in_progress(struct gve_priv *priv)
314 clear_bit(GVE_PRIV_FLAGS_RESET_IN_PROGRESS, &priv->service_task_flags);
317 static inline bool gve_get_probe_in_progress(struct gve_priv *priv)
319 return test_bit(GVE_PRIV_FLAGS_PROBE_IN_PROGRESS,
320 &priv->service_task_flags);
323 static inline void gve_set_probe_in_progress(struct gve_priv *priv)
325 set_bit(GVE_PRIV_FLAGS_PROBE_IN_PROGRESS, &priv->service_task_flags);
328 static inline void gve_clear_probe_in_progress(struct gve_priv *priv)
330 clear_bit(GVE_PRIV_FLAGS_PROBE_IN_PROGRESS, &priv->service_task_flags);
333 static inline bool gve_get_do_report_stats(struct gve_priv *priv)
335 return test_bit(GVE_PRIV_FLAGS_DO_REPORT_STATS,
336 &priv->service_task_flags);
339 static inline void gve_set_do_report_stats(struct gve_priv *priv)
341 set_bit(GVE_PRIV_FLAGS_DO_REPORT_STATS, &priv->service_task_flags);
344 static inline void gve_clear_do_report_stats(struct gve_priv *priv)
346 clear_bit(GVE_PRIV_FLAGS_DO_REPORT_STATS, &priv->service_task_flags);
349 static inline bool gve_get_admin_queue_ok(struct gve_priv *priv)
351 return test_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags);
354 static inline void gve_set_admin_queue_ok(struct gve_priv *priv)
356 set_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags);
359 static inline void gve_clear_admin_queue_ok(struct gve_priv *priv)
361 clear_bit(GVE_PRIV_FLAGS_ADMIN_QUEUE_OK, &priv->state_flags);
364 static inline bool gve_get_device_resources_ok(struct gve_priv *priv)
366 return test_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags);
369 static inline void gve_set_device_resources_ok(struct gve_priv *priv)
371 set_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags);
374 static inline void gve_clear_device_resources_ok(struct gve_priv *priv)
376 clear_bit(GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK, &priv->state_flags);
379 static inline bool gve_get_device_rings_ok(struct gve_priv *priv)
381 return test_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags);
384 static inline void gve_set_device_rings_ok(struct gve_priv *priv)
386 set_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags);
389 static inline void gve_clear_device_rings_ok(struct gve_priv *priv)
391 clear_bit(GVE_PRIV_FLAGS_DEVICE_RINGS_OK, &priv->state_flags);
394 static inline bool gve_get_napi_enabled(struct gve_priv *priv)
396 return test_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags);
399 static inline void gve_set_napi_enabled(struct gve_priv *priv)
401 set_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags);
404 static inline void gve_clear_napi_enabled(struct gve_priv *priv)
406 clear_bit(GVE_PRIV_FLAGS_NAPI_ENABLED, &priv->state_flags);
409 static inline bool gve_get_report_stats(struct gve_priv *priv)
411 return test_bit(GVE_PRIV_FLAGS_REPORT_STATS, &priv->ethtool_flags);
414 static inline void gve_clear_report_stats(struct gve_priv *priv)
416 clear_bit(GVE_PRIV_FLAGS_REPORT_STATS, &priv->ethtool_flags);
419 /* Returns the address of the ntfy_blocks irq doorbell
421 static inline __be32 __iomem *gve_irq_doorbell(struct gve_priv *priv,
422 struct gve_notify_block *block)
424 return &priv->db_bar2[be32_to_cpu(block->irq_db_index)];
427 /* Returns the index into ntfy_blocks of the given tx ring's block
429 static inline u32 gve_tx_idx_to_ntfy(struct gve_priv *priv, u32 queue_idx)
434 /* Returns the index into ntfy_blocks of the given rx ring's block
436 static inline u32 gve_rx_idx_to_ntfy(struct gve_priv *priv, u32 queue_idx)
438 return (priv->num_ntfy_blks / 2) + queue_idx;
441 /* Returns the number of tx queue page lists
443 static inline u32 gve_num_tx_qpls(struct gve_priv *priv)
445 return priv->tx_cfg.num_queues;
448 /* Returns the number of rx queue page lists
450 static inline u32 gve_num_rx_qpls(struct gve_priv *priv)
452 return priv->raw_addressing ? 0 : priv->rx_cfg.num_queues;
455 /* Returns a pointer to the next available tx qpl in the list of qpls
458 struct gve_queue_page_list *gve_assign_tx_qpl(struct gve_priv *priv)
460 int id = find_first_zero_bit(priv->qpl_cfg.qpl_id_map,
461 priv->qpl_cfg.qpl_map_size);
463 /* we are out of tx qpls */
464 if (id >= gve_num_tx_qpls(priv))
467 set_bit(id, priv->qpl_cfg.qpl_id_map);
468 return &priv->qpls[id];
471 /* Returns a pointer to the next available rx qpl in the list of qpls
474 struct gve_queue_page_list *gve_assign_rx_qpl(struct gve_priv *priv)
476 int id = find_next_zero_bit(priv->qpl_cfg.qpl_id_map,
477 priv->qpl_cfg.qpl_map_size,
478 gve_num_tx_qpls(priv));
480 /* we are out of rx qpls */
481 if (id == priv->qpl_cfg.qpl_map_size)
484 set_bit(id, priv->qpl_cfg.qpl_id_map);
485 return &priv->qpls[id];
488 /* Unassigns the qpl with the given id
490 static inline void gve_unassign_qpl(struct gve_priv *priv, int id)
492 clear_bit(id, priv->qpl_cfg.qpl_id_map);
495 /* Returns the correct dma direction for tx and rx qpls
497 static inline enum dma_data_direction gve_qpl_dma_dir(struct gve_priv *priv,
500 if (id < gve_num_tx_qpls(priv))
501 return DMA_TO_DEVICE;
503 return DMA_FROM_DEVICE;
507 int gve_alloc_page(struct gve_priv *priv, struct device *dev,
508 struct page **page, dma_addr_t *dma,
509 enum dma_data_direction);
510 void gve_free_page(struct device *dev, struct page *page, dma_addr_t dma,
511 enum dma_data_direction);
513 netdev_tx_t gve_tx(struct sk_buff *skb, struct net_device *dev);
514 bool gve_tx_poll(struct gve_notify_block *block, int budget);
515 int gve_tx_alloc_rings(struct gve_priv *priv);
516 void gve_tx_free_rings(struct gve_priv *priv);
517 __be32 gve_tx_load_event_counter(struct gve_priv *priv,
518 struct gve_tx_ring *tx);
520 void gve_rx_write_doorbell(struct gve_priv *priv, struct gve_rx_ring *rx);
521 bool gve_rx_poll(struct gve_notify_block *block, int budget);
522 int gve_rx_alloc_rings(struct gve_priv *priv);
523 void gve_rx_free_rings(struct gve_priv *priv);
524 bool gve_clean_rx_done(struct gve_rx_ring *rx, int budget,
525 netdev_features_t feat);
527 void gve_schedule_reset(struct gve_priv *priv);
528 int gve_reset(struct gve_priv *priv, bool attempt_teardown);
529 int gve_adjust_queues(struct gve_priv *priv,
530 struct gve_queue_config new_rx_config,
531 struct gve_queue_config new_tx_config);
532 /* report stats handling */
533 void gve_handle_report_stats(struct gve_priv *priv);
534 /* exported by ethtool.c */
535 extern const struct ethtool_ops gve_ethtool_ops;
536 /* needed by ethtool */
537 extern const char gve_version_str[];