drivers/net/ethernet/freescale/ucc_geth.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
   4  *
   5  * Author: Shlomi Gridish <gridish@freescale.com>
   6  *         Li Yang <leoli@freescale.com>
   7  *
   8  * Description:
   9  * QE UCC Gigabit Ethernet Driver
  10  */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/slab.h>
  18 #include <linux/stddef.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/mm.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/mii.h>
  28 #include <linux/phy.h>
  29 #include <linux/phy_fixed.h>
  30 #include <linux/workqueue.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_mdio.h>
  34 #include <linux/of_net.h>
  35 #include <linux/of_platform.h>
  36
  37 #include <linux/uaccess.h>
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40 #include <soc/fsl/qe/immap_qe.h>
  41 #include <soc/fsl/qe/qe.h>
  42 #include <soc/fsl/qe/ucc.h>
  43 #include <soc/fsl/qe/ucc_fast.h>
  44 #include <asm/machdep.h>
  45
  46 #include "ucc_geth.h"
  47
  48 #undef DEBUG
  49
  50 #define ugeth_printk(level, format, arg...)  \
  51         printk(level format "\n", ## arg)
  52
  53 #define ugeth_dbg(format, arg...)            \
  54         ugeth_printk(KERN_DEBUG , format , ## arg)
  55
  56 #ifdef UGETH_VERBOSE_DEBUG
  57 #define ugeth_vdbg ugeth_dbg
  58 #else
  59 #define ugeth_vdbg(fmt, args...) do { } while (0)
  60 #endif                          /* UGETH_VERBOSE_DEBUG */
  61 #define UGETH_MSG_DEFAULT       (NETIF_MSG_IFUP << 1 ) - 1
  62
  63
  64 static DEFINE_SPINLOCK(ugeth_lock);
  65
  66 static struct {
  67         u32 msg_enable;
  68 } debug = { -1 };
  69
  70 module_param_named(debug, debug.msg_enable, int, 0);
  71 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
  72
  73 static struct ucc_geth_info ugeth_primary_info = {
  74         .uf_info = {
  75                     .bd_mem_part = MEM_PART_SYSTEM,
  76                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
  77                     .max_rx_buf_length = 1536,
  78                     /* adjusted at startup if max-speed 1000 */
  79                     .urfs = UCC_GETH_URFS_INIT,
  80                     .urfet = UCC_GETH_URFET_INIT,
  81                     .urfset = UCC_GETH_URFSET_INIT,
  82                     .utfs = UCC_GETH_UTFS_INIT,
  83                     .utfet = UCC_GETH_UTFET_INIT,
  84                     .utftt = UCC_GETH_UTFTT_INIT,
  85                     .ufpt = 256,
  86                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
  87                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
  88                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
  89                     .renc = UCC_FAST_RX_ENCODING_NRZ,
  90                     .tcrc = UCC_FAST_16_BIT_CRC,
  91                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
  92                     },
  93         .numQueuesTx = 1,
  94         .numQueuesRx = 1,
  95         .extendedFilteringChainPointer = ((uint32_t) NULL),
  96         .typeorlen = 3072 /*1536 */ ,
  97         .nonBackToBackIfgPart1 = 0x40,
  98         .nonBackToBackIfgPart2 = 0x60,
  99         .miminumInterFrameGapEnforcement = 0x50,
 100         .backToBackInterFrameGap = 0x60,
 101         .mblinterval = 128,
 102         .nortsrbytetime = 5,
 103         .fracsiz = 1,
 104         .strictpriorityq = 0xff,
 105         .altBebTruncation = 0xa,
 106         .excessDefer = 1,
 107         .maxRetransmission = 0xf,
 108         .collisionWindow = 0x37,
 109         .receiveFlowControl = 1,
 110         .transmitFlowControl = 1,
 111         .maxGroupAddrInHash = 4,
 112         .maxIndAddrInHash = 4,
 113         .prel = 7,
 114         .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
 115         .minFrameLength = 64,
 116         .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
 117         .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
 118         .vlantype = 0x8100,
 119         .ecamptr = ((uint32_t) NULL),
 120         .eventRegMask = UCCE_OTHER,
 121         .pausePeriod = 0xf000,
 122         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
 123         .bdRingLenTx = {
 124                         TX_BD_RING_LEN,
 125                         TX_BD_RING_LEN,
 126                         TX_BD_RING_LEN,
 127                         TX_BD_RING_LEN,
 128                         TX_BD_RING_LEN,
 129                         TX_BD_RING_LEN,
 130                         TX_BD_RING_LEN,
 131                         TX_BD_RING_LEN},
 132
 133         .bdRingLenRx = {
 134                         RX_BD_RING_LEN,
 135                         RX_BD_RING_LEN,
 136                         RX_BD_RING_LEN,
 137                         RX_BD_RING_LEN,
 138                         RX_BD_RING_LEN,
 139                         RX_BD_RING_LEN,
 140                         RX_BD_RING_LEN,
 141                         RX_BD_RING_LEN},
 142
 143         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
 144         .largestexternallookupkeysize =
 145             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
 146         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
 147                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
 148                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
 149         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
 150         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
 151         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
 152         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
 153         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
 154         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
 155         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
 156         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 157         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 158 };
 159
 160 static struct ucc_geth_info ugeth_info[8];
 161
 162 #ifdef DEBUG
 163 static void mem_disp(u8 *addr, int size)
 164 {
 165         u8 *i;
 166         int size16Aling = (size >> 4) << 4;
 167         int size4Aling = (size >> 2) << 2;
 168         int notAlign = 0;
 169         if (size % 16)
 170                 notAlign = 1;
 171
 172         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
 173                 printk("0x%08x: %08x %08x %08x %08x\r\n",
 174                        (u32) i,
 175                        *((u32 *) (i)),
 176                        *((u32 *) (i + 4)),
 177                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
 178         if (notAlign == 1)
 179                 printk("0x%08x: ", (u32) i);
 180         for (; (u32) i < (u32) addr + size4Aling; i += 4)
 181                 printk("%08x ", *((u32 *) (i)));
 182         for (; (u32) i < (u32) addr + size; i++)
 183                 printk("%02x", *((i)));
 184         if (notAlign == 1)
 185                 printk("\r\n");
 186 }
 187 #endif /* DEBUG */
 188
 189 static struct list_head *dequeue(struct list_head *lh)
 190 {
 191         unsigned long flags;
 192
 193         spin_lock_irqsave(&ugeth_lock, flags);
 194         if (!list_empty(lh)) {
 195                 struct list_head *node = lh->next;
 196                 list_del(node);
 197                 spin_unlock_irqrestore(&ugeth_lock, flags);
 198                 return node;
 199         } else {
 200                 spin_unlock_irqrestore(&ugeth_lock, flags);
 201                 return NULL;
 202         }
 203 }
 204
 205 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
 206                 u8 __iomem *bd)
 207 {
 208         struct sk_buff *skb;
 209
 210         skb = netdev_alloc_skb(ugeth->ndev,
 211                                ugeth->ug_info->uf_info.max_rx_buf_length +
 212                                UCC_GETH_RX_DATA_BUF_ALIGNMENT);
 213         if (!skb)
 214                 return NULL;
 215
 216         /* We need the data buffer to be aligned properly.  We will reserve
 217          * as many bytes as needed to align the data properly
 218          */
 219         skb_reserve(skb,
 220                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 221                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 222                                               1)));
 223
 224         out_be32(&((struct qe_bd __iomem *)bd)->buf,
 225                       dma_map_single(ugeth->dev,
 226                                      skb->data,
 227                                      ugeth->ug_info->uf_info.max_rx_buf_length +
 228                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
 229                                      DMA_FROM_DEVICE));
 230
 231         out_be32((u32 __iomem *)bd,
 232                         (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
 233
 234         return skb;
 235 }
 236
 237 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
 238 {
 239         u8 __iomem *bd;
 240         u32 bd_status;
 241         struct sk_buff *skb;
 242         int i;
 243
 244         bd = ugeth->p_rx_bd_ring[rxQ];
 245         i = 0;
 246
 247         do {
 248                 bd_status = in_be32((u32 __iomem *)bd);
 249                 skb = get_new_skb(ugeth, bd);
 250
 251                 if (!skb)       /* If can not allocate data buffer,
 252                                 abort. Cleanup will be elsewhere */
 253                         return -ENOMEM;
 254
 255                 ugeth->rx_skbuff[rxQ][i] = skb;
 256
 257                 /* advance the BD pointer */
 258                 bd += sizeof(struct qe_bd);
 259                 i++;
 260         } while (!(bd_status & R_W));
 261
 262         return 0;
 263 }
 264
 265 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
 266                                   u32 *p_start,
 267                                   u8 num_entries,
 268                                   u32 thread_size,
 269                                   u32 thread_alignment,
 270                                   unsigned int risc,
 271                                   int skip_page_for_first_entry)
 272 {
 273         u32 init_enet_offset;
 274         u8 i;
 275         int snum;
 276
 277         for (i = 0; i < num_entries; i++) {
 278                 if ((snum = qe_get_snum()) < 0) {
 279                         if (netif_msg_ifup(ugeth))
 280                                 pr_err("Can not get SNUM\n");
 281                         return snum;
 282                 }
 283                 if ((i == 0) && skip_page_for_first_entry)
 284                 /* First entry of Rx does not have page */
 285                         init_enet_offset = 0;
 286                 else {
 287                         init_enet_offset =
 288                             qe_muram_alloc(thread_size, thread_alignment);
 289                         if (IS_ERR_VALUE(init_enet_offset)) {
 290                                 if (netif_msg_ifup(ugeth))
 291                                         pr_err("Can not allocate DPRAM memory\n");
 292                                 qe_put_snum((u8) snum);
 293                                 return -ENOMEM;
 294                         }
 295                 }
 296                 *(p_start++) =
 297                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
 298                     | risc;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
 305                                     u32 *p_start,
 306                                     u8 num_entries,
 307                                     unsigned int risc,
 308                                     int skip_page_for_first_entry)
 309 {
 310         u32 init_enet_offset;
 311         u8 i;
 312         int snum;
 313
 314         for (i = 0; i < num_entries; i++) {
 315                 u32 val = *p_start;
 316
 317                 /* Check that this entry was actually valid --
 318                 needed in case failed in allocations */
 319                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 320                         snum =
 321                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 322                             ENET_INIT_PARAM_SNUM_SHIFT;
 323                         qe_put_snum((u8) snum);
 324                         if (!((i == 0) && skip_page_for_first_entry)) {
 325                         /* First entry of Rx does not have page */
 326                                 init_enet_offset =
 327                                     (val & ENET_INIT_PARAM_PTR_MASK);
 328                                 qe_muram_free(init_enet_offset);
 329                         }
 330                         *p_start++ = 0;
 331                 }
 332         }
 333
 334         return 0;
 335 }
 336
 337 #ifdef DEBUG
 338 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
 339                                   u32 __iomem *p_start,
 340                                   u8 num_entries,
 341                                   u32 thread_size,
 342                                   unsigned int risc,
 343                                   int skip_page_for_first_entry)
 344 {
 345         u32 init_enet_offset;
 346         u8 i;
 347         int snum;
 348
 349         for (i = 0; i < num_entries; i++) {
 350                 u32 val = in_be32(p_start);
 351
 352                 /* Check that this entry was actually valid --
 353                 needed in case failed in allocations */
 354                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 355                         snum =
 356                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 357                             ENET_INIT_PARAM_SNUM_SHIFT;
 358                         qe_put_snum((u8) snum);
 359                         if (!((i == 0) && skip_page_for_first_entry)) {
 360                         /* First entry of Rx does not have page */
 361                                 init_enet_offset =
 362                                     (in_be32(p_start) &
 363                                      ENET_INIT_PARAM_PTR_MASK);
 364                                 pr_info("Init enet entry %d:\n", i);
 365                                 pr_info("Base address: 0x%08x\n",
 366                                         (u32)qe_muram_addr(init_enet_offset));
 367                                 mem_disp(qe_muram_addr(init_enet_offset),
 368                                          thread_size);
 369                         }
 370                         p_start++;
 371                 }
 372         }
 373
 374         return 0;
 375 }
 376 #endif
 377
 378 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
 379 {
 380         kfree(enet_addr_cont);
 381 }
 382
 383 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
 384 {
 385         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
 386         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
 387         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
 388 }
 389
 390 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
 391 {
 392         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 393
 394         if (paddr_num >= NUM_OF_PADDRS) {
 395                 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num);
 396                 return -EINVAL;
 397         }
 398
 399         p_82xx_addr_filt =
 400             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 401             addressfiltering;
 402
 403         /* Writing address ff.ff.ff.ff.ff.ff disables address
 404         recognition for this register */
 405         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
 406         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
 407         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
 408
 409         return 0;
 410 }
 411
 412 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
 413                                 u8 *p_enet_addr)
 414 {
 415         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 416         u32 cecr_subblock;
 417
 418         p_82xx_addr_filt =
 419             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 420             addressfiltering;
 421
 422         cecr_subblock =
 423             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
 424
 425         /* Ethernet frames are defined in Little Endian mode,
 426         therefore to insert */
 427         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
 428
 429         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
 430
 431         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
 432                      QE_CR_PROTOCOL_ETHERNET, 0);
 433 }
 434
 435 #ifdef DEBUG
 436 static void get_statistics(struct ucc_geth_private *ugeth,
 437                            struct ucc_geth_tx_firmware_statistics *
 438                            tx_firmware_statistics,
 439                            struct ucc_geth_rx_firmware_statistics *
 440                            rx_firmware_statistics,
 441                            struct ucc_geth_hardware_statistics *hardware_statistics)
 442 {
 443         struct ucc_fast __iomem *uf_regs;
 444         struct ucc_geth __iomem *ug_regs;
 445         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
 446         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
 447
 448         ug_regs = ugeth->ug_regs;
 449         uf_regs = (struct ucc_fast __iomem *) ug_regs;
 450         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
 451         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
 452
 453         /* Tx firmware only if user handed pointer and driver actually
 454         gathers Tx firmware statistics */
 455         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
 456                 tx_firmware_statistics->sicoltx =
 457                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
 458                 tx_firmware_statistics->mulcoltx =
 459                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
 460                 tx_firmware_statistics->latecoltxfr =
 461                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
 462                 tx_firmware_statistics->frabortduecol =
 463                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
 464                 tx_firmware_statistics->frlostinmactxer =
 465                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
 466                 tx_firmware_statistics->carriersenseertx =
 467                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
 468                 tx_firmware_statistics->frtxok =
 469                     in_be32(&p_tx_fw_statistics_pram->frtxok);
 470                 tx_firmware_statistics->txfrexcessivedefer =
 471                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
 472                 tx_firmware_statistics->txpkts256 =
 473                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
 474                 tx_firmware_statistics->txpkts512 =
 475                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
 476                 tx_firmware_statistics->txpkts1024 =
 477                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
 478                 tx_firmware_statistics->txpktsjumbo =
 479                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
 480         }
 481
 482         /* Rx firmware only if user handed pointer and driver actually
 483          * gathers Rx firmware statistics */
 484         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
 485                 int i;
 486                 rx_firmware_statistics->frrxfcser =
 487                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
 488                 rx_firmware_statistics->fraligner =
 489                     in_be32(&p_rx_fw_statistics_pram->fraligner);
 490                 rx_firmware_statistics->inrangelenrxer =
 491                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
 492                 rx_firmware_statistics->outrangelenrxer =
 493                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
 494                 rx_firmware_statistics->frtoolong =
 495                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
 496                 rx_firmware_statistics->runt =
 497                     in_be32(&p_rx_fw_statistics_pram->runt);
 498                 rx_firmware_statistics->verylongevent =
 499                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
 500                 rx_firmware_statistics->symbolerror =
 501                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
 502                 rx_firmware_statistics->dropbsy =
 503                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
 504                 for (i = 0; i < 0x8; i++)
 505                         rx_firmware_statistics->res0[i] =
 506                             p_rx_fw_statistics_pram->res0[i];
 507                 rx_firmware_statistics->mismatchdrop =
 508                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
 509                 rx_firmware_statistics->underpkts =
 510                     in_be32(&p_rx_fw_statistics_pram->underpkts);
 511                 rx_firmware_statistics->pkts256 =
 512                     in_be32(&p_rx_fw_statistics_pram->pkts256);
 513                 rx_firmware_statistics->pkts512 =
 514                     in_be32(&p_rx_fw_statistics_pram->pkts512);
 515                 rx_firmware_statistics->pkts1024 =
 516                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
 517                 rx_firmware_statistics->pktsjumbo =
 518                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
 519                 rx_firmware_statistics->frlossinmacer =
 520                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
 521                 rx_firmware_statistics->pausefr =
 522                     in_be32(&p_rx_fw_statistics_pram->pausefr);
 523                 for (i = 0; i < 0x4; i++)
 524                         rx_firmware_statistics->res1[i] =
 525                             p_rx_fw_statistics_pram->res1[i];
 526                 rx_firmware_statistics->removevlan =
 527                     in_be32(&p_rx_fw_statistics_pram->removevlan);
 528                 rx_firmware_statistics->replacevlan =
 529                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
 530                 rx_firmware_statistics->insertvlan =
 531                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
 532         }
 533
 534         /* Hardware only if user handed pointer and driver actually
 535         gathers hardware statistics */
 536         if (hardware_statistics &&
 537             (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
 538                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
 539                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
 540                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
 541                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
 542                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
 543                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
 544                 hardware_statistics->txok = in_be32(&ug_regs->txok);
 545                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
 546                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
 547                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
 548                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
 549                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
 550                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
 551                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
 552                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
 553         }
 554 }
 555
 556 static void dump_bds(struct ucc_geth_private *ugeth)
 557 {
 558         int i;
 559         int length;
 560
 561         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 562                 if (ugeth->p_tx_bd_ring[i]) {
 563                         length =
 564                             (ugeth->ug_info->bdRingLenTx[i] *
 565                              sizeof(struct qe_bd));
 566                         pr_info("TX BDs[%d]\n", i);
 567                         mem_disp(ugeth->p_tx_bd_ring[i], length);
 568                 }
 569         }
 570         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 571                 if (ugeth->p_rx_bd_ring[i]) {
 572                         length =
 573                             (ugeth->ug_info->bdRingLenRx[i] *
 574                              sizeof(struct qe_bd));
 575                         pr_info("RX BDs[%d]\n", i);
 576                         mem_disp(ugeth->p_rx_bd_ring[i], length);
 577                 }
 578         }
 579 }
 580
 581 static void dump_regs(struct ucc_geth_private *ugeth)
 582 {
 583         int i;
 584
 585         pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
 586         pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
 587
 588         pr_info("maccfg1    : addr - 0x%08x, val - 0x%08x\n",
 589                 (u32)&ugeth->ug_regs->maccfg1,
 590                 in_be32(&ugeth->ug_regs->maccfg1));
 591         pr_info("maccfg2    : addr - 0x%08x, val - 0x%08x\n",
 592                 (u32)&ugeth->ug_regs->maccfg2,
 593                 in_be32(&ugeth->ug_regs->maccfg2));
 594         pr_info("ipgifg     : addr - 0x%08x, val - 0x%08x\n",
 595                 (u32)&ugeth->ug_regs->ipgifg,
 596                 in_be32(&ugeth->ug_regs->ipgifg));
 597         pr_info("hafdup     : addr - 0x%08x, val - 0x%08x\n",
 598                 (u32)&ugeth->ug_regs->hafdup,
 599                 in_be32(&ugeth->ug_regs->hafdup));
 600         pr_info("ifctl      : addr - 0x%08x, val - 0x%08x\n",
 601                 (u32)&ugeth->ug_regs->ifctl,
 602                 in_be32(&ugeth->ug_regs->ifctl));
 603         pr_info("ifstat     : addr - 0x%08x, val - 0x%08x\n",
 604                 (u32)&ugeth->ug_regs->ifstat,
 605                 in_be32(&ugeth->ug_regs->ifstat));
 606         pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
 607                 (u32)&ugeth->ug_regs->macstnaddr1,
 608                 in_be32(&ugeth->ug_regs->macstnaddr1));
 609         pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
 610                 (u32)&ugeth->ug_regs->macstnaddr2,
 611                 in_be32(&ugeth->ug_regs->macstnaddr2));
 612         pr_info("uempr      : addr - 0x%08x, val - 0x%08x\n",
 613                 (u32)&ugeth->ug_regs->uempr,
 614                 in_be32(&ugeth->ug_regs->uempr));
 615         pr_info("utbipar    : addr - 0x%08x, val - 0x%08x\n",
 616                 (u32)&ugeth->ug_regs->utbipar,
 617                 in_be32(&ugeth->ug_regs->utbipar));
 618         pr_info("uescr      : addr - 0x%08x, val - 0x%04x\n",
 619                 (u32)&ugeth->ug_regs->uescr,
 620                 in_be16(&ugeth->ug_regs->uescr));
 621         pr_info("tx64       : addr - 0x%08x, val - 0x%08x\n",
 622                 (u32)&ugeth->ug_regs->tx64,
 623                 in_be32(&ugeth->ug_regs->tx64));
 624         pr_info("tx127      : addr - 0x%08x, val - 0x%08x\n",
 625                 (u32)&ugeth->ug_regs->tx127,
 626                 in_be32(&ugeth->ug_regs->tx127));
 627         pr_info("tx255      : addr - 0x%08x, val - 0x%08x\n",
 628                 (u32)&ugeth->ug_regs->tx255,
 629                 in_be32(&ugeth->ug_regs->tx255));
 630         pr_info("rx64       : addr - 0x%08x, val - 0x%08x\n",
 631                 (u32)&ugeth->ug_regs->rx64,
 632                 in_be32(&ugeth->ug_regs->rx64));
 633         pr_info("rx127      : addr - 0x%08x, val - 0x%08x\n",
 634                 (u32)&ugeth->ug_regs->rx127,
 635                 in_be32(&ugeth->ug_regs->rx127));
 636         pr_info("rx255      : addr - 0x%08x, val - 0x%08x\n",
 637                 (u32)&ugeth->ug_regs->rx255,
 638                 in_be32(&ugeth->ug_regs->rx255));
 639         pr_info("txok       : addr - 0x%08x, val - 0x%08x\n",
 640                 (u32)&ugeth->ug_regs->txok,
 641                 in_be32(&ugeth->ug_regs->txok));
 642         pr_info("txcf       : addr - 0x%08x, val - 0x%04x\n",
 643                 (u32)&ugeth->ug_regs->txcf,
 644                 in_be16(&ugeth->ug_regs->txcf));
 645         pr_info("tmca       : addr - 0x%08x, val - 0x%08x\n",
 646                 (u32)&ugeth->ug_regs->tmca,
 647                 in_be32(&ugeth->ug_regs->tmca));
 648         pr_info("tbca       : addr - 0x%08x, val - 0x%08x\n",
 649                 (u32)&ugeth->ug_regs->tbca,
 650                 in_be32(&ugeth->ug_regs->tbca));
 651         pr_info("rxfok      : addr - 0x%08x, val - 0x%08x\n",
 652                 (u32)&ugeth->ug_regs->rxfok,
 653                 in_be32(&ugeth->ug_regs->rxfok));
 654         pr_info("rxbok      : addr - 0x%08x, val - 0x%08x\n",
 655                 (u32)&ugeth->ug_regs->rxbok,
 656                 in_be32(&ugeth->ug_regs->rxbok));
 657         pr_info("rbyt       : addr - 0x%08x, val - 0x%08x\n",
 658                 (u32)&ugeth->ug_regs->rbyt,
 659                 in_be32(&ugeth->ug_regs->rbyt));
 660         pr_info("rmca       : addr - 0x%08x, val - 0x%08x\n",
 661                 (u32)&ugeth->ug_regs->rmca,
 662                 in_be32(&ugeth->ug_regs->rmca));
 663         pr_info("rbca       : addr - 0x%08x, val - 0x%08x\n",
 664                 (u32)&ugeth->ug_regs->rbca,
 665                 in_be32(&ugeth->ug_regs->rbca));
 666         pr_info("scar       : addr - 0x%08x, val - 0x%08x\n",
 667                 (u32)&ugeth->ug_regs->scar,
 668                 in_be32(&ugeth->ug_regs->scar));
 669         pr_info("scam       : addr - 0x%08x, val - 0x%08x\n",
 670                 (u32)&ugeth->ug_regs->scam,
 671                 in_be32(&ugeth->ug_regs->scam));
 672
 673         if (ugeth->p_thread_data_tx) {
 674                 int numThreadsTxNumerical;
 675                 switch (ugeth->ug_info->numThreadsTx) {
 676                 case UCC_GETH_NUM_OF_THREADS_1:
 677                         numThreadsTxNumerical = 1;
 678                         break;
 679                 case UCC_GETH_NUM_OF_THREADS_2:
 680                         numThreadsTxNumerical = 2;
 681                         break;
 682                 case UCC_GETH_NUM_OF_THREADS_4:
 683                         numThreadsTxNumerical = 4;
 684                         break;
 685                 case UCC_GETH_NUM_OF_THREADS_6:
 686                         numThreadsTxNumerical = 6;
 687                         break;
 688                 case UCC_GETH_NUM_OF_THREADS_8:
 689                         numThreadsTxNumerical = 8;
 690                         break;
 691                 default:
 692                         numThreadsTxNumerical = 0;
 693                         break;
 694                 }
 695
 696                 pr_info("Thread data TXs:\n");
 697                 pr_info("Base address: 0x%08x\n",
 698                         (u32)ugeth->p_thread_data_tx);
 699                 for (i = 0; i < numThreadsTxNumerical; i++) {
 700                         pr_info("Thread data TX[%d]:\n", i);
 701                         pr_info("Base address: 0x%08x\n",
 702                                 (u32)&ugeth->p_thread_data_tx[i]);
 703                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
 704                                  sizeof(struct ucc_geth_thread_data_tx));
 705                 }
 706         }
 707         if (ugeth->p_thread_data_rx) {
 708                 int numThreadsRxNumerical;
 709                 switch (ugeth->ug_info->numThreadsRx) {
 710                 case UCC_GETH_NUM_OF_THREADS_1:
 711                         numThreadsRxNumerical = 1;
 712                         break;
 713                 case UCC_GETH_NUM_OF_THREADS_2:
 714                         numThreadsRxNumerical = 2;
 715                         break;
 716                 case UCC_GETH_NUM_OF_THREADS_4:
 717                         numThreadsRxNumerical = 4;
 718                         break;
 719                 case UCC_GETH_NUM_OF_THREADS_6:
 720                         numThreadsRxNumerical = 6;
 721                         break;
 722                 case UCC_GETH_NUM_OF_THREADS_8:
 723                         numThreadsRxNumerical = 8;
 724                         break;
 725                 default:
 726                         numThreadsRxNumerical = 0;
 727                         break;
 728                 }
 729
 730                 pr_info("Thread data RX:\n");
 731                 pr_info("Base address: 0x%08x\n",
 732                         (u32)ugeth->p_thread_data_rx);
 733                 for (i = 0; i < numThreadsRxNumerical; i++) {
 734                         pr_info("Thread data RX[%d]:\n", i);
 735                         pr_info("Base address: 0x%08x\n",
 736                                 (u32)&ugeth->p_thread_data_rx[i]);
 737                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
 738                                  sizeof(struct ucc_geth_thread_data_rx));
 739                 }
 740         }
 741         if (ugeth->p_exf_glbl_param) {
 742                 pr_info("EXF global param:\n");
 743                 pr_info("Base address: 0x%08x\n",
 744                         (u32)ugeth->p_exf_glbl_param);
 745                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
 746                          sizeof(*ugeth->p_exf_glbl_param));
 747         }
 748         if (ugeth->p_tx_glbl_pram) {
 749                 pr_info("TX global param:\n");
 750                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
 751                 pr_info("temoder      : addr - 0x%08x, val - 0x%04x\n",
 752                         (u32)&ugeth->p_tx_glbl_pram->temoder,
 753                         in_be16(&ugeth->p_tx_glbl_pram->temoder));
 754                pr_info("sqptr        : addr - 0x%08x, val - 0x%08x\n",
 755                         (u32)&ugeth->p_tx_glbl_pram->sqptr,
 756                         in_be32(&ugeth->p_tx_glbl_pram->sqptr));
 757                 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
 758                         (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
 759                         in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
 760                 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
 761                         (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
 762                         in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
 763                 pr_info("tstate       : addr - 0x%08x, val - 0x%08x\n",
 764                         (u32)&ugeth->p_tx_glbl_pram->tstate,
 765                         in_be32(&ugeth->p_tx_glbl_pram->tstate));
 766                 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
 767                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
 768                         ugeth->p_tx_glbl_pram->iphoffset[0]);
 769                 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
 770                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
 771                         ugeth->p_tx_glbl_pram->iphoffset[1]);
 772                 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
 773                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
 774                         ugeth->p_tx_glbl_pram->iphoffset[2]);
 775                 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
 776                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
 777                         ugeth->p_tx_glbl_pram->iphoffset[3]);
 778                 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
 779                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
 780                         ugeth->p_tx_glbl_pram->iphoffset[4]);
 781                 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
 782                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
 783                         ugeth->p_tx_glbl_pram->iphoffset[5]);
 784                 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
 785                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
 786                         ugeth->p_tx_glbl_pram->iphoffset[6]);
 787                 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
 788                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
 789                         ugeth->p_tx_glbl_pram->iphoffset[7]);
 790                 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
 791                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
 792                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
 793                 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
 794                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
 795                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
 796                 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
 797                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
 798                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
 799                 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
 800                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
 801                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
 802                 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
 803                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
 804                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
 805                 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
 806                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
 807                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
 808                 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
 809                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
 810                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
 811                 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
 812                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
 813                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
 814                 pr_info("tqptr        : addr - 0x%08x, val - 0x%08x\n",
 815                         (u32)&ugeth->p_tx_glbl_pram->tqptr,
 816                         in_be32(&ugeth->p_tx_glbl_pram->tqptr));
 817         }
 818         if (ugeth->p_rx_glbl_pram) {
 819                 pr_info("RX global param:\n");
 820                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
 821                 pr_info("remoder         : addr - 0x%08x, val - 0x%08x\n",
 822                         (u32)&ugeth->p_rx_glbl_pram->remoder,
 823                         in_be32(&ugeth->p_rx_glbl_pram->remoder));
 824                 pr_info("rqptr           : addr - 0x%08x, val - 0x%08x\n",
 825                         (u32)&ugeth->p_rx_glbl_pram->rqptr,
 826                         in_be32(&ugeth->p_rx_glbl_pram->rqptr));
 827                 pr_info("typeorlen       : addr - 0x%08x, val - 0x%04x\n",
 828                         (u32)&ugeth->p_rx_glbl_pram->typeorlen,
 829                         in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
 830                 pr_info("rxgstpack       : addr - 0x%08x, val - 0x%02x\n",
 831                         (u32)&ugeth->p_rx_glbl_pram->rxgstpack,
 832                         ugeth->p_rx_glbl_pram->rxgstpack);
 833                 pr_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x\n",
 834                         (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
 835                         in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
 836                 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
 837                         (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
 838                         in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
 839                 pr_info("rstate          : addr - 0x%08x, val - 0x%02x\n",
 840                         (u32)&ugeth->p_rx_glbl_pram->rstate,
 841                         ugeth->p_rx_glbl_pram->rstate);
 842                 pr_info("mrblr           : addr - 0x%08x, val - 0x%04x\n",
 843                         (u32)&ugeth->p_rx_glbl_pram->mrblr,
 844                         in_be16(&ugeth->p_rx_glbl_pram->mrblr));
 845                 pr_info("rbdqptr         : addr - 0x%08x, val - 0x%08x\n",
 846                         (u32)&ugeth->p_rx_glbl_pram->rbdqptr,
 847                         in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
 848                 pr_info("mflr            : addr - 0x%08x, val - 0x%04x\n",
 849                         (u32)&ugeth->p_rx_glbl_pram->mflr,
 850                         in_be16(&ugeth->p_rx_glbl_pram->mflr));
 851                 pr_info("minflr          : addr - 0x%08x, val - 0x%04x\n",
 852                         (u32)&ugeth->p_rx_glbl_pram->minflr,
 853                         in_be16(&ugeth->p_rx_glbl_pram->minflr));
 854                 pr_info("maxd1           : addr - 0x%08x, val - 0x%04x\n",
 855                         (u32)&ugeth->p_rx_glbl_pram->maxd1,
 856                         in_be16(&ugeth->p_rx_glbl_pram->maxd1));
 857                 pr_info("maxd2           : addr - 0x%08x, val - 0x%04x\n",
 858                         (u32)&ugeth->p_rx_glbl_pram->maxd2,
 859                         in_be16(&ugeth->p_rx_glbl_pram->maxd2));
 860                 pr_info("ecamptr         : addr - 0x%08x, val - 0x%08x\n",
 861                         (u32)&ugeth->p_rx_glbl_pram->ecamptr,
 862                         in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
 863                 pr_info("l2qt            : addr - 0x%08x, val - 0x%08x\n",
 864                         (u32)&ugeth->p_rx_glbl_pram->l2qt,
 865                         in_be32(&ugeth->p_rx_glbl_pram->l2qt));
 866                 pr_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x\n",
 867                         (u32)&ugeth->p_rx_glbl_pram->l3qt[0],
 868                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
 869                 pr_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x\n",
 870                         (u32)&ugeth->p_rx_glbl_pram->l3qt[1],
 871                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
 872                 pr_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x\n",
 873                         (u32)&ugeth->p_rx_glbl_pram->l3qt[2],
 874                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
 875                 pr_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x\n",
 876                         (u32)&ugeth->p_rx_glbl_pram->l3qt[3],
 877                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
 878                 pr_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x\n",
 879                         (u32)&ugeth->p_rx_glbl_pram->l3qt[4],
 880                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
 881                 pr_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x\n",
 882                         (u32)&ugeth->p_rx_glbl_pram->l3qt[5],
 883                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
 884                 pr_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x\n",
 885                         (u32)&ugeth->p_rx_glbl_pram->l3qt[6],
 886                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
 887                 pr_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x\n",
 888                         (u32)&ugeth->p_rx_glbl_pram->l3qt[7],
 889                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
 890                 pr_info("vlantype        : addr - 0x%08x, val - 0x%04x\n",
 891                         (u32)&ugeth->p_rx_glbl_pram->vlantype,
 892                         in_be16(&ugeth->p_rx_glbl_pram->vlantype));
 893                 pr_info("vlantci         : addr - 0x%08x, val - 0x%04x\n",
 894                         (u32)&ugeth->p_rx_glbl_pram->vlantci,
 895                         in_be16(&ugeth->p_rx_glbl_pram->vlantci));
 896                 for (i = 0; i < 64; i++)
 897                         pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
 898                                 i,
 899                                 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
 900                                 ugeth->p_rx_glbl_pram->addressfiltering[i]);
 901                 pr_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x\n",
 902                         (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
 903                         in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
 904         }
 905         if (ugeth->p_send_q_mem_reg) {
 906                 pr_info("Send Q memory registers:\n");
 907                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
 908                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 909                         pr_info("SQQD[%d]:\n", i);
 910                         pr_info("Base address: 0x%08x\n",
 911                                 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
 912                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
 913                                  sizeof(struct ucc_geth_send_queue_qd));
 914                 }
 915         }
 916         if (ugeth->p_scheduler) {
 917                 pr_info("Scheduler:\n");
 918                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
 919                 mem_disp((u8 *) ugeth->p_scheduler,
 920                          sizeof(*ugeth->p_scheduler));
 921         }
 922         if (ugeth->p_tx_fw_statistics_pram) {
 923                 pr_info("TX FW statistics pram:\n");
 924                 pr_info("Base address: 0x%08x\n",
 925                         (u32)ugeth->p_tx_fw_statistics_pram);
 926                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
 927                          sizeof(*ugeth->p_tx_fw_statistics_pram));
 928         }
 929         if (ugeth->p_rx_fw_statistics_pram) {
 930                 pr_info("RX FW statistics pram:\n");
 931                 pr_info("Base address: 0x%08x\n",
 932                         (u32)ugeth->p_rx_fw_statistics_pram);
 933                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
 934                          sizeof(*ugeth->p_rx_fw_statistics_pram));
 935         }
 936         if (ugeth->p_rx_irq_coalescing_tbl) {
 937                 pr_info("RX IRQ coalescing tables:\n");
 938                 pr_info("Base address: 0x%08x\n",
 939                         (u32)ugeth->p_rx_irq_coalescing_tbl);
 940                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 941                         pr_info("RX IRQ coalescing table entry[%d]:\n", i);
 942                         pr_info("Base address: 0x%08x\n",
 943                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 944                                 coalescingentry[i]);
 945                         pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
 946                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 947                                 coalescingentry[i].interruptcoalescingmaxvalue,
 948                                 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 949                                         coalescingentry[i].
 950                                         interruptcoalescingmaxvalue));
 951                         pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
 952                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 953                                 coalescingentry[i].interruptcoalescingcounter,
 954                                 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 955                                         coalescingentry[i].
 956                                         interruptcoalescingcounter));
 957                 }
 958         }
 959         if (ugeth->p_rx_bd_qs_tbl) {
 960                 pr_info("RX BD QS tables:\n");
 961                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
 962                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 963                         pr_info("RX BD QS table[%d]:\n", i);
 964                         pr_info("Base address: 0x%08x\n",
 965                                 (u32)&ugeth->p_rx_bd_qs_tbl[i]);
 966                         pr_info("bdbaseptr        : addr - 0x%08x, val - 0x%08x\n",
 967                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
 968                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
 969                         pr_info("bdptr            : addr - 0x%08x, val - 0x%08x\n",
 970                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
 971                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
 972                         pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
 973                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
 974                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
 975                                         externalbdbaseptr));
 976                         pr_info("externalbdptr    : addr - 0x%08x, val - 0x%08x\n",
 977                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
 978                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
 979                         pr_info("ucode RX Prefetched BDs:\n");
 980                         pr_info("Base address: 0x%08x\n",
 981                                 (u32)qe_muram_addr(in_be32
 982                                                    (&ugeth->p_rx_bd_qs_tbl[i].
 983                                                     bdbaseptr)));
 984                         mem_disp((u8 *)
 985                                  qe_muram_addr(in_be32
 986                                                (&ugeth->p_rx_bd_qs_tbl[i].
 987                                                 bdbaseptr)),
 988                                  sizeof(struct ucc_geth_rx_prefetched_bds));
 989                 }
 990         }
 991         if (ugeth->p_init_enet_param_shadow) {
 992                 int size;
 993                 pr_info("Init enet param shadow:\n");
 994                 pr_info("Base address: 0x%08x\n",
 995                         (u32) ugeth->p_init_enet_param_shadow);
 996                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
 997                          sizeof(*ugeth->p_init_enet_param_shadow));
 998
 999                 size = sizeof(struct ucc_geth_thread_rx_pram);
1000                 if (ugeth->ug_info->rxExtendedFiltering) {
1001                         size +=
1002                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1003                         if (ugeth->ug_info->largestexternallookupkeysize ==
1004                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1005                                 size +=
1006                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1007                         if (ugeth->ug_info->largestexternallookupkeysize ==
1008                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1009                                 size +=
1010                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1011                 }
1012
1013                 dump_init_enet_entries(ugeth,
1014                                        &(ugeth->p_init_enet_param_shadow->
1015                                          txthread[0]),
1016                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1017                                        sizeof(struct ucc_geth_thread_tx_pram),
1018                                        ugeth->ug_info->riscTx, 0);
1019                 dump_init_enet_entries(ugeth,
1020                                        &(ugeth->p_init_enet_param_shadow->
1021                                          rxthread[0]),
1022                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1023                                        ugeth->ug_info->riscRx, 1);
1024         }
1025 }
1026 #endif /* DEBUG */
1027
1028 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1029                                   u32 __iomem *maccfg1_register,
1030                                   u32 __iomem *maccfg2_register)
1031 {
1032         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1033         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1034         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1035 }
1036
1037 static int init_half_duplex_params(int alt_beb,
1038                                    int back_pressure_no_backoff,
1039                                    int no_backoff,
1040                                    int excess_defer,
1041                                    u8 alt_beb_truncation,
1042                                    u8 max_retransmissions,
1043                                    u8 collision_window,
1044                                    u32 __iomem *hafdup_register)
1045 {
1046         u32 value = 0;
1047
1048         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1049             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1050             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1051                 return -EINVAL;
1052
1053         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1054
1055         if (alt_beb)
1056                 value |= HALFDUP_ALT_BEB;
1057         if (back_pressure_no_backoff)
1058                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1059         if (no_backoff)
1060                 value |= HALFDUP_NO_BACKOFF;
1061         if (excess_defer)
1062                 value |= HALFDUP_EXCESSIVE_DEFER;
1063
1064         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1065
1066         value |= collision_window;
1067
1068         out_be32(hafdup_register, value);
1069         return 0;
1070 }
1071
1072 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1073                                        u8 non_btb_ipg,
1074                                        u8 min_ifg,
1075                                        u8 btb_ipg,
1076                                        u32 __iomem *ipgifg_register)
1077 {
1078         u32 value = 0;
1079
1080         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1081         IPG part 2 */
1082         if (non_btb_cs_ipg > non_btb_ipg)
1083                 return -EINVAL;
1084
1085         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1086             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1087             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1088             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1089                 return -EINVAL;
1090
1091         value |=
1092             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1093              IPGIFG_NBTB_CS_IPG_MASK);
1094         value |=
1095             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1096              IPGIFG_NBTB_IPG_MASK);
1097         value |=
1098             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1099              IPGIFG_MIN_IFG_MASK);
1100         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1101
1102         out_be32(ipgifg_register, value);
1103         return 0;
1104 }
1105
1106 int init_flow_control_params(u32 automatic_flow_control_mode,
1107                                     int rx_flow_control_enable,
1108                                     int tx_flow_control_enable,
1109                                     u16 pause_period,
1110                                     u16 extension_field,
1111                                     u32 __iomem *upsmr_register,
1112                                     u32 __iomem *uempr_register,
1113                                     u32 __iomem *maccfg1_register)
1114 {
1115         u32 value = 0;
1116
1117         /* Set UEMPR register */
1118         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1119         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1120         out_be32(uempr_register, value);
1121
1122         /* Set UPSMR register */
1123         setbits32(upsmr_register, automatic_flow_control_mode);
1124
1125         value = in_be32(maccfg1_register);
1126         if (rx_flow_control_enable)
1127                 value |= MACCFG1_FLOW_RX;
1128         if (tx_flow_control_enable)
1129                 value |= MACCFG1_FLOW_TX;
1130         out_be32(maccfg1_register, value);
1131
1132         return 0;
1133 }
1134
1135 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1136                                              int auto_zero_hardware_statistics,
1137                                              u32 __iomem *upsmr_register,
1138                                              u16 __iomem *uescr_register)
1139 {
1140         u16 uescr_value = 0;
1141
1142         /* Enable hardware statistics gathering if requested */
1143         if (enable_hardware_statistics)
1144                 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1145
1146         /* Clear hardware statistics counters */
1147         uescr_value = in_be16(uescr_register);
1148         uescr_value |= UESCR_CLRCNT;
1149         /* Automatically zero hardware statistics counters on read,
1150         if requested */
1151         if (auto_zero_hardware_statistics)
1152                 uescr_value |= UESCR_AUTOZ;
1153         out_be16(uescr_register, uescr_value);
1154
1155         return 0;
1156 }
1157
1158 static int init_firmware_statistics_gathering_mode(int
1159                 enable_tx_firmware_statistics,
1160                 int enable_rx_firmware_statistics,
1161                 u32 __iomem *tx_rmon_base_ptr,
1162                 u32 tx_firmware_statistics_structure_address,
1163                 u32 __iomem *rx_rmon_base_ptr,
1164                 u32 rx_firmware_statistics_structure_address,
1165                 u16 __iomem *temoder_register,
1166                 u32 __iomem *remoder_register)
1167 {
1168         /* Note: this function does not check if */
1169         /* the parameters it receives are NULL   */
1170
1171         if (enable_tx_firmware_statistics) {
1172                 out_be32(tx_rmon_base_ptr,
1173                          tx_firmware_statistics_structure_address);
1174                 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1175         }
1176
1177         if (enable_rx_firmware_statistics) {
1178                 out_be32(rx_rmon_base_ptr,
1179                          rx_firmware_statistics_structure_address);
1180                 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1181         }
1182
1183         return 0;
1184 }
1185
1186 static int init_mac_station_addr_regs(u8 address_byte_0,
1187                                       u8 address_byte_1,
1188                                       u8 address_byte_2,
1189                                       u8 address_byte_3,
1190                                       u8 address_byte_4,
1191                                       u8 address_byte_5,
1192                                       u32 __iomem *macstnaddr1_register,
1193                                       u32 __iomem *macstnaddr2_register)
1194 {
1195         u32 value = 0;
1196
1197         /* Example: for a station address of 0x12345678ABCD, */
1198         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1199
1200         /* MACSTNADDR1 Register: */
1201
1202         /* 0                      7   8                      15  */
1203         /* station address byte 5     station address byte 4     */
1204         /* 16                     23  24                     31  */
1205         /* station address byte 3     station address byte 2     */
1206         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1207         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1208         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1209         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1210
1211         out_be32(macstnaddr1_register, value);
1212
1213         /* MACSTNADDR2 Register: */
1214
1215         /* 0                      7   8                      15  */
1216         /* station address byte 1     station address byte 0     */
1217         /* 16                     23  24                     31  */
1218         /*         reserved                   reserved           */
1219         value = 0;
1220         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1221         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1222
1223         out_be32(macstnaddr2_register, value);
1224
1225         return 0;
1226 }
1227
1228 static int init_check_frame_length_mode(int length_check,
1229                                         u32 __iomem *maccfg2_register)
1230 {
1231         u32 value = 0;
1232
1233         value = in_be32(maccfg2_register);
1234
1235         if (length_check)
1236                 value |= MACCFG2_LC;
1237         else
1238                 value &= ~MACCFG2_LC;
1239
1240         out_be32(maccfg2_register, value);
1241         return 0;
1242 }
1243
1244 static int init_preamble_length(u8 preamble_length,
1245                                 u32 __iomem *maccfg2_register)
1246 {
1247         if ((preamble_length < 3) || (preamble_length > 7))
1248                 return -EINVAL;
1249
1250         clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1251                         preamble_length << MACCFG2_PREL_SHIFT);
1252
1253         return 0;
1254 }
1255
1256 static int init_rx_parameters(int reject_broadcast,
1257                               int receive_short_frames,
1258                               int promiscuous, u32 __iomem *upsmr_register)
1259 {
1260         u32 value = 0;
1261
1262         value = in_be32(upsmr_register);
1263
1264         if (reject_broadcast)
1265                 value |= UCC_GETH_UPSMR_BRO;
1266         else
1267                 value &= ~UCC_GETH_UPSMR_BRO;
1268
1269         if (receive_short_frames)
1270                 value |= UCC_GETH_UPSMR_RSH;
1271         else
1272                 value &= ~UCC_GETH_UPSMR_RSH;
1273
1274         if (promiscuous)
1275                 value |= UCC_GETH_UPSMR_PRO;
1276         else
1277                 value &= ~UCC_GETH_UPSMR_PRO;
1278
1279         out_be32(upsmr_register, value);
1280
1281         return 0;
1282 }
1283
1284 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1285                                 u16 __iomem *mrblr_register)
1286 {
1287         /* max_rx_buf_len value must be a multiple of 128 */
1288         if ((max_rx_buf_len == 0) ||
1289             (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1290                 return -EINVAL;
1291
1292         out_be16(mrblr_register, max_rx_buf_len);
1293         return 0;
1294 }
1295
1296 static int init_min_frame_len(u16 min_frame_length,
1297                               u16 __iomem *minflr_register,
1298                               u16 __iomem *mrblr_register)
1299 {
1300         u16 mrblr_value = 0;
1301
1302         mrblr_value = in_be16(mrblr_register);
1303         if (min_frame_length >= (mrblr_value - 4))
1304                 return -EINVAL;
1305
1306         out_be16(minflr_register, min_frame_length);
1307         return 0;
1308 }
1309
1310 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1311 {
1312         struct ucc_geth_info *ug_info;
1313         struct ucc_geth __iomem *ug_regs;
1314         struct ucc_fast __iomem *uf_regs;
1315         int ret_val;
1316         u32 upsmr, maccfg2;
1317         u16 value;
1318
1319         ugeth_vdbg("%s: IN", __func__);
1320
1321         ug_info = ugeth->ug_info;
1322         ug_regs = ugeth->ug_regs;
1323         uf_regs = ugeth->uccf->uf_regs;
1324
1325         /*                    Set MACCFG2                    */
1326         maccfg2 = in_be32(&ug_regs->maccfg2);
1327         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1328         if ((ugeth->max_speed == SPEED_10) ||
1329             (ugeth->max_speed == SPEED_100))
1330                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1331         else if (ugeth->max_speed == SPEED_1000)
1332                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1333         maccfg2 |= ug_info->padAndCrc;
1334         out_be32(&ug_regs->maccfg2, maccfg2);
1335
1336         /*                    Set UPSMR                      */
1337         upsmr = in_be32(&uf_regs->upsmr);
1338         upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1339                    UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1340         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1341             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1342             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1343             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1344             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1345             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1346                 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1347                         upsmr |= UCC_GETH_UPSMR_RPM;
1348                 switch (ugeth->max_speed) {
1349                 case SPEED_10:
1350                         upsmr |= UCC_GETH_UPSMR_R10M;
1351                         fallthrough;
1352                 case SPEED_100:
1353                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1354                                 upsmr |= UCC_GETH_UPSMR_RMM;
1355                 }
1356         }
1357         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1358             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1359                 upsmr |= UCC_GETH_UPSMR_TBIM;
1360         }
1361         if (ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)
1362                 upsmr |= UCC_GETH_UPSMR_SGMM;
1363
1364         out_be32(&uf_regs->upsmr, upsmr);
1365
1366         /* Disable autonegotiation in tbi mode, because by default it
1367         comes up in autonegotiation mode. */
1368         /* Note that this depends on proper setting in utbipar register. */
1369         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1370             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1371                 struct ucc_geth_info *ug_info = ugeth->ug_info;
1372                 struct phy_device *tbiphy;
1373
1374                 if (!ug_info->tbi_node)
1375                         pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
1376
1377                 tbiphy = of_phy_find_device(ug_info->tbi_node);
1378                 if (!tbiphy)
1379                         pr_warn("Could not get TBI device\n");
1380
1381                 value = phy_read(tbiphy, ENET_TBI_MII_CR);
1382                 value &= ~0x1000;       /* Turn off autonegotiation */
1383                 phy_write(tbiphy, ENET_TBI_MII_CR, value);
1384
1385                 put_device(&tbiphy->mdio.dev);
1386         }
1387
1388         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1389
1390         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1391         if (ret_val != 0) {
1392                 if (netif_msg_probe(ugeth))
1393                         pr_err("Preamble length must be between 3 and 7 inclusive\n");
1394                 return ret_val;
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1401 {
1402         struct ucc_fast_private *uccf;
1403         u32 cecr_subblock;
1404         u32 temp;
1405         int i = 10;
1406
1407         uccf = ugeth->uccf;
1408
1409         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1410         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1411         out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1412
1413         /* Issue host command */
1414         cecr_subblock =
1415             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1416         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1417                      QE_CR_PROTOCOL_ETHERNET, 0);
1418
1419         /* Wait for command to complete */
1420         do {
1421                 msleep(10);
1422                 temp = in_be32(uccf->p_ucce);
1423         } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1424
1425         uccf->stopped_tx = 1;
1426
1427         return 0;
1428 }
1429
1430 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1431 {
1432         struct ucc_fast_private *uccf;
1433         u32 cecr_subblock;
1434         u8 temp;
1435         int i = 10;
1436
1437         uccf = ugeth->uccf;
1438
1439         /* Clear acknowledge bit */
1440         temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1441         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1442         out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1443
1444         /* Keep issuing command and checking acknowledge bit until
1445         it is asserted, according to spec */
1446         do {
1447                 /* Issue host command */
1448                 cecr_subblock =
1449                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1450                                                 ucc_num);
1451                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1452                              QE_CR_PROTOCOL_ETHERNET, 0);
1453                 msleep(10);
1454                 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1455         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1456
1457         uccf->stopped_rx = 1;
1458
1459         return 0;
1460 }
1461
1462 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1463 {
1464         struct ucc_fast_private *uccf;
1465         u32 cecr_subblock;
1466
1467         uccf = ugeth->uccf;
1468
1469         cecr_subblock =
1470             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1471         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1472         uccf->stopped_tx = 0;
1473
1474         return 0;
1475 }
1476
1477 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1478 {
1479         struct ucc_fast_private *uccf;
1480         u32 cecr_subblock;
1481
1482         uccf = ugeth->uccf;
1483
1484         cecr_subblock =
1485             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1486         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1487                      0);
1488         uccf->stopped_rx = 0;
1489
1490         return 0;
1491 }
1492
1493 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1494 {
1495         struct ucc_fast_private *uccf;
1496         int enabled_tx, enabled_rx;
1497
1498         uccf = ugeth->uccf;
1499
1500         /* check if the UCC number is in range. */
1501         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1502                 if (netif_msg_probe(ugeth))
1503                         pr_err("ucc_num out of range\n");
1504                 return -EINVAL;
1505         }
1506
1507         enabled_tx = uccf->enabled_tx;
1508         enabled_rx = uccf->enabled_rx;
1509
1510         /* Get Tx and Rx going again, in case this channel was actively
1511         disabled. */
1512         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1513                 ugeth_restart_tx(ugeth);
1514         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1515                 ugeth_restart_rx(ugeth);
1516
1517         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1518
1519         return 0;
1520
1521 }
1522
1523 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1524 {
1525         struct ucc_fast_private *uccf;
1526
1527         uccf = ugeth->uccf;
1528
1529         /* check if the UCC number is in range. */
1530         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1531                 if (netif_msg_probe(ugeth))
1532                         pr_err("ucc_num out of range\n");
1533                 return -EINVAL;
1534         }
1535
1536         /* Stop any transmissions */
1537         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1538                 ugeth_graceful_stop_tx(ugeth);
1539
1540         /* Stop any receptions */
1541         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1542                 ugeth_graceful_stop_rx(ugeth);
1543
1544         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1545
1546         return 0;
1547 }
1548
1549 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1550 {
1551         /* Prevent any further xmits */
1552         netif_tx_stop_all_queues(ugeth->ndev);
1553
1554         /* Disable the interrupt to avoid NAPI rescheduling. */
1555         disable_irq(ugeth->ug_info->uf_info.irq);
1556
1557         /* Stop NAPI, and possibly wait for its completion. */
1558         napi_disable(&ugeth->napi);
1559 }
1560
1561 static void ugeth_activate(struct ucc_geth_private *ugeth)
1562 {
1563         napi_enable(&ugeth->napi);
1564         enable_irq(ugeth->ug_info->uf_info.irq);
1565
1566         /* allow to xmit again  */
1567         netif_tx_wake_all_queues(ugeth->ndev);
1568         __netdev_watchdog_up(ugeth->ndev);
1569 }
1570
1571 /* Called every time the controller might need to be made
1572  * aware of new link state.  The PHY code conveys this
1573  * information through variables in the ugeth structure, and this
1574  * function converts those variables into the appropriate
1575  * register values, and can bring down the device if needed.
1576  */
1577
1578 static void adjust_link(struct net_device *dev)
1579 {
1580         struct ucc_geth_private *ugeth = netdev_priv(dev);
1581         struct ucc_geth __iomem *ug_regs;
1582         struct ucc_fast __iomem *uf_regs;
1583         struct phy_device *phydev = ugeth->phydev;
1584         int new_state = 0;
1585
1586         ug_regs = ugeth->ug_regs;
1587         uf_regs = ugeth->uccf->uf_regs;
1588
1589         if (phydev->link) {
1590                 u32 tempval = in_be32(&ug_regs->maccfg2);
1591                 u32 upsmr = in_be32(&uf_regs->upsmr);
1592                 /* Now we make sure that we can be in full duplex mode.
1593                  * If not, we operate in half-duplex mode. */
1594                 if (phydev->duplex != ugeth->oldduplex) {
1595                         new_state = 1;
1596                         if (!(phydev->duplex))
1597                                 tempval &= ~(MACCFG2_FDX);
1598                         else
1599                                 tempval |= MACCFG2_FDX;
1600                         ugeth->oldduplex = phydev->duplex;
1601                 }
1602
1603                 if (phydev->speed != ugeth->oldspeed) {
1604                         new_state = 1;
1605                         switch (phydev->speed) {
1606                         case SPEED_1000:
1607                                 tempval = ((tempval &
1608                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1609                                             MACCFG2_INTERFACE_MODE_BYTE);
1610                                 break;
1611                         case SPEED_100:
1612                         case SPEED_10:
1613                                 tempval = ((tempval &
1614                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1615                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1616                                 /* if reduced mode, re-set UPSMR.R10M */
1617                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1618                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1619                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1620                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1621                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1622                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1623                                         if (phydev->speed == SPEED_10)
1624                                                 upsmr |= UCC_GETH_UPSMR_R10M;
1625                                         else
1626                                                 upsmr &= ~UCC_GETH_UPSMR_R10M;
1627                                 }
1628                                 break;
1629                         default:
1630                                 if (netif_msg_link(ugeth))
1631                                         pr_warn(
1632                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1633                                                 dev->name, phydev->speed);
1634                                 break;
1635                         }
1636                         ugeth->oldspeed = phydev->speed;
1637                 }
1638
1639                 if (!ugeth->oldlink) {
1640                         new_state = 1;
1641                         ugeth->oldlink = 1;
1642                 }
1643
1644                 if (new_state) {
1645                         /*
1646                          * To change the MAC configuration we need to disable
1647                          * the controller. To do so, we have to either grab
1648                          * ugeth->lock, which is a bad idea since 'graceful
1649                          * stop' commands might take quite a while, or we can
1650                          * quiesce driver's activity.
1651                          */
1652                         ugeth_quiesce(ugeth);
1653                         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1654
1655                         out_be32(&ug_regs->maccfg2, tempval);
1656                         out_be32(&uf_regs->upsmr, upsmr);
1657
1658                         ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1659                         ugeth_activate(ugeth);
1660                 }
1661         } else if (ugeth->oldlink) {
1662                         new_state = 1;
1663                         ugeth->oldlink = 0;
1664                         ugeth->oldspeed = 0;
1665                         ugeth->oldduplex = -1;
1666         }
1667
1668         if (new_state && netif_msg_link(ugeth))
1669                 phy_print_status(phydev);
1670 }
1671
1672 /* Initialize TBI PHY interface for communicating with the
1673  * SERDES lynx PHY on the chip.  We communicate with this PHY
1674  * through the MDIO bus on each controller, treating it as a
1675  * "normal" PHY at the address found in the UTBIPA register.  We assume
1676  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1677  * it to a value that doesn't conflict with other PHYs on the bus, or the
1678  * value doesn't matter, as there are no other PHYs on the bus.
1679  */
1680 static void uec_configure_serdes(struct net_device *dev)
1681 {
1682         struct ucc_geth_private *ugeth = netdev_priv(dev);
1683         struct ucc_geth_info *ug_info = ugeth->ug_info;
1684         struct phy_device *tbiphy;
1685
1686         if (!ug_info->tbi_node) {
1687                 dev_warn(&dev->dev, "SGMII mode requires that the device "
1688                         "tree specify a tbi-handle\n");
1689                 return;
1690         }
1691
1692         tbiphy = of_phy_find_device(ug_info->tbi_node);
1693         if (!tbiphy) {
1694                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1695                 return;
1696         }
1697
1698         /*
1699          * If the link is already up, we must already be ok, and don't need to
1700          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1701          * everything for us?  Resetting it takes the link down and requires
1702          * several seconds for it to come back.
1703          */
1704         if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) {
1705                 put_device(&tbiphy->mdio.dev);
1706                 return;
1707         }
1708
1709         /* Single clk mode, mii mode off(for serdes communication) */
1710         phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1711
1712         phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1713
1714         phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1715
1716         put_device(&tbiphy->mdio.dev);
1717 }
1718
1719 /* Configure the PHY for dev.
1720  * returns 0 if success.  -1 if failure
1721  */
1722 static int init_phy(struct net_device *dev)
1723 {
1724         struct ucc_geth_private *priv = netdev_priv(dev);
1725         struct ucc_geth_info *ug_info = priv->ug_info;
1726         struct phy_device *phydev;
1727
1728         priv->oldlink = 0;
1729         priv->oldspeed = 0;
1730         priv->oldduplex = -1;
1731
1732         phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1733                                 priv->phy_interface);
1734         if (!phydev) {
1735                 dev_err(&dev->dev, "Could not attach to PHY\n");
1736                 return -ENODEV;
1737         }
1738
1739         if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1740                 uec_configure_serdes(dev);
1741
1742         phy_set_max_speed(phydev, priv->max_speed);
1743
1744         priv->phydev = phydev;
1745
1746         return 0;
1747 }
1748
1749 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1750 {
1751 #ifdef DEBUG
1752         ucc_fast_dump_regs(ugeth->uccf);
1753         dump_regs(ugeth);
1754         dump_bds(ugeth);
1755 #endif
1756 }
1757
1758 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1759                                                        ugeth,
1760                                                        enum enet_addr_type
1761                                                        enet_addr_type)
1762 {
1763         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1764         struct ucc_fast_private *uccf;
1765         enum comm_dir comm_dir;
1766         struct list_head *p_lh;
1767         u16 i, num;
1768         u32 __iomem *addr_h;
1769         u32 __iomem *addr_l;
1770         u8 *p_counter;
1771
1772         uccf = ugeth->uccf;
1773
1774         p_82xx_addr_filt =
1775             (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1776             ugeth->p_rx_glbl_pram->addressfiltering;
1777
1778         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1779                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1780                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1781                 p_lh = &ugeth->group_hash_q;
1782                 p_counter = &(ugeth->numGroupAddrInHash);
1783         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1784                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1785                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1786                 p_lh = &ugeth->ind_hash_q;
1787                 p_counter = &(ugeth->numIndAddrInHash);
1788         } else
1789                 return -EINVAL;
1790
1791         comm_dir = 0;
1792         if (uccf->enabled_tx)
1793                 comm_dir |= COMM_DIR_TX;
1794         if (uccf->enabled_rx)
1795                 comm_dir |= COMM_DIR_RX;
1796         if (comm_dir)
1797                 ugeth_disable(ugeth, comm_dir);
1798
1799         /* Clear the hash table. */
1800         out_be32(addr_h, 0x00000000);
1801         out_be32(addr_l, 0x00000000);
1802
1803         if (!p_lh)
1804                 return 0;
1805
1806         num = *p_counter;
1807
1808         /* Delete all remaining CQ elements */
1809         for (i = 0; i < num; i++)
1810                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1811
1812         *p_counter = 0;
1813
1814         if (comm_dir)
1815                 ugeth_enable(ugeth, comm_dir);
1816
1817         return 0;
1818 }
1819
1820 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1821                                                     u8 paddr_num)
1822 {
1823         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1824         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1825 }
1826
1827 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1828 {
1829         struct ucc_geth_info *ug_info;
1830         struct ucc_fast_info *uf_info;
1831         u16 i, j;
1832         u8 __iomem *bd;
1833
1834
1835         ug_info = ugeth->ug_info;
1836         uf_info = &ug_info->uf_info;
1837
1838         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1839                 if (ugeth->p_rx_bd_ring[i]) {
1840                         /* Return existing data buffers in ring */
1841                         bd = ugeth->p_rx_bd_ring[i];
1842                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1843                                 if (ugeth->rx_skbuff[i][j]) {
1844                                         dma_unmap_single(ugeth->dev,
1845                                                 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1846                                                 ugeth->ug_info->
1847                                                 uf_info.max_rx_buf_length +
1848                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1849                                                 DMA_FROM_DEVICE);
1850                                         dev_kfree_skb_any(
1851                                                 ugeth->rx_skbuff[i][j]);
1852                                         ugeth->rx_skbuff[i][j] = NULL;
1853                                 }
1854                                 bd += sizeof(struct qe_bd);
1855                         }
1856
1857                         kfree(ugeth->rx_skbuff[i]);
1858
1859                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1860                             MEM_PART_SYSTEM)
1861                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1862                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1863                                  MEM_PART_MURAM)
1864                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1865                         ugeth->p_rx_bd_ring[i] = NULL;
1866                 }
1867         }
1868
1869 }
1870
1871 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
1872 {
1873         struct ucc_geth_info *ug_info;
1874         struct ucc_fast_info *uf_info;
1875         u16 i, j;
1876         u8 __iomem *bd;
1877
1878         netdev_reset_queue(ugeth->ndev);
1879
1880         ug_info = ugeth->ug_info;
1881         uf_info = &ug_info->uf_info;
1882
1883         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1884                 bd = ugeth->p_tx_bd_ring[i];
1885                 if (!bd)
1886                         continue;
1887                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1888                         if (ugeth->tx_skbuff[i][j]) {
1889                                 dma_unmap_single(ugeth->dev,
1890                                                  in_be32(&((struct qe_bd __iomem *)bd)->buf),
1891                                                  (in_be32((u32 __iomem *)bd) &
1892                                                   BD_LENGTH_MASK),
1893                                                  DMA_TO_DEVICE);
1894                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1895                                 ugeth->tx_skbuff[i][j] = NULL;
1896                         }
1897                 }
1898
1899                 kfree(ugeth->tx_skbuff[i]);
1900
1901                 if (ugeth->p_tx_bd_ring[i]) {
1902                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1903                             MEM_PART_SYSTEM)
1904                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1905                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1906                                  MEM_PART_MURAM)
1907                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1908                         ugeth->p_tx_bd_ring[i] = NULL;
1909                 }
1910         }
1911
1912 }
1913
1914 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1915 {
1916         if (!ugeth)
1917                 return;
1918
1919         if (ugeth->uccf) {
1920                 ucc_fast_free(ugeth->uccf);
1921                 ugeth->uccf = NULL;
1922         }
1923
1924         qe_muram_free_addr(ugeth->p_thread_data_tx);
1925         ugeth->p_thread_data_tx = NULL;
1926
1927         qe_muram_free_addr(ugeth->p_thread_data_rx);
1928         ugeth->p_thread_data_rx = NULL;
1929
1930         qe_muram_free_addr(ugeth->p_exf_glbl_param);
1931         ugeth->p_exf_glbl_param = NULL;
1932
1933         qe_muram_free_addr(ugeth->p_rx_glbl_pram);
1934         ugeth->p_rx_glbl_pram = NULL;
1935
1936         qe_muram_free_addr(ugeth->p_tx_glbl_pram);
1937         ugeth->p_tx_glbl_pram = NULL;
1938
1939         qe_muram_free_addr(ugeth->p_send_q_mem_reg);
1940         ugeth->p_send_q_mem_reg = NULL;
1941
1942         qe_muram_free_addr(ugeth->p_scheduler);
1943         ugeth->p_scheduler = NULL;
1944
1945         qe_muram_free_addr(ugeth->p_tx_fw_statistics_pram);
1946         ugeth->p_tx_fw_statistics_pram = NULL;
1947
1948         qe_muram_free_addr(ugeth->p_rx_fw_statistics_pram);
1949         ugeth->p_rx_fw_statistics_pram = NULL;
1950
1951         qe_muram_free_addr(ugeth->p_rx_irq_coalescing_tbl);
1952         ugeth->p_rx_irq_coalescing_tbl = NULL;
1953
1954         qe_muram_free_addr(ugeth->p_rx_bd_qs_tbl);
1955         ugeth->p_rx_bd_qs_tbl = NULL;
1956
1957         if (ugeth->p_init_enet_param_shadow) {
1958                 return_init_enet_entries(ugeth,
1959                                          &(ugeth->p_init_enet_param_shadow->
1960                                            rxthread[0]),
1961                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
1962                                          ugeth->ug_info->riscRx, 1);
1963                 return_init_enet_entries(ugeth,
1964                                          &(ugeth->p_init_enet_param_shadow->
1965                                            txthread[0]),
1966                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
1967                                          ugeth->ug_info->riscTx, 0);
1968                 kfree(ugeth->p_init_enet_param_shadow);
1969                 ugeth->p_init_enet_param_shadow = NULL;
1970         }
1971         ucc_geth_free_tx(ugeth);
1972         ucc_geth_free_rx(ugeth);
1973         while (!list_empty(&ugeth->group_hash_q))
1974                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1975                                         (dequeue(&ugeth->group_hash_q)));
1976         while (!list_empty(&ugeth->ind_hash_q))
1977                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1978                                         (dequeue(&ugeth->ind_hash_q)));
1979         if (ugeth->ug_regs) {
1980                 iounmap(ugeth->ug_regs);
1981                 ugeth->ug_regs = NULL;
1982         }
1983 }
1984
1985 static void ucc_geth_set_multi(struct net_device *dev)
1986 {
1987         struct ucc_geth_private *ugeth;
1988         struct netdev_hw_addr *ha;
1989         struct ucc_fast __iomem *uf_regs;
1990         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1991
1992         ugeth = netdev_priv(dev);
1993
1994         uf_regs = ugeth->uccf->uf_regs;
1995
1996         if (dev->flags & IFF_PROMISC) {
1997                 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1998         } else {
1999                 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2000
2001                 p_82xx_addr_filt =
2002                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2003                     p_rx_glbl_pram->addressfiltering;
2004
2005                 if (dev->flags & IFF_ALLMULTI) {
2006                         /* Catch all multicast addresses, so set the
2007                          * filter to all 1's.
2008                          */
2009                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2010                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2011                 } else {
2012                         /* Clear filter and add the addresses in the list.
2013                          */
2014                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2015                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2016
2017                         netdev_for_each_mc_addr(ha, dev) {
2018                                 /* Ask CPM to run CRC and set bit in
2019                                  * filter mask.
2020                                  */
2021                                 hw_add_addr_in_hash(ugeth, ha->addr);
2022                         }
2023                 }
2024         }
2025 }
2026
2027 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2028 {
2029         struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2030         struct phy_device *phydev = ugeth->phydev;
2031
2032         ugeth_vdbg("%s: IN", __func__);
2033
2034         /*
2035          * Tell the kernel the link is down.
2036          * Must be done before disabling the controller
2037          * or deadlock may happen.
2038          */
2039         phy_stop(phydev);
2040
2041         /* Disable the controller */
2042         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2043
2044         /* Mask all interrupts */
2045         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2046
2047         /* Clear all interrupts */
2048         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2049
2050         /* Disable Rx and Tx */
2051         clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2052
2053         ucc_geth_memclean(ugeth);
2054 }
2055
2056 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2057 {
2058         struct ucc_geth_info *ug_info;
2059         struct ucc_fast_info *uf_info;
2060         int i;
2061
2062         ug_info = ugeth->ug_info;
2063         uf_info = &ug_info->uf_info;
2064
2065         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2066               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2067                 if (netif_msg_probe(ugeth))
2068                         pr_err("Bad memory partition value\n");
2069                 return -EINVAL;
2070         }
2071
2072         /* Rx BD lengths */
2073         for (i = 0; i < ug_info->numQueuesRx; i++) {
2074                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2075                     (ug_info->bdRingLenRx[i] %
2076                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2077                         if (netif_msg_probe(ugeth))
2078                                 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
2079                         return -EINVAL;
2080                 }
2081         }
2082
2083         /* Tx BD lengths */
2084         for (i = 0; i < ug_info->numQueuesTx; i++) {
2085                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2086                         if (netif_msg_probe(ugeth))
2087                                 pr_err("Tx BD ring length must be no smaller than 2\n");
2088                         return -EINVAL;
2089                 }
2090         }
2091
2092         /* mrblr */
2093         if ((uf_info->max_rx_buf_length == 0) ||
2094             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2095                 if (netif_msg_probe(ugeth))
2096                         pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
2097                 return -EINVAL;
2098         }
2099
2100         /* num Tx queues */
2101         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2102                 if (netif_msg_probe(ugeth))
2103                         pr_err("number of tx queues too large\n");
2104                 return -EINVAL;
2105         }
2106
2107         /* num Rx queues */
2108         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2109                 if (netif_msg_probe(ugeth))
2110                         pr_err("number of rx queues too large\n");
2111                 return -EINVAL;
2112         }
2113
2114         /* l2qt */
2115         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2116                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2117                         if (netif_msg_probe(ugeth))
2118                                 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
2119                         return -EINVAL;
2120                 }
2121         }
2122
2123         /* l3qt */
2124         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2125                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2126                         if (netif_msg_probe(ugeth))
2127                                 pr_err("IP priority table entry must not be larger than number of Rx queues\n");
2128                         return -EINVAL;
2129                 }
2130         }
2131
2132         if (ug_info->cam && !ug_info->ecamptr) {
2133                 if (netif_msg_probe(ugeth))
2134                         pr_err("If cam mode is chosen, must supply cam ptr\n");
2135                 return -EINVAL;
2136         }
2137
2138         if ((ug_info->numStationAddresses !=
2139              UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2140             ug_info->rxExtendedFiltering) {
2141                 if (netif_msg_probe(ugeth))
2142                         pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
2143                 return -EINVAL;
2144         }
2145
2146         /* Generate uccm_mask for receive */
2147         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2148         for (i = 0; i < ug_info->numQueuesRx; i++)
2149                 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2150
2151         for (i = 0; i < ug_info->numQueuesTx; i++)
2152                 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2153         /* Initialize the general fast UCC block. */
2154         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2155                 if (netif_msg_probe(ugeth))
2156                         pr_err("Failed to init uccf\n");
2157                 return -ENOMEM;
2158         }
2159
2160         /* read the number of risc engines, update the riscTx and riscRx
2161          * if there are 4 riscs in QE
2162          */
2163         if (qe_get_num_of_risc() == 4) {
2164                 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2165                 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2166         }
2167
2168         ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2169         if (!ugeth->ug_regs) {
2170                 if (netif_msg_probe(ugeth))
2171                         pr_err("Failed to ioremap regs\n");
2172                 return -ENOMEM;
2173         }
2174
2175         return 0;
2176 }
2177
2178 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2179 {
2180         struct ucc_geth_info *ug_info;
2181         struct ucc_fast_info *uf_info;
2182         int length;
2183         u16 i, j;
2184         u8 __iomem *bd;
2185
2186         ug_info = ugeth->ug_info;
2187         uf_info = &ug_info->uf_info;
2188
2189         /* Allocate Tx bds */
2190         for (j = 0; j < ug_info->numQueuesTx; j++) {
2191                 /* Allocate in multiple of
2192                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2193                    according to spec */
2194                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2195                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2196                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2197                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2198                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2199                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2200                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2201                         u32 align = 4;
2202                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2203                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2204                         ugeth->tx_bd_ring_offset[j] =
2205                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2206
2207                         if (ugeth->tx_bd_ring_offset[j] != 0)
2208                                 ugeth->p_tx_bd_ring[j] =
2209                                         (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2210                                         align) & ~(align - 1));
2211                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2212                         ugeth->tx_bd_ring_offset[j] =
2213                             qe_muram_alloc(length,
2214                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2215                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2216                                 ugeth->p_tx_bd_ring[j] =
2217                                     (u8 __iomem *) qe_muram_addr(ugeth->
2218                                                          tx_bd_ring_offset[j]);
2219                 }
2220                 if (!ugeth->p_tx_bd_ring[j]) {
2221                         if (netif_msg_ifup(ugeth))
2222                                 pr_err("Can not allocate memory for Tx bd rings\n");
2223                         return -ENOMEM;
2224                 }
2225                 /* Zero unused end of bd ring, according to spec */
2226                 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2227                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2228                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2229         }
2230
2231         /* Init Tx bds */
2232         for (j = 0; j < ug_info->numQueuesTx; j++) {
2233                 /* Setup the skbuff rings */
2234                 ugeth->tx_skbuff[j] =
2235                         kmalloc_array(ugeth->ug_info->bdRingLenTx[j],
2236                                       sizeof(struct sk_buff *), GFP_KERNEL);
2237
2238                 if (ugeth->tx_skbuff[j] == NULL) {
2239                         if (netif_msg_ifup(ugeth))
2240                                 pr_err("Could not allocate tx_skbuff\n");
2241                         return -ENOMEM;
2242                 }
2243
2244                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2245                         ugeth->tx_skbuff[j][i] = NULL;
2246
2247                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2248                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2249                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2250                         /* clear bd buffer */
2251                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2252                         /* set bd status and length */
2253                         out_be32((u32 __iomem *)bd, 0);
2254                         bd += sizeof(struct qe_bd);
2255                 }
2256                 bd -= sizeof(struct qe_bd);
2257                 /* set bd status and length */
2258                 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2265 {
2266         struct ucc_geth_info *ug_info;
2267         struct ucc_fast_info *uf_info;
2268         int length;
2269         u16 i, j;
2270         u8 __iomem *bd;
2271
2272         ug_info = ugeth->ug_info;
2273         uf_info = &ug_info->uf_info;
2274
2275         /* Allocate Rx bds */
2276         for (j = 0; j < ug_info->numQueuesRx; j++) {
2277                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2278                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2279                         u32 align = 4;
2280                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2281                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2282                         ugeth->rx_bd_ring_offset[j] =
2283                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2284                         if (ugeth->rx_bd_ring_offset[j] != 0)
2285                                 ugeth->p_rx_bd_ring[j] =
2286                                         (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2287                                         align) & ~(align - 1));
2288                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2289                         ugeth->rx_bd_ring_offset[j] =
2290                             qe_muram_alloc(length,
2291                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2292                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2293                                 ugeth->p_rx_bd_ring[j] =
2294                                     (u8 __iomem *) qe_muram_addr(ugeth->
2295                                                          rx_bd_ring_offset[j]);
2296                 }
2297                 if (!ugeth->p_rx_bd_ring[j]) {
2298                         if (netif_msg_ifup(ugeth))
2299                                 pr_err("Can not allocate memory for Rx bd rings\n");
2300                         return -ENOMEM;
2301                 }
2302         }
2303
2304         /* Init Rx bds */
2305         for (j = 0; j < ug_info->numQueuesRx; j++) {
2306                 /* Setup the skbuff rings */
2307                 ugeth->rx_skbuff[j] =
2308                         kmalloc_array(ugeth->ug_info->bdRingLenRx[j],
2309                                       sizeof(struct sk_buff *), GFP_KERNEL);
2310
2311                 if (ugeth->rx_skbuff[j] == NULL) {
2312                         if (netif_msg_ifup(ugeth))
2313                                 pr_err("Could not allocate rx_skbuff\n");
2314                         return -ENOMEM;
2315                 }
2316
2317                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2318                         ugeth->rx_skbuff[j][i] = NULL;
2319
2320                 ugeth->skb_currx[j] = 0;
2321                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2322                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2323                         /* set bd status and length */
2324                         out_be32((u32 __iomem *)bd, R_I);
2325                         /* clear bd buffer */
2326                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2327                         bd += sizeof(struct qe_bd);
2328                 }
2329                 bd -= sizeof(struct qe_bd);
2330                 /* set bd status and length */
2331                 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2332         }
2333
2334         return 0;
2335 }
2336
2337 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2338 {
2339         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2340         struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2341         struct ucc_fast_private *uccf;
2342         struct ucc_geth_info *ug_info;
2343         struct ucc_fast_info *uf_info;
2344         struct ucc_fast __iomem *uf_regs;
2345         struct ucc_geth __iomem *ug_regs;
2346         int ret_val = -EINVAL;
2347         u32 remoder = UCC_GETH_REMODER_INIT;
2348         u32 init_enet_pram_offset, cecr_subblock, command;
2349         u32 ifstat, i, j, size, l2qt, l3qt;
2350         u16 temoder = UCC_GETH_TEMODER_INIT;
2351         u8 function_code = 0;
2352         u8 __iomem *endOfRing;
2353         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2354
2355         ugeth_vdbg("%s: IN", __func__);
2356         uccf = ugeth->uccf;
2357         ug_info = ugeth->ug_info;
2358         uf_info = &ug_info->uf_info;
2359         uf_regs = uccf->uf_regs;
2360         ug_regs = ugeth->ug_regs;
2361
2362         switch (ug_info->numThreadsRx) {
2363         case UCC_GETH_NUM_OF_THREADS_1:
2364                 numThreadsRxNumerical = 1;
2365                 break;
2366         case UCC_GETH_NUM_OF_THREADS_2:
2367                 numThreadsRxNumerical = 2;
2368                 break;
2369         case UCC_GETH_NUM_OF_THREADS_4:
2370                 numThreadsRxNumerical = 4;
2371                 break;
2372         case UCC_GETH_NUM_OF_THREADS_6:
2373                 numThreadsRxNumerical = 6;
2374                 break;
2375         case UCC_GETH_NUM_OF_THREADS_8:
2376                 numThreadsRxNumerical = 8;
2377                 break;
2378         default:
2379                 if (netif_msg_ifup(ugeth))
2380                         pr_err("Bad number of Rx threads value\n");
2381                 return -EINVAL;
2382         }
2383
2384         switch (ug_info->numThreadsTx) {
2385         case UCC_GETH_NUM_OF_THREADS_1:
2386                 numThreadsTxNumerical = 1;
2387                 break;
2388         case UCC_GETH_NUM_OF_THREADS_2:
2389                 numThreadsTxNumerical = 2;
2390                 break;
2391         case UCC_GETH_NUM_OF_THREADS_4:
2392                 numThreadsTxNumerical = 4;
2393                 break;
2394         case UCC_GETH_NUM_OF_THREADS_6:
2395                 numThreadsTxNumerical = 6;
2396                 break;
2397         case UCC_GETH_NUM_OF_THREADS_8:
2398                 numThreadsTxNumerical = 8;
2399                 break;
2400         default:
2401                 if (netif_msg_ifup(ugeth))
2402                         pr_err("Bad number of Tx threads value\n");
2403                 return -EINVAL;
2404         }
2405
2406         /* Calculate rx_extended_features */
2407         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2408             ug_info->ipAddressAlignment ||
2409             (ug_info->numStationAddresses !=
2410              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2411
2412         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2413                 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2414                 (ug_info->vlanOperationNonTagged !=
2415                  UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2416
2417         init_default_reg_vals(&uf_regs->upsmr,
2418                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2419
2420         /*                    Set UPSMR                      */
2421         /* For more details see the hardware spec.           */
2422         init_rx_parameters(ug_info->bro,
2423                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2424
2425         /* We're going to ignore other registers for now, */
2426         /* except as needed to get up and running         */
2427
2428         /*                    Set MACCFG1                    */
2429         /* For more details see the hardware spec.           */
2430         init_flow_control_params(ug_info->aufc,
2431                                  ug_info->receiveFlowControl,
2432                                  ug_info->transmitFlowControl,
2433                                  ug_info->pausePeriod,
2434                                  ug_info->extensionField,
2435                                  &uf_regs->upsmr,
2436                                  &ug_regs->uempr, &ug_regs->maccfg1);
2437
2438         setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2439
2440         /*                    Set IPGIFG                     */
2441         /* For more details see the hardware spec.           */
2442         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2443                                               ug_info->nonBackToBackIfgPart2,
2444                                               ug_info->
2445                                               miminumInterFrameGapEnforcement,
2446                                               ug_info->backToBackInterFrameGap,
2447                                               &ug_regs->ipgifg);
2448         if (ret_val != 0) {
2449                 if (netif_msg_ifup(ugeth))
2450                         pr_err("IPGIFG initialization parameter too large\n");
2451                 return ret_val;
2452         }
2453
2454         /*                    Set HAFDUP                     */
2455         /* For more details see the hardware spec.           */
2456         ret_val = init_half_duplex_params(ug_info->altBeb,
2457                                           ug_info->backPressureNoBackoff,
2458                                           ug_info->noBackoff,
2459                                           ug_info->excessDefer,
2460                                           ug_info->altBebTruncation,
2461                                           ug_info->maxRetransmission,
2462                                           ug_info->collisionWindow,
2463                                           &ug_regs->hafdup);
2464         if (ret_val != 0) {
2465                 if (netif_msg_ifup(ugeth))
2466                         pr_err("Half Duplex initialization parameter too large\n");
2467                 return ret_val;
2468         }
2469
2470         /*                    Set IFSTAT                     */
2471         /* For more details see the hardware spec.           */
2472         /* Read only - resets upon read                      */
2473         ifstat = in_be32(&ug_regs->ifstat);
2474
2475         /*                    Clear UEMPR                    */
2476         /* For more details see the hardware spec.           */
2477         out_be32(&ug_regs->uempr, 0);
2478
2479         /*                    Set UESCR                      */
2480         /* For more details see the hardware spec.           */
2481         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2482                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2483                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2484
2485         ret_val = ucc_geth_alloc_tx(ugeth);
2486         if (ret_val != 0)
2487                 return ret_val;
2488
2489         ret_val = ucc_geth_alloc_rx(ugeth);
2490         if (ret_val != 0)
2491                 return ret_val;
2492
2493         /*
2494          * Global PRAM
2495          */
2496         /* Tx global PRAM */
2497         /* Allocate global tx parameter RAM page */
2498         ugeth->tx_glbl_pram_offset =
2499             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2500                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2501         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2502                 if (netif_msg_ifup(ugeth))
2503                         pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
2504                 return -ENOMEM;
2505         }
2506         ugeth->p_tx_glbl_pram =
2507             (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2508                                                         tx_glbl_pram_offset);
2509         /* Fill global PRAM */
2510
2511         /* TQPTR */
2512         /* Size varies with number of Tx threads */
2513         ugeth->thread_dat_tx_offset =
2514             qe_muram_alloc(numThreadsTxNumerical *
2515                            sizeof(struct ucc_geth_thread_data_tx) +
2516                            32 * (numThreadsTxNumerical == 1),
2517                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2518         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2519                 if (netif_msg_ifup(ugeth))
2520                         pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
2521                 return -ENOMEM;
2522         }
2523
2524         ugeth->p_thread_data_tx =
2525             (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2526                                                         thread_dat_tx_offset);
2527         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2528
2529         /* vtagtable */
2530         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2531                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2532                          ug_info->vtagtable[i]);
2533
2534         /* iphoffset */
2535         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2536                 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2537                                 ug_info->iphoffset[i]);
2538
2539         /* SQPTR */
2540         /* Size varies with number of Tx queues */
2541         ugeth->send_q_mem_reg_offset =
2542             qe_muram_alloc(ug_info->numQueuesTx *
2543                            sizeof(struct ucc_geth_send_queue_qd),
2544                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2545         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2546                 if (netif_msg_ifup(ugeth))
2547                         pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
2548                 return -ENOMEM;
2549         }
2550
2551         ugeth->p_send_q_mem_reg =
2552             (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2553                         send_q_mem_reg_offset);
2554         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2555
2556         /* Setup the table */
2557         /* Assume BD rings are already established */
2558         for (i = 0; i < ug_info->numQueuesTx; i++) {
2559                 endOfRing =
2560                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2561                                               1) * sizeof(struct qe_bd);
2562                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2563                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2564                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2565                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2566                                  last_bd_completed_address,
2567                                  (u32) virt_to_phys(endOfRing));
2568                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2569                            MEM_PART_MURAM) {
2570                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2571                                  (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
2572                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2573                                  last_bd_completed_address,
2574                                  (u32)qe_muram_dma(endOfRing));
2575                 }
2576         }
2577
2578         /* schedulerbasepointer */
2579
2580         if (ug_info->numQueuesTx > 1) {
2581         /* scheduler exists only if more than 1 tx queue */
2582                 ugeth->scheduler_offset =
2583                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2584                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2585                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2586                         if (netif_msg_ifup(ugeth))
2587                                 pr_err("Can not allocate DPRAM memory for p_scheduler\n");
2588                         return -ENOMEM;
2589                 }
2590
2591                 ugeth->p_scheduler =
2592                     (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2593                                                            scheduler_offset);
2594                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2595                          ugeth->scheduler_offset);
2596
2597                 /* Set values in scheduler */
2598                 out_be32(&ugeth->p_scheduler->mblinterval,
2599                          ug_info->mblinterval);
2600                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2601                          ug_info->nortsrbytetime);
2602                 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2603                 out_8(&ugeth->p_scheduler->strictpriorityq,
2604                                 ug_info->strictpriorityq);
2605                 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2606                 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2607                 for (i = 0; i < NUM_TX_QUEUES; i++)
2608                         out_8(&ugeth->p_scheduler->weightfactor[i],
2609                             ug_info->weightfactor[i]);
2610
2611                 /* Set pointers to cpucount registers in scheduler */
2612                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2613                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2614                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2615                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2616                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2617                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2618                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2619                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2620         }
2621
2622         /* schedulerbasepointer */
2623         /* TxRMON_PTR (statistics) */
2624         if (ug_info->
2625             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2626                 ugeth->tx_fw_statistics_pram_offset =
2627                     qe_muram_alloc(sizeof
2628                                    (struct ucc_geth_tx_firmware_statistics_pram),
2629                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2630                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2631                         if (netif_msg_ifup(ugeth))
2632                                 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
2633                         return -ENOMEM;
2634                 }
2635                 ugeth->p_tx_fw_statistics_pram =
2636                     (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2637                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2638         }
2639
2640         /* temoder */
2641         /* Already has speed set */
2642
2643         if (ug_info->numQueuesTx > 1)
2644                 temoder |= TEMODER_SCHEDULER_ENABLE;
2645         if (ug_info->ipCheckSumGenerate)
2646                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2647         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2648         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2649
2650         /* Function code register value to be used later */
2651         function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2652         /* Required for QE */
2653
2654         /* function code register */
2655         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2656
2657         /* Rx global PRAM */
2658         /* Allocate global rx parameter RAM page */
2659         ugeth->rx_glbl_pram_offset =
2660             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2661                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2662         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2663                 if (netif_msg_ifup(ugeth))
2664                         pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
2665                 return -ENOMEM;
2666         }
2667         ugeth->p_rx_glbl_pram =
2668             (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2669                                                         rx_glbl_pram_offset);
2670         /* Fill global PRAM */
2671
2672         /* RQPTR */
2673         /* Size varies with number of Rx threads */
2674         ugeth->thread_dat_rx_offset =
2675             qe_muram_alloc(numThreadsRxNumerical *
2676                            sizeof(struct ucc_geth_thread_data_rx),
2677                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2678         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2679                 if (netif_msg_ifup(ugeth))
2680                         pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
2681                 return -ENOMEM;
2682         }
2683
2684         ugeth->p_thread_data_rx =
2685             (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2686                                                         thread_dat_rx_offset);
2687         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2688
2689         /* typeorlen */
2690         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2691
2692         /* rxrmonbaseptr (statistics) */
2693         if (ug_info->
2694             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2695                 ugeth->rx_fw_statistics_pram_offset =
2696                     qe_muram_alloc(sizeof
2697                                    (struct ucc_geth_rx_firmware_statistics_pram),
2698                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2699                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2700                         if (netif_msg_ifup(ugeth))
2701                                 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
2702                         return -ENOMEM;
2703                 }
2704                 ugeth->p_rx_fw_statistics_pram =
2705                     (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2706                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2707         }
2708
2709         /* intCoalescingPtr */
2710
2711         /* Size varies with number of Rx queues */
2712         ugeth->rx_irq_coalescing_tbl_offset =
2713             qe_muram_alloc(ug_info->numQueuesRx *
2714                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2715                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2716         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2717                 if (netif_msg_ifup(ugeth))
2718                         pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
2719                 return -ENOMEM;
2720         }
2721
2722         ugeth->p_rx_irq_coalescing_tbl =
2723             (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2724             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2725         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2726                  ugeth->rx_irq_coalescing_tbl_offset);
2727
2728         /* Fill interrupt coalescing table */
2729         for (i = 0; i < ug_info->numQueuesRx; i++) {
2730                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2731                          interruptcoalescingmaxvalue,
2732                          ug_info->interruptcoalescingmaxvalue[i]);
2733                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2734                          interruptcoalescingcounter,
2735                          ug_info->interruptcoalescingmaxvalue[i]);
2736         }
2737
2738         /* MRBLR */
2739         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2740                              &ugeth->p_rx_glbl_pram->mrblr);
2741         /* MFLR */
2742         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2743         /* MINFLR */
2744         init_min_frame_len(ug_info->minFrameLength,
2745                            &ugeth->p_rx_glbl_pram->minflr,
2746                            &ugeth->p_rx_glbl_pram->mrblr);
2747         /* MAXD1 */
2748         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2749         /* MAXD2 */
2750         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2751
2752         /* l2qt */
2753         l2qt = 0;
2754         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2755                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2756         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2757
2758         /* l3qt */
2759         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2760                 l3qt = 0;
2761                 for (i = 0; i < 8; i++)
2762                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2763                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2764         }
2765
2766         /* vlantype */
2767         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2768
2769         /* vlantci */
2770         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2771
2772         /* ecamptr */
2773         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2774
2775         /* RBDQPTR */
2776         /* Size varies with number of Rx queues */
2777         ugeth->rx_bd_qs_tbl_offset =
2778             qe_muram_alloc(ug_info->numQueuesRx *
2779                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2780                             sizeof(struct ucc_geth_rx_prefetched_bds)),
2781                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2782         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2783                 if (netif_msg_ifup(ugeth))
2784                         pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
2785                 return -ENOMEM;
2786         }
2787
2788         ugeth->p_rx_bd_qs_tbl =
2789             (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2790                                     rx_bd_qs_tbl_offset);
2791         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2792
2793         /* Setup the table */
2794         /* Assume BD rings are already established */
2795         for (i = 0; i < ug_info->numQueuesRx; i++) {
2796                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2797                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2798                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2799                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2800                            MEM_PART_MURAM) {
2801                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2802                                  (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
2803                 }
2804                 /* rest of fields handled by QE */
2805         }
2806
2807         /* remoder */
2808         /* Already has speed set */
2809
2810         if (ugeth->rx_extended_features)
2811                 remoder |= REMODER_RX_EXTENDED_FEATURES;
2812         if (ug_info->rxExtendedFiltering)
2813                 remoder |= REMODER_RX_EXTENDED_FILTERING;
2814         if (ug_info->dynamicMaxFrameLength)
2815                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2816         if (ug_info->dynamicMinFrameLength)
2817                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2818         remoder |=
2819             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2820         remoder |=
2821             ug_info->
2822             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2823         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2824         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2825         if (ug_info->ipCheckSumCheck)
2826                 remoder |= REMODER_IP_CHECKSUM_CHECK;
2827         if (ug_info->ipAddressAlignment)
2828                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2829         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2830
2831         /* Note that this function must be called */
2832         /* ONLY AFTER p_tx_fw_statistics_pram */
2833         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2834         init_firmware_statistics_gathering_mode((ug_info->
2835                 statisticsMode &
2836                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2837                 (ug_info->statisticsMode &
2838                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2839                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2840                 ugeth->tx_fw_statistics_pram_offset,
2841                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2842                 ugeth->rx_fw_statistics_pram_offset,
2843                 &ugeth->p_tx_glbl_pram->temoder,
2844                 &ugeth->p_rx_glbl_pram->remoder);
2845
2846         /* function code register */
2847         out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2848
2849         /* initialize extended filtering */
2850         if (ug_info->rxExtendedFiltering) {
2851                 if (!ug_info->extendedFilteringChainPointer) {
2852                         if (netif_msg_ifup(ugeth))
2853                                 pr_err("Null Extended Filtering Chain Pointer\n");
2854                         return -EINVAL;
2855                 }
2856
2857                 /* Allocate memory for extended filtering Mode Global
2858                 Parameters */
2859                 ugeth->exf_glbl_param_offset =
2860                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2861                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2862                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2863                         if (netif_msg_ifup(ugeth))
2864                                 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
2865                         return -ENOMEM;
2866                 }
2867
2868                 ugeth->p_exf_glbl_param =
2869                     (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2870                                  exf_glbl_param_offset);
2871                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2872                          ugeth->exf_glbl_param_offset);
2873                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2874                          (u32) ug_info->extendedFilteringChainPointer);
2875
2876         } else {                /* initialize 82xx style address filtering */
2877
2878                 /* Init individual address recognition registers to disabled */
2879
2880                 for (j = 0; j < NUM_OF_PADDRS; j++)
2881                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2882
2883                 p_82xx_addr_filt =
2884                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2885                     p_rx_glbl_pram->addressfiltering;
2886
2887                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2888                         ENET_ADDR_TYPE_GROUP);
2889                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2890                         ENET_ADDR_TYPE_INDIVIDUAL);
2891         }
2892
2893         /*
2894          * Initialize UCC at QE level
2895          */
2896
2897         command = QE_INIT_TX_RX;
2898
2899         /* Allocate shadow InitEnet command parameter structure.
2900          * This is needed because after the InitEnet command is executed,
2901          * the structure in DPRAM is released, because DPRAM is a premium
2902          * resource.
2903          * This shadow structure keeps a copy of what was done so that the
2904          * allocated resources can be released when the channel is freed.
2905          */
2906         if (!(ugeth->p_init_enet_param_shadow =
2907               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2908                 if (netif_msg_ifup(ugeth))
2909                         pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
2910                 return -ENOMEM;
2911         }
2912         /* Zero out *p_init_enet_param_shadow */
2913         memset((char *)ugeth->p_init_enet_param_shadow,
2914                0, sizeof(struct ucc_geth_init_pram));
2915
2916         /* Fill shadow InitEnet command parameter structure */
2917
2918         ugeth->p_init_enet_param_shadow->resinit1 =
2919             ENET_INIT_PARAM_MAGIC_RES_INIT1;
2920         ugeth->p_init_enet_param_shadow->resinit2 =
2921             ENET_INIT_PARAM_MAGIC_RES_INIT2;
2922         ugeth->p_init_enet_param_shadow->resinit3 =
2923             ENET_INIT_PARAM_MAGIC_RES_INIT3;
2924         ugeth->p_init_enet_param_shadow->resinit4 =
2925             ENET_INIT_PARAM_MAGIC_RES_INIT4;
2926         ugeth->p_init_enet_param_shadow->resinit5 =
2927             ENET_INIT_PARAM_MAGIC_RES_INIT5;
2928         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2929             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2930         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2931             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2932
2933         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2934             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2935         if ((ug_info->largestexternallookupkeysize !=
2936              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2937             (ug_info->largestexternallookupkeysize !=
2938              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2939             (ug_info->largestexternallookupkeysize !=
2940              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2941                 if (netif_msg_ifup(ugeth))
2942                         pr_err("Invalid largest External Lookup Key Size\n");
2943                 return -EINVAL;
2944         }
2945         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2946             ug_info->largestexternallookupkeysize;
2947         size = sizeof(struct ucc_geth_thread_rx_pram);
2948         if (ug_info->rxExtendedFiltering) {
2949                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2950                 if (ug_info->largestexternallookupkeysize ==
2951                     QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2952                         size +=
2953                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2954                 if (ug_info->largestexternallookupkeysize ==
2955                     QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2956                         size +=
2957                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2958         }
2959
2960         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2961                 p_init_enet_param_shadow->rxthread[0]),
2962                 (u8) (numThreadsRxNumerical + 1)
2963                 /* Rx needs one extra for terminator */
2964                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2965                 ug_info->riscRx, 1)) != 0) {
2966                 if (netif_msg_ifup(ugeth))
2967                         pr_err("Can not fill p_init_enet_param_shadow\n");
2968                 return ret_val;
2969         }
2970
2971         ugeth->p_init_enet_param_shadow->txglobal =
2972             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
2973         if ((ret_val =
2974              fill_init_enet_entries(ugeth,
2975                                     &(ugeth->p_init_enet_param_shadow->
2976                                       txthread[0]), numThreadsTxNumerical,
2977                                     sizeof(struct ucc_geth_thread_tx_pram),
2978                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
2979                                     ug_info->riscTx, 0)) != 0) {
2980                 if (netif_msg_ifup(ugeth))
2981                         pr_err("Can not fill p_init_enet_param_shadow\n");
2982                 return ret_val;
2983         }
2984
2985         /* Load Rx bds with buffers */
2986         for (i = 0; i < ug_info->numQueuesRx; i++) {
2987                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
2988                         if (netif_msg_ifup(ugeth))
2989                                 pr_err("Can not fill Rx bds with buffers\n");
2990                         return ret_val;
2991                 }
2992         }
2993
2994         /* Allocate InitEnet command parameter structure */
2995         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
2996         if (IS_ERR_VALUE(init_enet_pram_offset)) {
2997                 if (netif_msg_ifup(ugeth))
2998                         pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
2999                 return -ENOMEM;
3000         }
3001         p_init_enet_pram =
3002             (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3003
3004         /* Copy shadow InitEnet command parameter structure into PRAM */
3005         out_8(&p_init_enet_pram->resinit1,
3006                         ugeth->p_init_enet_param_shadow->resinit1);
3007         out_8(&p_init_enet_pram->resinit2,
3008                         ugeth->p_init_enet_param_shadow->resinit2);
3009         out_8(&p_init_enet_pram->resinit3,
3010                         ugeth->p_init_enet_param_shadow->resinit3);
3011         out_8(&p_init_enet_pram->resinit4,
3012                         ugeth->p_init_enet_param_shadow->resinit4);
3013         out_be16(&p_init_enet_pram->resinit5,
3014                  ugeth->p_init_enet_param_shadow->resinit5);
3015         out_8(&p_init_enet_pram->largestexternallookupkeysize,
3016             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3017         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3018                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3019         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3020                 out_be32(&p_init_enet_pram->rxthread[i],
3021                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3022         out_be32(&p_init_enet_pram->txglobal,
3023                  ugeth->p_init_enet_param_shadow->txglobal);
3024         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3025                 out_be32(&p_init_enet_pram->txthread[i],
3026                          ugeth->p_init_enet_param_shadow->txthread[i]);
3027
3028         /* Issue QE command */
3029         cecr_subblock =
3030             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3031         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3032                      init_enet_pram_offset);
3033
3034         /* Free InitEnet command parameter */
3035         qe_muram_free(init_enet_pram_offset);
3036
3037         return 0;
3038 }
3039
3040 /* This is called by the kernel when a frame is ready for transmission. */
3041 /* It is pointed to by the dev->hard_start_xmit function pointer */
3042 static netdev_tx_t
3043 ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3044 {
3045         struct ucc_geth_private *ugeth = netdev_priv(dev);
3046 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3047         struct ucc_fast_private *uccf;
3048 #endif
3049         u8 __iomem *bd;                 /* BD pointer */
3050         u32 bd_status;
3051         u8 txQ = 0;
3052         unsigned long flags;
3053
3054         ugeth_vdbg("%s: IN", __func__);
3055
3056         netdev_sent_queue(dev, skb->len);
3057         spin_lock_irqsave(&ugeth->lock, flags);
3058
3059         dev->stats.tx_bytes += skb->len;
3060
3061         /* Start from the next BD that should be filled */
3062         bd = ugeth->txBd[txQ];
3063         bd_status = in_be32((u32 __iomem *)bd);
3064         /* Save the skb pointer so we can free it later */
3065         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3066
3067         /* Update the current skb pointer (wrapping if this was the last) */
3068         ugeth->skb_curtx[txQ] =
3069             (ugeth->skb_curtx[txQ] +
3070              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3071
3072         /* set up the buffer descriptor */
3073         out_be32(&((struct qe_bd __iomem *)bd)->buf,
3074                       dma_map_single(ugeth->dev, skb->data,
3075                               skb->len, DMA_TO_DEVICE));
3076
3077         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3078
3079         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3080
3081         /* set bd status and length */
3082         out_be32((u32 __iomem *)bd, bd_status);
3083
3084         /* Move to next BD in the ring */
3085         if (!(bd_status & T_W))
3086                 bd += sizeof(struct qe_bd);
3087         else
3088                 bd = ugeth->p_tx_bd_ring[txQ];
3089
3090         /* If the next BD still needs to be cleaned up, then the bds
3091            are full.  We need to tell the kernel to stop sending us stuff. */
3092         if (bd == ugeth->confBd[txQ]) {
3093                 if (!netif_queue_stopped(dev))
3094                         netif_stop_queue(dev);
3095         }
3096
3097         ugeth->txBd[txQ] = bd;
3098
3099         skb_tx_timestamp(skb);
3100
3101         if (ugeth->p_scheduler) {
3102                 ugeth->cpucount[txQ]++;
3103                 /* Indicate to QE that there are more Tx bds ready for
3104                 transmission */
3105                 /* This is done by writing a running counter of the bd
3106                 count to the scheduler PRAM. */
3107                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3108         }
3109
3110 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3111         uccf = ugeth->uccf;
3112         out_be16(uccf->p_utodr, UCC_FAST_TOD);
3113 #endif
3114         spin_unlock_irqrestore(&ugeth->lock, flags);
3115
3116         return NETDEV_TX_OK;
3117 }
3118
3119 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3120 {
3121         struct sk_buff *skb;
3122         u8 __iomem *bd;
3123         u16 length, howmany = 0;
3124         u32 bd_status;
3125         u8 *bdBuffer;
3126         struct net_device *dev;
3127
3128         ugeth_vdbg("%s: IN", __func__);
3129
3130         dev = ugeth->ndev;
3131
3132         /* collect received buffers */
3133         bd = ugeth->rxBd[rxQ];
3134
3135         bd_status = in_be32((u32 __iomem *)bd);
3136
3137         /* while there are received buffers and BD is full (~R_E) */
3138         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3139                 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3140                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3141                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3142
3143                 /* determine whether buffer is first, last, first and last
3144                 (single buffer frame) or middle (not first and not last) */
3145                 if (!skb ||
3146                     (!(bd_status & (R_F | R_L))) ||
3147                     (bd_status & R_ERRORS_FATAL)) {
3148                         if (netif_msg_rx_err(ugeth))
3149                                 pr_err("%d: ERROR!!! skb - 0x%08x\n",
3150                                        __LINE__, (u32)skb);
3151                         dev_kfree_skb(skb);
3152
3153                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3154                         dev->stats.rx_dropped++;
3155                 } else {
3156                         dev->stats.rx_packets++;
3157                         howmany++;
3158
3159                         /* Prep the skb for the packet */
3160                         skb_put(skb, length);
3161
3162                         /* Tell the skb what kind of packet this is */
3163                         skb->protocol = eth_type_trans(skb, ugeth->ndev);
3164
3165                         dev->stats.rx_bytes += length;
3166                         /* Send the packet up the stack */
3167                         netif_receive_skb(skb);
3168                 }
3169
3170                 skb = get_new_skb(ugeth, bd);
3171                 if (!skb) {
3172                         if (netif_msg_rx_err(ugeth))
3173                                 pr_warn("No Rx Data Buffer\n");
3174                         dev->stats.rx_dropped++;
3175                         break;
3176                 }
3177
3178                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3179
3180                 /* update to point at the next skb */
3181                 ugeth->skb_currx[rxQ] =
3182                     (ugeth->skb_currx[rxQ] +
3183                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3184
3185                 if (bd_status & R_W)
3186                         bd = ugeth->p_rx_bd_ring[rxQ];
3187                 else
3188                         bd += sizeof(struct qe_bd);
3189
3190                 bd_status = in_be32((u32 __iomem *)bd);
3191         }
3192
3193         ugeth->rxBd[rxQ] = bd;
3194         return howmany;
3195 }
3196
3197 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3198 {
3199         /* Start from the next BD that should be filled */
3200         struct ucc_geth_private *ugeth = netdev_priv(dev);
3201         unsigned int bytes_sent = 0;
3202         int howmany = 0;
3203         u8 __iomem *bd;         /* BD pointer */
3204         u32 bd_status;
3205
3206         bd = ugeth->confBd[txQ];
3207         bd_status = in_be32((u32 __iomem *)bd);
3208
3209         /* Normal processing. */
3210         while ((bd_status & T_R) == 0) {
3211                 struct sk_buff *skb;
3212
3213                 /* BD contains already transmitted buffer.   */
3214                 /* Handle the transmitted buffer and release */
3215                 /* the BD to be used with the current frame  */
3216
3217                 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3218                 if (!skb)
3219                         break;
3220                 howmany++;
3221                 bytes_sent += skb->len;
3222                 dev->stats.tx_packets++;
3223
3224                 dev_consume_skb_any(skb);
3225
3226                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3227                 ugeth->skb_dirtytx[txQ] =
3228                     (ugeth->skb_dirtytx[txQ] +
3229                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3230
3231                 /* We freed a buffer, so now we can restart transmission */
3232                 if (netif_queue_stopped(dev))
3233                         netif_wake_queue(dev);
3234
3235                 /* Advance the confirmation BD pointer */
3236                 if (!(bd_status & T_W))
3237                         bd += sizeof(struct qe_bd);
3238                 else
3239                         bd = ugeth->p_tx_bd_ring[txQ];
3240                 bd_status = in_be32((u32 __iomem *)bd);
3241         }
3242         ugeth->confBd[txQ] = bd;
3243         netdev_completed_queue(dev, howmany, bytes_sent);
3244         return 0;
3245 }
3246
3247 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3248 {
3249         struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3250         struct ucc_geth_info *ug_info;
3251         int howmany, i;
3252
3253         ug_info = ugeth->ug_info;
3254
3255         /* Tx event processing */
3256         spin_lock(&ugeth->lock);
3257         for (i = 0; i < ug_info->numQueuesTx; i++)
3258                 ucc_geth_tx(ugeth->ndev, i);
3259         spin_unlock(&ugeth->lock);
3260
3261         howmany = 0;
3262         for (i = 0; i < ug_info->numQueuesRx; i++)
3263                 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3264
3265         if (howmany < budget) {
3266                 napi_complete_done(napi, howmany);
3267                 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3268         }
3269
3270         return howmany;
3271 }
3272
3273 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3274 {
3275         struct net_device *dev = info;
3276         struct ucc_geth_private *ugeth = netdev_priv(dev);
3277         struct ucc_fast_private *uccf;
3278         struct ucc_geth_info *ug_info;
3279         register u32 ucce;
3280         register u32 uccm;
3281
3282         ugeth_vdbg("%s: IN", __func__);
3283
3284         uccf = ugeth->uccf;
3285         ug_info = ugeth->ug_info;
3286
3287         /* read and clear events */
3288         ucce = (u32) in_be32(uccf->p_ucce);
3289         uccm = (u32) in_be32(uccf->p_uccm);
3290         ucce &= uccm;
3291         out_be32(uccf->p_ucce, ucce);
3292
3293         /* check for receive events that require processing */
3294         if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3295                 if (napi_schedule_prep(&ugeth->napi)) {
3296                         uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3297                         out_be32(uccf->p_uccm, uccm);
3298                         __napi_schedule(&ugeth->napi);
3299                 }
3300         }
3301
3302         /* Errors and other events */
3303         if (ucce & UCCE_OTHER) {
3304                 if (ucce & UCC_GETH_UCCE_BSY)
3305                         dev->stats.rx_errors++;
3306                 if (ucce & UCC_GETH_UCCE_TXE)
3307                         dev->stats.tx_errors++;
3308         }
3309
3310         return IRQ_HANDLED;
3311 }
3312
3313 #ifdef CONFIG_NET_POLL_CONTROLLER
3314 /*
3315  * Polling 'interrupt' - used by things like netconsole to send skbs
3316  * without having to re-enable interrupts. It's not called while
3317  * the interrupt routine is executing.
3318  */
3319 static void ucc_netpoll(struct net_device *dev)
3320 {
3321         struct ucc_geth_private *ugeth = netdev_priv(dev);
3322         int irq = ugeth->ug_info->uf_info.irq;
3323
3324         disable_irq(irq);
3325         ucc_geth_irq_handler(irq, dev);
3326         enable_irq(irq);
3327 }
3328 #endif /* CONFIG_NET_POLL_CONTROLLER */
3329
3330 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3331 {
3332         struct ucc_geth_private *ugeth = netdev_priv(dev);
3333         struct sockaddr *addr = p;
3334
3335         if (!is_valid_ether_addr(addr->sa_data))
3336                 return -EADDRNOTAVAIL;
3337
3338         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3339
3340         /*
3341          * If device is not running, we will set mac addr register
3342          * when opening the device.
3343          */
3344         if (!netif_running(dev))
3345                 return 0;
3346
3347         spin_lock_irq(&ugeth->lock);
3348         init_mac_station_addr_regs(dev->dev_addr[0],
3349                                    dev->dev_addr[1],
3350                                    dev->dev_addr[2],
3351                                    dev->dev_addr[3],
3352                                    dev->dev_addr[4],
3353                                    dev->dev_addr[5],
3354                                    &ugeth->ug_regs->macstnaddr1,
3355                                    &ugeth->ug_regs->macstnaddr2);
3356         spin_unlock_irq(&ugeth->lock);
3357
3358         return 0;
3359 }
3360
3361 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3362 {
3363         struct net_device *dev = ugeth->ndev;
3364         int err;
3365
3366         err = ucc_struct_init(ugeth);
3367         if (err) {
3368                 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
3369                 goto err;
3370         }
3371
3372         err = ucc_geth_startup(ugeth);
3373         if (err) {
3374                 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3375                 goto err;
3376         }
3377
3378         err = adjust_enet_interface(ugeth);
3379         if (err) {
3380                 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3381                 goto err;
3382         }
3383
3384         /*       Set MACSTNADDR1, MACSTNADDR2                */
3385         /* For more details see the hardware spec.           */
3386         init_mac_station_addr_regs(dev->dev_addr[0],
3387                                    dev->dev_addr[1],
3388                                    dev->dev_addr[2],
3389                                    dev->dev_addr[3],
3390                                    dev->dev_addr[4],
3391                                    dev->dev_addr[5],
3392                                    &ugeth->ug_regs->macstnaddr1,
3393                                    &ugeth->ug_regs->macstnaddr2);
3394
3395         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3396         if (err) {
3397                 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n");
3398                 goto err;
3399         }
3400
3401         return 0;
3402 err:
3403         ucc_geth_stop(ugeth);
3404         return err;
3405 }
3406
3407 /* Called when something needs to use the ethernet device */
3408 /* Returns 0 for success. */
3409 static int ucc_geth_open(struct net_device *dev)
3410 {
3411         struct ucc_geth_private *ugeth = netdev_priv(dev);
3412         int err;
3413
3414         ugeth_vdbg("%s: IN", __func__);
3415
3416         /* Test station address */
3417         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3418                 netif_err(ugeth, ifup, dev,
3419                           "Multicast address used for station address - is this what you wanted?\n");
3420                 return -EINVAL;
3421         }
3422
3423         err = init_phy(dev);
3424         if (err) {
3425                 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n");
3426                 return err;
3427         }
3428
3429         err = ucc_geth_init_mac(ugeth);
3430         if (err) {
3431                 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
3432                 goto err;
3433         }
3434
3435         err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3436                           0, "UCC Geth", dev);
3437         if (err) {
3438                 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
3439                 goto err;
3440         }
3441
3442         phy_start(ugeth->phydev);
3443         napi_enable(&ugeth->napi);
3444         netdev_reset_queue(dev);
3445         netif_start_queue(dev);
3446
3447         device_set_wakeup_capable(&dev->dev,
3448                         qe_alive_during_sleep() || ugeth->phydev->irq);
3449         device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3450
3451         return err;
3452
3453 err:
3454         ucc_geth_stop(ugeth);
3455         return err;
3456 }
3457
3458 /* Stops the kernel queue, and halts the controller */
3459 static int ucc_geth_close(struct net_device *dev)
3460 {
3461         struct ucc_geth_private *ugeth = netdev_priv(dev);
3462
3463         ugeth_vdbg("%s: IN", __func__);
3464
3465         napi_disable(&ugeth->napi);
3466
3467         cancel_work_sync(&ugeth->timeout_work);
3468         ucc_geth_stop(ugeth);
3469         phy_disconnect(ugeth->phydev);
3470         ugeth->phydev = NULL;
3471
3472         free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3473
3474         netif_stop_queue(dev);
3475         netdev_reset_queue(dev);
3476
3477         return 0;
3478 }
3479
3480 /* Reopen device. This will reset the MAC and PHY. */
3481 static void ucc_geth_timeout_work(struct work_struct *work)
3482 {
3483         struct ucc_geth_private *ugeth;
3484         struct net_device *dev;
3485
3486         ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3487         dev = ugeth->ndev;
3488
3489         ugeth_vdbg("%s: IN", __func__);
3490
3491         dev->stats.tx_errors++;
3492
3493         ugeth_dump_regs(ugeth);
3494
3495         if (dev->flags & IFF_UP) {
3496                 /*
3497                  * Must reset MAC *and* PHY. This is done by reopening
3498                  * the device.
3499                  */
3500                 netif_tx_stop_all_queues(dev);
3501                 ucc_geth_stop(ugeth);
3502                 ucc_geth_init_mac(ugeth);
3503                 /* Must start PHY here */
3504                 phy_start(ugeth->phydev);
3505                 netif_tx_start_all_queues(dev);
3506         }
3507
3508         netif_tx_schedule_all(dev);
3509 }
3510
3511 /*
3512  * ucc_geth_timeout gets called when a packet has not been
3513  * transmitted after a set amount of time.
3514  */
3515 static void ucc_geth_timeout(struct net_device *dev, unsigned int txqueue)
3516 {
3517         struct ucc_geth_private *ugeth = netdev_priv(dev);
3518
3519         schedule_work(&ugeth->timeout_work);
3520 }
3521
3522
3523 #ifdef CONFIG_PM
3524
3525 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
3526 {
3527         struct net_device *ndev = platform_get_drvdata(ofdev);
3528         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3529
3530         if (!netif_running(ndev))
3531                 return 0;
3532
3533         netif_device_detach(ndev);
3534         napi_disable(&ugeth->napi);
3535
3536         /*
3537          * Disable the controller, otherwise we'll wakeup on any network
3538          * activity.
3539          */
3540         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3541
3542         if (ugeth->wol_en & WAKE_MAGIC) {
3543                 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3544                 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3545                 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3546         } else if (!(ugeth->wol_en & WAKE_PHY)) {
3547                 phy_stop(ugeth->phydev);
3548         }
3549
3550         return 0;
3551 }
3552
3553 static int ucc_geth_resume(struct platform_device *ofdev)
3554 {
3555         struct net_device *ndev = platform_get_drvdata(ofdev);
3556         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3557         int err;
3558
3559         if (!netif_running(ndev))
3560                 return 0;
3561
3562         if (qe_alive_during_sleep()) {
3563                 if (ugeth->wol_en & WAKE_MAGIC) {
3564                         ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3565                         clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3566                         clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3567                 }
3568                 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3569         } else {
3570                 /*
3571                  * Full reinitialization is required if QE shuts down
3572                  * during sleep.
3573                  */
3574                 ucc_geth_memclean(ugeth);
3575
3576                 err = ucc_geth_init_mac(ugeth);
3577                 if (err) {
3578                         netdev_err(ndev, "Cannot initialize MAC, aborting\n");
3579                         return err;
3580                 }
3581         }
3582
3583         ugeth->oldlink = 0;
3584         ugeth->oldspeed = 0;
3585         ugeth->oldduplex = -1;
3586
3587         phy_stop(ugeth->phydev);
3588         phy_start(ugeth->phydev);
3589
3590         napi_enable(&ugeth->napi);
3591         netif_device_attach(ndev);
3592
3593         return 0;
3594 }
3595
3596 #else
3597 #define ucc_geth_suspend NULL
3598 #define ucc_geth_resume NULL
3599 #endif
3600
3601 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3602 {
3603         if (strcasecmp(phy_connection_type, "mii") == 0)
3604                 return PHY_INTERFACE_MODE_MII;
3605         if (strcasecmp(phy_connection_type, "gmii") == 0)
3606                 return PHY_INTERFACE_MODE_GMII;
3607         if (strcasecmp(phy_connection_type, "tbi") == 0)
3608                 return PHY_INTERFACE_MODE_TBI;
3609         if (strcasecmp(phy_connection_type, "rmii") == 0)
3610                 return PHY_INTERFACE_MODE_RMII;
3611         if (strcasecmp(phy_connection_type, "rgmii") == 0)
3612                 return PHY_INTERFACE_MODE_RGMII;
3613         if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3614                 return PHY_INTERFACE_MODE_RGMII_ID;
3615         if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3616                 return PHY_INTERFACE_MODE_RGMII_TXID;
3617         if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3618                 return PHY_INTERFACE_MODE_RGMII_RXID;
3619         if (strcasecmp(phy_connection_type, "rtbi") == 0)
3620                 return PHY_INTERFACE_MODE_RTBI;
3621         if (strcasecmp(phy_connection_type, "sgmii") == 0)
3622                 return PHY_INTERFACE_MODE_SGMII;
3623
3624         return PHY_INTERFACE_MODE_MII;
3625 }
3626
3627 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3628 {
3629         struct ucc_geth_private *ugeth = netdev_priv(dev);
3630
3631         if (!netif_running(dev))
3632                 return -EINVAL;
3633
3634         if (!ugeth->phydev)
3635                 return -ENODEV;
3636
3637         return phy_mii_ioctl(ugeth->phydev, rq, cmd);
3638 }
3639
3640 static const struct net_device_ops ucc_geth_netdev_ops = {
3641         .ndo_open               = ucc_geth_open,
3642         .ndo_stop               = ucc_geth_close,
3643         .ndo_start_xmit         = ucc_geth_start_xmit,
3644         .ndo_validate_addr      = eth_validate_addr,
3645         .ndo_change_carrier     = fixed_phy_change_carrier,
3646         .ndo_set_mac_address    = ucc_geth_set_mac_addr,
3647         .ndo_set_rx_mode        = ucc_geth_set_multi,
3648         .ndo_tx_timeout         = ucc_geth_timeout,
3649         .ndo_do_ioctl           = ucc_geth_ioctl,
3650 #ifdef CONFIG_NET_POLL_CONTROLLER
3651         .ndo_poll_controller    = ucc_netpoll,
3652 #endif
3653 };
3654
3655 static int ucc_geth_probe(struct platform_device* ofdev)
3656 {
3657         struct device *device = &ofdev->dev;
3658         struct device_node *np = ofdev->dev.of_node;
3659         struct net_device *dev = NULL;
3660         struct ucc_geth_private *ugeth = NULL;
3661         struct ucc_geth_info *ug_info;
3662         struct resource res;
3663         int err, ucc_num, max_speed = 0;
3664         const unsigned int *prop;
3665         const char *sprop;
3666         const void *mac_addr;
3667         phy_interface_t phy_interface;
3668         static const int enet_to_speed[] = {
3669                 SPEED_10, SPEED_10, SPEED_10,
3670                 SPEED_100, SPEED_100, SPEED_100,
3671                 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3672         };
3673         static const phy_interface_t enet_to_phy_interface[] = {
3674                 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3675                 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3676                 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3677                 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3678                 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3679                 PHY_INTERFACE_MODE_SGMII,
3680         };
3681
3682         ugeth_vdbg("%s: IN", __func__);
3683
3684         prop = of_get_property(np, "cell-index", NULL);
3685         if (!prop) {
3686                 prop = of_get_property(np, "device-id", NULL);
3687                 if (!prop)
3688                         return -ENODEV;
3689         }
3690
3691         ucc_num = *prop - 1;
3692         if ((ucc_num < 0) || (ucc_num > 7))
3693                 return -ENODEV;
3694
3695         ug_info = &ugeth_info[ucc_num];
3696         if (ug_info == NULL) {
3697                 if (netif_msg_probe(&debug))
3698                         pr_err("[%d] Missing additional data!\n", ucc_num);
3699                 return -ENODEV;
3700         }
3701
3702         ug_info->uf_info.ucc_num = ucc_num;
3703
3704         sprop = of_get_property(np, "rx-clock-name", NULL);
3705         if (sprop) {
3706                 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3707                 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3708                     (ug_info->uf_info.rx_clock > QE_CLK24)) {
3709                         pr_err("invalid rx-clock-name property\n");
3710                         return -EINVAL;
3711                 }
3712         } else {
3713                 prop = of_get_property(np, "rx-clock", NULL);
3714                 if (!prop) {
3715                         /* If both rx-clock-name and rx-clock are missing,
3716                            we want to tell people to use rx-clock-name. */
3717                         pr_err("missing rx-clock-name property\n");
3718                         return -EINVAL;
3719                 }
3720                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3721                         pr_err("invalid rx-clock property\n");
3722                         return -EINVAL;
3723                 }
3724                 ug_info->uf_info.rx_clock = *prop;
3725         }
3726
3727         sprop = of_get_property(np, "tx-clock-name", NULL);
3728         if (sprop) {
3729                 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3730                 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3731                     (ug_info->uf_info.tx_clock > QE_CLK24)) {
3732                         pr_err("invalid tx-clock-name property\n");
3733                         return -EINVAL;
3734                 }
3735         } else {
3736                 prop = of_get_property(np, "tx-clock", NULL);
3737                 if (!prop) {
3738                         pr_err("missing tx-clock-name property\n");
3739                         return -EINVAL;
3740                 }
3741                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3742                         pr_err("invalid tx-clock property\n");
3743                         return -EINVAL;
3744                 }
3745                 ug_info->uf_info.tx_clock = *prop;
3746         }
3747
3748         err = of_address_to_resource(np, 0, &res);
3749         if (err)
3750                 return -EINVAL;
3751
3752         ug_info->uf_info.regs = res.start;
3753         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3754
3755         ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3756         if (!ug_info->phy_node && of_phy_is_fixed_link(np)) {
3757                 /*
3758                  * In the case of a fixed PHY, the DT node associated
3759                  * to the PHY is the Ethernet MAC DT node.
3760                  */
3761                 err = of_phy_register_fixed_link(np);
3762                 if (err)
3763                         return err;
3764                 ug_info->phy_node = of_node_get(np);
3765         }
3766
3767         /* Find the TBI PHY node.  If it's not there, we don't support SGMII */
3768         ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3769
3770         /* get the phy interface type, or default to MII */
3771         prop = of_get_property(np, "phy-connection-type", NULL);
3772         if (!prop) {
3773                 /* handle interface property present in old trees */
3774                 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3775                 if (prop != NULL) {
3776                         phy_interface = enet_to_phy_interface[*prop];
3777                         max_speed = enet_to_speed[*prop];
3778                 } else
3779                         phy_interface = PHY_INTERFACE_MODE_MII;
3780         } else {
3781                 phy_interface = to_phy_interface((const char *)prop);
3782         }
3783
3784         /* get speed, or derive from PHY interface */
3785         if (max_speed == 0)
3786                 switch (phy_interface) {
3787                 case PHY_INTERFACE_MODE_GMII:
3788                 case PHY_INTERFACE_MODE_RGMII:
3789                 case PHY_INTERFACE_MODE_RGMII_ID:
3790                 case PHY_INTERFACE_MODE_RGMII_RXID:
3791                 case PHY_INTERFACE_MODE_RGMII_TXID:
3792                 case PHY_INTERFACE_MODE_TBI:
3793                 case PHY_INTERFACE_MODE_RTBI:
3794                 case PHY_INTERFACE_MODE_SGMII:
3795                         max_speed = SPEED_1000;
3796                         break;
3797                 default:
3798                         max_speed = SPEED_100;
3799                         break;
3800                 }
3801
3802         if (max_speed == SPEED_1000) {
3803                 unsigned int snums = qe_get_num_of_snums();
3804
3805                 /* configure muram FIFOs for gigabit operation */
3806                 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3807                 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3808                 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3809                 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3810                 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3811                 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3812                 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3813
3814                 /* If QE's snum number is 46/76 which means we need to support
3815                  * 4 UECs at 1000Base-T simultaneously, we need to allocate
3816                  * more Threads to Rx.
3817                  */
3818                 if ((snums == 76) || (snums == 46))
3819                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3820                 else
3821                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3822         }
3823
3824         if (netif_msg_probe(&debug))
3825                 pr_info("UCC%1d at 0x%8llx (irq = %d)\n",
3826                         ug_info->uf_info.ucc_num + 1,
3827                         (u64)ug_info->uf_info.regs,
3828                         ug_info->uf_info.irq);
3829
3830         /* Create an ethernet device instance */
3831         dev = alloc_etherdev(sizeof(*ugeth));
3832
3833         if (dev == NULL) {
3834                 err = -ENOMEM;
3835                 goto err_deregister_fixed_link;
3836         }
3837
3838         ugeth = netdev_priv(dev);
3839         spin_lock_init(&ugeth->lock);
3840
3841         /* Create CQs for hash tables */
3842         INIT_LIST_HEAD(&ugeth->group_hash_q);
3843         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3844
3845         dev_set_drvdata(device, dev);
3846
3847         /* Set the dev->base_addr to the gfar reg region */
3848         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3849
3850         SET_NETDEV_DEV(dev, device);
3851
3852         /* Fill in the dev structure */
3853         uec_set_ethtool_ops(dev);
3854         dev->netdev_ops = &ucc_geth_netdev_ops;
3855         dev->watchdog_timeo = TX_TIMEOUT;
3856         INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3857         netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3858         dev->mtu = 1500;
3859         dev->max_mtu = 1518;
3860
3861         ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3862         ugeth->phy_interface = phy_interface;
3863         ugeth->max_speed = max_speed;
3864
3865         /* Carrier starts down, phylib will bring it up */
3866         netif_carrier_off(dev);
3867
3868         err = register_netdev(dev);
3869         if (err) {
3870                 if (netif_msg_probe(ugeth))
3871                         pr_err("%s: Cannot register net device, aborting\n",
3872                                dev->name);
3873                 goto err_free_netdev;
3874         }
3875
3876         mac_addr = of_get_mac_address(np);
3877         if (!IS_ERR(mac_addr))
3878                 ether_addr_copy(dev->dev_addr, mac_addr);
3879
3880         ugeth->ug_info = ug_info;
3881         ugeth->dev = device;
3882         ugeth->ndev = dev;
3883         ugeth->node = np;
3884
3885         return 0;
3886
3887 err_free_netdev:
3888         free_netdev(dev);
3889 err_deregister_fixed_link:
3890         if (of_phy_is_fixed_link(np))
3891                 of_phy_deregister_fixed_link(np);
3892         of_node_put(ug_info->tbi_node);
3893         of_node_put(ug_info->phy_node);
3894
3895         return err;
3896 }
3897
3898 static int ucc_geth_remove(struct platform_device* ofdev)
3899 {
3900         struct net_device *dev = platform_get_drvdata(ofdev);
3901         struct ucc_geth_private *ugeth = netdev_priv(dev);
3902         struct device_node *np = ofdev->dev.of_node;
3903
3904         unregister_netdev(dev);
3905         ucc_geth_memclean(ugeth);
3906         if (of_phy_is_fixed_link(np))
3907                 of_phy_deregister_fixed_link(np);
3908         of_node_put(ugeth->ug_info->tbi_node);
3909         of_node_put(ugeth->ug_info->phy_node);
3910         free_netdev(dev);
3911
3912         return 0;
3913 }
3914
3915 static const struct of_device_id ucc_geth_match[] = {
3916         {
3917                 .type = "network",
3918                 .compatible = "ucc_geth",
3919         },
3920         {},
3921 };
3922
3923 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3924
3925 static struct platform_driver ucc_geth_driver = {
3926         .driver = {
3927                 .name = DRV_NAME,
3928                 .of_match_table = ucc_geth_match,
3929         },
3930         .probe          = ucc_geth_probe,
3931         .remove         = ucc_geth_remove,
3932         .suspend        = ucc_geth_suspend,
3933         .resume         = ucc_geth_resume,
3934 };
3935
3936 static int __init ucc_geth_init(void)
3937 {
3938         int i, ret;
3939
3940         if (netif_msg_drv(&debug))
3941                 pr_info(DRV_DESC "\n");
3942         for (i = 0; i < 8; i++)
3943                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3944                        sizeof(ugeth_primary_info));
3945
3946         ret = platform_driver_register(&ucc_geth_driver);
3947
3948         return ret;
3949 }
3950
3951 static void __exit ucc_geth_exit(void)
3952 {
3953         platform_driver_unregister(&ucc_geth_driver);
3954 }
3955
3956 module_init(ucc_geth_init);
3957 module_exit(ucc_geth_exit);
3958
3959 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3960 MODULE_DESCRIPTION(DRV_DESC);
3961 MODULE_LICENSE("GPL");