1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* drivers/net/ethernet/freescale/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
16 * Gianfar: AKA Lambda Draconis, "Dragon"
24 * The driver is initialized through of_device. Configuration information
25 * is therefore conveyed through an OF-style device tree.
27 * The Gianfar Ethernet Controller uses a ring of buffer
28 * descriptors. The beginning is indicated by a register
29 * pointing to the physical address of the start of the ring.
30 * The end is determined by a "wrap" bit being set in the
31 * last descriptor of the ring.
33 * When a packet is received, the RXF bit in the
34 * IEVENT register is set, triggering an interrupt when the
35 * corresponding bit in the IMASK register is also set (if
36 * interrupt coalescing is active, then the interrupt may not
37 * happen immediately, but will wait until either a set number
38 * of frames or amount of time have passed). In NAPI, the
39 * interrupt handler will signal there is work to be done, and
40 * exit. This method will start at the last known empty
41 * descriptor, and process every subsequent descriptor until there
42 * are none left with data (NAPI will stop after a set number of
43 * packets to give time to other tasks, but will eventually
44 * process all the packets). The data arrives inside a
45 * pre-allocated skb, and so after the skb is passed up to the
46 * stack, a new skb must be allocated, and the address field in
47 * the buffer descriptor must be updated to indicate this new
50 * When the kernel requests that a packet be transmitted, the
51 * driver starts where it left off last time, and points the
52 * descriptor at the buffer which was passed in. The driver
53 * then informs the DMA engine that there are packets ready to
54 * be transmitted. Once the controller is finished transmitting
55 * the packet, an interrupt may be triggered (under the same
56 * conditions as for reception, but depending on the TXF bit).
57 * The driver then cleans up the buffer.
60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
63 #include <linux/kernel.h>
64 #include <linux/string.h>
65 #include <linux/errno.h>
66 #include <linux/unistd.h>
67 #include <linux/slab.h>
68 #include <linux/interrupt.h>
69 #include <linux/delay.h>
70 #include <linux/netdevice.h>
71 #include <linux/etherdevice.h>
72 #include <linux/skbuff.h>
73 #include <linux/if_vlan.h>
74 #include <linux/spinlock.h>
76 #include <linux/of_address.h>
77 #include <linux/of_irq.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
84 #include <linux/net_tstamp.h>
89 #include <asm/mpc85xx.h>
92 #include <linux/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
100 #include <linux/of_net.h>
104 #define TX_TIMEOUT (5*HZ)
106 MODULE_AUTHOR("Freescale Semiconductor, Inc");
107 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
108 MODULE_LICENSE("GPL");
110 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
115 bdp->bufPtr = cpu_to_be32(buf);
117 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
118 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
119 lstatus |= BD_LFLAG(RXBD_WRAP);
123 bdp->lstatus = cpu_to_be32(lstatus);
126 static void gfar_init_tx_rx_base(struct gfar_private *priv)
128 struct gfar __iomem *regs = priv->gfargrp[0].regs;
132 baddr = ®s->tbase0;
133 for (i = 0; i < priv->num_tx_queues; i++) {
134 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
138 baddr = ®s->rbase0;
139 for (i = 0; i < priv->num_rx_queues; i++) {
140 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
145 static void gfar_init_rqprm(struct gfar_private *priv)
147 struct gfar __iomem *regs = priv->gfargrp[0].regs;
151 baddr = ®s->rqprm0;
152 for (i = 0; i < priv->num_rx_queues; i++) {
153 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
154 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
159 static void gfar_rx_offload_en(struct gfar_private *priv)
161 /* set this when rx hw offload (TOE) functions are being used */
162 priv->uses_rxfcb = 0;
164 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
165 priv->uses_rxfcb = 1;
167 if (priv->hwts_rx_en || priv->rx_filer_enable)
168 priv->uses_rxfcb = 1;
171 static void gfar_mac_rx_config(struct gfar_private *priv)
173 struct gfar __iomem *regs = priv->gfargrp[0].regs;
176 if (priv->rx_filer_enable) {
177 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
178 /* Program the RIR0 reg with the required distribution */
179 if (priv->poll_mode == GFAR_SQ_POLLING)
180 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
181 else /* GFAR_MQ_POLLING */
182 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
185 /* Restore PROMISC mode */
186 if (priv->ndev->flags & IFF_PROMISC)
189 if (priv->ndev->features & NETIF_F_RXCSUM)
190 rctrl |= RCTRL_CHECKSUMMING;
192 if (priv->extended_hash)
193 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
196 rctrl &= ~RCTRL_PAL_MASK;
197 rctrl |= RCTRL_PADDING(priv->padding);
200 /* Enable HW time stamping if requested from user space */
201 if (priv->hwts_rx_en)
202 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
204 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
205 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
207 /* Clear the LFC bit */
208 gfar_write(®s->rctrl, rctrl);
209 /* Init flow control threshold values */
210 gfar_init_rqprm(priv);
211 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
214 /* Init rctrl based on our settings */
215 gfar_write(®s->rctrl, rctrl);
218 static void gfar_mac_tx_config(struct gfar_private *priv)
220 struct gfar __iomem *regs = priv->gfargrp[0].regs;
223 if (priv->ndev->features & NETIF_F_IP_CSUM)
224 tctrl |= TCTRL_INIT_CSUM;
226 if (priv->prio_sched_en)
227 tctrl |= TCTRL_TXSCHED_PRIO;
229 tctrl |= TCTRL_TXSCHED_WRRS;
230 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
231 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
234 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
235 tctrl |= TCTRL_VLINS;
237 gfar_write(®s->tctrl, tctrl);
240 static void gfar_configure_coalescing(struct gfar_private *priv,
241 unsigned long tx_mask, unsigned long rx_mask)
243 struct gfar __iomem *regs = priv->gfargrp[0].regs;
246 if (priv->mode == MQ_MG_MODE) {
249 baddr = ®s->txic0;
250 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
251 gfar_write(baddr + i, 0);
252 if (likely(priv->tx_queue[i]->txcoalescing))
253 gfar_write(baddr + i, priv->tx_queue[i]->txic);
256 baddr = ®s->rxic0;
257 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
258 gfar_write(baddr + i, 0);
259 if (likely(priv->rx_queue[i]->rxcoalescing))
260 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
263 /* Backward compatible case -- even if we enable
264 * multiple queues, there's only single reg to program
266 gfar_write(®s->txic, 0);
267 if (likely(priv->tx_queue[0]->txcoalescing))
268 gfar_write(®s->txic, priv->tx_queue[0]->txic);
270 gfar_write(®s->rxic, 0);
271 if (unlikely(priv->rx_queue[0]->rxcoalescing))
272 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
276 static void gfar_configure_coalescing_all(struct gfar_private *priv)
278 gfar_configure_coalescing(priv, 0xFF, 0xFF);
281 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
283 struct gfar_private *priv = netdev_priv(dev);
284 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
285 unsigned long tx_packets = 0, tx_bytes = 0;
288 for (i = 0; i < priv->num_rx_queues; i++) {
289 rx_packets += priv->rx_queue[i]->stats.rx_packets;
290 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
291 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
294 dev->stats.rx_packets = rx_packets;
295 dev->stats.rx_bytes = rx_bytes;
296 dev->stats.rx_dropped = rx_dropped;
298 for (i = 0; i < priv->num_tx_queues; i++) {
299 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
300 tx_packets += priv->tx_queue[i]->stats.tx_packets;
303 dev->stats.tx_bytes = tx_bytes;
304 dev->stats.tx_packets = tx_packets;
309 /* Set the appropriate hash bit for the given addr */
310 /* The algorithm works like so:
311 * 1) Take the Destination Address (ie the multicast address), and
312 * do a CRC on it (little endian), and reverse the bits of the
314 * 2) Use the 8 most significant bits as a hash into a 256-entry
315 * table. The table is controlled through 8 32-bit registers:
316 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
317 * gaddr7. This means that the 3 most significant bits in the
318 * hash index which gaddr register to use, and the 5 other bits
319 * indicate which bit (assuming an IBM numbering scheme, which
320 * for PowerPC (tm) is usually the case) in the register holds
323 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
326 struct gfar_private *priv = netdev_priv(dev);
327 u32 result = ether_crc(ETH_ALEN, addr);
328 int width = priv->hash_width;
329 u8 whichbit = (result >> (32 - width)) & 0x1f;
330 u8 whichreg = result >> (32 - width + 5);
331 u32 value = (1 << (31-whichbit));
333 tempval = gfar_read(priv->hash_regs[whichreg]);
335 gfar_write(priv->hash_regs[whichreg], tempval);
338 /* There are multiple MAC Address register pairs on some controllers
339 * This function sets the numth pair to a given address
341 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
344 struct gfar_private *priv = netdev_priv(dev);
345 struct gfar __iomem *regs = priv->gfargrp[0].regs;
347 u32 __iomem *macptr = ®s->macstnaddr1;
351 /* For a station address of 0x12345678ABCD in transmission
352 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
353 * MACnADDR2 is set to 0x34120000.
355 tempval = (addr[5] << 24) | (addr[4] << 16) |
356 (addr[3] << 8) | addr[2];
358 gfar_write(macptr, tempval);
360 tempval = (addr[1] << 24) | (addr[0] << 16);
362 gfar_write(macptr+1, tempval);
365 static int gfar_set_mac_addr(struct net_device *dev, void *p)
367 eth_mac_addr(dev, p);
369 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
374 static void gfar_ints_disable(struct gfar_private *priv)
377 for (i = 0; i < priv->num_grps; i++) {
378 struct gfar __iomem *regs = priv->gfargrp[i].regs;
380 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
382 /* Initialize IMASK */
383 gfar_write(®s->imask, IMASK_INIT_CLEAR);
387 static void gfar_ints_enable(struct gfar_private *priv)
390 for (i = 0; i < priv->num_grps; i++) {
391 struct gfar __iomem *regs = priv->gfargrp[i].regs;
392 /* Unmask the interrupts we look for */
393 gfar_write(®s->imask, IMASK_DEFAULT);
397 static int gfar_alloc_tx_queues(struct gfar_private *priv)
401 for (i = 0; i < priv->num_tx_queues; i++) {
402 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
404 if (!priv->tx_queue[i])
407 priv->tx_queue[i]->tx_skbuff = NULL;
408 priv->tx_queue[i]->qindex = i;
409 priv->tx_queue[i]->dev = priv->ndev;
410 spin_lock_init(&(priv->tx_queue[i]->txlock));
415 static int gfar_alloc_rx_queues(struct gfar_private *priv)
419 for (i = 0; i < priv->num_rx_queues; i++) {
420 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
422 if (!priv->rx_queue[i])
425 priv->rx_queue[i]->qindex = i;
426 priv->rx_queue[i]->ndev = priv->ndev;
431 static void gfar_free_tx_queues(struct gfar_private *priv)
435 for (i = 0; i < priv->num_tx_queues; i++)
436 kfree(priv->tx_queue[i]);
439 static void gfar_free_rx_queues(struct gfar_private *priv)
443 for (i = 0; i < priv->num_rx_queues; i++)
444 kfree(priv->rx_queue[i]);
447 static void unmap_group_regs(struct gfar_private *priv)
451 for (i = 0; i < MAXGROUPS; i++)
452 if (priv->gfargrp[i].regs)
453 iounmap(priv->gfargrp[i].regs);
456 static void free_gfar_dev(struct gfar_private *priv)
460 for (i = 0; i < priv->num_grps; i++)
461 for (j = 0; j < GFAR_NUM_IRQS; j++) {
462 kfree(priv->gfargrp[i].irqinfo[j]);
463 priv->gfargrp[i].irqinfo[j] = NULL;
466 free_netdev(priv->ndev);
469 static void disable_napi(struct gfar_private *priv)
473 for (i = 0; i < priv->num_grps; i++) {
474 napi_disable(&priv->gfargrp[i].napi_rx);
475 napi_disable(&priv->gfargrp[i].napi_tx);
479 static void enable_napi(struct gfar_private *priv)
483 for (i = 0; i < priv->num_grps; i++) {
484 napi_enable(&priv->gfargrp[i].napi_rx);
485 napi_enable(&priv->gfargrp[i].napi_tx);
489 static int gfar_parse_group(struct device_node *np,
490 struct gfar_private *priv, const char *model)
492 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
495 for (i = 0; i < GFAR_NUM_IRQS; i++) {
496 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
498 if (!grp->irqinfo[i])
502 grp->regs = of_iomap(np, 0);
506 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
508 /* If we aren't the FEC we have multiple interrupts */
509 if (model && strcasecmp(model, "FEC")) {
510 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
511 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
512 if (!gfar_irq(grp, TX)->irq ||
513 !gfar_irq(grp, RX)->irq ||
514 !gfar_irq(grp, ER)->irq)
519 spin_lock_init(&grp->grplock);
520 if (priv->mode == MQ_MG_MODE) {
521 u32 rxq_mask, txq_mask;
524 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
525 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
527 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
529 grp->rx_bit_map = rxq_mask ?
530 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
533 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
535 grp->tx_bit_map = txq_mask ?
536 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
539 if (priv->poll_mode == GFAR_SQ_POLLING) {
540 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
541 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
542 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
545 grp->rx_bit_map = 0xFF;
546 grp->tx_bit_map = 0xFF;
549 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
550 * right to left, so we need to revert the 8 bits to get the q index
552 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
553 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
555 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
556 * also assign queues to groups
558 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
560 grp->rx_queue = priv->rx_queue[i];
561 grp->num_rx_queues++;
562 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
563 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
564 priv->rx_queue[i]->grp = grp;
567 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
569 grp->tx_queue = priv->tx_queue[i];
570 grp->num_tx_queues++;
571 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
572 priv->tqueue |= (TQUEUE_EN0 >> i);
573 priv->tx_queue[i]->grp = grp;
581 static int gfar_of_group_count(struct device_node *np)
583 struct device_node *child;
586 for_each_available_child_of_node(np, child)
587 if (of_node_name_eq(child, "queue-group"))
593 /* Reads the controller's registers to determine what interface
594 * connects it to the PHY.
596 static phy_interface_t gfar_get_interface(struct net_device *dev)
598 struct gfar_private *priv = netdev_priv(dev);
599 struct gfar __iomem *regs = priv->gfargrp[0].regs;
602 ecntrl = gfar_read(®s->ecntrl);
604 if (ecntrl & ECNTRL_SGMII_MODE)
605 return PHY_INTERFACE_MODE_SGMII;
607 if (ecntrl & ECNTRL_TBI_MODE) {
608 if (ecntrl & ECNTRL_REDUCED_MODE)
609 return PHY_INTERFACE_MODE_RTBI;
611 return PHY_INTERFACE_MODE_TBI;
614 if (ecntrl & ECNTRL_REDUCED_MODE) {
615 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
616 return PHY_INTERFACE_MODE_RMII;
619 phy_interface_t interface = priv->interface;
621 /* This isn't autodetected right now, so it must
622 * be set by the device tree or platform code.
624 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
625 return PHY_INTERFACE_MODE_RGMII_ID;
627 return PHY_INTERFACE_MODE_RGMII;
631 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
632 return PHY_INTERFACE_MODE_GMII;
634 return PHY_INTERFACE_MODE_MII;
637 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
640 const void *mac_addr;
642 phy_interface_t interface;
643 struct net_device *dev = NULL;
644 struct gfar_private *priv = NULL;
645 struct device_node *np = ofdev->dev.of_node;
646 struct device_node *child = NULL;
649 unsigned int num_tx_qs, num_rx_qs;
650 unsigned short mode, poll_mode;
655 if (of_device_is_compatible(np, "fsl,etsec2")) {
657 poll_mode = GFAR_SQ_POLLING;
660 poll_mode = GFAR_SQ_POLLING;
663 if (mode == SQ_SG_MODE) {
666 } else { /* MQ_MG_MODE */
667 /* get the actual number of supported groups */
668 unsigned int num_grps = gfar_of_group_count(np);
670 if (num_grps == 0 || num_grps > MAXGROUPS) {
671 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
673 pr_err("Cannot do alloc_etherdev, aborting\n");
677 if (poll_mode == GFAR_SQ_POLLING) {
678 num_tx_qs = num_grps; /* one txq per int group */
679 num_rx_qs = num_grps; /* one rxq per int group */
680 } else { /* GFAR_MQ_POLLING */
681 u32 tx_queues, rx_queues;
684 /* parse the num of HW tx and rx queues */
685 ret = of_property_read_u32(np, "fsl,num_tx_queues",
687 num_tx_qs = ret ? 1 : tx_queues;
689 ret = of_property_read_u32(np, "fsl,num_rx_queues",
691 num_rx_qs = ret ? 1 : rx_queues;
695 if (num_tx_qs > MAX_TX_QS) {
696 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
697 num_tx_qs, MAX_TX_QS);
698 pr_err("Cannot do alloc_etherdev, aborting\n");
702 if (num_rx_qs > MAX_RX_QS) {
703 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
704 num_rx_qs, MAX_RX_QS);
705 pr_err("Cannot do alloc_etherdev, aborting\n");
709 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
714 priv = netdev_priv(dev);
718 priv->poll_mode = poll_mode;
720 priv->num_tx_queues = num_tx_qs;
721 netif_set_real_num_rx_queues(dev, num_rx_qs);
722 priv->num_rx_queues = num_rx_qs;
724 err = gfar_alloc_tx_queues(priv);
726 goto tx_alloc_failed;
728 err = gfar_alloc_rx_queues(priv);
730 goto rx_alloc_failed;
732 err = of_property_read_string(np, "model", &model);
734 pr_err("Device model property missing, aborting\n");
735 goto rx_alloc_failed;
738 /* Init Rx queue filer rule set linked list */
739 INIT_LIST_HEAD(&priv->rx_list.list);
740 priv->rx_list.count = 0;
741 mutex_init(&priv->rx_queue_access);
743 for (i = 0; i < MAXGROUPS; i++)
744 priv->gfargrp[i].regs = NULL;
746 /* Parse and initialize group specific information */
747 if (priv->mode == MQ_MG_MODE) {
748 for_each_available_child_of_node(np, child) {
749 if (!of_node_name_eq(child, "queue-group"))
752 err = gfar_parse_group(child, priv, model);
756 } else { /* SQ_SG_MODE */
757 err = gfar_parse_group(np, priv, model);
762 if (of_property_read_bool(np, "bd-stash")) {
763 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
764 priv->bd_stash_en = 1;
767 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
770 priv->rx_stash_size = stash_len;
772 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
775 priv->rx_stash_index = stash_idx;
777 if (stash_len || stash_idx)
778 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
780 mac_addr = of_get_mac_address(np);
782 if (!IS_ERR(mac_addr)) {
783 ether_addr_copy(dev->dev_addr, mac_addr);
785 eth_hw_addr_random(dev);
786 dev_info(&ofdev->dev, "Using random MAC address: %pM\n", dev->dev_addr);
789 if (model && !strcasecmp(model, "TSEC"))
790 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
791 FSL_GIANFAR_DEV_HAS_COALESCE |
792 FSL_GIANFAR_DEV_HAS_RMON |
793 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
795 if (model && !strcasecmp(model, "eTSEC"))
796 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
797 FSL_GIANFAR_DEV_HAS_COALESCE |
798 FSL_GIANFAR_DEV_HAS_RMON |
799 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
800 FSL_GIANFAR_DEV_HAS_CSUM |
801 FSL_GIANFAR_DEV_HAS_VLAN |
802 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
803 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
804 FSL_GIANFAR_DEV_HAS_TIMER |
805 FSL_GIANFAR_DEV_HAS_RX_FILER;
807 /* Use PHY connection type from the DT node if one is specified there.
808 * rgmii-id really needs to be specified. Other types can be
809 * detected by hardware
811 err = of_get_phy_mode(np, &interface);
813 priv->interface = interface;
815 priv->interface = gfar_get_interface(dev);
817 if (of_find_property(np, "fsl,magic-packet", NULL))
818 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
820 if (of_get_property(np, "fsl,wake-on-filer", NULL))
821 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
823 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
825 /* In the case of a fixed PHY, the DT node associated
826 * to the PHY is the Ethernet MAC DT node.
828 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
829 err = of_phy_register_fixed_link(np);
833 priv->phy_node = of_node_get(np);
836 /* Find the TBI PHY. If it's not there, we don't support SGMII */
837 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
842 unmap_group_regs(priv);
844 gfar_free_rx_queues(priv);
846 gfar_free_tx_queues(priv);
851 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
854 u32 rqfpr = FPR_FILER_MASK;
858 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
859 priv->ftp_rqfpr[rqfar] = rqfpr;
860 priv->ftp_rqfcr[rqfar] = rqfcr;
861 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
864 rqfcr = RQFCR_CMP_NOMATCH;
865 priv->ftp_rqfpr[rqfar] = rqfpr;
866 priv->ftp_rqfcr[rqfar] = rqfcr;
867 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
870 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
872 priv->ftp_rqfcr[rqfar] = rqfcr;
873 priv->ftp_rqfpr[rqfar] = rqfpr;
874 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
877 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
879 priv->ftp_rqfcr[rqfar] = rqfcr;
880 priv->ftp_rqfpr[rqfar] = rqfpr;
881 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
886 static void gfar_init_filer_table(struct gfar_private *priv)
889 u32 rqfar = MAX_FILER_IDX;
891 u32 rqfpr = FPR_FILER_MASK;
894 rqfcr = RQFCR_CMP_MATCH;
895 priv->ftp_rqfcr[rqfar] = rqfcr;
896 priv->ftp_rqfpr[rqfar] = rqfpr;
897 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
900 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
901 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
902 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
903 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
904 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
906 /* cur_filer_idx indicated the first non-masked rule */
907 priv->cur_filer_idx = rqfar;
909 /* Rest are masked rules */
910 rqfcr = RQFCR_CMP_NOMATCH;
911 for (i = 0; i < rqfar; i++) {
912 priv->ftp_rqfcr[i] = rqfcr;
913 priv->ftp_rqfpr[i] = rqfpr;
914 gfar_write_filer(priv, i, rqfcr, rqfpr);
919 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
921 unsigned int pvr = mfspr(SPRN_PVR);
922 unsigned int svr = mfspr(SPRN_SVR);
923 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
924 unsigned int rev = svr & 0xffff;
926 /* MPC8313 Rev 2.0 and higher; All MPC837x */
927 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
928 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
929 priv->errata |= GFAR_ERRATA_74;
931 /* MPC8313 and MPC837x all rev */
932 if ((pvr == 0x80850010 && mod == 0x80b0) ||
933 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
934 priv->errata |= GFAR_ERRATA_76;
936 /* MPC8313 Rev < 2.0 */
937 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
938 priv->errata |= GFAR_ERRATA_12;
941 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
943 unsigned int svr = mfspr(SPRN_SVR);
945 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
946 priv->errata |= GFAR_ERRATA_12;
947 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
948 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
949 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
950 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
951 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
955 static void gfar_detect_errata(struct gfar_private *priv)
957 struct device *dev = &priv->ofdev->dev;
959 /* no plans to fix */
960 priv->errata |= GFAR_ERRATA_A002;
963 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
964 __gfar_detect_errata_85xx(priv);
965 else /* non-mpc85xx parts, i.e. e300 core based */
966 __gfar_detect_errata_83xx(priv);
970 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
974 static void gfar_init_addr_hash_table(struct gfar_private *priv)
976 struct gfar __iomem *regs = priv->gfargrp[0].regs;
978 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
979 priv->extended_hash = 1;
980 priv->hash_width = 9;
982 priv->hash_regs[0] = ®s->igaddr0;
983 priv->hash_regs[1] = ®s->igaddr1;
984 priv->hash_regs[2] = ®s->igaddr2;
985 priv->hash_regs[3] = ®s->igaddr3;
986 priv->hash_regs[4] = ®s->igaddr4;
987 priv->hash_regs[5] = ®s->igaddr5;
988 priv->hash_regs[6] = ®s->igaddr6;
989 priv->hash_regs[7] = ®s->igaddr7;
990 priv->hash_regs[8] = ®s->gaddr0;
991 priv->hash_regs[9] = ®s->gaddr1;
992 priv->hash_regs[10] = ®s->gaddr2;
993 priv->hash_regs[11] = ®s->gaddr3;
994 priv->hash_regs[12] = ®s->gaddr4;
995 priv->hash_regs[13] = ®s->gaddr5;
996 priv->hash_regs[14] = ®s->gaddr6;
997 priv->hash_regs[15] = ®s->gaddr7;
1000 priv->extended_hash = 0;
1001 priv->hash_width = 8;
1003 priv->hash_regs[0] = ®s->gaddr0;
1004 priv->hash_regs[1] = ®s->gaddr1;
1005 priv->hash_regs[2] = ®s->gaddr2;
1006 priv->hash_regs[3] = ®s->gaddr3;
1007 priv->hash_regs[4] = ®s->gaddr4;
1008 priv->hash_regs[5] = ®s->gaddr5;
1009 priv->hash_regs[6] = ®s->gaddr6;
1010 priv->hash_regs[7] = ®s->gaddr7;
1014 static int __gfar_is_rx_idle(struct gfar_private *priv)
1018 /* Normaly TSEC should not hang on GRS commands, so we should
1019 * actually wait for IEVENT_GRSC flag.
1021 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1024 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1025 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1026 * and the Rx can be safely reset.
1028 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1030 if ((res & 0xffff) == (res >> 16))
1036 /* Halt the receive and transmit queues */
1037 static void gfar_halt_nodisable(struct gfar_private *priv)
1039 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1041 unsigned int timeout;
1044 gfar_ints_disable(priv);
1046 if (gfar_is_dma_stopped(priv))
1049 /* Stop the DMA, and wait for it to stop */
1050 tempval = gfar_read(®s->dmactrl);
1051 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1052 gfar_write(®s->dmactrl, tempval);
1056 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1062 stopped = gfar_is_dma_stopped(priv);
1064 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1065 !__gfar_is_rx_idle(priv))
1069 /* Halt the receive and transmit queues */
1070 static void gfar_halt(struct gfar_private *priv)
1072 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1075 /* Dissable the Rx/Tx hw queues */
1076 gfar_write(®s->rqueue, 0);
1077 gfar_write(®s->tqueue, 0);
1081 gfar_halt_nodisable(priv);
1083 /* Disable Rx/Tx DMA */
1084 tempval = gfar_read(®s->maccfg1);
1085 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1086 gfar_write(®s->maccfg1, tempval);
1089 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1091 struct txbd8 *txbdp;
1092 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1095 txbdp = tx_queue->tx_bd_base;
1097 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1098 if (!tx_queue->tx_skbuff[i])
1101 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1102 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1104 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1107 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1108 be16_to_cpu(txbdp->length),
1112 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1113 tx_queue->tx_skbuff[i] = NULL;
1115 kfree(tx_queue->tx_skbuff);
1116 tx_queue->tx_skbuff = NULL;
1119 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1123 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1125 dev_kfree_skb(rx_queue->skb);
1127 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1128 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1137 dma_unmap_page(rx_queue->dev, rxb->dma,
1138 PAGE_SIZE, DMA_FROM_DEVICE);
1139 __free_page(rxb->page);
1144 kfree(rx_queue->rx_buff);
1145 rx_queue->rx_buff = NULL;
1148 /* If there are any tx skbs or rx skbs still around, free them.
1149 * Then free tx_skbuff and rx_skbuff
1151 static void free_skb_resources(struct gfar_private *priv)
1153 struct gfar_priv_tx_q *tx_queue = NULL;
1154 struct gfar_priv_rx_q *rx_queue = NULL;
1157 /* Go through all the buffer descriptors and free their data buffers */
1158 for (i = 0; i < priv->num_tx_queues; i++) {
1159 struct netdev_queue *txq;
1161 tx_queue = priv->tx_queue[i];
1162 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1163 if (tx_queue->tx_skbuff)
1164 free_skb_tx_queue(tx_queue);
1165 netdev_tx_reset_queue(txq);
1168 for (i = 0; i < priv->num_rx_queues; i++) {
1169 rx_queue = priv->rx_queue[i];
1170 if (rx_queue->rx_buff)
1171 free_skb_rx_queue(rx_queue);
1174 dma_free_coherent(priv->dev,
1175 sizeof(struct txbd8) * priv->total_tx_ring_size +
1176 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1177 priv->tx_queue[0]->tx_bd_base,
1178 priv->tx_queue[0]->tx_bd_dma_base);
1181 void stop_gfar(struct net_device *dev)
1183 struct gfar_private *priv = netdev_priv(dev);
1185 netif_tx_stop_all_queues(dev);
1187 smp_mb__before_atomic();
1188 set_bit(GFAR_DOWN, &priv->state);
1189 smp_mb__after_atomic();
1193 /* disable ints and gracefully shut down Rx/Tx DMA */
1196 phy_stop(dev->phydev);
1198 free_skb_resources(priv);
1201 static void gfar_start(struct gfar_private *priv)
1203 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1207 /* Enable Rx/Tx hw queues */
1208 gfar_write(®s->rqueue, priv->rqueue);
1209 gfar_write(®s->tqueue, priv->tqueue);
1211 /* Initialize DMACTRL to have WWR and WOP */
1212 tempval = gfar_read(®s->dmactrl);
1213 tempval |= DMACTRL_INIT_SETTINGS;
1214 gfar_write(®s->dmactrl, tempval);
1216 /* Make sure we aren't stopped */
1217 tempval = gfar_read(®s->dmactrl);
1218 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1219 gfar_write(®s->dmactrl, tempval);
1221 for (i = 0; i < priv->num_grps; i++) {
1222 regs = priv->gfargrp[i].regs;
1223 /* Clear THLT/RHLT, so that the DMA starts polling now */
1224 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1225 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1228 /* Enable Rx/Tx DMA */
1229 tempval = gfar_read(®s->maccfg1);
1230 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1231 gfar_write(®s->maccfg1, tempval);
1233 gfar_ints_enable(priv);
1235 netif_trans_update(priv->ndev); /* prevent tx timeout */
1238 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1243 page = dev_alloc_page();
1244 if (unlikely(!page))
1247 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1248 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
1256 rxb->page_offset = 0;
1261 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
1263 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1264 struct gfar_extra_stats *estats = &priv->extra_stats;
1266 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
1267 atomic64_inc(&estats->rx_alloc_err);
1270 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
1274 struct gfar_rx_buff *rxb;
1277 i = rx_queue->next_to_use;
1278 bdp = &rx_queue->rx_bd_base[i];
1279 rxb = &rx_queue->rx_buff[i];
1281 while (alloc_cnt--) {
1282 /* try reuse page */
1283 if (unlikely(!rxb->page)) {
1284 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
1285 gfar_rx_alloc_err(rx_queue);
1290 /* Setup the new RxBD */
1291 gfar_init_rxbdp(rx_queue, bdp,
1292 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
1294 /* Update to the next pointer */
1298 if (unlikely(++i == rx_queue->rx_ring_size)) {
1300 bdp = rx_queue->rx_bd_base;
1301 rxb = rx_queue->rx_buff;
1305 rx_queue->next_to_use = i;
1306 rx_queue->next_to_alloc = i;
1309 static void gfar_init_bds(struct net_device *ndev)
1311 struct gfar_private *priv = netdev_priv(ndev);
1312 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1313 struct gfar_priv_tx_q *tx_queue = NULL;
1314 struct gfar_priv_rx_q *rx_queue = NULL;
1315 struct txbd8 *txbdp;
1316 u32 __iomem *rfbptr;
1319 for (i = 0; i < priv->num_tx_queues; i++) {
1320 tx_queue = priv->tx_queue[i];
1321 /* Initialize some variables in our dev structure */
1322 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
1323 tx_queue->dirty_tx = tx_queue->tx_bd_base;
1324 tx_queue->cur_tx = tx_queue->tx_bd_base;
1325 tx_queue->skb_curtx = 0;
1326 tx_queue->skb_dirtytx = 0;
1328 /* Initialize Transmit Descriptor Ring */
1329 txbdp = tx_queue->tx_bd_base;
1330 for (j = 0; j < tx_queue->tx_ring_size; j++) {
1336 /* Set the last descriptor in the ring to indicate wrap */
1338 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
1342 rfbptr = ®s->rfbptr0;
1343 for (i = 0; i < priv->num_rx_queues; i++) {
1344 rx_queue = priv->rx_queue[i];
1346 rx_queue->next_to_clean = 0;
1347 rx_queue->next_to_use = 0;
1348 rx_queue->next_to_alloc = 0;
1350 /* make sure next_to_clean != next_to_use after this
1351 * by leaving at least 1 unused descriptor
1353 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
1355 rx_queue->rfbptr = rfbptr;
1360 static int gfar_alloc_skb_resources(struct net_device *ndev)
1365 struct gfar_private *priv = netdev_priv(ndev);
1366 struct device *dev = priv->dev;
1367 struct gfar_priv_tx_q *tx_queue = NULL;
1368 struct gfar_priv_rx_q *rx_queue = NULL;
1370 priv->total_tx_ring_size = 0;
1371 for (i = 0; i < priv->num_tx_queues; i++)
1372 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
1374 priv->total_rx_ring_size = 0;
1375 for (i = 0; i < priv->num_rx_queues; i++)
1376 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
1378 /* Allocate memory for the buffer descriptors */
1379 vaddr = dma_alloc_coherent(dev,
1380 (priv->total_tx_ring_size *
1381 sizeof(struct txbd8)) +
1382 (priv->total_rx_ring_size *
1383 sizeof(struct rxbd8)),
1388 for (i = 0; i < priv->num_tx_queues; i++) {
1389 tx_queue = priv->tx_queue[i];
1390 tx_queue->tx_bd_base = vaddr;
1391 tx_queue->tx_bd_dma_base = addr;
1392 tx_queue->dev = ndev;
1393 /* enet DMA only understands physical addresses */
1394 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1395 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1398 /* Start the rx descriptor ring where the tx ring leaves off */
1399 for (i = 0; i < priv->num_rx_queues; i++) {
1400 rx_queue = priv->rx_queue[i];
1401 rx_queue->rx_bd_base = vaddr;
1402 rx_queue->rx_bd_dma_base = addr;
1403 rx_queue->ndev = ndev;
1404 rx_queue->dev = dev;
1405 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1406 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1409 /* Setup the skbuff rings */
1410 for (i = 0; i < priv->num_tx_queues; i++) {
1411 tx_queue = priv->tx_queue[i];
1412 tx_queue->tx_skbuff =
1413 kmalloc_array(tx_queue->tx_ring_size,
1414 sizeof(*tx_queue->tx_skbuff),
1416 if (!tx_queue->tx_skbuff)
1419 for (j = 0; j < tx_queue->tx_ring_size; j++)
1420 tx_queue->tx_skbuff[j] = NULL;
1423 for (i = 0; i < priv->num_rx_queues; i++) {
1424 rx_queue = priv->rx_queue[i];
1425 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
1426 sizeof(*rx_queue->rx_buff),
1428 if (!rx_queue->rx_buff)
1432 gfar_init_bds(ndev);
1437 free_skb_resources(priv);
1441 /* Bring the controller up and running */
1442 int startup_gfar(struct net_device *ndev)
1444 struct gfar_private *priv = netdev_priv(ndev);
1447 gfar_mac_reset(priv);
1449 err = gfar_alloc_skb_resources(ndev);
1453 gfar_init_tx_rx_base(priv);
1455 smp_mb__before_atomic();
1456 clear_bit(GFAR_DOWN, &priv->state);
1457 smp_mb__after_atomic();
1459 /* Start Rx/Tx DMA and enable the interrupts */
1462 /* force link state update after mac reset */
1465 priv->oldduplex = -1;
1467 phy_start(ndev->phydev);
1471 netif_tx_wake_all_queues(ndev);
1476 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
1478 struct net_device *ndev = priv->ndev;
1479 struct phy_device *phydev = ndev->phydev;
1482 if (!phydev->duplex)
1485 if (!priv->pause_aneg_en) {
1486 if (priv->tx_pause_en)
1487 val |= MACCFG1_TX_FLOW;
1488 if (priv->rx_pause_en)
1489 val |= MACCFG1_RX_FLOW;
1491 u16 lcl_adv, rmt_adv;
1493 /* get link partner capabilities */
1496 rmt_adv = LPA_PAUSE_CAP;
1497 if (phydev->asym_pause)
1498 rmt_adv |= LPA_PAUSE_ASYM;
1500 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1501 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1502 if (flowctrl & FLOW_CTRL_TX)
1503 val |= MACCFG1_TX_FLOW;
1504 if (flowctrl & FLOW_CTRL_RX)
1505 val |= MACCFG1_RX_FLOW;
1511 static noinline void gfar_update_link_state(struct gfar_private *priv)
1513 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1514 struct net_device *ndev = priv->ndev;
1515 struct phy_device *phydev = ndev->phydev;
1516 struct gfar_priv_rx_q *rx_queue = NULL;
1519 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
1523 u32 tempval1 = gfar_read(®s->maccfg1);
1524 u32 tempval = gfar_read(®s->maccfg2);
1525 u32 ecntrl = gfar_read(®s->ecntrl);
1526 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
1528 if (phydev->duplex != priv->oldduplex) {
1529 if (!(phydev->duplex))
1530 tempval &= ~(MACCFG2_FULL_DUPLEX);
1532 tempval |= MACCFG2_FULL_DUPLEX;
1534 priv->oldduplex = phydev->duplex;
1537 if (phydev->speed != priv->oldspeed) {
1538 switch (phydev->speed) {
1541 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1543 ecntrl &= ~(ECNTRL_R100);
1548 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1550 /* Reduced mode distinguishes
1551 * between 10 and 100
1553 if (phydev->speed == SPEED_100)
1554 ecntrl |= ECNTRL_R100;
1556 ecntrl &= ~(ECNTRL_R100);
1559 netif_warn(priv, link, priv->ndev,
1560 "Ack! Speed (%d) is not 10/100/1000!\n",
1565 priv->oldspeed = phydev->speed;
1568 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1569 tempval1 |= gfar_get_flowctrl_cfg(priv);
1571 /* Turn last free buffer recording on */
1572 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
1573 for (i = 0; i < priv->num_rx_queues; i++) {
1576 rx_queue = priv->rx_queue[i];
1577 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
1578 gfar_write(rx_queue->rfbptr, bdp_dma);
1581 priv->tx_actual_en = 1;
1584 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
1585 priv->tx_actual_en = 0;
1587 gfar_write(®s->maccfg1, tempval1);
1588 gfar_write(®s->maccfg2, tempval);
1589 gfar_write(®s->ecntrl, ecntrl);
1594 } else if (priv->oldlink) {
1597 priv->oldduplex = -1;
1600 if (netif_msg_link(priv))
1601 phy_print_status(phydev);
1604 /* Called every time the controller might need to be made
1605 * aware of new link state. The PHY code conveys this
1606 * information through variables in the phydev structure, and this
1607 * function converts those variables into the appropriate
1608 * register values, and can bring down the device if needed.
1610 static void adjust_link(struct net_device *dev)
1612 struct gfar_private *priv = netdev_priv(dev);
1613 struct phy_device *phydev = dev->phydev;
1615 if (unlikely(phydev->link != priv->oldlink ||
1616 (phydev->link && (phydev->duplex != priv->oldduplex ||
1617 phydev->speed != priv->oldspeed))))
1618 gfar_update_link_state(priv);
1621 /* Initialize TBI PHY interface for communicating with the
1622 * SERDES lynx PHY on the chip. We communicate with this PHY
1623 * through the MDIO bus on each controller, treating it as a
1624 * "normal" PHY at the address found in the TBIPA register. We assume
1625 * that the TBIPA register is valid. Either the MDIO bus code will set
1626 * it to a value that doesn't conflict with other PHYs on the bus, or the
1627 * value doesn't matter, as there are no other PHYs on the bus.
1629 static void gfar_configure_serdes(struct net_device *dev)
1631 struct gfar_private *priv = netdev_priv(dev);
1632 struct phy_device *tbiphy;
1634 if (!priv->tbi_node) {
1635 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1636 "device tree specify a tbi-handle\n");
1640 tbiphy = of_phy_find_device(priv->tbi_node);
1642 dev_err(&dev->dev, "error: Could not get TBI device\n");
1646 /* If the link is already up, we must already be ok, and don't need to
1647 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1648 * everything for us? Resetting it takes the link down and requires
1649 * several seconds for it to come back.
1651 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1652 put_device(&tbiphy->mdio.dev);
1656 /* Single clk mode, mii mode off(for serdes communication) */
1657 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1659 phy_write(tbiphy, MII_ADVERTISE,
1660 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1661 ADVERTISE_1000XPSE_ASYM);
1663 phy_write(tbiphy, MII_BMCR,
1664 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1667 put_device(&tbiphy->mdio.dev);
1670 /* Initializes driver's PHY state, and attaches to the PHY.
1671 * Returns 0 on success.
1673 static int init_phy(struct net_device *dev)
1675 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1676 struct gfar_private *priv = netdev_priv(dev);
1677 phy_interface_t interface = priv->interface;
1678 struct phy_device *phydev;
1679 struct ethtool_eee edata;
1681 linkmode_set_bit_array(phy_10_100_features_array,
1682 ARRAY_SIZE(phy_10_100_features_array),
1684 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1685 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1686 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1687 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask);
1691 priv->oldduplex = -1;
1693 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1696 dev_err(&dev->dev, "could not attach to PHY\n");
1700 if (interface == PHY_INTERFACE_MODE_SGMII)
1701 gfar_configure_serdes(dev);
1703 /* Remove any features not supported by the controller */
1704 linkmode_and(phydev->supported, phydev->supported, mask);
1705 linkmode_copy(phydev->advertising, phydev->supported);
1707 /* Add support for flow control */
1708 phy_support_asym_pause(phydev);
1710 /* disable EEE autoneg, EEE not supported by eTSEC */
1711 memset(&edata, 0, sizeof(struct ethtool_eee));
1712 phy_ethtool_set_eee(phydev, &edata);
1717 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1719 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
1721 memset(fcb, 0, GMAC_FCB_LEN);
1726 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1729 /* If we're here, it's a IP packet with a TCP or UDP
1730 * payload. We set it to checksum, using a pseudo-header
1733 u8 flags = TXFCB_DEFAULT;
1735 /* Tell the controller what the protocol is
1736 * And provide the already calculated phcs
1738 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1740 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
1742 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
1744 /* l3os is the distance between the start of the
1745 * frame (skb->data) and the start of the IP hdr.
1746 * l4os is the distance between the start of the
1747 * l3 hdr and the l4 hdr
1749 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
1750 fcb->l4os = skb_network_header_len(skb);
1755 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1757 fcb->flags |= TXFCB_VLN;
1758 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
1761 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1762 struct txbd8 *base, int ring_size)
1764 struct txbd8 *new_bd = bdp + stride;
1766 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1769 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1772 return skip_txbd(bdp, 1, base, ring_size);
1775 /* eTSEC12: csum generation not supported for some fcb offsets */
1776 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
1777 unsigned long fcb_addr)
1779 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
1780 (fcb_addr % 0x20) > 0x18);
1783 /* eTSEC76: csum generation for frames larger than 2500 may
1784 * cause excess delays before start of transmission
1786 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
1789 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
1793 /* This is called by the kernel when a frame is ready for transmission.
1794 * It is pointed to by the dev->hard_start_xmit function pointer
1796 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1798 struct gfar_private *priv = netdev_priv(dev);
1799 struct gfar_priv_tx_q *tx_queue = NULL;
1800 struct netdev_queue *txq;
1801 struct gfar __iomem *regs = NULL;
1802 struct txfcb *fcb = NULL;
1803 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1807 int do_tstamp, do_csum, do_vlan;
1809 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
1811 rq = skb->queue_mapping;
1812 tx_queue = priv->tx_queue[rq];
1813 txq = netdev_get_tx_queue(dev, rq);
1814 base = tx_queue->tx_bd_base;
1815 regs = tx_queue->grp->regs;
1817 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
1818 do_vlan = skb_vlan_tag_present(skb);
1819 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1822 if (do_csum || do_vlan)
1823 fcb_len = GMAC_FCB_LEN;
1825 /* check if time stamp should be generated */
1826 if (unlikely(do_tstamp))
1827 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1829 /* make space for additional header when fcb is needed */
1830 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
1831 struct sk_buff *skb_new;
1833 skb_new = skb_realloc_headroom(skb, fcb_len);
1835 dev->stats.tx_errors++;
1836 dev_kfree_skb_any(skb);
1837 return NETDEV_TX_OK;
1841 skb_set_owner_w(skb_new, skb->sk);
1842 dev_consume_skb_any(skb);
1846 /* total number of fragments in the SKB */
1847 nr_frags = skb_shinfo(skb)->nr_frags;
1849 /* calculate the required number of TxBDs for this skb */
1850 if (unlikely(do_tstamp))
1851 nr_txbds = nr_frags + 2;
1853 nr_txbds = nr_frags + 1;
1855 /* check if there is space to queue this packet */
1856 if (nr_txbds > tx_queue->num_txbdfree) {
1857 /* no space, stop the queue */
1858 netif_tx_stop_queue(txq);
1859 dev->stats.tx_fifo_errors++;
1860 return NETDEV_TX_BUSY;
1863 /* Update transmit stats */
1864 bytes_sent = skb->len;
1865 tx_queue->stats.tx_bytes += bytes_sent;
1866 /* keep Tx bytes on wire for BQL accounting */
1867 GFAR_CB(skb)->bytes_sent = bytes_sent;
1868 tx_queue->stats.tx_packets++;
1870 txbdp = txbdp_start = tx_queue->cur_tx;
1871 lstatus = be32_to_cpu(txbdp->lstatus);
1873 /* Add TxPAL between FCB and frame if required */
1874 if (unlikely(do_tstamp)) {
1875 skb_push(skb, GMAC_TXPAL_LEN);
1876 memset(skb->data, 0, GMAC_TXPAL_LEN);
1879 /* Add TxFCB if required */
1881 fcb = gfar_add_fcb(skb);
1882 lstatus |= BD_LFLAG(TXBD_TOE);
1885 /* Set up checksumming */
1887 gfar_tx_checksum(skb, fcb, fcb_len);
1889 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
1890 unlikely(gfar_csum_errata_76(priv, skb->len))) {
1891 __skb_pull(skb, GMAC_FCB_LEN);
1892 skb_checksum_help(skb);
1893 if (do_vlan || do_tstamp) {
1894 /* put back a new fcb for vlan/tstamp TOE */
1895 fcb = gfar_add_fcb(skb);
1897 /* Tx TOE not used */
1898 lstatus &= ~(BD_LFLAG(TXBD_TOE));
1905 gfar_tx_vlan(skb, fcb);
1907 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
1909 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1912 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1914 /* Time stamp insertion requires one additional TxBD */
1915 if (unlikely(do_tstamp))
1916 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
1917 tx_queue->tx_ring_size);
1919 if (likely(!nr_frags)) {
1920 if (likely(!do_tstamp))
1921 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1923 u32 lstatus_start = lstatus;
1925 /* Place the fragment addresses and lengths into the TxBDs */
1926 frag = &skb_shinfo(skb)->frags[0];
1927 for (i = 0; i < nr_frags; i++, frag++) {
1930 /* Point at the next BD, wrapping as needed */
1931 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1933 size = skb_frag_size(frag);
1935 lstatus = be32_to_cpu(txbdp->lstatus) | size |
1936 BD_LFLAG(TXBD_READY);
1938 /* Handle the last BD specially */
1939 if (i == nr_frags - 1)
1940 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1942 bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
1943 size, DMA_TO_DEVICE);
1944 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1947 /* set the TxBD length and buffer pointer */
1948 txbdp->bufPtr = cpu_to_be32(bufaddr);
1949 txbdp->lstatus = cpu_to_be32(lstatus);
1952 lstatus = lstatus_start;
1955 /* If time stamping is requested one additional TxBD must be set up. The
1956 * first TxBD points to the FCB and must have a data length of
1957 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
1958 * the full frame length.
1960 if (unlikely(do_tstamp)) {
1961 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
1963 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
1966 lstatus_ts |= BD_LFLAG(TXBD_READY) |
1967 (skb_headlen(skb) - fcb_len);
1969 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1971 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
1972 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
1973 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
1975 /* Setup tx hardware time stamping */
1976 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1979 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1982 netdev_tx_sent_queue(txq, bytes_sent);
1986 txbdp_start->lstatus = cpu_to_be32(lstatus);
1988 gfar_wmb(); /* force lstatus write before tx_skbuff */
1990 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1992 /* Update the current skb pointer to the next entry we will use
1993 * (wrapping if necessary)
1995 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1996 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1998 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2000 /* We can work in parallel with gfar_clean_tx_ring(), except
2001 * when modifying num_txbdfree. Note that we didn't grab the lock
2002 * when we were reading the num_txbdfree and checking for available
2003 * space, that's because outside of this function it can only grow.
2005 spin_lock_bh(&tx_queue->txlock);
2006 /* reduce TxBD free count */
2007 tx_queue->num_txbdfree -= (nr_txbds);
2008 spin_unlock_bh(&tx_queue->txlock);
2010 /* If the next BD still needs to be cleaned up, then the bds
2011 * are full. We need to tell the kernel to stop sending us stuff.
2013 if (!tx_queue->num_txbdfree) {
2014 netif_tx_stop_queue(txq);
2016 dev->stats.tx_fifo_errors++;
2019 /* Tell the DMA to go go go */
2020 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2022 return NETDEV_TX_OK;
2025 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2027 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2028 for (i = 0; i < nr_frags; i++) {
2029 lstatus = be32_to_cpu(txbdp->lstatus);
2030 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2033 lstatus &= ~BD_LFLAG(TXBD_READY);
2034 txbdp->lstatus = cpu_to_be32(lstatus);
2035 bufaddr = be32_to_cpu(txbdp->bufPtr);
2036 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2038 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2041 dev_kfree_skb_any(skb);
2042 return NETDEV_TX_OK;
2045 /* Changes the mac address if the controller is not running. */
2046 static int gfar_set_mac_address(struct net_device *dev)
2048 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2053 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2055 struct gfar_private *priv = netdev_priv(dev);
2057 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2060 if (dev->flags & IFF_UP)
2065 if (dev->flags & IFF_UP)
2068 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2073 static void reset_gfar(struct net_device *ndev)
2075 struct gfar_private *priv = netdev_priv(ndev);
2077 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2083 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2086 /* gfar_reset_task gets scheduled when a packet has not been
2087 * transmitted after a set amount of time.
2088 * For now, assume that clearing out all the structures, and
2089 * starting over will fix the problem.
2091 static void gfar_reset_task(struct work_struct *work)
2093 struct gfar_private *priv = container_of(work, struct gfar_private,
2095 reset_gfar(priv->ndev);
2098 static void gfar_timeout(struct net_device *dev, unsigned int txqueue)
2100 struct gfar_private *priv = netdev_priv(dev);
2102 dev->stats.tx_errors++;
2103 schedule_work(&priv->reset_task);
2106 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
2108 struct hwtstamp_config config;
2109 struct gfar_private *priv = netdev_priv(netdev);
2111 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2114 /* reserved for future extensions */
2118 switch (config.tx_type) {
2119 case HWTSTAMP_TX_OFF:
2120 priv->hwts_tx_en = 0;
2122 case HWTSTAMP_TX_ON:
2123 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2125 priv->hwts_tx_en = 1;
2131 switch (config.rx_filter) {
2132 case HWTSTAMP_FILTER_NONE:
2133 if (priv->hwts_rx_en) {
2134 priv->hwts_rx_en = 0;
2139 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2141 if (!priv->hwts_rx_en) {
2142 priv->hwts_rx_en = 1;
2145 config.rx_filter = HWTSTAMP_FILTER_ALL;
2149 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2153 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
2155 struct hwtstamp_config config;
2156 struct gfar_private *priv = netdev_priv(netdev);
2159 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2160 config.rx_filter = (priv->hwts_rx_en ?
2161 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
2163 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2167 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2169 struct phy_device *phydev = dev->phydev;
2171 if (!netif_running(dev))
2174 if (cmd == SIOCSHWTSTAMP)
2175 return gfar_hwtstamp_set(dev, rq);
2176 if (cmd == SIOCGHWTSTAMP)
2177 return gfar_hwtstamp_get(dev, rq);
2182 return phy_mii_ioctl(phydev, rq, cmd);
2185 /* Interrupt Handler for Transmit complete */
2186 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2188 struct net_device *dev = tx_queue->dev;
2189 struct netdev_queue *txq;
2190 struct gfar_private *priv = netdev_priv(dev);
2191 struct txbd8 *bdp, *next = NULL;
2192 struct txbd8 *lbdp = NULL;
2193 struct txbd8 *base = tx_queue->tx_bd_base;
2194 struct sk_buff *skb;
2196 int tx_ring_size = tx_queue->tx_ring_size;
2197 int frags = 0, nr_txbds = 0;
2200 int tqi = tx_queue->qindex;
2201 unsigned int bytes_sent = 0;
2205 txq = netdev_get_tx_queue(dev, tqi);
2206 bdp = tx_queue->dirty_tx;
2207 skb_dirtytx = tx_queue->skb_dirtytx;
2209 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2212 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2215 frags = skb_shinfo(skb)->nr_frags;
2217 /* When time stamping, one additional TxBD must be freed.
2218 * Also, we need to dma_unmap_single() the TxPAL.
2220 if (unlikely(do_tstamp))
2221 nr_txbds = frags + 2;
2223 nr_txbds = frags + 1;
2225 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2227 lstatus = be32_to_cpu(lbdp->lstatus);
2229 /* Only clean completed frames */
2230 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2231 (lstatus & BD_LENGTH_MASK))
2234 if (unlikely(do_tstamp)) {
2235 next = next_txbd(bdp, base, tx_ring_size);
2236 buflen = be16_to_cpu(next->length) +
2237 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2239 buflen = be16_to_cpu(bdp->length);
2241 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2242 buflen, DMA_TO_DEVICE);
2244 if (unlikely(do_tstamp)) {
2245 struct skb_shared_hwtstamps shhwtstamps;
2246 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2249 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2250 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2251 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2252 skb_tstamp_tx(skb, &shhwtstamps);
2253 gfar_clear_txbd_status(bdp);
2257 gfar_clear_txbd_status(bdp);
2258 bdp = next_txbd(bdp, base, tx_ring_size);
2260 for (i = 0; i < frags; i++) {
2261 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2262 be16_to_cpu(bdp->length),
2264 gfar_clear_txbd_status(bdp);
2265 bdp = next_txbd(bdp, base, tx_ring_size);
2268 bytes_sent += GFAR_CB(skb)->bytes_sent;
2270 dev_kfree_skb_any(skb);
2272 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2274 skb_dirtytx = (skb_dirtytx + 1) &
2275 TX_RING_MOD_MASK(tx_ring_size);
2278 spin_lock(&tx_queue->txlock);
2279 tx_queue->num_txbdfree += nr_txbds;
2280 spin_unlock(&tx_queue->txlock);
2283 /* If we freed a buffer, we can restart transmission, if necessary */
2284 if (tx_queue->num_txbdfree &&
2285 netif_tx_queue_stopped(txq) &&
2286 !(test_bit(GFAR_DOWN, &priv->state)))
2287 netif_wake_subqueue(priv->ndev, tqi);
2289 /* Update dirty indicators */
2290 tx_queue->skb_dirtytx = skb_dirtytx;
2291 tx_queue->dirty_tx = bdp;
2293 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2296 static void count_errors(u32 lstatus, struct net_device *ndev)
2298 struct gfar_private *priv = netdev_priv(ndev);
2299 struct net_device_stats *stats = &ndev->stats;
2300 struct gfar_extra_stats *estats = &priv->extra_stats;
2302 /* If the packet was truncated, none of the other errors matter */
2303 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2304 stats->rx_length_errors++;
2306 atomic64_inc(&estats->rx_trunc);
2310 /* Count the errors, if there were any */
2311 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2312 stats->rx_length_errors++;
2314 if (lstatus & BD_LFLAG(RXBD_LARGE))
2315 atomic64_inc(&estats->rx_large);
2317 atomic64_inc(&estats->rx_short);
2319 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2320 stats->rx_frame_errors++;
2321 atomic64_inc(&estats->rx_nonoctet);
2323 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2324 atomic64_inc(&estats->rx_crcerr);
2325 stats->rx_crc_errors++;
2327 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2328 atomic64_inc(&estats->rx_overrun);
2329 stats->rx_over_errors++;
2333 static irqreturn_t gfar_receive(int irq, void *grp_id)
2335 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2336 unsigned long flags;
2339 ievent = gfar_read(&grp->regs->ievent);
2341 if (unlikely(ievent & IEVENT_FGPI)) {
2342 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2346 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2347 spin_lock_irqsave(&grp->grplock, flags);
2348 imask = gfar_read(&grp->regs->imask);
2349 imask &= IMASK_RX_DISABLED;
2350 gfar_write(&grp->regs->imask, imask);
2351 spin_unlock_irqrestore(&grp->grplock, flags);
2352 __napi_schedule(&grp->napi_rx);
2354 /* Clear IEVENT, so interrupts aren't called again
2355 * because of the packets that have already arrived.
2357 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2363 /* Interrupt Handler for Transmit complete */
2364 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2366 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2367 unsigned long flags;
2370 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2371 spin_lock_irqsave(&grp->grplock, flags);
2372 imask = gfar_read(&grp->regs->imask);
2373 imask &= IMASK_TX_DISABLED;
2374 gfar_write(&grp->regs->imask, imask);
2375 spin_unlock_irqrestore(&grp->grplock, flags);
2376 __napi_schedule(&grp->napi_tx);
2378 /* Clear IEVENT, so interrupts aren't called again
2379 * because of the packets that have already arrived.
2381 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2387 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2388 struct sk_buff *skb, bool first)
2390 int size = lstatus & BD_LENGTH_MASK;
2391 struct page *page = rxb->page;
2393 if (likely(first)) {
2396 /* the last fragments' length contains the full frame length */
2397 if (lstatus & BD_LFLAG(RXBD_LAST))
2400 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2401 rxb->page_offset + RXBUF_ALIGNMENT,
2402 size, GFAR_RXB_TRUESIZE);
2405 /* try reuse page */
2406 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2409 /* change offset to the other half */
2410 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2417 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2418 struct gfar_rx_buff *old_rxb)
2420 struct gfar_rx_buff *new_rxb;
2421 u16 nta = rxq->next_to_alloc;
2423 new_rxb = &rxq->rx_buff[nta];
2425 /* find next buf that can reuse a page */
2427 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2429 /* copy page reference */
2430 *new_rxb = *old_rxb;
2432 /* sync for use by the device */
2433 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2434 old_rxb->page_offset,
2435 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2438 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2439 u32 lstatus, struct sk_buff *skb)
2441 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2442 struct page *page = rxb->page;
2446 void *buff_addr = page_address(page) + rxb->page_offset;
2448 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2449 if (unlikely(!skb)) {
2450 gfar_rx_alloc_err(rx_queue);
2453 skb_reserve(skb, RXBUF_ALIGNMENT);
2457 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2458 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2460 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2461 /* reuse the free half of the page */
2462 gfar_reuse_rx_page(rx_queue, rxb);
2464 /* page cannot be reused, unmap it */
2465 dma_unmap_page(rx_queue->dev, rxb->dma,
2466 PAGE_SIZE, DMA_FROM_DEVICE);
2469 /* clear rxb content */
2475 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2477 /* If valid headers were found, and valid sums
2478 * were verified, then we tell the kernel that no
2479 * checksumming is necessary. Otherwise, it is [FIXME]
2481 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2482 (RXFCB_CIP | RXFCB_CTU))
2483 skb->ip_summed = CHECKSUM_UNNECESSARY;
2485 skb_checksum_none_assert(skb);
2488 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2489 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2491 struct gfar_private *priv = netdev_priv(ndev);
2492 struct rxfcb *fcb = NULL;
2494 /* fcb is at the beginning if exists */
2495 fcb = (struct rxfcb *)skb->data;
2497 /* Remove the FCB from the skb
2498 * Remove the padded bytes, if there are any
2500 if (priv->uses_rxfcb)
2501 skb_pull(skb, GMAC_FCB_LEN);
2503 /* Get receive timestamp from the skb */
2504 if (priv->hwts_rx_en) {
2505 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2506 u64 *ns = (u64 *) skb->data;
2508 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2509 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2513 skb_pull(skb, priv->padding);
2515 /* Trim off the FCS */
2516 pskb_trim(skb, skb->len - ETH_FCS_LEN);
2518 if (ndev->features & NETIF_F_RXCSUM)
2519 gfar_rx_checksum(skb, fcb);
2521 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2522 * Even if vlan rx accel is disabled, on some chips
2523 * RXFCB_VLN is pseudo randomly set.
2525 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2526 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2527 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2528 be16_to_cpu(fcb->vlctl));
2531 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2532 * until the budget/quota has been reached. Returns the number
2535 static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
2538 struct net_device *ndev = rx_queue->ndev;
2539 struct gfar_private *priv = netdev_priv(ndev);
2542 struct sk_buff *skb = rx_queue->skb;
2543 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2544 unsigned int total_bytes = 0, total_pkts = 0;
2546 /* Get the first full descriptor */
2547 i = rx_queue->next_to_clean;
2549 while (rx_work_limit--) {
2552 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2553 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2557 bdp = &rx_queue->rx_bd_base[i];
2558 lstatus = be32_to_cpu(bdp->lstatus);
2559 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2562 /* order rx buffer descriptor reads */
2565 /* fetch next to clean buffer from the ring */
2566 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2573 if (unlikely(++i == rx_queue->rx_ring_size))
2576 rx_queue->next_to_clean = i;
2578 /* fetch next buffer if not the last in frame */
2579 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2582 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2583 count_errors(lstatus, ndev);
2585 /* discard faulty buffer */
2588 rx_queue->stats.rx_dropped++;
2592 gfar_process_frame(ndev, skb);
2594 /* Increment the number of packets */
2596 total_bytes += skb->len;
2598 skb_record_rx_queue(skb, rx_queue->qindex);
2600 skb->protocol = eth_type_trans(skb, ndev);
2602 /* Send the packet up the stack */
2603 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2608 /* Store incomplete frames for completion */
2609 rx_queue->skb = skb;
2611 rx_queue->stats.rx_packets += total_pkts;
2612 rx_queue->stats.rx_bytes += total_bytes;
2615 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2617 /* Update Last Free RxBD pointer for LFC */
2618 if (unlikely(priv->tx_actual_en)) {
2619 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
2621 gfar_write(rx_queue->rfbptr, bdp_dma);
2627 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2629 struct gfar_priv_grp *gfargrp =
2630 container_of(napi, struct gfar_priv_grp, napi_rx);
2631 struct gfar __iomem *regs = gfargrp->regs;
2632 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2635 /* Clear IEVENT, so interrupts aren't called again
2636 * because of the packets that have already arrived
2638 gfar_write(®s->ievent, IEVENT_RX_MASK);
2640 work_done = gfar_clean_rx_ring(rx_queue, budget);
2642 if (work_done < budget) {
2644 napi_complete_done(napi, work_done);
2645 /* Clear the halt bit in RSTAT */
2646 gfar_write(®s->rstat, gfargrp->rstat);
2648 spin_lock_irq(&gfargrp->grplock);
2649 imask = gfar_read(®s->imask);
2650 imask |= IMASK_RX_DEFAULT;
2651 gfar_write(®s->imask, imask);
2652 spin_unlock_irq(&gfargrp->grplock);
2658 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2660 struct gfar_priv_grp *gfargrp =
2661 container_of(napi, struct gfar_priv_grp, napi_tx);
2662 struct gfar __iomem *regs = gfargrp->regs;
2663 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2666 /* Clear IEVENT, so interrupts aren't called again
2667 * because of the packets that have already arrived
2669 gfar_write(®s->ievent, IEVENT_TX_MASK);
2671 /* run Tx cleanup to completion */
2672 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2673 gfar_clean_tx_ring(tx_queue);
2675 napi_complete(napi);
2677 spin_lock_irq(&gfargrp->grplock);
2678 imask = gfar_read(®s->imask);
2679 imask |= IMASK_TX_DEFAULT;
2680 gfar_write(®s->imask, imask);
2681 spin_unlock_irq(&gfargrp->grplock);
2686 static int gfar_poll_rx(struct napi_struct *napi, int budget)
2688 struct gfar_priv_grp *gfargrp =
2689 container_of(napi, struct gfar_priv_grp, napi_rx);
2690 struct gfar_private *priv = gfargrp->priv;
2691 struct gfar __iomem *regs = gfargrp->regs;
2692 struct gfar_priv_rx_q *rx_queue = NULL;
2693 int work_done = 0, work_done_per_q = 0;
2694 int i, budget_per_q = 0;
2695 unsigned long rstat_rxf;
2698 /* Clear IEVENT, so interrupts aren't called again
2699 * because of the packets that have already arrived
2701 gfar_write(®s->ievent, IEVENT_RX_MASK);
2703 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
2705 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2707 budget_per_q = budget/num_act_queues;
2709 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2710 /* skip queue if not active */
2711 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2714 rx_queue = priv->rx_queue[i];
2716 gfar_clean_rx_ring(rx_queue, budget_per_q);
2717 work_done += work_done_per_q;
2719 /* finished processing this queue */
2720 if (work_done_per_q < budget_per_q) {
2721 /* clear active queue hw indication */
2722 gfar_write(®s->rstat,
2723 RSTAT_CLEAR_RXF0 >> i);
2726 if (!num_act_queues)
2731 if (!num_act_queues) {
2733 napi_complete_done(napi, work_done);
2735 /* Clear the halt bit in RSTAT */
2736 gfar_write(®s->rstat, gfargrp->rstat);
2738 spin_lock_irq(&gfargrp->grplock);
2739 imask = gfar_read(®s->imask);
2740 imask |= IMASK_RX_DEFAULT;
2741 gfar_write(®s->imask, imask);
2742 spin_unlock_irq(&gfargrp->grplock);
2748 static int gfar_poll_tx(struct napi_struct *napi, int budget)
2750 struct gfar_priv_grp *gfargrp =
2751 container_of(napi, struct gfar_priv_grp, napi_tx);
2752 struct gfar_private *priv = gfargrp->priv;
2753 struct gfar __iomem *regs = gfargrp->regs;
2754 struct gfar_priv_tx_q *tx_queue = NULL;
2755 int has_tx_work = 0;
2758 /* Clear IEVENT, so interrupts aren't called again
2759 * because of the packets that have already arrived
2761 gfar_write(®s->ievent, IEVENT_TX_MASK);
2763 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2764 tx_queue = priv->tx_queue[i];
2765 /* run Tx cleanup to completion */
2766 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2767 gfar_clean_tx_ring(tx_queue);
2774 napi_complete(napi);
2776 spin_lock_irq(&gfargrp->grplock);
2777 imask = gfar_read(®s->imask);
2778 imask |= IMASK_TX_DEFAULT;
2779 gfar_write(®s->imask, imask);
2780 spin_unlock_irq(&gfargrp->grplock);
2786 /* GFAR error interrupt handler */
2787 static irqreturn_t gfar_error(int irq, void *grp_id)
2789 struct gfar_priv_grp *gfargrp = grp_id;
2790 struct gfar __iomem *regs = gfargrp->regs;
2791 struct gfar_private *priv= gfargrp->priv;
2792 struct net_device *dev = priv->ndev;
2794 /* Save ievent for future reference */
2795 u32 events = gfar_read(®s->ievent);
2798 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
2800 /* Magic Packet is not an error. */
2801 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2802 (events & IEVENT_MAG))
2803 events &= ~IEVENT_MAG;
2806 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2808 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
2809 events, gfar_read(®s->imask));
2811 /* Update the error counters */
2812 if (events & IEVENT_TXE) {
2813 dev->stats.tx_errors++;
2815 if (events & IEVENT_LC)
2816 dev->stats.tx_window_errors++;
2817 if (events & IEVENT_CRL)
2818 dev->stats.tx_aborted_errors++;
2819 if (events & IEVENT_XFUN) {
2820 netif_dbg(priv, tx_err, dev,
2821 "TX FIFO underrun, packet dropped\n");
2822 dev->stats.tx_dropped++;
2823 atomic64_inc(&priv->extra_stats.tx_underrun);
2825 schedule_work(&priv->reset_task);
2827 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
2829 if (events & IEVENT_BSY) {
2830 dev->stats.rx_over_errors++;
2831 atomic64_inc(&priv->extra_stats.rx_bsy);
2833 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
2834 gfar_read(®s->rstat));
2836 if (events & IEVENT_BABR) {
2837 dev->stats.rx_errors++;
2838 atomic64_inc(&priv->extra_stats.rx_babr);
2840 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
2842 if (events & IEVENT_EBERR) {
2843 atomic64_inc(&priv->extra_stats.eberr);
2844 netif_dbg(priv, rx_err, dev, "bus error\n");
2846 if (events & IEVENT_RXC)
2847 netif_dbg(priv, rx_status, dev, "control frame\n");
2849 if (events & IEVENT_BABT) {
2850 atomic64_inc(&priv->extra_stats.tx_babt);
2851 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
2856 /* The interrupt handler for devices with one interrupt */
2857 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2859 struct gfar_priv_grp *gfargrp = grp_id;
2861 /* Save ievent for future reference */
2862 u32 events = gfar_read(&gfargrp->regs->ievent);
2864 /* Check for reception */
2865 if (events & IEVENT_RX_MASK)
2866 gfar_receive(irq, grp_id);
2868 /* Check for transmit completion */
2869 if (events & IEVENT_TX_MASK)
2870 gfar_transmit(irq, grp_id);
2872 /* Check for errors */
2873 if (events & IEVENT_ERR_MASK)
2874 gfar_error(irq, grp_id);
2879 #ifdef CONFIG_NET_POLL_CONTROLLER
2880 /* Polling 'interrupt' - used by things like netconsole to send skbs
2881 * without having to re-enable interrupts. It's not called while
2882 * the interrupt routine is executing.
2884 static void gfar_netpoll(struct net_device *dev)
2886 struct gfar_private *priv = netdev_priv(dev);
2889 /* If the device has multiple interrupts, run tx/rx */
2890 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2891 for (i = 0; i < priv->num_grps; i++) {
2892 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2894 disable_irq(gfar_irq(grp, TX)->irq);
2895 disable_irq(gfar_irq(grp, RX)->irq);
2896 disable_irq(gfar_irq(grp, ER)->irq);
2897 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2898 enable_irq(gfar_irq(grp, ER)->irq);
2899 enable_irq(gfar_irq(grp, RX)->irq);
2900 enable_irq(gfar_irq(grp, TX)->irq);
2903 for (i = 0; i < priv->num_grps; i++) {
2904 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2906 disable_irq(gfar_irq(grp, TX)->irq);
2907 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2908 enable_irq(gfar_irq(grp, TX)->irq);
2914 static void free_grp_irqs(struct gfar_priv_grp *grp)
2916 free_irq(gfar_irq(grp, TX)->irq, grp);
2917 free_irq(gfar_irq(grp, RX)->irq, grp);
2918 free_irq(gfar_irq(grp, ER)->irq, grp);
2921 static int register_grp_irqs(struct gfar_priv_grp *grp)
2923 struct gfar_private *priv = grp->priv;
2924 struct net_device *dev = priv->ndev;
2927 /* If the device has multiple interrupts, register for
2928 * them. Otherwise, only register for the one
2930 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2931 /* Install our interrupt handlers for Error,
2932 * Transmit, and Receive
2934 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2935 gfar_irq(grp, ER)->name, grp);
2937 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2938 gfar_irq(grp, ER)->irq);
2942 enable_irq_wake(gfar_irq(grp, ER)->irq);
2944 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2945 gfar_irq(grp, TX)->name, grp);
2947 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2948 gfar_irq(grp, TX)->irq);
2951 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2952 gfar_irq(grp, RX)->name, grp);
2954 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2955 gfar_irq(grp, RX)->irq);
2958 enable_irq_wake(gfar_irq(grp, RX)->irq);
2961 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2962 gfar_irq(grp, TX)->name, grp);
2964 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2965 gfar_irq(grp, TX)->irq);
2968 enable_irq_wake(gfar_irq(grp, TX)->irq);
2974 free_irq(gfar_irq(grp, TX)->irq, grp);
2976 free_irq(gfar_irq(grp, ER)->irq, grp);
2982 static void gfar_free_irq(struct gfar_private *priv)
2987 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2988 for (i = 0; i < priv->num_grps; i++)
2989 free_grp_irqs(&priv->gfargrp[i]);
2991 for (i = 0; i < priv->num_grps; i++)
2992 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2997 static int gfar_request_irq(struct gfar_private *priv)
3001 for (i = 0; i < priv->num_grps; i++) {
3002 err = register_grp_irqs(&priv->gfargrp[i]);
3004 for (j = 0; j < i; j++)
3005 free_grp_irqs(&priv->gfargrp[j]);
3013 /* Called when something needs to use the ethernet device
3014 * Returns 0 for success.
3016 static int gfar_enet_open(struct net_device *dev)
3018 struct gfar_private *priv = netdev_priv(dev);
3021 err = init_phy(dev);
3025 err = gfar_request_irq(priv);
3029 err = startup_gfar(dev);
3036 /* Stops the kernel queue, and halts the controller */
3037 static int gfar_close(struct net_device *dev)
3039 struct gfar_private *priv = netdev_priv(dev);
3041 cancel_work_sync(&priv->reset_task);
3044 /* Disconnect from the PHY */
3045 phy_disconnect(dev->phydev);
3047 gfar_free_irq(priv);
3052 /* Clears each of the exact match registers to zero, so they
3053 * don't interfere with normal reception
3055 static void gfar_clear_exact_match(struct net_device *dev)
3058 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3060 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3061 gfar_set_mac_for_addr(dev, idx, zero_arr);
3064 /* Update the hash table based on the current list of multicast
3065 * addresses we subscribe to. Also, change the promiscuity of
3066 * the device based on the flags (this function is called
3067 * whenever dev->flags is changed
3069 static void gfar_set_multi(struct net_device *dev)
3071 struct netdev_hw_addr *ha;
3072 struct gfar_private *priv = netdev_priv(dev);
3073 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3076 if (dev->flags & IFF_PROMISC) {
3077 /* Set RCTRL to PROM */
3078 tempval = gfar_read(®s->rctrl);
3079 tempval |= RCTRL_PROM;
3080 gfar_write(®s->rctrl, tempval);
3082 /* Set RCTRL to not PROM */
3083 tempval = gfar_read(®s->rctrl);
3084 tempval &= ~(RCTRL_PROM);
3085 gfar_write(®s->rctrl, tempval);
3088 if (dev->flags & IFF_ALLMULTI) {
3089 /* Set the hash to rx all multicast frames */
3090 gfar_write(®s->igaddr0, 0xffffffff);
3091 gfar_write(®s->igaddr1, 0xffffffff);
3092 gfar_write(®s->igaddr2, 0xffffffff);
3093 gfar_write(®s->igaddr3, 0xffffffff);
3094 gfar_write(®s->igaddr4, 0xffffffff);
3095 gfar_write(®s->igaddr5, 0xffffffff);
3096 gfar_write(®s->igaddr6, 0xffffffff);
3097 gfar_write(®s->igaddr7, 0xffffffff);
3098 gfar_write(®s->gaddr0, 0xffffffff);
3099 gfar_write(®s->gaddr1, 0xffffffff);
3100 gfar_write(®s->gaddr2, 0xffffffff);
3101 gfar_write(®s->gaddr3, 0xffffffff);
3102 gfar_write(®s->gaddr4, 0xffffffff);
3103 gfar_write(®s->gaddr5, 0xffffffff);
3104 gfar_write(®s->gaddr6, 0xffffffff);
3105 gfar_write(®s->gaddr7, 0xffffffff);
3110 /* zero out the hash */
3111 gfar_write(®s->igaddr0, 0x0);
3112 gfar_write(®s->igaddr1, 0x0);
3113 gfar_write(®s->igaddr2, 0x0);
3114 gfar_write(®s->igaddr3, 0x0);
3115 gfar_write(®s->igaddr4, 0x0);
3116 gfar_write(®s->igaddr5, 0x0);
3117 gfar_write(®s->igaddr6, 0x0);
3118 gfar_write(®s->igaddr7, 0x0);
3119 gfar_write(®s->gaddr0, 0x0);
3120 gfar_write(®s->gaddr1, 0x0);
3121 gfar_write(®s->gaddr2, 0x0);
3122 gfar_write(®s->gaddr3, 0x0);
3123 gfar_write(®s->gaddr4, 0x0);
3124 gfar_write(®s->gaddr5, 0x0);
3125 gfar_write(®s->gaddr6, 0x0);
3126 gfar_write(®s->gaddr7, 0x0);
3128 /* If we have extended hash tables, we need to
3129 * clear the exact match registers to prepare for
3132 if (priv->extended_hash) {
3133 em_num = GFAR_EM_NUM + 1;
3134 gfar_clear_exact_match(dev);
3141 if (netdev_mc_empty(dev))
3144 /* Parse the list, and set the appropriate bits */
3145 netdev_for_each_mc_addr(ha, dev) {
3147 gfar_set_mac_for_addr(dev, idx, ha->addr);
3150 gfar_set_hash_for_addr(dev, ha->addr);
3155 void gfar_mac_reset(struct gfar_private *priv)
3157 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3160 /* Reset MAC layer */
3161 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
3163 /* We need to delay at least 3 TX clocks */
3166 /* the soft reset bit is not self-resetting, so we need to
3167 * clear it before resuming normal operation
3169 gfar_write(®s->maccfg1, 0);
3173 gfar_rx_offload_en(priv);
3175 /* Initialize the max receive frame/buffer lengths */
3176 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE);
3177 gfar_write(®s->mrblr, GFAR_RXB_SIZE);
3179 /* Initialize the Minimum Frame Length Register */
3180 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
3182 /* Initialize MACCFG2. */
3183 tempval = MACCFG2_INIT_SETTINGS;
3185 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
3186 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1,
3187 * and by checking RxBD[LG] and discarding larger than MAXFRM.
3189 if (gfar_has_errata(priv, GFAR_ERRATA_74))
3190 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
3192 gfar_write(®s->maccfg2, tempval);
3194 /* Clear mac addr hash registers */
3195 gfar_write(®s->igaddr0, 0);
3196 gfar_write(®s->igaddr1, 0);
3197 gfar_write(®s->igaddr2, 0);
3198 gfar_write(®s->igaddr3, 0);
3199 gfar_write(®s->igaddr4, 0);
3200 gfar_write(®s->igaddr5, 0);
3201 gfar_write(®s->igaddr6, 0);
3202 gfar_write(®s->igaddr7, 0);
3204 gfar_write(®s->gaddr0, 0);
3205 gfar_write(®s->gaddr1, 0);
3206 gfar_write(®s->gaddr2, 0);
3207 gfar_write(®s->gaddr3, 0);
3208 gfar_write(®s->gaddr4, 0);
3209 gfar_write(®s->gaddr5, 0);
3210 gfar_write(®s->gaddr6, 0);
3211 gfar_write(®s->gaddr7, 0);
3213 if (priv->extended_hash)
3214 gfar_clear_exact_match(priv->ndev);
3216 gfar_mac_rx_config(priv);
3218 gfar_mac_tx_config(priv);
3220 gfar_set_mac_address(priv->ndev);
3222 gfar_set_multi(priv->ndev);
3224 /* clear ievent and imask before configuring coalescing */
3225 gfar_ints_disable(priv);
3227 /* Configure the coalescing support */
3228 gfar_configure_coalescing_all(priv);
3231 static void gfar_hw_init(struct gfar_private *priv)
3233 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3236 /* Stop the DMA engine now, in case it was running before
3237 * (The firmware could have used it, and left it running).
3241 gfar_mac_reset(priv);
3243 /* Zero out the rmon mib registers if it has them */
3244 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3245 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
3247 /* Mask off the CAM interrupts */
3248 gfar_write(®s->rmon.cam1, 0xffffffff);
3249 gfar_write(®s->rmon.cam2, 0xffffffff);
3252 /* Initialize ECNTRL */
3253 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
3255 /* Set the extraction length and index */
3256 attrs = ATTRELI_EL(priv->rx_stash_size) |
3257 ATTRELI_EI(priv->rx_stash_index);
3259 gfar_write(®s->attreli, attrs);
3261 /* Start with defaults, and add stashing
3262 * depending on driver parameters
3264 attrs = ATTR_INIT_SETTINGS;
3266 if (priv->bd_stash_en)
3267 attrs |= ATTR_BDSTASH;
3269 if (priv->rx_stash_size != 0)
3270 attrs |= ATTR_BUFSTASH;
3272 gfar_write(®s->attr, attrs);
3275 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
3276 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
3277 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
3279 /* Program the interrupt steering regs, only for MG devices */
3280 if (priv->num_grps > 1)
3281 gfar_write_isrg(priv);
3284 static const struct net_device_ops gfar_netdev_ops = {
3285 .ndo_open = gfar_enet_open,
3286 .ndo_start_xmit = gfar_start_xmit,
3287 .ndo_stop = gfar_close,
3288 .ndo_change_mtu = gfar_change_mtu,
3289 .ndo_set_features = gfar_set_features,
3290 .ndo_set_rx_mode = gfar_set_multi,
3291 .ndo_tx_timeout = gfar_timeout,
3292 .ndo_do_ioctl = gfar_ioctl,
3293 .ndo_get_stats = gfar_get_stats,
3294 .ndo_change_carrier = fixed_phy_change_carrier,
3295 .ndo_set_mac_address = gfar_set_mac_addr,
3296 .ndo_validate_addr = eth_validate_addr,
3297 #ifdef CONFIG_NET_POLL_CONTROLLER
3298 .ndo_poll_controller = gfar_netpoll,
3302 /* Set up the ethernet device structure, private data,
3303 * and anything else we need before we start
3305 static int gfar_probe(struct platform_device *ofdev)
3307 struct device_node *np = ofdev->dev.of_node;
3308 struct net_device *dev = NULL;
3309 struct gfar_private *priv = NULL;
3312 err = gfar_of_init(ofdev, &dev);
3317 priv = netdev_priv(dev);
3319 priv->ofdev = ofdev;
3320 priv->dev = &ofdev->dev;
3321 SET_NETDEV_DEV(dev, &ofdev->dev);
3323 INIT_WORK(&priv->reset_task, gfar_reset_task);
3325 platform_set_drvdata(ofdev, priv);
3327 gfar_detect_errata(priv);
3329 /* Set the dev->base_addr to the gfar reg region */
3330 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
3332 /* Fill in the dev structure */
3333 dev->watchdog_timeo = TX_TIMEOUT;
3334 /* MTU range: 50 - 9586 */
3337 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
3338 dev->netdev_ops = &gfar_netdev_ops;
3339 dev->ethtool_ops = &gfar_ethtool_ops;
3341 /* Register for napi ...We are registering NAPI for each grp */
3342 for (i = 0; i < priv->num_grps; i++) {
3343 if (priv->poll_mode == GFAR_SQ_POLLING) {
3344 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3345 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
3346 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3347 gfar_poll_tx_sq, 2);
3349 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3350 gfar_poll_rx, GFAR_DEV_WEIGHT);
3351 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3356 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
3357 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3359 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
3360 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
3363 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
3364 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3365 NETIF_F_HW_VLAN_CTAG_RX;
3366 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3369 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3371 gfar_init_addr_hash_table(priv);
3373 /* Insert receive time stamps into padding alignment bytes, and
3374 * plus 2 bytes padding to ensure the cpu alignment.
3376 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3377 priv->padding = 8 + DEFAULT_PADDING;
3379 if (dev->features & NETIF_F_IP_CSUM ||
3380 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3381 dev->needed_headroom = GMAC_FCB_LEN;
3383 /* Initializing some of the rx/tx queue level parameters */
3384 for (i = 0; i < priv->num_tx_queues; i++) {
3385 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
3386 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
3387 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
3388 priv->tx_queue[i]->txic = DEFAULT_TXIC;
3391 for (i = 0; i < priv->num_rx_queues; i++) {
3392 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
3393 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
3394 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
3397 /* Always enable rx filer if available */
3398 priv->rx_filer_enable =
3399 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
3400 /* Enable most messages by default */
3401 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3402 /* use pritority h/w tx queue scheduling for single queue devices */
3403 if (priv->num_tx_queues == 1)
3404 priv->prio_sched_en = 1;
3406 set_bit(GFAR_DOWN, &priv->state);
3410 /* Carrier starts down, phylib will bring it up */
3411 netif_carrier_off(dev);
3413 err = register_netdev(dev);
3416 pr_err("%s: Cannot register net device, aborting\n", dev->name);
3420 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
3421 priv->wol_supported |= GFAR_WOL_MAGIC;
3423 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
3424 priv->rx_filer_enable)
3425 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
3427 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
3429 /* fill out IRQ number and name fields */
3430 for (i = 0; i < priv->num_grps; i++) {
3431 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3432 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3433 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
3434 dev->name, "_g", '0' + i, "_tx");
3435 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
3436 dev->name, "_g", '0' + i, "_rx");
3437 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
3438 dev->name, "_g", '0' + i, "_er");
3440 strcpy(gfar_irq(grp, TX)->name, dev->name);
3443 /* Initialize the filer table */
3444 gfar_init_filer_table(priv);
3446 /* Print out the device info */
3447 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
3449 /* Even more device info helps when determining which kernel
3450 * provided which set of benchmarks.
3452 netdev_info(dev, "Running with NAPI enabled\n");
3453 for (i = 0; i < priv->num_rx_queues; i++)
3454 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
3455 i, priv->rx_queue[i]->rx_ring_size);
3456 for (i = 0; i < priv->num_tx_queues; i++)
3457 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
3458 i, priv->tx_queue[i]->tx_ring_size);
3463 if (of_phy_is_fixed_link(np))
3464 of_phy_deregister_fixed_link(np);
3465 unmap_group_regs(priv);
3466 gfar_free_rx_queues(priv);
3467 gfar_free_tx_queues(priv);
3468 of_node_put(priv->phy_node);
3469 of_node_put(priv->tbi_node);
3470 free_gfar_dev(priv);
3474 static int gfar_remove(struct platform_device *ofdev)
3476 struct gfar_private *priv = platform_get_drvdata(ofdev);
3477 struct device_node *np = ofdev->dev.of_node;
3479 of_node_put(priv->phy_node);
3480 of_node_put(priv->tbi_node);
3482 unregister_netdev(priv->ndev);
3484 if (of_phy_is_fixed_link(np))
3485 of_phy_deregister_fixed_link(np);
3487 unmap_group_regs(priv);
3488 gfar_free_rx_queues(priv);
3489 gfar_free_tx_queues(priv);
3490 free_gfar_dev(priv);
3497 static void __gfar_filer_disable(struct gfar_private *priv)
3499 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3502 temp = gfar_read(®s->rctrl);
3503 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
3504 gfar_write(®s->rctrl, temp);
3507 static void __gfar_filer_enable(struct gfar_private *priv)
3509 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3512 temp = gfar_read(®s->rctrl);
3513 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
3514 gfar_write(®s->rctrl, temp);
3517 /* Filer rules implementing wol capabilities */
3518 static void gfar_filer_config_wol(struct gfar_private *priv)
3523 __gfar_filer_disable(priv);
3525 /* clear the filer table, reject any packet by default */
3526 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
3527 for (i = 0; i <= MAX_FILER_IDX; i++)
3528 gfar_write_filer(priv, i, rqfcr, 0);
3531 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
3532 /* unicast packet, accept it */
3533 struct net_device *ndev = priv->ndev;
3534 /* get the default rx queue index */
3535 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
3536 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
3537 (ndev->dev_addr[1] << 8) |
3540 rqfcr = (qindex << 10) | RQFCR_AND |
3541 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
3543 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3545 dest_mac_addr = (ndev->dev_addr[3] << 16) |
3546 (ndev->dev_addr[4] << 8) |
3548 rqfcr = (qindex << 10) | RQFCR_GPI |
3549 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
3550 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3553 __gfar_filer_enable(priv);
3556 static void gfar_filer_restore_table(struct gfar_private *priv)
3561 __gfar_filer_disable(priv);
3563 for (i = 0; i <= MAX_FILER_IDX; i++) {
3564 rqfcr = priv->ftp_rqfcr[i];
3565 rqfpr = priv->ftp_rqfpr[i];
3566 gfar_write_filer(priv, i, rqfcr, rqfpr);
3569 __gfar_filer_enable(priv);
3572 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
3573 static void gfar_start_wol_filer(struct gfar_private *priv)
3575 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3579 /* Enable Rx hw queues */
3580 gfar_write(®s->rqueue, priv->rqueue);
3582 /* Initialize DMACTRL to have WWR and WOP */
3583 tempval = gfar_read(®s->dmactrl);
3584 tempval |= DMACTRL_INIT_SETTINGS;
3585 gfar_write(®s->dmactrl, tempval);
3587 /* Make sure we aren't stopped */
3588 tempval = gfar_read(®s->dmactrl);
3589 tempval &= ~DMACTRL_GRS;
3590 gfar_write(®s->dmactrl, tempval);
3592 for (i = 0; i < priv->num_grps; i++) {
3593 regs = priv->gfargrp[i].regs;
3594 /* Clear RHLT, so that the DMA starts polling now */
3595 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
3596 /* enable the Filer General Purpose Interrupt */
3597 gfar_write(®s->imask, IMASK_FGPI);
3601 tempval = gfar_read(®s->maccfg1);
3602 tempval |= MACCFG1_RX_EN;
3603 gfar_write(®s->maccfg1, tempval);
3606 static int gfar_suspend(struct device *dev)
3608 struct gfar_private *priv = dev_get_drvdata(dev);
3609 struct net_device *ndev = priv->ndev;
3610 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3612 u16 wol = priv->wol_opts;
3614 if (!netif_running(ndev))
3618 netif_tx_lock(ndev);
3619 netif_device_detach(ndev);
3620 netif_tx_unlock(ndev);
3624 if (wol & GFAR_WOL_MAGIC) {
3625 /* Enable interrupt on Magic Packet */
3626 gfar_write(®s->imask, IMASK_MAG);
3628 /* Enable Magic Packet mode */
3629 tempval = gfar_read(®s->maccfg2);
3630 tempval |= MACCFG2_MPEN;
3631 gfar_write(®s->maccfg2, tempval);
3633 /* re-enable the Rx block */
3634 tempval = gfar_read(®s->maccfg1);
3635 tempval |= MACCFG1_RX_EN;
3636 gfar_write(®s->maccfg1, tempval);
3638 } else if (wol & GFAR_WOL_FILER_UCAST) {
3639 gfar_filer_config_wol(priv);
3640 gfar_start_wol_filer(priv);
3643 phy_stop(ndev->phydev);
3649 static int gfar_resume(struct device *dev)
3651 struct gfar_private *priv = dev_get_drvdata(dev);
3652 struct net_device *ndev = priv->ndev;
3653 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3655 u16 wol = priv->wol_opts;
3657 if (!netif_running(ndev))
3660 if (wol & GFAR_WOL_MAGIC) {
3661 /* Disable Magic Packet mode */
3662 tempval = gfar_read(®s->maccfg2);
3663 tempval &= ~MACCFG2_MPEN;
3664 gfar_write(®s->maccfg2, tempval);
3666 } else if (wol & GFAR_WOL_FILER_UCAST) {
3667 /* need to stop rx only, tx is already down */
3669 gfar_filer_restore_table(priv);
3672 phy_start(ndev->phydev);
3677 netif_device_attach(ndev);
3683 static int gfar_restore(struct device *dev)
3685 struct gfar_private *priv = dev_get_drvdata(dev);
3686 struct net_device *ndev = priv->ndev;
3688 if (!netif_running(ndev)) {
3689 netif_device_attach(ndev);
3694 gfar_init_bds(ndev);
3696 gfar_mac_reset(priv);
3698 gfar_init_tx_rx_base(priv);
3704 priv->oldduplex = -1;
3707 phy_start(ndev->phydev);
3709 netif_device_attach(ndev);
3715 static const struct dev_pm_ops gfar_pm_ops = {
3716 .suspend = gfar_suspend,
3717 .resume = gfar_resume,
3718 .freeze = gfar_suspend,
3719 .thaw = gfar_resume,
3720 .restore = gfar_restore,
3723 #define GFAR_PM_OPS (&gfar_pm_ops)
3727 #define GFAR_PM_OPS NULL
3731 static const struct of_device_id gfar_match[] =
3735 .compatible = "gianfar",
3738 .compatible = "fsl,etsec2",
3742 MODULE_DEVICE_TABLE(of, gfar_match);
3744 /* Structure for a device driver */
3745 static struct platform_driver gfar_driver = {
3747 .name = "fsl-gianfar",
3749 .of_match_table = gfar_match,
3751 .probe = gfar_probe,
3752 .remove = gfar_remove,
3755 module_platform_driver(gfar_driver);