drivers/net/ethernet/freescale/gianfar.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* drivers/net/ethernet/freescale/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  17  *  RA 11 31 24.2
  18  *  Dec +69 19 52
  19  *  V 3.84
  20  *  B-V +1.62
  21  *
  22  *  Theory of operation
  23  *
  24  *  The driver is initialized through of_device. Configuration information
  25  *  is therefore conveyed through an OF-style device tree.
  26  *
  27  *  The Gianfar Ethernet Controller uses a ring of buffer
  28  *  descriptors.  The beginning is indicated by a register
  29  *  pointing to the physical address of the start of the ring.
  30  *  The end is determined by a "wrap" bit being set in the
  31  *  last descriptor of the ring.
  32  *
  33  *  When a packet is received, the RXF bit in the
  34  *  IEVENT register is set, triggering an interrupt when the
  35  *  corresponding bit in the IMASK register is also set (if
  36  *  interrupt coalescing is active, then the interrupt may not
  37  *  happen immediately, but will wait until either a set number
  38  *  of frames or amount of time have passed).  In NAPI, the
  39  *  interrupt handler will signal there is work to be done, and
  40  *  exit. This method will start at the last known empty
  41  *  descriptor, and process every subsequent descriptor until there
  42  *  are none left with data (NAPI will stop after a set number of
  43  *  packets to give time to other tasks, but will eventually
  44  *  process all the packets).  The data arrives inside a
  45  *  pre-allocated skb, and so after the skb is passed up to the
  46  *  stack, a new skb must be allocated, and the address field in
  47  *  the buffer descriptor must be updated to indicate this new
  48  *  skb.
  49  *
  50  *  When the kernel requests that a packet be transmitted, the
  51  *  driver starts where it left off last time, and points the
  52  *  descriptor at the buffer which was passed in.  The driver
  53  *  then informs the DMA engine that there are packets ready to
  54  *  be transmitted.  Once the controller is finished transmitting
  55  *  the packet, an interrupt may be triggered (under the same
  56  *  conditions as for reception, but depending on the TXF bit).
  57  *  The driver then cleans up the buffer.
  58  */
  59
  60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  61 #define DEBUG
  62
  63 #include <linux/kernel.h>
  64 #include <linux/string.h>
  65 #include <linux/errno.h>
  66 #include <linux/unistd.h>
  67 #include <linux/slab.h>
  68 #include <linux/interrupt.h>
  69 #include <linux/delay.h>
  70 #include <linux/netdevice.h>
  71 #include <linux/etherdevice.h>
  72 #include <linux/skbuff.h>
  73 #include <linux/if_vlan.h>
  74 #include <linux/spinlock.h>
  75 #include <linux/mm.h>
  76 #include <linux/of_address.h>
  77 #include <linux/of_irq.h>
  78 #include <linux/of_mdio.h>
  79 #include <linux/of_platform.h>
  80 #include <linux/ip.h>
  81 #include <linux/tcp.h>
  82 #include <linux/udp.h>
  83 #include <linux/in.h>
  84 #include <linux/net_tstamp.h>
  85
  86 #include <asm/io.h>
  87 #ifdef CONFIG_PPC
  88 #include <asm/reg.h>
  89 #include <asm/mpc85xx.h>
  90 #endif
  91 #include <asm/irq.h>
  92 #include <linux/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (5*HZ)
 105
 106 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 107 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 108 MODULE_LICENSE("GPL");
 109
 110 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 111                             dma_addr_t buf)
 112 {
 113         u32 lstatus;
 114
 115         bdp->bufPtr = cpu_to_be32(buf);
 116
 117         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 118         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 119                 lstatus |= BD_LFLAG(RXBD_WRAP);
 120
 121         gfar_wmb();
 122
 123         bdp->lstatus = cpu_to_be32(lstatus);
 124 }
 125
 126 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 127 {
 128         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 129         u32 __iomem *baddr;
 130         int i;
 131
 132         baddr = &regs->tbase0;
 133         for (i = 0; i < priv->num_tx_queues; i++) {
 134                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 135                 baddr += 2;
 136         }
 137
 138         baddr = &regs->rbase0;
 139         for (i = 0; i < priv->num_rx_queues; i++) {
 140                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 141                 baddr += 2;
 142         }
 143 }
 144
 145 static void gfar_init_rqprm(struct gfar_private *priv)
 146 {
 147         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 148         u32 __iomem *baddr;
 149         int i;
 150
 151         baddr = &regs->rqprm0;
 152         for (i = 0; i < priv->num_rx_queues; i++) {
 153                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 154                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 155                 baddr++;
 156         }
 157 }
 158
 159 static void gfar_rx_offload_en(struct gfar_private *priv)
 160 {
 161         /* set this when rx hw offload (TOE) functions are being used */
 162         priv->uses_rxfcb = 0;
 163
 164         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 165                 priv->uses_rxfcb = 1;
 166
 167         if (priv->hwts_rx_en || priv->rx_filer_enable)
 168                 priv->uses_rxfcb = 1;
 169 }
 170
 171 static void gfar_mac_rx_config(struct gfar_private *priv)
 172 {
 173         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 174         u32 rctrl = 0;
 175
 176         if (priv->rx_filer_enable) {
 177                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 178                 /* Program the RIR0 reg with the required distribution */
 179                 if (priv->poll_mode == GFAR_SQ_POLLING)
 180                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 181                 else /* GFAR_MQ_POLLING */
 182                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 183         }
 184
 185         /* Restore PROMISC mode */
 186         if (priv->ndev->flags & IFF_PROMISC)
 187                 rctrl |= RCTRL_PROM;
 188
 189         if (priv->ndev->features & NETIF_F_RXCSUM)
 190                 rctrl |= RCTRL_CHECKSUMMING;
 191
 192         if (priv->extended_hash)
 193                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 194
 195         if (priv->padding) {
 196                 rctrl &= ~RCTRL_PAL_MASK;
 197                 rctrl |= RCTRL_PADDING(priv->padding);
 198         }
 199
 200         /* Enable HW time stamping if requested from user space */
 201         if (priv->hwts_rx_en)
 202                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 203
 204         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 205                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 206
 207         /* Clear the LFC bit */
 208         gfar_write(&regs->rctrl, rctrl);
 209         /* Init flow control threshold values */
 210         gfar_init_rqprm(priv);
 211         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 212         rctrl |= RCTRL_LFC;
 213
 214         /* Init rctrl based on our settings */
 215         gfar_write(&regs->rctrl, rctrl);
 216 }
 217
 218 static void gfar_mac_tx_config(struct gfar_private *priv)
 219 {
 220         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 221         u32 tctrl = 0;
 222
 223         if (priv->ndev->features & NETIF_F_IP_CSUM)
 224                 tctrl |= TCTRL_INIT_CSUM;
 225
 226         if (priv->prio_sched_en)
 227                 tctrl |= TCTRL_TXSCHED_PRIO;
 228         else {
 229                 tctrl |= TCTRL_TXSCHED_WRRS;
 230                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 231                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 232         }
 233
 234         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 235                 tctrl |= TCTRL_VLINS;
 236
 237         gfar_write(&regs->tctrl, tctrl);
 238 }
 239
 240 static void gfar_configure_coalescing(struct gfar_private *priv,
 241                                unsigned long tx_mask, unsigned long rx_mask)
 242 {
 243         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 244         u32 __iomem *baddr;
 245
 246         if (priv->mode == MQ_MG_MODE) {
 247                 int i = 0;
 248
 249                 baddr = &regs->txic0;
 250                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 251                         gfar_write(baddr + i, 0);
 252                         if (likely(priv->tx_queue[i]->txcoalescing))
 253                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 254                 }
 255
 256                 baddr = &regs->rxic0;
 257                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 258                         gfar_write(baddr + i, 0);
 259                         if (likely(priv->rx_queue[i]->rxcoalescing))
 260                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 261                 }
 262         } else {
 263                 /* Backward compatible case -- even if we enable
 264                  * multiple queues, there's only single reg to program
 265                  */
 266                 gfar_write(&regs->txic, 0);
 267                 if (likely(priv->tx_queue[0]->txcoalescing))
 268                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 269
 270                 gfar_write(&regs->rxic, 0);
 271                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 272                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 273         }
 274 }
 275
 276 static void gfar_configure_coalescing_all(struct gfar_private *priv)
 277 {
 278         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 279 }
 280
 281 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 282 {
 283         struct gfar_private *priv = netdev_priv(dev);
 284         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 285         unsigned long tx_packets = 0, tx_bytes = 0;
 286         int i;
 287
 288         for (i = 0; i < priv->num_rx_queues; i++) {
 289                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 290                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 291                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 292         }
 293
 294         dev->stats.rx_packets = rx_packets;
 295         dev->stats.rx_bytes   = rx_bytes;
 296         dev->stats.rx_dropped = rx_dropped;
 297
 298         for (i = 0; i < priv->num_tx_queues; i++) {
 299                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 300                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 301         }
 302
 303         dev->stats.tx_bytes   = tx_bytes;
 304         dev->stats.tx_packets = tx_packets;
 305
 306         return &dev->stats;
 307 }
 308
 309 /* Set the appropriate hash bit for the given addr */
 310 /* The algorithm works like so:
 311  * 1) Take the Destination Address (ie the multicast address), and
 312  * do a CRC on it (little endian), and reverse the bits of the
 313  * result.
 314  * 2) Use the 8 most significant bits as a hash into a 256-entry
 315  * table.  The table is controlled through 8 32-bit registers:
 316  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
 317  * gaddr7.  This means that the 3 most significant bits in the
 318  * hash index which gaddr register to use, and the 5 other bits
 319  * indicate which bit (assuming an IBM numbering scheme, which
 320  * for PowerPC (tm) is usually the case) in the register holds
 321  * the entry.
 322  */
 323 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
 324 {
 325         u32 tempval;
 326         struct gfar_private *priv = netdev_priv(dev);
 327         u32 result = ether_crc(ETH_ALEN, addr);
 328         int width = priv->hash_width;
 329         u8 whichbit = (result >> (32 - width)) & 0x1f;
 330         u8 whichreg = result >> (32 - width + 5);
 331         u32 value = (1 << (31-whichbit));
 332
 333         tempval = gfar_read(priv->hash_regs[whichreg]);
 334         tempval |= value;
 335         gfar_write(priv->hash_regs[whichreg], tempval);
 336 }
 337
 338 /* There are multiple MAC Address register pairs on some controllers
 339  * This function sets the numth pair to a given address
 340  */
 341 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 342                                   const u8 *addr)
 343 {
 344         struct gfar_private *priv = netdev_priv(dev);
 345         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 346         u32 tempval;
 347         u32 __iomem *macptr = &regs->macstnaddr1;
 348
 349         macptr += num*2;
 350
 351         /* For a station address of 0x12345678ABCD in transmission
 352          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
 353          * MACnADDR2 is set to 0x34120000.
 354          */
 355         tempval = (addr[5] << 24) | (addr[4] << 16) |
 356                   (addr[3] << 8)  |  addr[2];
 357
 358         gfar_write(macptr, tempval);
 359
 360         tempval = (addr[1] << 24) | (addr[0] << 16);
 361
 362         gfar_write(macptr+1, tempval);
 363 }
 364
 365 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 366 {
 367         eth_mac_addr(dev, p);
 368
 369         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 370
 371         return 0;
 372 }
 373
 374 static void gfar_ints_disable(struct gfar_private *priv)
 375 {
 376         int i;
 377         for (i = 0; i < priv->num_grps; i++) {
 378                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 379                 /* Clear IEVENT */
 380                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 381
 382                 /* Initialize IMASK */
 383                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 384         }
 385 }
 386
 387 static void gfar_ints_enable(struct gfar_private *priv)
 388 {
 389         int i;
 390         for (i = 0; i < priv->num_grps; i++) {
 391                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 392                 /* Unmask the interrupts we look for */
 393                 gfar_write(&regs->imask, IMASK_DEFAULT);
 394         }
 395 }
 396
 397 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 398 {
 399         int i;
 400
 401         for (i = 0; i < priv->num_tx_queues; i++) {
 402                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 403                                             GFP_KERNEL);
 404                 if (!priv->tx_queue[i])
 405                         return -ENOMEM;
 406
 407                 priv->tx_queue[i]->tx_skbuff = NULL;
 408                 priv->tx_queue[i]->qindex = i;
 409                 priv->tx_queue[i]->dev = priv->ndev;
 410                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 411         }
 412         return 0;
 413 }
 414
 415 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 416 {
 417         int i;
 418
 419         for (i = 0; i < priv->num_rx_queues; i++) {
 420                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 421                                             GFP_KERNEL);
 422                 if (!priv->rx_queue[i])
 423                         return -ENOMEM;
 424
 425                 priv->rx_queue[i]->qindex = i;
 426                 priv->rx_queue[i]->ndev = priv->ndev;
 427         }
 428         return 0;
 429 }
 430
 431 static void gfar_free_tx_queues(struct gfar_private *priv)
 432 {
 433         int i;
 434
 435         for (i = 0; i < priv->num_tx_queues; i++)
 436                 kfree(priv->tx_queue[i]);
 437 }
 438
 439 static void gfar_free_rx_queues(struct gfar_private *priv)
 440 {
 441         int i;
 442
 443         for (i = 0; i < priv->num_rx_queues; i++)
 444                 kfree(priv->rx_queue[i]);
 445 }
 446
 447 static void unmap_group_regs(struct gfar_private *priv)
 448 {
 449         int i;
 450
 451         for (i = 0; i < MAXGROUPS; i++)
 452                 if (priv->gfargrp[i].regs)
 453                         iounmap(priv->gfargrp[i].regs);
 454 }
 455
 456 static void free_gfar_dev(struct gfar_private *priv)
 457 {
 458         int i, j;
 459
 460         for (i = 0; i < priv->num_grps; i++)
 461                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 462                         kfree(priv->gfargrp[i].irqinfo[j]);
 463                         priv->gfargrp[i].irqinfo[j] = NULL;
 464                 }
 465
 466         free_netdev(priv->ndev);
 467 }
 468
 469 static void disable_napi(struct gfar_private *priv)
 470 {
 471         int i;
 472
 473         for (i = 0; i < priv->num_grps; i++) {
 474                 napi_disable(&priv->gfargrp[i].napi_rx);
 475                 napi_disable(&priv->gfargrp[i].napi_tx);
 476         }
 477 }
 478
 479 static void enable_napi(struct gfar_private *priv)
 480 {
 481         int i;
 482
 483         for (i = 0; i < priv->num_grps; i++) {
 484                 napi_enable(&priv->gfargrp[i].napi_rx);
 485                 napi_enable(&priv->gfargrp[i].napi_tx);
 486         }
 487 }
 488
 489 static int gfar_parse_group(struct device_node *np,
 490                             struct gfar_private *priv, const char *model)
 491 {
 492         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 493         int i;
 494
 495         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 496                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 497                                           GFP_KERNEL);
 498                 if (!grp->irqinfo[i])
 499                         return -ENOMEM;
 500         }
 501
 502         grp->regs = of_iomap(np, 0);
 503         if (!grp->regs)
 504                 return -ENOMEM;
 505
 506         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 507
 508         /* If we aren't the FEC we have multiple interrupts */
 509         if (model && strcasecmp(model, "FEC")) {
 510                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 511                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 512                 if (!gfar_irq(grp, TX)->irq ||
 513                     !gfar_irq(grp, RX)->irq ||
 514                     !gfar_irq(grp, ER)->irq)
 515                         return -EINVAL;
 516         }
 517
 518         grp->priv = priv;
 519         spin_lock_init(&grp->grplock);
 520         if (priv->mode == MQ_MG_MODE) {
 521                 u32 rxq_mask, txq_mask;
 522                 int ret;
 523
 524                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 525                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 526
 527                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 528                 if (!ret) {
 529                         grp->rx_bit_map = rxq_mask ?
 530                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 531                 }
 532
 533                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 534                 if (!ret) {
 535                         grp->tx_bit_map = txq_mask ?
 536                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 537                 }
 538
 539                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 540                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 541                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 542                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 543                 }
 544         } else {
 545                 grp->rx_bit_map = 0xFF;
 546                 grp->tx_bit_map = 0xFF;
 547         }
 548
 549         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 550          * right to left, so we need to revert the 8 bits to get the q index
 551          */
 552         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 553         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 554
 555         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 556          * also assign queues to groups
 557          */
 558         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 559                 if (!grp->rx_queue)
 560                         grp->rx_queue = priv->rx_queue[i];
 561                 grp->num_rx_queues++;
 562                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 563                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 564                 priv->rx_queue[i]->grp = grp;
 565         }
 566
 567         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 568                 if (!grp->tx_queue)
 569                         grp->tx_queue = priv->tx_queue[i];
 570                 grp->num_tx_queues++;
 571                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 572                 priv->tqueue |= (TQUEUE_EN0 >> i);
 573                 priv->tx_queue[i]->grp = grp;
 574         }
 575
 576         priv->num_grps++;
 577
 578         return 0;
 579 }
 580
 581 static int gfar_of_group_count(struct device_node *np)
 582 {
 583         struct device_node *child;
 584         int num = 0;
 585
 586         for_each_available_child_of_node(np, child)
 587                 if (of_node_name_eq(child, "queue-group"))
 588                         num++;
 589
 590         return num;
 591 }
 592
 593 /* Reads the controller's registers to determine what interface
 594  * connects it to the PHY.
 595  */
 596 static phy_interface_t gfar_get_interface(struct net_device *dev)
 597 {
 598         struct gfar_private *priv = netdev_priv(dev);
 599         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 600         u32 ecntrl;
 601
 602         ecntrl = gfar_read(&regs->ecntrl);
 603
 604         if (ecntrl & ECNTRL_SGMII_MODE)
 605                 return PHY_INTERFACE_MODE_SGMII;
 606
 607         if (ecntrl & ECNTRL_TBI_MODE) {
 608                 if (ecntrl & ECNTRL_REDUCED_MODE)
 609                         return PHY_INTERFACE_MODE_RTBI;
 610                 else
 611                         return PHY_INTERFACE_MODE_TBI;
 612         }
 613
 614         if (ecntrl & ECNTRL_REDUCED_MODE) {
 615                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
 616                         return PHY_INTERFACE_MODE_RMII;
 617                 }
 618                 else {
 619                         phy_interface_t interface = priv->interface;
 620
 621                         /* This isn't autodetected right now, so it must
 622                          * be set by the device tree or platform code.
 623                          */
 624                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 625                                 return PHY_INTERFACE_MODE_RGMII_ID;
 626
 627                         return PHY_INTERFACE_MODE_RGMII;
 628                 }
 629         }
 630
 631         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 632                 return PHY_INTERFACE_MODE_GMII;
 633
 634         return PHY_INTERFACE_MODE_MII;
 635 }
 636
 637 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 638 {
 639         const char *model;
 640         const void *mac_addr;
 641         int err = 0, i;
 642         phy_interface_t interface;
 643         struct net_device *dev = NULL;
 644         struct gfar_private *priv = NULL;
 645         struct device_node *np = ofdev->dev.of_node;
 646         struct device_node *child = NULL;
 647         u32 stash_len = 0;
 648         u32 stash_idx = 0;
 649         unsigned int num_tx_qs, num_rx_qs;
 650         unsigned short mode, poll_mode;
 651
 652         if (!np)
 653                 return -ENODEV;
 654
 655         if (of_device_is_compatible(np, "fsl,etsec2")) {
 656                 mode = MQ_MG_MODE;
 657                 poll_mode = GFAR_SQ_POLLING;
 658         } else {
 659                 mode = SQ_SG_MODE;
 660                 poll_mode = GFAR_SQ_POLLING;
 661         }
 662
 663         if (mode == SQ_SG_MODE) {
 664                 num_tx_qs = 1;
 665                 num_rx_qs = 1;
 666         } else { /* MQ_MG_MODE */
 667                 /* get the actual number of supported groups */
 668                 unsigned int num_grps = gfar_of_group_count(np);
 669
 670                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 671                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 672                                 num_grps);
 673                         pr_err("Cannot do alloc_etherdev, aborting\n");
 674                         return -EINVAL;
 675                 }
 676
 677                 if (poll_mode == GFAR_SQ_POLLING) {
 678                         num_tx_qs = num_grps; /* one txq per int group */
 679                         num_rx_qs = num_grps; /* one rxq per int group */
 680                 } else { /* GFAR_MQ_POLLING */
 681                         u32 tx_queues, rx_queues;
 682                         int ret;
 683
 684                         /* parse the num of HW tx and rx queues */
 685                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 686                                                    &tx_queues);
 687                         num_tx_qs = ret ? 1 : tx_queues;
 688
 689                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 690                                                    &rx_queues);
 691                         num_rx_qs = ret ? 1 : rx_queues;
 692                 }
 693         }
 694
 695         if (num_tx_qs > MAX_TX_QS) {
 696                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 697                        num_tx_qs, MAX_TX_QS);
 698                 pr_err("Cannot do alloc_etherdev, aborting\n");
 699                 return -EINVAL;
 700         }
 701
 702         if (num_rx_qs > MAX_RX_QS) {
 703                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 704                        num_rx_qs, MAX_RX_QS);
 705                 pr_err("Cannot do alloc_etherdev, aborting\n");
 706                 return -EINVAL;
 707         }
 708
 709         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 710         dev = *pdev;
 711         if (NULL == dev)
 712                 return -ENOMEM;
 713
 714         priv = netdev_priv(dev);
 715         priv->ndev = dev;
 716
 717         priv->mode = mode;
 718         priv->poll_mode = poll_mode;
 719
 720         priv->num_tx_queues = num_tx_qs;
 721         netif_set_real_num_rx_queues(dev, num_rx_qs);
 722         priv->num_rx_queues = num_rx_qs;
 723
 724         err = gfar_alloc_tx_queues(priv);
 725         if (err)
 726                 goto tx_alloc_failed;
 727
 728         err = gfar_alloc_rx_queues(priv);
 729         if (err)
 730                 goto rx_alloc_failed;
 731
 732         err = of_property_read_string(np, "model", &model);
 733         if (err) {
 734                 pr_err("Device model property missing, aborting\n");
 735                 goto rx_alloc_failed;
 736         }
 737
 738         /* Init Rx queue filer rule set linked list */
 739         INIT_LIST_HEAD(&priv->rx_list.list);
 740         priv->rx_list.count = 0;
 741         mutex_init(&priv->rx_queue_access);
 742
 743         for (i = 0; i < MAXGROUPS; i++)
 744                 priv->gfargrp[i].regs = NULL;
 745
 746         /* Parse and initialize group specific information */
 747         if (priv->mode == MQ_MG_MODE) {
 748                 for_each_available_child_of_node(np, child) {
 749                         if (!of_node_name_eq(child, "queue-group"))
 750                                 continue;
 751
 752                         err = gfar_parse_group(child, priv, model);
 753                         if (err)
 754                                 goto err_grp_init;
 755                 }
 756         } else { /* SQ_SG_MODE */
 757                 err = gfar_parse_group(np, priv, model);
 758                 if (err)
 759                         goto err_grp_init;
 760         }
 761
 762         if (of_property_read_bool(np, "bd-stash")) {
 763                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 764                 priv->bd_stash_en = 1;
 765         }
 766
 767         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 768
 769         if (err == 0)
 770                 priv->rx_stash_size = stash_len;
 771
 772         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 773
 774         if (err == 0)
 775                 priv->rx_stash_index = stash_idx;
 776
 777         if (stash_len || stash_idx)
 778                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 779
 780         mac_addr = of_get_mac_address(np);
 781
 782         if (!IS_ERR(mac_addr)) {
 783                 ether_addr_copy(dev->dev_addr, mac_addr);
 784         } else {
 785                 eth_hw_addr_random(dev);
 786                 dev_info(&ofdev->dev, "Using random MAC address: %pM\n", dev->dev_addr);
 787         }
 788
 789         if (model && !strcasecmp(model, "TSEC"))
 790                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 791                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 792                                      FSL_GIANFAR_DEV_HAS_RMON |
 793                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 794
 795         if (model && !strcasecmp(model, "eTSEC"))
 796                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 797                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 798                                      FSL_GIANFAR_DEV_HAS_RMON |
 799                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 800                                      FSL_GIANFAR_DEV_HAS_CSUM |
 801                                      FSL_GIANFAR_DEV_HAS_VLAN |
 802                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 803                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 804                                      FSL_GIANFAR_DEV_HAS_TIMER |
 805                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 806
 807         /* Use PHY connection type from the DT node if one is specified there.
 808          * rgmii-id really needs to be specified. Other types can be
 809          * detected by hardware
 810          */
 811         err = of_get_phy_mode(np, &interface);
 812         if (!err)
 813                 priv->interface = interface;
 814         else
 815                 priv->interface = gfar_get_interface(dev);
 816
 817         if (of_find_property(np, "fsl,magic-packet", NULL))
 818                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 819
 820         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 821                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 822
 823         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 824
 825         /* In the case of a fixed PHY, the DT node associated
 826          * to the PHY is the Ethernet MAC DT node.
 827          */
 828         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 829                 err = of_phy_register_fixed_link(np);
 830                 if (err)
 831                         goto err_grp_init;
 832
 833                 priv->phy_node = of_node_get(np);
 834         }
 835
 836         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 837         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 838
 839         return 0;
 840
 841 err_grp_init:
 842         unmap_group_regs(priv);
 843 rx_alloc_failed:
 844         gfar_free_rx_queues(priv);
 845 tx_alloc_failed:
 846         gfar_free_tx_queues(priv);
 847         free_gfar_dev(priv);
 848         return err;
 849 }
 850
 851 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 852                                    u32 class)
 853 {
 854         u32 rqfpr = FPR_FILER_MASK;
 855         u32 rqfcr = 0x0;
 856
 857         rqfar--;
 858         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 859         priv->ftp_rqfpr[rqfar] = rqfpr;
 860         priv->ftp_rqfcr[rqfar] = rqfcr;
 861         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 862
 863         rqfar--;
 864         rqfcr = RQFCR_CMP_NOMATCH;
 865         priv->ftp_rqfpr[rqfar] = rqfpr;
 866         priv->ftp_rqfcr[rqfar] = rqfcr;
 867         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 868
 869         rqfar--;
 870         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 871         rqfpr = class;
 872         priv->ftp_rqfcr[rqfar] = rqfcr;
 873         priv->ftp_rqfpr[rqfar] = rqfpr;
 874         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 875
 876         rqfar--;
 877         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 878         rqfpr = class;
 879         priv->ftp_rqfcr[rqfar] = rqfcr;
 880         priv->ftp_rqfpr[rqfar] = rqfpr;
 881         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 882
 883         return rqfar;
 884 }
 885
 886 static void gfar_init_filer_table(struct gfar_private *priv)
 887 {
 888         int i = 0x0;
 889         u32 rqfar = MAX_FILER_IDX;
 890         u32 rqfcr = 0x0;
 891         u32 rqfpr = FPR_FILER_MASK;
 892
 893         /* Default rule */
 894         rqfcr = RQFCR_CMP_MATCH;
 895         priv->ftp_rqfcr[rqfar] = rqfcr;
 896         priv->ftp_rqfpr[rqfar] = rqfpr;
 897         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 898
 899         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 900         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 901         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 902         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 903         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 904         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 905
 906         /* cur_filer_idx indicated the first non-masked rule */
 907         priv->cur_filer_idx = rqfar;
 908
 909         /* Rest are masked rules */
 910         rqfcr = RQFCR_CMP_NOMATCH;
 911         for (i = 0; i < rqfar; i++) {
 912                 priv->ftp_rqfcr[i] = rqfcr;
 913                 priv->ftp_rqfpr[i] = rqfpr;
 914                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 915         }
 916 }
 917
 918 #ifdef CONFIG_PPC
 919 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
 920 {
 921         unsigned int pvr = mfspr(SPRN_PVR);
 922         unsigned int svr = mfspr(SPRN_SVR);
 923         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 924         unsigned int rev = svr & 0xffff;
 925
 926         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 927         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 928             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 929                 priv->errata |= GFAR_ERRATA_74;
 930
 931         /* MPC8313 and MPC837x all rev */
 932         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 933             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 934                 priv->errata |= GFAR_ERRATA_76;
 935
 936         /* MPC8313 Rev < 2.0 */
 937         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
 938                 priv->errata |= GFAR_ERRATA_12;
 939 }
 940
 941 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
 942 {
 943         unsigned int svr = mfspr(SPRN_SVR);
 944
 945         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
 946                 priv->errata |= GFAR_ERRATA_12;
 947         /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
 948         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
 949             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
 950             ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
 951                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
 952 }
 953 #endif
 954
 955 static void gfar_detect_errata(struct gfar_private *priv)
 956 {
 957         struct device *dev = &priv->ofdev->dev;
 958
 959         /* no plans to fix */
 960         priv->errata |= GFAR_ERRATA_A002;
 961
 962 #ifdef CONFIG_PPC
 963         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
 964                 __gfar_detect_errata_85xx(priv);
 965         else /* non-mpc85xx parts, i.e. e300 core based */
 966                 __gfar_detect_errata_83xx(priv);
 967 #endif
 968
 969         if (priv->errata)
 970                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 971                          priv->errata);
 972 }
 973
 974 static void gfar_init_addr_hash_table(struct gfar_private *priv)
 975 {
 976         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 977
 978         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 979                 priv->extended_hash = 1;
 980                 priv->hash_width = 9;
 981
 982                 priv->hash_regs[0] = &regs->igaddr0;
 983                 priv->hash_regs[1] = &regs->igaddr1;
 984                 priv->hash_regs[2] = &regs->igaddr2;
 985                 priv->hash_regs[3] = &regs->igaddr3;
 986                 priv->hash_regs[4] = &regs->igaddr4;
 987                 priv->hash_regs[5] = &regs->igaddr5;
 988                 priv->hash_regs[6] = &regs->igaddr6;
 989                 priv->hash_regs[7] = &regs->igaddr7;
 990                 priv->hash_regs[8] = &regs->gaddr0;
 991                 priv->hash_regs[9] = &regs->gaddr1;
 992                 priv->hash_regs[10] = &regs->gaddr2;
 993                 priv->hash_regs[11] = &regs->gaddr3;
 994                 priv->hash_regs[12] = &regs->gaddr4;
 995                 priv->hash_regs[13] = &regs->gaddr5;
 996                 priv->hash_regs[14] = &regs->gaddr6;
 997                 priv->hash_regs[15] = &regs->gaddr7;
 998
 999         } else {
1000                 priv->extended_hash = 0;
1001                 priv->hash_width = 8;
1002
1003                 priv->hash_regs[0] = &regs->gaddr0;
1004                 priv->hash_regs[1] = &regs->gaddr1;
1005                 priv->hash_regs[2] = &regs->gaddr2;
1006                 priv->hash_regs[3] = &regs->gaddr3;
1007                 priv->hash_regs[4] = &regs->gaddr4;
1008                 priv->hash_regs[5] = &regs->gaddr5;
1009                 priv->hash_regs[6] = &regs->gaddr6;
1010                 priv->hash_regs[7] = &regs->gaddr7;
1011         }
1012 }
1013
1014 static int __gfar_is_rx_idle(struct gfar_private *priv)
1015 {
1016         u32 res;
1017
1018         /* Normaly TSEC should not hang on GRS commands, so we should
1019          * actually wait for IEVENT_GRSC flag.
1020          */
1021         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1022                 return 0;
1023
1024         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1025          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1026          * and the Rx can be safely reset.
1027          */
1028         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1029         res &= 0x7f807f80;
1030         if ((res & 0xffff) == (res >> 16))
1031                 return 1;
1032
1033         return 0;
1034 }
1035
1036 /* Halt the receive and transmit queues */
1037 static void gfar_halt_nodisable(struct gfar_private *priv)
1038 {
1039         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1040         u32 tempval;
1041         unsigned int timeout;
1042         int stopped;
1043
1044         gfar_ints_disable(priv);
1045
1046         if (gfar_is_dma_stopped(priv))
1047                 return;
1048
1049         /* Stop the DMA, and wait for it to stop */
1050         tempval = gfar_read(&regs->dmactrl);
1051         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1052         gfar_write(&regs->dmactrl, tempval);
1053
1054 retry:
1055         timeout = 1000;
1056         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1057                 cpu_relax();
1058                 timeout--;
1059         }
1060
1061         if (!timeout)
1062                 stopped = gfar_is_dma_stopped(priv);
1063
1064         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1065             !__gfar_is_rx_idle(priv))
1066                 goto retry;
1067 }
1068
1069 /* Halt the receive and transmit queues */
1070 static void gfar_halt(struct gfar_private *priv)
1071 {
1072         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1073         u32 tempval;
1074
1075         /* Dissable the Rx/Tx hw queues */
1076         gfar_write(&regs->rqueue, 0);
1077         gfar_write(&regs->tqueue, 0);
1078
1079         mdelay(10);
1080
1081         gfar_halt_nodisable(priv);
1082
1083         /* Disable Rx/Tx DMA */
1084         tempval = gfar_read(&regs->maccfg1);
1085         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1086         gfar_write(&regs->maccfg1, tempval);
1087 }
1088
1089 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1090 {
1091         struct txbd8 *txbdp;
1092         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1093         int i, j;
1094
1095         txbdp = tx_queue->tx_bd_base;
1096
1097         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1098                 if (!tx_queue->tx_skbuff[i])
1099                         continue;
1100
1101                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1102                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1103                 txbdp->lstatus = 0;
1104                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1105                      j++) {
1106                         txbdp++;
1107                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1108                                        be16_to_cpu(txbdp->length),
1109                                        DMA_TO_DEVICE);
1110                 }
1111                 txbdp++;
1112                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1113                 tx_queue->tx_skbuff[i] = NULL;
1114         }
1115         kfree(tx_queue->tx_skbuff);
1116         tx_queue->tx_skbuff = NULL;
1117 }
1118
1119 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1120 {
1121         int i;
1122
1123         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1124
1125         dev_kfree_skb(rx_queue->skb);
1126
1127         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1128                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1129
1130                 rxbdp->lstatus = 0;
1131                 rxbdp->bufPtr = 0;
1132                 rxbdp++;
1133
1134                 if (!rxb->page)
1135                         continue;
1136
1137                 dma_unmap_page(rx_queue->dev, rxb->dma,
1138                                PAGE_SIZE, DMA_FROM_DEVICE);
1139                 __free_page(rxb->page);
1140
1141                 rxb->page = NULL;
1142         }
1143
1144         kfree(rx_queue->rx_buff);
1145         rx_queue->rx_buff = NULL;
1146 }
1147
1148 /* If there are any tx skbs or rx skbs still around, free them.
1149  * Then free tx_skbuff and rx_skbuff
1150  */
1151 static void free_skb_resources(struct gfar_private *priv)
1152 {
1153         struct gfar_priv_tx_q *tx_queue = NULL;
1154         struct gfar_priv_rx_q *rx_queue = NULL;
1155         int i;
1156
1157         /* Go through all the buffer descriptors and free their data buffers */
1158         for (i = 0; i < priv->num_tx_queues; i++) {
1159                 struct netdev_queue *txq;
1160
1161                 tx_queue = priv->tx_queue[i];
1162                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1163                 if (tx_queue->tx_skbuff)
1164                         free_skb_tx_queue(tx_queue);
1165                 netdev_tx_reset_queue(txq);
1166         }
1167
1168         for (i = 0; i < priv->num_rx_queues; i++) {
1169                 rx_queue = priv->rx_queue[i];
1170                 if (rx_queue->rx_buff)
1171                         free_skb_rx_queue(rx_queue);
1172         }
1173
1174         dma_free_coherent(priv->dev,
1175                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1176                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1177                           priv->tx_queue[0]->tx_bd_base,
1178                           priv->tx_queue[0]->tx_bd_dma_base);
1179 }
1180
1181 void stop_gfar(struct net_device *dev)
1182 {
1183         struct gfar_private *priv = netdev_priv(dev);
1184
1185         netif_tx_stop_all_queues(dev);
1186
1187         smp_mb__before_atomic();
1188         set_bit(GFAR_DOWN, &priv->state);
1189         smp_mb__after_atomic();
1190
1191         disable_napi(priv);
1192
1193         /* disable ints and gracefully shut down Rx/Tx DMA */
1194         gfar_halt(priv);
1195
1196         phy_stop(dev->phydev);
1197
1198         free_skb_resources(priv);
1199 }
1200
1201 static void gfar_start(struct gfar_private *priv)
1202 {
1203         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1204         u32 tempval;
1205         int i = 0;
1206
1207         /* Enable Rx/Tx hw queues */
1208         gfar_write(&regs->rqueue, priv->rqueue);
1209         gfar_write(&regs->tqueue, priv->tqueue);
1210
1211         /* Initialize DMACTRL to have WWR and WOP */
1212         tempval = gfar_read(&regs->dmactrl);
1213         tempval |= DMACTRL_INIT_SETTINGS;
1214         gfar_write(&regs->dmactrl, tempval);
1215
1216         /* Make sure we aren't stopped */
1217         tempval = gfar_read(&regs->dmactrl);
1218         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1219         gfar_write(&regs->dmactrl, tempval);
1220
1221         for (i = 0; i < priv->num_grps; i++) {
1222                 regs = priv->gfargrp[i].regs;
1223                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1224                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1225                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1226         }
1227
1228         /* Enable Rx/Tx DMA */
1229         tempval = gfar_read(&regs->maccfg1);
1230         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1231         gfar_write(&regs->maccfg1, tempval);
1232
1233         gfar_ints_enable(priv);
1234
1235         netif_trans_update(priv->ndev); /* prevent tx timeout */
1236 }
1237
1238 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1239 {
1240         struct page *page;
1241         dma_addr_t addr;
1242
1243         page = dev_alloc_page();
1244         if (unlikely(!page))
1245                 return false;
1246
1247         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1248         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
1249                 __free_page(page);
1250
1251                 return false;
1252         }
1253
1254         rxb->dma = addr;
1255         rxb->page = page;
1256         rxb->page_offset = 0;
1257
1258         return true;
1259 }
1260
1261 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
1262 {
1263         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1264         struct gfar_extra_stats *estats = &priv->extra_stats;
1265
1266         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
1267         atomic64_inc(&estats->rx_alloc_err);
1268 }
1269
1270 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
1271                                 int alloc_cnt)
1272 {
1273         struct rxbd8 *bdp;
1274         struct gfar_rx_buff *rxb;
1275         int i;
1276
1277         i = rx_queue->next_to_use;
1278         bdp = &rx_queue->rx_bd_base[i];
1279         rxb = &rx_queue->rx_buff[i];
1280
1281         while (alloc_cnt--) {
1282                 /* try reuse page */
1283                 if (unlikely(!rxb->page)) {
1284                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
1285                                 gfar_rx_alloc_err(rx_queue);
1286                                 break;
1287                         }
1288                 }
1289
1290                 /* Setup the new RxBD */
1291                 gfar_init_rxbdp(rx_queue, bdp,
1292                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
1293
1294                 /* Update to the next pointer */
1295                 bdp++;
1296                 rxb++;
1297
1298                 if (unlikely(++i == rx_queue->rx_ring_size)) {
1299                         i = 0;
1300                         bdp = rx_queue->rx_bd_base;
1301                         rxb = rx_queue->rx_buff;
1302                 }
1303         }
1304
1305         rx_queue->next_to_use = i;
1306         rx_queue->next_to_alloc = i;
1307 }
1308
1309 static void gfar_init_bds(struct net_device *ndev)
1310 {
1311         struct gfar_private *priv = netdev_priv(ndev);
1312         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1313         struct gfar_priv_tx_q *tx_queue = NULL;
1314         struct gfar_priv_rx_q *rx_queue = NULL;
1315         struct txbd8 *txbdp;
1316         u32 __iomem *rfbptr;
1317         int i, j;
1318
1319         for (i = 0; i < priv->num_tx_queues; i++) {
1320                 tx_queue = priv->tx_queue[i];
1321                 /* Initialize some variables in our dev structure */
1322                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
1323                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
1324                 tx_queue->cur_tx = tx_queue->tx_bd_base;
1325                 tx_queue->skb_curtx = 0;
1326                 tx_queue->skb_dirtytx = 0;
1327
1328                 /* Initialize Transmit Descriptor Ring */
1329                 txbdp = tx_queue->tx_bd_base;
1330                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
1331                         txbdp->lstatus = 0;
1332                         txbdp->bufPtr = 0;
1333                         txbdp++;
1334                 }
1335
1336                 /* Set the last descriptor in the ring to indicate wrap */
1337                 txbdp--;
1338                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
1339                                             TXBD_WRAP);
1340         }
1341
1342         rfbptr = &regs->rfbptr0;
1343         for (i = 0; i < priv->num_rx_queues; i++) {
1344                 rx_queue = priv->rx_queue[i];
1345
1346                 rx_queue->next_to_clean = 0;
1347                 rx_queue->next_to_use = 0;
1348                 rx_queue->next_to_alloc = 0;
1349
1350                 /* make sure next_to_clean != next_to_use after this
1351                  * by leaving at least 1 unused descriptor
1352                  */
1353                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
1354
1355                 rx_queue->rfbptr = rfbptr;
1356                 rfbptr += 2;
1357         }
1358 }
1359
1360 static int gfar_alloc_skb_resources(struct net_device *ndev)
1361 {
1362         void *vaddr;
1363         dma_addr_t addr;
1364         int i, j;
1365         struct gfar_private *priv = netdev_priv(ndev);
1366         struct device *dev = priv->dev;
1367         struct gfar_priv_tx_q *tx_queue = NULL;
1368         struct gfar_priv_rx_q *rx_queue = NULL;
1369
1370         priv->total_tx_ring_size = 0;
1371         for (i = 0; i < priv->num_tx_queues; i++)
1372                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
1373
1374         priv->total_rx_ring_size = 0;
1375         for (i = 0; i < priv->num_rx_queues; i++)
1376                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
1377
1378         /* Allocate memory for the buffer descriptors */
1379         vaddr = dma_alloc_coherent(dev,
1380                                    (priv->total_tx_ring_size *
1381                                     sizeof(struct txbd8)) +
1382                                    (priv->total_rx_ring_size *
1383                                     sizeof(struct rxbd8)),
1384                                    &addr, GFP_KERNEL);
1385         if (!vaddr)
1386                 return -ENOMEM;
1387
1388         for (i = 0; i < priv->num_tx_queues; i++) {
1389                 tx_queue = priv->tx_queue[i];
1390                 tx_queue->tx_bd_base = vaddr;
1391                 tx_queue->tx_bd_dma_base = addr;
1392                 tx_queue->dev = ndev;
1393                 /* enet DMA only understands physical addresses */
1394                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1395                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1396         }
1397
1398         /* Start the rx descriptor ring where the tx ring leaves off */
1399         for (i = 0; i < priv->num_rx_queues; i++) {
1400                 rx_queue = priv->rx_queue[i];
1401                 rx_queue->rx_bd_base = vaddr;
1402                 rx_queue->rx_bd_dma_base = addr;
1403                 rx_queue->ndev = ndev;
1404                 rx_queue->dev = dev;
1405                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1406                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1407         }
1408
1409         /* Setup the skbuff rings */
1410         for (i = 0; i < priv->num_tx_queues; i++) {
1411                 tx_queue = priv->tx_queue[i];
1412                 tx_queue->tx_skbuff =
1413                         kmalloc_array(tx_queue->tx_ring_size,
1414                                       sizeof(*tx_queue->tx_skbuff),
1415                                       GFP_KERNEL);
1416                 if (!tx_queue->tx_skbuff)
1417                         goto cleanup;
1418
1419                 for (j = 0; j < tx_queue->tx_ring_size; j++)
1420                         tx_queue->tx_skbuff[j] = NULL;
1421         }
1422
1423         for (i = 0; i < priv->num_rx_queues; i++) {
1424                 rx_queue = priv->rx_queue[i];
1425                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
1426                                             sizeof(*rx_queue->rx_buff),
1427                                             GFP_KERNEL);
1428                 if (!rx_queue->rx_buff)
1429                         goto cleanup;
1430         }
1431
1432         gfar_init_bds(ndev);
1433
1434         return 0;
1435
1436 cleanup:
1437         free_skb_resources(priv);
1438         return -ENOMEM;
1439 }
1440
1441 /* Bring the controller up and running */
1442 int startup_gfar(struct net_device *ndev)
1443 {
1444         struct gfar_private *priv = netdev_priv(ndev);
1445         int err;
1446
1447         gfar_mac_reset(priv);
1448
1449         err = gfar_alloc_skb_resources(ndev);
1450         if (err)
1451                 return err;
1452
1453         gfar_init_tx_rx_base(priv);
1454
1455         smp_mb__before_atomic();
1456         clear_bit(GFAR_DOWN, &priv->state);
1457         smp_mb__after_atomic();
1458
1459         /* Start Rx/Tx DMA and enable the interrupts */
1460         gfar_start(priv);
1461
1462         /* force link state update after mac reset */
1463         priv->oldlink = 0;
1464         priv->oldspeed = 0;
1465         priv->oldduplex = -1;
1466
1467         phy_start(ndev->phydev);
1468
1469         enable_napi(priv);
1470
1471         netif_tx_wake_all_queues(ndev);
1472
1473         return 0;
1474 }
1475
1476 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
1477 {
1478         struct net_device *ndev = priv->ndev;
1479         struct phy_device *phydev = ndev->phydev;
1480         u32 val = 0;
1481
1482         if (!phydev->duplex)
1483                 return val;
1484
1485         if (!priv->pause_aneg_en) {
1486                 if (priv->tx_pause_en)
1487                         val |= MACCFG1_TX_FLOW;
1488                 if (priv->rx_pause_en)
1489                         val |= MACCFG1_RX_FLOW;
1490         } else {
1491                 u16 lcl_adv, rmt_adv;
1492                 u8 flowctrl;
1493                 /* get link partner capabilities */
1494                 rmt_adv = 0;
1495                 if (phydev->pause)
1496                         rmt_adv = LPA_PAUSE_CAP;
1497                 if (phydev->asym_pause)
1498                         rmt_adv |= LPA_PAUSE_ASYM;
1499
1500                 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1501                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1502                 if (flowctrl & FLOW_CTRL_TX)
1503                         val |= MACCFG1_TX_FLOW;
1504                 if (flowctrl & FLOW_CTRL_RX)
1505                         val |= MACCFG1_RX_FLOW;
1506         }
1507
1508         return val;
1509 }
1510
1511 static noinline void gfar_update_link_state(struct gfar_private *priv)
1512 {
1513         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1514         struct net_device *ndev = priv->ndev;
1515         struct phy_device *phydev = ndev->phydev;
1516         struct gfar_priv_rx_q *rx_queue = NULL;
1517         int i;
1518
1519         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
1520                 return;
1521
1522         if (phydev->link) {
1523                 u32 tempval1 = gfar_read(&regs->maccfg1);
1524                 u32 tempval = gfar_read(&regs->maccfg2);
1525                 u32 ecntrl = gfar_read(&regs->ecntrl);
1526                 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
1527
1528                 if (phydev->duplex != priv->oldduplex) {
1529                         if (!(phydev->duplex))
1530                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1531                         else
1532                                 tempval |= MACCFG2_FULL_DUPLEX;
1533
1534                         priv->oldduplex = phydev->duplex;
1535                 }
1536
1537                 if (phydev->speed != priv->oldspeed) {
1538                         switch (phydev->speed) {
1539                         case 1000:
1540                                 tempval =
1541                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1542
1543                                 ecntrl &= ~(ECNTRL_R100);
1544                                 break;
1545                         case 100:
1546                         case 10:
1547                                 tempval =
1548                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1549
1550                                 /* Reduced mode distinguishes
1551                                  * between 10 and 100
1552                                  */
1553                                 if (phydev->speed == SPEED_100)
1554                                         ecntrl |= ECNTRL_R100;
1555                                 else
1556                                         ecntrl &= ~(ECNTRL_R100);
1557                                 break;
1558                         default:
1559                                 netif_warn(priv, link, priv->ndev,
1560                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
1561                                            phydev->speed);
1562                                 break;
1563                         }
1564
1565                         priv->oldspeed = phydev->speed;
1566                 }
1567
1568                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1569                 tempval1 |= gfar_get_flowctrl_cfg(priv);
1570
1571                 /* Turn last free buffer recording on */
1572                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
1573                         for (i = 0; i < priv->num_rx_queues; i++) {
1574                                 u32 bdp_dma;
1575
1576                                 rx_queue = priv->rx_queue[i];
1577                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
1578                                 gfar_write(rx_queue->rfbptr, bdp_dma);
1579                         }
1580
1581                         priv->tx_actual_en = 1;
1582                 }
1583
1584                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
1585                         priv->tx_actual_en = 0;
1586
1587                 gfar_write(&regs->maccfg1, tempval1);
1588                 gfar_write(&regs->maccfg2, tempval);
1589                 gfar_write(&regs->ecntrl, ecntrl);
1590
1591                 if (!priv->oldlink)
1592                         priv->oldlink = 1;
1593
1594         } else if (priv->oldlink) {
1595                 priv->oldlink = 0;
1596                 priv->oldspeed = 0;
1597                 priv->oldduplex = -1;
1598         }
1599
1600         if (netif_msg_link(priv))
1601                 phy_print_status(phydev);
1602 }
1603
1604 /* Called every time the controller might need to be made
1605  * aware of new link state.  The PHY code conveys this
1606  * information through variables in the phydev structure, and this
1607  * function converts those variables into the appropriate
1608  * register values, and can bring down the device if needed.
1609  */
1610 static void adjust_link(struct net_device *dev)
1611 {
1612         struct gfar_private *priv = netdev_priv(dev);
1613         struct phy_device *phydev = dev->phydev;
1614
1615         if (unlikely(phydev->link != priv->oldlink ||
1616                      (phydev->link && (phydev->duplex != priv->oldduplex ||
1617                                        phydev->speed != priv->oldspeed))))
1618                 gfar_update_link_state(priv);
1619 }
1620
1621 /* Initialize TBI PHY interface for communicating with the
1622  * SERDES lynx PHY on the chip.  We communicate with this PHY
1623  * through the MDIO bus on each controller, treating it as a
1624  * "normal" PHY at the address found in the TBIPA register.  We assume
1625  * that the TBIPA register is valid.  Either the MDIO bus code will set
1626  * it to a value that doesn't conflict with other PHYs on the bus, or the
1627  * value doesn't matter, as there are no other PHYs on the bus.
1628  */
1629 static void gfar_configure_serdes(struct net_device *dev)
1630 {
1631         struct gfar_private *priv = netdev_priv(dev);
1632         struct phy_device *tbiphy;
1633
1634         if (!priv->tbi_node) {
1635                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1636                                     "device tree specify a tbi-handle\n");
1637                 return;
1638         }
1639
1640         tbiphy = of_phy_find_device(priv->tbi_node);
1641         if (!tbiphy) {
1642                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1643                 return;
1644         }
1645
1646         /* If the link is already up, we must already be ok, and don't need to
1647          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1648          * everything for us?  Resetting it takes the link down and requires
1649          * several seconds for it to come back.
1650          */
1651         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1652                 put_device(&tbiphy->mdio.dev);
1653                 return;
1654         }
1655
1656         /* Single clk mode, mii mode off(for serdes communication) */
1657         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1658
1659         phy_write(tbiphy, MII_ADVERTISE,
1660                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1661                   ADVERTISE_1000XPSE_ASYM);
1662
1663         phy_write(tbiphy, MII_BMCR,
1664                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1665                   BMCR_SPEED1000);
1666
1667         put_device(&tbiphy->mdio.dev);
1668 }
1669
1670 /* Initializes driver's PHY state, and attaches to the PHY.
1671  * Returns 0 on success.
1672  */
1673 static int init_phy(struct net_device *dev)
1674 {
1675         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1676         struct gfar_private *priv = netdev_priv(dev);
1677         phy_interface_t interface = priv->interface;
1678         struct phy_device *phydev;
1679         struct ethtool_eee edata;
1680
1681         linkmode_set_bit_array(phy_10_100_features_array,
1682                                ARRAY_SIZE(phy_10_100_features_array),
1683                                mask);
1684         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1685         linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1686         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1687                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask);
1688
1689         priv->oldlink = 0;
1690         priv->oldspeed = 0;
1691         priv->oldduplex = -1;
1692
1693         phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1694                                 interface);
1695         if (!phydev) {
1696                 dev_err(&dev->dev, "could not attach to PHY\n");
1697                 return -ENODEV;
1698         }
1699
1700         if (interface == PHY_INTERFACE_MODE_SGMII)
1701                 gfar_configure_serdes(dev);
1702
1703         /* Remove any features not supported by the controller */
1704         linkmode_and(phydev->supported, phydev->supported, mask);
1705         linkmode_copy(phydev->advertising, phydev->supported);
1706
1707         /* Add support for flow control */
1708         phy_support_asym_pause(phydev);
1709
1710         /* disable EEE autoneg, EEE not supported by eTSEC */
1711         memset(&edata, 0, sizeof(struct ethtool_eee));
1712         phy_ethtool_set_eee(phydev, &edata);
1713
1714         return 0;
1715 }
1716
1717 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1718 {
1719         struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
1720
1721         memset(fcb, 0, GMAC_FCB_LEN);
1722
1723         return fcb;
1724 }
1725
1726 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1727                                     int fcb_length)
1728 {
1729         /* If we're here, it's a IP packet with a TCP or UDP
1730          * payload.  We set it to checksum, using a pseudo-header
1731          * we provide
1732          */
1733         u8 flags = TXFCB_DEFAULT;
1734
1735         /* Tell the controller what the protocol is
1736          * And provide the already calculated phcs
1737          */
1738         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1739                 flags |= TXFCB_UDP;
1740                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
1741         } else
1742                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
1743
1744         /* l3os is the distance between the start of the
1745          * frame (skb->data) and the start of the IP hdr.
1746          * l4os is the distance between the start of the
1747          * l3 hdr and the l4 hdr
1748          */
1749         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
1750         fcb->l4os = skb_network_header_len(skb);
1751
1752         fcb->flags = flags;
1753 }
1754
1755 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1756 {
1757         fcb->flags |= TXFCB_VLN;
1758         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
1759 }
1760
1761 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1762                                       struct txbd8 *base, int ring_size)
1763 {
1764         struct txbd8 *new_bd = bdp + stride;
1765
1766         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1767 }
1768
1769 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1770                                       int ring_size)
1771 {
1772         return skip_txbd(bdp, 1, base, ring_size);
1773 }
1774
1775 /* eTSEC12: csum generation not supported for some fcb offsets */
1776 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
1777                                        unsigned long fcb_addr)
1778 {
1779         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
1780                (fcb_addr % 0x20) > 0x18);
1781 }
1782
1783 /* eTSEC76: csum generation for frames larger than 2500 may
1784  * cause excess delays before start of transmission
1785  */
1786 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
1787                                        unsigned int len)
1788 {
1789         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
1790                (len > 2500));
1791 }
1792
1793 /* This is called by the kernel when a frame is ready for transmission.
1794  * It is pointed to by the dev->hard_start_xmit function pointer
1795  */
1796 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1797 {
1798         struct gfar_private *priv = netdev_priv(dev);
1799         struct gfar_priv_tx_q *tx_queue = NULL;
1800         struct netdev_queue *txq;
1801         struct gfar __iomem *regs = NULL;
1802         struct txfcb *fcb = NULL;
1803         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1804         u32 lstatus;
1805         skb_frag_t *frag;
1806         int i, rq = 0;
1807         int do_tstamp, do_csum, do_vlan;
1808         u32 bufaddr;
1809         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
1810
1811         rq = skb->queue_mapping;
1812         tx_queue = priv->tx_queue[rq];
1813         txq = netdev_get_tx_queue(dev, rq);
1814         base = tx_queue->tx_bd_base;
1815         regs = tx_queue->grp->regs;
1816
1817         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
1818         do_vlan = skb_vlan_tag_present(skb);
1819         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1820                     priv->hwts_tx_en;
1821
1822         if (do_csum || do_vlan)
1823                 fcb_len = GMAC_FCB_LEN;
1824
1825         /* check if time stamp should be generated */
1826         if (unlikely(do_tstamp))
1827                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1828
1829         /* make space for additional header when fcb is needed */
1830         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
1831                 struct sk_buff *skb_new;
1832
1833                 skb_new = skb_realloc_headroom(skb, fcb_len);
1834                 if (!skb_new) {
1835                         dev->stats.tx_errors++;
1836                         dev_kfree_skb_any(skb);
1837                         return NETDEV_TX_OK;
1838                 }
1839
1840                 if (skb->sk)
1841                         skb_set_owner_w(skb_new, skb->sk);
1842                 dev_consume_skb_any(skb);
1843                 skb = skb_new;
1844         }
1845
1846         /* total number of fragments in the SKB */
1847         nr_frags = skb_shinfo(skb)->nr_frags;
1848
1849         /* calculate the required number of TxBDs for this skb */
1850         if (unlikely(do_tstamp))
1851                 nr_txbds = nr_frags + 2;
1852         else
1853                 nr_txbds = nr_frags + 1;
1854
1855         /* check if there is space to queue this packet */
1856         if (nr_txbds > tx_queue->num_txbdfree) {
1857                 /* no space, stop the queue */
1858                 netif_tx_stop_queue(txq);
1859                 dev->stats.tx_fifo_errors++;
1860                 return NETDEV_TX_BUSY;
1861         }
1862
1863         /* Update transmit stats */
1864         bytes_sent = skb->len;
1865         tx_queue->stats.tx_bytes += bytes_sent;
1866         /* keep Tx bytes on wire for BQL accounting */
1867         GFAR_CB(skb)->bytes_sent = bytes_sent;
1868         tx_queue->stats.tx_packets++;
1869
1870         txbdp = txbdp_start = tx_queue->cur_tx;
1871         lstatus = be32_to_cpu(txbdp->lstatus);
1872
1873         /* Add TxPAL between FCB and frame if required */
1874         if (unlikely(do_tstamp)) {
1875                 skb_push(skb, GMAC_TXPAL_LEN);
1876                 memset(skb->data, 0, GMAC_TXPAL_LEN);
1877         }
1878
1879         /* Add TxFCB if required */
1880         if (fcb_len) {
1881                 fcb = gfar_add_fcb(skb);
1882                 lstatus |= BD_LFLAG(TXBD_TOE);
1883         }
1884
1885         /* Set up checksumming */
1886         if (do_csum) {
1887                 gfar_tx_checksum(skb, fcb, fcb_len);
1888
1889                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
1890                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
1891                         __skb_pull(skb, GMAC_FCB_LEN);
1892                         skb_checksum_help(skb);
1893                         if (do_vlan || do_tstamp) {
1894                                 /* put back a new fcb for vlan/tstamp TOE */
1895                                 fcb = gfar_add_fcb(skb);
1896                         } else {
1897                                 /* Tx TOE not used */
1898                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
1899                                 fcb = NULL;
1900                         }
1901                 }
1902         }
1903
1904         if (do_vlan)
1905                 gfar_tx_vlan(skb, fcb);
1906
1907         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
1908                                  DMA_TO_DEVICE);
1909         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1910                 goto dma_map_err;
1911
1912         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1913
1914         /* Time stamp insertion requires one additional TxBD */
1915         if (unlikely(do_tstamp))
1916                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
1917                                                  tx_queue->tx_ring_size);
1918
1919         if (likely(!nr_frags)) {
1920                 if (likely(!do_tstamp))
1921                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1922         } else {
1923                 u32 lstatus_start = lstatus;
1924
1925                 /* Place the fragment addresses and lengths into the TxBDs */
1926                 frag = &skb_shinfo(skb)->frags[0];
1927                 for (i = 0; i < nr_frags; i++, frag++) {
1928                         unsigned int size;
1929
1930                         /* Point at the next BD, wrapping as needed */
1931                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1932
1933                         size = skb_frag_size(frag);
1934
1935                         lstatus = be32_to_cpu(txbdp->lstatus) | size |
1936                                   BD_LFLAG(TXBD_READY);
1937
1938                         /* Handle the last BD specially */
1939                         if (i == nr_frags - 1)
1940                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1941
1942                         bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
1943                                                    size, DMA_TO_DEVICE);
1944                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1945                                 goto dma_map_err;
1946
1947                         /* set the TxBD length and buffer pointer */
1948                         txbdp->bufPtr = cpu_to_be32(bufaddr);
1949                         txbdp->lstatus = cpu_to_be32(lstatus);
1950                 }
1951
1952                 lstatus = lstatus_start;
1953         }
1954
1955         /* If time stamping is requested one additional TxBD must be set up. The
1956          * first TxBD points to the FCB and must have a data length of
1957          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
1958          * the full frame length.
1959          */
1960         if (unlikely(do_tstamp)) {
1961                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
1962
1963                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
1964                 bufaddr += fcb_len;
1965
1966                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
1967                               (skb_headlen(skb) - fcb_len);
1968                 if (!nr_frags)
1969                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1970
1971                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
1972                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
1973                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
1974
1975                 /* Setup tx hardware time stamping */
1976                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1977                 fcb->ptp = 1;
1978         } else {
1979                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1980         }
1981
1982         netdev_tx_sent_queue(txq, bytes_sent);
1983
1984         gfar_wmb();
1985
1986         txbdp_start->lstatus = cpu_to_be32(lstatus);
1987
1988         gfar_wmb(); /* force lstatus write before tx_skbuff */
1989
1990         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1991
1992         /* Update the current skb pointer to the next entry we will use
1993          * (wrapping if necessary)
1994          */
1995         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1996                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1997
1998         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1999
2000         /* We can work in parallel with gfar_clean_tx_ring(), except
2001          * when modifying num_txbdfree. Note that we didn't grab the lock
2002          * when we were reading the num_txbdfree and checking for available
2003          * space, that's because outside of this function it can only grow.
2004          */
2005         spin_lock_bh(&tx_queue->txlock);
2006         /* reduce TxBD free count */
2007         tx_queue->num_txbdfree -= (nr_txbds);
2008         spin_unlock_bh(&tx_queue->txlock);
2009
2010         /* If the next BD still needs to be cleaned up, then the bds
2011          * are full.  We need to tell the kernel to stop sending us stuff.
2012          */
2013         if (!tx_queue->num_txbdfree) {
2014                 netif_tx_stop_queue(txq);
2015
2016                 dev->stats.tx_fifo_errors++;
2017         }
2018
2019         /* Tell the DMA to go go go */
2020         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2021
2022         return NETDEV_TX_OK;
2023
2024 dma_map_err:
2025         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2026         if (do_tstamp)
2027                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2028         for (i = 0; i < nr_frags; i++) {
2029                 lstatus = be32_to_cpu(txbdp->lstatus);
2030                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2031                         break;
2032
2033                 lstatus &= ~BD_LFLAG(TXBD_READY);
2034                 txbdp->lstatus = cpu_to_be32(lstatus);
2035                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2036                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2037                                DMA_TO_DEVICE);
2038                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2039         }
2040         gfar_wmb();
2041         dev_kfree_skb_any(skb);
2042         return NETDEV_TX_OK;
2043 }
2044
2045 /* Changes the mac address if the controller is not running. */
2046 static int gfar_set_mac_address(struct net_device *dev)
2047 {
2048         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2049
2050         return 0;
2051 }
2052
2053 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2054 {
2055         struct gfar_private *priv = netdev_priv(dev);
2056
2057         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2058                 cpu_relax();
2059
2060         if (dev->flags & IFF_UP)
2061                 stop_gfar(dev);
2062
2063         dev->mtu = new_mtu;
2064
2065         if (dev->flags & IFF_UP)
2066                 startup_gfar(dev);
2067
2068         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2069
2070         return 0;
2071 }
2072
2073 static void reset_gfar(struct net_device *ndev)
2074 {
2075         struct gfar_private *priv = netdev_priv(ndev);
2076
2077         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2078                 cpu_relax();
2079
2080         stop_gfar(ndev);
2081         startup_gfar(ndev);
2082
2083         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2084 }
2085
2086 /* gfar_reset_task gets scheduled when a packet has not been
2087  * transmitted after a set amount of time.
2088  * For now, assume that clearing out all the structures, and
2089  * starting over will fix the problem.
2090  */
2091 static void gfar_reset_task(struct work_struct *work)
2092 {
2093         struct gfar_private *priv = container_of(work, struct gfar_private,
2094                                                  reset_task);
2095         reset_gfar(priv->ndev);
2096 }
2097
2098 static void gfar_timeout(struct net_device *dev, unsigned int txqueue)
2099 {
2100         struct gfar_private *priv = netdev_priv(dev);
2101
2102         dev->stats.tx_errors++;
2103         schedule_work(&priv->reset_task);
2104 }
2105
2106 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
2107 {
2108         struct hwtstamp_config config;
2109         struct gfar_private *priv = netdev_priv(netdev);
2110
2111         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2112                 return -EFAULT;
2113
2114         /* reserved for future extensions */
2115         if (config.flags)
2116                 return -EINVAL;
2117
2118         switch (config.tx_type) {
2119         case HWTSTAMP_TX_OFF:
2120                 priv->hwts_tx_en = 0;
2121                 break;
2122         case HWTSTAMP_TX_ON:
2123                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2124                         return -ERANGE;
2125                 priv->hwts_tx_en = 1;
2126                 break;
2127         default:
2128                 return -ERANGE;
2129         }
2130
2131         switch (config.rx_filter) {
2132         case HWTSTAMP_FILTER_NONE:
2133                 if (priv->hwts_rx_en) {
2134                         priv->hwts_rx_en = 0;
2135                         reset_gfar(netdev);
2136                 }
2137                 break;
2138         default:
2139                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2140                         return -ERANGE;
2141                 if (!priv->hwts_rx_en) {
2142                         priv->hwts_rx_en = 1;
2143                         reset_gfar(netdev);
2144                 }
2145                 config.rx_filter = HWTSTAMP_FILTER_ALL;
2146                 break;
2147         }
2148
2149         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2150                 -EFAULT : 0;
2151 }
2152
2153 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
2154 {
2155         struct hwtstamp_config config;
2156         struct gfar_private *priv = netdev_priv(netdev);
2157
2158         config.flags = 0;
2159         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2160         config.rx_filter = (priv->hwts_rx_en ?
2161                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
2162
2163         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2164                 -EFAULT : 0;
2165 }
2166
2167 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2168 {
2169         struct phy_device *phydev = dev->phydev;
2170
2171         if (!netif_running(dev))
2172                 return -EINVAL;
2173
2174         if (cmd == SIOCSHWTSTAMP)
2175                 return gfar_hwtstamp_set(dev, rq);
2176         if (cmd == SIOCGHWTSTAMP)
2177                 return gfar_hwtstamp_get(dev, rq);
2178
2179         if (!phydev)
2180                 return -ENODEV;
2181
2182         return phy_mii_ioctl(phydev, rq, cmd);
2183 }
2184
2185 /* Interrupt Handler for Transmit complete */
2186 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2187 {
2188         struct net_device *dev = tx_queue->dev;
2189         struct netdev_queue *txq;
2190         struct gfar_private *priv = netdev_priv(dev);
2191         struct txbd8 *bdp, *next = NULL;
2192         struct txbd8 *lbdp = NULL;
2193         struct txbd8 *base = tx_queue->tx_bd_base;
2194         struct sk_buff *skb;
2195         int skb_dirtytx;
2196         int tx_ring_size = tx_queue->tx_ring_size;
2197         int frags = 0, nr_txbds = 0;
2198         int i;
2199         int howmany = 0;
2200         int tqi = tx_queue->qindex;
2201         unsigned int bytes_sent = 0;
2202         u32 lstatus;
2203         size_t buflen;
2204
2205         txq = netdev_get_tx_queue(dev, tqi);
2206         bdp = tx_queue->dirty_tx;
2207         skb_dirtytx = tx_queue->skb_dirtytx;
2208
2209         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2210                 bool do_tstamp;
2211
2212                 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2213                             priv->hwts_tx_en;
2214
2215                 frags = skb_shinfo(skb)->nr_frags;
2216
2217                 /* When time stamping, one additional TxBD must be freed.
2218                  * Also, we need to dma_unmap_single() the TxPAL.
2219                  */
2220                 if (unlikely(do_tstamp))
2221                         nr_txbds = frags + 2;
2222                 else
2223                         nr_txbds = frags + 1;
2224
2225                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2226
2227                 lstatus = be32_to_cpu(lbdp->lstatus);
2228
2229                 /* Only clean completed frames */
2230                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2231                     (lstatus & BD_LENGTH_MASK))
2232                         break;
2233
2234                 if (unlikely(do_tstamp)) {
2235                         next = next_txbd(bdp, base, tx_ring_size);
2236                         buflen = be16_to_cpu(next->length) +
2237                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2238                 } else
2239                         buflen = be16_to_cpu(bdp->length);
2240
2241                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2242                                  buflen, DMA_TO_DEVICE);
2243
2244                 if (unlikely(do_tstamp)) {
2245                         struct skb_shared_hwtstamps shhwtstamps;
2246                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2247                                           ~0x7UL);
2248
2249                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2250                         shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2251                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2252                         skb_tstamp_tx(skb, &shhwtstamps);
2253                         gfar_clear_txbd_status(bdp);
2254                         bdp = next;
2255                 }
2256
2257                 gfar_clear_txbd_status(bdp);
2258                 bdp = next_txbd(bdp, base, tx_ring_size);
2259
2260                 for (i = 0; i < frags; i++) {
2261                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2262                                        be16_to_cpu(bdp->length),
2263                                        DMA_TO_DEVICE);
2264                         gfar_clear_txbd_status(bdp);
2265                         bdp = next_txbd(bdp, base, tx_ring_size);
2266                 }
2267
2268                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2269
2270                 dev_kfree_skb_any(skb);
2271
2272                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2273
2274                 skb_dirtytx = (skb_dirtytx + 1) &
2275                               TX_RING_MOD_MASK(tx_ring_size);
2276
2277                 howmany++;
2278                 spin_lock(&tx_queue->txlock);
2279                 tx_queue->num_txbdfree += nr_txbds;
2280                 spin_unlock(&tx_queue->txlock);
2281         }
2282
2283         /* If we freed a buffer, we can restart transmission, if necessary */
2284         if (tx_queue->num_txbdfree &&
2285             netif_tx_queue_stopped(txq) &&
2286             !(test_bit(GFAR_DOWN, &priv->state)))
2287                 netif_wake_subqueue(priv->ndev, tqi);
2288
2289         /* Update dirty indicators */
2290         tx_queue->skb_dirtytx = skb_dirtytx;
2291         tx_queue->dirty_tx = bdp;
2292
2293         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2294 }
2295
2296 static void count_errors(u32 lstatus, struct net_device *ndev)
2297 {
2298         struct gfar_private *priv = netdev_priv(ndev);
2299         struct net_device_stats *stats = &ndev->stats;
2300         struct gfar_extra_stats *estats = &priv->extra_stats;
2301
2302         /* If the packet was truncated, none of the other errors matter */
2303         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2304                 stats->rx_length_errors++;
2305
2306                 atomic64_inc(&estats->rx_trunc);
2307
2308                 return;
2309         }
2310         /* Count the errors, if there were any */
2311         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2312                 stats->rx_length_errors++;
2313
2314                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2315                         atomic64_inc(&estats->rx_large);
2316                 else
2317                         atomic64_inc(&estats->rx_short);
2318         }
2319         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2320                 stats->rx_frame_errors++;
2321                 atomic64_inc(&estats->rx_nonoctet);
2322         }
2323         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2324                 atomic64_inc(&estats->rx_crcerr);
2325                 stats->rx_crc_errors++;
2326         }
2327         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2328                 atomic64_inc(&estats->rx_overrun);
2329                 stats->rx_over_errors++;
2330         }
2331 }
2332
2333 static irqreturn_t gfar_receive(int irq, void *grp_id)
2334 {
2335         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2336         unsigned long flags;
2337         u32 imask, ievent;
2338
2339         ievent = gfar_read(&grp->regs->ievent);
2340
2341         if (unlikely(ievent & IEVENT_FGPI)) {
2342                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2343                 return IRQ_HANDLED;
2344         }
2345
2346         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2347                 spin_lock_irqsave(&grp->grplock, flags);
2348                 imask = gfar_read(&grp->regs->imask);
2349                 imask &= IMASK_RX_DISABLED;
2350                 gfar_write(&grp->regs->imask, imask);
2351                 spin_unlock_irqrestore(&grp->grplock, flags);
2352                 __napi_schedule(&grp->napi_rx);
2353         } else {
2354                 /* Clear IEVENT, so interrupts aren't called again
2355                  * because of the packets that have already arrived.
2356                  */
2357                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2358         }
2359
2360         return IRQ_HANDLED;
2361 }
2362
2363 /* Interrupt Handler for Transmit complete */
2364 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2365 {
2366         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2367         unsigned long flags;
2368         u32 imask;
2369
2370         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2371                 spin_lock_irqsave(&grp->grplock, flags);
2372                 imask = gfar_read(&grp->regs->imask);
2373                 imask &= IMASK_TX_DISABLED;
2374                 gfar_write(&grp->regs->imask, imask);
2375                 spin_unlock_irqrestore(&grp->grplock, flags);
2376                 __napi_schedule(&grp->napi_tx);
2377         } else {
2378                 /* Clear IEVENT, so interrupts aren't called again
2379                  * because of the packets that have already arrived.
2380                  */
2381                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2382         }
2383
2384         return IRQ_HANDLED;
2385 }
2386
2387 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2388                              struct sk_buff *skb, bool first)
2389 {
2390         int size = lstatus & BD_LENGTH_MASK;
2391         struct page *page = rxb->page;
2392
2393         if (likely(first)) {
2394                 skb_put(skb, size);
2395         } else {
2396                 /* the last fragments' length contains the full frame length */
2397                 if (lstatus & BD_LFLAG(RXBD_LAST))
2398                         size -= skb->len;
2399
2400                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2401                                 rxb->page_offset + RXBUF_ALIGNMENT,
2402                                 size, GFAR_RXB_TRUESIZE);
2403         }
2404
2405         /* try reuse page */
2406         if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2407                 return false;
2408
2409         /* change offset to the other half */
2410         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2411
2412         page_ref_inc(page);
2413
2414         return true;
2415 }
2416
2417 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2418                                struct gfar_rx_buff *old_rxb)
2419 {
2420         struct gfar_rx_buff *new_rxb;
2421         u16 nta = rxq->next_to_alloc;
2422
2423         new_rxb = &rxq->rx_buff[nta];
2424
2425         /* find next buf that can reuse a page */
2426         nta++;
2427         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2428
2429         /* copy page reference */
2430         *new_rxb = *old_rxb;
2431
2432         /* sync for use by the device */
2433         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2434                                          old_rxb->page_offset,
2435                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2436 }
2437
2438 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2439                                             u32 lstatus, struct sk_buff *skb)
2440 {
2441         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2442         struct page *page = rxb->page;
2443         bool first = false;
2444
2445         if (likely(!skb)) {
2446                 void *buff_addr = page_address(page) + rxb->page_offset;
2447
2448                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2449                 if (unlikely(!skb)) {
2450                         gfar_rx_alloc_err(rx_queue);
2451                         return NULL;
2452                 }
2453                 skb_reserve(skb, RXBUF_ALIGNMENT);
2454                 first = true;
2455         }
2456
2457         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2458                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2459
2460         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2461                 /* reuse the free half of the page */
2462                 gfar_reuse_rx_page(rx_queue, rxb);
2463         } else {
2464                 /* page cannot be reused, unmap it */
2465                 dma_unmap_page(rx_queue->dev, rxb->dma,
2466                                PAGE_SIZE, DMA_FROM_DEVICE);
2467         }
2468
2469         /* clear rxb content */
2470         rxb->page = NULL;
2471
2472         return skb;
2473 }
2474
2475 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2476 {
2477         /* If valid headers were found, and valid sums
2478          * were verified, then we tell the kernel that no
2479          * checksumming is necessary.  Otherwise, it is [FIXME]
2480          */
2481         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2482             (RXFCB_CIP | RXFCB_CTU))
2483                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2484         else
2485                 skb_checksum_none_assert(skb);
2486 }
2487
2488 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2489 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2490 {
2491         struct gfar_private *priv = netdev_priv(ndev);
2492         struct rxfcb *fcb = NULL;
2493
2494         /* fcb is at the beginning if exists */
2495         fcb = (struct rxfcb *)skb->data;
2496
2497         /* Remove the FCB from the skb
2498          * Remove the padded bytes, if there are any
2499          */
2500         if (priv->uses_rxfcb)
2501                 skb_pull(skb, GMAC_FCB_LEN);
2502
2503         /* Get receive timestamp from the skb */
2504         if (priv->hwts_rx_en) {
2505                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2506                 u64 *ns = (u64 *) skb->data;
2507
2508                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2509                 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2510         }
2511
2512         if (priv->padding)
2513                 skb_pull(skb, priv->padding);
2514
2515         /* Trim off the FCS */
2516         pskb_trim(skb, skb->len - ETH_FCS_LEN);
2517
2518         if (ndev->features & NETIF_F_RXCSUM)
2519                 gfar_rx_checksum(skb, fcb);
2520
2521         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2522          * Even if vlan rx accel is disabled, on some chips
2523          * RXFCB_VLN is pseudo randomly set.
2524          */
2525         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2526             be16_to_cpu(fcb->flags) & RXFCB_VLN)
2527                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2528                                        be16_to_cpu(fcb->vlctl));
2529 }
2530
2531 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2532  * until the budget/quota has been reached. Returns the number
2533  * of frames handled
2534  */
2535 static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
2536                               int rx_work_limit)
2537 {
2538         struct net_device *ndev = rx_queue->ndev;
2539         struct gfar_private *priv = netdev_priv(ndev);
2540         struct rxbd8 *bdp;
2541         int i, howmany = 0;
2542         struct sk_buff *skb = rx_queue->skb;
2543         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2544         unsigned int total_bytes = 0, total_pkts = 0;
2545
2546         /* Get the first full descriptor */
2547         i = rx_queue->next_to_clean;
2548
2549         while (rx_work_limit--) {
2550                 u32 lstatus;
2551
2552                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2553                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2554                         cleaned_cnt = 0;
2555                 }
2556
2557                 bdp = &rx_queue->rx_bd_base[i];
2558                 lstatus = be32_to_cpu(bdp->lstatus);
2559                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2560                         break;
2561
2562                 /* order rx buffer descriptor reads */
2563                 rmb();
2564
2565                 /* fetch next to clean buffer from the ring */
2566                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2567                 if (unlikely(!skb))
2568                         break;
2569
2570                 cleaned_cnt++;
2571                 howmany++;
2572
2573                 if (unlikely(++i == rx_queue->rx_ring_size))
2574                         i = 0;
2575
2576                 rx_queue->next_to_clean = i;
2577
2578                 /* fetch next buffer if not the last in frame */
2579                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2580                         continue;
2581
2582                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2583                         count_errors(lstatus, ndev);
2584
2585                         /* discard faulty buffer */
2586                         dev_kfree_skb(skb);
2587                         skb = NULL;
2588                         rx_queue->stats.rx_dropped++;
2589                         continue;
2590                 }
2591
2592                 gfar_process_frame(ndev, skb);
2593
2594                 /* Increment the number of packets */
2595                 total_pkts++;
2596                 total_bytes += skb->len;
2597
2598                 skb_record_rx_queue(skb, rx_queue->qindex);
2599
2600                 skb->protocol = eth_type_trans(skb, ndev);
2601
2602                 /* Send the packet up the stack */
2603                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2604
2605                 skb = NULL;
2606         }
2607
2608         /* Store incomplete frames for completion */
2609         rx_queue->skb = skb;
2610
2611         rx_queue->stats.rx_packets += total_pkts;
2612         rx_queue->stats.rx_bytes += total_bytes;
2613
2614         if (cleaned_cnt)
2615                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2616
2617         /* Update Last Free RxBD pointer for LFC */
2618         if (unlikely(priv->tx_actual_en)) {
2619                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
2620
2621                 gfar_write(rx_queue->rfbptr, bdp_dma);
2622         }
2623
2624         return howmany;
2625 }
2626
2627 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2628 {
2629         struct gfar_priv_grp *gfargrp =
2630                 container_of(napi, struct gfar_priv_grp, napi_rx);
2631         struct gfar __iomem *regs = gfargrp->regs;
2632         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2633         int work_done = 0;
2634
2635         /* Clear IEVENT, so interrupts aren't called again
2636          * because of the packets that have already arrived
2637          */
2638         gfar_write(&regs->ievent, IEVENT_RX_MASK);
2639
2640         work_done = gfar_clean_rx_ring(rx_queue, budget);
2641
2642         if (work_done < budget) {
2643                 u32 imask;
2644                 napi_complete_done(napi, work_done);
2645                 /* Clear the halt bit in RSTAT */
2646                 gfar_write(&regs->rstat, gfargrp->rstat);
2647
2648                 spin_lock_irq(&gfargrp->grplock);
2649                 imask = gfar_read(&regs->imask);
2650                 imask |= IMASK_RX_DEFAULT;
2651                 gfar_write(&regs->imask, imask);
2652                 spin_unlock_irq(&gfargrp->grplock);
2653         }
2654
2655         return work_done;
2656 }
2657
2658 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2659 {
2660         struct gfar_priv_grp *gfargrp =
2661                 container_of(napi, struct gfar_priv_grp, napi_tx);
2662         struct gfar __iomem *regs = gfargrp->regs;
2663         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2664         u32 imask;
2665
2666         /* Clear IEVENT, so interrupts aren't called again
2667          * because of the packets that have already arrived
2668          */
2669         gfar_write(&regs->ievent, IEVENT_TX_MASK);
2670
2671         /* run Tx cleanup to completion */
2672         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2673                 gfar_clean_tx_ring(tx_queue);
2674
2675         napi_complete(napi);
2676
2677         spin_lock_irq(&gfargrp->grplock);
2678         imask = gfar_read(&regs->imask);
2679         imask |= IMASK_TX_DEFAULT;
2680         gfar_write(&regs->imask, imask);
2681         spin_unlock_irq(&gfargrp->grplock);
2682
2683         return 0;
2684 }
2685
2686 static int gfar_poll_rx(struct napi_struct *napi, int budget)
2687 {
2688         struct gfar_priv_grp *gfargrp =
2689                 container_of(napi, struct gfar_priv_grp, napi_rx);
2690         struct gfar_private *priv = gfargrp->priv;
2691         struct gfar __iomem *regs = gfargrp->regs;
2692         struct gfar_priv_rx_q *rx_queue = NULL;
2693         int work_done = 0, work_done_per_q = 0;
2694         int i, budget_per_q = 0;
2695         unsigned long rstat_rxf;
2696         int num_act_queues;
2697
2698         /* Clear IEVENT, so interrupts aren't called again
2699          * because of the packets that have already arrived
2700          */
2701         gfar_write(&regs->ievent, IEVENT_RX_MASK);
2702
2703         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2704
2705         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2706         if (num_act_queues)
2707                 budget_per_q = budget/num_act_queues;
2708
2709         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2710                 /* skip queue if not active */
2711                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2712                         continue;
2713
2714                 rx_queue = priv->rx_queue[i];
2715                 work_done_per_q =
2716                         gfar_clean_rx_ring(rx_queue, budget_per_q);
2717                 work_done += work_done_per_q;
2718
2719                 /* finished processing this queue */
2720                 if (work_done_per_q < budget_per_q) {
2721                         /* clear active queue hw indication */
2722                         gfar_write(&regs->rstat,
2723                                    RSTAT_CLEAR_RXF0 >> i);
2724                         num_act_queues--;
2725
2726                         if (!num_act_queues)
2727                                 break;
2728                 }
2729         }
2730
2731         if (!num_act_queues) {
2732                 u32 imask;
2733                 napi_complete_done(napi, work_done);
2734
2735                 /* Clear the halt bit in RSTAT */
2736                 gfar_write(&regs->rstat, gfargrp->rstat);
2737
2738                 spin_lock_irq(&gfargrp->grplock);
2739                 imask = gfar_read(&regs->imask);
2740                 imask |= IMASK_RX_DEFAULT;
2741                 gfar_write(&regs->imask, imask);
2742                 spin_unlock_irq(&gfargrp->grplock);
2743         }
2744
2745         return work_done;
2746 }
2747
2748 static int gfar_poll_tx(struct napi_struct *napi, int budget)
2749 {
2750         struct gfar_priv_grp *gfargrp =
2751                 container_of(napi, struct gfar_priv_grp, napi_tx);
2752         struct gfar_private *priv = gfargrp->priv;
2753         struct gfar __iomem *regs = gfargrp->regs;
2754         struct gfar_priv_tx_q *tx_queue = NULL;
2755         int has_tx_work = 0;
2756         int i;
2757
2758         /* Clear IEVENT, so interrupts aren't called again
2759          * because of the packets that have already arrived
2760          */
2761         gfar_write(&regs->ievent, IEVENT_TX_MASK);
2762
2763         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2764                 tx_queue = priv->tx_queue[i];
2765                 /* run Tx cleanup to completion */
2766                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2767                         gfar_clean_tx_ring(tx_queue);
2768                         has_tx_work = 1;
2769                 }
2770         }
2771
2772         if (!has_tx_work) {
2773                 u32 imask;
2774                 napi_complete(napi);
2775
2776                 spin_lock_irq(&gfargrp->grplock);
2777                 imask = gfar_read(&regs->imask);
2778                 imask |= IMASK_TX_DEFAULT;
2779                 gfar_write(&regs->imask, imask);
2780                 spin_unlock_irq(&gfargrp->grplock);
2781         }
2782
2783         return 0;
2784 }
2785
2786 /* GFAR error interrupt handler */
2787 static irqreturn_t gfar_error(int irq, void *grp_id)
2788 {
2789         struct gfar_priv_grp *gfargrp = grp_id;
2790         struct gfar __iomem *regs = gfargrp->regs;
2791         struct gfar_private *priv= gfargrp->priv;
2792         struct net_device *dev = priv->ndev;
2793
2794         /* Save ievent for future reference */
2795         u32 events = gfar_read(&regs->ievent);
2796
2797         /* Clear IEVENT */
2798         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
2799
2800         /* Magic Packet is not an error. */
2801         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2802             (events & IEVENT_MAG))
2803                 events &= ~IEVENT_MAG;
2804
2805         /* Hmm... */
2806         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2807                 netdev_dbg(dev,
2808                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
2809                            events, gfar_read(&regs->imask));
2810
2811         /* Update the error counters */
2812         if (events & IEVENT_TXE) {
2813                 dev->stats.tx_errors++;
2814
2815                 if (events & IEVENT_LC)
2816                         dev->stats.tx_window_errors++;
2817                 if (events & IEVENT_CRL)
2818                         dev->stats.tx_aborted_errors++;
2819                 if (events & IEVENT_XFUN) {
2820                         netif_dbg(priv, tx_err, dev,
2821                                   "TX FIFO underrun, packet dropped\n");
2822                         dev->stats.tx_dropped++;
2823                         atomic64_inc(&priv->extra_stats.tx_underrun);
2824
2825                         schedule_work(&priv->reset_task);
2826                 }
2827                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
2828         }
2829         if (events & IEVENT_BSY) {
2830                 dev->stats.rx_over_errors++;
2831                 atomic64_inc(&priv->extra_stats.rx_bsy);
2832
2833                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
2834                           gfar_read(&regs->rstat));
2835         }
2836         if (events & IEVENT_BABR) {
2837                 dev->stats.rx_errors++;
2838                 atomic64_inc(&priv->extra_stats.rx_babr);
2839
2840                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
2841         }
2842         if (events & IEVENT_EBERR) {
2843                 atomic64_inc(&priv->extra_stats.eberr);
2844                 netif_dbg(priv, rx_err, dev, "bus error\n");
2845         }
2846         if (events & IEVENT_RXC)
2847                 netif_dbg(priv, rx_status, dev, "control frame\n");
2848
2849         if (events & IEVENT_BABT) {
2850                 atomic64_inc(&priv->extra_stats.tx_babt);
2851                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
2852         }
2853         return IRQ_HANDLED;
2854 }
2855
2856 /* The interrupt handler for devices with one interrupt */
2857 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2858 {
2859         struct gfar_priv_grp *gfargrp = grp_id;
2860
2861         /* Save ievent for future reference */
2862         u32 events = gfar_read(&gfargrp->regs->ievent);
2863
2864         /* Check for reception */
2865         if (events & IEVENT_RX_MASK)
2866                 gfar_receive(irq, grp_id);
2867
2868         /* Check for transmit completion */
2869         if (events & IEVENT_TX_MASK)
2870                 gfar_transmit(irq, grp_id);
2871
2872         /* Check for errors */
2873         if (events & IEVENT_ERR_MASK)
2874                 gfar_error(irq, grp_id);
2875
2876         return IRQ_HANDLED;
2877 }
2878
2879 #ifdef CONFIG_NET_POLL_CONTROLLER
2880 /* Polling 'interrupt' - used by things like netconsole to send skbs
2881  * without having to re-enable interrupts. It's not called while
2882  * the interrupt routine is executing.
2883  */
2884 static void gfar_netpoll(struct net_device *dev)
2885 {
2886         struct gfar_private *priv = netdev_priv(dev);
2887         int i;
2888
2889         /* If the device has multiple interrupts, run tx/rx */
2890         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2891                 for (i = 0; i < priv->num_grps; i++) {
2892                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2893
2894                         disable_irq(gfar_irq(grp, TX)->irq);
2895                         disable_irq(gfar_irq(grp, RX)->irq);
2896                         disable_irq(gfar_irq(grp, ER)->irq);
2897                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2898                         enable_irq(gfar_irq(grp, ER)->irq);
2899                         enable_irq(gfar_irq(grp, RX)->irq);
2900                         enable_irq(gfar_irq(grp, TX)->irq);
2901                 }
2902         } else {
2903                 for (i = 0; i < priv->num_grps; i++) {
2904                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2905
2906                         disable_irq(gfar_irq(grp, TX)->irq);
2907                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2908                         enable_irq(gfar_irq(grp, TX)->irq);
2909                 }
2910         }
2911 }
2912 #endif
2913
2914 static void free_grp_irqs(struct gfar_priv_grp *grp)
2915 {
2916         free_irq(gfar_irq(grp, TX)->irq, grp);
2917         free_irq(gfar_irq(grp, RX)->irq, grp);
2918         free_irq(gfar_irq(grp, ER)->irq, grp);
2919 }
2920
2921 static int register_grp_irqs(struct gfar_priv_grp *grp)
2922 {
2923         struct gfar_private *priv = grp->priv;
2924         struct net_device *dev = priv->ndev;
2925         int err;
2926
2927         /* If the device has multiple interrupts, register for
2928          * them.  Otherwise, only register for the one
2929          */
2930         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2931                 /* Install our interrupt handlers for Error,
2932                  * Transmit, and Receive
2933                  */
2934                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2935                                   gfar_irq(grp, ER)->name, grp);
2936                 if (err < 0) {
2937                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2938                                   gfar_irq(grp, ER)->irq);
2939
2940                         goto err_irq_fail;
2941                 }
2942                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2943
2944                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2945                                   gfar_irq(grp, TX)->name, grp);
2946                 if (err < 0) {
2947                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2948                                   gfar_irq(grp, TX)->irq);
2949                         goto tx_irq_fail;
2950                 }
2951                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2952                                   gfar_irq(grp, RX)->name, grp);
2953                 if (err < 0) {
2954                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2955                                   gfar_irq(grp, RX)->irq);
2956                         goto rx_irq_fail;
2957                 }
2958                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2959
2960         } else {
2961                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2962                                   gfar_irq(grp, TX)->name, grp);
2963                 if (err < 0) {
2964                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2965                                   gfar_irq(grp, TX)->irq);
2966                         goto err_irq_fail;
2967                 }
2968                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2969         }
2970
2971         return 0;
2972
2973 rx_irq_fail:
2974         free_irq(gfar_irq(grp, TX)->irq, grp);
2975 tx_irq_fail:
2976         free_irq(gfar_irq(grp, ER)->irq, grp);
2977 err_irq_fail:
2978         return err;
2979
2980 }
2981
2982 static void gfar_free_irq(struct gfar_private *priv)
2983 {
2984         int i;
2985
2986         /* Free the IRQs */
2987         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2988                 for (i = 0; i < priv->num_grps; i++)
2989                         free_grp_irqs(&priv->gfargrp[i]);
2990         } else {
2991                 for (i = 0; i < priv->num_grps; i++)
2992                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2993                                  &priv->gfargrp[i]);
2994         }
2995 }
2996
2997 static int gfar_request_irq(struct gfar_private *priv)
2998 {
2999         int err, i, j;
3000
3001         for (i = 0; i < priv->num_grps; i++) {
3002                 err = register_grp_irqs(&priv->gfargrp[i]);
3003                 if (err) {
3004                         for (j = 0; j < i; j++)
3005                                 free_grp_irqs(&priv->gfargrp[j]);
3006                         return err;
3007                 }
3008         }
3009
3010         return 0;
3011 }
3012
3013 /* Called when something needs to use the ethernet device
3014  * Returns 0 for success.
3015  */
3016 static int gfar_enet_open(struct net_device *dev)
3017 {
3018         struct gfar_private *priv = netdev_priv(dev);
3019         int err;
3020
3021         err = init_phy(dev);
3022         if (err)
3023                 return err;
3024
3025         err = gfar_request_irq(priv);
3026         if (err)
3027                 return err;
3028
3029         err = startup_gfar(dev);
3030         if (err)
3031                 return err;
3032
3033         return err;
3034 }
3035
3036 /* Stops the kernel queue, and halts the controller */
3037 static int gfar_close(struct net_device *dev)
3038 {
3039         struct gfar_private *priv = netdev_priv(dev);
3040
3041         cancel_work_sync(&priv->reset_task);
3042         stop_gfar(dev);
3043
3044         /* Disconnect from the PHY */
3045         phy_disconnect(dev->phydev);
3046
3047         gfar_free_irq(priv);
3048
3049         return 0;
3050 }
3051
3052 /* Clears each of the exact match registers to zero, so they
3053  * don't interfere with normal reception
3054  */
3055 static void gfar_clear_exact_match(struct net_device *dev)
3056 {
3057         int idx;
3058         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3059
3060         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3061                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3062 }
3063
3064 /* Update the hash table based on the current list of multicast
3065  * addresses we subscribe to.  Also, change the promiscuity of
3066  * the device based on the flags (this function is called
3067  * whenever dev->flags is changed
3068  */
3069 static void gfar_set_multi(struct net_device *dev)
3070 {
3071         struct netdev_hw_addr *ha;
3072         struct gfar_private *priv = netdev_priv(dev);
3073         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3074         u32 tempval;
3075
3076         if (dev->flags & IFF_PROMISC) {
3077                 /* Set RCTRL to PROM */
3078                 tempval = gfar_read(&regs->rctrl);
3079                 tempval |= RCTRL_PROM;
3080                 gfar_write(&regs->rctrl, tempval);
3081         } else {
3082                 /* Set RCTRL to not PROM */
3083                 tempval = gfar_read(&regs->rctrl);
3084                 tempval &= ~(RCTRL_PROM);
3085                 gfar_write(&regs->rctrl, tempval);
3086         }
3087
3088         if (dev->flags & IFF_ALLMULTI) {
3089                 /* Set the hash to rx all multicast frames */
3090                 gfar_write(&regs->igaddr0, 0xffffffff);
3091                 gfar_write(&regs->igaddr1, 0xffffffff);
3092                 gfar_write(&regs->igaddr2, 0xffffffff);
3093                 gfar_write(&regs->igaddr3, 0xffffffff);
3094                 gfar_write(&regs->igaddr4, 0xffffffff);
3095                 gfar_write(&regs->igaddr5, 0xffffffff);
3096                 gfar_write(&regs->igaddr6, 0xffffffff);
3097                 gfar_write(&regs->igaddr7, 0xffffffff);
3098                 gfar_write(&regs->gaddr0, 0xffffffff);
3099                 gfar_write(&regs->gaddr1, 0xffffffff);
3100                 gfar_write(&regs->gaddr2, 0xffffffff);
3101                 gfar_write(&regs->gaddr3, 0xffffffff);
3102                 gfar_write(&regs->gaddr4, 0xffffffff);
3103                 gfar_write(&regs->gaddr5, 0xffffffff);
3104                 gfar_write(&regs->gaddr6, 0xffffffff);
3105                 gfar_write(&regs->gaddr7, 0xffffffff);
3106         } else {
3107                 int em_num;
3108                 int idx;
3109
3110                 /* zero out the hash */
3111                 gfar_write(&regs->igaddr0, 0x0);
3112                 gfar_write(&regs->igaddr1, 0x0);
3113                 gfar_write(&regs->igaddr2, 0x0);
3114                 gfar_write(&regs->igaddr3, 0x0);
3115                 gfar_write(&regs->igaddr4, 0x0);
3116                 gfar_write(&regs->igaddr5, 0x0);
3117                 gfar_write(&regs->igaddr6, 0x0);
3118                 gfar_write(&regs->igaddr7, 0x0);
3119                 gfar_write(&regs->gaddr0, 0x0);
3120                 gfar_write(&regs->gaddr1, 0x0);
3121                 gfar_write(&regs->gaddr2, 0x0);
3122                 gfar_write(&regs->gaddr3, 0x0);
3123                 gfar_write(&regs->gaddr4, 0x0);
3124                 gfar_write(&regs->gaddr5, 0x0);
3125                 gfar_write(&regs->gaddr6, 0x0);
3126                 gfar_write(&regs->gaddr7, 0x0);
3127
3128                 /* If we have extended hash tables, we need to
3129                  * clear the exact match registers to prepare for
3130                  * setting them
3131                  */
3132                 if (priv->extended_hash) {
3133                         em_num = GFAR_EM_NUM + 1;
3134                         gfar_clear_exact_match(dev);
3135                         idx = 1;
3136                 } else {
3137                         idx = 0;
3138                         em_num = 0;
3139                 }
3140
3141                 if (netdev_mc_empty(dev))
3142                         return;
3143
3144                 /* Parse the list, and set the appropriate bits */
3145                 netdev_for_each_mc_addr(ha, dev) {
3146                         if (idx < em_num) {
3147                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3148                                 idx++;
3149                         } else
3150                                 gfar_set_hash_for_addr(dev, ha->addr);
3151                 }
3152         }
3153 }
3154
3155 void gfar_mac_reset(struct gfar_private *priv)
3156 {
3157         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3158         u32 tempval;
3159
3160         /* Reset MAC layer */
3161         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
3162
3163         /* We need to delay at least 3 TX clocks */
3164         udelay(3);
3165
3166         /* the soft reset bit is not self-resetting, so we need to
3167          * clear it before resuming normal operation
3168          */
3169         gfar_write(&regs->maccfg1, 0);
3170
3171         udelay(3);
3172
3173         gfar_rx_offload_en(priv);
3174
3175         /* Initialize the max receive frame/buffer lengths */
3176         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
3177         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
3178
3179         /* Initialize the Minimum Frame Length Register */
3180         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
3181
3182         /* Initialize MACCFG2. */
3183         tempval = MACCFG2_INIT_SETTINGS;
3184
3185         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
3186          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
3187          * and by checking RxBD[LG] and discarding larger than MAXFRM.
3188          */
3189         if (gfar_has_errata(priv, GFAR_ERRATA_74))
3190                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
3191
3192         gfar_write(&regs->maccfg2, tempval);
3193
3194         /* Clear mac addr hash registers */
3195         gfar_write(&regs->igaddr0, 0);
3196         gfar_write(&regs->igaddr1, 0);
3197         gfar_write(&regs->igaddr2, 0);
3198         gfar_write(&regs->igaddr3, 0);
3199         gfar_write(&regs->igaddr4, 0);
3200         gfar_write(&regs->igaddr5, 0);
3201         gfar_write(&regs->igaddr6, 0);
3202         gfar_write(&regs->igaddr7, 0);
3203
3204         gfar_write(&regs->gaddr0, 0);
3205         gfar_write(&regs->gaddr1, 0);
3206         gfar_write(&regs->gaddr2, 0);
3207         gfar_write(&regs->gaddr3, 0);
3208         gfar_write(&regs->gaddr4, 0);
3209         gfar_write(&regs->gaddr5, 0);
3210         gfar_write(&regs->gaddr6, 0);
3211         gfar_write(&regs->gaddr7, 0);
3212
3213         if (priv->extended_hash)
3214                 gfar_clear_exact_match(priv->ndev);
3215
3216         gfar_mac_rx_config(priv);
3217
3218         gfar_mac_tx_config(priv);
3219
3220         gfar_set_mac_address(priv->ndev);
3221
3222         gfar_set_multi(priv->ndev);
3223
3224         /* clear ievent and imask before configuring coalescing */
3225         gfar_ints_disable(priv);
3226
3227         /* Configure the coalescing support */
3228         gfar_configure_coalescing_all(priv);
3229 }
3230
3231 static void gfar_hw_init(struct gfar_private *priv)
3232 {
3233         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3234         u32 attrs;
3235
3236         /* Stop the DMA engine now, in case it was running before
3237          * (The firmware could have used it, and left it running).
3238          */
3239         gfar_halt(priv);
3240
3241         gfar_mac_reset(priv);
3242
3243         /* Zero out the rmon mib registers if it has them */
3244         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3245                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
3246
3247                 /* Mask off the CAM interrupts */
3248                 gfar_write(&regs->rmon.cam1, 0xffffffff);
3249                 gfar_write(&regs->rmon.cam2, 0xffffffff);
3250         }
3251
3252         /* Initialize ECNTRL */
3253         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
3254
3255         /* Set the extraction length and index */
3256         attrs = ATTRELI_EL(priv->rx_stash_size) |
3257                 ATTRELI_EI(priv->rx_stash_index);
3258
3259         gfar_write(&regs->attreli, attrs);
3260
3261         /* Start with defaults, and add stashing
3262          * depending on driver parameters
3263          */
3264         attrs = ATTR_INIT_SETTINGS;
3265
3266         if (priv->bd_stash_en)
3267                 attrs |= ATTR_BDSTASH;
3268
3269         if (priv->rx_stash_size != 0)
3270                 attrs |= ATTR_BUFSTASH;
3271
3272         gfar_write(&regs->attr, attrs);
3273
3274         /* FIFO configs */
3275         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
3276         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
3277         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
3278
3279         /* Program the interrupt steering regs, only for MG devices */
3280         if (priv->num_grps > 1)
3281                 gfar_write_isrg(priv);
3282 }
3283
3284 static const struct net_device_ops gfar_netdev_ops = {
3285         .ndo_open = gfar_enet_open,
3286         .ndo_start_xmit = gfar_start_xmit,
3287         .ndo_stop = gfar_close,
3288         .ndo_change_mtu = gfar_change_mtu,
3289         .ndo_set_features = gfar_set_features,
3290         .ndo_set_rx_mode = gfar_set_multi,
3291         .ndo_tx_timeout = gfar_timeout,
3292         .ndo_do_ioctl = gfar_ioctl,
3293         .ndo_get_stats = gfar_get_stats,
3294         .ndo_change_carrier = fixed_phy_change_carrier,
3295         .ndo_set_mac_address = gfar_set_mac_addr,
3296         .ndo_validate_addr = eth_validate_addr,
3297 #ifdef CONFIG_NET_POLL_CONTROLLER
3298         .ndo_poll_controller = gfar_netpoll,
3299 #endif
3300 };
3301
3302 /* Set up the ethernet device structure, private data,
3303  * and anything else we need before we start
3304  */
3305 static int gfar_probe(struct platform_device *ofdev)
3306 {
3307         struct device_node *np = ofdev->dev.of_node;
3308         struct net_device *dev = NULL;
3309         struct gfar_private *priv = NULL;
3310         int err = 0, i;
3311
3312         err = gfar_of_init(ofdev, &dev);
3313
3314         if (err)
3315                 return err;
3316
3317         priv = netdev_priv(dev);
3318         priv->ndev = dev;
3319         priv->ofdev = ofdev;
3320         priv->dev = &ofdev->dev;
3321         SET_NETDEV_DEV(dev, &ofdev->dev);
3322
3323         INIT_WORK(&priv->reset_task, gfar_reset_task);
3324
3325         platform_set_drvdata(ofdev, priv);
3326
3327         gfar_detect_errata(priv);
3328
3329         /* Set the dev->base_addr to the gfar reg region */
3330         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
3331
3332         /* Fill in the dev structure */
3333         dev->watchdog_timeo = TX_TIMEOUT;
3334         /* MTU range: 50 - 9586 */
3335         dev->mtu = 1500;
3336         dev->min_mtu = 50;
3337         dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
3338         dev->netdev_ops = &gfar_netdev_ops;
3339         dev->ethtool_ops = &gfar_ethtool_ops;
3340
3341         /* Register for napi ...We are registering NAPI for each grp */
3342         for (i = 0; i < priv->num_grps; i++) {
3343                 if (priv->poll_mode == GFAR_SQ_POLLING) {
3344                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3345                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
3346                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3347                                        gfar_poll_tx_sq, 2);
3348                 } else {
3349                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3350                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
3351                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3352                                        gfar_poll_tx, 2);
3353                 }
3354         }
3355
3356         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
3357                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3358                                    NETIF_F_RXCSUM;
3359                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
3360                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
3361         }
3362
3363         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
3364                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3365                                     NETIF_F_HW_VLAN_CTAG_RX;
3366                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3367         }
3368
3369         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3370
3371         gfar_init_addr_hash_table(priv);
3372
3373         /* Insert receive time stamps into padding alignment bytes, and
3374          * plus 2 bytes padding to ensure the cpu alignment.
3375          */
3376         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3377                 priv->padding = 8 + DEFAULT_PADDING;
3378
3379         if (dev->features & NETIF_F_IP_CSUM ||
3380             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3381                 dev->needed_headroom = GMAC_FCB_LEN;
3382
3383         /* Initializing some of the rx/tx queue level parameters */
3384         for (i = 0; i < priv->num_tx_queues; i++) {
3385                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
3386                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
3387                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
3388                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
3389         }
3390
3391         for (i = 0; i < priv->num_rx_queues; i++) {
3392                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
3393                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
3394                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
3395         }
3396
3397         /* Always enable rx filer if available */
3398         priv->rx_filer_enable =
3399             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
3400         /* Enable most messages by default */
3401         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3402         /* use pritority h/w tx queue scheduling for single queue devices */
3403         if (priv->num_tx_queues == 1)
3404                 priv->prio_sched_en = 1;
3405
3406         set_bit(GFAR_DOWN, &priv->state);
3407
3408         gfar_hw_init(priv);
3409
3410         /* Carrier starts down, phylib will bring it up */
3411         netif_carrier_off(dev);
3412
3413         err = register_netdev(dev);
3414
3415         if (err) {
3416                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
3417                 goto register_fail;
3418         }
3419
3420         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
3421                 priv->wol_supported |= GFAR_WOL_MAGIC;
3422
3423         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
3424             priv->rx_filer_enable)
3425                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
3426
3427         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
3428
3429         /* fill out IRQ number and name fields */
3430         for (i = 0; i < priv->num_grps; i++) {
3431                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3432                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3433                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
3434                                 dev->name, "_g", '0' + i, "_tx");
3435                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
3436                                 dev->name, "_g", '0' + i, "_rx");
3437                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
3438                                 dev->name, "_g", '0' + i, "_er");
3439                 } else
3440                         strcpy(gfar_irq(grp, TX)->name, dev->name);
3441         }
3442
3443         /* Initialize the filer table */
3444         gfar_init_filer_table(priv);
3445
3446         /* Print out the device info */
3447         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
3448
3449         /* Even more device info helps when determining which kernel
3450          * provided which set of benchmarks.
3451          */
3452         netdev_info(dev, "Running with NAPI enabled\n");
3453         for (i = 0; i < priv->num_rx_queues; i++)
3454                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
3455                             i, priv->rx_queue[i]->rx_ring_size);
3456         for (i = 0; i < priv->num_tx_queues; i++)
3457                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
3458                             i, priv->tx_queue[i]->tx_ring_size);
3459
3460         return 0;
3461
3462 register_fail:
3463         if (of_phy_is_fixed_link(np))
3464                 of_phy_deregister_fixed_link(np);
3465         unmap_group_regs(priv);
3466         gfar_free_rx_queues(priv);
3467         gfar_free_tx_queues(priv);
3468         of_node_put(priv->phy_node);
3469         of_node_put(priv->tbi_node);
3470         free_gfar_dev(priv);
3471         return err;
3472 }
3473
3474 static int gfar_remove(struct platform_device *ofdev)
3475 {
3476         struct gfar_private *priv = platform_get_drvdata(ofdev);
3477         struct device_node *np = ofdev->dev.of_node;
3478
3479         of_node_put(priv->phy_node);
3480         of_node_put(priv->tbi_node);
3481
3482         unregister_netdev(priv->ndev);
3483
3484         if (of_phy_is_fixed_link(np))
3485                 of_phy_deregister_fixed_link(np);
3486
3487         unmap_group_regs(priv);
3488         gfar_free_rx_queues(priv);
3489         gfar_free_tx_queues(priv);
3490         free_gfar_dev(priv);
3491
3492         return 0;
3493 }
3494
3495 #ifdef CONFIG_PM
3496
3497 static void __gfar_filer_disable(struct gfar_private *priv)
3498 {
3499         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3500         u32 temp;
3501
3502         temp = gfar_read(&regs->rctrl);
3503         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
3504         gfar_write(&regs->rctrl, temp);
3505 }
3506
3507 static void __gfar_filer_enable(struct gfar_private *priv)
3508 {
3509         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3510         u32 temp;
3511
3512         temp = gfar_read(&regs->rctrl);
3513         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
3514         gfar_write(&regs->rctrl, temp);
3515 }
3516
3517 /* Filer rules implementing wol capabilities */
3518 static void gfar_filer_config_wol(struct gfar_private *priv)
3519 {
3520         unsigned int i;
3521         u32 rqfcr;
3522
3523         __gfar_filer_disable(priv);
3524
3525         /* clear the filer table, reject any packet by default */
3526         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
3527         for (i = 0; i <= MAX_FILER_IDX; i++)
3528                 gfar_write_filer(priv, i, rqfcr, 0);
3529
3530         i = 0;
3531         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
3532                 /* unicast packet, accept it */
3533                 struct net_device *ndev = priv->ndev;
3534                 /* get the default rx queue index */
3535                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
3536                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
3537                                     (ndev->dev_addr[1] << 8) |
3538                                      ndev->dev_addr[2];
3539
3540                 rqfcr = (qindex << 10) | RQFCR_AND |
3541                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
3542
3543                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3544
3545                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
3546                                 (ndev->dev_addr[4] << 8) |
3547                                  ndev->dev_addr[5];
3548                 rqfcr = (qindex << 10) | RQFCR_GPI |
3549                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
3550                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3551         }
3552
3553         __gfar_filer_enable(priv);
3554 }
3555
3556 static void gfar_filer_restore_table(struct gfar_private *priv)
3557 {
3558         u32 rqfcr, rqfpr;
3559         unsigned int i;
3560
3561         __gfar_filer_disable(priv);
3562
3563         for (i = 0; i <= MAX_FILER_IDX; i++) {
3564                 rqfcr = priv->ftp_rqfcr[i];
3565                 rqfpr = priv->ftp_rqfpr[i];
3566                 gfar_write_filer(priv, i, rqfcr, rqfpr);
3567         }
3568
3569         __gfar_filer_enable(priv);
3570 }
3571
3572 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
3573 static void gfar_start_wol_filer(struct gfar_private *priv)
3574 {
3575         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3576         u32 tempval;
3577         int i = 0;
3578
3579         /* Enable Rx hw queues */
3580         gfar_write(&regs->rqueue, priv->rqueue);
3581
3582         /* Initialize DMACTRL to have WWR and WOP */
3583         tempval = gfar_read(&regs->dmactrl);
3584         tempval |= DMACTRL_INIT_SETTINGS;
3585         gfar_write(&regs->dmactrl, tempval);
3586
3587         /* Make sure we aren't stopped */
3588         tempval = gfar_read(&regs->dmactrl);
3589         tempval &= ~DMACTRL_GRS;
3590         gfar_write(&regs->dmactrl, tempval);
3591
3592         for (i = 0; i < priv->num_grps; i++) {
3593                 regs = priv->gfargrp[i].regs;
3594                 /* Clear RHLT, so that the DMA starts polling now */
3595                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
3596                 /* enable the Filer General Purpose Interrupt */
3597                 gfar_write(&regs->imask, IMASK_FGPI);
3598         }
3599
3600         /* Enable Rx DMA */
3601         tempval = gfar_read(&regs->maccfg1);
3602         tempval |= MACCFG1_RX_EN;
3603         gfar_write(&regs->maccfg1, tempval);
3604 }
3605
3606 static int gfar_suspend(struct device *dev)
3607 {
3608         struct gfar_private *priv = dev_get_drvdata(dev);
3609         struct net_device *ndev = priv->ndev;
3610         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3611         u32 tempval;
3612         u16 wol = priv->wol_opts;
3613
3614         if (!netif_running(ndev))
3615                 return 0;
3616
3617         disable_napi(priv);
3618         netif_tx_lock(ndev);
3619         netif_device_detach(ndev);
3620         netif_tx_unlock(ndev);
3621
3622         gfar_halt(priv);
3623
3624         if (wol & GFAR_WOL_MAGIC) {
3625                 /* Enable interrupt on Magic Packet */
3626                 gfar_write(&regs->imask, IMASK_MAG);
3627
3628                 /* Enable Magic Packet mode */
3629                 tempval = gfar_read(&regs->maccfg2);
3630                 tempval |= MACCFG2_MPEN;
3631                 gfar_write(&regs->maccfg2, tempval);
3632
3633                 /* re-enable the Rx block */
3634                 tempval = gfar_read(&regs->maccfg1);
3635                 tempval |= MACCFG1_RX_EN;
3636                 gfar_write(&regs->maccfg1, tempval);
3637
3638         } else if (wol & GFAR_WOL_FILER_UCAST) {
3639                 gfar_filer_config_wol(priv);
3640                 gfar_start_wol_filer(priv);
3641
3642         } else {
3643                 phy_stop(ndev->phydev);
3644         }
3645
3646         return 0;
3647 }
3648
3649 static int gfar_resume(struct device *dev)
3650 {
3651         struct gfar_private *priv = dev_get_drvdata(dev);
3652         struct net_device *ndev = priv->ndev;
3653         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3654         u32 tempval;
3655         u16 wol = priv->wol_opts;
3656
3657         if (!netif_running(ndev))
3658                 return 0;
3659
3660         if (wol & GFAR_WOL_MAGIC) {
3661                 /* Disable Magic Packet mode */
3662                 tempval = gfar_read(&regs->maccfg2);
3663                 tempval &= ~MACCFG2_MPEN;
3664                 gfar_write(&regs->maccfg2, tempval);
3665
3666         } else if (wol & GFAR_WOL_FILER_UCAST) {
3667                 /* need to stop rx only, tx is already down */
3668                 gfar_halt(priv);
3669                 gfar_filer_restore_table(priv);
3670
3671         } else {
3672                 phy_start(ndev->phydev);
3673         }
3674
3675         gfar_start(priv);
3676
3677         netif_device_attach(ndev);
3678         enable_napi(priv);
3679
3680         return 0;
3681 }
3682
3683 static int gfar_restore(struct device *dev)
3684 {
3685         struct gfar_private *priv = dev_get_drvdata(dev);
3686         struct net_device *ndev = priv->ndev;
3687
3688         if (!netif_running(ndev)) {
3689                 netif_device_attach(ndev);
3690
3691                 return 0;
3692         }
3693
3694         gfar_init_bds(ndev);
3695
3696         gfar_mac_reset(priv);
3697
3698         gfar_init_tx_rx_base(priv);
3699
3700         gfar_start(priv);
3701
3702         priv->oldlink = 0;
3703         priv->oldspeed = 0;
3704         priv->oldduplex = -1;
3705
3706         if (ndev->phydev)
3707                 phy_start(ndev->phydev);
3708
3709         netif_device_attach(ndev);
3710         enable_napi(priv);
3711
3712         return 0;
3713 }
3714
3715 static const struct dev_pm_ops gfar_pm_ops = {
3716         .suspend = gfar_suspend,
3717         .resume = gfar_resume,
3718         .freeze = gfar_suspend,
3719         .thaw = gfar_resume,
3720         .restore = gfar_restore,
3721 };
3722
3723 #define GFAR_PM_OPS (&gfar_pm_ops)
3724
3725 #else
3726
3727 #define GFAR_PM_OPS NULL
3728
3729 #endif
3730
3731 static const struct of_device_id gfar_match[] =
3732 {
3733         {
3734                 .type = "network",
3735                 .compatible = "gianfar",
3736         },
3737         {
3738                 .compatible = "fsl,etsec2",
3739         },
3740         {},
3741 };
3742 MODULE_DEVICE_TABLE(of, gfar_match);
3743
3744 /* Structure for a device driver */
3745 static struct platform_driver gfar_driver = {
3746         .driver = {
3747                 .name = "fsl-gianfar",
3748                 .pm = GFAR_PM_OPS,
3749                 .of_match_table = gfar_match,
3750         },
3751         .probe = gfar_probe,
3752         .remove = gfar_remove,
3753 };
3754
3755 module_platform_driver(gfar_driver);