2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/pinctrl/consumer.h>
57 #include <linux/regulator/consumer.h>
59 #include <asm/cacheflush.h>
63 #if defined(CONFIG_ARM)
64 #define FEC_ALIGNMENT 0xf
66 #define FEC_ALIGNMENT 0x3
69 #define DRIVER_NAME "fec"
70 #define FEC_NAPI_WEIGHT 64
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90 /* Controller has hardware checksum support */
91 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 static struct platform_device_id fec_devtype[] = {
95 /* keep it for coldfire */
100 .driver_data = FEC_QUIRK_USE_GASKET,
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
109 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM,
112 .name = "mvf600-fec",
113 .driver_data = FEC_QUIRK_ENET_MAC,
118 MODULE_DEVICE_TABLE(platform, fec_devtype);
121 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
122 IMX27_FEC, /* runs on i.mx27/35/51 */
128 static const struct of_device_id fec_dt_ids[] = {
129 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
130 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
131 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
132 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
133 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
136 MODULE_DEVICE_TABLE(of, fec_dt_ids);
138 static unsigned char macaddr[ETH_ALEN];
139 module_param_array(macaddr, byte, NULL, 0);
140 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
142 #if defined(CONFIG_M5272)
144 * Some hardware gets it MAC address out of local flash memory.
145 * if this is non-zero then assume it is the address to get MAC from.
147 #if defined(CONFIG_NETtel)
148 #define FEC_FLASHMAC 0xf0006006
149 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
150 #define FEC_FLASHMAC 0xf0006000
151 #elif defined(CONFIG_CANCam)
152 #define FEC_FLASHMAC 0xf0020000
153 #elif defined (CONFIG_M5272C3)
154 #define FEC_FLASHMAC (0xffe04000 + 4)
155 #elif defined(CONFIG_MOD5272)
156 #define FEC_FLASHMAC 0xffc0406b
158 #define FEC_FLASHMAC 0
160 #endif /* CONFIG_M5272 */
162 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
163 #error "FEC: descriptor ring size constants too large"
166 /* Interrupt events/masks. */
167 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
168 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
169 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
170 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
171 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
172 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
173 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
174 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
175 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
176 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
178 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
179 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
181 /* The FEC stores dest/src/type, data, and checksum for receive packets.
183 #define PKT_MAXBUF_SIZE 1518
184 #define PKT_MINBUF_SIZE 64
185 #define PKT_MAXBLR_SIZE 1520
187 /* FEC receive acceleration */
188 #define FEC_RACC_IPDIS (1 << 1)
189 #define FEC_RACC_PRODIS (1 << 2)
190 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
193 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
194 * size bits. Other FEC hardware does not, so we need to take that into
195 * account when setting it.
197 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
198 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
199 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
201 #define OPT_FRAME_SIZE 0
204 /* FEC MII MMFR bits definition */
205 #define FEC_MMFR_ST (1 << 30)
206 #define FEC_MMFR_OP_READ (2 << 28)
207 #define FEC_MMFR_OP_WRITE (1 << 28)
208 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
209 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
210 #define FEC_MMFR_TA (2 << 16)
211 #define FEC_MMFR_DATA(v) (v & 0xffff)
213 #define FEC_MII_TIMEOUT 30000 /* us */
215 /* Transmitter timeout */
216 #define TX_TIMEOUT (2 * HZ)
218 #define FEC_PAUSE_FLAG_AUTONEG 0x1
219 #define FEC_PAUSE_FLAG_ENABLE 0x2
223 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
225 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
227 return (struct bufdesc *)(ex + 1);
232 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
234 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
236 return (struct bufdesc *)(ex - 1);
241 static void *swap_buffer(void *bufaddr, int len)
244 unsigned int *buf = bufaddr;
246 for (i = 0; i < (len + 3) / 4; i++, buf++)
247 *buf = cpu_to_be32(*buf);
253 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
255 /* Only run for packets requiring a checksum. */
256 if (skb->ip_summed != CHECKSUM_PARTIAL)
259 if (unlikely(skb_cow_head(skb, 0)))
262 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
268 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
270 struct fec_enet_private *fep = netdev_priv(ndev);
271 const struct platform_device_id *id_entry =
272 platform_get_device_id(fep->pdev);
275 unsigned short status;
279 /* Link is down or auto-negotiation is in progress. */
280 return NETDEV_TX_BUSY;
283 /* Fill in a Tx ring entry */
286 status = bdp->cbd_sc;
288 if (status & BD_ENET_TX_READY) {
289 /* Ooops. All transmit buffers are full. Bail out.
290 * This should not happen, since ndev->tbusy should be set.
292 netdev_err(ndev, "tx queue full!\n");
293 return NETDEV_TX_BUSY;
296 /* Protocol checksum off-load for TCP and UDP. */
297 if (fec_enet_clear_csum(skb, ndev)) {
302 /* Clear all of the status flags */
303 status &= ~BD_ENET_TX_STATS;
305 /* Set buffer length and buffer pointer */
307 bdp->cbd_datlen = skb->len;
310 * On some FEC implementations data must be aligned on
311 * 4-byte boundaries. Use bounce buffers to copy data
312 * and get it aligned. Ugh.
315 index = (struct bufdesc_ex *)bdp -
316 (struct bufdesc_ex *)fep->tx_bd_base;
318 index = bdp - fep->tx_bd_base;
320 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
321 memcpy(fep->tx_bounce[index], skb->data, skb->len);
322 bufaddr = fep->tx_bounce[index];
326 * Some design made an incorrect assumption on endian mode of
327 * the system that it's running on. As the result, driver has to
328 * swap every frame going to and coming from the controller.
330 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
331 swap_buffer(bufaddr, skb->len);
333 /* Save skb pointer */
334 fep->tx_skbuff[index] = skb;
336 /* Push the data cache so the CPM does not get stale memory
339 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
340 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
342 /* Send it on its way. Tell FEC it's ready, interrupt when done,
343 * it's the last BD of the frame, and to put the CRC on the end.
345 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
346 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
347 bdp->cbd_sc = status;
349 if (fep->bufdesc_ex) {
351 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
353 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
355 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
356 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
358 ebdp->cbd_esc = BD_ENET_TX_INT;
360 /* Enable protocol checksum flags
361 * We do not bother with the IP Checksum bits as they
362 * are done by the kernel
364 if (skb->ip_summed == CHECKSUM_PARTIAL)
365 ebdp->cbd_esc |= BD_ENET_TX_PINS;
368 /* If this was the last BD in the ring, start at the beginning again. */
369 if (status & BD_ENET_TX_WRAP)
370 bdp = fep->tx_bd_base;
372 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
376 if (fep->cur_tx == fep->dirty_tx)
377 netif_stop_queue(ndev);
379 /* Trigger transmission start */
380 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
382 skb_tx_timestamp(skb);
387 /* Init RX & TX buffer descriptors
389 static void fec_enet_bd_init(struct net_device *dev)
391 struct fec_enet_private *fep = netdev_priv(dev);
395 /* Initialize the receive buffer descriptors. */
396 bdp = fep->rx_bd_base;
397 for (i = 0; i < RX_RING_SIZE; i++) {
399 /* Initialize the BD for every fragment in the page. */
400 if (bdp->cbd_bufaddr)
401 bdp->cbd_sc = BD_ENET_RX_EMPTY;
404 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
407 /* Set the last buffer to wrap */
408 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
409 bdp->cbd_sc |= BD_SC_WRAP;
411 fep->cur_rx = fep->rx_bd_base;
413 /* ...and the same for transmit */
414 bdp = fep->tx_bd_base;
416 for (i = 0; i < TX_RING_SIZE; i++) {
418 /* Initialize the BD for every fragment in the page. */
420 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
421 dev_kfree_skb_any(fep->tx_skbuff[i]);
422 fep->tx_skbuff[i] = NULL;
424 bdp->cbd_bufaddr = 0;
425 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
428 /* Set the last buffer to wrap */
429 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
430 bdp->cbd_sc |= BD_SC_WRAP;
434 /* This function is called to start or restart the FEC during a link
435 * change. This only happens when switching between half and full
439 fec_restart(struct net_device *ndev, int duplex)
441 struct fec_enet_private *fep = netdev_priv(ndev);
442 const struct platform_device_id *id_entry =
443 platform_get_device_id(fep->pdev);
447 u32 rcntl = OPT_FRAME_SIZE | 0x04;
448 u32 ecntl = 0x2; /* ETHEREN */
450 if (netif_running(ndev)) {
451 netif_device_detach(ndev);
452 napi_disable(&fep->napi);
453 netif_stop_queue(ndev);
454 netif_tx_lock_bh(ndev);
457 /* Whack a reset. We should wait for this. */
458 writel(1, fep->hwp + FEC_ECNTRL);
462 * enet-mac reset will reset mac address registers too,
463 * so need to reconfigure it.
465 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
466 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
467 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
468 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
471 /* Clear any outstanding interrupt. */
472 writel(0xffc00000, fep->hwp + FEC_IEVENT);
474 /* Reset all multicast. */
475 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
476 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
478 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
479 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
482 /* Set maximum receive buffer size. */
483 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
485 fec_enet_bd_init(ndev);
487 /* Set receive and transmit descriptor base. */
488 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
490 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
491 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
493 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
494 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
497 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
498 if (fep->tx_skbuff[i]) {
499 dev_kfree_skb_any(fep->tx_skbuff[i]);
500 fep->tx_skbuff[i] = NULL;
504 /* Enable MII mode */
507 writel(0x04, fep->hwp + FEC_X_CNTRL);
511 writel(0x0, fep->hwp + FEC_X_CNTRL);
514 fep->full_duplex = duplex;
517 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
519 /* set RX checksum */
520 val = readl(fep->hwp + FEC_RACC);
521 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
522 val |= FEC_RACC_OPTIONS;
524 val &= ~FEC_RACC_OPTIONS;
525 writel(val, fep->hwp + FEC_RACC);
528 * The phy interface and speed need to get configured
529 * differently on enet-mac.
531 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
532 /* Enable flow control and length check */
533 rcntl |= 0x40000000 | 0x00000020;
535 /* RGMII, RMII or MII */
536 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
538 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
543 /* 1G, 100M or 10M */
545 if (fep->phy_dev->speed == SPEED_1000)
547 else if (fep->phy_dev->speed == SPEED_100)
553 #ifdef FEC_MIIGSK_ENR
554 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
556 /* disable the gasket and wait */
557 writel(0, fep->hwp + FEC_MIIGSK_ENR);
558 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
562 * configure the gasket:
563 * RMII, 50 MHz, no loopback, no echo
564 * MII, 25 MHz, no loopback, no echo
566 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
567 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
568 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
569 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
570 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
572 /* re-enable the gasket */
573 writel(2, fep->hwp + FEC_MIIGSK_ENR);
578 /* enable pause frame*/
579 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
580 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
581 fep->phy_dev && fep->phy_dev->pause)) {
582 rcntl |= FEC_ENET_FCE;
584 /* set FIFO threshold parameter to reduce overrun */
585 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
586 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
587 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
588 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
591 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
593 rcntl &= ~FEC_ENET_FCE;
596 writel(rcntl, fep->hwp + FEC_R_CNTRL);
598 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
599 /* enable ENET endian swap */
601 /* enable ENET store and forward mode */
602 writel(1 << 8, fep->hwp + FEC_X_WMRK);
608 /* And last, enable the transmit and receive processing */
609 writel(ecntl, fep->hwp + FEC_ECNTRL);
610 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
613 fec_ptp_start_cyclecounter(ndev);
615 /* Enable interrupts we wish to service */
616 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
618 if (netif_running(ndev)) {
619 netif_tx_unlock_bh(ndev);
620 netif_wake_queue(ndev);
621 napi_enable(&fep->napi);
622 netif_device_attach(ndev);
627 fec_stop(struct net_device *ndev)
629 struct fec_enet_private *fep = netdev_priv(ndev);
630 const struct platform_device_id *id_entry =
631 platform_get_device_id(fep->pdev);
632 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
634 /* We cannot expect a graceful transmit stop without link !!! */
636 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
638 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
639 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
642 /* Whack a reset. We should wait for this. */
643 writel(1, fep->hwp + FEC_ECNTRL);
645 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
646 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
648 /* We have to keep ENET enabled to have MII interrupt stay working */
649 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
650 writel(2, fep->hwp + FEC_ECNTRL);
651 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
657 fec_timeout(struct net_device *ndev)
659 struct fec_enet_private *fep = netdev_priv(ndev);
661 ndev->stats.tx_errors++;
663 fep->delay_work.timeout = true;
664 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
667 static void fec_enet_work(struct work_struct *work)
669 struct fec_enet_private *fep =
671 struct fec_enet_private,
672 delay_work.delay_work.work);
674 if (fep->delay_work.timeout) {
675 fep->delay_work.timeout = false;
676 fec_restart(fep->netdev, fep->full_duplex);
677 netif_wake_queue(fep->netdev);
682 fec_enet_tx(struct net_device *ndev)
684 struct fec_enet_private *fep;
686 unsigned short status;
690 fep = netdev_priv(ndev);
693 /* get next bdp of dirty_tx */
694 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
695 bdp = fep->tx_bd_base;
697 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
699 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
701 /* current queue is empty */
702 if (bdp == fep->cur_tx)
706 index = (struct bufdesc_ex *)bdp -
707 (struct bufdesc_ex *)fep->tx_bd_base;
709 index = bdp - fep->tx_bd_base;
711 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
712 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
713 bdp->cbd_bufaddr = 0;
715 skb = fep->tx_skbuff[index];
717 /* Check for errors. */
718 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
719 BD_ENET_TX_RL | BD_ENET_TX_UN |
721 ndev->stats.tx_errors++;
722 if (status & BD_ENET_TX_HB) /* No heartbeat */
723 ndev->stats.tx_heartbeat_errors++;
724 if (status & BD_ENET_TX_LC) /* Late collision */
725 ndev->stats.tx_window_errors++;
726 if (status & BD_ENET_TX_RL) /* Retrans limit */
727 ndev->stats.tx_aborted_errors++;
728 if (status & BD_ENET_TX_UN) /* Underrun */
729 ndev->stats.tx_fifo_errors++;
730 if (status & BD_ENET_TX_CSL) /* Carrier lost */
731 ndev->stats.tx_carrier_errors++;
733 ndev->stats.tx_packets++;
736 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
738 struct skb_shared_hwtstamps shhwtstamps;
740 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
742 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
743 spin_lock_irqsave(&fep->tmreg_lock, flags);
744 shhwtstamps.hwtstamp = ns_to_ktime(
745 timecounter_cyc2time(&fep->tc, ebdp->ts));
746 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
747 skb_tstamp_tx(skb, &shhwtstamps);
750 if (status & BD_ENET_TX_READY)
751 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
753 /* Deferred means some collisions occurred during transmit,
754 * but we eventually sent the packet OK.
756 if (status & BD_ENET_TX_DEF)
757 ndev->stats.collisions++;
759 /* Free the sk buffer associated with this last transmit */
760 dev_kfree_skb_any(skb);
761 fep->tx_skbuff[index] = NULL;
765 /* Update pointer to next buffer descriptor to be transmitted */
766 if (status & BD_ENET_TX_WRAP)
767 bdp = fep->tx_bd_base;
769 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
771 /* Since we have freed up a buffer, the ring is no longer full
773 if (fep->dirty_tx != fep->cur_tx) {
774 if (netif_queue_stopped(ndev))
775 netif_wake_queue(ndev);
782 /* During a receive, the cur_rx points to the current incoming buffer.
783 * When we update through the ring, if the next incoming buffer has
784 * not been given to the system, we just set the empty indicator,
785 * effectively tossing the packet.
788 fec_enet_rx(struct net_device *ndev, int budget)
790 struct fec_enet_private *fep = netdev_priv(ndev);
791 const struct platform_device_id *id_entry =
792 platform_get_device_id(fep->pdev);
794 unsigned short status;
798 int pkt_received = 0;
804 /* First, grab all of the stats for the incoming packet.
805 * These get messed up if we get called due to a busy condition.
809 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
811 if (pkt_received >= budget)
815 /* Since we have allocated space to hold a complete frame,
816 * the last indicator should be set.
818 if ((status & BD_ENET_RX_LAST) == 0)
819 netdev_err(ndev, "rcv is not +last\n");
822 goto rx_processing_done;
824 /* Check for errors. */
825 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
826 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
827 ndev->stats.rx_errors++;
828 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
829 /* Frame too long or too short. */
830 ndev->stats.rx_length_errors++;
832 if (status & BD_ENET_RX_NO) /* Frame alignment */
833 ndev->stats.rx_frame_errors++;
834 if (status & BD_ENET_RX_CR) /* CRC Error */
835 ndev->stats.rx_crc_errors++;
836 if (status & BD_ENET_RX_OV) /* FIFO overrun */
837 ndev->stats.rx_fifo_errors++;
840 /* Report late collisions as a frame error.
841 * On this error, the BD is closed, but we don't know what we
842 * have in the buffer. So, just drop this frame on the floor.
844 if (status & BD_ENET_RX_CL) {
845 ndev->stats.rx_errors++;
846 ndev->stats.rx_frame_errors++;
847 goto rx_processing_done;
850 /* Process the incoming frame. */
851 ndev->stats.rx_packets++;
852 pkt_len = bdp->cbd_datlen;
853 ndev->stats.rx_bytes += pkt_len;
854 data = (__u8*)__va(bdp->cbd_bufaddr);
856 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
857 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
859 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
860 swap_buffer(data, pkt_len);
862 /* This does 16 byte alignment, exactly what we need.
863 * The packet length includes FCS, but we don't want to
864 * include that when passing upstream as it messes up
865 * bridging applications.
867 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
869 if (unlikely(!skb)) {
870 ndev->stats.rx_dropped++;
872 skb_reserve(skb, NET_IP_ALIGN);
873 skb_put(skb, pkt_len - 4); /* Make room */
874 skb_copy_to_linear_data(skb, data, pkt_len - 4);
875 skb->protocol = eth_type_trans(skb, ndev);
877 /* Get receive timestamp from the skb */
878 if (fep->hwts_rx_en && fep->bufdesc_ex) {
879 struct skb_shared_hwtstamps *shhwtstamps =
882 struct bufdesc_ex *ebdp =
883 (struct bufdesc_ex *)bdp;
885 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
887 spin_lock_irqsave(&fep->tmreg_lock, flags);
888 shhwtstamps->hwtstamp = ns_to_ktime(
889 timecounter_cyc2time(&fep->tc, ebdp->ts));
890 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
893 if (fep->bufdesc_ex &&
894 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
895 struct bufdesc_ex *ebdp =
896 (struct bufdesc_ex *)bdp;
897 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
899 skb->ip_summed = CHECKSUM_UNNECESSARY;
901 skb_checksum_none_assert(skb);
905 if (!skb_defer_rx_timestamp(skb))
906 napi_gro_receive(&fep->napi, skb);
909 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
910 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
912 /* Clear the status flags for this buffer */
913 status &= ~BD_ENET_RX_STATS;
915 /* Mark the buffer empty */
916 status |= BD_ENET_RX_EMPTY;
917 bdp->cbd_sc = status;
919 if (fep->bufdesc_ex) {
920 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
922 ebdp->cbd_esc = BD_ENET_RX_INT;
927 /* Update BD pointer to next entry */
928 if (status & BD_ENET_RX_WRAP)
929 bdp = fep->rx_bd_base;
931 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
932 /* Doing this here will keep the FEC running while we process
933 * incoming frames. On a heavily loaded network, we should be
934 * able to keep up at the expense of system resources.
936 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
944 fec_enet_interrupt(int irq, void *dev_id)
946 struct net_device *ndev = dev_id;
947 struct fec_enet_private *fep = netdev_priv(ndev);
949 irqreturn_t ret = IRQ_NONE;
952 int_events = readl(fep->hwp + FEC_IEVENT);
953 writel(int_events, fep->hwp + FEC_IEVENT);
955 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
958 /* Disable the RX interrupt */
959 if (napi_schedule_prep(&fep->napi)) {
960 writel(FEC_RX_DISABLED_IMASK,
961 fep->hwp + FEC_IMASK);
962 __napi_schedule(&fep->napi);
966 if (int_events & FEC_ENET_MII) {
968 complete(&fep->mdio_done);
970 } while (int_events);
975 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
977 struct net_device *ndev = napi->dev;
978 int pkts = fec_enet_rx(ndev, budget);
979 struct fec_enet_private *fep = netdev_priv(ndev);
985 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
990 /* ------------------------------------------------------------------------- */
991 static void fec_get_mac(struct net_device *ndev)
993 struct fec_enet_private *fep = netdev_priv(ndev);
994 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
995 unsigned char *iap, tmpaddr[ETH_ALEN];
998 * try to get mac address in following order:
1000 * 1) module parameter via kernel command line in form
1001 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1006 * 2) from device tree data
1008 if (!is_valid_ether_addr(iap)) {
1009 struct device_node *np = fep->pdev->dev.of_node;
1011 const char *mac = of_get_mac_address(np);
1013 iap = (unsigned char *) mac;
1018 * 3) from flash or fuse (via platform data)
1020 if (!is_valid_ether_addr(iap)) {
1023 iap = (unsigned char *)FEC_FLASHMAC;
1026 iap = (unsigned char *)&pdata->mac;
1031 * 4) FEC mac registers set by bootloader
1033 if (!is_valid_ether_addr(iap)) {
1034 *((unsigned long *) &tmpaddr[0]) =
1035 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
1036 *((unsigned short *) &tmpaddr[4]) =
1037 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1042 * 5) random mac address
1044 if (!is_valid_ether_addr(iap)) {
1045 /* Report it and use a random ethernet address instead */
1046 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1047 eth_hw_addr_random(ndev);
1048 netdev_info(ndev, "Using random MAC address: %pM\n",
1053 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1055 /* Adjust MAC if using macaddr */
1057 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1060 /* ------------------------------------------------------------------------- */
1065 static void fec_enet_adjust_link(struct net_device *ndev)
1067 struct fec_enet_private *fep = netdev_priv(ndev);
1068 struct phy_device *phy_dev = fep->phy_dev;
1069 int status_change = 0;
1071 /* Prevent a state halted on mii error */
1072 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1073 phy_dev->state = PHY_RESUMING;
1077 if (phy_dev->link) {
1079 fep->link = phy_dev->link;
1083 if (fep->full_duplex != phy_dev->duplex)
1086 if (phy_dev->speed != fep->speed) {
1087 fep->speed = phy_dev->speed;
1091 /* if any of the above changed restart the FEC */
1093 fec_restart(ndev, phy_dev->duplex);
1097 fep->link = phy_dev->link;
1103 phy_print_status(phy_dev);
1106 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1108 struct fec_enet_private *fep = bus->priv;
1109 unsigned long time_left;
1111 fep->mii_timeout = 0;
1112 init_completion(&fep->mdio_done);
1114 /* start a read op */
1115 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1116 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1117 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1119 /* wait for end of transfer */
1120 time_left = wait_for_completion_timeout(&fep->mdio_done,
1121 usecs_to_jiffies(FEC_MII_TIMEOUT));
1122 if (time_left == 0) {
1123 fep->mii_timeout = 1;
1124 netdev_err(fep->netdev, "MDIO read timeout\n");
1129 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1132 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1135 struct fec_enet_private *fep = bus->priv;
1136 unsigned long time_left;
1138 fep->mii_timeout = 0;
1139 init_completion(&fep->mdio_done);
1141 /* start a write op */
1142 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1143 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1144 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1145 fep->hwp + FEC_MII_DATA);
1147 /* wait for end of transfer */
1148 time_left = wait_for_completion_timeout(&fep->mdio_done,
1149 usecs_to_jiffies(FEC_MII_TIMEOUT));
1150 if (time_left == 0) {
1151 fep->mii_timeout = 1;
1152 netdev_err(fep->netdev, "MDIO write timeout\n");
1159 static int fec_enet_mdio_reset(struct mii_bus *bus)
1164 static int fec_enet_mii_probe(struct net_device *ndev)
1166 struct fec_enet_private *fep = netdev_priv(ndev);
1167 const struct platform_device_id *id_entry =
1168 platform_get_device_id(fep->pdev);
1169 struct phy_device *phy_dev = NULL;
1170 char mdio_bus_id[MII_BUS_ID_SIZE];
1171 char phy_name[MII_BUS_ID_SIZE + 3];
1173 int dev_id = fep->dev_id;
1175 fep->phy_dev = NULL;
1177 /* check for attached phy */
1178 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1179 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1181 if (fep->mii_bus->phy_map[phy_id] == NULL)
1183 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1187 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1191 if (phy_id >= PHY_MAX_ADDR) {
1192 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1193 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1197 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1198 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1199 fep->phy_interface);
1200 if (IS_ERR(phy_dev)) {
1201 netdev_err(ndev, "could not attach to PHY\n");
1202 return PTR_ERR(phy_dev);
1205 /* mask with MAC supported features */
1206 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1207 phy_dev->supported &= PHY_GBIT_FEATURES;
1208 phy_dev->supported |= SUPPORTED_Pause;
1211 phy_dev->supported &= PHY_BASIC_FEATURES;
1213 phy_dev->advertising = phy_dev->supported;
1215 fep->phy_dev = phy_dev;
1217 fep->full_duplex = 0;
1219 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1220 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1226 static int fec_enet_mii_init(struct platform_device *pdev)
1228 static struct mii_bus *fec0_mii_bus;
1229 struct net_device *ndev = platform_get_drvdata(pdev);
1230 struct fec_enet_private *fep = netdev_priv(ndev);
1231 const struct platform_device_id *id_entry =
1232 platform_get_device_id(fep->pdev);
1233 int err = -ENXIO, i;
1236 * The dual fec interfaces are not equivalent with enet-mac.
1237 * Here are the differences:
1239 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1240 * - fec0 acts as the 1588 time master while fec1 is slave
1241 * - external phys can only be configured by fec0
1243 * That is to say fec1 can not work independently. It only works
1244 * when fec0 is working. The reason behind this design is that the
1245 * second interface is added primarily for Switch mode.
1247 * Because of the last point above, both phys are attached on fec0
1248 * mdio interface in board design, and need to be configured by
1251 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1252 /* fec1 uses fec0 mii_bus */
1253 if (mii_cnt && fec0_mii_bus) {
1254 fep->mii_bus = fec0_mii_bus;
1261 fep->mii_timeout = 0;
1264 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1266 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1267 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1268 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1271 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1272 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1274 fep->phy_speed <<= 1;
1275 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1277 fep->mii_bus = mdiobus_alloc();
1278 if (fep->mii_bus == NULL) {
1283 fep->mii_bus->name = "fec_enet_mii_bus";
1284 fep->mii_bus->read = fec_enet_mdio_read;
1285 fep->mii_bus->write = fec_enet_mdio_write;
1286 fep->mii_bus->reset = fec_enet_mdio_reset;
1287 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1288 pdev->name, fep->dev_id + 1);
1289 fep->mii_bus->priv = fep;
1290 fep->mii_bus->parent = &pdev->dev;
1292 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1293 if (!fep->mii_bus->irq) {
1295 goto err_out_free_mdiobus;
1298 for (i = 0; i < PHY_MAX_ADDR; i++)
1299 fep->mii_bus->irq[i] = PHY_POLL;
1301 if (mdiobus_register(fep->mii_bus))
1302 goto err_out_free_mdio_irq;
1306 /* save fec0 mii_bus */
1307 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1308 fec0_mii_bus = fep->mii_bus;
1312 err_out_free_mdio_irq:
1313 kfree(fep->mii_bus->irq);
1314 err_out_free_mdiobus:
1315 mdiobus_free(fep->mii_bus);
1320 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1322 if (--mii_cnt == 0) {
1323 mdiobus_unregister(fep->mii_bus);
1324 kfree(fep->mii_bus->irq);
1325 mdiobus_free(fep->mii_bus);
1329 static int fec_enet_get_settings(struct net_device *ndev,
1330 struct ethtool_cmd *cmd)
1332 struct fec_enet_private *fep = netdev_priv(ndev);
1333 struct phy_device *phydev = fep->phy_dev;
1338 return phy_ethtool_gset(phydev, cmd);
1341 static int fec_enet_set_settings(struct net_device *ndev,
1342 struct ethtool_cmd *cmd)
1344 struct fec_enet_private *fep = netdev_priv(ndev);
1345 struct phy_device *phydev = fep->phy_dev;
1350 return phy_ethtool_sset(phydev, cmd);
1353 static void fec_enet_get_drvinfo(struct net_device *ndev,
1354 struct ethtool_drvinfo *info)
1356 struct fec_enet_private *fep = netdev_priv(ndev);
1358 strlcpy(info->driver, fep->pdev->dev.driver->name,
1359 sizeof(info->driver));
1360 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1361 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1364 static int fec_enet_get_ts_info(struct net_device *ndev,
1365 struct ethtool_ts_info *info)
1367 struct fec_enet_private *fep = netdev_priv(ndev);
1369 if (fep->bufdesc_ex) {
1371 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1372 SOF_TIMESTAMPING_RX_SOFTWARE |
1373 SOF_TIMESTAMPING_SOFTWARE |
1374 SOF_TIMESTAMPING_TX_HARDWARE |
1375 SOF_TIMESTAMPING_RX_HARDWARE |
1376 SOF_TIMESTAMPING_RAW_HARDWARE;
1378 info->phc_index = ptp_clock_index(fep->ptp_clock);
1380 info->phc_index = -1;
1382 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1383 (1 << HWTSTAMP_TX_ON);
1385 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1386 (1 << HWTSTAMP_FILTER_ALL);
1389 return ethtool_op_get_ts_info(ndev, info);
1393 static void fec_enet_get_pauseparam(struct net_device *ndev,
1394 struct ethtool_pauseparam *pause)
1396 struct fec_enet_private *fep = netdev_priv(ndev);
1398 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1399 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1400 pause->rx_pause = pause->tx_pause;
1403 static int fec_enet_set_pauseparam(struct net_device *ndev,
1404 struct ethtool_pauseparam *pause)
1406 struct fec_enet_private *fep = netdev_priv(ndev);
1408 if (pause->tx_pause != pause->rx_pause) {
1410 "hardware only support enable/disable both tx and rx");
1414 fep->pause_flag = 0;
1416 /* tx pause must be same as rx pause */
1417 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1418 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1420 if (pause->rx_pause || pause->autoneg) {
1421 fep->phy_dev->supported |= ADVERTISED_Pause;
1422 fep->phy_dev->advertising |= ADVERTISED_Pause;
1424 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1425 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1428 if (pause->autoneg) {
1429 if (netif_running(ndev))
1431 phy_start_aneg(fep->phy_dev);
1433 if (netif_running(ndev))
1434 fec_restart(ndev, 0);
1439 static const struct ethtool_ops fec_enet_ethtool_ops = {
1440 .get_pauseparam = fec_enet_get_pauseparam,
1441 .set_pauseparam = fec_enet_set_pauseparam,
1442 .get_settings = fec_enet_get_settings,
1443 .set_settings = fec_enet_set_settings,
1444 .get_drvinfo = fec_enet_get_drvinfo,
1445 .get_link = ethtool_op_get_link,
1446 .get_ts_info = fec_enet_get_ts_info,
1449 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1451 struct fec_enet_private *fep = netdev_priv(ndev);
1452 struct phy_device *phydev = fep->phy_dev;
1454 if (!netif_running(ndev))
1460 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1461 return fec_ptp_ioctl(ndev, rq, cmd);
1463 return phy_mii_ioctl(phydev, rq, cmd);
1466 static void fec_enet_free_buffers(struct net_device *ndev)
1468 struct fec_enet_private *fep = netdev_priv(ndev);
1470 struct sk_buff *skb;
1471 struct bufdesc *bdp;
1473 bdp = fep->rx_bd_base;
1474 for (i = 0; i < RX_RING_SIZE; i++) {
1475 skb = fep->rx_skbuff[i];
1477 if (bdp->cbd_bufaddr)
1478 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1479 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1482 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1485 bdp = fep->tx_bd_base;
1486 for (i = 0; i < TX_RING_SIZE; i++)
1487 kfree(fep->tx_bounce[i]);
1490 static int fec_enet_alloc_buffers(struct net_device *ndev)
1492 struct fec_enet_private *fep = netdev_priv(ndev);
1494 struct sk_buff *skb;
1495 struct bufdesc *bdp;
1497 bdp = fep->rx_bd_base;
1498 for (i = 0; i < RX_RING_SIZE; i++) {
1499 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1501 fec_enet_free_buffers(ndev);
1504 fep->rx_skbuff[i] = skb;
1506 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1507 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1508 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1510 if (fep->bufdesc_ex) {
1511 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1512 ebdp->cbd_esc = BD_ENET_RX_INT;
1515 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1518 /* Set the last buffer to wrap. */
1519 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1520 bdp->cbd_sc |= BD_SC_WRAP;
1522 bdp = fep->tx_bd_base;
1523 for (i = 0; i < TX_RING_SIZE; i++) {
1524 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1527 bdp->cbd_bufaddr = 0;
1529 if (fep->bufdesc_ex) {
1530 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1531 ebdp->cbd_esc = BD_ENET_TX_INT;
1534 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1537 /* Set the last buffer to wrap. */
1538 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1539 bdp->cbd_sc |= BD_SC_WRAP;
1545 fec_enet_open(struct net_device *ndev)
1547 struct fec_enet_private *fep = netdev_priv(ndev);
1550 napi_enable(&fep->napi);
1552 /* I should reset the ring buffers here, but I don't yet know
1553 * a simple way to do that.
1556 ret = fec_enet_alloc_buffers(ndev);
1560 /* Probe and connect to PHY when open the interface */
1561 ret = fec_enet_mii_probe(ndev);
1563 fec_enet_free_buffers(ndev);
1566 phy_start(fep->phy_dev);
1567 netif_start_queue(ndev);
1573 fec_enet_close(struct net_device *ndev)
1575 struct fec_enet_private *fep = netdev_priv(ndev);
1577 /* Don't know what to do yet. */
1578 napi_disable(&fep->napi);
1580 netif_stop_queue(ndev);
1584 phy_stop(fep->phy_dev);
1585 phy_disconnect(fep->phy_dev);
1588 fec_enet_free_buffers(ndev);
1593 /* Set or clear the multicast filter for this adaptor.
1594 * Skeleton taken from sunlance driver.
1595 * The CPM Ethernet implementation allows Multicast as well as individual
1596 * MAC address filtering. Some of the drivers check to make sure it is
1597 * a group multicast address, and discard those that are not. I guess I
1598 * will do the same for now, but just remove the test if you want
1599 * individual filtering as well (do the upper net layers want or support
1600 * this kind of feature?).
1603 #define HASH_BITS 6 /* #bits in hash */
1604 #define CRC32_POLY 0xEDB88320
1606 static void set_multicast_list(struct net_device *ndev)
1608 struct fec_enet_private *fep = netdev_priv(ndev);
1609 struct netdev_hw_addr *ha;
1610 unsigned int i, bit, data, crc, tmp;
1613 if (ndev->flags & IFF_PROMISC) {
1614 tmp = readl(fep->hwp + FEC_R_CNTRL);
1616 writel(tmp, fep->hwp + FEC_R_CNTRL);
1620 tmp = readl(fep->hwp + FEC_R_CNTRL);
1622 writel(tmp, fep->hwp + FEC_R_CNTRL);
1624 if (ndev->flags & IFF_ALLMULTI) {
1625 /* Catch all multicast addresses, so set the
1628 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1629 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1634 /* Clear filter and add the addresses in hash register
1636 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1637 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1639 netdev_for_each_mc_addr(ha, ndev) {
1640 /* calculate crc32 value of mac address */
1643 for (i = 0; i < ndev->addr_len; i++) {
1645 for (bit = 0; bit < 8; bit++, data >>= 1) {
1647 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1651 /* only upper 6 bits (HASH_BITS) are used
1652 * which point to specific bit in he hash registers
1654 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1657 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1658 tmp |= 1 << (hash - 32);
1659 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1661 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1663 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1668 /* Set a MAC change in hardware. */
1670 fec_set_mac_address(struct net_device *ndev, void *p)
1672 struct fec_enet_private *fep = netdev_priv(ndev);
1673 struct sockaddr *addr = p;
1675 if (!is_valid_ether_addr(addr->sa_data))
1676 return -EADDRNOTAVAIL;
1678 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1680 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1681 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1682 fep->hwp + FEC_ADDR_LOW);
1683 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1684 fep->hwp + FEC_ADDR_HIGH);
1688 #ifdef CONFIG_NET_POLL_CONTROLLER
1690 * fec_poll_controller - FEC Poll controller function
1691 * @dev: The FEC network adapter
1693 * Polled functionality used by netconsole and others in non interrupt mode
1696 static void fec_poll_controller(struct net_device *dev)
1699 struct fec_enet_private *fep = netdev_priv(dev);
1701 for (i = 0; i < FEC_IRQ_NUM; i++) {
1702 if (fep->irq[i] > 0) {
1703 disable_irq(fep->irq[i]);
1704 fec_enet_interrupt(fep->irq[i], dev);
1705 enable_irq(fep->irq[i]);
1711 static int fec_set_features(struct net_device *netdev,
1712 netdev_features_t features)
1714 struct fec_enet_private *fep = netdev_priv(netdev);
1715 netdev_features_t changed = features ^ netdev->features;
1717 netdev->features = features;
1719 /* Receive checksum has been changed */
1720 if (changed & NETIF_F_RXCSUM) {
1721 if (features & NETIF_F_RXCSUM)
1722 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1724 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1726 if (netif_running(netdev)) {
1728 fec_restart(netdev, fep->phy_dev->duplex);
1729 netif_wake_queue(netdev);
1731 fec_restart(netdev, fep->phy_dev->duplex);
1738 static const struct net_device_ops fec_netdev_ops = {
1739 .ndo_open = fec_enet_open,
1740 .ndo_stop = fec_enet_close,
1741 .ndo_start_xmit = fec_enet_start_xmit,
1742 .ndo_set_rx_mode = set_multicast_list,
1743 .ndo_change_mtu = eth_change_mtu,
1744 .ndo_validate_addr = eth_validate_addr,
1745 .ndo_tx_timeout = fec_timeout,
1746 .ndo_set_mac_address = fec_set_mac_address,
1747 .ndo_do_ioctl = fec_enet_ioctl,
1748 #ifdef CONFIG_NET_POLL_CONTROLLER
1749 .ndo_poll_controller = fec_poll_controller,
1751 .ndo_set_features = fec_set_features,
1755 * XXX: We need to clean up on failure exits here.
1758 static int fec_enet_init(struct net_device *ndev)
1760 struct fec_enet_private *fep = netdev_priv(ndev);
1761 const struct platform_device_id *id_entry =
1762 platform_get_device_id(fep->pdev);
1763 struct bufdesc *cbd_base;
1765 /* Allocate memory for buffer descriptors. */
1766 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1771 memset(cbd_base, 0, PAGE_SIZE);
1775 /* Get the Ethernet address */
1778 /* Set receive and transmit descriptor base. */
1779 fep->rx_bd_base = cbd_base;
1780 if (fep->bufdesc_ex)
1781 fep->tx_bd_base = (struct bufdesc *)
1782 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1784 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1786 /* The FEC Ethernet specific entries in the device structure */
1787 ndev->watchdog_timeo = TX_TIMEOUT;
1788 ndev->netdev_ops = &fec_netdev_ops;
1789 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1791 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1792 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1794 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
1795 /* enable hw accelerator */
1796 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1798 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1800 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1803 fec_restart(ndev, 0);
1809 static void fec_reset_phy(struct platform_device *pdev)
1813 struct device_node *np = pdev->dev.of_node;
1818 of_property_read_u32(np, "phy-reset-duration", &msec);
1819 /* A sane reset duration should not be longer than 1s */
1823 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1824 if (!gpio_is_valid(phy_reset))
1827 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1828 GPIOF_OUT_INIT_LOW, "phy-reset");
1830 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1834 gpio_set_value(phy_reset, 1);
1836 #else /* CONFIG_OF */
1837 static void fec_reset_phy(struct platform_device *pdev)
1840 * In case of platform probe, the reset has been done
1844 #endif /* CONFIG_OF */
1847 fec_probe(struct platform_device *pdev)
1849 struct fec_enet_private *fep;
1850 struct fec_platform_data *pdata;
1851 struct net_device *ndev;
1852 int i, irq, ret = 0;
1854 const struct of_device_id *of_id;
1856 struct pinctrl *pinctrl;
1857 struct regulator *reg_phy;
1859 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1861 pdev->id_entry = of_id->data;
1863 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1867 /* Init network device */
1868 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1872 SET_NETDEV_DEV(ndev, &pdev->dev);
1874 /* setup board info structure */
1875 fep = netdev_priv(ndev);
1877 /* default enable pause frame auto negotiation */
1878 if (pdev->id_entry &&
1879 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1880 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1882 fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
1884 fep->dev_id = dev_id++;
1886 fep->bufdesc_ex = 0;
1890 goto failed_ioremap;
1893 platform_set_drvdata(pdev, ndev);
1895 ret = of_get_phy_mode(pdev->dev.of_node);
1897 pdata = pdev->dev.platform_data;
1899 fep->phy_interface = pdata->phy;
1901 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1903 fep->phy_interface = ret;
1906 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1907 if (IS_ERR(pinctrl)) {
1908 ret = PTR_ERR(pinctrl);
1912 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1913 if (IS_ERR(fep->clk_ipg)) {
1914 ret = PTR_ERR(fep->clk_ipg);
1918 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1919 if (IS_ERR(fep->clk_ahb)) {
1920 ret = PTR_ERR(fep->clk_ahb);
1924 /* enet_out is optional, depends on board */
1925 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
1926 if (IS_ERR(fep->clk_enet_out))
1927 fep->clk_enet_out = NULL;
1929 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1931 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1932 if (IS_ERR(fep->clk_ptp)) {
1933 fep->clk_ptp = NULL;
1934 fep->bufdesc_ex = 0;
1937 clk_prepare_enable(fep->clk_ahb);
1938 clk_prepare_enable(fep->clk_ipg);
1939 clk_prepare_enable(fep->clk_enet_out);
1940 clk_prepare_enable(fep->clk_ptp);
1942 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1943 if (!IS_ERR(reg_phy)) {
1944 ret = regulator_enable(reg_phy);
1947 "Failed to enable phy regulator: %d\n", ret);
1948 goto failed_regulator;
1952 fec_reset_phy(pdev);
1954 if (fep->bufdesc_ex)
1955 fec_ptp_init(ndev, pdev);
1957 ret = fec_enet_init(ndev);
1961 for (i = 0; i < FEC_IRQ_NUM; i++) {
1962 irq = platform_get_irq(pdev, i);
1969 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1972 irq = platform_get_irq(pdev, i);
1973 free_irq(irq, ndev);
1979 ret = fec_enet_mii_init(pdev);
1981 goto failed_mii_init;
1983 /* Carrier starts down, phylib will bring it up */
1984 netif_carrier_off(ndev);
1986 ret = register_netdev(ndev);
1988 goto failed_register;
1990 if (fep->bufdesc_ex && fep->ptp_clock)
1991 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
1993 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
1997 fec_enet_mii_remove(fep);
2000 for (i = 0; i < FEC_IRQ_NUM; i++) {
2001 irq = platform_get_irq(pdev, i);
2003 free_irq(irq, ndev);
2007 clk_disable_unprepare(fep->clk_ahb);
2008 clk_disable_unprepare(fep->clk_ipg);
2009 clk_disable_unprepare(fep->clk_enet_out);
2010 clk_disable_unprepare(fep->clk_ptp);
2020 fec_drv_remove(struct platform_device *pdev)
2022 struct net_device *ndev = platform_get_drvdata(pdev);
2023 struct fec_enet_private *fep = netdev_priv(ndev);
2026 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2027 unregister_netdev(ndev);
2028 fec_enet_mii_remove(fep);
2029 del_timer_sync(&fep->time_keep);
2030 clk_disable_unprepare(fep->clk_ptp);
2032 ptp_clock_unregister(fep->ptp_clock);
2033 clk_disable_unprepare(fep->clk_enet_out);
2034 clk_disable_unprepare(fep->clk_ahb);
2035 clk_disable_unprepare(fep->clk_ipg);
2036 for (i = 0; i < FEC_IRQ_NUM; i++) {
2037 int irq = platform_get_irq(pdev, i);
2039 free_irq(irq, ndev);
2043 platform_set_drvdata(pdev, NULL);
2048 #ifdef CONFIG_PM_SLEEP
2050 fec_suspend(struct device *dev)
2052 struct net_device *ndev = dev_get_drvdata(dev);
2053 struct fec_enet_private *fep = netdev_priv(ndev);
2055 if (netif_running(ndev)) {
2057 netif_device_detach(ndev);
2059 clk_disable_unprepare(fep->clk_enet_out);
2060 clk_disable_unprepare(fep->clk_ahb);
2061 clk_disable_unprepare(fep->clk_ipg);
2067 fec_resume(struct device *dev)
2069 struct net_device *ndev = dev_get_drvdata(dev);
2070 struct fec_enet_private *fep = netdev_priv(ndev);
2072 clk_prepare_enable(fep->clk_enet_out);
2073 clk_prepare_enable(fep->clk_ahb);
2074 clk_prepare_enable(fep->clk_ipg);
2075 if (netif_running(ndev)) {
2076 fec_restart(ndev, fep->full_duplex);
2077 netif_device_attach(ndev);
2082 #endif /* CONFIG_PM_SLEEP */
2084 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2086 static struct platform_driver fec_driver = {
2088 .name = DRIVER_NAME,
2089 .owner = THIS_MODULE,
2091 .of_match_table = fec_dt_ids,
2093 .id_table = fec_devtype,
2095 .remove = fec_drv_remove,
2098 module_platform_driver(fec_driver);
2100 MODULE_LICENSE("GPL");