1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2019 NXP */
4 #include <linux/mdio.h>
5 #include <linux/of_mdio.h>
6 #include <linux/iopoll.h>
11 struct enetc_mdio_regs {
12 u32 mdio_cfg; /* MDIO configuration and status */
13 u32 mdio_ctl; /* MDIO control */
14 u32 mdio_data; /* MDIO data */
15 u32 mdio_addr; /* MDIO address */
18 #define bus_to_enetc_regs(bus) (struct enetc_mdio_regs __iomem *)((bus)->priv)
20 #define ENETC_MDIO_REG_OFFSET 0x1c00
21 #define ENETC_MDC_DIV 258
23 #define MDIO_CFG_CLKDIV(x) ((((x) >> 1) & 0xff) << 8)
24 #define MDIO_CFG_BSY BIT(0)
25 #define MDIO_CFG_RD_ER BIT(1)
26 #define MDIO_CFG_ENC45 BIT(6)
27 /* external MDIO only - driven on neg MDC edge */
28 #define MDIO_CFG_NEG BIT(23)
30 #define MDIO_CTL_DEV_ADDR(x) ((x) & 0x1f)
31 #define MDIO_CTL_PORT_ADDR(x) (((x) & 0x1f) << 5)
32 #define MDIO_CTL_READ BIT(15)
33 #define MDIO_DATA(x) ((x) & 0xffff)
36 static int enetc_mdio_wait_complete(struct enetc_mdio_regs __iomem *regs)
40 return readx_poll_timeout(enetc_rd_reg, ®s->mdio_cfg, val,
41 !(val & MDIO_CFG_BSY), 10, 10 * TIMEOUT);
44 static int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
47 struct enetc_mdio_regs __iomem *regs = bus_to_enetc_regs(bus);
48 u32 mdio_ctl, mdio_cfg;
52 mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
53 if (regnum & MII_ADDR_C45) {
54 dev_addr = (regnum >> 16) & 0x1f;
55 mdio_cfg |= MDIO_CFG_ENC45;
57 /* clause 22 (ie 1G) */
58 dev_addr = regnum & 0x1f;
59 mdio_cfg &= ~MDIO_CFG_ENC45;
62 enetc_wr_reg(®s->mdio_cfg, mdio_cfg);
64 ret = enetc_mdio_wait_complete(regs);
68 /* set port and dev addr */
69 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
70 enetc_wr_reg(®s->mdio_ctl, mdio_ctl);
72 /* set the register address */
73 if (regnum & MII_ADDR_C45) {
74 enetc_wr_reg(®s->mdio_addr, regnum & 0xffff);
76 ret = enetc_mdio_wait_complete(regs);
82 enetc_wr_reg(®s->mdio_data, MDIO_DATA(value));
84 ret = enetc_mdio_wait_complete(regs);
91 static int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
93 struct enetc_mdio_regs __iomem *regs = bus_to_enetc_regs(bus);
94 u32 mdio_ctl, mdio_cfg;
98 mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
99 if (regnum & MII_ADDR_C45) {
100 dev_addr = (regnum >> 16) & 0x1f;
101 mdio_cfg |= MDIO_CFG_ENC45;
103 dev_addr = regnum & 0x1f;
104 mdio_cfg &= ~MDIO_CFG_ENC45;
107 enetc_wr_reg(®s->mdio_cfg, mdio_cfg);
109 ret = enetc_mdio_wait_complete(regs);
113 /* set port and device addr */
114 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
115 enetc_wr_reg(®s->mdio_ctl, mdio_ctl);
117 /* set the register address */
118 if (regnum & MII_ADDR_C45) {
119 enetc_wr_reg(®s->mdio_addr, regnum & 0xffff);
121 ret = enetc_mdio_wait_complete(regs);
126 /* initiate the read */
127 enetc_wr_reg(®s->mdio_ctl, mdio_ctl | MDIO_CTL_READ);
129 ret = enetc_mdio_wait_complete(regs);
133 /* return all Fs if nothing was there */
134 if (enetc_rd_reg(®s->mdio_cfg) & MDIO_CFG_RD_ER) {
136 "Error while reading PHY%d reg at %d.%hhu\n",
137 phy_id, dev_addr, regnum);
141 value = enetc_rd_reg(®s->mdio_data) & 0xffff;
146 int enetc_mdio_probe(struct enetc_pf *pf)
148 struct device *dev = &pf->si->pdev->dev;
149 struct enetc_mdio_regs __iomem *regs;
150 struct device_node *np;
154 bus = mdiobus_alloc_size(sizeof(regs));
158 bus->name = "Freescale ENETC MDIO Bus";
159 bus->read = enetc_mdio_read;
160 bus->write = enetc_mdio_write;
162 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
164 /* store the enetc mdio base address for this bus */
165 regs = pf->si->hw.port + ENETC_MDIO_REG_OFFSET;
168 np = of_get_child_by_name(dev->of_node, "mdio");
170 dev_err(dev, "MDIO node missing\n");
172 goto err_registration;
175 ret = of_mdiobus_register(bus, np);
178 dev_err(dev, "cannot register MDIO bus\n");
179 goto err_registration;
193 void enetc_mdio_remove(struct enetc_pf *pf)
196 mdiobus_unregister(pf->mdio);
197 mdiobus_free(pf->mdio);