drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
   3  * Copyright 2016-2020 NXP
   4  */
   5 #include <linux/init.h>
   6 #include <linux/module.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/of_net.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/msi.h>
  12 #include <linux/kthread.h>
  13 #include <linux/iommu.h>
  14 #include <linux/net_tstamp.h>
  15 #include <linux/fsl/mc.h>
  16 #include <linux/bpf.h>
  17 #include <linux/bpf_trace.h>
  18 #include <net/sock.h>
  19
  20 #include "dpaa2-eth.h"
  21
  22 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
  23  * using trace events only need to #include <trace/events/sched.h>
  24  */
  25 #define CREATE_TRACE_POINTS
  26 #include "dpaa2-eth-trace.h"
  27
  28 MODULE_LICENSE("Dual BSD/GPL");
  29 MODULE_AUTHOR("Freescale Semiconductor, Inc");
  30 MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
  31
  32 static void *dpaa2_iova_to_virt(struct iommu_domain *domain,
  33                                 dma_addr_t iova_addr)
  34 {
  35         phys_addr_t phys_addr;
  36
  37         phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
  38
  39         return phys_to_virt(phys_addr);
  40 }
  41
  42 static void validate_rx_csum(struct dpaa2_eth_priv *priv,
  43                              u32 fd_status,
  44                              struct sk_buff *skb)
  45 {
  46         skb_checksum_none_assert(skb);
  47
  48         /* HW checksum validation is disabled, nothing to do here */
  49         if (!(priv->net_dev->features & NETIF_F_RXCSUM))
  50                 return;
  51
  52         /* Read checksum validation bits */
  53         if (!((fd_status & DPAA2_FAS_L3CV) &&
  54               (fd_status & DPAA2_FAS_L4CV)))
  55                 return;
  56
  57         /* Inform the stack there's no need to compute L3/L4 csum anymore */
  58         skb->ip_summed = CHECKSUM_UNNECESSARY;
  59 }
  60
  61 /* Free a received FD.
  62  * Not to be used for Tx conf FDs or on any other paths.
  63  */
  64 static void free_rx_fd(struct dpaa2_eth_priv *priv,
  65                        const struct dpaa2_fd *fd,
  66                        void *vaddr)
  67 {
  68         struct device *dev = priv->net_dev->dev.parent;
  69         dma_addr_t addr = dpaa2_fd_get_addr(fd);
  70         u8 fd_format = dpaa2_fd_get_format(fd);
  71         struct dpaa2_sg_entry *sgt;
  72         void *sg_vaddr;
  73         int i;
  74
  75         /* If single buffer frame, just free the data buffer */
  76         if (fd_format == dpaa2_fd_single)
  77                 goto free_buf;
  78         else if (fd_format != dpaa2_fd_sg)
  79                 /* We don't support any other format */
  80                 return;
  81
  82         /* For S/G frames, we first need to free all SG entries
  83          * except the first one, which was taken care of already
  84          */
  85         sgt = vaddr + dpaa2_fd_get_offset(fd);
  86         for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
  87                 addr = dpaa2_sg_get_addr(&sgt[i]);
  88                 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
  89                 dma_unmap_page(dev, addr, priv->rx_buf_size,
  90                                DMA_BIDIRECTIONAL);
  91
  92                 free_pages((unsigned long)sg_vaddr, 0);
  93                 if (dpaa2_sg_is_final(&sgt[i]))
  94                         break;
  95         }
  96
  97 free_buf:
  98         free_pages((unsigned long)vaddr, 0);
  99 }
 100
 101 /* Build a linear skb based on a single-buffer frame descriptor */
 102 static struct sk_buff *build_linear_skb(struct dpaa2_eth_channel *ch,
 103                                         const struct dpaa2_fd *fd,
 104                                         void *fd_vaddr)
 105 {
 106         struct sk_buff *skb = NULL;
 107         u16 fd_offset = dpaa2_fd_get_offset(fd);
 108         u32 fd_length = dpaa2_fd_get_len(fd);
 109
 110         ch->buf_count--;
 111
 112         skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
 113         if (unlikely(!skb))
 114                 return NULL;
 115
 116         skb_reserve(skb, fd_offset);
 117         skb_put(skb, fd_length);
 118
 119         return skb;
 120 }
 121
 122 /* Build a non linear (fragmented) skb based on a S/G table */
 123 static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv,
 124                                       struct dpaa2_eth_channel *ch,
 125                                       struct dpaa2_sg_entry *sgt)
 126 {
 127         struct sk_buff *skb = NULL;
 128         struct device *dev = priv->net_dev->dev.parent;
 129         void *sg_vaddr;
 130         dma_addr_t sg_addr;
 131         u16 sg_offset;
 132         u32 sg_length;
 133         struct page *page, *head_page;
 134         int page_offset;
 135         int i;
 136
 137         for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
 138                 struct dpaa2_sg_entry *sge = &sgt[i];
 139
 140                 /* NOTE: We only support SG entries in dpaa2_sg_single format,
 141                  * but this is the only format we may receive from HW anyway
 142                  */
 143
 144                 /* Get the address and length from the S/G entry */
 145                 sg_addr = dpaa2_sg_get_addr(sge);
 146                 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
 147                 dma_unmap_page(dev, sg_addr, priv->rx_buf_size,
 148                                DMA_BIDIRECTIONAL);
 149
 150                 sg_length = dpaa2_sg_get_len(sge);
 151
 152                 if (i == 0) {
 153                         /* We build the skb around the first data buffer */
 154                         skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
 155                         if (unlikely(!skb)) {
 156                                 /* Free the first SG entry now, since we already
 157                                  * unmapped it and obtained the virtual address
 158                                  */
 159                                 free_pages((unsigned long)sg_vaddr, 0);
 160
 161                                 /* We still need to subtract the buffers used
 162                                  * by this FD from our software counter
 163                                  */
 164                                 while (!dpaa2_sg_is_final(&sgt[i]) &&
 165                                        i < DPAA2_ETH_MAX_SG_ENTRIES)
 166                                         i++;
 167                                 break;
 168                         }
 169
 170                         sg_offset = dpaa2_sg_get_offset(sge);
 171                         skb_reserve(skb, sg_offset);
 172                         skb_put(skb, sg_length);
 173                 } else {
 174                         /* Rest of the data buffers are stored as skb frags */
 175                         page = virt_to_page(sg_vaddr);
 176                         head_page = virt_to_head_page(sg_vaddr);
 177
 178                         /* Offset in page (which may be compound).
 179                          * Data in subsequent SG entries is stored from the
 180                          * beginning of the buffer, so we don't need to add the
 181                          * sg_offset.
 182                          */
 183                         page_offset = ((unsigned long)sg_vaddr &
 184                                 (PAGE_SIZE - 1)) +
 185                                 (page_address(page) - page_address(head_page));
 186
 187                         skb_add_rx_frag(skb, i - 1, head_page, page_offset,
 188                                         sg_length, priv->rx_buf_size);
 189                 }
 190
 191                 if (dpaa2_sg_is_final(sge))
 192                         break;
 193         }
 194
 195         WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
 196
 197         /* Count all data buffers + SG table buffer */
 198         ch->buf_count -= i + 2;
 199
 200         return skb;
 201 }
 202
 203 /* Free buffers acquired from the buffer pool or which were meant to
 204  * be released in the pool
 205  */
 206 static void free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array, int count)
 207 {
 208         struct device *dev = priv->net_dev->dev.parent;
 209         void *vaddr;
 210         int i;
 211
 212         for (i = 0; i < count; i++) {
 213                 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
 214                 dma_unmap_page(dev, buf_array[i], priv->rx_buf_size,
 215                                DMA_BIDIRECTIONAL);
 216                 free_pages((unsigned long)vaddr, 0);
 217         }
 218 }
 219
 220 static void xdp_release_buf(struct dpaa2_eth_priv *priv,
 221                             struct dpaa2_eth_channel *ch,
 222                             dma_addr_t addr)
 223 {
 224         int retries = 0;
 225         int err;
 226
 227         ch->xdp.drop_bufs[ch->xdp.drop_cnt++] = addr;
 228         if (ch->xdp.drop_cnt < DPAA2_ETH_BUFS_PER_CMD)
 229                 return;
 230
 231         while ((err = dpaa2_io_service_release(ch->dpio, priv->bpid,
 232                                                ch->xdp.drop_bufs,
 233                                                ch->xdp.drop_cnt)) == -EBUSY) {
 234                 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
 235                         break;
 236                 cpu_relax();
 237         }
 238
 239         if (err) {
 240                 free_bufs(priv, ch->xdp.drop_bufs, ch->xdp.drop_cnt);
 241                 ch->buf_count -= ch->xdp.drop_cnt;
 242         }
 243
 244         ch->xdp.drop_cnt = 0;
 245 }
 246
 247 static int dpaa2_eth_xdp_flush(struct dpaa2_eth_priv *priv,
 248                                struct dpaa2_eth_fq *fq,
 249                                struct dpaa2_eth_xdp_fds *xdp_fds)
 250 {
 251         int total_enqueued = 0, retries = 0, enqueued;
 252         struct dpaa2_eth_drv_stats *percpu_extras;
 253         int num_fds, err, max_retries;
 254         struct dpaa2_fd *fds;
 255
 256         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 257
 258         /* try to enqueue all the FDs until the max number of retries is hit */
 259         fds = xdp_fds->fds;
 260         num_fds = xdp_fds->num;
 261         max_retries = num_fds * DPAA2_ETH_ENQUEUE_RETRIES;
 262         while (total_enqueued < num_fds && retries < max_retries) {
 263                 err = priv->enqueue(priv, fq, &fds[total_enqueued],
 264                                     0, num_fds - total_enqueued, &enqueued);
 265                 if (err == -EBUSY) {
 266                         percpu_extras->tx_portal_busy += ++retries;
 267                         continue;
 268                 }
 269                 total_enqueued += enqueued;
 270         }
 271         xdp_fds->num = 0;
 272
 273         return total_enqueued;
 274 }
 275
 276 static void xdp_tx_flush(struct dpaa2_eth_priv *priv,
 277                          struct dpaa2_eth_channel *ch,
 278                          struct dpaa2_eth_fq *fq)
 279 {
 280         struct rtnl_link_stats64 *percpu_stats;
 281         struct dpaa2_fd *fds;
 282         int enqueued, i;
 283
 284         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 285
 286         // enqueue the array of XDP_TX frames
 287         enqueued = dpaa2_eth_xdp_flush(priv, fq, &fq->xdp_tx_fds);
 288
 289         /* update statistics */
 290         percpu_stats->tx_packets += enqueued;
 291         fds = fq->xdp_tx_fds.fds;
 292         for (i = 0; i < enqueued; i++) {
 293                 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
 294                 ch->stats.xdp_tx++;
 295         }
 296         for (i = enqueued; i < fq->xdp_tx_fds.num; i++) {
 297                 xdp_release_buf(priv, ch, dpaa2_fd_get_addr(&fds[i]));
 298                 percpu_stats->tx_errors++;
 299                 ch->stats.xdp_tx_err++;
 300         }
 301         fq->xdp_tx_fds.num = 0;
 302 }
 303
 304 static void xdp_enqueue(struct dpaa2_eth_priv *priv,
 305                         struct dpaa2_eth_channel *ch,
 306                         struct dpaa2_fd *fd,
 307                         void *buf_start, u16 queue_id)
 308 {
 309         struct dpaa2_faead *faead;
 310         struct dpaa2_fd *dest_fd;
 311         struct dpaa2_eth_fq *fq;
 312         u32 ctrl, frc;
 313
 314         /* Mark the egress frame hardware annotation area as valid */
 315         frc = dpaa2_fd_get_frc(fd);
 316         dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
 317         dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL);
 318
 319         /* Instruct hardware to release the FD buffer directly into
 320          * the buffer pool once transmission is completed, instead of
 321          * sending a Tx confirmation frame to us
 322          */
 323         ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV;
 324         faead = dpaa2_get_faead(buf_start, false);
 325         faead->ctrl = cpu_to_le32(ctrl);
 326         faead->conf_fqid = 0;
 327
 328         fq = &priv->fq[queue_id];
 329         dest_fd = &fq->xdp_tx_fds.fds[fq->xdp_tx_fds.num++];
 330         memcpy(dest_fd, fd, sizeof(*dest_fd));
 331
 332         if (fq->xdp_tx_fds.num < DEV_MAP_BULK_SIZE)
 333                 return;
 334
 335         xdp_tx_flush(priv, ch, fq);
 336 }
 337
 338 static u32 run_xdp(struct dpaa2_eth_priv *priv,
 339                    struct dpaa2_eth_channel *ch,
 340                    struct dpaa2_eth_fq *rx_fq,
 341                    struct dpaa2_fd *fd, void *vaddr)
 342 {
 343         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 344         struct bpf_prog *xdp_prog;
 345         struct xdp_buff xdp;
 346         u32 xdp_act = XDP_PASS;
 347         int err;
 348
 349         rcu_read_lock();
 350
 351         xdp_prog = READ_ONCE(ch->xdp.prog);
 352         if (!xdp_prog)
 353                 goto out;
 354
 355         xdp.data = vaddr + dpaa2_fd_get_offset(fd);
 356         xdp.data_end = xdp.data + dpaa2_fd_get_len(fd);
 357         xdp.data_hard_start = xdp.data - XDP_PACKET_HEADROOM;
 358         xdp_set_data_meta_invalid(&xdp);
 359         xdp.rxq = &ch->xdp_rxq;
 360
 361         xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE -
 362                 (dpaa2_fd_get_offset(fd) - XDP_PACKET_HEADROOM);
 363
 364         xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
 365
 366         /* xdp.data pointer may have changed */
 367         dpaa2_fd_set_offset(fd, xdp.data - vaddr);
 368         dpaa2_fd_set_len(fd, xdp.data_end - xdp.data);
 369
 370         switch (xdp_act) {
 371         case XDP_PASS:
 372                 break;
 373         case XDP_TX:
 374                 xdp_enqueue(priv, ch, fd, vaddr, rx_fq->flowid);
 375                 break;
 376         default:
 377                 bpf_warn_invalid_xdp_action(xdp_act);
 378                 /* fall through */
 379         case XDP_ABORTED:
 380                 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
 381                 /* fall through */
 382         case XDP_DROP:
 383                 xdp_release_buf(priv, ch, addr);
 384                 ch->stats.xdp_drop++;
 385                 break;
 386         case XDP_REDIRECT:
 387                 dma_unmap_page(priv->net_dev->dev.parent, addr,
 388                                priv->rx_buf_size, DMA_BIDIRECTIONAL);
 389                 ch->buf_count--;
 390
 391                 /* Allow redirect use of full headroom */
 392                 xdp.data_hard_start = vaddr;
 393                 xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE;
 394
 395                 err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
 396                 if (unlikely(err))
 397                         ch->stats.xdp_drop++;
 398                 else
 399                         ch->stats.xdp_redirect++;
 400                 break;
 401         }
 402
 403         ch->xdp.res |= xdp_act;
 404 out:
 405         rcu_read_unlock();
 406         return xdp_act;
 407 }
 408
 409 /* Main Rx frame processing routine */
 410 static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
 411                          struct dpaa2_eth_channel *ch,
 412                          const struct dpaa2_fd *fd,
 413                          struct dpaa2_eth_fq *fq)
 414 {
 415         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 416         u8 fd_format = dpaa2_fd_get_format(fd);
 417         void *vaddr;
 418         struct sk_buff *skb;
 419         struct rtnl_link_stats64 *percpu_stats;
 420         struct dpaa2_eth_drv_stats *percpu_extras;
 421         struct device *dev = priv->net_dev->dev.parent;
 422         struct dpaa2_fas *fas;
 423         void *buf_data;
 424         u32 status = 0;
 425         u32 xdp_act;
 426
 427         /* Tracing point */
 428         trace_dpaa2_rx_fd(priv->net_dev, fd);
 429
 430         vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
 431         dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
 432                                 DMA_BIDIRECTIONAL);
 433
 434         fas = dpaa2_get_fas(vaddr, false);
 435         prefetch(fas);
 436         buf_data = vaddr + dpaa2_fd_get_offset(fd);
 437         prefetch(buf_data);
 438
 439         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 440         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 441
 442         if (fd_format == dpaa2_fd_single) {
 443                 xdp_act = run_xdp(priv, ch, fq, (struct dpaa2_fd *)fd, vaddr);
 444                 if (xdp_act != XDP_PASS) {
 445                         percpu_stats->rx_packets++;
 446                         percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
 447                         return;
 448                 }
 449
 450                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 451                                DMA_BIDIRECTIONAL);
 452                 skb = build_linear_skb(ch, fd, vaddr);
 453         } else if (fd_format == dpaa2_fd_sg) {
 454                 WARN_ON(priv->xdp_prog);
 455
 456                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 457                                DMA_BIDIRECTIONAL);
 458                 skb = build_frag_skb(priv, ch, buf_data);
 459                 free_pages((unsigned long)vaddr, 0);
 460                 percpu_extras->rx_sg_frames++;
 461                 percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
 462         } else {
 463                 /* We don't support any other format */
 464                 goto err_frame_format;
 465         }
 466
 467         if (unlikely(!skb))
 468                 goto err_build_skb;
 469
 470         prefetch(skb->data);
 471
 472         /* Get the timestamp value */
 473         if (priv->rx_tstamp) {
 474                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
 475                 __le64 *ts = dpaa2_get_ts(vaddr, false);
 476                 u64 ns;
 477
 478                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 479
 480                 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
 481                 shhwtstamps->hwtstamp = ns_to_ktime(ns);
 482         }
 483
 484         /* Check if we need to validate the L4 csum */
 485         if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
 486                 status = le32_to_cpu(fas->status);
 487                 validate_rx_csum(priv, status, skb);
 488         }
 489
 490         skb->protocol = eth_type_trans(skb, priv->net_dev);
 491         skb_record_rx_queue(skb, fq->flowid);
 492
 493         percpu_stats->rx_packets++;
 494         percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
 495
 496         list_add_tail(&skb->list, ch->rx_list);
 497
 498         return;
 499
 500 err_build_skb:
 501         free_rx_fd(priv, fd, vaddr);
 502 err_frame_format:
 503         percpu_stats->rx_dropped++;
 504 }
 505
 506 /* Consume all frames pull-dequeued into the store. This is the simplest way to
 507  * make sure we don't accidentally issue another volatile dequeue which would
 508  * overwrite (leak) frames already in the store.
 509  *
 510  * Observance of NAPI budget is not our concern, leaving that to the caller.
 511  */
 512 static int consume_frames(struct dpaa2_eth_channel *ch,
 513                           struct dpaa2_eth_fq **src)
 514 {
 515         struct dpaa2_eth_priv *priv = ch->priv;
 516         struct dpaa2_eth_fq *fq = NULL;
 517         struct dpaa2_dq *dq;
 518         const struct dpaa2_fd *fd;
 519         int cleaned = 0, retries = 0;
 520         int is_last;
 521
 522         do {
 523                 dq = dpaa2_io_store_next(ch->store, &is_last);
 524                 if (unlikely(!dq)) {
 525                         /* If we're here, we *must* have placed a
 526                          * volatile dequeue comnmand, so keep reading through
 527                          * the store until we get some sort of valid response
 528                          * token (either a valid frame or an "empty dequeue")
 529                          */
 530                         if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) {
 531                                 netdev_err_once(priv->net_dev,
 532                                                 "Unable to read a valid dequeue response\n");
 533                                 return -ETIMEDOUT;
 534                         }
 535                         continue;
 536                 }
 537
 538                 fd = dpaa2_dq_fd(dq);
 539                 fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
 540
 541                 fq->consume(priv, ch, fd, fq);
 542                 cleaned++;
 543                 retries = 0;
 544         } while (!is_last);
 545
 546         if (!cleaned)
 547                 return 0;
 548
 549         fq->stats.frames += cleaned;
 550         ch->stats.frames += cleaned;
 551
 552         /* A dequeue operation only pulls frames from a single queue
 553          * into the store. Return the frame queue as an out param.
 554          */
 555         if (src)
 556                 *src = fq;
 557
 558         return cleaned;
 559 }
 560
 561 /* Configure the egress frame annotation for timestamp update */
 562 static void enable_tx_tstamp(struct dpaa2_fd *fd, void *buf_start)
 563 {
 564         struct dpaa2_faead *faead;
 565         u32 ctrl, frc;
 566
 567         /* Mark the egress frame annotation area as valid */
 568         frc = dpaa2_fd_get_frc(fd);
 569         dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
 570
 571         /* Set hardware annotation size */
 572         ctrl = dpaa2_fd_get_ctrl(fd);
 573         dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
 574
 575         /* enable UPD (update prepanded data) bit in FAEAD field of
 576          * hardware frame annotation area
 577          */
 578         ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
 579         faead = dpaa2_get_faead(buf_start, true);
 580         faead->ctrl = cpu_to_le32(ctrl);
 581 }
 582
 583 /* Create a frame descriptor based on a fragmented skb */
 584 static int build_sg_fd(struct dpaa2_eth_priv *priv,
 585                        struct sk_buff *skb,
 586                        struct dpaa2_fd *fd)
 587 {
 588         struct device *dev = priv->net_dev->dev.parent;
 589         void *sgt_buf = NULL;
 590         dma_addr_t addr;
 591         int nr_frags = skb_shinfo(skb)->nr_frags;
 592         struct dpaa2_sg_entry *sgt;
 593         int i, err;
 594         int sgt_buf_size;
 595         struct scatterlist *scl, *crt_scl;
 596         int num_sg;
 597         int num_dma_bufs;
 598         struct dpaa2_eth_swa *swa;
 599
 600         /* Create and map scatterlist.
 601          * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
 602          * to go beyond nr_frags+1.
 603          * Note: We don't support chained scatterlists
 604          */
 605         if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
 606                 return -EINVAL;
 607
 608         scl = kcalloc(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
 609         if (unlikely(!scl))
 610                 return -ENOMEM;
 611
 612         sg_init_table(scl, nr_frags + 1);
 613         num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
 614         num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
 615         if (unlikely(!num_dma_bufs)) {
 616                 err = -ENOMEM;
 617                 goto dma_map_sg_failed;
 618         }
 619
 620         /* Prepare the HW SGT structure */
 621         sgt_buf_size = priv->tx_data_offset +
 622                        sizeof(struct dpaa2_sg_entry) *  num_dma_bufs;
 623         sgt_buf = napi_alloc_frag(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN);
 624         if (unlikely(!sgt_buf)) {
 625                 err = -ENOMEM;
 626                 goto sgt_buf_alloc_failed;
 627         }
 628         sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
 629         memset(sgt_buf, 0, sgt_buf_size);
 630
 631         sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
 632
 633         /* Fill in the HW SGT structure.
 634          *
 635          * sgt_buf is zeroed out, so the following fields are implicit
 636          * in all sgt entries:
 637          *   - offset is 0
 638          *   - format is 'dpaa2_sg_single'
 639          */
 640         for_each_sg(scl, crt_scl, num_dma_bufs, i) {
 641                 dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
 642                 dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
 643         }
 644         dpaa2_sg_set_final(&sgt[i - 1], true);
 645
 646         /* Store the skb backpointer in the SGT buffer.
 647          * Fit the scatterlist and the number of buffers alongside the
 648          * skb backpointer in the software annotation area. We'll need
 649          * all of them on Tx Conf.
 650          */
 651         swa = (struct dpaa2_eth_swa *)sgt_buf;
 652         swa->type = DPAA2_ETH_SWA_SG;
 653         swa->sg.skb = skb;
 654         swa->sg.scl = scl;
 655         swa->sg.num_sg = num_sg;
 656         swa->sg.sgt_size = sgt_buf_size;
 657
 658         /* Separately map the SGT buffer */
 659         addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
 660         if (unlikely(dma_mapping_error(dev, addr))) {
 661                 err = -ENOMEM;
 662                 goto dma_map_single_failed;
 663         }
 664         dpaa2_fd_set_offset(fd, priv->tx_data_offset);
 665         dpaa2_fd_set_format(fd, dpaa2_fd_sg);
 666         dpaa2_fd_set_addr(fd, addr);
 667         dpaa2_fd_set_len(fd, skb->len);
 668         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 669
 670         if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
 671                 enable_tx_tstamp(fd, sgt_buf);
 672
 673         return 0;
 674
 675 dma_map_single_failed:
 676         skb_free_frag(sgt_buf);
 677 sgt_buf_alloc_failed:
 678         dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
 679 dma_map_sg_failed:
 680         kfree(scl);
 681         return err;
 682 }
 683
 684 /* Create a frame descriptor based on a linear skb */
 685 static int build_single_fd(struct dpaa2_eth_priv *priv,
 686                            struct sk_buff *skb,
 687                            struct dpaa2_fd *fd)
 688 {
 689         struct device *dev = priv->net_dev->dev.parent;
 690         u8 *buffer_start, *aligned_start;
 691         struct dpaa2_eth_swa *swa;
 692         dma_addr_t addr;
 693
 694         buffer_start = skb->data - dpaa2_eth_needed_headroom(priv, skb);
 695
 696         /* If there's enough room to align the FD address, do it.
 697          * It will help hardware optimize accesses.
 698          */
 699         aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
 700                                   DPAA2_ETH_TX_BUF_ALIGN);
 701         if (aligned_start >= skb->head)
 702                 buffer_start = aligned_start;
 703
 704         /* Store a backpointer to the skb at the beginning of the buffer
 705          * (in the private data area) such that we can release it
 706          * on Tx confirm
 707          */
 708         swa = (struct dpaa2_eth_swa *)buffer_start;
 709         swa->type = DPAA2_ETH_SWA_SINGLE;
 710         swa->single.skb = skb;
 711
 712         addr = dma_map_single(dev, buffer_start,
 713                               skb_tail_pointer(skb) - buffer_start,
 714                               DMA_BIDIRECTIONAL);
 715         if (unlikely(dma_mapping_error(dev, addr)))
 716                 return -ENOMEM;
 717
 718         dpaa2_fd_set_addr(fd, addr);
 719         dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
 720         dpaa2_fd_set_len(fd, skb->len);
 721         dpaa2_fd_set_format(fd, dpaa2_fd_single);
 722         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 723
 724         if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
 725                 enable_tx_tstamp(fd, buffer_start);
 726
 727         return 0;
 728 }
 729
 730 /* FD freeing routine on the Tx path
 731  *
 732  * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb
 733  * back-pointed to is also freed.
 734  * This can be called either from dpaa2_eth_tx_conf() or on the error path of
 735  * dpaa2_eth_tx().
 736  */
 737 static void free_tx_fd(const struct dpaa2_eth_priv *priv,
 738                        struct dpaa2_eth_fq *fq,
 739                        const struct dpaa2_fd *fd, bool in_napi)
 740 {
 741         struct device *dev = priv->net_dev->dev.parent;
 742         dma_addr_t fd_addr;
 743         struct sk_buff *skb = NULL;
 744         unsigned char *buffer_start;
 745         struct dpaa2_eth_swa *swa;
 746         u8 fd_format = dpaa2_fd_get_format(fd);
 747         u32 fd_len = dpaa2_fd_get_len(fd);
 748
 749         fd_addr = dpaa2_fd_get_addr(fd);
 750         buffer_start = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
 751         swa = (struct dpaa2_eth_swa *)buffer_start;
 752
 753         if (fd_format == dpaa2_fd_single) {
 754                 if (swa->type == DPAA2_ETH_SWA_SINGLE) {
 755                         skb = swa->single.skb;
 756                         /* Accessing the skb buffer is safe before dma unmap,
 757                          * because we didn't map the actual skb shell.
 758                          */
 759                         dma_unmap_single(dev, fd_addr,
 760                                          skb_tail_pointer(skb) - buffer_start,
 761                                          DMA_BIDIRECTIONAL);
 762                 } else {
 763                         WARN_ONCE(swa->type != DPAA2_ETH_SWA_XDP, "Wrong SWA type");
 764                         dma_unmap_single(dev, fd_addr, swa->xdp.dma_size,
 765                                          DMA_BIDIRECTIONAL);
 766                 }
 767         } else if (fd_format == dpaa2_fd_sg) {
 768                 skb = swa->sg.skb;
 769
 770                 /* Unmap the scatterlist */
 771                 dma_unmap_sg(dev, swa->sg.scl, swa->sg.num_sg,
 772                              DMA_BIDIRECTIONAL);
 773                 kfree(swa->sg.scl);
 774
 775                 /* Unmap the SGT buffer */
 776                 dma_unmap_single(dev, fd_addr, swa->sg.sgt_size,
 777                                  DMA_BIDIRECTIONAL);
 778         } else {
 779                 netdev_dbg(priv->net_dev, "Invalid FD format\n");
 780                 return;
 781         }
 782
 783         if (swa->type != DPAA2_ETH_SWA_XDP && in_napi) {
 784                 fq->dq_frames++;
 785                 fq->dq_bytes += fd_len;
 786         }
 787
 788         if (swa->type == DPAA2_ETH_SWA_XDP) {
 789                 xdp_return_frame(swa->xdp.xdpf);
 790                 return;
 791         }
 792
 793         /* Get the timestamp value */
 794         if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
 795                 struct skb_shared_hwtstamps shhwtstamps;
 796                 __le64 *ts = dpaa2_get_ts(buffer_start, true);
 797                 u64 ns;
 798
 799                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 800
 801                 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
 802                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
 803                 skb_tstamp_tx(skb, &shhwtstamps);
 804         }
 805
 806         /* Free SGT buffer allocated on tx */
 807         if (fd_format != dpaa2_fd_single)
 808                 skb_free_frag(buffer_start);
 809
 810         /* Move on with skb release */
 811         napi_consume_skb(skb, in_napi);
 812 }
 813
 814 static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
 815 {
 816         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
 817         struct dpaa2_fd fd;
 818         struct rtnl_link_stats64 *percpu_stats;
 819         struct dpaa2_eth_drv_stats *percpu_extras;
 820         struct dpaa2_eth_fq *fq;
 821         struct netdev_queue *nq;
 822         u16 queue_mapping;
 823         unsigned int needed_headroom;
 824         u32 fd_len;
 825         u8 prio = 0;
 826         int err, i;
 827
 828         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 829         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 830
 831         needed_headroom = dpaa2_eth_needed_headroom(priv, skb);
 832         if (skb_headroom(skb) < needed_headroom) {
 833                 struct sk_buff *ns;
 834
 835                 ns = skb_realloc_headroom(skb, needed_headroom);
 836                 if (unlikely(!ns)) {
 837                         percpu_stats->tx_dropped++;
 838                         goto err_alloc_headroom;
 839                 }
 840                 percpu_extras->tx_reallocs++;
 841
 842                 if (skb->sk)
 843                         skb_set_owner_w(ns, skb->sk);
 844
 845                 dev_kfree_skb(skb);
 846                 skb = ns;
 847         }
 848
 849         /* We'll be holding a back-reference to the skb until Tx Confirmation;
 850          * we don't want that overwritten by a concurrent Tx with a cloned skb.
 851          */
 852         skb = skb_unshare(skb, GFP_ATOMIC);
 853         if (unlikely(!skb)) {
 854                 /* skb_unshare() has already freed the skb */
 855                 percpu_stats->tx_dropped++;
 856                 return NETDEV_TX_OK;
 857         }
 858
 859         /* Setup the FD fields */
 860         memset(&fd, 0, sizeof(fd));
 861
 862         if (skb_is_nonlinear(skb)) {
 863                 err = build_sg_fd(priv, skb, &fd);
 864                 percpu_extras->tx_sg_frames++;
 865                 percpu_extras->tx_sg_bytes += skb->len;
 866         } else {
 867                 err = build_single_fd(priv, skb, &fd);
 868         }
 869
 870         if (unlikely(err)) {
 871                 percpu_stats->tx_dropped++;
 872                 goto err_build_fd;
 873         }
 874
 875         /* Tracing point */
 876         trace_dpaa2_tx_fd(net_dev, &fd);
 877
 878         /* TxConf FQ selection relies on queue id from the stack.
 879          * In case of a forwarded frame from another DPNI interface, we choose
 880          * a queue affined to the same core that processed the Rx frame
 881          */
 882         queue_mapping = skb_get_queue_mapping(skb);
 883
 884         if (net_dev->num_tc) {
 885                 prio = netdev_txq_to_tc(net_dev, queue_mapping);
 886                 /* Hardware interprets priority level 0 as being the highest,
 887                  * so we need to do a reverse mapping to the netdev tc index
 888                  */
 889                 prio = net_dev->num_tc - prio - 1;
 890                 /* We have only one FQ array entry for all Tx hardware queues
 891                  * with the same flow id (but different priority levels)
 892                  */
 893                 queue_mapping %= dpaa2_eth_queue_count(priv);
 894         }
 895         fq = &priv->fq[queue_mapping];
 896
 897         fd_len = dpaa2_fd_get_len(&fd);
 898         nq = netdev_get_tx_queue(net_dev, queue_mapping);
 899         netdev_tx_sent_queue(nq, fd_len);
 900
 901         /* Everything that happens after this enqueues might race with
 902          * the Tx confirmation callback for this frame
 903          */
 904         for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
 905                 err = priv->enqueue(priv, fq, &fd, prio, 1, NULL);
 906                 if (err != -EBUSY)
 907                         break;
 908         }
 909         percpu_extras->tx_portal_busy += i;
 910         if (unlikely(err < 0)) {
 911                 percpu_stats->tx_errors++;
 912                 /* Clean up everything, including freeing the skb */
 913                 free_tx_fd(priv, fq, &fd, false);
 914                 netdev_tx_completed_queue(nq, 1, fd_len);
 915         } else {
 916                 percpu_stats->tx_packets++;
 917                 percpu_stats->tx_bytes += fd_len;
 918         }
 919
 920         return NETDEV_TX_OK;
 921
 922 err_build_fd:
 923 err_alloc_headroom:
 924         dev_kfree_skb(skb);
 925
 926         return NETDEV_TX_OK;
 927 }
 928
 929 /* Tx confirmation frame processing routine */
 930 static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
 931                               struct dpaa2_eth_channel *ch __always_unused,
 932                               const struct dpaa2_fd *fd,
 933                               struct dpaa2_eth_fq *fq)
 934 {
 935         struct rtnl_link_stats64 *percpu_stats;
 936         struct dpaa2_eth_drv_stats *percpu_extras;
 937         u32 fd_len = dpaa2_fd_get_len(fd);
 938         u32 fd_errors;
 939
 940         /* Tracing point */
 941         trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
 942
 943         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 944         percpu_extras->tx_conf_frames++;
 945         percpu_extras->tx_conf_bytes += fd_len;
 946
 947         /* Check frame errors in the FD field */
 948         fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
 949         free_tx_fd(priv, fq, fd, true);
 950
 951         if (likely(!fd_errors))
 952                 return;
 953
 954         if (net_ratelimit())
 955                 netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
 956                            fd_errors);
 957
 958         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 959         /* Tx-conf logically pertains to the egress path. */
 960         percpu_stats->tx_errors++;
 961 }
 962
 963 static int set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
 964 {
 965         int err;
 966
 967         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
 968                                DPNI_OFF_RX_L3_CSUM, enable);
 969         if (err) {
 970                 netdev_err(priv->net_dev,
 971                            "dpni_set_offload(RX_L3_CSUM) failed\n");
 972                 return err;
 973         }
 974
 975         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
 976                                DPNI_OFF_RX_L4_CSUM, enable);
 977         if (err) {
 978                 netdev_err(priv->net_dev,
 979                            "dpni_set_offload(RX_L4_CSUM) failed\n");
 980                 return err;
 981         }
 982
 983         return 0;
 984 }
 985
 986 static int set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
 987 {
 988         int err;
 989
 990         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
 991                                DPNI_OFF_TX_L3_CSUM, enable);
 992         if (err) {
 993                 netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n");
 994                 return err;
 995         }
 996
 997         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
 998                                DPNI_OFF_TX_L4_CSUM, enable);
 999         if (err) {
1000                 netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n");
1001                 return err;
1002         }
1003
1004         return 0;
1005 }
1006
1007 /* Perform a single release command to add buffers
1008  * to the specified buffer pool
1009  */
1010 static int add_bufs(struct dpaa2_eth_priv *priv,
1011                     struct dpaa2_eth_channel *ch, u16 bpid)
1012 {
1013         struct device *dev = priv->net_dev->dev.parent;
1014         u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1015         struct page *page;
1016         dma_addr_t addr;
1017         int retries = 0;
1018         int i, err;
1019
1020         for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
1021                 /* Allocate buffer visible to WRIOP + skb shared info +
1022                  * alignment padding
1023                  */
1024                 /* allocate one page for each Rx buffer. WRIOP sees
1025                  * the entire page except for a tailroom reserved for
1026                  * skb shared info
1027                  */
1028                 page = dev_alloc_pages(0);
1029                 if (!page)
1030                         goto err_alloc;
1031
1032                 addr = dma_map_page(dev, page, 0, priv->rx_buf_size,
1033                                     DMA_BIDIRECTIONAL);
1034                 if (unlikely(dma_mapping_error(dev, addr)))
1035                         goto err_map;
1036
1037                 buf_array[i] = addr;
1038
1039                 /* tracing point */
1040                 trace_dpaa2_eth_buf_seed(priv->net_dev,
1041                                          page, DPAA2_ETH_RX_BUF_RAW_SIZE,
1042                                          addr, priv->rx_buf_size,
1043                                          bpid);
1044         }
1045
1046 release_bufs:
1047         /* In case the portal is busy, retry until successful */
1048         while ((err = dpaa2_io_service_release(ch->dpio, bpid,
1049                                                buf_array, i)) == -EBUSY) {
1050                 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
1051                         break;
1052                 cpu_relax();
1053         }
1054
1055         /* If release command failed, clean up and bail out;
1056          * not much else we can do about it
1057          */
1058         if (err) {
1059                 free_bufs(priv, buf_array, i);
1060                 return 0;
1061         }
1062
1063         return i;
1064
1065 err_map:
1066         __free_pages(page, 0);
1067 err_alloc:
1068         /* If we managed to allocate at least some buffers,
1069          * release them to hardware
1070          */
1071         if (i)
1072                 goto release_bufs;
1073
1074         return 0;
1075 }
1076
1077 static int seed_pool(struct dpaa2_eth_priv *priv, u16 bpid)
1078 {
1079         int i, j;
1080         int new_count;
1081
1082         for (j = 0; j < priv->num_channels; j++) {
1083                 for (i = 0; i < DPAA2_ETH_NUM_BUFS;
1084                      i += DPAA2_ETH_BUFS_PER_CMD) {
1085                         new_count = add_bufs(priv, priv->channel[j], bpid);
1086                         priv->channel[j]->buf_count += new_count;
1087
1088                         if (new_count < DPAA2_ETH_BUFS_PER_CMD) {
1089                                 return -ENOMEM;
1090                         }
1091                 }
1092         }
1093
1094         return 0;
1095 }
1096
1097 /**
1098  * Drain the specified number of buffers from the DPNI's private buffer pool.
1099  * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD
1100  */
1101 static void drain_bufs(struct dpaa2_eth_priv *priv, int count)
1102 {
1103         u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1104         int retries = 0;
1105         int ret;
1106
1107         do {
1108                 ret = dpaa2_io_service_acquire(NULL, priv->bpid,
1109                                                buf_array, count);
1110                 if (ret < 0) {
1111                         if (ret == -EBUSY &&
1112                             retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
1113                                 continue;
1114                         netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
1115                         return;
1116                 }
1117                 free_bufs(priv, buf_array, ret);
1118                 retries = 0;
1119         } while (ret);
1120 }
1121
1122 static void drain_pool(struct dpaa2_eth_priv *priv)
1123 {
1124         int i;
1125
1126         drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD);
1127         drain_bufs(priv, 1);
1128
1129         for (i = 0; i < priv->num_channels; i++)
1130                 priv->channel[i]->buf_count = 0;
1131 }
1132
1133 /* Function is called from softirq context only, so we don't need to guard
1134  * the access to percpu count
1135  */
1136 static int refill_pool(struct dpaa2_eth_priv *priv,
1137                        struct dpaa2_eth_channel *ch,
1138                        u16 bpid)
1139 {
1140         int new_count;
1141
1142         if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH))
1143                 return 0;
1144
1145         do {
1146                 new_count = add_bufs(priv, ch, bpid);
1147                 if (unlikely(!new_count)) {
1148                         /* Out of memory; abort for now, we'll try later on */
1149                         break;
1150                 }
1151                 ch->buf_count += new_count;
1152         } while (ch->buf_count < DPAA2_ETH_NUM_BUFS);
1153
1154         if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS))
1155                 return -ENOMEM;
1156
1157         return 0;
1158 }
1159
1160 static int pull_channel(struct dpaa2_eth_channel *ch)
1161 {
1162         int err;
1163         int dequeues = -1;
1164
1165         /* Retry while portal is busy */
1166         do {
1167                 err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id,
1168                                                     ch->store);
1169                 dequeues++;
1170                 cpu_relax();
1171         } while (err == -EBUSY && dequeues < DPAA2_ETH_SWP_BUSY_RETRIES);
1172
1173         ch->stats.dequeue_portal_busy += dequeues;
1174         if (unlikely(err))
1175                 ch->stats.pull_err++;
1176
1177         return err;
1178 }
1179
1180 /* NAPI poll routine
1181  *
1182  * Frames are dequeued from the QMan channel associated with this NAPI context.
1183  * Rx, Tx confirmation and (if configured) Rx error frames all count
1184  * towards the NAPI budget.
1185  */
1186 static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
1187 {
1188         struct dpaa2_eth_channel *ch;
1189         struct dpaa2_eth_priv *priv;
1190         int rx_cleaned = 0, txconf_cleaned = 0;
1191         struct dpaa2_eth_fq *fq, *txc_fq = NULL;
1192         struct netdev_queue *nq;
1193         int store_cleaned, work_done;
1194         struct list_head rx_list;
1195         int retries = 0;
1196         u16 flowid;
1197         int err;
1198
1199         ch = container_of(napi, struct dpaa2_eth_channel, napi);
1200         ch->xdp.res = 0;
1201         priv = ch->priv;
1202
1203         INIT_LIST_HEAD(&rx_list);
1204         ch->rx_list = &rx_list;
1205
1206         do {
1207                 err = pull_channel(ch);
1208                 if (unlikely(err))
1209                         break;
1210
1211                 /* Refill pool if appropriate */
1212                 refill_pool(priv, ch, priv->bpid);
1213
1214                 store_cleaned = consume_frames(ch, &fq);
1215                 if (store_cleaned <= 0)
1216                         break;
1217                 if (fq->type == DPAA2_RX_FQ) {
1218                         rx_cleaned += store_cleaned;
1219                         flowid = fq->flowid;
1220                 } else {
1221                         txconf_cleaned += store_cleaned;
1222                         /* We have a single Tx conf FQ on this channel */
1223                         txc_fq = fq;
1224                 }
1225
1226                 /* If we either consumed the whole NAPI budget with Rx frames
1227                  * or we reached the Tx confirmations threshold, we're done.
1228                  */
1229                 if (rx_cleaned >= budget ||
1230                     txconf_cleaned >= DPAA2_ETH_TXCONF_PER_NAPI) {
1231                         work_done = budget;
1232                         goto out;
1233                 }
1234         } while (store_cleaned);
1235
1236         /* We didn't consume the entire budget, so finish napi and
1237          * re-enable data availability notifications
1238          */
1239         napi_complete_done(napi, rx_cleaned);
1240         do {
1241                 err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx);
1242                 cpu_relax();
1243         } while (err == -EBUSY && retries++ < DPAA2_ETH_SWP_BUSY_RETRIES);
1244         WARN_ONCE(err, "CDAN notifications rearm failed on core %d",
1245                   ch->nctx.desired_cpu);
1246
1247         work_done = max(rx_cleaned, 1);
1248
1249 out:
1250         netif_receive_skb_list(ch->rx_list);
1251
1252         if (txc_fq && txc_fq->dq_frames) {
1253                 nq = netdev_get_tx_queue(priv->net_dev, txc_fq->flowid);
1254                 netdev_tx_completed_queue(nq, txc_fq->dq_frames,
1255                                           txc_fq->dq_bytes);
1256                 txc_fq->dq_frames = 0;
1257                 txc_fq->dq_bytes = 0;
1258         }
1259
1260         if (ch->xdp.res & XDP_REDIRECT)
1261                 xdp_do_flush_map();
1262         else if (rx_cleaned && ch->xdp.res & XDP_TX)
1263                 xdp_tx_flush(priv, ch, &priv->fq[flowid]);
1264
1265         return work_done;
1266 }
1267
1268 static void enable_ch_napi(struct dpaa2_eth_priv *priv)
1269 {
1270         struct dpaa2_eth_channel *ch;
1271         int i;
1272
1273         for (i = 0; i < priv->num_channels; i++) {
1274                 ch = priv->channel[i];
1275                 napi_enable(&ch->napi);
1276         }
1277 }
1278
1279 static void disable_ch_napi(struct dpaa2_eth_priv *priv)
1280 {
1281         struct dpaa2_eth_channel *ch;
1282         int i;
1283
1284         for (i = 0; i < priv->num_channels; i++) {
1285                 ch = priv->channel[i];
1286                 napi_disable(&ch->napi);
1287         }
1288 }
1289
1290 static void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
1291                                       bool tx_pause)
1292 {
1293         struct dpni_taildrop td = {0};
1294         struct dpaa2_eth_fq *fq;
1295         int i, err;
1296
1297         td.enable = !tx_pause;
1298         if (priv->rx_td_enabled == td.enable)
1299                 return;
1300
1301         /* FQ taildrop: threshold is in bytes, per frame queue */
1302         td.threshold = DPAA2_ETH_FQ_TAILDROP_THRESH;
1303         td.units = DPNI_CONGESTION_UNIT_BYTES;
1304
1305         for (i = 0; i < priv->num_fqs; i++) {
1306                 fq = &priv->fq[i];
1307                 if (fq->type != DPAA2_RX_FQ)
1308                         continue;
1309                 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
1310                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
1311                                         fq->tc, fq->flowid, &td);
1312                 if (err) {
1313                         netdev_err(priv->net_dev,
1314                                    "dpni_set_taildrop(FQ) failed\n");
1315                         return;
1316                 }
1317         }
1318
1319         /* Congestion group taildrop: threshold is in frames, per group
1320          * of FQs belonging to the same traffic class
1321          */
1322         td.threshold = DPAA2_ETH_CG_TAILDROP_THRESH(priv);
1323         td.units = DPNI_CONGESTION_UNIT_FRAMES;
1324         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
1325                 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
1326                                         DPNI_CP_GROUP, DPNI_QUEUE_RX,
1327                                         i, 0, &td);
1328                 if (err) {
1329                         netdev_err(priv->net_dev,
1330                                    "dpni_set_taildrop(CG) failed\n");
1331                         return;
1332                 }
1333         }
1334
1335         priv->rx_td_enabled = td.enable;
1336 }
1337
1338 static int link_state_update(struct dpaa2_eth_priv *priv)
1339 {
1340         struct dpni_link_state state = {0};
1341         bool tx_pause;
1342         int err;
1343
1344         err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
1345         if (unlikely(err)) {
1346                 netdev_err(priv->net_dev,
1347                            "dpni_get_link_state() failed\n");
1348                 return err;
1349         }
1350
1351         /* If Tx pause frame settings have changed, we need to update
1352          * Rx FQ taildrop configuration as well. We configure taildrop
1353          * only when pause frame generation is disabled.
1354          */
1355         tx_pause = dpaa2_eth_tx_pause_enabled(state.options);
1356         dpaa2_eth_set_rx_taildrop(priv, tx_pause);
1357
1358         /* When we manage the MAC/PHY using phylink there is no need
1359          * to manually update the netif_carrier.
1360          */
1361         if (priv->mac)
1362                 goto out;
1363
1364         /* Chech link state; speed / duplex changes are not treated yet */
1365         if (priv->link_state.up == state.up)
1366                 goto out;
1367
1368         if (state.up) {
1369                 netif_carrier_on(priv->net_dev);
1370                 netif_tx_start_all_queues(priv->net_dev);
1371         } else {
1372                 netif_tx_stop_all_queues(priv->net_dev);
1373                 netif_carrier_off(priv->net_dev);
1374         }
1375
1376         netdev_info(priv->net_dev, "Link Event: state %s\n",
1377                     state.up ? "up" : "down");
1378
1379 out:
1380         priv->link_state = state;
1381
1382         return 0;
1383 }
1384
1385 static int dpaa2_eth_open(struct net_device *net_dev)
1386 {
1387         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1388         int err;
1389
1390         err = seed_pool(priv, priv->bpid);
1391         if (err) {
1392                 /* Not much to do; the buffer pool, though not filled up,
1393                  * may still contain some buffers which would enable us
1394                  * to limp on.
1395                  */
1396                 netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
1397                            priv->dpbp_dev->obj_desc.id, priv->bpid);
1398         }
1399
1400         if (!priv->mac) {
1401                 /* We'll only start the txqs when the link is actually ready;
1402                  * make sure we don't race against the link up notification,
1403                  * which may come immediately after dpni_enable();
1404                  */
1405                 netif_tx_stop_all_queues(net_dev);
1406
1407                 /* Also, explicitly set carrier off, otherwise
1408                  * netif_carrier_ok() will return true and cause 'ip link show'
1409                  * to report the LOWER_UP flag, even though the link
1410                  * notification wasn't even received.
1411                  */
1412                 netif_carrier_off(net_dev);
1413         }
1414         enable_ch_napi(priv);
1415
1416         err = dpni_enable(priv->mc_io, 0, priv->mc_token);
1417         if (err < 0) {
1418                 netdev_err(net_dev, "dpni_enable() failed\n");
1419                 goto enable_err;
1420         }
1421
1422         if (!priv->mac) {
1423                 /* If the DPMAC object has already processed the link up
1424                  * interrupt, we have to learn the link state ourselves.
1425                  */
1426                 err = link_state_update(priv);
1427                 if (err < 0) {
1428                         netdev_err(net_dev, "Can't update link state\n");
1429                         goto link_state_err;
1430                 }
1431         } else {
1432                 phylink_start(priv->mac->phylink);
1433         }
1434
1435         return 0;
1436
1437 link_state_err:
1438 enable_err:
1439         disable_ch_napi(priv);
1440         drain_pool(priv);
1441         return err;
1442 }
1443
1444 /* Total number of in-flight frames on ingress queues */
1445 static u32 ingress_fq_count(struct dpaa2_eth_priv *priv)
1446 {
1447         struct dpaa2_eth_fq *fq;
1448         u32 fcnt = 0, bcnt = 0, total = 0;
1449         int i, err;
1450
1451         for (i = 0; i < priv->num_fqs; i++) {
1452                 fq = &priv->fq[i];
1453                 err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt);
1454                 if (err) {
1455                         netdev_warn(priv->net_dev, "query_fq_count failed");
1456                         break;
1457                 }
1458                 total += fcnt;
1459         }
1460
1461         return total;
1462 }
1463
1464 static void wait_for_ingress_fq_empty(struct dpaa2_eth_priv *priv)
1465 {
1466         int retries = 10;
1467         u32 pending;
1468
1469         do {
1470                 pending = ingress_fq_count(priv);
1471                 if (pending)
1472                         msleep(100);
1473         } while (pending && --retries);
1474 }
1475
1476 #define DPNI_TX_PENDING_VER_MAJOR       7
1477 #define DPNI_TX_PENDING_VER_MINOR       13
1478 static void wait_for_egress_fq_empty(struct dpaa2_eth_priv *priv)
1479 {
1480         union dpni_statistics stats;
1481         int retries = 10;
1482         int err;
1483
1484         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_TX_PENDING_VER_MAJOR,
1485                                    DPNI_TX_PENDING_VER_MINOR) < 0)
1486                 goto out;
1487
1488         do {
1489                 err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token, 6,
1490                                           &stats);
1491                 if (err)
1492                         goto out;
1493                 if (stats.page_6.tx_pending_frames == 0)
1494                         return;
1495         } while (--retries);
1496
1497 out:
1498         msleep(500);
1499 }
1500
1501 static int dpaa2_eth_stop(struct net_device *net_dev)
1502 {
1503         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1504         int dpni_enabled = 0;
1505         int retries = 10;
1506
1507         if (!priv->mac) {
1508                 netif_tx_stop_all_queues(net_dev);
1509                 netif_carrier_off(net_dev);
1510         } else {
1511                 phylink_stop(priv->mac->phylink);
1512         }
1513
1514         /* On dpni_disable(), the MC firmware will:
1515          * - stop MAC Rx and wait for all Rx frames to be enqueued to software
1516          * - cut off WRIOP dequeues from egress FQs and wait until transmission
1517          * of all in flight Tx frames is finished (and corresponding Tx conf
1518          * frames are enqueued back to software)
1519          *
1520          * Before calling dpni_disable(), we wait for all Tx frames to arrive
1521          * on WRIOP. After it finishes, wait until all remaining frames on Rx
1522          * and Tx conf queues are consumed on NAPI poll.
1523          */
1524         wait_for_egress_fq_empty(priv);
1525
1526         do {
1527                 dpni_disable(priv->mc_io, 0, priv->mc_token);
1528                 dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled);
1529                 if (dpni_enabled)
1530                         /* Allow the hardware some slack */
1531                         msleep(100);
1532         } while (dpni_enabled && --retries);
1533         if (!retries) {
1534                 netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
1535                 /* Must go on and disable NAPI nonetheless, so we don't crash at
1536                  * the next "ifconfig up"
1537                  */
1538         }
1539
1540         wait_for_ingress_fq_empty(priv);
1541         disable_ch_napi(priv);
1542
1543         /* Empty the buffer pool */
1544         drain_pool(priv);
1545
1546         return 0;
1547 }
1548
1549 static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
1550 {
1551         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1552         struct device *dev = net_dev->dev.parent;
1553         int err;
1554
1555         err = eth_mac_addr(net_dev, addr);
1556         if (err < 0) {
1557                 dev_err(dev, "eth_mac_addr() failed (%d)\n", err);
1558                 return err;
1559         }
1560
1561         err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
1562                                         net_dev->dev_addr);
1563         if (err) {
1564                 dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err);
1565                 return err;
1566         }
1567
1568         return 0;
1569 }
1570
1571 /** Fill in counters maintained by the GPP driver. These may be different from
1572  * the hardware counters obtained by ethtool.
1573  */
1574 static void dpaa2_eth_get_stats(struct net_device *net_dev,
1575                                 struct rtnl_link_stats64 *stats)
1576 {
1577         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1578         struct rtnl_link_stats64 *percpu_stats;
1579         u64 *cpustats;
1580         u64 *netstats = (u64 *)stats;
1581         int i, j;
1582         int num = sizeof(struct rtnl_link_stats64) / sizeof(u64);
1583
1584         for_each_possible_cpu(i) {
1585                 percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
1586                 cpustats = (u64 *)percpu_stats;
1587                 for (j = 0; j < num; j++)
1588                         netstats[j] += cpustats[j];
1589         }
1590 }
1591
1592 /* Copy mac unicast addresses from @net_dev to @priv.
1593  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1594  */
1595 static void add_uc_hw_addr(const struct net_device *net_dev,
1596                            struct dpaa2_eth_priv *priv)
1597 {
1598         struct netdev_hw_addr *ha;
1599         int err;
1600
1601         netdev_for_each_uc_addr(ha, net_dev) {
1602                 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1603                                         ha->addr);
1604                 if (err)
1605                         netdev_warn(priv->net_dev,
1606                                     "Could not add ucast MAC %pM to the filtering table (err %d)\n",
1607                                     ha->addr, err);
1608         }
1609 }
1610
1611 /* Copy mac multicast addresses from @net_dev to @priv
1612  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1613  */
1614 static void add_mc_hw_addr(const struct net_device *net_dev,
1615                            struct dpaa2_eth_priv *priv)
1616 {
1617         struct netdev_hw_addr *ha;
1618         int err;
1619
1620         netdev_for_each_mc_addr(ha, net_dev) {
1621                 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1622                                         ha->addr);
1623                 if (err)
1624                         netdev_warn(priv->net_dev,
1625                                     "Could not add mcast MAC %pM to the filtering table (err %d)\n",
1626                                     ha->addr, err);
1627         }
1628 }
1629
1630 static void dpaa2_eth_set_rx_mode(struct net_device *net_dev)
1631 {
1632         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1633         int uc_count = netdev_uc_count(net_dev);
1634         int mc_count = netdev_mc_count(net_dev);
1635         u8 max_mac = priv->dpni_attrs.mac_filter_entries;
1636         u32 options = priv->dpni_attrs.options;
1637         u16 mc_token = priv->mc_token;
1638         struct fsl_mc_io *mc_io = priv->mc_io;
1639         int err;
1640
1641         /* Basic sanity checks; these probably indicate a misconfiguration */
1642         if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0)
1643                 netdev_info(net_dev,
1644                             "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n",
1645                             max_mac);
1646
1647         /* Force promiscuous if the uc or mc counts exceed our capabilities. */
1648         if (uc_count > max_mac) {
1649                 netdev_info(net_dev,
1650                             "Unicast addr count reached %d, max allowed is %d; forcing promisc\n",
1651                             uc_count, max_mac);
1652                 goto force_promisc;
1653         }
1654         if (mc_count + uc_count > max_mac) {
1655                 netdev_info(net_dev,
1656                             "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n",
1657                             uc_count + mc_count, max_mac);
1658                 goto force_mc_promisc;
1659         }
1660
1661         /* Adjust promisc settings due to flag combinations */
1662         if (net_dev->flags & IFF_PROMISC)
1663                 goto force_promisc;
1664         if (net_dev->flags & IFF_ALLMULTI) {
1665                 /* First, rebuild unicast filtering table. This should be done
1666                  * in promisc mode, in order to avoid frame loss while we
1667                  * progressively add entries to the table.
1668                  * We don't know whether we had been in promisc already, and
1669                  * making an MC call to find out is expensive; so set uc promisc
1670                  * nonetheless.
1671                  */
1672                 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1673                 if (err)
1674                         netdev_warn(net_dev, "Can't set uc promisc\n");
1675
1676                 /* Actual uc table reconstruction. */
1677                 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0);
1678                 if (err)
1679                         netdev_warn(net_dev, "Can't clear uc filters\n");
1680                 add_uc_hw_addr(net_dev, priv);
1681
1682                 /* Finally, clear uc promisc and set mc promisc as requested. */
1683                 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1684                 if (err)
1685                         netdev_warn(net_dev, "Can't clear uc promisc\n");
1686                 goto force_mc_promisc;
1687         }
1688
1689         /* Neither unicast, nor multicast promisc will be on... eventually.
1690          * For now, rebuild mac filtering tables while forcing both of them on.
1691          */
1692         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1693         if (err)
1694                 netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err);
1695         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1696         if (err)
1697                 netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err);
1698
1699         /* Actual mac filtering tables reconstruction */
1700         err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1);
1701         if (err)
1702                 netdev_warn(net_dev, "Can't clear mac filters\n");
1703         add_mc_hw_addr(net_dev, priv);
1704         add_uc_hw_addr(net_dev, priv);
1705
1706         /* Now we can clear both ucast and mcast promisc, without risking
1707          * to drop legitimate frames anymore.
1708          */
1709         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1710         if (err)
1711                 netdev_warn(net_dev, "Can't clear ucast promisc\n");
1712         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0);
1713         if (err)
1714                 netdev_warn(net_dev, "Can't clear mcast promisc\n");
1715
1716         return;
1717
1718 force_promisc:
1719         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1720         if (err)
1721                 netdev_warn(net_dev, "Can't set ucast promisc\n");
1722 force_mc_promisc:
1723         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1724         if (err)
1725                 netdev_warn(net_dev, "Can't set mcast promisc\n");
1726 }
1727
1728 static int dpaa2_eth_set_features(struct net_device *net_dev,
1729                                   netdev_features_t features)
1730 {
1731         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1732         netdev_features_t changed = features ^ net_dev->features;
1733         bool enable;
1734         int err;
1735
1736         if (changed & NETIF_F_RXCSUM) {
1737                 enable = !!(features & NETIF_F_RXCSUM);
1738                 err = set_rx_csum(priv, enable);
1739                 if (err)
1740                         return err;
1741         }
1742
1743         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
1744                 enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
1745                 err = set_tx_csum(priv, enable);
1746                 if (err)
1747                         return err;
1748         }
1749
1750         return 0;
1751 }
1752
1753 static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1754 {
1755         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1756         struct hwtstamp_config config;
1757
1758         if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
1759                 return -EFAULT;
1760
1761         switch (config.tx_type) {
1762         case HWTSTAMP_TX_OFF:
1763                 priv->tx_tstamp = false;
1764                 break;
1765         case HWTSTAMP_TX_ON:
1766                 priv->tx_tstamp = true;
1767                 break;
1768         default:
1769                 return -ERANGE;
1770         }
1771
1772         if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
1773                 priv->rx_tstamp = false;
1774         } else {
1775                 priv->rx_tstamp = true;
1776                 /* TS is set for all frame types, not only those requested */
1777                 config.rx_filter = HWTSTAMP_FILTER_ALL;
1778         }
1779
1780         return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
1781                         -EFAULT : 0;
1782 }
1783
1784 static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1785 {
1786         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1787
1788         if (cmd == SIOCSHWTSTAMP)
1789                 return dpaa2_eth_ts_ioctl(dev, rq, cmd);
1790
1791         if (priv->mac)
1792                 return phylink_mii_ioctl(priv->mac->phylink, rq, cmd);
1793
1794         return -EOPNOTSUPP;
1795 }
1796
1797 static bool xdp_mtu_valid(struct dpaa2_eth_priv *priv, int mtu)
1798 {
1799         int mfl, linear_mfl;
1800
1801         mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
1802         linear_mfl = priv->rx_buf_size - DPAA2_ETH_RX_HWA_SIZE -
1803                      dpaa2_eth_rx_head_room(priv) - XDP_PACKET_HEADROOM;
1804
1805         if (mfl > linear_mfl) {
1806                 netdev_warn(priv->net_dev, "Maximum MTU for XDP is %d\n",
1807                             linear_mfl - VLAN_ETH_HLEN);
1808                 return false;
1809         }
1810
1811         return true;
1812 }
1813
1814 static int set_rx_mfl(struct dpaa2_eth_priv *priv, int mtu, bool has_xdp)
1815 {
1816         int mfl, err;
1817
1818         /* We enforce a maximum Rx frame length based on MTU only if we have
1819          * an XDP program attached (in order to avoid Rx S/G frames).
1820          * Otherwise, we accept all incoming frames as long as they are not
1821          * larger than maximum size supported in hardware
1822          */
1823         if (has_xdp)
1824                 mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
1825         else
1826                 mfl = DPAA2_ETH_MFL;
1827
1828         err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, mfl);
1829         if (err) {
1830                 netdev_err(priv->net_dev, "dpni_set_max_frame_length failed\n");
1831                 return err;
1832         }
1833
1834         return 0;
1835 }
1836
1837 static int dpaa2_eth_change_mtu(struct net_device *dev, int new_mtu)
1838 {
1839         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1840         int err;
1841
1842         if (!priv->xdp_prog)
1843                 goto out;
1844
1845         if (!xdp_mtu_valid(priv, new_mtu))
1846                 return -EINVAL;
1847
1848         err = set_rx_mfl(priv, new_mtu, true);
1849         if (err)
1850                 return err;
1851
1852 out:
1853         dev->mtu = new_mtu;
1854         return 0;
1855 }
1856
1857 static int update_rx_buffer_headroom(struct dpaa2_eth_priv *priv, bool has_xdp)
1858 {
1859         struct dpni_buffer_layout buf_layout = {0};
1860         int err;
1861
1862         err = dpni_get_buffer_layout(priv->mc_io, 0, priv->mc_token,
1863                                      DPNI_QUEUE_RX, &buf_layout);
1864         if (err) {
1865                 netdev_err(priv->net_dev, "dpni_get_buffer_layout failed\n");
1866                 return err;
1867         }
1868
1869         /* Reserve extra headroom for XDP header size changes */
1870         buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv) +
1871                                     (has_xdp ? XDP_PACKET_HEADROOM : 0);
1872         buf_layout.options = DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM;
1873         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
1874                                      DPNI_QUEUE_RX, &buf_layout);
1875         if (err) {
1876                 netdev_err(priv->net_dev, "dpni_set_buffer_layout failed\n");
1877                 return err;
1878         }
1879
1880         return 0;
1881 }
1882
1883 static int setup_xdp(struct net_device *dev, struct bpf_prog *prog)
1884 {
1885         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1886         struct dpaa2_eth_channel *ch;
1887         struct bpf_prog *old;
1888         bool up, need_update;
1889         int i, err;
1890
1891         if (prog && !xdp_mtu_valid(priv, dev->mtu))
1892                 return -EINVAL;
1893
1894         if (prog)
1895                 bpf_prog_add(prog, priv->num_channels);
1896
1897         up = netif_running(dev);
1898         need_update = (!!priv->xdp_prog != !!prog);
1899
1900         if (up)
1901                 dpaa2_eth_stop(dev);
1902
1903         /* While in xdp mode, enforce a maximum Rx frame size based on MTU.
1904          * Also, when switching between xdp/non-xdp modes we need to reconfigure
1905          * our Rx buffer layout. Buffer pool was drained on dpaa2_eth_stop,
1906          * so we are sure no old format buffers will be used from now on.
1907          */
1908         if (need_update) {
1909                 err = set_rx_mfl(priv, dev->mtu, !!prog);
1910                 if (err)
1911                         goto out_err;
1912                 err = update_rx_buffer_headroom(priv, !!prog);
1913                 if (err)
1914                         goto out_err;
1915         }
1916
1917         old = xchg(&priv->xdp_prog, prog);
1918         if (old)
1919                 bpf_prog_put(old);
1920
1921         for (i = 0; i < priv->num_channels; i++) {
1922                 ch = priv->channel[i];
1923                 old = xchg(&ch->xdp.prog, prog);
1924                 if (old)
1925                         bpf_prog_put(old);
1926         }
1927
1928         if (up) {
1929                 err = dpaa2_eth_open(dev);
1930                 if (err)
1931                         return err;
1932         }
1933
1934         return 0;
1935
1936 out_err:
1937         if (prog)
1938                 bpf_prog_sub(prog, priv->num_channels);
1939         if (up)
1940                 dpaa2_eth_open(dev);
1941
1942         return err;
1943 }
1944
1945 static int dpaa2_eth_xdp(struct net_device *dev, struct netdev_bpf *xdp)
1946 {
1947         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1948
1949         switch (xdp->command) {
1950         case XDP_SETUP_PROG:
1951                 return setup_xdp(dev, xdp->prog);
1952         case XDP_QUERY_PROG:
1953                 xdp->prog_id = priv->xdp_prog ? priv->xdp_prog->aux->id : 0;
1954                 break;
1955         default:
1956                 return -EINVAL;
1957         }
1958
1959         return 0;
1960 }
1961
1962 static int dpaa2_eth_xdp_create_fd(struct net_device *net_dev,
1963                                    struct xdp_frame *xdpf,
1964                                    struct dpaa2_fd *fd)
1965 {
1966         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1967         struct device *dev = net_dev->dev.parent;
1968         unsigned int needed_headroom;
1969         struct dpaa2_eth_swa *swa;
1970         void *buffer_start, *aligned_start;
1971         dma_addr_t addr;
1972
1973         /* We require a minimum headroom to be able to transmit the frame.
1974          * Otherwise return an error and let the original net_device handle it
1975          */
1976         needed_headroom = dpaa2_eth_needed_headroom(priv, NULL);
1977         if (xdpf->headroom < needed_headroom)
1978                 return -EINVAL;
1979
1980         /* Setup the FD fields */
1981         memset(fd, 0, sizeof(*fd));
1982
1983         /* Align FD address, if possible */
1984         buffer_start = xdpf->data - needed_headroom;
1985         aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
1986                                   DPAA2_ETH_TX_BUF_ALIGN);
1987         if (aligned_start >= xdpf->data - xdpf->headroom)
1988                 buffer_start = aligned_start;
1989
1990         swa = (struct dpaa2_eth_swa *)buffer_start;
1991         /* fill in necessary fields here */
1992         swa->type = DPAA2_ETH_SWA_XDP;
1993         swa->xdp.dma_size = xdpf->data + xdpf->len - buffer_start;
1994         swa->xdp.xdpf = xdpf;
1995
1996         addr = dma_map_single(dev, buffer_start,
1997                               swa->xdp.dma_size,
1998                               DMA_BIDIRECTIONAL);
1999         if (unlikely(dma_mapping_error(dev, addr)))
2000                 return -ENOMEM;
2001
2002         dpaa2_fd_set_addr(fd, addr);
2003         dpaa2_fd_set_offset(fd, xdpf->data - buffer_start);
2004         dpaa2_fd_set_len(fd, xdpf->len);
2005         dpaa2_fd_set_format(fd, dpaa2_fd_single);
2006         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
2007
2008         return 0;
2009 }
2010
2011 static int dpaa2_eth_xdp_xmit(struct net_device *net_dev, int n,
2012                               struct xdp_frame **frames, u32 flags)
2013 {
2014         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2015         struct dpaa2_eth_xdp_fds *xdp_redirect_fds;
2016         struct rtnl_link_stats64 *percpu_stats;
2017         struct dpaa2_eth_fq *fq;
2018         struct dpaa2_fd *fds;
2019         int enqueued, i, err;
2020
2021         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2022                 return -EINVAL;
2023
2024         if (!netif_running(net_dev))
2025                 return -ENETDOWN;
2026
2027         fq = &priv->fq[smp_processor_id()];
2028         xdp_redirect_fds = &fq->xdp_redirect_fds;
2029         fds = xdp_redirect_fds->fds;
2030
2031         percpu_stats = this_cpu_ptr(priv->percpu_stats);
2032
2033         /* create a FD for each xdp_frame in the list received */
2034         for (i = 0; i < n; i++) {
2035                 err = dpaa2_eth_xdp_create_fd(net_dev, frames[i], &fds[i]);
2036                 if (err)
2037                         break;
2038         }
2039         xdp_redirect_fds->num = i;
2040
2041         /* enqueue all the frame descriptors */
2042         enqueued = dpaa2_eth_xdp_flush(priv, fq, xdp_redirect_fds);
2043
2044         /* update statistics */
2045         percpu_stats->tx_packets += enqueued;
2046         for (i = 0; i < enqueued; i++)
2047                 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
2048         for (i = enqueued; i < n; i++)
2049                 xdp_return_frame_rx_napi(frames[i]);
2050
2051         return enqueued;
2052 }
2053
2054 static int update_xps(struct dpaa2_eth_priv *priv)
2055 {
2056         struct net_device *net_dev = priv->net_dev;
2057         struct cpumask xps_mask;
2058         struct dpaa2_eth_fq *fq;
2059         int i, num_queues, netdev_queues;
2060         int err = 0;
2061
2062         num_queues = dpaa2_eth_queue_count(priv);
2063         netdev_queues = (net_dev->num_tc ? : 1) * num_queues;
2064
2065         /* The first <num_queues> entries in priv->fq array are Tx/Tx conf
2066          * queues, so only process those
2067          */
2068         for (i = 0; i < netdev_queues; i++) {
2069                 fq = &priv->fq[i % num_queues];
2070
2071                 cpumask_clear(&xps_mask);
2072                 cpumask_set_cpu(fq->target_cpu, &xps_mask);
2073
2074                 err = netif_set_xps_queue(net_dev, &xps_mask, i);
2075                 if (err) {
2076                         netdev_warn_once(net_dev, "Error setting XPS queue\n");
2077                         break;
2078                 }
2079         }
2080
2081         return err;
2082 }
2083
2084 static int dpaa2_eth_setup_tc(struct net_device *net_dev,
2085                               enum tc_setup_type type, void *type_data)
2086 {
2087         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2088         struct tc_mqprio_qopt *mqprio = type_data;
2089         u8 num_tc, num_queues;
2090         int i;
2091
2092         if (type != TC_SETUP_QDISC_MQPRIO)
2093                 return -EOPNOTSUPP;
2094
2095         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2096         num_queues = dpaa2_eth_queue_count(priv);
2097         num_tc = mqprio->num_tc;
2098
2099         if (num_tc == net_dev->num_tc)
2100                 return 0;
2101
2102         if (num_tc  > dpaa2_eth_tc_count(priv)) {
2103                 netdev_err(net_dev, "Max %d traffic classes supported\n",
2104                            dpaa2_eth_tc_count(priv));
2105                 return -EOPNOTSUPP;
2106         }
2107
2108         if (!num_tc) {
2109                 netdev_reset_tc(net_dev);
2110                 netif_set_real_num_tx_queues(net_dev, num_queues);
2111                 goto out;
2112         }
2113
2114         netdev_set_num_tc(net_dev, num_tc);
2115         netif_set_real_num_tx_queues(net_dev, num_tc * num_queues);
2116
2117         for (i = 0; i < num_tc; i++)
2118                 netdev_set_tc_queue(net_dev, i, num_queues, i * num_queues);
2119
2120 out:
2121         update_xps(priv);
2122
2123         return 0;
2124 }
2125
2126 static const struct net_device_ops dpaa2_eth_ops = {
2127         .ndo_open = dpaa2_eth_open,
2128         .ndo_start_xmit = dpaa2_eth_tx,
2129         .ndo_stop = dpaa2_eth_stop,
2130         .ndo_set_mac_address = dpaa2_eth_set_addr,
2131         .ndo_get_stats64 = dpaa2_eth_get_stats,
2132         .ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
2133         .ndo_set_features = dpaa2_eth_set_features,
2134         .ndo_do_ioctl = dpaa2_eth_ioctl,
2135         .ndo_change_mtu = dpaa2_eth_change_mtu,
2136         .ndo_bpf = dpaa2_eth_xdp,
2137         .ndo_xdp_xmit = dpaa2_eth_xdp_xmit,
2138         .ndo_setup_tc = dpaa2_eth_setup_tc,
2139 };
2140
2141 static void cdan_cb(struct dpaa2_io_notification_ctx *ctx)
2142 {
2143         struct dpaa2_eth_channel *ch;
2144
2145         ch = container_of(ctx, struct dpaa2_eth_channel, nctx);
2146
2147         /* Update NAPI statistics */
2148         ch->stats.cdan++;
2149
2150         napi_schedule_irqoff(&ch->napi);
2151 }
2152
2153 /* Allocate and configure a DPCON object */
2154 static struct fsl_mc_device *setup_dpcon(struct dpaa2_eth_priv *priv)
2155 {
2156         struct fsl_mc_device *dpcon;
2157         struct device *dev = priv->net_dev->dev.parent;
2158         int err;
2159
2160         err = fsl_mc_object_allocate(to_fsl_mc_device(dev),
2161                                      FSL_MC_POOL_DPCON, &dpcon);
2162         if (err) {
2163                 if (err == -ENXIO)
2164                         err = -EPROBE_DEFER;
2165                 else
2166                         dev_info(dev, "Not enough DPCONs, will go on as-is\n");
2167                 return ERR_PTR(err);
2168         }
2169
2170         err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
2171         if (err) {
2172                 dev_err(dev, "dpcon_open() failed\n");
2173                 goto free;
2174         }
2175
2176         err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
2177         if (err) {
2178                 dev_err(dev, "dpcon_reset() failed\n");
2179                 goto close;
2180         }
2181
2182         err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
2183         if (err) {
2184                 dev_err(dev, "dpcon_enable() failed\n");
2185                 goto close;
2186         }
2187
2188         return dpcon;
2189
2190 close:
2191         dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
2192 free:
2193         fsl_mc_object_free(dpcon);
2194
2195         return NULL;
2196 }
2197
2198 static void free_dpcon(struct dpaa2_eth_priv *priv,
2199                        struct fsl_mc_device *dpcon)
2200 {
2201         dpcon_disable(priv->mc_io, 0, dpcon->mc_handle);
2202         dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
2203         fsl_mc_object_free(dpcon);
2204 }
2205
2206 static struct dpaa2_eth_channel *
2207 alloc_channel(struct dpaa2_eth_priv *priv)
2208 {
2209         struct dpaa2_eth_channel *channel;
2210         struct dpcon_attr attr;
2211         struct device *dev = priv->net_dev->dev.parent;
2212         int err;
2213
2214         channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2215         if (!channel)
2216                 return NULL;
2217
2218         channel->dpcon = setup_dpcon(priv);
2219         if (IS_ERR_OR_NULL(channel->dpcon)) {
2220                 err = PTR_ERR_OR_ZERO(channel->dpcon);
2221                 goto err_setup;
2222         }
2223
2224         err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle,
2225                                    &attr);
2226         if (err) {
2227                 dev_err(dev, "dpcon_get_attributes() failed\n");
2228                 goto err_get_attr;
2229         }
2230
2231         channel->dpcon_id = attr.id;
2232         channel->ch_id = attr.qbman_ch_id;
2233         channel->priv = priv;
2234
2235         return channel;
2236
2237 err_get_attr:
2238         free_dpcon(priv, channel->dpcon);
2239 err_setup:
2240         kfree(channel);
2241         return ERR_PTR(err);
2242 }
2243
2244 static void free_channel(struct dpaa2_eth_priv *priv,
2245                          struct dpaa2_eth_channel *channel)
2246 {
2247         free_dpcon(priv, channel->dpcon);
2248         kfree(channel);
2249 }
2250
2251 /* DPIO setup: allocate and configure QBMan channels, setup core affinity
2252  * and register data availability notifications
2253  */
2254 static int setup_dpio(struct dpaa2_eth_priv *priv)
2255 {
2256         struct dpaa2_io_notification_ctx *nctx;
2257         struct dpaa2_eth_channel *channel;
2258         struct dpcon_notification_cfg dpcon_notif_cfg;
2259         struct device *dev = priv->net_dev->dev.parent;
2260         int i, err;
2261
2262         /* We want the ability to spread ingress traffic (RX, TX conf) to as
2263          * many cores as possible, so we need one channel for each core
2264          * (unless there's fewer queues than cores, in which case the extra
2265          * channels would be wasted).
2266          * Allocate one channel per core and register it to the core's
2267          * affine DPIO. If not enough channels are available for all cores
2268          * or if some cores don't have an affine DPIO, there will be no
2269          * ingress frame processing on those cores.
2270          */
2271         cpumask_clear(&priv->dpio_cpumask);
2272         for_each_online_cpu(i) {
2273                 /* Try to allocate a channel */
2274                 channel = alloc_channel(priv);
2275                 if (IS_ERR_OR_NULL(channel)) {
2276                         err = PTR_ERR_OR_ZERO(channel);
2277                         if (err != -EPROBE_DEFER)
2278                                 dev_info(dev,
2279                                          "No affine channel for cpu %d and above\n", i);
2280                         goto err_alloc_ch;
2281                 }
2282
2283                 priv->channel[priv->num_channels] = channel;
2284
2285                 nctx = &channel->nctx;
2286                 nctx->is_cdan = 1;
2287                 nctx->cb = cdan_cb;
2288                 nctx->id = channel->ch_id;
2289                 nctx->desired_cpu = i;
2290
2291                 /* Register the new context */
2292                 channel->dpio = dpaa2_io_service_select(i);
2293                 err = dpaa2_io_service_register(channel->dpio, nctx, dev);
2294                 if (err) {
2295                         dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
2296                         /* If no affine DPIO for this core, there's probably
2297                          * none available for next cores either. Signal we want
2298                          * to retry later, in case the DPIO devices weren't
2299                          * probed yet.
2300                          */
2301                         err = -EPROBE_DEFER;
2302                         goto err_service_reg;
2303                 }
2304
2305                 /* Register DPCON notification with MC */
2306                 dpcon_notif_cfg.dpio_id = nctx->dpio_id;
2307                 dpcon_notif_cfg.priority = 0;
2308                 dpcon_notif_cfg.user_ctx = nctx->qman64;
2309                 err = dpcon_set_notification(priv->mc_io, 0,
2310                                              channel->dpcon->mc_handle,
2311                                              &dpcon_notif_cfg);
2312                 if (err) {
2313                         dev_err(dev, "dpcon_set_notification failed()\n");
2314                         goto err_set_cdan;
2315                 }
2316
2317                 /* If we managed to allocate a channel and also found an affine
2318                  * DPIO for this core, add it to the final mask
2319                  */
2320                 cpumask_set_cpu(i, &priv->dpio_cpumask);
2321                 priv->num_channels++;
2322
2323                 /* Stop if we already have enough channels to accommodate all
2324                  * RX and TX conf queues
2325                  */
2326                 if (priv->num_channels == priv->dpni_attrs.num_queues)
2327                         break;
2328         }
2329
2330         return 0;
2331
2332 err_set_cdan:
2333         dpaa2_io_service_deregister(channel->dpio, nctx, dev);
2334 err_service_reg:
2335         free_channel(priv, channel);
2336 err_alloc_ch:
2337         if (err == -EPROBE_DEFER) {
2338                 for (i = 0; i < priv->num_channels; i++) {
2339                         channel = priv->channel[i];
2340                         nctx = &channel->nctx;
2341                         dpaa2_io_service_deregister(channel->dpio, nctx, dev);
2342                         free_channel(priv, channel);
2343                 }
2344                 priv->num_channels = 0;
2345                 return err;
2346         }
2347
2348         if (cpumask_empty(&priv->dpio_cpumask)) {
2349                 dev_err(dev, "No cpu with an affine DPIO/DPCON\n");
2350                 return -ENODEV;
2351         }
2352
2353         dev_info(dev, "Cores %*pbl available for processing ingress traffic\n",
2354                  cpumask_pr_args(&priv->dpio_cpumask));
2355
2356         return 0;
2357 }
2358
2359 static void free_dpio(struct dpaa2_eth_priv *priv)
2360 {
2361         struct device *dev = priv->net_dev->dev.parent;
2362         struct dpaa2_eth_channel *ch;
2363         int i;
2364
2365         /* deregister CDAN notifications and free channels */
2366         for (i = 0; i < priv->num_channels; i++) {
2367                 ch = priv->channel[i];
2368                 dpaa2_io_service_deregister(ch->dpio, &ch->nctx, dev);
2369                 free_channel(priv, ch);
2370         }
2371 }
2372
2373 static struct dpaa2_eth_channel *get_affine_channel(struct dpaa2_eth_priv *priv,
2374                                                     int cpu)
2375 {
2376         struct device *dev = priv->net_dev->dev.parent;
2377         int i;
2378
2379         for (i = 0; i < priv->num_channels; i++)
2380                 if (priv->channel[i]->nctx.desired_cpu == cpu)
2381                         return priv->channel[i];
2382
2383         /* We should never get here. Issue a warning and return
2384          * the first channel, because it's still better than nothing
2385          */
2386         dev_warn(dev, "No affine channel found for cpu %d\n", cpu);
2387
2388         return priv->channel[0];
2389 }
2390
2391 static void set_fq_affinity(struct dpaa2_eth_priv *priv)
2392 {
2393         struct device *dev = priv->net_dev->dev.parent;
2394         struct dpaa2_eth_fq *fq;
2395         int rx_cpu, txc_cpu;
2396         int i;
2397
2398         /* For each FQ, pick one channel/CPU to deliver frames to.
2399          * This may well change at runtime, either through irqbalance or
2400          * through direct user intervention.
2401          */
2402         rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask);
2403
2404         for (i = 0; i < priv->num_fqs; i++) {
2405                 fq = &priv->fq[i];
2406                 switch (fq->type) {
2407                 case DPAA2_RX_FQ:
2408                         fq->target_cpu = rx_cpu;
2409                         rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
2410                         if (rx_cpu >= nr_cpu_ids)
2411                                 rx_cpu = cpumask_first(&priv->dpio_cpumask);
2412                         break;
2413                 case DPAA2_TX_CONF_FQ:
2414                         fq->target_cpu = txc_cpu;
2415                         txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
2416                         if (txc_cpu >= nr_cpu_ids)
2417                                 txc_cpu = cpumask_first(&priv->dpio_cpumask);
2418                         break;
2419                 default:
2420                         dev_err(dev, "Unknown FQ type: %d\n", fq->type);
2421                 }
2422                 fq->channel = get_affine_channel(priv, fq->target_cpu);
2423         }
2424
2425         update_xps(priv);
2426 }
2427
2428 static void setup_fqs(struct dpaa2_eth_priv *priv)
2429 {
2430         int i, j;
2431
2432         /* We have one TxConf FQ per Tx flow.
2433          * The number of Tx and Rx queues is the same.
2434          * Tx queues come first in the fq array.
2435          */
2436         for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
2437                 priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ;
2438                 priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf;
2439                 priv->fq[priv->num_fqs++].flowid = (u16)i;
2440         }
2441
2442         for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
2443                 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
2444                         priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
2445                         priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
2446                         priv->fq[priv->num_fqs].tc = (u8)j;
2447                         priv->fq[priv->num_fqs++].flowid = (u16)i;
2448                 }
2449         }
2450
2451         /* For each FQ, decide on which core to process incoming frames */
2452         set_fq_affinity(priv);
2453 }
2454
2455 /* Allocate and configure one buffer pool for each interface */
2456 static int setup_dpbp(struct dpaa2_eth_priv *priv)
2457 {
2458         int err;
2459         struct fsl_mc_device *dpbp_dev;
2460         struct device *dev = priv->net_dev->dev.parent;
2461         struct dpbp_attr dpbp_attrs;
2462
2463         err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP,
2464                                      &dpbp_dev);
2465         if (err) {
2466                 if (err == -ENXIO)
2467                         err = -EPROBE_DEFER;
2468                 else
2469                         dev_err(dev, "DPBP device allocation failed\n");
2470                 return err;
2471         }
2472
2473         priv->dpbp_dev = dpbp_dev;
2474
2475         err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id,
2476                         &dpbp_dev->mc_handle);
2477         if (err) {
2478                 dev_err(dev, "dpbp_open() failed\n");
2479                 goto err_open;
2480         }
2481
2482         err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle);
2483         if (err) {
2484                 dev_err(dev, "dpbp_reset() failed\n");
2485                 goto err_reset;
2486         }
2487
2488         err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle);
2489         if (err) {
2490                 dev_err(dev, "dpbp_enable() failed\n");
2491                 goto err_enable;
2492         }
2493
2494         err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle,
2495                                   &dpbp_attrs);
2496         if (err) {
2497                 dev_err(dev, "dpbp_get_attributes() failed\n");
2498                 goto err_get_attr;
2499         }
2500         priv->bpid = dpbp_attrs.bpid;
2501
2502         return 0;
2503
2504 err_get_attr:
2505         dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle);
2506 err_enable:
2507 err_reset:
2508         dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle);
2509 err_open:
2510         fsl_mc_object_free(dpbp_dev);
2511
2512         return err;
2513 }
2514
2515 static void free_dpbp(struct dpaa2_eth_priv *priv)
2516 {
2517         drain_pool(priv);
2518         dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
2519         dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
2520         fsl_mc_object_free(priv->dpbp_dev);
2521 }
2522
2523 static int set_buffer_layout(struct dpaa2_eth_priv *priv)
2524 {
2525         struct device *dev = priv->net_dev->dev.parent;
2526         struct dpni_buffer_layout buf_layout = {0};
2527         u16 rx_buf_align;
2528         int err;
2529
2530         /* We need to check for WRIOP version 1.0.0, but depending on the MC
2531          * version, this number is not always provided correctly on rev1.
2532          * We need to check for both alternatives in this situation.
2533          */
2534         if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) ||
2535             priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0))
2536                 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1;
2537         else
2538                 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN;
2539
2540         /* We need to ensure that the buffer size seen by WRIOP is a multiple
2541          * of 64 or 256 bytes depending on the WRIOP version.
2542          */
2543         priv->rx_buf_size = ALIGN_DOWN(DPAA2_ETH_RX_BUF_SIZE, rx_buf_align);
2544
2545         /* tx buffer */
2546         buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
2547         buf_layout.pass_timestamp = true;
2548         buf_layout.options = DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
2549                              DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2550         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2551                                      DPNI_QUEUE_TX, &buf_layout);
2552         if (err) {
2553                 dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
2554                 return err;
2555         }
2556
2557         /* tx-confirm buffer */
2558         buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2559         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2560                                      DPNI_QUEUE_TX_CONFIRM, &buf_layout);
2561         if (err) {
2562                 dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
2563                 return err;
2564         }
2565
2566         /* Now that we've set our tx buffer layout, retrieve the minimum
2567          * required tx data offset.
2568          */
2569         err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
2570                                       &priv->tx_data_offset);
2571         if (err) {
2572                 dev_err(dev, "dpni_get_tx_data_offset() failed\n");
2573                 return err;
2574         }
2575
2576         if ((priv->tx_data_offset % 64) != 0)
2577                 dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
2578                          priv->tx_data_offset);
2579
2580         /* rx buffer */
2581         buf_layout.pass_frame_status = true;
2582         buf_layout.pass_parser_result = true;
2583         buf_layout.data_align = rx_buf_align;
2584         buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv);
2585         buf_layout.private_data_size = 0;
2586         buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
2587                              DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2588                              DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
2589                              DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
2590                              DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2591         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2592                                      DPNI_QUEUE_RX, &buf_layout);
2593         if (err) {
2594                 dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
2595                 return err;
2596         }
2597
2598         return 0;
2599 }
2600
2601 #define DPNI_ENQUEUE_FQID_VER_MAJOR     7
2602 #define DPNI_ENQUEUE_FQID_VER_MINOR     9
2603
2604 static inline int dpaa2_eth_enqueue_qd(struct dpaa2_eth_priv *priv,
2605                                        struct dpaa2_eth_fq *fq,
2606                                        struct dpaa2_fd *fd, u8 prio,
2607                                        u32 num_frames __always_unused,
2608                                        int *frames_enqueued)
2609 {
2610         int err;
2611
2612         err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
2613                                           priv->tx_qdid, prio,
2614                                           fq->tx_qdbin, fd);
2615         if (!err && frames_enqueued)
2616                 *frames_enqueued = 1;
2617         return err;
2618 }
2619
2620 static inline int dpaa2_eth_enqueue_fq_multiple(struct dpaa2_eth_priv *priv,
2621                                                 struct dpaa2_eth_fq *fq,
2622                                                 struct dpaa2_fd *fd,
2623                                                 u8 prio, u32 num_frames,
2624                                                 int *frames_enqueued)
2625 {
2626         int err;
2627
2628         err = dpaa2_io_service_enqueue_multiple_fq(fq->channel->dpio,
2629                                                    fq->tx_fqid[prio],
2630                                                    fd, num_frames);
2631
2632         if (err == 0)
2633                 return -EBUSY;
2634
2635         if (frames_enqueued)
2636                 *frames_enqueued = err;
2637         return 0;
2638 }
2639
2640 static void set_enqueue_mode(struct dpaa2_eth_priv *priv)
2641 {
2642         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
2643                                    DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
2644                 priv->enqueue = dpaa2_eth_enqueue_qd;
2645         else
2646                 priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
2647 }
2648
2649 static int set_pause(struct dpaa2_eth_priv *priv)
2650 {
2651         struct device *dev = priv->net_dev->dev.parent;
2652         struct dpni_link_cfg link_cfg = {0};
2653         int err;
2654
2655         /* Get the default link options so we don't override other flags */
2656         err = dpni_get_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
2657         if (err) {
2658                 dev_err(dev, "dpni_get_link_cfg() failed\n");
2659                 return err;
2660         }
2661
2662         /* By default, enable both Rx and Tx pause frames */
2663         link_cfg.options |= DPNI_LINK_OPT_PAUSE;
2664         link_cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2665         err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
2666         if (err) {
2667                 dev_err(dev, "dpni_set_link_cfg() failed\n");
2668                 return err;
2669         }
2670
2671         priv->link_state.options = link_cfg.options;
2672
2673         return 0;
2674 }
2675
2676 static void update_tx_fqids(struct dpaa2_eth_priv *priv)
2677 {
2678         struct dpni_queue_id qid = {0};
2679         struct dpaa2_eth_fq *fq;
2680         struct dpni_queue queue;
2681         int i, j, err;
2682
2683         /* We only use Tx FQIDs for FQID-based enqueue, so check
2684          * if DPNI version supports it before updating FQIDs
2685          */
2686         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
2687                                    DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
2688                 return;
2689
2690         for (i = 0; i < priv->num_fqs; i++) {
2691                 fq = &priv->fq[i];
2692                 if (fq->type != DPAA2_TX_CONF_FQ)
2693                         continue;
2694                 for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
2695                         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
2696                                              DPNI_QUEUE_TX, j, fq->flowid,
2697                                              &queue, &qid);
2698                         if (err)
2699                                 goto out_err;
2700
2701                         fq->tx_fqid[j] = qid.fqid;
2702                         if (fq->tx_fqid[j] == 0)
2703                                 goto out_err;
2704                 }
2705         }
2706
2707         priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
2708
2709         return;
2710
2711 out_err:
2712         netdev_info(priv->net_dev,
2713                     "Error reading Tx FQID, fallback to QDID-based enqueue\n");
2714         priv->enqueue = dpaa2_eth_enqueue_qd;
2715 }
2716
2717 /* Configure ingress classification based on VLAN PCP */
2718 static int set_vlan_qos(struct dpaa2_eth_priv *priv)
2719 {
2720         struct device *dev = priv->net_dev->dev.parent;
2721         struct dpkg_profile_cfg kg_cfg = {0};
2722         struct dpni_qos_tbl_cfg qos_cfg = {0};
2723         struct dpni_rule_cfg key_params;
2724         void *dma_mem, *key, *mask;
2725         u8 key_size = 2;        /* VLAN TCI field */
2726         int i, pcp, err;
2727
2728         /* VLAN-based classification only makes sense if we have multiple
2729          * traffic classes.
2730          * Also, we need to extract just the 3-bit PCP field from the VLAN
2731          * header and we can only do that by using a mask
2732          */
2733         if (dpaa2_eth_tc_count(priv) == 1 || !dpaa2_eth_fs_mask_enabled(priv)) {
2734                 dev_dbg(dev, "VLAN-based QoS classification not supported\n");
2735                 return -EOPNOTSUPP;
2736         }
2737
2738         dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
2739         if (!dma_mem)
2740                 return -ENOMEM;
2741
2742         kg_cfg.num_extracts = 1;
2743         kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_HDR;
2744         kg_cfg.extracts[0].extract.from_hdr.prot = NET_PROT_VLAN;
2745         kg_cfg.extracts[0].extract.from_hdr.type = DPKG_FULL_FIELD;
2746         kg_cfg.extracts[0].extract.from_hdr.field = NH_FLD_VLAN_TCI;
2747
2748         err = dpni_prepare_key_cfg(&kg_cfg, dma_mem);
2749         if (err) {
2750                 dev_err(dev, "dpni_prepare_key_cfg failed\n");
2751                 goto out_free_tbl;
2752         }
2753
2754         /* set QoS table */
2755         qos_cfg.default_tc = 0;
2756         qos_cfg.discard_on_miss = 0;
2757         qos_cfg.key_cfg_iova = dma_map_single(dev, dma_mem,
2758                                               DPAA2_CLASSIFIER_DMA_SIZE,
2759                                               DMA_TO_DEVICE);
2760         if (dma_mapping_error(dev, qos_cfg.key_cfg_iova)) {
2761                 dev_err(dev, "QoS table DMA mapping failed\n");
2762                 err = -ENOMEM;
2763                 goto out_free_tbl;
2764         }
2765
2766         err = dpni_set_qos_table(priv->mc_io, 0, priv->mc_token, &qos_cfg);
2767         if (err) {
2768                 dev_err(dev, "dpni_set_qos_table failed\n");
2769                 goto out_unmap_tbl;
2770         }
2771
2772         /* Add QoS table entries */
2773         key = kzalloc(key_size * 2, GFP_KERNEL);
2774         if (!key) {
2775                 err = -ENOMEM;
2776                 goto out_unmap_tbl;
2777         }
2778         mask = key + key_size;
2779         *(__be16 *)mask = cpu_to_be16(VLAN_PRIO_MASK);
2780
2781         key_params.key_iova = dma_map_single(dev, key, key_size * 2,
2782                                              DMA_TO_DEVICE);
2783         if (dma_mapping_error(dev, key_params.key_iova)) {
2784                 dev_err(dev, "Qos table entry DMA mapping failed\n");
2785                 err = -ENOMEM;
2786                 goto out_free_key;
2787         }
2788
2789         key_params.mask_iova = key_params.key_iova + key_size;
2790         key_params.key_size = key_size;
2791
2792         /* We add rules for PCP-based distribution starting with highest
2793          * priority (VLAN PCP = 7). If this DPNI doesn't have enough traffic
2794          * classes to accommodate all priority levels, the lowest ones end up
2795          * on TC 0 which was configured as default
2796          */
2797         for (i = dpaa2_eth_tc_count(priv) - 1, pcp = 7; i >= 0; i--, pcp--) {
2798                 *(__be16 *)key = cpu_to_be16(pcp << VLAN_PRIO_SHIFT);
2799                 dma_sync_single_for_device(dev, key_params.key_iova,
2800                                            key_size * 2, DMA_TO_DEVICE);
2801
2802                 err = dpni_add_qos_entry(priv->mc_io, 0, priv->mc_token,
2803                                          &key_params, i, i);
2804                 if (err) {
2805                         dev_err(dev, "dpni_add_qos_entry failed\n");
2806                         dpni_clear_qos_table(priv->mc_io, 0, priv->mc_token);
2807                         goto out_unmap_key;
2808                 }
2809         }
2810
2811         priv->vlan_cls_enabled = true;
2812
2813         /* Table and key memory is not persistent, clean everything up after
2814          * configuration is finished
2815          */
2816 out_unmap_key:
2817         dma_unmap_single(dev, key_params.key_iova, key_size * 2, DMA_TO_DEVICE);
2818 out_free_key:
2819         kfree(key);
2820 out_unmap_tbl:
2821         dma_unmap_single(dev, qos_cfg.key_cfg_iova, DPAA2_CLASSIFIER_DMA_SIZE,
2822                          DMA_TO_DEVICE);
2823 out_free_tbl:
2824         kfree(dma_mem);
2825
2826         return err;
2827 }
2828
2829 /* Configure the DPNI object this interface is associated with */
2830 static int setup_dpni(struct fsl_mc_device *ls_dev)
2831 {
2832         struct device *dev = &ls_dev->dev;
2833         struct dpaa2_eth_priv *priv;
2834         struct net_device *net_dev;
2835         int err;
2836
2837         net_dev = dev_get_drvdata(dev);
2838         priv = netdev_priv(net_dev);
2839
2840         /* get a handle for the DPNI object */
2841         err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
2842         if (err) {
2843                 dev_err(dev, "dpni_open() failed\n");
2844                 return err;
2845         }
2846
2847         /* Check if we can work with this DPNI object */
2848         err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major,
2849                                    &priv->dpni_ver_minor);
2850         if (err) {
2851                 dev_err(dev, "dpni_get_api_version() failed\n");
2852                 goto close;
2853         }
2854         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) {
2855                 dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n",
2856                         priv->dpni_ver_major, priv->dpni_ver_minor,
2857                         DPNI_VER_MAJOR, DPNI_VER_MINOR);
2858                 err = -ENOTSUPP;
2859                 goto close;
2860         }
2861
2862         ls_dev->mc_io = priv->mc_io;
2863         ls_dev->mc_handle = priv->mc_token;
2864
2865         err = dpni_reset(priv->mc_io, 0, priv->mc_token);
2866         if (err) {
2867                 dev_err(dev, "dpni_reset() failed\n");
2868                 goto close;
2869         }
2870
2871         err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
2872                                   &priv->dpni_attrs);
2873         if (err) {
2874                 dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
2875                 goto close;
2876         }
2877
2878         err = set_buffer_layout(priv);
2879         if (err)
2880                 goto close;
2881
2882         set_enqueue_mode(priv);
2883
2884         /* Enable pause frame support */
2885         if (dpaa2_eth_has_pause_support(priv)) {
2886                 err = set_pause(priv);
2887                 if (err)
2888                         goto close;
2889         }
2890
2891         err = set_vlan_qos(priv);
2892         if (err && err != -EOPNOTSUPP)
2893                 goto close;
2894
2895         priv->cls_rules = devm_kzalloc(dev, sizeof(struct dpaa2_eth_cls_rule) *
2896                                        dpaa2_eth_fs_count(priv), GFP_KERNEL);
2897         if (!priv->cls_rules) {
2898                 err = -ENOMEM;
2899                 goto close;
2900         }
2901
2902         return 0;
2903
2904 close:
2905         dpni_close(priv->mc_io, 0, priv->mc_token);
2906
2907         return err;
2908 }
2909
2910 static void free_dpni(struct dpaa2_eth_priv *priv)
2911 {
2912         int err;
2913
2914         err = dpni_reset(priv->mc_io, 0, priv->mc_token);
2915         if (err)
2916                 netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n",
2917                             err);
2918
2919         dpni_close(priv->mc_io, 0, priv->mc_token);
2920 }
2921
2922 static int setup_rx_flow(struct dpaa2_eth_priv *priv,
2923                          struct dpaa2_eth_fq *fq)
2924 {
2925         struct device *dev = priv->net_dev->dev.parent;
2926         struct dpni_queue queue;
2927         struct dpni_queue_id qid;
2928         int err;
2929
2930         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
2931                              DPNI_QUEUE_RX, fq->tc, fq->flowid, &queue, &qid);
2932         if (err) {
2933                 dev_err(dev, "dpni_get_queue(RX) failed\n");
2934                 return err;
2935         }
2936
2937         fq->fqid = qid.fqid;
2938
2939         queue.destination.id = fq->channel->dpcon_id;
2940         queue.destination.type = DPNI_DEST_DPCON;
2941         queue.destination.priority = 1;
2942         queue.user_context = (u64)(uintptr_t)fq;
2943         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
2944                              DPNI_QUEUE_RX, fq->tc, fq->flowid,
2945                              DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
2946                              &queue);
2947         if (err) {
2948                 dev_err(dev, "dpni_set_queue(RX) failed\n");
2949                 return err;
2950         }
2951
2952         /* xdp_rxq setup */
2953         /* only once for each channel */
2954         if (fq->tc > 0)
2955                 return 0;
2956
2957         err = xdp_rxq_info_reg(&fq->channel->xdp_rxq, priv->net_dev,
2958                                fq->flowid);
2959         if (err) {
2960                 dev_err(dev, "xdp_rxq_info_reg failed\n");
2961                 return err;
2962         }
2963
2964         err = xdp_rxq_info_reg_mem_model(&fq->channel->xdp_rxq,
2965                                          MEM_TYPE_PAGE_ORDER0, NULL);
2966         if (err) {
2967                 dev_err(dev, "xdp_rxq_info_reg_mem_model failed\n");
2968                 return err;
2969         }
2970
2971         return 0;
2972 }
2973
2974 static int setup_tx_flow(struct dpaa2_eth_priv *priv,
2975                          struct dpaa2_eth_fq *fq)
2976 {
2977         struct device *dev = priv->net_dev->dev.parent;
2978         struct dpni_queue queue;
2979         struct dpni_queue_id qid;
2980         int i, err;
2981
2982         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
2983                 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
2984                                      DPNI_QUEUE_TX, i, fq->flowid,
2985                                      &queue, &qid);
2986                 if (err) {
2987                         dev_err(dev, "dpni_get_queue(TX) failed\n");
2988                         return err;
2989                 }
2990                 fq->tx_fqid[i] = qid.fqid;
2991         }
2992
2993         /* All Tx queues belonging to the same flowid have the same qdbin */
2994         fq->tx_qdbin = qid.qdbin;
2995
2996         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
2997                              DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
2998                              &queue, &qid);
2999         if (err) {
3000                 dev_err(dev, "dpni_get_queue(TX_CONF) failed\n");
3001                 return err;
3002         }
3003
3004         fq->fqid = qid.fqid;
3005
3006         queue.destination.id = fq->channel->dpcon_id;
3007         queue.destination.type = DPNI_DEST_DPCON;
3008         queue.destination.priority = 0;
3009         queue.user_context = (u64)(uintptr_t)fq;
3010         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3011                              DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3012                              DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
3013                              &queue);
3014         if (err) {
3015                 dev_err(dev, "dpni_set_queue(TX_CONF) failed\n");
3016                 return err;
3017         }
3018
3019         return 0;
3020 }
3021
3022 /* Supported header fields for Rx hash distribution key */
3023 static const struct dpaa2_eth_dist_fields dist_fields[] = {
3024         {
3025                 /* L2 header */
3026                 .rxnfc_field = RXH_L2DA,
3027                 .cls_prot = NET_PROT_ETH,
3028                 .cls_field = NH_FLD_ETH_DA,
3029                 .id = DPAA2_ETH_DIST_ETHDST,
3030                 .size = 6,
3031         }, {
3032                 .cls_prot = NET_PROT_ETH,
3033                 .cls_field = NH_FLD_ETH_SA,
3034                 .id = DPAA2_ETH_DIST_ETHSRC,
3035                 .size = 6,
3036         }, {
3037                 /* This is the last ethertype field parsed:
3038                  * depending on frame format, it can be the MAC ethertype
3039                  * or the VLAN etype.
3040                  */
3041                 .cls_prot = NET_PROT_ETH,
3042                 .cls_field = NH_FLD_ETH_TYPE,
3043                 .id = DPAA2_ETH_DIST_ETHTYPE,
3044                 .size = 2,
3045         }, {
3046                 /* VLAN header */
3047                 .rxnfc_field = RXH_VLAN,
3048                 .cls_prot = NET_PROT_VLAN,
3049                 .cls_field = NH_FLD_VLAN_TCI,
3050                 .id = DPAA2_ETH_DIST_VLAN,
3051                 .size = 2,
3052         }, {
3053                 /* IP header */
3054                 .rxnfc_field = RXH_IP_SRC,
3055                 .cls_prot = NET_PROT_IP,
3056                 .cls_field = NH_FLD_IP_SRC,
3057                 .id = DPAA2_ETH_DIST_IPSRC,
3058                 .size = 4,
3059         }, {
3060                 .rxnfc_field = RXH_IP_DST,
3061                 .cls_prot = NET_PROT_IP,
3062                 .cls_field = NH_FLD_IP_DST,
3063                 .id = DPAA2_ETH_DIST_IPDST,
3064                 .size = 4,
3065         }, {
3066                 .rxnfc_field = RXH_L3_PROTO,
3067                 .cls_prot = NET_PROT_IP,
3068                 .cls_field = NH_FLD_IP_PROTO,
3069                 .id = DPAA2_ETH_DIST_IPPROTO,
3070                 .size = 1,
3071         }, {
3072                 /* Using UDP ports, this is functionally equivalent to raw
3073                  * byte pairs from L4 header.
3074                  */
3075                 .rxnfc_field = RXH_L4_B_0_1,
3076                 .cls_prot = NET_PROT_UDP,
3077                 .cls_field = NH_FLD_UDP_PORT_SRC,
3078                 .id = DPAA2_ETH_DIST_L4SRC,
3079                 .size = 2,
3080         }, {
3081                 .rxnfc_field = RXH_L4_B_2_3,
3082                 .cls_prot = NET_PROT_UDP,
3083                 .cls_field = NH_FLD_UDP_PORT_DST,
3084                 .id = DPAA2_ETH_DIST_L4DST,
3085                 .size = 2,
3086         },
3087 };
3088
3089 /* Configure the Rx hash key using the legacy API */
3090 static int config_legacy_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3091 {
3092         struct device *dev = priv->net_dev->dev.parent;
3093         struct dpni_rx_tc_dist_cfg dist_cfg;
3094         int i, err = 0;
3095
3096         memset(&dist_cfg, 0, sizeof(dist_cfg));
3097
3098         dist_cfg.key_cfg_iova = key;
3099         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3100         dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
3101
3102         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3103                 err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token,
3104                                           i, &dist_cfg);
3105                 if (err) {
3106                         dev_err(dev, "dpni_set_rx_tc_dist failed\n");
3107                         break;
3108                 }
3109         }
3110
3111         return err;
3112 }
3113
3114 /* Configure the Rx hash key using the new API */
3115 static int config_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3116 {
3117         struct device *dev = priv->net_dev->dev.parent;
3118         struct dpni_rx_dist_cfg dist_cfg;
3119         int i, err = 0;
3120
3121         memset(&dist_cfg, 0, sizeof(dist_cfg));
3122
3123         dist_cfg.key_cfg_iova = key;
3124         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3125         dist_cfg.enable = 1;
3126
3127         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3128                 dist_cfg.tc = i;
3129                 err = dpni_set_rx_hash_dist(priv->mc_io, 0, priv->mc_token,
3130                                             &dist_cfg);
3131                 if (err) {
3132                         dev_err(dev, "dpni_set_rx_hash_dist failed\n");
3133                         break;
3134                 }
3135         }
3136
3137         return err;
3138 }
3139
3140 /* Configure the Rx flow classification key */
3141 static int config_cls_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3142 {
3143         struct device *dev = priv->net_dev->dev.parent;
3144         struct dpni_rx_dist_cfg dist_cfg;
3145         int i, err = 0;
3146
3147         memset(&dist_cfg, 0, sizeof(dist_cfg));
3148
3149         dist_cfg.key_cfg_iova = key;
3150         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3151         dist_cfg.enable = 1;
3152
3153         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3154                 dist_cfg.tc = i;
3155                 err = dpni_set_rx_fs_dist(priv->mc_io, 0, priv->mc_token,
3156                                           &dist_cfg);
3157                 if (err) {
3158                         dev_err(dev, "dpni_set_rx_fs_dist failed\n");
3159                         break;
3160                 }
3161         }
3162
3163         return err;
3164 }
3165
3166 /* Size of the Rx flow classification key */
3167 int dpaa2_eth_cls_key_size(u64 fields)
3168 {
3169         int i, size = 0;
3170
3171         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3172                 if (!(fields & dist_fields[i].id))
3173                         continue;
3174                 size += dist_fields[i].size;
3175         }
3176
3177         return size;
3178 }
3179
3180 /* Offset of header field in Rx classification key */
3181 int dpaa2_eth_cls_fld_off(int prot, int field)
3182 {
3183         int i, off = 0;
3184
3185         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3186                 if (dist_fields[i].cls_prot == prot &&
3187                     dist_fields[i].cls_field == field)
3188                         return off;
3189                 off += dist_fields[i].size;
3190         }
3191
3192         WARN_ONCE(1, "Unsupported header field used for Rx flow cls\n");
3193         return 0;
3194 }
3195
3196 /* Prune unused fields from the classification rule.
3197  * Used when masking is not supported
3198  */
3199 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields)
3200 {
3201         int off = 0, new_off = 0;
3202         int i, size;
3203
3204         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3205                 size = dist_fields[i].size;
3206                 if (dist_fields[i].id & fields) {
3207                         memcpy(key_mem + new_off, key_mem + off, size);
3208                         new_off += size;
3209                 }
3210                 off += size;
3211         }
3212 }
3213
3214 /* Set Rx distribution (hash or flow classification) key
3215  * flags is a combination of RXH_ bits
3216  */
3217 static int dpaa2_eth_set_dist_key(struct net_device *net_dev,
3218                                   enum dpaa2_eth_rx_dist type, u64 flags)
3219 {
3220         struct device *dev = net_dev->dev.parent;
3221         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3222         struct dpkg_profile_cfg cls_cfg;
3223         u32 rx_hash_fields = 0;
3224         dma_addr_t key_iova;
3225         u8 *dma_mem;
3226         int i;
3227         int err = 0;
3228
3229         memset(&cls_cfg, 0, sizeof(cls_cfg));
3230
3231         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3232                 struct dpkg_extract *key =
3233                         &cls_cfg.extracts[cls_cfg.num_extracts];
3234
3235                 /* For both Rx hashing and classification keys
3236                  * we set only the selected fields.
3237                  */
3238                 if (!(flags & dist_fields[i].id))
3239                         continue;
3240                 if (type == DPAA2_ETH_RX_DIST_HASH)
3241                         rx_hash_fields |= dist_fields[i].rxnfc_field;
3242
3243                 if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) {
3244                         dev_err(dev, "error adding key extraction rule, too many rules?\n");
3245                         return -E2BIG;
3246                 }
3247
3248                 key->type = DPKG_EXTRACT_FROM_HDR;
3249                 key->extract.from_hdr.prot = dist_fields[i].cls_prot;
3250                 key->extract.from_hdr.type = DPKG_FULL_FIELD;
3251                 key->extract.from_hdr.field = dist_fields[i].cls_field;
3252                 cls_cfg.num_extracts++;
3253         }
3254
3255         dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
3256         if (!dma_mem)
3257                 return -ENOMEM;
3258
3259         err = dpni_prepare_key_cfg(&cls_cfg, dma_mem);
3260         if (err) {
3261                 dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
3262                 goto free_key;
3263         }
3264
3265         /* Prepare for setting the rx dist */
3266         key_iova = dma_map_single(dev, dma_mem, DPAA2_CLASSIFIER_DMA_SIZE,
3267                                   DMA_TO_DEVICE);
3268         if (dma_mapping_error(dev, key_iova)) {
3269                 dev_err(dev, "DMA mapping failed\n");
3270                 err = -ENOMEM;
3271                 goto free_key;
3272         }
3273
3274         if (type == DPAA2_ETH_RX_DIST_HASH) {
3275                 if (dpaa2_eth_has_legacy_dist(priv))
3276                         err = config_legacy_hash_key(priv, key_iova);
3277                 else
3278                         err = config_hash_key(priv, key_iova);
3279         } else {
3280                 err = config_cls_key(priv, key_iova);
3281         }
3282
3283         dma_unmap_single(dev, key_iova, DPAA2_CLASSIFIER_DMA_SIZE,
3284                          DMA_TO_DEVICE);
3285         if (!err && type == DPAA2_ETH_RX_DIST_HASH)
3286                 priv->rx_hash_fields = rx_hash_fields;
3287
3288 free_key:
3289         kfree(dma_mem);
3290         return err;
3291 }
3292
3293 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags)
3294 {
3295         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3296         u64 key = 0;
3297         int i;
3298
3299         if (!dpaa2_eth_hash_enabled(priv))
3300                 return -EOPNOTSUPP;
3301
3302         for (i = 0; i < ARRAY_SIZE(dist_fields); i++)
3303                 if (dist_fields[i].rxnfc_field & flags)
3304                         key |= dist_fields[i].id;
3305
3306         return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_HASH, key);
3307 }
3308
3309 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 flags)
3310 {
3311         return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_CLS, flags);
3312 }
3313
3314 static int dpaa2_eth_set_default_cls(struct dpaa2_eth_priv *priv)
3315 {
3316         struct device *dev = priv->net_dev->dev.parent;
3317         int err;
3318
3319         /* Check if we actually support Rx flow classification */
3320         if (dpaa2_eth_has_legacy_dist(priv)) {
3321                 dev_dbg(dev, "Rx cls not supported by current MC version\n");
3322                 return -EOPNOTSUPP;
3323         }
3324
3325         if (!dpaa2_eth_fs_enabled(priv)) {
3326                 dev_dbg(dev, "Rx cls disabled in DPNI options\n");
3327                 return -EOPNOTSUPP;
3328         }
3329
3330         if (!dpaa2_eth_hash_enabled(priv)) {
3331                 dev_dbg(dev, "Rx cls disabled for single queue DPNIs\n");
3332                 return -EOPNOTSUPP;
3333         }
3334
3335         /* If there is no support for masking in the classification table,
3336          * we don't set a default key, as it will depend on the rules
3337          * added by the user at runtime.
3338          */
3339         if (!dpaa2_eth_fs_mask_enabled(priv))
3340                 goto out;
3341
3342         err = dpaa2_eth_set_cls(priv->net_dev, DPAA2_ETH_DIST_ALL);
3343         if (err)
3344                 return err;
3345
3346 out:
3347         priv->rx_cls_enabled = 1;
3348
3349         return 0;
3350 }
3351
3352 /* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs,
3353  * frame queues and channels
3354  */
3355 static int bind_dpni(struct dpaa2_eth_priv *priv)
3356 {
3357         struct net_device *net_dev = priv->net_dev;
3358         struct device *dev = net_dev->dev.parent;
3359         struct dpni_pools_cfg pools_params;
3360         struct dpni_error_cfg err_cfg;
3361         int err = 0;
3362         int i;
3363
3364         pools_params.num_dpbp = 1;
3365         pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id;
3366         pools_params.pools[0].backup_pool = 0;
3367         pools_params.pools[0].buffer_size = priv->rx_buf_size;
3368         err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
3369         if (err) {
3370                 dev_err(dev, "dpni_set_pools() failed\n");
3371                 return err;
3372         }
3373
3374         /* have the interface implicitly distribute traffic based on
3375          * the default hash key
3376          */
3377         err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_DEFAULT);
3378         if (err && err != -EOPNOTSUPP)
3379                 dev_err(dev, "Failed to configure hashing\n");
3380
3381         /* Configure the flow classification key; it includes all
3382          * supported header fields and cannot be modified at runtime
3383          */
3384         err = dpaa2_eth_set_default_cls(priv);
3385         if (err && err != -EOPNOTSUPP)
3386                 dev_err(dev, "Failed to configure Rx classification key\n");
3387
3388         /* Configure handling of error frames */
3389         err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
3390         err_cfg.set_frame_annotation = 1;
3391         err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
3392         err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
3393                                        &err_cfg);
3394         if (err) {
3395                 dev_err(dev, "dpni_set_errors_behavior failed\n");
3396                 return err;
3397         }
3398
3399         /* Configure Rx and Tx conf queues to generate CDANs */
3400         for (i = 0; i < priv->num_fqs; i++) {
3401                 switch (priv->fq[i].type) {
3402                 case DPAA2_RX_FQ:
3403                         err = setup_rx_flow(priv, &priv->fq[i]);
3404                         break;
3405                 case DPAA2_TX_CONF_FQ:
3406                         err = setup_tx_flow(priv, &priv->fq[i]);
3407                         break;
3408                 default:
3409                         dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
3410                         return -EINVAL;
3411                 }
3412                 if (err)
3413                         return err;
3414         }
3415
3416         err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token,
3417                             DPNI_QUEUE_TX, &priv->tx_qdid);
3418         if (err) {
3419                 dev_err(dev, "dpni_get_qdid() failed\n");
3420                 return err;
3421         }
3422
3423         return 0;
3424 }
3425
3426 /* Allocate rings for storing incoming frame descriptors */
3427 static int alloc_rings(struct dpaa2_eth_priv *priv)
3428 {
3429         struct net_device *net_dev = priv->net_dev;
3430         struct device *dev = net_dev->dev.parent;
3431         int i;
3432
3433         for (i = 0; i < priv->num_channels; i++) {
3434                 priv->channel[i]->store =
3435                         dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev);
3436                 if (!priv->channel[i]->store) {
3437                         netdev_err(net_dev, "dpaa2_io_store_create() failed\n");
3438                         goto err_ring;
3439                 }
3440         }
3441
3442         return 0;
3443
3444 err_ring:
3445         for (i = 0; i < priv->num_channels; i++) {
3446                 if (!priv->channel[i]->store)
3447                         break;
3448                 dpaa2_io_store_destroy(priv->channel[i]->store);
3449         }
3450
3451         return -ENOMEM;
3452 }
3453
3454 static void free_rings(struct dpaa2_eth_priv *priv)
3455 {
3456         int i;
3457
3458         for (i = 0; i < priv->num_channels; i++)
3459                 dpaa2_io_store_destroy(priv->channel[i]->store);
3460 }
3461
3462 static int set_mac_addr(struct dpaa2_eth_priv *priv)
3463 {
3464         struct net_device *net_dev = priv->net_dev;
3465         struct device *dev = net_dev->dev.parent;
3466         u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN];
3467         int err;
3468
3469         /* Get firmware address, if any */
3470         err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr);
3471         if (err) {
3472                 dev_err(dev, "dpni_get_port_mac_addr() failed\n");
3473                 return err;
3474         }
3475
3476         /* Get DPNI attributes address, if any */
3477         err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
3478                                         dpni_mac_addr);
3479         if (err) {
3480                 dev_err(dev, "dpni_get_primary_mac_addr() failed\n");
3481                 return err;
3482         }
3483
3484         /* First check if firmware has any address configured by bootloader */
3485         if (!is_zero_ether_addr(mac_addr)) {
3486                 /* If the DPMAC addr != DPNI addr, update it */
3487                 if (!ether_addr_equal(mac_addr, dpni_mac_addr)) {
3488                         err = dpni_set_primary_mac_addr(priv->mc_io, 0,
3489                                                         priv->mc_token,
3490                                                         mac_addr);
3491                         if (err) {
3492                                 dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
3493                                 return err;
3494                         }
3495                 }
3496                 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
3497         } else if (is_zero_ether_addr(dpni_mac_addr)) {
3498                 /* No MAC address configured, fill in net_dev->dev_addr
3499                  * with a random one
3500                  */
3501                 eth_hw_addr_random(net_dev);
3502                 dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n");
3503
3504                 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
3505                                                 net_dev->dev_addr);
3506                 if (err) {
3507                         dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
3508                         return err;
3509                 }
3510
3511                 /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all
3512                  * practical purposes, this will be our "permanent" mac address,
3513                  * at least until the next reboot. This move will also permit
3514                  * register_netdevice() to properly fill up net_dev->perm_addr.
3515                  */
3516                 net_dev->addr_assign_type = NET_ADDR_PERM;
3517         } else {
3518                 /* NET_ADDR_PERM is default, all we have to do is
3519                  * fill in the device addr.
3520                  */
3521                 memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len);
3522         }
3523
3524         return 0;
3525 }
3526
3527 static int netdev_init(struct net_device *net_dev)
3528 {
3529         struct device *dev = net_dev->dev.parent;
3530         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3531         u32 options = priv->dpni_attrs.options;
3532         u64 supported = 0, not_supported = 0;
3533         u8 bcast_addr[ETH_ALEN];
3534         u8 num_queues;
3535         int err;
3536
3537         net_dev->netdev_ops = &dpaa2_eth_ops;
3538         net_dev->ethtool_ops = &dpaa2_ethtool_ops;
3539
3540         err = set_mac_addr(priv);
3541         if (err)
3542                 return err;
3543
3544         /* Explicitly add the broadcast address to the MAC filtering table */
3545         eth_broadcast_addr(bcast_addr);
3546         err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr);
3547         if (err) {
3548                 dev_err(dev, "dpni_add_mac_addr() failed\n");
3549                 return err;
3550         }
3551
3552         /* Set MTU upper limit; lower limit is 68B (default value) */
3553         net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
3554         err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
3555                                         DPAA2_ETH_MFL);
3556         if (err) {
3557                 dev_err(dev, "dpni_set_max_frame_length() failed\n");
3558                 return err;
3559         }
3560
3561         /* Set actual number of queues in the net device */
3562         num_queues = dpaa2_eth_queue_count(priv);
3563         err = netif_set_real_num_tx_queues(net_dev, num_queues);
3564         if (err) {
3565                 dev_err(dev, "netif_set_real_num_tx_queues() failed\n");
3566                 return err;
3567         }
3568         err = netif_set_real_num_rx_queues(net_dev, num_queues);
3569         if (err) {
3570                 dev_err(dev, "netif_set_real_num_rx_queues() failed\n");
3571                 return err;
3572         }
3573
3574         /* Capabilities listing */
3575         supported |= IFF_LIVE_ADDR_CHANGE;
3576
3577         if (options & DPNI_OPT_NO_MAC_FILTER)
3578                 not_supported |= IFF_UNICAST_FLT;
3579         else
3580                 supported |= IFF_UNICAST_FLT;
3581
3582         net_dev->priv_flags |= supported;
3583         net_dev->priv_flags &= ~not_supported;
3584
3585         /* Features */
3586         net_dev->features = NETIF_F_RXCSUM |
3587                             NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3588                             NETIF_F_SG | NETIF_F_HIGHDMA |
3589                             NETIF_F_LLTX;
3590         net_dev->hw_features = net_dev->features;
3591
3592         return 0;
3593 }
3594
3595 static int poll_link_state(void *arg)
3596 {
3597         struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg;
3598         int err;
3599
3600         while (!kthread_should_stop()) {
3601                 err = link_state_update(priv);
3602                 if (unlikely(err))
3603                         return err;
3604
3605                 msleep(DPAA2_ETH_LINK_STATE_REFRESH);
3606         }
3607
3608         return 0;
3609 }
3610
3611 static int dpaa2_eth_connect_mac(struct dpaa2_eth_priv *priv)
3612 {
3613         struct fsl_mc_device *dpni_dev, *dpmac_dev;
3614         struct dpaa2_mac *mac;
3615         int err;
3616
3617         dpni_dev = to_fsl_mc_device(priv->net_dev->dev.parent);
3618         dpmac_dev = fsl_mc_get_endpoint(dpni_dev);
3619         if (IS_ERR(dpmac_dev) || dpmac_dev->dev.type != &fsl_mc_bus_dpmac_type)
3620                 return 0;
3621
3622         if (dpaa2_mac_is_type_fixed(dpmac_dev, priv->mc_io))
3623                 return 0;
3624
3625         mac = kzalloc(sizeof(struct dpaa2_mac), GFP_KERNEL);
3626         if (!mac)
3627                 return -ENOMEM;
3628
3629         mac->mc_dev = dpmac_dev;
3630         mac->mc_io = priv->mc_io;
3631         mac->net_dev = priv->net_dev;
3632
3633         err = dpaa2_mac_connect(mac);
3634         if (err) {
3635                 netdev_err(priv->net_dev, "Error connecting to the MAC endpoint\n");
3636                 kfree(mac);
3637                 return err;
3638         }
3639         priv->mac = mac;
3640
3641         return 0;
3642 }
3643
3644 static void dpaa2_eth_disconnect_mac(struct dpaa2_eth_priv *priv)
3645 {
3646         if (!priv->mac)
3647                 return;
3648
3649         dpaa2_mac_disconnect(priv->mac);
3650         kfree(priv->mac);
3651         priv->mac = NULL;
3652 }
3653
3654 static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
3655 {
3656         u32 status = ~0;
3657         struct device *dev = (struct device *)arg;
3658         struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
3659         struct net_device *net_dev = dev_get_drvdata(dev);
3660         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3661         int err;
3662
3663         err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
3664                                   DPNI_IRQ_INDEX, &status);
3665         if (unlikely(err)) {
3666                 netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
3667                 return IRQ_HANDLED;
3668         }
3669
3670         if (status & DPNI_IRQ_EVENT_LINK_CHANGED)
3671                 link_state_update(netdev_priv(net_dev));
3672
3673         if (status & DPNI_IRQ_EVENT_ENDPOINT_CHANGED) {
3674                 set_mac_addr(netdev_priv(net_dev));
3675                 update_tx_fqids(priv);
3676
3677                 rtnl_lock();
3678                 if (priv->mac)
3679                         dpaa2_eth_disconnect_mac(priv);
3680                 else
3681                         dpaa2_eth_connect_mac(priv);
3682                 rtnl_unlock();
3683         }
3684
3685         return IRQ_HANDLED;
3686 }
3687
3688 static int setup_irqs(struct fsl_mc_device *ls_dev)
3689 {
3690         int err = 0;
3691         struct fsl_mc_device_irq *irq;
3692
3693         err = fsl_mc_allocate_irqs(ls_dev);
3694         if (err) {
3695                 dev_err(&ls_dev->dev, "MC irqs allocation failed\n");
3696                 return err;
3697         }
3698
3699         irq = ls_dev->irqs[0];
3700         err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq,
3701                                         NULL, dpni_irq0_handler_thread,
3702                                         IRQF_NO_SUSPEND | IRQF_ONESHOT,
3703                                         dev_name(&ls_dev->dev), &ls_dev->dev);
3704         if (err < 0) {
3705                 dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err);
3706                 goto free_mc_irq;
3707         }
3708
3709         err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle,
3710                                 DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED |
3711                                 DPNI_IRQ_EVENT_ENDPOINT_CHANGED);
3712         if (err < 0) {
3713                 dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err);
3714                 goto free_irq;
3715         }
3716
3717         err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle,
3718                                   DPNI_IRQ_INDEX, 1);
3719         if (err < 0) {
3720                 dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err);
3721                 goto free_irq;
3722         }
3723
3724         return 0;
3725
3726 free_irq:
3727         devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev);
3728 free_mc_irq:
3729         fsl_mc_free_irqs(ls_dev);
3730
3731         return err;
3732 }
3733
3734 static void add_ch_napi(struct dpaa2_eth_priv *priv)
3735 {
3736         int i;
3737         struct dpaa2_eth_channel *ch;
3738
3739         for (i = 0; i < priv->num_channels; i++) {
3740                 ch = priv->channel[i];
3741                 /* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */
3742                 netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll,
3743                                NAPI_POLL_WEIGHT);
3744         }
3745 }
3746
3747 static void del_ch_napi(struct dpaa2_eth_priv *priv)
3748 {
3749         int i;
3750         struct dpaa2_eth_channel *ch;
3751
3752         for (i = 0; i < priv->num_channels; i++) {
3753                 ch = priv->channel[i];
3754                 netif_napi_del(&ch->napi);
3755         }
3756 }
3757
3758 static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
3759 {
3760         struct device *dev;
3761         struct net_device *net_dev = NULL;
3762         struct dpaa2_eth_priv *priv = NULL;
3763         int err = 0;
3764
3765         dev = &dpni_dev->dev;
3766
3767         /* Net device */
3768         net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_NETDEV_QUEUES);
3769         if (!net_dev) {
3770                 dev_err(dev, "alloc_etherdev_mq() failed\n");
3771                 return -ENOMEM;
3772         }
3773
3774         SET_NETDEV_DEV(net_dev, dev);
3775         dev_set_drvdata(dev, net_dev);
3776
3777         priv = netdev_priv(net_dev);
3778         priv->net_dev = net_dev;
3779
3780         priv->iommu_domain = iommu_get_domain_for_dev(dev);
3781
3782         /* Obtain a MC portal */
3783         err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
3784                                      &priv->mc_io);
3785         if (err) {
3786                 if (err == -ENXIO)
3787                         err = -EPROBE_DEFER;
3788                 else
3789                         dev_err(dev, "MC portal allocation failed\n");
3790                 goto err_portal_alloc;
3791         }
3792
3793         /* MC objects initialization and configuration */
3794         err = setup_dpni(dpni_dev);
3795         if (err)
3796                 goto err_dpni_setup;
3797
3798         err = setup_dpio(priv);
3799         if (err)
3800                 goto err_dpio_setup;
3801
3802         setup_fqs(priv);
3803
3804         err = setup_dpbp(priv);
3805         if (err)
3806                 goto err_dpbp_setup;
3807
3808         err = bind_dpni(priv);
3809         if (err)
3810                 goto err_bind;
3811
3812         /* Add a NAPI context for each channel */
3813         add_ch_napi(priv);
3814
3815         /* Percpu statistics */
3816         priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
3817         if (!priv->percpu_stats) {
3818                 dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
3819                 err = -ENOMEM;
3820                 goto err_alloc_percpu_stats;
3821         }
3822         priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
3823         if (!priv->percpu_extras) {
3824                 dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
3825                 err = -ENOMEM;
3826                 goto err_alloc_percpu_extras;
3827         }
3828
3829         err = netdev_init(net_dev);
3830         if (err)
3831                 goto err_netdev_init;
3832
3833         /* Configure checksum offload based on current interface flags */
3834         err = set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
3835         if (err)
3836                 goto err_csum;
3837
3838         err = set_tx_csum(priv, !!(net_dev->features &
3839                                    (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
3840         if (err)
3841                 goto err_csum;
3842
3843         err = alloc_rings(priv);
3844         if (err)
3845                 goto err_alloc_rings;
3846
3847 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
3848         if (dpaa2_eth_has_pause_support(priv) && priv->vlan_cls_enabled) {
3849                 priv->dcbx_mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
3850                 net_dev->dcbnl_ops = &dpaa2_eth_dcbnl_ops;
3851         } else {
3852                 dev_dbg(dev, "PFC not supported\n");
3853         }
3854 #endif
3855
3856         err = setup_irqs(dpni_dev);
3857         if (err) {
3858                 netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n");
3859                 priv->poll_thread = kthread_run(poll_link_state, priv,
3860                                                 "%s_poll_link", net_dev->name);
3861                 if (IS_ERR(priv->poll_thread)) {
3862                         dev_err(dev, "Error starting polling thread\n");
3863                         goto err_poll_thread;
3864                 }
3865                 priv->do_link_poll = true;
3866         }
3867
3868         err = dpaa2_eth_connect_mac(priv);
3869         if (err)
3870                 goto err_connect_mac;
3871
3872         err = register_netdev(net_dev);
3873         if (err < 0) {
3874                 dev_err(dev, "register_netdev() failed\n");
3875                 goto err_netdev_reg;
3876         }
3877
3878 #ifdef CONFIG_DEBUG_FS
3879         dpaa2_dbg_add(priv);
3880 #endif
3881
3882         dev_info(dev, "Probed interface %s\n", net_dev->name);
3883         return 0;
3884
3885 err_netdev_reg:
3886         dpaa2_eth_disconnect_mac(priv);
3887 err_connect_mac:
3888         if (priv->do_link_poll)
3889                 kthread_stop(priv->poll_thread);
3890         else
3891                 fsl_mc_free_irqs(dpni_dev);
3892 err_poll_thread:
3893         free_rings(priv);
3894 err_alloc_rings:
3895 err_csum:
3896 err_netdev_init:
3897         free_percpu(priv->percpu_extras);
3898 err_alloc_percpu_extras:
3899         free_percpu(priv->percpu_stats);
3900 err_alloc_percpu_stats:
3901         del_ch_napi(priv);
3902 err_bind:
3903         free_dpbp(priv);
3904 err_dpbp_setup:
3905         free_dpio(priv);
3906 err_dpio_setup:
3907         free_dpni(priv);
3908 err_dpni_setup:
3909         fsl_mc_portal_free(priv->mc_io);
3910 err_portal_alloc:
3911         dev_set_drvdata(dev, NULL);
3912         free_netdev(net_dev);
3913
3914         return err;
3915 }
3916
3917 static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
3918 {
3919         struct device *dev;
3920         struct net_device *net_dev;
3921         struct dpaa2_eth_priv *priv;
3922
3923         dev = &ls_dev->dev;
3924         net_dev = dev_get_drvdata(dev);
3925         priv = netdev_priv(net_dev);
3926
3927 #ifdef CONFIG_DEBUG_FS
3928         dpaa2_dbg_remove(priv);
3929 #endif
3930         rtnl_lock();
3931         dpaa2_eth_disconnect_mac(priv);
3932         rtnl_unlock();
3933
3934         unregister_netdev(net_dev);
3935
3936         if (priv->do_link_poll)
3937                 kthread_stop(priv->poll_thread);
3938         else
3939                 fsl_mc_free_irqs(ls_dev);
3940
3941         free_rings(priv);
3942         free_percpu(priv->percpu_stats);
3943         free_percpu(priv->percpu_extras);
3944
3945         del_ch_napi(priv);
3946         free_dpbp(priv);
3947         free_dpio(priv);
3948         free_dpni(priv);
3949
3950         fsl_mc_portal_free(priv->mc_io);
3951
3952         free_netdev(net_dev);
3953
3954         dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
3955
3956         return 0;
3957 }
3958
3959 static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = {
3960         {
3961                 .vendor = FSL_MC_VENDOR_FREESCALE,
3962                 .obj_type = "dpni",
3963         },
3964         { .vendor = 0x0 }
3965 };
3966 MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table);
3967
3968 static struct fsl_mc_driver dpaa2_eth_driver = {
3969         .driver = {
3970                 .name = KBUILD_MODNAME,
3971                 .owner = THIS_MODULE,
3972         },
3973         .probe = dpaa2_eth_probe,
3974         .remove = dpaa2_eth_remove,
3975         .match_id_table = dpaa2_eth_match_id_table
3976 };
3977
3978 static int __init dpaa2_eth_driver_init(void)
3979 {
3980         int err;
3981
3982         dpaa2_eth_dbg_init();
3983         err = fsl_mc_driver_register(&dpaa2_eth_driver);
3984         if (err) {
3985                 dpaa2_eth_dbg_exit();
3986                 return err;
3987         }
3988
3989         return 0;
3990 }
3991
3992 static void __exit dpaa2_eth_driver_exit(void)
3993 {
3994         dpaa2_eth_dbg_exit();
3995         fsl_mc_driver_unregister(&dpaa2_eth_driver);
3996 }
3997
3998 module_init(dpaa2_eth_driver_init);
3999 module_exit(dpaa2_eth_driver_exit);