drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
   3  * Copyright 2016-2020 NXP
   4  */
   5 #include <linux/init.h>
   6 #include <linux/module.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/of_net.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/msi.h>
  12 #include <linux/kthread.h>
  13 #include <linux/iommu.h>
  14 #include <linux/fsl/mc.h>
  15 #include <linux/bpf.h>
  16 #include <linux/bpf_trace.h>
  17 #include <linux/fsl/ptp_qoriq.h>
  18 #include <linux/ptp_classify.h>
  19 #include <net/pkt_cls.h>
  20 #include <net/sock.h>
  21
  22 #include "dpaa2-eth.h"
  23
  24 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
  25  * using trace events only need to #include <trace/events/sched.h>
  26  */
  27 #define CREATE_TRACE_POINTS
  28 #include "dpaa2-eth-trace.h"
  29
  30 MODULE_LICENSE("Dual BSD/GPL");
  31 MODULE_AUTHOR("Freescale Semiconductor, Inc");
  32 MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
  33
  34 struct ptp_qoriq *dpaa2_ptp;
  35 EXPORT_SYMBOL(dpaa2_ptp);
  36
  37 static void *dpaa2_iova_to_virt(struct iommu_domain *domain,
  38                                 dma_addr_t iova_addr)
  39 {
  40         phys_addr_t phys_addr;
  41
  42         phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
  43
  44         return phys_to_virt(phys_addr);
  45 }
  46
  47 static void dpaa2_eth_validate_rx_csum(struct dpaa2_eth_priv *priv,
  48                                        u32 fd_status,
  49                                        struct sk_buff *skb)
  50 {
  51         skb_checksum_none_assert(skb);
  52
  53         /* HW checksum validation is disabled, nothing to do here */
  54         if (!(priv->net_dev->features & NETIF_F_RXCSUM))
  55                 return;
  56
  57         /* Read checksum validation bits */
  58         if (!((fd_status & DPAA2_FAS_L3CV) &&
  59               (fd_status & DPAA2_FAS_L4CV)))
  60                 return;
  61
  62         /* Inform the stack there's no need to compute L3/L4 csum anymore */
  63         skb->ip_summed = CHECKSUM_UNNECESSARY;
  64 }
  65
  66 /* Free a received FD.
  67  * Not to be used for Tx conf FDs or on any other paths.
  68  */
  69 static void dpaa2_eth_free_rx_fd(struct dpaa2_eth_priv *priv,
  70                                  const struct dpaa2_fd *fd,
  71                                  void *vaddr)
  72 {
  73         struct device *dev = priv->net_dev->dev.parent;
  74         dma_addr_t addr = dpaa2_fd_get_addr(fd);
  75         u8 fd_format = dpaa2_fd_get_format(fd);
  76         struct dpaa2_sg_entry *sgt;
  77         void *sg_vaddr;
  78         int i;
  79
  80         /* If single buffer frame, just free the data buffer */
  81         if (fd_format == dpaa2_fd_single)
  82                 goto free_buf;
  83         else if (fd_format != dpaa2_fd_sg)
  84                 /* We don't support any other format */
  85                 return;
  86
  87         /* For S/G frames, we first need to free all SG entries
  88          * except the first one, which was taken care of already
  89          */
  90         sgt = vaddr + dpaa2_fd_get_offset(fd);
  91         for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
  92                 addr = dpaa2_sg_get_addr(&sgt[i]);
  93                 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
  94                 dma_unmap_page(dev, addr, priv->rx_buf_size,
  95                                DMA_BIDIRECTIONAL);
  96
  97                 free_pages((unsigned long)sg_vaddr, 0);
  98                 if (dpaa2_sg_is_final(&sgt[i]))
  99                         break;
 100         }
 101
 102 free_buf:
 103         free_pages((unsigned long)vaddr, 0);
 104 }
 105
 106 /* Build a linear skb based on a single-buffer frame descriptor */
 107 static struct sk_buff *dpaa2_eth_build_linear_skb(struct dpaa2_eth_channel *ch,
 108                                                   const struct dpaa2_fd *fd,
 109                                                   void *fd_vaddr)
 110 {
 111         struct sk_buff *skb = NULL;
 112         u16 fd_offset = dpaa2_fd_get_offset(fd);
 113         u32 fd_length = dpaa2_fd_get_len(fd);
 114
 115         ch->buf_count--;
 116
 117         skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
 118         if (unlikely(!skb))
 119                 return NULL;
 120
 121         skb_reserve(skb, fd_offset);
 122         skb_put(skb, fd_length);
 123
 124         return skb;
 125 }
 126
 127 /* Build a non linear (fragmented) skb based on a S/G table */
 128 static struct sk_buff *dpaa2_eth_build_frag_skb(struct dpaa2_eth_priv *priv,
 129                                                 struct dpaa2_eth_channel *ch,
 130                                                 struct dpaa2_sg_entry *sgt)
 131 {
 132         struct sk_buff *skb = NULL;
 133         struct device *dev = priv->net_dev->dev.parent;
 134         void *sg_vaddr;
 135         dma_addr_t sg_addr;
 136         u16 sg_offset;
 137         u32 sg_length;
 138         struct page *page, *head_page;
 139         int page_offset;
 140         int i;
 141
 142         for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
 143                 struct dpaa2_sg_entry *sge = &sgt[i];
 144
 145                 /* NOTE: We only support SG entries in dpaa2_sg_single format,
 146                  * but this is the only format we may receive from HW anyway
 147                  */
 148
 149                 /* Get the address and length from the S/G entry */
 150                 sg_addr = dpaa2_sg_get_addr(sge);
 151                 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
 152                 dma_unmap_page(dev, sg_addr, priv->rx_buf_size,
 153                                DMA_BIDIRECTIONAL);
 154
 155                 sg_length = dpaa2_sg_get_len(sge);
 156
 157                 if (i == 0) {
 158                         /* We build the skb around the first data buffer */
 159                         skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
 160                         if (unlikely(!skb)) {
 161                                 /* Free the first SG entry now, since we already
 162                                  * unmapped it and obtained the virtual address
 163                                  */
 164                                 free_pages((unsigned long)sg_vaddr, 0);
 165
 166                                 /* We still need to subtract the buffers used
 167                                  * by this FD from our software counter
 168                                  */
 169                                 while (!dpaa2_sg_is_final(&sgt[i]) &&
 170                                        i < DPAA2_ETH_MAX_SG_ENTRIES)
 171                                         i++;
 172                                 break;
 173                         }
 174
 175                         sg_offset = dpaa2_sg_get_offset(sge);
 176                         skb_reserve(skb, sg_offset);
 177                         skb_put(skb, sg_length);
 178                 } else {
 179                         /* Rest of the data buffers are stored as skb frags */
 180                         page = virt_to_page(sg_vaddr);
 181                         head_page = virt_to_head_page(sg_vaddr);
 182
 183                         /* Offset in page (which may be compound).
 184                          * Data in subsequent SG entries is stored from the
 185                          * beginning of the buffer, so we don't need to add the
 186                          * sg_offset.
 187                          */
 188                         page_offset = ((unsigned long)sg_vaddr &
 189                                 (PAGE_SIZE - 1)) +
 190                                 (page_address(page) - page_address(head_page));
 191
 192                         skb_add_rx_frag(skb, i - 1, head_page, page_offset,
 193                                         sg_length, priv->rx_buf_size);
 194                 }
 195
 196                 if (dpaa2_sg_is_final(sge))
 197                         break;
 198         }
 199
 200         WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
 201
 202         /* Count all data buffers + SG table buffer */
 203         ch->buf_count -= i + 2;
 204
 205         return skb;
 206 }
 207
 208 /* Free buffers acquired from the buffer pool or which were meant to
 209  * be released in the pool
 210  */
 211 static void dpaa2_eth_free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array,
 212                                 int count)
 213 {
 214         struct device *dev = priv->net_dev->dev.parent;
 215         void *vaddr;
 216         int i;
 217
 218         for (i = 0; i < count; i++) {
 219                 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
 220                 dma_unmap_page(dev, buf_array[i], priv->rx_buf_size,
 221                                DMA_BIDIRECTIONAL);
 222                 free_pages((unsigned long)vaddr, 0);
 223         }
 224 }
 225
 226 static void dpaa2_eth_xdp_release_buf(struct dpaa2_eth_priv *priv,
 227                                       struct dpaa2_eth_channel *ch,
 228                                       dma_addr_t addr)
 229 {
 230         int retries = 0;
 231         int err;
 232
 233         ch->xdp.drop_bufs[ch->xdp.drop_cnt++] = addr;
 234         if (ch->xdp.drop_cnt < DPAA2_ETH_BUFS_PER_CMD)
 235                 return;
 236
 237         while ((err = dpaa2_io_service_release(ch->dpio, priv->bpid,
 238                                                ch->xdp.drop_bufs,
 239                                                ch->xdp.drop_cnt)) == -EBUSY) {
 240                 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
 241                         break;
 242                 cpu_relax();
 243         }
 244
 245         if (err) {
 246                 dpaa2_eth_free_bufs(priv, ch->xdp.drop_bufs, ch->xdp.drop_cnt);
 247                 ch->buf_count -= ch->xdp.drop_cnt;
 248         }
 249
 250         ch->xdp.drop_cnt = 0;
 251 }
 252
 253 static int dpaa2_eth_xdp_flush(struct dpaa2_eth_priv *priv,
 254                                struct dpaa2_eth_fq *fq,
 255                                struct dpaa2_eth_xdp_fds *xdp_fds)
 256 {
 257         int total_enqueued = 0, retries = 0, enqueued;
 258         struct dpaa2_eth_drv_stats *percpu_extras;
 259         int num_fds, err, max_retries;
 260         struct dpaa2_fd *fds;
 261
 262         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 263
 264         /* try to enqueue all the FDs until the max number of retries is hit */
 265         fds = xdp_fds->fds;
 266         num_fds = xdp_fds->num;
 267         max_retries = num_fds * DPAA2_ETH_ENQUEUE_RETRIES;
 268         while (total_enqueued < num_fds && retries < max_retries) {
 269                 err = priv->enqueue(priv, fq, &fds[total_enqueued],
 270                                     0, num_fds - total_enqueued, &enqueued);
 271                 if (err == -EBUSY) {
 272                         percpu_extras->tx_portal_busy += ++retries;
 273                         continue;
 274                 }
 275                 total_enqueued += enqueued;
 276         }
 277         xdp_fds->num = 0;
 278
 279         return total_enqueued;
 280 }
 281
 282 static void dpaa2_eth_xdp_tx_flush(struct dpaa2_eth_priv *priv,
 283                                    struct dpaa2_eth_channel *ch,
 284                                    struct dpaa2_eth_fq *fq)
 285 {
 286         struct rtnl_link_stats64 *percpu_stats;
 287         struct dpaa2_fd *fds;
 288         int enqueued, i;
 289
 290         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 291
 292         // enqueue the array of XDP_TX frames
 293         enqueued = dpaa2_eth_xdp_flush(priv, fq, &fq->xdp_tx_fds);
 294
 295         /* update statistics */
 296         percpu_stats->tx_packets += enqueued;
 297         fds = fq->xdp_tx_fds.fds;
 298         for (i = 0; i < enqueued; i++) {
 299                 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
 300                 ch->stats.xdp_tx++;
 301         }
 302         for (i = enqueued; i < fq->xdp_tx_fds.num; i++) {
 303                 dpaa2_eth_xdp_release_buf(priv, ch, dpaa2_fd_get_addr(&fds[i]));
 304                 percpu_stats->tx_errors++;
 305                 ch->stats.xdp_tx_err++;
 306         }
 307         fq->xdp_tx_fds.num = 0;
 308 }
 309
 310 static void dpaa2_eth_xdp_enqueue(struct dpaa2_eth_priv *priv,
 311                                   struct dpaa2_eth_channel *ch,
 312                                   struct dpaa2_fd *fd,
 313                                   void *buf_start, u16 queue_id)
 314 {
 315         struct dpaa2_faead *faead;
 316         struct dpaa2_fd *dest_fd;
 317         struct dpaa2_eth_fq *fq;
 318         u32 ctrl, frc;
 319
 320         /* Mark the egress frame hardware annotation area as valid */
 321         frc = dpaa2_fd_get_frc(fd);
 322         dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
 323         dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL);
 324
 325         /* Instruct hardware to release the FD buffer directly into
 326          * the buffer pool once transmission is completed, instead of
 327          * sending a Tx confirmation frame to us
 328          */
 329         ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV;
 330         faead = dpaa2_get_faead(buf_start, false);
 331         faead->ctrl = cpu_to_le32(ctrl);
 332         faead->conf_fqid = 0;
 333
 334         fq = &priv->fq[queue_id];
 335         dest_fd = &fq->xdp_tx_fds.fds[fq->xdp_tx_fds.num++];
 336         memcpy(dest_fd, fd, sizeof(*dest_fd));
 337
 338         if (fq->xdp_tx_fds.num < DEV_MAP_BULK_SIZE)
 339                 return;
 340
 341         dpaa2_eth_xdp_tx_flush(priv, ch, fq);
 342 }
 343
 344 static u32 dpaa2_eth_run_xdp(struct dpaa2_eth_priv *priv,
 345                              struct dpaa2_eth_channel *ch,
 346                              struct dpaa2_eth_fq *rx_fq,
 347                              struct dpaa2_fd *fd, void *vaddr)
 348 {
 349         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 350         struct bpf_prog *xdp_prog;
 351         struct xdp_buff xdp;
 352         u32 xdp_act = XDP_PASS;
 353         int err, offset;
 354
 355         rcu_read_lock();
 356
 357         xdp_prog = READ_ONCE(ch->xdp.prog);
 358         if (!xdp_prog)
 359                 goto out;
 360
 361         offset = dpaa2_fd_get_offset(fd) - XDP_PACKET_HEADROOM;
 362         xdp_init_buff(&xdp, DPAA2_ETH_RX_BUF_RAW_SIZE - offset, &ch->xdp_rxq);
 363         xdp_prepare_buff(&xdp, vaddr + offset, XDP_PACKET_HEADROOM,
 364                          dpaa2_fd_get_len(fd), false);
 365
 366         xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
 367
 368         /* xdp.data pointer may have changed */
 369         dpaa2_fd_set_offset(fd, xdp.data - vaddr);
 370         dpaa2_fd_set_len(fd, xdp.data_end - xdp.data);
 371
 372         switch (xdp_act) {
 373         case XDP_PASS:
 374                 break;
 375         case XDP_TX:
 376                 dpaa2_eth_xdp_enqueue(priv, ch, fd, vaddr, rx_fq->flowid);
 377                 break;
 378         default:
 379                 bpf_warn_invalid_xdp_action(xdp_act);
 380                 fallthrough;
 381         case XDP_ABORTED:
 382                 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
 383                 fallthrough;
 384         case XDP_DROP:
 385                 dpaa2_eth_xdp_release_buf(priv, ch, addr);
 386                 ch->stats.xdp_drop++;
 387                 break;
 388         case XDP_REDIRECT:
 389                 dma_unmap_page(priv->net_dev->dev.parent, addr,
 390                                priv->rx_buf_size, DMA_BIDIRECTIONAL);
 391                 ch->buf_count--;
 392
 393                 /* Allow redirect use of full headroom */
 394                 xdp.data_hard_start = vaddr;
 395                 xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE;
 396
 397                 err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
 398                 if (unlikely(err))
 399                         ch->stats.xdp_drop++;
 400                 else
 401                         ch->stats.xdp_redirect++;
 402                 break;
 403         }
 404
 405         ch->xdp.res |= xdp_act;
 406 out:
 407         rcu_read_unlock();
 408         return xdp_act;
 409 }
 410
 411 /* Main Rx frame processing routine */
 412 static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
 413                          struct dpaa2_eth_channel *ch,
 414                          const struct dpaa2_fd *fd,
 415                          struct dpaa2_eth_fq *fq)
 416 {
 417         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 418         u8 fd_format = dpaa2_fd_get_format(fd);
 419         void *vaddr;
 420         struct sk_buff *skb;
 421         struct rtnl_link_stats64 *percpu_stats;
 422         struct dpaa2_eth_drv_stats *percpu_extras;
 423         struct device *dev = priv->net_dev->dev.parent;
 424         struct dpaa2_fas *fas;
 425         void *buf_data;
 426         u32 status = 0;
 427         u32 xdp_act;
 428
 429         /* Tracing point */
 430         trace_dpaa2_rx_fd(priv->net_dev, fd);
 431
 432         vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
 433         dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
 434                                 DMA_BIDIRECTIONAL);
 435
 436         fas = dpaa2_get_fas(vaddr, false);
 437         prefetch(fas);
 438         buf_data = vaddr + dpaa2_fd_get_offset(fd);
 439         prefetch(buf_data);
 440
 441         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 442         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 443
 444         if (fd_format == dpaa2_fd_single) {
 445                 xdp_act = dpaa2_eth_run_xdp(priv, ch, fq, (struct dpaa2_fd *)fd, vaddr);
 446                 if (xdp_act != XDP_PASS) {
 447                         percpu_stats->rx_packets++;
 448                         percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
 449                         return;
 450                 }
 451
 452                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 453                                DMA_BIDIRECTIONAL);
 454                 skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr);
 455         } else if (fd_format == dpaa2_fd_sg) {
 456                 WARN_ON(priv->xdp_prog);
 457
 458                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 459                                DMA_BIDIRECTIONAL);
 460                 skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data);
 461                 free_pages((unsigned long)vaddr, 0);
 462                 percpu_extras->rx_sg_frames++;
 463                 percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
 464         } else {
 465                 /* We don't support any other format */
 466                 goto err_frame_format;
 467         }
 468
 469         if (unlikely(!skb))
 470                 goto err_build_skb;
 471
 472         prefetch(skb->data);
 473
 474         /* Get the timestamp value */
 475         if (priv->rx_tstamp) {
 476                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
 477                 __le64 *ts = dpaa2_get_ts(vaddr, false);
 478                 u64 ns;
 479
 480                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 481
 482                 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
 483                 shhwtstamps->hwtstamp = ns_to_ktime(ns);
 484         }
 485
 486         /* Check if we need to validate the L4 csum */
 487         if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
 488                 status = le32_to_cpu(fas->status);
 489                 dpaa2_eth_validate_rx_csum(priv, status, skb);
 490         }
 491
 492         skb->protocol = eth_type_trans(skb, priv->net_dev);
 493         skb_record_rx_queue(skb, fq->flowid);
 494
 495         percpu_stats->rx_packets++;
 496         percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
 497
 498         list_add_tail(&skb->list, ch->rx_list);
 499
 500         return;
 501
 502 err_build_skb:
 503         dpaa2_eth_free_rx_fd(priv, fd, vaddr);
 504 err_frame_format:
 505         percpu_stats->rx_dropped++;
 506 }
 507
 508 /* Processing of Rx frames received on the error FQ
 509  * We check and print the error bits and then free the frame
 510  */
 511 static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv,
 512                              struct dpaa2_eth_channel *ch,
 513                              const struct dpaa2_fd *fd,
 514                              struct dpaa2_eth_fq *fq __always_unused)
 515 {
 516         struct device *dev = priv->net_dev->dev.parent;
 517         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 518         u8 fd_format = dpaa2_fd_get_format(fd);
 519         struct rtnl_link_stats64 *percpu_stats;
 520         struct dpaa2_eth_trap_item *trap_item;
 521         struct dpaa2_fapr *fapr;
 522         struct sk_buff *skb;
 523         void *buf_data;
 524         void *vaddr;
 525
 526         vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
 527         dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
 528                                 DMA_BIDIRECTIONAL);
 529
 530         buf_data = vaddr + dpaa2_fd_get_offset(fd);
 531
 532         if (fd_format == dpaa2_fd_single) {
 533                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 534                                DMA_BIDIRECTIONAL);
 535                 skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr);
 536         } else if (fd_format == dpaa2_fd_sg) {
 537                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 538                                DMA_BIDIRECTIONAL);
 539                 skb = dpaa2_eth_build_frag_skb(priv, ch, buf_data);
 540                 free_pages((unsigned long)vaddr, 0);
 541         } else {
 542                 /* We don't support any other format */
 543                 dpaa2_eth_free_rx_fd(priv, fd, vaddr);
 544                 goto err_frame_format;
 545         }
 546
 547         fapr = dpaa2_get_fapr(vaddr, false);
 548         trap_item = dpaa2_eth_dl_get_trap(priv, fapr);
 549         if (trap_item)
 550                 devlink_trap_report(priv->devlink, skb, trap_item->trap_ctx,
 551                                     &priv->devlink_port, NULL);
 552         consume_skb(skb);
 553
 554 err_frame_format:
 555         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 556         percpu_stats->rx_errors++;
 557         ch->buf_count--;
 558 }
 559
 560 /* Consume all frames pull-dequeued into the store. This is the simplest way to
 561  * make sure we don't accidentally issue another volatile dequeue which would
 562  * overwrite (leak) frames already in the store.
 563  *
 564  * Observance of NAPI budget is not our concern, leaving that to the caller.
 565  */
 566 static int dpaa2_eth_consume_frames(struct dpaa2_eth_channel *ch,
 567                                     struct dpaa2_eth_fq **src)
 568 {
 569         struct dpaa2_eth_priv *priv = ch->priv;
 570         struct dpaa2_eth_fq *fq = NULL;
 571         struct dpaa2_dq *dq;
 572         const struct dpaa2_fd *fd;
 573         int cleaned = 0, retries = 0;
 574         int is_last;
 575
 576         do {
 577                 dq = dpaa2_io_store_next(ch->store, &is_last);
 578                 if (unlikely(!dq)) {
 579                         /* If we're here, we *must* have placed a
 580                          * volatile dequeue comnmand, so keep reading through
 581                          * the store until we get some sort of valid response
 582                          * token (either a valid frame or an "empty dequeue")
 583                          */
 584                         if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) {
 585                                 netdev_err_once(priv->net_dev,
 586                                                 "Unable to read a valid dequeue response\n");
 587                                 return -ETIMEDOUT;
 588                         }
 589                         continue;
 590                 }
 591
 592                 fd = dpaa2_dq_fd(dq);
 593                 fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
 594
 595                 fq->consume(priv, ch, fd, fq);
 596                 cleaned++;
 597                 retries = 0;
 598         } while (!is_last);
 599
 600         if (!cleaned)
 601                 return 0;
 602
 603         fq->stats.frames += cleaned;
 604         ch->stats.frames += cleaned;
 605
 606         /* A dequeue operation only pulls frames from a single queue
 607          * into the store. Return the frame queue as an out param.
 608          */
 609         if (src)
 610                 *src = fq;
 611
 612         return cleaned;
 613 }
 614
 615 static int dpaa2_eth_ptp_parse(struct sk_buff *skb,
 616                                u8 *msgtype, u8 *twostep, u8 *udp,
 617                                u16 *correction_offset,
 618                                u16 *origintimestamp_offset)
 619 {
 620         unsigned int ptp_class;
 621         struct ptp_header *hdr;
 622         unsigned int type;
 623         u8 *base;
 624
 625         ptp_class = ptp_classify_raw(skb);
 626         if (ptp_class == PTP_CLASS_NONE)
 627                 return -EINVAL;
 628
 629         hdr = ptp_parse_header(skb, ptp_class);
 630         if (!hdr)
 631                 return -EINVAL;
 632
 633         *msgtype = ptp_get_msgtype(hdr, ptp_class);
 634         *twostep = hdr->flag_field[0] & 0x2;
 635
 636         type = ptp_class & PTP_CLASS_PMASK;
 637         if (type == PTP_CLASS_IPV4 ||
 638             type == PTP_CLASS_IPV6)
 639                 *udp = 1;
 640         else
 641                 *udp = 0;
 642
 643         base = skb_mac_header(skb);
 644         *correction_offset = (u8 *)&hdr->correction - base;
 645         *origintimestamp_offset = (u8 *)hdr + sizeof(struct ptp_header) - base;
 646
 647         return 0;
 648 }
 649
 650 /* Configure the egress frame annotation for timestamp update */
 651 static void dpaa2_eth_enable_tx_tstamp(struct dpaa2_eth_priv *priv,
 652                                        struct dpaa2_fd *fd,
 653                                        void *buf_start,
 654                                        struct sk_buff *skb)
 655 {
 656         struct ptp_tstamp origin_timestamp;
 657         struct dpni_single_step_cfg cfg;
 658         u8 msgtype, twostep, udp;
 659         struct dpaa2_faead *faead;
 660         struct dpaa2_fas *fas;
 661         struct timespec64 ts;
 662         u16 offset1, offset2;
 663         u32 ctrl, frc;
 664         __le64 *ns;
 665         u8 *data;
 666
 667         /* Mark the egress frame annotation area as valid */
 668         frc = dpaa2_fd_get_frc(fd);
 669         dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
 670
 671         /* Set hardware annotation size */
 672         ctrl = dpaa2_fd_get_ctrl(fd);
 673         dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
 674
 675         /* enable UPD (update prepanded data) bit in FAEAD field of
 676          * hardware frame annotation area
 677          */
 678         ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
 679         faead = dpaa2_get_faead(buf_start, true);
 680         faead->ctrl = cpu_to_le32(ctrl);
 681
 682         if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
 683                 if (dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp,
 684                                         &offset1, &offset2) ||
 685                     msgtype != PTP_MSGTYPE_SYNC || twostep) {
 686                         WARN_ONCE(1, "Bad packet for one-step timestamping\n");
 687                         return;
 688                 }
 689
 690                 /* Mark the frame annotation status as valid */
 691                 frc = dpaa2_fd_get_frc(fd);
 692                 dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FASV);
 693
 694                 /* Mark the PTP flag for one step timestamping */
 695                 fas = dpaa2_get_fas(buf_start, true);
 696                 fas->status = cpu_to_le32(DPAA2_FAS_PTP);
 697
 698                 dpaa2_ptp->caps.gettime64(&dpaa2_ptp->caps, &ts);
 699                 ns = dpaa2_get_ts(buf_start, true);
 700                 *ns = cpu_to_le64(timespec64_to_ns(&ts) /
 701                                   DPAA2_PTP_CLK_PERIOD_NS);
 702
 703                 /* Update current time to PTP message originTimestamp field */
 704                 ns_to_ptp_tstamp(&origin_timestamp, le64_to_cpup(ns));
 705                 data = skb_mac_header(skb);
 706                 *(__be16 *)(data + offset2) = htons(origin_timestamp.sec_msb);
 707                 *(__be32 *)(data + offset2 + 2) =
 708                         htonl(origin_timestamp.sec_lsb);
 709                 *(__be32 *)(data + offset2 + 6) = htonl(origin_timestamp.nsec);
 710
 711                 cfg.en = 1;
 712                 cfg.ch_update = udp;
 713                 cfg.offset = offset1;
 714                 cfg.peer_delay = 0;
 715
 716                 if (dpni_set_single_step_cfg(priv->mc_io, 0, priv->mc_token,
 717                                              &cfg))
 718                         WARN_ONCE(1, "Failed to set single step register");
 719         }
 720 }
 721
 722 /* Create a frame descriptor based on a fragmented skb */
 723 static int dpaa2_eth_build_sg_fd(struct dpaa2_eth_priv *priv,
 724                                  struct sk_buff *skb,
 725                                  struct dpaa2_fd *fd,
 726                                  void **swa_addr)
 727 {
 728         struct device *dev = priv->net_dev->dev.parent;
 729         void *sgt_buf = NULL;
 730         dma_addr_t addr;
 731         int nr_frags = skb_shinfo(skb)->nr_frags;
 732         struct dpaa2_sg_entry *sgt;
 733         int i, err;
 734         int sgt_buf_size;
 735         struct scatterlist *scl, *crt_scl;
 736         int num_sg;
 737         int num_dma_bufs;
 738         struct dpaa2_eth_swa *swa;
 739
 740         /* Create and map scatterlist.
 741          * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
 742          * to go beyond nr_frags+1.
 743          * Note: We don't support chained scatterlists
 744          */
 745         if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
 746                 return -EINVAL;
 747
 748         scl = kmalloc_array(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
 749         if (unlikely(!scl))
 750                 return -ENOMEM;
 751
 752         sg_init_table(scl, nr_frags + 1);
 753         num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
 754         if (unlikely(num_sg < 0)) {
 755                 err = -ENOMEM;
 756                 goto dma_map_sg_failed;
 757         }
 758         num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
 759         if (unlikely(!num_dma_bufs)) {
 760                 err = -ENOMEM;
 761                 goto dma_map_sg_failed;
 762         }
 763
 764         /* Prepare the HW SGT structure */
 765         sgt_buf_size = priv->tx_data_offset +
 766                        sizeof(struct dpaa2_sg_entry) *  num_dma_bufs;
 767         sgt_buf = napi_alloc_frag(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN);
 768         if (unlikely(!sgt_buf)) {
 769                 err = -ENOMEM;
 770                 goto sgt_buf_alloc_failed;
 771         }
 772         sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
 773         memset(sgt_buf, 0, sgt_buf_size);
 774
 775         sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
 776
 777         /* Fill in the HW SGT structure.
 778          *
 779          * sgt_buf is zeroed out, so the following fields are implicit
 780          * in all sgt entries:
 781          *   - offset is 0
 782          *   - format is 'dpaa2_sg_single'
 783          */
 784         for_each_sg(scl, crt_scl, num_dma_bufs, i) {
 785                 dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
 786                 dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
 787         }
 788         dpaa2_sg_set_final(&sgt[i - 1], true);
 789
 790         /* Store the skb backpointer in the SGT buffer.
 791          * Fit the scatterlist and the number of buffers alongside the
 792          * skb backpointer in the software annotation area. We'll need
 793          * all of them on Tx Conf.
 794          */
 795         *swa_addr = (void *)sgt_buf;
 796         swa = (struct dpaa2_eth_swa *)sgt_buf;
 797         swa->type = DPAA2_ETH_SWA_SG;
 798         swa->sg.skb = skb;
 799         swa->sg.scl = scl;
 800         swa->sg.num_sg = num_sg;
 801         swa->sg.sgt_size = sgt_buf_size;
 802
 803         /* Separately map the SGT buffer */
 804         addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
 805         if (unlikely(dma_mapping_error(dev, addr))) {
 806                 err = -ENOMEM;
 807                 goto dma_map_single_failed;
 808         }
 809         dpaa2_fd_set_offset(fd, priv->tx_data_offset);
 810         dpaa2_fd_set_format(fd, dpaa2_fd_sg);
 811         dpaa2_fd_set_addr(fd, addr);
 812         dpaa2_fd_set_len(fd, skb->len);
 813         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 814
 815         return 0;
 816
 817 dma_map_single_failed:
 818         skb_free_frag(sgt_buf);
 819 sgt_buf_alloc_failed:
 820         dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
 821 dma_map_sg_failed:
 822         kfree(scl);
 823         return err;
 824 }
 825
 826 /* Create a SG frame descriptor based on a linear skb.
 827  *
 828  * This function is used on the Tx path when the skb headroom is not large
 829  * enough for the HW requirements, thus instead of realloc-ing the skb we
 830  * create a SG frame descriptor with only one entry.
 831  */
 832 static int dpaa2_eth_build_sg_fd_single_buf(struct dpaa2_eth_priv *priv,
 833                                             struct sk_buff *skb,
 834                                             struct dpaa2_fd *fd,
 835                                             void **swa_addr)
 836 {
 837         struct device *dev = priv->net_dev->dev.parent;
 838         struct dpaa2_eth_sgt_cache *sgt_cache;
 839         struct dpaa2_sg_entry *sgt;
 840         struct dpaa2_eth_swa *swa;
 841         dma_addr_t addr, sgt_addr;
 842         void *sgt_buf = NULL;
 843         int sgt_buf_size;
 844         int err;
 845
 846         /* Prepare the HW SGT structure */
 847         sgt_cache = this_cpu_ptr(priv->sgt_cache);
 848         sgt_buf_size = priv->tx_data_offset + sizeof(struct dpaa2_sg_entry);
 849
 850         if (sgt_cache->count == 0)
 851                 sgt_buf = kzalloc(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN,
 852                                   GFP_ATOMIC);
 853         else
 854                 sgt_buf = sgt_cache->buf[--sgt_cache->count];
 855         if (unlikely(!sgt_buf))
 856                 return -ENOMEM;
 857
 858         sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
 859         sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
 860
 861         addr = dma_map_single(dev, skb->data, skb->len, DMA_BIDIRECTIONAL);
 862         if (unlikely(dma_mapping_error(dev, addr))) {
 863                 err = -ENOMEM;
 864                 goto data_map_failed;
 865         }
 866
 867         /* Fill in the HW SGT structure */
 868         dpaa2_sg_set_addr(sgt, addr);
 869         dpaa2_sg_set_len(sgt, skb->len);
 870         dpaa2_sg_set_final(sgt, true);
 871
 872         /* Store the skb backpointer in the SGT buffer */
 873         *swa_addr = (void *)sgt_buf;
 874         swa = (struct dpaa2_eth_swa *)sgt_buf;
 875         swa->type = DPAA2_ETH_SWA_SINGLE;
 876         swa->single.skb = skb;
 877         swa->single.sgt_size = sgt_buf_size;
 878
 879         /* Separately map the SGT buffer */
 880         sgt_addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
 881         if (unlikely(dma_mapping_error(dev, sgt_addr))) {
 882                 err = -ENOMEM;
 883                 goto sgt_map_failed;
 884         }
 885
 886         dpaa2_fd_set_offset(fd, priv->tx_data_offset);
 887         dpaa2_fd_set_format(fd, dpaa2_fd_sg);
 888         dpaa2_fd_set_addr(fd, sgt_addr);
 889         dpaa2_fd_set_len(fd, skb->len);
 890         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 891
 892         return 0;
 893
 894 sgt_map_failed:
 895         dma_unmap_single(dev, addr, skb->len, DMA_BIDIRECTIONAL);
 896 data_map_failed:
 897         if (sgt_cache->count >= DPAA2_ETH_SGT_CACHE_SIZE)
 898                 kfree(sgt_buf);
 899         else
 900                 sgt_cache->buf[sgt_cache->count++] = sgt_buf;
 901
 902         return err;
 903 }
 904
 905 /* Create a frame descriptor based on a linear skb */
 906 static int dpaa2_eth_build_single_fd(struct dpaa2_eth_priv *priv,
 907                                      struct sk_buff *skb,
 908                                      struct dpaa2_fd *fd,
 909                                      void **swa_addr)
 910 {
 911         struct device *dev = priv->net_dev->dev.parent;
 912         u8 *buffer_start, *aligned_start;
 913         struct dpaa2_eth_swa *swa;
 914         dma_addr_t addr;
 915
 916         buffer_start = skb->data - dpaa2_eth_needed_headroom(skb);
 917
 918         /* If there's enough room to align the FD address, do it.
 919          * It will help hardware optimize accesses.
 920          */
 921         aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
 922                                   DPAA2_ETH_TX_BUF_ALIGN);
 923         if (aligned_start >= skb->head)
 924                 buffer_start = aligned_start;
 925
 926         /* Store a backpointer to the skb at the beginning of the buffer
 927          * (in the private data area) such that we can release it
 928          * on Tx confirm
 929          */
 930         *swa_addr = (void *)buffer_start;
 931         swa = (struct dpaa2_eth_swa *)buffer_start;
 932         swa->type = DPAA2_ETH_SWA_SINGLE;
 933         swa->single.skb = skb;
 934
 935         addr = dma_map_single(dev, buffer_start,
 936                               skb_tail_pointer(skb) - buffer_start,
 937                               DMA_BIDIRECTIONAL);
 938         if (unlikely(dma_mapping_error(dev, addr)))
 939                 return -ENOMEM;
 940
 941         dpaa2_fd_set_addr(fd, addr);
 942         dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
 943         dpaa2_fd_set_len(fd, skb->len);
 944         dpaa2_fd_set_format(fd, dpaa2_fd_single);
 945         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 946
 947         return 0;
 948 }
 949
 950 /* FD freeing routine on the Tx path
 951  *
 952  * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb
 953  * back-pointed to is also freed.
 954  * This can be called either from dpaa2_eth_tx_conf() or on the error path of
 955  * dpaa2_eth_tx().
 956  */
 957 static void dpaa2_eth_free_tx_fd(struct dpaa2_eth_priv *priv,
 958                                  struct dpaa2_eth_fq *fq,
 959                                  const struct dpaa2_fd *fd, bool in_napi)
 960 {
 961         struct device *dev = priv->net_dev->dev.parent;
 962         dma_addr_t fd_addr, sg_addr;
 963         struct sk_buff *skb = NULL;
 964         unsigned char *buffer_start;
 965         struct dpaa2_eth_swa *swa;
 966         u8 fd_format = dpaa2_fd_get_format(fd);
 967         u32 fd_len = dpaa2_fd_get_len(fd);
 968
 969         struct dpaa2_eth_sgt_cache *sgt_cache;
 970         struct dpaa2_sg_entry *sgt;
 971
 972         fd_addr = dpaa2_fd_get_addr(fd);
 973         buffer_start = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
 974         swa = (struct dpaa2_eth_swa *)buffer_start;
 975
 976         if (fd_format == dpaa2_fd_single) {
 977                 if (swa->type == DPAA2_ETH_SWA_SINGLE) {
 978                         skb = swa->single.skb;
 979                         /* Accessing the skb buffer is safe before dma unmap,
 980                          * because we didn't map the actual skb shell.
 981                          */
 982                         dma_unmap_single(dev, fd_addr,
 983                                          skb_tail_pointer(skb) - buffer_start,
 984                                          DMA_BIDIRECTIONAL);
 985                 } else {
 986                         WARN_ONCE(swa->type != DPAA2_ETH_SWA_XDP, "Wrong SWA type");
 987                         dma_unmap_single(dev, fd_addr, swa->xdp.dma_size,
 988                                          DMA_BIDIRECTIONAL);
 989                 }
 990         } else if (fd_format == dpaa2_fd_sg) {
 991                 if (swa->type == DPAA2_ETH_SWA_SG) {
 992                         skb = swa->sg.skb;
 993
 994                         /* Unmap the scatterlist */
 995                         dma_unmap_sg(dev, swa->sg.scl, swa->sg.num_sg,
 996                                      DMA_BIDIRECTIONAL);
 997                         kfree(swa->sg.scl);
 998
 999                         /* Unmap the SGT buffer */
1000                         dma_unmap_single(dev, fd_addr, swa->sg.sgt_size,
1001                                          DMA_BIDIRECTIONAL);
1002                 } else {
1003                         skb = swa->single.skb;
1004
1005                         /* Unmap the SGT Buffer */
1006                         dma_unmap_single(dev, fd_addr, swa->single.sgt_size,
1007                                          DMA_BIDIRECTIONAL);
1008
1009                         sgt = (struct dpaa2_sg_entry *)(buffer_start +
1010                                                         priv->tx_data_offset);
1011                         sg_addr = dpaa2_sg_get_addr(sgt);
1012                         dma_unmap_single(dev, sg_addr, skb->len, DMA_BIDIRECTIONAL);
1013                 }
1014         } else {
1015                 netdev_dbg(priv->net_dev, "Invalid FD format\n");
1016                 return;
1017         }
1018
1019         if (swa->type != DPAA2_ETH_SWA_XDP && in_napi) {
1020                 fq->dq_frames++;
1021                 fq->dq_bytes += fd_len;
1022         }
1023
1024         if (swa->type == DPAA2_ETH_SWA_XDP) {
1025                 xdp_return_frame(swa->xdp.xdpf);
1026                 return;
1027         }
1028
1029         /* Get the timestamp value */
1030         if (skb->cb[0] == TX_TSTAMP) {
1031                 struct skb_shared_hwtstamps shhwtstamps;
1032                 __le64 *ts = dpaa2_get_ts(buffer_start, true);
1033                 u64 ns;
1034
1035                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1036
1037                 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
1038                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
1039                 skb_tstamp_tx(skb, &shhwtstamps);
1040         } else if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
1041                 mutex_unlock(&priv->onestep_tstamp_lock);
1042         }
1043
1044         /* Free SGT buffer allocated on tx */
1045         if (fd_format != dpaa2_fd_single) {
1046                 sgt_cache = this_cpu_ptr(priv->sgt_cache);
1047                 if (swa->type == DPAA2_ETH_SWA_SG) {
1048                         skb_free_frag(buffer_start);
1049                 } else {
1050                         if (sgt_cache->count >= DPAA2_ETH_SGT_CACHE_SIZE)
1051                                 kfree(buffer_start);
1052                         else
1053                                 sgt_cache->buf[sgt_cache->count++] = buffer_start;
1054                 }
1055         }
1056
1057         /* Move on with skb release */
1058         napi_consume_skb(skb, in_napi);
1059 }
1060
1061 static netdev_tx_t __dpaa2_eth_tx(struct sk_buff *skb,
1062                                   struct net_device *net_dev)
1063 {
1064         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1065         struct dpaa2_fd fd;
1066         struct rtnl_link_stats64 *percpu_stats;
1067         struct dpaa2_eth_drv_stats *percpu_extras;
1068         struct dpaa2_eth_fq *fq;
1069         struct netdev_queue *nq;
1070         u16 queue_mapping;
1071         unsigned int needed_headroom;
1072         u32 fd_len;
1073         u8 prio = 0;
1074         int err, i;
1075         void *swa;
1076
1077         percpu_stats = this_cpu_ptr(priv->percpu_stats);
1078         percpu_extras = this_cpu_ptr(priv->percpu_extras);
1079
1080         needed_headroom = dpaa2_eth_needed_headroom(skb);
1081
1082         /* We'll be holding a back-reference to the skb until Tx Confirmation;
1083          * we don't want that overwritten by a concurrent Tx with a cloned skb.
1084          */
1085         skb = skb_unshare(skb, GFP_ATOMIC);
1086         if (unlikely(!skb)) {
1087                 /* skb_unshare() has already freed the skb */
1088                 percpu_stats->tx_dropped++;
1089                 return NETDEV_TX_OK;
1090         }
1091
1092         /* Setup the FD fields */
1093         memset(&fd, 0, sizeof(fd));
1094
1095         if (skb_is_nonlinear(skb)) {
1096                 err = dpaa2_eth_build_sg_fd(priv, skb, &fd, &swa);
1097                 percpu_extras->tx_sg_frames++;
1098                 percpu_extras->tx_sg_bytes += skb->len;
1099         } else if (skb_headroom(skb) < needed_headroom) {
1100                 err = dpaa2_eth_build_sg_fd_single_buf(priv, skb, &fd, &swa);
1101                 percpu_extras->tx_sg_frames++;
1102                 percpu_extras->tx_sg_bytes += skb->len;
1103                 percpu_extras->tx_converted_sg_frames++;
1104                 percpu_extras->tx_converted_sg_bytes += skb->len;
1105         } else {
1106                 err = dpaa2_eth_build_single_fd(priv, skb, &fd, &swa);
1107         }
1108
1109         if (unlikely(err)) {
1110                 percpu_stats->tx_dropped++;
1111                 goto err_build_fd;
1112         }
1113
1114         if (skb->cb[0])
1115                 dpaa2_eth_enable_tx_tstamp(priv, &fd, swa, skb);
1116
1117         /* Tracing point */
1118         trace_dpaa2_tx_fd(net_dev, &fd);
1119
1120         /* TxConf FQ selection relies on queue id from the stack.
1121          * In case of a forwarded frame from another DPNI interface, we choose
1122          * a queue affined to the same core that processed the Rx frame
1123          */
1124         queue_mapping = skb_get_queue_mapping(skb);
1125
1126         if (net_dev->num_tc) {
1127                 prio = netdev_txq_to_tc(net_dev, queue_mapping);
1128                 /* Hardware interprets priority level 0 as being the highest,
1129                  * so we need to do a reverse mapping to the netdev tc index
1130                  */
1131                 prio = net_dev->num_tc - prio - 1;
1132                 /* We have only one FQ array entry for all Tx hardware queues
1133                  * with the same flow id (but different priority levels)
1134                  */
1135                 queue_mapping %= dpaa2_eth_queue_count(priv);
1136         }
1137         fq = &priv->fq[queue_mapping];
1138
1139         fd_len = dpaa2_fd_get_len(&fd);
1140         nq = netdev_get_tx_queue(net_dev, queue_mapping);
1141         netdev_tx_sent_queue(nq, fd_len);
1142
1143         /* Everything that happens after this enqueues might race with
1144          * the Tx confirmation callback for this frame
1145          */
1146         for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
1147                 err = priv->enqueue(priv, fq, &fd, prio, 1, NULL);
1148                 if (err != -EBUSY)
1149                         break;
1150         }
1151         percpu_extras->tx_portal_busy += i;
1152         if (unlikely(err < 0)) {
1153                 percpu_stats->tx_errors++;
1154                 /* Clean up everything, including freeing the skb */
1155                 dpaa2_eth_free_tx_fd(priv, fq, &fd, false);
1156                 netdev_tx_completed_queue(nq, 1, fd_len);
1157         } else {
1158                 percpu_stats->tx_packets++;
1159                 percpu_stats->tx_bytes += fd_len;
1160         }
1161
1162         return NETDEV_TX_OK;
1163
1164 err_build_fd:
1165         dev_kfree_skb(skb);
1166
1167         return NETDEV_TX_OK;
1168 }
1169
1170 static void dpaa2_eth_tx_onestep_tstamp(struct work_struct *work)
1171 {
1172         struct dpaa2_eth_priv *priv = container_of(work, struct dpaa2_eth_priv,
1173                                                    tx_onestep_tstamp);
1174         struct sk_buff *skb;
1175
1176         while (true) {
1177                 skb = skb_dequeue(&priv->tx_skbs);
1178                 if (!skb)
1179                         return;
1180
1181                 /* Lock just before TX one-step timestamping packet,
1182                  * and release the lock in dpaa2_eth_free_tx_fd when
1183                  * confirm the packet has been sent on hardware, or
1184                  * when clean up during transmit failure.
1185                  */
1186                 mutex_lock(&priv->onestep_tstamp_lock);
1187                 __dpaa2_eth_tx(skb, priv->net_dev);
1188         }
1189 }
1190
1191 static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
1192 {
1193         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1194         u8 msgtype, twostep, udp;
1195         u16 offset1, offset2;
1196
1197         /* Utilize skb->cb[0] for timestamping request per skb */
1198         skb->cb[0] = 0;
1199
1200         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && dpaa2_ptp) {
1201                 if (priv->tx_tstamp_type == HWTSTAMP_TX_ON)
1202                         skb->cb[0] = TX_TSTAMP;
1203                 else if (priv->tx_tstamp_type == HWTSTAMP_TX_ONESTEP_SYNC)
1204                         skb->cb[0] = TX_TSTAMP_ONESTEP_SYNC;
1205         }
1206
1207         /* TX for one-step timestamping PTP Sync packet */
1208         if (skb->cb[0] == TX_TSTAMP_ONESTEP_SYNC) {
1209                 if (!dpaa2_eth_ptp_parse(skb, &msgtype, &twostep, &udp,
1210                                          &offset1, &offset2))
1211                         if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) {
1212                                 skb_queue_tail(&priv->tx_skbs, skb);
1213                                 queue_work(priv->dpaa2_ptp_wq,
1214                                            &priv->tx_onestep_tstamp);
1215                                 return NETDEV_TX_OK;
1216                         }
1217                 /* Use two-step timestamping if not one-step timestamping
1218                  * PTP Sync packet
1219                  */
1220                 skb->cb[0] = TX_TSTAMP;
1221         }
1222
1223         /* TX for other packets */
1224         return __dpaa2_eth_tx(skb, net_dev);
1225 }
1226
1227 /* Tx confirmation frame processing routine */
1228 static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
1229                               struct dpaa2_eth_channel *ch __always_unused,
1230                               const struct dpaa2_fd *fd,
1231                               struct dpaa2_eth_fq *fq)
1232 {
1233         struct rtnl_link_stats64 *percpu_stats;
1234         struct dpaa2_eth_drv_stats *percpu_extras;
1235         u32 fd_len = dpaa2_fd_get_len(fd);
1236         u32 fd_errors;
1237
1238         /* Tracing point */
1239         trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
1240
1241         percpu_extras = this_cpu_ptr(priv->percpu_extras);
1242         percpu_extras->tx_conf_frames++;
1243         percpu_extras->tx_conf_bytes += fd_len;
1244
1245         /* Check frame errors in the FD field */
1246         fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
1247         dpaa2_eth_free_tx_fd(priv, fq, fd, true);
1248
1249         if (likely(!fd_errors))
1250                 return;
1251
1252         if (net_ratelimit())
1253                 netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
1254                            fd_errors);
1255
1256         percpu_stats = this_cpu_ptr(priv->percpu_stats);
1257         /* Tx-conf logically pertains to the egress path. */
1258         percpu_stats->tx_errors++;
1259 }
1260
1261 static int dpaa2_eth_set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
1262 {
1263         int err;
1264
1265         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1266                                DPNI_OFF_RX_L3_CSUM, enable);
1267         if (err) {
1268                 netdev_err(priv->net_dev,
1269                            "dpni_set_offload(RX_L3_CSUM) failed\n");
1270                 return err;
1271         }
1272
1273         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1274                                DPNI_OFF_RX_L4_CSUM, enable);
1275         if (err) {
1276                 netdev_err(priv->net_dev,
1277                            "dpni_set_offload(RX_L4_CSUM) failed\n");
1278                 return err;
1279         }
1280
1281         return 0;
1282 }
1283
1284 static int dpaa2_eth_set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
1285 {
1286         int err;
1287
1288         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1289                                DPNI_OFF_TX_L3_CSUM, enable);
1290         if (err) {
1291                 netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n");
1292                 return err;
1293         }
1294
1295         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
1296                                DPNI_OFF_TX_L4_CSUM, enable);
1297         if (err) {
1298                 netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n");
1299                 return err;
1300         }
1301
1302         return 0;
1303 }
1304
1305 /* Perform a single release command to add buffers
1306  * to the specified buffer pool
1307  */
1308 static int dpaa2_eth_add_bufs(struct dpaa2_eth_priv *priv,
1309                               struct dpaa2_eth_channel *ch, u16 bpid)
1310 {
1311         struct device *dev = priv->net_dev->dev.parent;
1312         u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1313         struct page *page;
1314         dma_addr_t addr;
1315         int retries = 0;
1316         int i, err;
1317
1318         for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
1319                 /* Allocate buffer visible to WRIOP + skb shared info +
1320                  * alignment padding
1321                  */
1322                 /* allocate one page for each Rx buffer. WRIOP sees
1323                  * the entire page except for a tailroom reserved for
1324                  * skb shared info
1325                  */
1326                 page = dev_alloc_pages(0);
1327                 if (!page)
1328                         goto err_alloc;
1329
1330                 addr = dma_map_page(dev, page, 0, priv->rx_buf_size,
1331                                     DMA_BIDIRECTIONAL);
1332                 if (unlikely(dma_mapping_error(dev, addr)))
1333                         goto err_map;
1334
1335                 buf_array[i] = addr;
1336
1337                 /* tracing point */
1338                 trace_dpaa2_eth_buf_seed(priv->net_dev,
1339                                          page, DPAA2_ETH_RX_BUF_RAW_SIZE,
1340                                          addr, priv->rx_buf_size,
1341                                          bpid);
1342         }
1343
1344 release_bufs:
1345         /* In case the portal is busy, retry until successful */
1346         while ((err = dpaa2_io_service_release(ch->dpio, bpid,
1347                                                buf_array, i)) == -EBUSY) {
1348                 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
1349                         break;
1350                 cpu_relax();
1351         }
1352
1353         /* If release command failed, clean up and bail out;
1354          * not much else we can do about it
1355          */
1356         if (err) {
1357                 dpaa2_eth_free_bufs(priv, buf_array, i);
1358                 return 0;
1359         }
1360
1361         return i;
1362
1363 err_map:
1364         __free_pages(page, 0);
1365 err_alloc:
1366         /* If we managed to allocate at least some buffers,
1367          * release them to hardware
1368          */
1369         if (i)
1370                 goto release_bufs;
1371
1372         return 0;
1373 }
1374
1375 static int dpaa2_eth_seed_pool(struct dpaa2_eth_priv *priv, u16 bpid)
1376 {
1377         int i, j;
1378         int new_count;
1379
1380         for (j = 0; j < priv->num_channels; j++) {
1381                 for (i = 0; i < DPAA2_ETH_NUM_BUFS;
1382                      i += DPAA2_ETH_BUFS_PER_CMD) {
1383                         new_count = dpaa2_eth_add_bufs(priv, priv->channel[j], bpid);
1384                         priv->channel[j]->buf_count += new_count;
1385
1386                         if (new_count < DPAA2_ETH_BUFS_PER_CMD) {
1387                                 return -ENOMEM;
1388                         }
1389                 }
1390         }
1391
1392         return 0;
1393 }
1394
1395 /*
1396  * Drain the specified number of buffers from the DPNI's private buffer pool.
1397  * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD
1398  */
1399 static void dpaa2_eth_drain_bufs(struct dpaa2_eth_priv *priv, int count)
1400 {
1401         u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1402         int retries = 0;
1403         int ret;
1404
1405         do {
1406                 ret = dpaa2_io_service_acquire(NULL, priv->bpid,
1407                                                buf_array, count);
1408                 if (ret < 0) {
1409                         if (ret == -EBUSY &&
1410                             retries++ < DPAA2_ETH_SWP_BUSY_RETRIES)
1411                                 continue;
1412                         netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
1413                         return;
1414                 }
1415                 dpaa2_eth_free_bufs(priv, buf_array, ret);
1416                 retries = 0;
1417         } while (ret);
1418 }
1419
1420 static void dpaa2_eth_drain_pool(struct dpaa2_eth_priv *priv)
1421 {
1422         int i;
1423
1424         dpaa2_eth_drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD);
1425         dpaa2_eth_drain_bufs(priv, 1);
1426
1427         for (i = 0; i < priv->num_channels; i++)
1428                 priv->channel[i]->buf_count = 0;
1429 }
1430
1431 /* Function is called from softirq context only, so we don't need to guard
1432  * the access to percpu count
1433  */
1434 static int dpaa2_eth_refill_pool(struct dpaa2_eth_priv *priv,
1435                                  struct dpaa2_eth_channel *ch,
1436                                  u16 bpid)
1437 {
1438         int new_count;
1439
1440         if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH))
1441                 return 0;
1442
1443         do {
1444                 new_count = dpaa2_eth_add_bufs(priv, ch, bpid);
1445                 if (unlikely(!new_count)) {
1446                         /* Out of memory; abort for now, we'll try later on */
1447                         break;
1448                 }
1449                 ch->buf_count += new_count;
1450         } while (ch->buf_count < DPAA2_ETH_NUM_BUFS);
1451
1452         if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS))
1453                 return -ENOMEM;
1454
1455         return 0;
1456 }
1457
1458 static void dpaa2_eth_sgt_cache_drain(struct dpaa2_eth_priv *priv)
1459 {
1460         struct dpaa2_eth_sgt_cache *sgt_cache;
1461         u16 count;
1462         int k, i;
1463
1464         for_each_possible_cpu(k) {
1465                 sgt_cache = per_cpu_ptr(priv->sgt_cache, k);
1466                 count = sgt_cache->count;
1467
1468                 for (i = 0; i < count; i++)
1469                         kfree(sgt_cache->buf[i]);
1470                 sgt_cache->count = 0;
1471         }
1472 }
1473
1474 static int dpaa2_eth_pull_channel(struct dpaa2_eth_channel *ch)
1475 {
1476         int err;
1477         int dequeues = -1;
1478
1479         /* Retry while portal is busy */
1480         do {
1481                 err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id,
1482                                                     ch->store);
1483                 dequeues++;
1484                 cpu_relax();
1485         } while (err == -EBUSY && dequeues < DPAA2_ETH_SWP_BUSY_RETRIES);
1486
1487         ch->stats.dequeue_portal_busy += dequeues;
1488         if (unlikely(err))
1489                 ch->stats.pull_err++;
1490
1491         return err;
1492 }
1493
1494 /* NAPI poll routine
1495  *
1496  * Frames are dequeued from the QMan channel associated with this NAPI context.
1497  * Rx, Tx confirmation and (if configured) Rx error frames all count
1498  * towards the NAPI budget.
1499  */
1500 static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
1501 {
1502         struct dpaa2_eth_channel *ch;
1503         struct dpaa2_eth_priv *priv;
1504         int rx_cleaned = 0, txconf_cleaned = 0;
1505         struct dpaa2_eth_fq *fq, *txc_fq = NULL;
1506         struct netdev_queue *nq;
1507         int store_cleaned, work_done;
1508         struct list_head rx_list;
1509         int retries = 0;
1510         u16 flowid;
1511         int err;
1512
1513         ch = container_of(napi, struct dpaa2_eth_channel, napi);
1514         ch->xdp.res = 0;
1515         priv = ch->priv;
1516
1517         INIT_LIST_HEAD(&rx_list);
1518         ch->rx_list = &rx_list;
1519
1520         do {
1521                 err = dpaa2_eth_pull_channel(ch);
1522                 if (unlikely(err))
1523                         break;
1524
1525                 /* Refill pool if appropriate */
1526                 dpaa2_eth_refill_pool(priv, ch, priv->bpid);
1527
1528                 store_cleaned = dpaa2_eth_consume_frames(ch, &fq);
1529                 if (store_cleaned <= 0)
1530                         break;
1531                 if (fq->type == DPAA2_RX_FQ) {
1532                         rx_cleaned += store_cleaned;
1533                         flowid = fq->flowid;
1534                 } else {
1535                         txconf_cleaned += store_cleaned;
1536                         /* We have a single Tx conf FQ on this channel */
1537                         txc_fq = fq;
1538                 }
1539
1540                 /* If we either consumed the whole NAPI budget with Rx frames
1541                  * or we reached the Tx confirmations threshold, we're done.
1542                  */
1543                 if (rx_cleaned >= budget ||
1544                     txconf_cleaned >= DPAA2_ETH_TXCONF_PER_NAPI) {
1545                         work_done = budget;
1546                         goto out;
1547                 }
1548         } while (store_cleaned);
1549
1550         /* We didn't consume the entire budget, so finish napi and
1551          * re-enable data availability notifications
1552          */
1553         napi_complete_done(napi, rx_cleaned);
1554         do {
1555                 err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx);
1556                 cpu_relax();
1557         } while (err == -EBUSY && retries++ < DPAA2_ETH_SWP_BUSY_RETRIES);
1558         WARN_ONCE(err, "CDAN notifications rearm failed on core %d",
1559                   ch->nctx.desired_cpu);
1560
1561         work_done = max(rx_cleaned, 1);
1562
1563 out:
1564         netif_receive_skb_list(ch->rx_list);
1565
1566         if (txc_fq && txc_fq->dq_frames) {
1567                 nq = netdev_get_tx_queue(priv->net_dev, txc_fq->flowid);
1568                 netdev_tx_completed_queue(nq, txc_fq->dq_frames,
1569                                           txc_fq->dq_bytes);
1570                 txc_fq->dq_frames = 0;
1571                 txc_fq->dq_bytes = 0;
1572         }
1573
1574         if (ch->xdp.res & XDP_REDIRECT)
1575                 xdp_do_flush_map();
1576         else if (rx_cleaned && ch->xdp.res & XDP_TX)
1577                 dpaa2_eth_xdp_tx_flush(priv, ch, &priv->fq[flowid]);
1578
1579         return work_done;
1580 }
1581
1582 static void dpaa2_eth_enable_ch_napi(struct dpaa2_eth_priv *priv)
1583 {
1584         struct dpaa2_eth_channel *ch;
1585         int i;
1586
1587         for (i = 0; i < priv->num_channels; i++) {
1588                 ch = priv->channel[i];
1589                 napi_enable(&ch->napi);
1590         }
1591 }
1592
1593 static void dpaa2_eth_disable_ch_napi(struct dpaa2_eth_priv *priv)
1594 {
1595         struct dpaa2_eth_channel *ch;
1596         int i;
1597
1598         for (i = 0; i < priv->num_channels; i++) {
1599                 ch = priv->channel[i];
1600                 napi_disable(&ch->napi);
1601         }
1602 }
1603
1604 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
1605                                bool tx_pause, bool pfc)
1606 {
1607         struct dpni_taildrop td = {0};
1608         struct dpaa2_eth_fq *fq;
1609         int i, err;
1610
1611         /* FQ taildrop: threshold is in bytes, per frame queue. Enabled if
1612          * flow control is disabled (as it might interfere with either the
1613          * buffer pool depletion trigger for pause frames or with the group
1614          * congestion trigger for PFC frames)
1615          */
1616         td.enable = !tx_pause;
1617         if (priv->rx_fqtd_enabled == td.enable)
1618                 goto set_cgtd;
1619
1620         td.threshold = DPAA2_ETH_FQ_TAILDROP_THRESH;
1621         td.units = DPNI_CONGESTION_UNIT_BYTES;
1622
1623         for (i = 0; i < priv->num_fqs; i++) {
1624                 fq = &priv->fq[i];
1625                 if (fq->type != DPAA2_RX_FQ)
1626                         continue;
1627                 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
1628                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
1629                                         fq->tc, fq->flowid, &td);
1630                 if (err) {
1631                         netdev_err(priv->net_dev,
1632                                    "dpni_set_taildrop(FQ) failed\n");
1633                         return;
1634                 }
1635         }
1636
1637         priv->rx_fqtd_enabled = td.enable;
1638
1639 set_cgtd:
1640         /* Congestion group taildrop: threshold is in frames, per group
1641          * of FQs belonging to the same traffic class
1642          * Enabled if general Tx pause disabled or if PFCs are enabled
1643          * (congestion group threhsold for PFC generation is lower than the
1644          * CG taildrop threshold, so it won't interfere with it; we also
1645          * want frames in non-PFC enabled traffic classes to be kept in check)
1646          */
1647         td.enable = !tx_pause || (tx_pause && pfc);
1648         if (priv->rx_cgtd_enabled == td.enable)
1649                 return;
1650
1651         td.threshold = DPAA2_ETH_CG_TAILDROP_THRESH(priv);
1652         td.units = DPNI_CONGESTION_UNIT_FRAMES;
1653         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
1654                 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
1655                                         DPNI_CP_GROUP, DPNI_QUEUE_RX,
1656                                         i, 0, &td);
1657                 if (err) {
1658                         netdev_err(priv->net_dev,
1659                                    "dpni_set_taildrop(CG) failed\n");
1660                         return;
1661                 }
1662         }
1663
1664         priv->rx_cgtd_enabled = td.enable;
1665 }
1666
1667 static int dpaa2_eth_link_state_update(struct dpaa2_eth_priv *priv)
1668 {
1669         struct dpni_link_state state = {0};
1670         bool tx_pause;
1671         int err;
1672
1673         err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
1674         if (unlikely(err)) {
1675                 netdev_err(priv->net_dev,
1676                            "dpni_get_link_state() failed\n");
1677                 return err;
1678         }
1679
1680         /* If Tx pause frame settings have changed, we need to update
1681          * Rx FQ taildrop configuration as well. We configure taildrop
1682          * only when pause frame generation is disabled.
1683          */
1684         tx_pause = dpaa2_eth_tx_pause_enabled(state.options);
1685         dpaa2_eth_set_rx_taildrop(priv, tx_pause, priv->pfc_enabled);
1686
1687         /* When we manage the MAC/PHY using phylink there is no need
1688          * to manually update the netif_carrier.
1689          */
1690         if (priv->mac)
1691                 goto out;
1692
1693         /* Chech link state; speed / duplex changes are not treated yet */
1694         if (priv->link_state.up == state.up)
1695                 goto out;
1696
1697         if (state.up) {
1698                 netif_carrier_on(priv->net_dev);
1699                 netif_tx_start_all_queues(priv->net_dev);
1700         } else {
1701                 netif_tx_stop_all_queues(priv->net_dev);
1702                 netif_carrier_off(priv->net_dev);
1703         }
1704
1705         netdev_info(priv->net_dev, "Link Event: state %s\n",
1706                     state.up ? "up" : "down");
1707
1708 out:
1709         priv->link_state = state;
1710
1711         return 0;
1712 }
1713
1714 static int dpaa2_eth_open(struct net_device *net_dev)
1715 {
1716         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1717         int err;
1718
1719         err = dpaa2_eth_seed_pool(priv, priv->bpid);
1720         if (err) {
1721                 /* Not much to do; the buffer pool, though not filled up,
1722                  * may still contain some buffers which would enable us
1723                  * to limp on.
1724                  */
1725                 netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
1726                            priv->dpbp_dev->obj_desc.id, priv->bpid);
1727         }
1728
1729         if (!priv->mac) {
1730                 /* We'll only start the txqs when the link is actually ready;
1731                  * make sure we don't race against the link up notification,
1732                  * which may come immediately after dpni_enable();
1733                  */
1734                 netif_tx_stop_all_queues(net_dev);
1735
1736                 /* Also, explicitly set carrier off, otherwise
1737                  * netif_carrier_ok() will return true and cause 'ip link show'
1738                  * to report the LOWER_UP flag, even though the link
1739                  * notification wasn't even received.
1740                  */
1741                 netif_carrier_off(net_dev);
1742         }
1743         dpaa2_eth_enable_ch_napi(priv);
1744
1745         err = dpni_enable(priv->mc_io, 0, priv->mc_token);
1746         if (err < 0) {
1747                 netdev_err(net_dev, "dpni_enable() failed\n");
1748                 goto enable_err;
1749         }
1750
1751         if (priv->mac)
1752                 phylink_start(priv->mac->phylink);
1753
1754         return 0;
1755
1756 enable_err:
1757         dpaa2_eth_disable_ch_napi(priv);
1758         dpaa2_eth_drain_pool(priv);
1759         return err;
1760 }
1761
1762 /* Total number of in-flight frames on ingress queues */
1763 static u32 dpaa2_eth_ingress_fq_count(struct dpaa2_eth_priv *priv)
1764 {
1765         struct dpaa2_eth_fq *fq;
1766         u32 fcnt = 0, bcnt = 0, total = 0;
1767         int i, err;
1768
1769         for (i = 0; i < priv->num_fqs; i++) {
1770                 fq = &priv->fq[i];
1771                 err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt);
1772                 if (err) {
1773                         netdev_warn(priv->net_dev, "query_fq_count failed");
1774                         break;
1775                 }
1776                 total += fcnt;
1777         }
1778
1779         return total;
1780 }
1781
1782 static void dpaa2_eth_wait_for_ingress_fq_empty(struct dpaa2_eth_priv *priv)
1783 {
1784         int retries = 10;
1785         u32 pending;
1786
1787         do {
1788                 pending = dpaa2_eth_ingress_fq_count(priv);
1789                 if (pending)
1790                         msleep(100);
1791         } while (pending && --retries);
1792 }
1793
1794 #define DPNI_TX_PENDING_VER_MAJOR       7
1795 #define DPNI_TX_PENDING_VER_MINOR       13
1796 static void dpaa2_eth_wait_for_egress_fq_empty(struct dpaa2_eth_priv *priv)
1797 {
1798         union dpni_statistics stats;
1799         int retries = 10;
1800         int err;
1801
1802         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_TX_PENDING_VER_MAJOR,
1803                                    DPNI_TX_PENDING_VER_MINOR) < 0)
1804                 goto out;
1805
1806         do {
1807                 err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token, 6,
1808                                           &stats);
1809                 if (err)
1810                         goto out;
1811                 if (stats.page_6.tx_pending_frames == 0)
1812                         return;
1813         } while (--retries);
1814
1815 out:
1816         msleep(500);
1817 }
1818
1819 static int dpaa2_eth_stop(struct net_device *net_dev)
1820 {
1821         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1822         int dpni_enabled = 0;
1823         int retries = 10;
1824
1825         if (!priv->mac) {
1826                 netif_tx_stop_all_queues(net_dev);
1827                 netif_carrier_off(net_dev);
1828         } else {
1829                 phylink_stop(priv->mac->phylink);
1830         }
1831
1832         /* On dpni_disable(), the MC firmware will:
1833          * - stop MAC Rx and wait for all Rx frames to be enqueued to software
1834          * - cut off WRIOP dequeues from egress FQs and wait until transmission
1835          * of all in flight Tx frames is finished (and corresponding Tx conf
1836          * frames are enqueued back to software)
1837          *
1838          * Before calling dpni_disable(), we wait for all Tx frames to arrive
1839          * on WRIOP. After it finishes, wait until all remaining frames on Rx
1840          * and Tx conf queues are consumed on NAPI poll.
1841          */
1842         dpaa2_eth_wait_for_egress_fq_empty(priv);
1843
1844         do {
1845                 dpni_disable(priv->mc_io, 0, priv->mc_token);
1846                 dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled);
1847                 if (dpni_enabled)
1848                         /* Allow the hardware some slack */
1849                         msleep(100);
1850         } while (dpni_enabled && --retries);
1851         if (!retries) {
1852                 netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
1853                 /* Must go on and disable NAPI nonetheless, so we don't crash at
1854                  * the next "ifconfig up"
1855                  */
1856         }
1857
1858         dpaa2_eth_wait_for_ingress_fq_empty(priv);
1859         dpaa2_eth_disable_ch_napi(priv);
1860
1861         /* Empty the buffer pool */
1862         dpaa2_eth_drain_pool(priv);
1863
1864         /* Empty the Scatter-Gather Buffer cache */
1865         dpaa2_eth_sgt_cache_drain(priv);
1866
1867         return 0;
1868 }
1869
1870 static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
1871 {
1872         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1873         struct device *dev = net_dev->dev.parent;
1874         int err;
1875
1876         err = eth_mac_addr(net_dev, addr);
1877         if (err < 0) {
1878                 dev_err(dev, "eth_mac_addr() failed (%d)\n", err);
1879                 return err;
1880         }
1881
1882         err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
1883                                         net_dev->dev_addr);
1884         if (err) {
1885                 dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err);
1886                 return err;
1887         }
1888
1889         return 0;
1890 }
1891
1892 /** Fill in counters maintained by the GPP driver. These may be different from
1893  * the hardware counters obtained by ethtool.
1894  */
1895 static void dpaa2_eth_get_stats(struct net_device *net_dev,
1896                                 struct rtnl_link_stats64 *stats)
1897 {
1898         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1899         struct rtnl_link_stats64 *percpu_stats;
1900         u64 *cpustats;
1901         u64 *netstats = (u64 *)stats;
1902         int i, j;
1903         int num = sizeof(struct rtnl_link_stats64) / sizeof(u64);
1904
1905         for_each_possible_cpu(i) {
1906                 percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
1907                 cpustats = (u64 *)percpu_stats;
1908                 for (j = 0; j < num; j++)
1909                         netstats[j] += cpustats[j];
1910         }
1911 }
1912
1913 /* Copy mac unicast addresses from @net_dev to @priv.
1914  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1915  */
1916 static void dpaa2_eth_add_uc_hw_addr(const struct net_device *net_dev,
1917                                      struct dpaa2_eth_priv *priv)
1918 {
1919         struct netdev_hw_addr *ha;
1920         int err;
1921
1922         netdev_for_each_uc_addr(ha, net_dev) {
1923                 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1924                                         ha->addr);
1925                 if (err)
1926                         netdev_warn(priv->net_dev,
1927                                     "Could not add ucast MAC %pM to the filtering table (err %d)\n",
1928                                     ha->addr, err);
1929         }
1930 }
1931
1932 /* Copy mac multicast addresses from @net_dev to @priv
1933  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1934  */
1935 static void dpaa2_eth_add_mc_hw_addr(const struct net_device *net_dev,
1936                                      struct dpaa2_eth_priv *priv)
1937 {
1938         struct netdev_hw_addr *ha;
1939         int err;
1940
1941         netdev_for_each_mc_addr(ha, net_dev) {
1942                 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1943                                         ha->addr);
1944                 if (err)
1945                         netdev_warn(priv->net_dev,
1946                                     "Could not add mcast MAC %pM to the filtering table (err %d)\n",
1947                                     ha->addr, err);
1948         }
1949 }
1950
1951 static void dpaa2_eth_set_rx_mode(struct net_device *net_dev)
1952 {
1953         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1954         int uc_count = netdev_uc_count(net_dev);
1955         int mc_count = netdev_mc_count(net_dev);
1956         u8 max_mac = priv->dpni_attrs.mac_filter_entries;
1957         u32 options = priv->dpni_attrs.options;
1958         u16 mc_token = priv->mc_token;
1959         struct fsl_mc_io *mc_io = priv->mc_io;
1960         int err;
1961
1962         /* Basic sanity checks; these probably indicate a misconfiguration */
1963         if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0)
1964                 netdev_info(net_dev,
1965                             "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n",
1966                             max_mac);
1967
1968         /* Force promiscuous if the uc or mc counts exceed our capabilities. */
1969         if (uc_count > max_mac) {
1970                 netdev_info(net_dev,
1971                             "Unicast addr count reached %d, max allowed is %d; forcing promisc\n",
1972                             uc_count, max_mac);
1973                 goto force_promisc;
1974         }
1975         if (mc_count + uc_count > max_mac) {
1976                 netdev_info(net_dev,
1977                             "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n",
1978                             uc_count + mc_count, max_mac);
1979                 goto force_mc_promisc;
1980         }
1981
1982         /* Adjust promisc settings due to flag combinations */
1983         if (net_dev->flags & IFF_PROMISC)
1984                 goto force_promisc;
1985         if (net_dev->flags & IFF_ALLMULTI) {
1986                 /* First, rebuild unicast filtering table. This should be done
1987                  * in promisc mode, in order to avoid frame loss while we
1988                  * progressively add entries to the table.
1989                  * We don't know whether we had been in promisc already, and
1990                  * making an MC call to find out is expensive; so set uc promisc
1991                  * nonetheless.
1992                  */
1993                 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1994                 if (err)
1995                         netdev_warn(net_dev, "Can't set uc promisc\n");
1996
1997                 /* Actual uc table reconstruction. */
1998                 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0);
1999                 if (err)
2000                         netdev_warn(net_dev, "Can't clear uc filters\n");
2001                 dpaa2_eth_add_uc_hw_addr(net_dev, priv);
2002
2003                 /* Finally, clear uc promisc and set mc promisc as requested. */
2004                 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
2005                 if (err)
2006                         netdev_warn(net_dev, "Can't clear uc promisc\n");
2007                 goto force_mc_promisc;
2008         }
2009
2010         /* Neither unicast, nor multicast promisc will be on... eventually.
2011          * For now, rebuild mac filtering tables while forcing both of them on.
2012          */
2013         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
2014         if (err)
2015                 netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err);
2016         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
2017         if (err)
2018                 netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err);
2019
2020         /* Actual mac filtering tables reconstruction */
2021         err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1);
2022         if (err)
2023                 netdev_warn(net_dev, "Can't clear mac filters\n");
2024         dpaa2_eth_add_mc_hw_addr(net_dev, priv);
2025         dpaa2_eth_add_uc_hw_addr(net_dev, priv);
2026
2027         /* Now we can clear both ucast and mcast promisc, without risking
2028          * to drop legitimate frames anymore.
2029          */
2030         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
2031         if (err)
2032                 netdev_warn(net_dev, "Can't clear ucast promisc\n");
2033         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0);
2034         if (err)
2035                 netdev_warn(net_dev, "Can't clear mcast promisc\n");
2036
2037         return;
2038
2039 force_promisc:
2040         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
2041         if (err)
2042                 netdev_warn(net_dev, "Can't set ucast promisc\n");
2043 force_mc_promisc:
2044         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
2045         if (err)
2046                 netdev_warn(net_dev, "Can't set mcast promisc\n");
2047 }
2048
2049 static int dpaa2_eth_set_features(struct net_device *net_dev,
2050                                   netdev_features_t features)
2051 {
2052         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2053         netdev_features_t changed = features ^ net_dev->features;
2054         bool enable;
2055         int err;
2056
2057         if (changed & NETIF_F_RXCSUM) {
2058                 enable = !!(features & NETIF_F_RXCSUM);
2059                 err = dpaa2_eth_set_rx_csum(priv, enable);
2060                 if (err)
2061                         return err;
2062         }
2063
2064         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2065                 enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
2066                 err = dpaa2_eth_set_tx_csum(priv, enable);
2067                 if (err)
2068                         return err;
2069         }
2070
2071         return 0;
2072 }
2073
2074 static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2075 {
2076         struct dpaa2_eth_priv *priv = netdev_priv(dev);
2077         struct hwtstamp_config config;
2078
2079         if (!dpaa2_ptp)
2080                 return -EINVAL;
2081
2082         if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
2083                 return -EFAULT;
2084
2085         switch (config.tx_type) {
2086         case HWTSTAMP_TX_OFF:
2087         case HWTSTAMP_TX_ON:
2088         case HWTSTAMP_TX_ONESTEP_SYNC:
2089                 priv->tx_tstamp_type = config.tx_type;
2090                 break;
2091         default:
2092                 return -ERANGE;
2093         }
2094
2095         if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
2096                 priv->rx_tstamp = false;
2097         } else {
2098                 priv->rx_tstamp = true;
2099                 /* TS is set for all frame types, not only those requested */
2100                 config.rx_filter = HWTSTAMP_FILTER_ALL;
2101         }
2102
2103         return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
2104                         -EFAULT : 0;
2105 }
2106
2107 static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2108 {
2109         struct dpaa2_eth_priv *priv = netdev_priv(dev);
2110
2111         if (cmd == SIOCSHWTSTAMP)
2112                 return dpaa2_eth_ts_ioctl(dev, rq, cmd);
2113
2114         if (priv->mac)
2115                 return phylink_mii_ioctl(priv->mac->phylink, rq, cmd);
2116
2117         return -EOPNOTSUPP;
2118 }
2119
2120 static bool xdp_mtu_valid(struct dpaa2_eth_priv *priv, int mtu)
2121 {
2122         int mfl, linear_mfl;
2123
2124         mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
2125         linear_mfl = priv->rx_buf_size - DPAA2_ETH_RX_HWA_SIZE -
2126                      dpaa2_eth_rx_head_room(priv) - XDP_PACKET_HEADROOM;
2127
2128         if (mfl > linear_mfl) {
2129                 netdev_warn(priv->net_dev, "Maximum MTU for XDP is %d\n",
2130                             linear_mfl - VLAN_ETH_HLEN);
2131                 return false;
2132         }
2133
2134         return true;
2135 }
2136
2137 static int dpaa2_eth_set_rx_mfl(struct dpaa2_eth_priv *priv, int mtu, bool has_xdp)
2138 {
2139         int mfl, err;
2140
2141         /* We enforce a maximum Rx frame length based on MTU only if we have
2142          * an XDP program attached (in order to avoid Rx S/G frames).
2143          * Otherwise, we accept all incoming frames as long as they are not
2144          * larger than maximum size supported in hardware
2145          */
2146         if (has_xdp)
2147                 mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
2148         else
2149                 mfl = DPAA2_ETH_MFL;
2150
2151         err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, mfl);
2152         if (err) {
2153                 netdev_err(priv->net_dev, "dpni_set_max_frame_length failed\n");
2154                 return err;
2155         }
2156
2157         return 0;
2158 }
2159
2160 static int dpaa2_eth_change_mtu(struct net_device *dev, int new_mtu)
2161 {
2162         struct dpaa2_eth_priv *priv = netdev_priv(dev);
2163         int err;
2164
2165         if (!priv->xdp_prog)
2166                 goto out;
2167
2168         if (!xdp_mtu_valid(priv, new_mtu))
2169                 return -EINVAL;
2170
2171         err = dpaa2_eth_set_rx_mfl(priv, new_mtu, true);
2172         if (err)
2173                 return err;
2174
2175 out:
2176         dev->mtu = new_mtu;
2177         return 0;
2178 }
2179
2180 static int dpaa2_eth_update_rx_buffer_headroom(struct dpaa2_eth_priv *priv, bool has_xdp)
2181 {
2182         struct dpni_buffer_layout buf_layout = {0};
2183         int err;
2184
2185         err = dpni_get_buffer_layout(priv->mc_io, 0, priv->mc_token,
2186                                      DPNI_QUEUE_RX, &buf_layout);
2187         if (err) {
2188                 netdev_err(priv->net_dev, "dpni_get_buffer_layout failed\n");
2189                 return err;
2190         }
2191
2192         /* Reserve extra headroom for XDP header size changes */
2193         buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv) +
2194                                     (has_xdp ? XDP_PACKET_HEADROOM : 0);
2195         buf_layout.options = DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM;
2196         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2197                                      DPNI_QUEUE_RX, &buf_layout);
2198         if (err) {
2199                 netdev_err(priv->net_dev, "dpni_set_buffer_layout failed\n");
2200                 return err;
2201         }
2202
2203         return 0;
2204 }
2205
2206 static int dpaa2_eth_setup_xdp(struct net_device *dev, struct bpf_prog *prog)
2207 {
2208         struct dpaa2_eth_priv *priv = netdev_priv(dev);
2209         struct dpaa2_eth_channel *ch;
2210         struct bpf_prog *old;
2211         bool up, need_update;
2212         int i, err;
2213
2214         if (prog && !xdp_mtu_valid(priv, dev->mtu))
2215                 return -EINVAL;
2216
2217         if (prog)
2218                 bpf_prog_add(prog, priv->num_channels);
2219
2220         up = netif_running(dev);
2221         need_update = (!!priv->xdp_prog != !!prog);
2222
2223         if (up)
2224                 dpaa2_eth_stop(dev);
2225
2226         /* While in xdp mode, enforce a maximum Rx frame size based on MTU.
2227          * Also, when switching between xdp/non-xdp modes we need to reconfigure
2228          * our Rx buffer layout. Buffer pool was drained on dpaa2_eth_stop,
2229          * so we are sure no old format buffers will be used from now on.
2230          */
2231         if (need_update) {
2232                 err = dpaa2_eth_set_rx_mfl(priv, dev->mtu, !!prog);
2233                 if (err)
2234                         goto out_err;
2235                 err = dpaa2_eth_update_rx_buffer_headroom(priv, !!prog);
2236                 if (err)
2237                         goto out_err;
2238         }
2239
2240         old = xchg(&priv->xdp_prog, prog);
2241         if (old)
2242                 bpf_prog_put(old);
2243
2244         for (i = 0; i < priv->num_channels; i++) {
2245                 ch = priv->channel[i];
2246                 old = xchg(&ch->xdp.prog, prog);
2247                 if (old)
2248                         bpf_prog_put(old);
2249         }
2250
2251         if (up) {
2252                 err = dpaa2_eth_open(dev);
2253                 if (err)
2254                         return err;
2255         }
2256
2257         return 0;
2258
2259 out_err:
2260         if (prog)
2261                 bpf_prog_sub(prog, priv->num_channels);
2262         if (up)
2263                 dpaa2_eth_open(dev);
2264
2265         return err;
2266 }
2267
2268 static int dpaa2_eth_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2269 {
2270         switch (xdp->command) {
2271         case XDP_SETUP_PROG:
2272                 return dpaa2_eth_setup_xdp(dev, xdp->prog);
2273         default:
2274                 return -EINVAL;
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int dpaa2_eth_xdp_create_fd(struct net_device *net_dev,
2281                                    struct xdp_frame *xdpf,
2282                                    struct dpaa2_fd *fd)
2283 {
2284         struct device *dev = net_dev->dev.parent;
2285         unsigned int needed_headroom;
2286         struct dpaa2_eth_swa *swa;
2287         void *buffer_start, *aligned_start;
2288         dma_addr_t addr;
2289
2290         /* We require a minimum headroom to be able to transmit the frame.
2291          * Otherwise return an error and let the original net_device handle it
2292          */
2293         needed_headroom = dpaa2_eth_needed_headroom(NULL);
2294         if (xdpf->headroom < needed_headroom)
2295                 return -EINVAL;
2296
2297         /* Setup the FD fields */
2298         memset(fd, 0, sizeof(*fd));
2299
2300         /* Align FD address, if possible */
2301         buffer_start = xdpf->data - needed_headroom;
2302         aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
2303                                   DPAA2_ETH_TX_BUF_ALIGN);
2304         if (aligned_start >= xdpf->data - xdpf->headroom)
2305                 buffer_start = aligned_start;
2306
2307         swa = (struct dpaa2_eth_swa *)buffer_start;
2308         /* fill in necessary fields here */
2309         swa->type = DPAA2_ETH_SWA_XDP;
2310         swa->xdp.dma_size = xdpf->data + xdpf->len - buffer_start;
2311         swa->xdp.xdpf = xdpf;
2312
2313         addr = dma_map_single(dev, buffer_start,
2314                               swa->xdp.dma_size,
2315                               DMA_BIDIRECTIONAL);
2316         if (unlikely(dma_mapping_error(dev, addr)))
2317                 return -ENOMEM;
2318
2319         dpaa2_fd_set_addr(fd, addr);
2320         dpaa2_fd_set_offset(fd, xdpf->data - buffer_start);
2321         dpaa2_fd_set_len(fd, xdpf->len);
2322         dpaa2_fd_set_format(fd, dpaa2_fd_single);
2323         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
2324
2325         return 0;
2326 }
2327
2328 static int dpaa2_eth_xdp_xmit(struct net_device *net_dev, int n,
2329                               struct xdp_frame **frames, u32 flags)
2330 {
2331         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2332         struct dpaa2_eth_xdp_fds *xdp_redirect_fds;
2333         struct rtnl_link_stats64 *percpu_stats;
2334         struct dpaa2_eth_fq *fq;
2335         struct dpaa2_fd *fds;
2336         int enqueued, i, err;
2337
2338         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2339                 return -EINVAL;
2340
2341         if (!netif_running(net_dev))
2342                 return -ENETDOWN;
2343
2344         fq = &priv->fq[smp_processor_id()];
2345         xdp_redirect_fds = &fq->xdp_redirect_fds;
2346         fds = xdp_redirect_fds->fds;
2347
2348         percpu_stats = this_cpu_ptr(priv->percpu_stats);
2349
2350         /* create a FD for each xdp_frame in the list received */
2351         for (i = 0; i < n; i++) {
2352                 err = dpaa2_eth_xdp_create_fd(net_dev, frames[i], &fds[i]);
2353                 if (err)
2354                         break;
2355         }
2356         xdp_redirect_fds->num = i;
2357
2358         /* enqueue all the frame descriptors */
2359         enqueued = dpaa2_eth_xdp_flush(priv, fq, xdp_redirect_fds);
2360
2361         /* update statistics */
2362         percpu_stats->tx_packets += enqueued;
2363         for (i = 0; i < enqueued; i++)
2364                 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
2365         for (i = enqueued; i < n; i++)
2366                 xdp_return_frame_rx_napi(frames[i]);
2367
2368         return enqueued;
2369 }
2370
2371 static int update_xps(struct dpaa2_eth_priv *priv)
2372 {
2373         struct net_device *net_dev = priv->net_dev;
2374         struct cpumask xps_mask;
2375         struct dpaa2_eth_fq *fq;
2376         int i, num_queues, netdev_queues;
2377         int err = 0;
2378
2379         num_queues = dpaa2_eth_queue_count(priv);
2380         netdev_queues = (net_dev->num_tc ? : 1) * num_queues;
2381
2382         /* The first <num_queues> entries in priv->fq array are Tx/Tx conf
2383          * queues, so only process those
2384          */
2385         for (i = 0; i < netdev_queues; i++) {
2386                 fq = &priv->fq[i % num_queues];
2387
2388                 cpumask_clear(&xps_mask);
2389                 cpumask_set_cpu(fq->target_cpu, &xps_mask);
2390
2391                 err = netif_set_xps_queue(net_dev, &xps_mask, i);
2392                 if (err) {
2393                         netdev_warn_once(net_dev, "Error setting XPS queue\n");
2394                         break;
2395                 }
2396         }
2397
2398         return err;
2399 }
2400
2401 static int dpaa2_eth_setup_mqprio(struct net_device *net_dev,
2402                                   struct tc_mqprio_qopt *mqprio)
2403 {
2404         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2405         u8 num_tc, num_queues;
2406         int i;
2407
2408         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2409         num_queues = dpaa2_eth_queue_count(priv);
2410         num_tc = mqprio->num_tc;
2411
2412         if (num_tc == net_dev->num_tc)
2413                 return 0;
2414
2415         if (num_tc  > dpaa2_eth_tc_count(priv)) {
2416                 netdev_err(net_dev, "Max %d traffic classes supported\n",
2417                            dpaa2_eth_tc_count(priv));
2418                 return -EOPNOTSUPP;
2419         }
2420
2421         if (!num_tc) {
2422                 netdev_reset_tc(net_dev);
2423                 netif_set_real_num_tx_queues(net_dev, num_queues);
2424                 goto out;
2425         }
2426
2427         netdev_set_num_tc(net_dev, num_tc);
2428         netif_set_real_num_tx_queues(net_dev, num_tc * num_queues);
2429
2430         for (i = 0; i < num_tc; i++)
2431                 netdev_set_tc_queue(net_dev, i, num_queues, i * num_queues);
2432
2433 out:
2434         update_xps(priv);
2435
2436         return 0;
2437 }
2438
2439 #define bps_to_mbits(rate) (div_u64((rate), 1000000) * 8)
2440
2441 static int dpaa2_eth_setup_tbf(struct net_device *net_dev, struct tc_tbf_qopt_offload *p)
2442 {
2443         struct tc_tbf_qopt_offload_replace_params *cfg = &p->replace_params;
2444         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2445         struct dpni_tx_shaping_cfg tx_cr_shaper = { 0 };
2446         struct dpni_tx_shaping_cfg tx_er_shaper = { 0 };
2447         int err;
2448
2449         if (p->command == TC_TBF_STATS)
2450                 return -EOPNOTSUPP;
2451
2452         /* Only per port Tx shaping */
2453         if (p->parent != TC_H_ROOT)
2454                 return -EOPNOTSUPP;
2455
2456         if (p->command == TC_TBF_REPLACE) {
2457                 if (cfg->max_size > DPAA2_ETH_MAX_BURST_SIZE) {
2458                         netdev_err(net_dev, "burst size cannot be greater than %d\n",
2459                                    DPAA2_ETH_MAX_BURST_SIZE);
2460                         return -EINVAL;
2461                 }
2462
2463                 tx_cr_shaper.max_burst_size = cfg->max_size;
2464                 /* The TBF interface is in bytes/s, whereas DPAA2 expects the
2465                  * rate in Mbits/s
2466                  */
2467                 tx_cr_shaper.rate_limit = bps_to_mbits(cfg->rate.rate_bytes_ps);
2468         }
2469
2470         err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, &tx_cr_shaper,
2471                                   &tx_er_shaper, 0);
2472         if (err) {
2473                 netdev_err(net_dev, "dpni_set_tx_shaping() = %d\n", err);
2474                 return err;
2475         }
2476
2477         return 0;
2478 }
2479
2480 static int dpaa2_eth_setup_tc(struct net_device *net_dev,
2481                               enum tc_setup_type type, void *type_data)
2482 {
2483         switch (type) {
2484         case TC_SETUP_QDISC_MQPRIO:
2485                 return dpaa2_eth_setup_mqprio(net_dev, type_data);
2486         case TC_SETUP_QDISC_TBF:
2487                 return dpaa2_eth_setup_tbf(net_dev, type_data);
2488         default:
2489                 return -EOPNOTSUPP;
2490         }
2491 }
2492
2493 static const struct net_device_ops dpaa2_eth_ops = {
2494         .ndo_open = dpaa2_eth_open,
2495         .ndo_start_xmit = dpaa2_eth_tx,
2496         .ndo_stop = dpaa2_eth_stop,
2497         .ndo_set_mac_address = dpaa2_eth_set_addr,
2498         .ndo_get_stats64 = dpaa2_eth_get_stats,
2499         .ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
2500         .ndo_set_features = dpaa2_eth_set_features,
2501         .ndo_do_ioctl = dpaa2_eth_ioctl,
2502         .ndo_change_mtu = dpaa2_eth_change_mtu,
2503         .ndo_bpf = dpaa2_eth_xdp,
2504         .ndo_xdp_xmit = dpaa2_eth_xdp_xmit,
2505         .ndo_setup_tc = dpaa2_eth_setup_tc,
2506 };
2507
2508 static void dpaa2_eth_cdan_cb(struct dpaa2_io_notification_ctx *ctx)
2509 {
2510         struct dpaa2_eth_channel *ch;
2511
2512         ch = container_of(ctx, struct dpaa2_eth_channel, nctx);
2513
2514         /* Update NAPI statistics */
2515         ch->stats.cdan++;
2516
2517         napi_schedule(&ch->napi);
2518 }
2519
2520 /* Allocate and configure a DPCON object */
2521 static struct fsl_mc_device *dpaa2_eth_setup_dpcon(struct dpaa2_eth_priv *priv)
2522 {
2523         struct fsl_mc_device *dpcon;
2524         struct device *dev = priv->net_dev->dev.parent;
2525         int err;
2526
2527         err = fsl_mc_object_allocate(to_fsl_mc_device(dev),
2528                                      FSL_MC_POOL_DPCON, &dpcon);
2529         if (err) {
2530                 if (err == -ENXIO)
2531                         err = -EPROBE_DEFER;
2532                 else
2533                         dev_info(dev, "Not enough DPCONs, will go on as-is\n");
2534                 return ERR_PTR(err);
2535         }
2536
2537         err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
2538         if (err) {
2539                 dev_err(dev, "dpcon_open() failed\n");
2540                 goto free;
2541         }
2542
2543         err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
2544         if (err) {
2545                 dev_err(dev, "dpcon_reset() failed\n");
2546                 goto close;
2547         }
2548
2549         err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
2550         if (err) {
2551                 dev_err(dev, "dpcon_enable() failed\n");
2552                 goto close;
2553         }
2554
2555         return dpcon;
2556
2557 close:
2558         dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
2559 free:
2560         fsl_mc_object_free(dpcon);
2561
2562         return ERR_PTR(err);
2563 }
2564
2565 static void dpaa2_eth_free_dpcon(struct dpaa2_eth_priv *priv,
2566                                  struct fsl_mc_device *dpcon)
2567 {
2568         dpcon_disable(priv->mc_io, 0, dpcon->mc_handle);
2569         dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
2570         fsl_mc_object_free(dpcon);
2571 }
2572
2573 static struct dpaa2_eth_channel *dpaa2_eth_alloc_channel(struct dpaa2_eth_priv *priv)
2574 {
2575         struct dpaa2_eth_channel *channel;
2576         struct dpcon_attr attr;
2577         struct device *dev = priv->net_dev->dev.parent;
2578         int err;
2579
2580         channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2581         if (!channel)
2582                 return NULL;
2583
2584         channel->dpcon = dpaa2_eth_setup_dpcon(priv);
2585         if (IS_ERR(channel->dpcon)) {
2586                 err = PTR_ERR(channel->dpcon);
2587                 goto err_setup;
2588         }
2589
2590         err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle,
2591                                    &attr);
2592         if (err) {
2593                 dev_err(dev, "dpcon_get_attributes() failed\n");
2594                 goto err_get_attr;
2595         }
2596
2597         channel->dpcon_id = attr.id;
2598         channel->ch_id = attr.qbman_ch_id;
2599         channel->priv = priv;
2600
2601         return channel;
2602
2603 err_get_attr:
2604         dpaa2_eth_free_dpcon(priv, channel->dpcon);
2605 err_setup:
2606         kfree(channel);
2607         return ERR_PTR(err);
2608 }
2609
2610 static void dpaa2_eth_free_channel(struct dpaa2_eth_priv *priv,
2611                                    struct dpaa2_eth_channel *channel)
2612 {
2613         dpaa2_eth_free_dpcon(priv, channel->dpcon);
2614         kfree(channel);
2615 }
2616
2617 /* DPIO setup: allocate and configure QBMan channels, setup core affinity
2618  * and register data availability notifications
2619  */
2620 static int dpaa2_eth_setup_dpio(struct dpaa2_eth_priv *priv)
2621 {
2622         struct dpaa2_io_notification_ctx *nctx;
2623         struct dpaa2_eth_channel *channel;
2624         struct dpcon_notification_cfg dpcon_notif_cfg;
2625         struct device *dev = priv->net_dev->dev.parent;
2626         int i, err;
2627
2628         /* We want the ability to spread ingress traffic (RX, TX conf) to as
2629          * many cores as possible, so we need one channel for each core
2630          * (unless there's fewer queues than cores, in which case the extra
2631          * channels would be wasted).
2632          * Allocate one channel per core and register it to the core's
2633          * affine DPIO. If not enough channels are available for all cores
2634          * or if some cores don't have an affine DPIO, there will be no
2635          * ingress frame processing on those cores.
2636          */
2637         cpumask_clear(&priv->dpio_cpumask);
2638         for_each_online_cpu(i) {
2639                 /* Try to allocate a channel */
2640                 channel = dpaa2_eth_alloc_channel(priv);
2641                 if (IS_ERR_OR_NULL(channel)) {
2642                         err = PTR_ERR_OR_ZERO(channel);
2643                         if (err != -EPROBE_DEFER)
2644                                 dev_info(dev,
2645                                          "No affine channel for cpu %d and above\n", i);
2646                         goto err_alloc_ch;
2647                 }
2648
2649                 priv->channel[priv->num_channels] = channel;
2650
2651                 nctx = &channel->nctx;
2652                 nctx->is_cdan = 1;
2653                 nctx->cb = dpaa2_eth_cdan_cb;
2654                 nctx->id = channel->ch_id;
2655                 nctx->desired_cpu = i;
2656
2657                 /* Register the new context */
2658                 channel->dpio = dpaa2_io_service_select(i);
2659                 err = dpaa2_io_service_register(channel->dpio, nctx, dev);
2660                 if (err) {
2661                         dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
2662                         /* If no affine DPIO for this core, there's probably
2663                          * none available for next cores either. Signal we want
2664                          * to retry later, in case the DPIO devices weren't
2665                          * probed yet.
2666                          */
2667                         err = -EPROBE_DEFER;
2668                         goto err_service_reg;
2669                 }
2670
2671                 /* Register DPCON notification with MC */
2672                 dpcon_notif_cfg.dpio_id = nctx->dpio_id;
2673                 dpcon_notif_cfg.priority = 0;
2674                 dpcon_notif_cfg.user_ctx = nctx->qman64;
2675                 err = dpcon_set_notification(priv->mc_io, 0,
2676                                              channel->dpcon->mc_handle,
2677                                              &dpcon_notif_cfg);
2678                 if (err) {
2679                         dev_err(dev, "dpcon_set_notification failed()\n");
2680                         goto err_set_cdan;
2681                 }
2682
2683                 /* If we managed to allocate a channel and also found an affine
2684                  * DPIO for this core, add it to the final mask
2685                  */
2686                 cpumask_set_cpu(i, &priv->dpio_cpumask);
2687                 priv->num_channels++;
2688
2689                 /* Stop if we already have enough channels to accommodate all
2690                  * RX and TX conf queues
2691                  */
2692                 if (priv->num_channels == priv->dpni_attrs.num_queues)
2693                         break;
2694         }
2695
2696         return 0;
2697
2698 err_set_cdan:
2699         dpaa2_io_service_deregister(channel->dpio, nctx, dev);
2700 err_service_reg:
2701         dpaa2_eth_free_channel(priv, channel);
2702 err_alloc_ch:
2703         if (err == -EPROBE_DEFER) {
2704                 for (i = 0; i < priv->num_channels; i++) {
2705                         channel = priv->channel[i];
2706                         nctx = &channel->nctx;
2707                         dpaa2_io_service_deregister(channel->dpio, nctx, dev);
2708                         dpaa2_eth_free_channel(priv, channel);
2709                 }
2710                 priv->num_channels = 0;
2711                 return err;
2712         }
2713
2714         if (cpumask_empty(&priv->dpio_cpumask)) {
2715                 dev_err(dev, "No cpu with an affine DPIO/DPCON\n");
2716                 return -ENODEV;
2717         }
2718
2719         dev_info(dev, "Cores %*pbl available for processing ingress traffic\n",
2720                  cpumask_pr_args(&priv->dpio_cpumask));
2721
2722         return 0;
2723 }
2724
2725 static void dpaa2_eth_free_dpio(struct dpaa2_eth_priv *priv)
2726 {
2727         struct device *dev = priv->net_dev->dev.parent;
2728         struct dpaa2_eth_channel *ch;
2729         int i;
2730
2731         /* deregister CDAN notifications and free channels */
2732         for (i = 0; i < priv->num_channels; i++) {
2733                 ch = priv->channel[i];
2734                 dpaa2_io_service_deregister(ch->dpio, &ch->nctx, dev);
2735                 dpaa2_eth_free_channel(priv, ch);
2736         }
2737 }
2738
2739 static struct dpaa2_eth_channel *dpaa2_eth_get_affine_channel(struct dpaa2_eth_priv *priv,
2740                                                               int cpu)
2741 {
2742         struct device *dev = priv->net_dev->dev.parent;
2743         int i;
2744
2745         for (i = 0; i < priv->num_channels; i++)
2746                 if (priv->channel[i]->nctx.desired_cpu == cpu)
2747                         return priv->channel[i];
2748
2749         /* We should never get here. Issue a warning and return
2750          * the first channel, because it's still better than nothing
2751          */
2752         dev_warn(dev, "No affine channel found for cpu %d\n", cpu);
2753
2754         return priv->channel[0];
2755 }
2756
2757 static void dpaa2_eth_set_fq_affinity(struct dpaa2_eth_priv *priv)
2758 {
2759         struct device *dev = priv->net_dev->dev.parent;
2760         struct dpaa2_eth_fq *fq;
2761         int rx_cpu, txc_cpu;
2762         int i;
2763
2764         /* For each FQ, pick one channel/CPU to deliver frames to.
2765          * This may well change at runtime, either through irqbalance or
2766          * through direct user intervention.
2767          */
2768         rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask);
2769
2770         for (i = 0; i < priv->num_fqs; i++) {
2771                 fq = &priv->fq[i];
2772                 switch (fq->type) {
2773                 case DPAA2_RX_FQ:
2774                 case DPAA2_RX_ERR_FQ:
2775                         fq->target_cpu = rx_cpu;
2776                         rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
2777                         if (rx_cpu >= nr_cpu_ids)
2778                                 rx_cpu = cpumask_first(&priv->dpio_cpumask);
2779                         break;
2780                 case DPAA2_TX_CONF_FQ:
2781                         fq->target_cpu = txc_cpu;
2782                         txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
2783                         if (txc_cpu >= nr_cpu_ids)
2784                                 txc_cpu = cpumask_first(&priv->dpio_cpumask);
2785                         break;
2786                 default:
2787                         dev_err(dev, "Unknown FQ type: %d\n", fq->type);
2788                 }
2789                 fq->channel = dpaa2_eth_get_affine_channel(priv, fq->target_cpu);
2790         }
2791
2792         update_xps(priv);
2793 }
2794
2795 static void dpaa2_eth_setup_fqs(struct dpaa2_eth_priv *priv)
2796 {
2797         int i, j;
2798
2799         /* We have one TxConf FQ per Tx flow.
2800          * The number of Tx and Rx queues is the same.
2801          * Tx queues come first in the fq array.
2802          */
2803         for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
2804                 priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ;
2805                 priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf;
2806                 priv->fq[priv->num_fqs++].flowid = (u16)i;
2807         }
2808
2809         for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
2810                 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
2811                         priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
2812                         priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
2813                         priv->fq[priv->num_fqs].tc = (u8)j;
2814                         priv->fq[priv->num_fqs++].flowid = (u16)i;
2815                 }
2816         }
2817
2818         /* We have exactly one Rx error queue per DPNI */
2819         priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ;
2820         priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err;
2821
2822         /* For each FQ, decide on which core to process incoming frames */
2823         dpaa2_eth_set_fq_affinity(priv);
2824 }
2825
2826 /* Allocate and configure one buffer pool for each interface */
2827 static int dpaa2_eth_setup_dpbp(struct dpaa2_eth_priv *priv)
2828 {
2829         int err;
2830         struct fsl_mc_device *dpbp_dev;
2831         struct device *dev = priv->net_dev->dev.parent;
2832         struct dpbp_attr dpbp_attrs;
2833
2834         err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP,
2835                                      &dpbp_dev);
2836         if (err) {
2837                 if (err == -ENXIO)
2838                         err = -EPROBE_DEFER;
2839                 else
2840                         dev_err(dev, "DPBP device allocation failed\n");
2841                 return err;
2842         }
2843
2844         priv->dpbp_dev = dpbp_dev;
2845
2846         err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id,
2847                         &dpbp_dev->mc_handle);
2848         if (err) {
2849                 dev_err(dev, "dpbp_open() failed\n");
2850                 goto err_open;
2851         }
2852
2853         err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle);
2854         if (err) {
2855                 dev_err(dev, "dpbp_reset() failed\n");
2856                 goto err_reset;
2857         }
2858
2859         err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle);
2860         if (err) {
2861                 dev_err(dev, "dpbp_enable() failed\n");
2862                 goto err_enable;
2863         }
2864
2865         err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle,
2866                                   &dpbp_attrs);
2867         if (err) {
2868                 dev_err(dev, "dpbp_get_attributes() failed\n");
2869                 goto err_get_attr;
2870         }
2871         priv->bpid = dpbp_attrs.bpid;
2872
2873         return 0;
2874
2875 err_get_attr:
2876         dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle);
2877 err_enable:
2878 err_reset:
2879         dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle);
2880 err_open:
2881         fsl_mc_object_free(dpbp_dev);
2882
2883         return err;
2884 }
2885
2886 static void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv)
2887 {
2888         dpaa2_eth_drain_pool(priv);
2889         dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
2890         dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
2891         fsl_mc_object_free(priv->dpbp_dev);
2892 }
2893
2894 static int dpaa2_eth_set_buffer_layout(struct dpaa2_eth_priv *priv)
2895 {
2896         struct device *dev = priv->net_dev->dev.parent;
2897         struct dpni_buffer_layout buf_layout = {0};
2898         u16 rx_buf_align;
2899         int err;
2900
2901         /* We need to check for WRIOP version 1.0.0, but depending on the MC
2902          * version, this number is not always provided correctly on rev1.
2903          * We need to check for both alternatives in this situation.
2904          */
2905         if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) ||
2906             priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0))
2907                 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1;
2908         else
2909                 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN;
2910
2911         /* We need to ensure that the buffer size seen by WRIOP is a multiple
2912          * of 64 or 256 bytes depending on the WRIOP version.
2913          */
2914         priv->rx_buf_size = ALIGN_DOWN(DPAA2_ETH_RX_BUF_SIZE, rx_buf_align);
2915
2916         /* tx buffer */
2917         buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
2918         buf_layout.pass_timestamp = true;
2919         buf_layout.pass_frame_status = true;
2920         buf_layout.options = DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
2921                              DPNI_BUF_LAYOUT_OPT_TIMESTAMP |
2922                              DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2923         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2924                                      DPNI_QUEUE_TX, &buf_layout);
2925         if (err) {
2926                 dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
2927                 return err;
2928         }
2929
2930         /* tx-confirm buffer */
2931         buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP |
2932                              DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2933         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2934                                      DPNI_QUEUE_TX_CONFIRM, &buf_layout);
2935         if (err) {
2936                 dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
2937                 return err;
2938         }
2939
2940         /* Now that we've set our tx buffer layout, retrieve the minimum
2941          * required tx data offset.
2942          */
2943         err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
2944                                       &priv->tx_data_offset);
2945         if (err) {
2946                 dev_err(dev, "dpni_get_tx_data_offset() failed\n");
2947                 return err;
2948         }
2949
2950         if ((priv->tx_data_offset % 64) != 0)
2951                 dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
2952                          priv->tx_data_offset);
2953
2954         /* rx buffer */
2955         buf_layout.pass_frame_status = true;
2956         buf_layout.pass_parser_result = true;
2957         buf_layout.data_align = rx_buf_align;
2958         buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv);
2959         buf_layout.private_data_size = 0;
2960         buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
2961                              DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2962                              DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
2963                              DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
2964                              DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2965         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2966                                      DPNI_QUEUE_RX, &buf_layout);
2967         if (err) {
2968                 dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
2969                 return err;
2970         }
2971
2972         return 0;
2973 }
2974
2975 #define DPNI_ENQUEUE_FQID_VER_MAJOR     7
2976 #define DPNI_ENQUEUE_FQID_VER_MINOR     9
2977
2978 static inline int dpaa2_eth_enqueue_qd(struct dpaa2_eth_priv *priv,
2979                                        struct dpaa2_eth_fq *fq,
2980                                        struct dpaa2_fd *fd, u8 prio,
2981                                        u32 num_frames __always_unused,
2982                                        int *frames_enqueued)
2983 {
2984         int err;
2985
2986         err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
2987                                           priv->tx_qdid, prio,
2988                                           fq->tx_qdbin, fd);
2989         if (!err && frames_enqueued)
2990                 *frames_enqueued = 1;
2991         return err;
2992 }
2993
2994 static inline int dpaa2_eth_enqueue_fq_multiple(struct dpaa2_eth_priv *priv,
2995                                                 struct dpaa2_eth_fq *fq,
2996                                                 struct dpaa2_fd *fd,
2997                                                 u8 prio, u32 num_frames,
2998                                                 int *frames_enqueued)
2999 {
3000         int err;
3001
3002         err = dpaa2_io_service_enqueue_multiple_fq(fq->channel->dpio,
3003                                                    fq->tx_fqid[prio],
3004                                                    fd, num_frames);
3005
3006         if (err == 0)
3007                 return -EBUSY;
3008
3009         if (frames_enqueued)
3010                 *frames_enqueued = err;
3011         return 0;
3012 }
3013
3014 static void dpaa2_eth_set_enqueue_mode(struct dpaa2_eth_priv *priv)
3015 {
3016         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
3017                                    DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
3018                 priv->enqueue = dpaa2_eth_enqueue_qd;
3019         else
3020                 priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
3021 }
3022
3023 static int dpaa2_eth_set_pause(struct dpaa2_eth_priv *priv)
3024 {
3025         struct device *dev = priv->net_dev->dev.parent;
3026         struct dpni_link_cfg link_cfg = {0};
3027         int err;
3028
3029         /* Get the default link options so we don't override other flags */
3030         err = dpni_get_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
3031         if (err) {
3032                 dev_err(dev, "dpni_get_link_cfg() failed\n");
3033                 return err;
3034         }
3035
3036         /* By default, enable both Rx and Tx pause frames */
3037         link_cfg.options |= DPNI_LINK_OPT_PAUSE;
3038         link_cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
3039         err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
3040         if (err) {
3041                 dev_err(dev, "dpni_set_link_cfg() failed\n");
3042                 return err;
3043         }
3044
3045         priv->link_state.options = link_cfg.options;
3046
3047         return 0;
3048 }
3049
3050 static void dpaa2_eth_update_tx_fqids(struct dpaa2_eth_priv *priv)
3051 {
3052         struct dpni_queue_id qid = {0};
3053         struct dpaa2_eth_fq *fq;
3054         struct dpni_queue queue;
3055         int i, j, err;
3056
3057         /* We only use Tx FQIDs for FQID-based enqueue, so check
3058          * if DPNI version supports it before updating FQIDs
3059          */
3060         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
3061                                    DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
3062                 return;
3063
3064         for (i = 0; i < priv->num_fqs; i++) {
3065                 fq = &priv->fq[i];
3066                 if (fq->type != DPAA2_TX_CONF_FQ)
3067                         continue;
3068                 for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
3069                         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3070                                              DPNI_QUEUE_TX, j, fq->flowid,
3071                                              &queue, &qid);
3072                         if (err)
3073                                 goto out_err;
3074
3075                         fq->tx_fqid[j] = qid.fqid;
3076                         if (fq->tx_fqid[j] == 0)
3077                                 goto out_err;
3078                 }
3079         }
3080
3081         priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
3082
3083         return;
3084
3085 out_err:
3086         netdev_info(priv->net_dev,
3087                     "Error reading Tx FQID, fallback to QDID-based enqueue\n");
3088         priv->enqueue = dpaa2_eth_enqueue_qd;
3089 }
3090
3091 /* Configure ingress classification based on VLAN PCP */
3092 static int dpaa2_eth_set_vlan_qos(struct dpaa2_eth_priv *priv)
3093 {
3094         struct device *dev = priv->net_dev->dev.parent;
3095         struct dpkg_profile_cfg kg_cfg = {0};
3096         struct dpni_qos_tbl_cfg qos_cfg = {0};
3097         struct dpni_rule_cfg key_params;
3098         void *dma_mem, *key, *mask;
3099         u8 key_size = 2;        /* VLAN TCI field */
3100         int i, pcp, err;
3101
3102         /* VLAN-based classification only makes sense if we have multiple
3103          * traffic classes.
3104          * Also, we need to extract just the 3-bit PCP field from the VLAN
3105          * header and we can only do that by using a mask
3106          */
3107         if (dpaa2_eth_tc_count(priv) == 1 || !dpaa2_eth_fs_mask_enabled(priv)) {
3108                 dev_dbg(dev, "VLAN-based QoS classification not supported\n");
3109                 return -EOPNOTSUPP;
3110         }
3111
3112         dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
3113         if (!dma_mem)
3114                 return -ENOMEM;
3115
3116         kg_cfg.num_extracts = 1;
3117         kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_HDR;
3118         kg_cfg.extracts[0].extract.from_hdr.prot = NET_PROT_VLAN;
3119         kg_cfg.extracts[0].extract.from_hdr.type = DPKG_FULL_FIELD;
3120         kg_cfg.extracts[0].extract.from_hdr.field = NH_FLD_VLAN_TCI;
3121
3122         err = dpni_prepare_key_cfg(&kg_cfg, dma_mem);
3123         if (err) {
3124                 dev_err(dev, "dpni_prepare_key_cfg failed\n");
3125                 goto out_free_tbl;
3126         }
3127
3128         /* set QoS table */
3129         qos_cfg.default_tc = 0;
3130         qos_cfg.discard_on_miss = 0;
3131         qos_cfg.key_cfg_iova = dma_map_single(dev, dma_mem,
3132                                               DPAA2_CLASSIFIER_DMA_SIZE,
3133                                               DMA_TO_DEVICE);
3134         if (dma_mapping_error(dev, qos_cfg.key_cfg_iova)) {
3135                 dev_err(dev, "QoS table DMA mapping failed\n");
3136                 err = -ENOMEM;
3137                 goto out_free_tbl;
3138         }
3139
3140         err = dpni_set_qos_table(priv->mc_io, 0, priv->mc_token, &qos_cfg);
3141         if (err) {
3142                 dev_err(dev, "dpni_set_qos_table failed\n");
3143                 goto out_unmap_tbl;
3144         }
3145
3146         /* Add QoS table entries */
3147         key = kzalloc(key_size * 2, GFP_KERNEL);
3148         if (!key) {
3149                 err = -ENOMEM;
3150                 goto out_unmap_tbl;
3151         }
3152         mask = key + key_size;
3153         *(__be16 *)mask = cpu_to_be16(VLAN_PRIO_MASK);
3154
3155         key_params.key_iova = dma_map_single(dev, key, key_size * 2,
3156                                              DMA_TO_DEVICE);
3157         if (dma_mapping_error(dev, key_params.key_iova)) {
3158                 dev_err(dev, "Qos table entry DMA mapping failed\n");
3159                 err = -ENOMEM;
3160                 goto out_free_key;
3161         }
3162
3163         key_params.mask_iova = key_params.key_iova + key_size;
3164         key_params.key_size = key_size;
3165
3166         /* We add rules for PCP-based distribution starting with highest
3167          * priority (VLAN PCP = 7). If this DPNI doesn't have enough traffic
3168          * classes to accommodate all priority levels, the lowest ones end up
3169          * on TC 0 which was configured as default
3170          */
3171         for (i = dpaa2_eth_tc_count(priv) - 1, pcp = 7; i >= 0; i--, pcp--) {
3172                 *(__be16 *)key = cpu_to_be16(pcp << VLAN_PRIO_SHIFT);
3173                 dma_sync_single_for_device(dev, key_params.key_iova,
3174                                            key_size * 2, DMA_TO_DEVICE);
3175
3176                 err = dpni_add_qos_entry(priv->mc_io, 0, priv->mc_token,
3177                                          &key_params, i, i);
3178                 if (err) {
3179                         dev_err(dev, "dpni_add_qos_entry failed\n");
3180                         dpni_clear_qos_table(priv->mc_io, 0, priv->mc_token);
3181                         goto out_unmap_key;
3182                 }
3183         }
3184
3185         priv->vlan_cls_enabled = true;
3186
3187         /* Table and key memory is not persistent, clean everything up after
3188          * configuration is finished
3189          */
3190 out_unmap_key:
3191         dma_unmap_single(dev, key_params.key_iova, key_size * 2, DMA_TO_DEVICE);
3192 out_free_key:
3193         kfree(key);
3194 out_unmap_tbl:
3195         dma_unmap_single(dev, qos_cfg.key_cfg_iova, DPAA2_CLASSIFIER_DMA_SIZE,
3196                          DMA_TO_DEVICE);
3197 out_free_tbl:
3198         kfree(dma_mem);
3199
3200         return err;
3201 }
3202
3203 /* Configure the DPNI object this interface is associated with */
3204 static int dpaa2_eth_setup_dpni(struct fsl_mc_device *ls_dev)
3205 {
3206         struct device *dev = &ls_dev->dev;
3207         struct dpaa2_eth_priv *priv;
3208         struct net_device *net_dev;
3209         int err;
3210
3211         net_dev = dev_get_drvdata(dev);
3212         priv = netdev_priv(net_dev);
3213
3214         /* get a handle for the DPNI object */
3215         err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
3216         if (err) {
3217                 dev_err(dev, "dpni_open() failed\n");
3218                 return err;
3219         }
3220
3221         /* Check if we can work with this DPNI object */
3222         err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major,
3223                                    &priv->dpni_ver_minor);
3224         if (err) {
3225                 dev_err(dev, "dpni_get_api_version() failed\n");
3226                 goto close;
3227         }
3228         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) {
3229                 dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n",
3230                         priv->dpni_ver_major, priv->dpni_ver_minor,
3231                         DPNI_VER_MAJOR, DPNI_VER_MINOR);
3232                 err = -ENOTSUPP;
3233                 goto close;
3234         }
3235
3236         ls_dev->mc_io = priv->mc_io;
3237         ls_dev->mc_handle = priv->mc_token;
3238
3239         err = dpni_reset(priv->mc_io, 0, priv->mc_token);
3240         if (err) {
3241                 dev_err(dev, "dpni_reset() failed\n");
3242                 goto close;
3243         }
3244
3245         err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
3246                                   &priv->dpni_attrs);
3247         if (err) {
3248                 dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
3249                 goto close;
3250         }
3251
3252         err = dpaa2_eth_set_buffer_layout(priv);
3253         if (err)
3254                 goto close;
3255
3256         dpaa2_eth_set_enqueue_mode(priv);
3257
3258         /* Enable pause frame support */
3259         if (dpaa2_eth_has_pause_support(priv)) {
3260                 err = dpaa2_eth_set_pause(priv);
3261                 if (err)
3262                         goto close;
3263         }
3264
3265         err = dpaa2_eth_set_vlan_qos(priv);
3266         if (err && err != -EOPNOTSUPP)
3267                 goto close;
3268
3269         priv->cls_rules = devm_kcalloc(dev, dpaa2_eth_fs_count(priv),
3270                                        sizeof(struct dpaa2_eth_cls_rule),
3271                                        GFP_KERNEL);
3272         if (!priv->cls_rules) {
3273                 err = -ENOMEM;
3274                 goto close;
3275         }
3276
3277         return 0;
3278
3279 close:
3280         dpni_close(priv->mc_io, 0, priv->mc_token);
3281
3282         return err;
3283 }
3284
3285 static void dpaa2_eth_free_dpni(struct dpaa2_eth_priv *priv)
3286 {
3287         int err;
3288
3289         err = dpni_reset(priv->mc_io, 0, priv->mc_token);
3290         if (err)
3291                 netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n",
3292                             err);
3293
3294         dpni_close(priv->mc_io, 0, priv->mc_token);
3295 }
3296
3297 static int dpaa2_eth_setup_rx_flow(struct dpaa2_eth_priv *priv,
3298                                    struct dpaa2_eth_fq *fq)
3299 {
3300         struct device *dev = priv->net_dev->dev.parent;
3301         struct dpni_queue queue;
3302         struct dpni_queue_id qid;
3303         int err;
3304
3305         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3306                              DPNI_QUEUE_RX, fq->tc, fq->flowid, &queue, &qid);
3307         if (err) {
3308                 dev_err(dev, "dpni_get_queue(RX) failed\n");
3309                 return err;
3310         }
3311
3312         fq->fqid = qid.fqid;
3313
3314         queue.destination.id = fq->channel->dpcon_id;
3315         queue.destination.type = DPNI_DEST_DPCON;
3316         queue.destination.priority = 1;
3317         queue.user_context = (u64)(uintptr_t)fq;
3318         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3319                              DPNI_QUEUE_RX, fq->tc, fq->flowid,
3320                              DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
3321                              &queue);
3322         if (err) {
3323                 dev_err(dev, "dpni_set_queue(RX) failed\n");
3324                 return err;
3325         }
3326
3327         /* xdp_rxq setup */
3328         /* only once for each channel */
3329         if (fq->tc > 0)
3330                 return 0;
3331
3332         err = xdp_rxq_info_reg(&fq->channel->xdp_rxq, priv->net_dev,
3333                                fq->flowid, 0);
3334         if (err) {
3335                 dev_err(dev, "xdp_rxq_info_reg failed\n");
3336                 return err;
3337         }
3338
3339         err = xdp_rxq_info_reg_mem_model(&fq->channel->xdp_rxq,
3340                                          MEM_TYPE_PAGE_ORDER0, NULL);
3341         if (err) {
3342                 dev_err(dev, "xdp_rxq_info_reg_mem_model failed\n");
3343                 return err;
3344         }
3345
3346         return 0;
3347 }
3348
3349 static int dpaa2_eth_setup_tx_flow(struct dpaa2_eth_priv *priv,
3350                                    struct dpaa2_eth_fq *fq)
3351 {
3352         struct device *dev = priv->net_dev->dev.parent;
3353         struct dpni_queue queue;
3354         struct dpni_queue_id qid;
3355         int i, err;
3356
3357         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3358                 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3359                                      DPNI_QUEUE_TX, i, fq->flowid,
3360                                      &queue, &qid);
3361                 if (err) {
3362                         dev_err(dev, "dpni_get_queue(TX) failed\n");
3363                         return err;
3364                 }
3365                 fq->tx_fqid[i] = qid.fqid;
3366         }
3367
3368         /* All Tx queues belonging to the same flowid have the same qdbin */
3369         fq->tx_qdbin = qid.qdbin;
3370
3371         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3372                              DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3373                              &queue, &qid);
3374         if (err) {
3375                 dev_err(dev, "dpni_get_queue(TX_CONF) failed\n");
3376                 return err;
3377         }
3378
3379         fq->fqid = qid.fqid;
3380
3381         queue.destination.id = fq->channel->dpcon_id;
3382         queue.destination.type = DPNI_DEST_DPCON;
3383         queue.destination.priority = 0;
3384         queue.user_context = (u64)(uintptr_t)fq;
3385         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3386                              DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3387                              DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
3388                              &queue);
3389         if (err) {
3390                 dev_err(dev, "dpni_set_queue(TX_CONF) failed\n");
3391                 return err;
3392         }
3393
3394         return 0;
3395 }
3396
3397 static int setup_rx_err_flow(struct dpaa2_eth_priv *priv,
3398                              struct dpaa2_eth_fq *fq)
3399 {
3400         struct device *dev = priv->net_dev->dev.parent;
3401         struct dpni_queue q = { { 0 } };
3402         struct dpni_queue_id qid;
3403         u8 q_opt = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST;
3404         int err;
3405
3406         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3407                              DPNI_QUEUE_RX_ERR, 0, 0, &q, &qid);
3408         if (err) {
3409                 dev_err(dev, "dpni_get_queue() failed (%d)\n", err);
3410                 return err;
3411         }
3412
3413         fq->fqid = qid.fqid;
3414
3415         q.destination.id = fq->channel->dpcon_id;
3416         q.destination.type = DPNI_DEST_DPCON;
3417         q.destination.priority = 1;
3418         q.user_context = (u64)(uintptr_t)fq;
3419         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3420                              DPNI_QUEUE_RX_ERR, 0, 0, q_opt, &q);
3421         if (err) {
3422                 dev_err(dev, "dpni_set_queue() failed (%d)\n", err);
3423                 return err;
3424         }
3425
3426         return 0;
3427 }
3428
3429 /* Supported header fields for Rx hash distribution key */
3430 static const struct dpaa2_eth_dist_fields dist_fields[] = {
3431         {
3432                 /* L2 header */
3433                 .rxnfc_field = RXH_L2DA,
3434                 .cls_prot = NET_PROT_ETH,
3435                 .cls_field = NH_FLD_ETH_DA,
3436                 .id = DPAA2_ETH_DIST_ETHDST,
3437                 .size = 6,
3438         }, {
3439                 .cls_prot = NET_PROT_ETH,
3440                 .cls_field = NH_FLD_ETH_SA,
3441                 .id = DPAA2_ETH_DIST_ETHSRC,
3442                 .size = 6,
3443         }, {
3444                 /* This is the last ethertype field parsed:
3445                  * depending on frame format, it can be the MAC ethertype
3446                  * or the VLAN etype.
3447                  */
3448                 .cls_prot = NET_PROT_ETH,
3449                 .cls_field = NH_FLD_ETH_TYPE,
3450                 .id = DPAA2_ETH_DIST_ETHTYPE,
3451                 .size = 2,
3452         }, {
3453                 /* VLAN header */
3454                 .rxnfc_field = RXH_VLAN,
3455                 .cls_prot = NET_PROT_VLAN,
3456                 .cls_field = NH_FLD_VLAN_TCI,
3457                 .id = DPAA2_ETH_DIST_VLAN,
3458                 .size = 2,
3459         }, {
3460                 /* IP header */
3461                 .rxnfc_field = RXH_IP_SRC,
3462                 .cls_prot = NET_PROT_IP,
3463                 .cls_field = NH_FLD_IP_SRC,
3464                 .id = DPAA2_ETH_DIST_IPSRC,
3465                 .size = 4,
3466         }, {
3467                 .rxnfc_field = RXH_IP_DST,
3468                 .cls_prot = NET_PROT_IP,
3469                 .cls_field = NH_FLD_IP_DST,
3470                 .id = DPAA2_ETH_DIST_IPDST,
3471                 .size = 4,
3472         }, {
3473                 .rxnfc_field = RXH_L3_PROTO,
3474                 .cls_prot = NET_PROT_IP,
3475                 .cls_field = NH_FLD_IP_PROTO,
3476                 .id = DPAA2_ETH_DIST_IPPROTO,
3477                 .size = 1,
3478         }, {
3479                 /* Using UDP ports, this is functionally equivalent to raw
3480                  * byte pairs from L4 header.
3481                  */
3482                 .rxnfc_field = RXH_L4_B_0_1,
3483                 .cls_prot = NET_PROT_UDP,
3484                 .cls_field = NH_FLD_UDP_PORT_SRC,
3485                 .id = DPAA2_ETH_DIST_L4SRC,
3486                 .size = 2,
3487         }, {
3488                 .rxnfc_field = RXH_L4_B_2_3,
3489                 .cls_prot = NET_PROT_UDP,
3490                 .cls_field = NH_FLD_UDP_PORT_DST,
3491                 .id = DPAA2_ETH_DIST_L4DST,
3492                 .size = 2,
3493         },
3494 };
3495
3496 /* Configure the Rx hash key using the legacy API */
3497 static int dpaa2_eth_config_legacy_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3498 {
3499         struct device *dev = priv->net_dev->dev.parent;
3500         struct dpni_rx_tc_dist_cfg dist_cfg;
3501         int i, err = 0;
3502
3503         memset(&dist_cfg, 0, sizeof(dist_cfg));
3504
3505         dist_cfg.key_cfg_iova = key;
3506         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3507         dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
3508
3509         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3510                 err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token,
3511                                           i, &dist_cfg);
3512                 if (err) {
3513                         dev_err(dev, "dpni_set_rx_tc_dist failed\n");
3514                         break;
3515                 }
3516         }
3517
3518         return err;
3519 }
3520
3521 /* Configure the Rx hash key using the new API */
3522 static int dpaa2_eth_config_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3523 {
3524         struct device *dev = priv->net_dev->dev.parent;
3525         struct dpni_rx_dist_cfg dist_cfg;
3526         int i, err = 0;
3527
3528         memset(&dist_cfg, 0, sizeof(dist_cfg));
3529
3530         dist_cfg.key_cfg_iova = key;
3531         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3532         dist_cfg.enable = 1;
3533
3534         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3535                 dist_cfg.tc = i;
3536                 err = dpni_set_rx_hash_dist(priv->mc_io, 0, priv->mc_token,
3537                                             &dist_cfg);
3538                 if (err) {
3539                         dev_err(dev, "dpni_set_rx_hash_dist failed\n");
3540                         break;
3541                 }
3542
3543                 /* If the flow steering / hashing key is shared between all
3544                  * traffic classes, install it just once
3545                  */
3546                 if (priv->dpni_attrs.options & DPNI_OPT_SHARED_FS)
3547                         break;
3548         }
3549
3550         return err;
3551 }
3552
3553 /* Configure the Rx flow classification key */
3554 static int dpaa2_eth_config_cls_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3555 {
3556         struct device *dev = priv->net_dev->dev.parent;
3557         struct dpni_rx_dist_cfg dist_cfg;
3558         int i, err = 0;
3559
3560         memset(&dist_cfg, 0, sizeof(dist_cfg));
3561
3562         dist_cfg.key_cfg_iova = key;
3563         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3564         dist_cfg.enable = 1;
3565
3566         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3567                 dist_cfg.tc = i;
3568                 err = dpni_set_rx_fs_dist(priv->mc_io, 0, priv->mc_token,
3569                                           &dist_cfg);
3570                 if (err) {
3571                         dev_err(dev, "dpni_set_rx_fs_dist failed\n");
3572                         break;
3573                 }
3574
3575                 /* If the flow steering / hashing key is shared between all
3576                  * traffic classes, install it just once
3577                  */
3578                 if (priv->dpni_attrs.options & DPNI_OPT_SHARED_FS)
3579                         break;
3580         }
3581
3582         return err;
3583 }
3584
3585 /* Size of the Rx flow classification key */
3586 int dpaa2_eth_cls_key_size(u64 fields)
3587 {
3588         int i, size = 0;
3589
3590         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3591                 if (!(fields & dist_fields[i].id))
3592                         continue;
3593                 size += dist_fields[i].size;
3594         }
3595
3596         return size;
3597 }
3598
3599 /* Offset of header field in Rx classification key */
3600 int dpaa2_eth_cls_fld_off(int prot, int field)
3601 {
3602         int i, off = 0;
3603
3604         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3605                 if (dist_fields[i].cls_prot == prot &&
3606                     dist_fields[i].cls_field == field)
3607                         return off;
3608                 off += dist_fields[i].size;
3609         }
3610
3611         WARN_ONCE(1, "Unsupported header field used for Rx flow cls\n");
3612         return 0;
3613 }
3614
3615 /* Prune unused fields from the classification rule.
3616  * Used when masking is not supported
3617  */
3618 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields)
3619 {
3620         int off = 0, new_off = 0;
3621         int i, size;
3622
3623         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3624                 size = dist_fields[i].size;
3625                 if (dist_fields[i].id & fields) {
3626                         memcpy(key_mem + new_off, key_mem + off, size);
3627                         new_off += size;
3628                 }
3629                 off += size;
3630         }
3631 }
3632
3633 /* Set Rx distribution (hash or flow classification) key
3634  * flags is a combination of RXH_ bits
3635  */
3636 static int dpaa2_eth_set_dist_key(struct net_device *net_dev,
3637                                   enum dpaa2_eth_rx_dist type, u64 flags)
3638 {
3639         struct device *dev = net_dev->dev.parent;
3640         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3641         struct dpkg_profile_cfg cls_cfg;
3642         u32 rx_hash_fields = 0;
3643         dma_addr_t key_iova;
3644         u8 *dma_mem;
3645         int i;
3646         int err = 0;
3647
3648         memset(&cls_cfg, 0, sizeof(cls_cfg));
3649
3650         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3651                 struct dpkg_extract *key =
3652                         &cls_cfg.extracts[cls_cfg.num_extracts];
3653
3654                 /* For both Rx hashing and classification keys
3655                  * we set only the selected fields.
3656                  */
3657                 if (!(flags & dist_fields[i].id))
3658                         continue;
3659                 if (type == DPAA2_ETH_RX_DIST_HASH)
3660                         rx_hash_fields |= dist_fields[i].rxnfc_field;
3661
3662                 if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) {
3663                         dev_err(dev, "error adding key extraction rule, too many rules?\n");
3664                         return -E2BIG;
3665                 }
3666
3667                 key->type = DPKG_EXTRACT_FROM_HDR;
3668                 key->extract.from_hdr.prot = dist_fields[i].cls_prot;
3669                 key->extract.from_hdr.type = DPKG_FULL_FIELD;
3670                 key->extract.from_hdr.field = dist_fields[i].cls_field;
3671                 cls_cfg.num_extracts++;
3672         }
3673
3674         dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
3675         if (!dma_mem)
3676                 return -ENOMEM;
3677
3678         err = dpni_prepare_key_cfg(&cls_cfg, dma_mem);
3679         if (err) {
3680                 dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
3681                 goto free_key;
3682         }
3683
3684         /* Prepare for setting the rx dist */
3685         key_iova = dma_map_single(dev, dma_mem, DPAA2_CLASSIFIER_DMA_SIZE,
3686                                   DMA_TO_DEVICE);
3687         if (dma_mapping_error(dev, key_iova)) {
3688                 dev_err(dev, "DMA mapping failed\n");
3689                 err = -ENOMEM;
3690                 goto free_key;
3691         }
3692
3693         if (type == DPAA2_ETH_RX_DIST_HASH) {
3694                 if (dpaa2_eth_has_legacy_dist(priv))
3695                         err = dpaa2_eth_config_legacy_hash_key(priv, key_iova);
3696                 else
3697                         err = dpaa2_eth_config_hash_key(priv, key_iova);
3698         } else {
3699                 err = dpaa2_eth_config_cls_key(priv, key_iova);
3700         }
3701
3702         dma_unmap_single(dev, key_iova, DPAA2_CLASSIFIER_DMA_SIZE,
3703                          DMA_TO_DEVICE);
3704         if (!err && type == DPAA2_ETH_RX_DIST_HASH)
3705                 priv->rx_hash_fields = rx_hash_fields;
3706
3707 free_key:
3708         kfree(dma_mem);
3709         return err;
3710 }
3711
3712 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags)
3713 {
3714         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3715         u64 key = 0;
3716         int i;
3717
3718         if (!dpaa2_eth_hash_enabled(priv))
3719                 return -EOPNOTSUPP;
3720
3721         for (i = 0; i < ARRAY_SIZE(dist_fields); i++)
3722                 if (dist_fields[i].rxnfc_field & flags)
3723                         key |= dist_fields[i].id;
3724
3725         return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_HASH, key);
3726 }
3727
3728 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 flags)
3729 {
3730         return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_CLS, flags);
3731 }
3732
3733 static int dpaa2_eth_set_default_cls(struct dpaa2_eth_priv *priv)
3734 {
3735         struct device *dev = priv->net_dev->dev.parent;
3736         int err;
3737
3738         /* Check if we actually support Rx flow classification */
3739         if (dpaa2_eth_has_legacy_dist(priv)) {
3740                 dev_dbg(dev, "Rx cls not supported by current MC version\n");
3741                 return -EOPNOTSUPP;
3742         }
3743
3744         if (!dpaa2_eth_fs_enabled(priv)) {
3745                 dev_dbg(dev, "Rx cls disabled in DPNI options\n");
3746                 return -EOPNOTSUPP;
3747         }
3748
3749         if (!dpaa2_eth_hash_enabled(priv)) {
3750                 dev_dbg(dev, "Rx cls disabled for single queue DPNIs\n");
3751                 return -EOPNOTSUPP;
3752         }
3753
3754         /* If there is no support for masking in the classification table,
3755          * we don't set a default key, as it will depend on the rules
3756          * added by the user at runtime.
3757          */
3758         if (!dpaa2_eth_fs_mask_enabled(priv))
3759                 goto out;
3760
3761         err = dpaa2_eth_set_cls(priv->net_dev, DPAA2_ETH_DIST_ALL);
3762         if (err)
3763                 return err;
3764
3765 out:
3766         priv->rx_cls_enabled = 1;
3767
3768         return 0;
3769 }
3770
3771 /* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs,
3772  * frame queues and channels
3773  */
3774 static int dpaa2_eth_bind_dpni(struct dpaa2_eth_priv *priv)
3775 {
3776         struct net_device *net_dev = priv->net_dev;
3777         struct device *dev = net_dev->dev.parent;
3778         struct dpni_pools_cfg pools_params;
3779         struct dpni_error_cfg err_cfg;
3780         int err = 0;
3781         int i;
3782
3783         pools_params.num_dpbp = 1;
3784         pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id;
3785         pools_params.pools[0].backup_pool = 0;
3786         pools_params.pools[0].buffer_size = priv->rx_buf_size;
3787         err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
3788         if (err) {
3789                 dev_err(dev, "dpni_set_pools() failed\n");
3790                 return err;
3791         }
3792
3793         /* have the interface implicitly distribute traffic based on
3794          * the default hash key
3795          */
3796         err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_DEFAULT);
3797         if (err && err != -EOPNOTSUPP)
3798                 dev_err(dev, "Failed to configure hashing\n");
3799
3800         /* Configure the flow classification key; it includes all
3801          * supported header fields and cannot be modified at runtime
3802          */
3803         err = dpaa2_eth_set_default_cls(priv);
3804         if (err && err != -EOPNOTSUPP)
3805                 dev_err(dev, "Failed to configure Rx classification key\n");
3806
3807         /* Configure handling of error frames */
3808         err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
3809         err_cfg.set_frame_annotation = 1;
3810         err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
3811         err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
3812                                        &err_cfg);
3813         if (err) {
3814                 dev_err(dev, "dpni_set_errors_behavior failed\n");
3815                 return err;
3816         }
3817
3818         /* Configure Rx and Tx conf queues to generate CDANs */
3819         for (i = 0; i < priv->num_fqs; i++) {
3820                 switch (priv->fq[i].type) {
3821                 case DPAA2_RX_FQ:
3822                         err = dpaa2_eth_setup_rx_flow(priv, &priv->fq[i]);
3823                         break;
3824                 case DPAA2_TX_CONF_FQ:
3825                         err = dpaa2_eth_setup_tx_flow(priv, &priv->fq[i]);
3826                         break;
3827                 case DPAA2_RX_ERR_FQ:
3828                         err = setup_rx_err_flow(priv, &priv->fq[i]);
3829                         break;
3830                 default:
3831                         dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
3832                         return -EINVAL;
3833                 }
3834                 if (err)
3835                         return err;
3836         }
3837
3838         err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token,
3839                             DPNI_QUEUE_TX, &priv->tx_qdid);
3840         if (err) {
3841                 dev_err(dev, "dpni_get_qdid() failed\n");
3842                 return err;
3843         }
3844
3845         return 0;
3846 }
3847
3848 /* Allocate rings for storing incoming frame descriptors */
3849 static int dpaa2_eth_alloc_rings(struct dpaa2_eth_priv *priv)
3850 {
3851         struct net_device *net_dev = priv->net_dev;
3852         struct device *dev = net_dev->dev.parent;
3853         int i;
3854
3855         for (i = 0; i < priv->num_channels; i++) {
3856                 priv->channel[i]->store =
3857                         dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev);
3858                 if (!priv->channel[i]->store) {
3859                         netdev_err(net_dev, "dpaa2_io_store_create() failed\n");
3860                         goto err_ring;
3861                 }
3862         }
3863
3864         return 0;
3865
3866 err_ring:
3867         for (i = 0; i < priv->num_channels; i++) {
3868                 if (!priv->channel[i]->store)
3869                         break;
3870                 dpaa2_io_store_destroy(priv->channel[i]->store);
3871         }
3872
3873         return -ENOMEM;
3874 }
3875
3876 static void dpaa2_eth_free_rings(struct dpaa2_eth_priv *priv)
3877 {
3878         int i;
3879
3880         for (i = 0; i < priv->num_channels; i++)
3881                 dpaa2_io_store_destroy(priv->channel[i]->store);
3882 }
3883
3884 static int dpaa2_eth_set_mac_addr(struct dpaa2_eth_priv *priv)
3885 {
3886         struct net_device *net_dev = priv->net_dev;
3887         struct device *dev = net_dev->dev.parent;
3888         u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN];
3889         int err;
3890
3891         /* Get firmware address, if any */
3892         err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr);
3893         if (err) {
3894                 dev_err(dev, "dpni_get_port_mac_addr() failed\n");
3895                 return err;
3896         }
3897
3898         /* Get DPNI attributes address, if any */
3899         err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
3900                                         dpni_mac_addr);
3901         if (err) {
3902                 dev_err(dev, "dpni_get_primary_mac_addr() failed\n");
3903                 return err;
3904         }
3905
3906         /* First check if firmware has any address configured by bootloader */
3907         if (!is_zero_ether_addr(mac_addr)) {
3908                 /* If the DPMAC addr != DPNI addr, update it */
3909                 if (!ether_addr_equal(mac_addr, dpni_mac_addr)) {
3910                         err = dpni_set_primary_mac_addr(priv->mc_io, 0,
3911                                                         priv->mc_token,
3912                                                         mac_addr);
3913                         if (err) {
3914                                 dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
3915                                 return err;
3916                         }
3917                 }
3918                 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
3919         } else if (is_zero_ether_addr(dpni_mac_addr)) {
3920                 /* No MAC address configured, fill in net_dev->dev_addr
3921                  * with a random one
3922                  */
3923                 eth_hw_addr_random(net_dev);
3924                 dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n");
3925
3926                 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
3927                                                 net_dev->dev_addr);
3928                 if (err) {
3929                         dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
3930                         return err;
3931                 }
3932
3933                 /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all
3934                  * practical purposes, this will be our "permanent" mac address,
3935                  * at least until the next reboot. This move will also permit
3936                  * register_netdevice() to properly fill up net_dev->perm_addr.
3937                  */
3938                 net_dev->addr_assign_type = NET_ADDR_PERM;
3939         } else {
3940                 /* NET_ADDR_PERM is default, all we have to do is
3941                  * fill in the device addr.
3942                  */
3943                 memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len);
3944         }
3945
3946         return 0;
3947 }
3948
3949 static int dpaa2_eth_netdev_init(struct net_device *net_dev)
3950 {
3951         struct device *dev = net_dev->dev.parent;
3952         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3953         u32 options = priv->dpni_attrs.options;
3954         u64 supported = 0, not_supported = 0;
3955         u8 bcast_addr[ETH_ALEN];
3956         u8 num_queues;
3957         int err;
3958
3959         net_dev->netdev_ops = &dpaa2_eth_ops;
3960         net_dev->ethtool_ops = &dpaa2_ethtool_ops;
3961
3962         err = dpaa2_eth_set_mac_addr(priv);
3963         if (err)
3964                 return err;
3965
3966         /* Explicitly add the broadcast address to the MAC filtering table */
3967         eth_broadcast_addr(bcast_addr);
3968         err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr);
3969         if (err) {
3970                 dev_err(dev, "dpni_add_mac_addr() failed\n");
3971                 return err;
3972         }
3973
3974         /* Set MTU upper limit; lower limit is 68B (default value) */
3975         net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
3976         err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
3977                                         DPAA2_ETH_MFL);
3978         if (err) {
3979                 dev_err(dev, "dpni_set_max_frame_length() failed\n");
3980                 return err;
3981         }
3982
3983         /* Set actual number of queues in the net device */
3984         num_queues = dpaa2_eth_queue_count(priv);
3985         err = netif_set_real_num_tx_queues(net_dev, num_queues);
3986         if (err) {
3987                 dev_err(dev, "netif_set_real_num_tx_queues() failed\n");
3988                 return err;
3989         }
3990         err = netif_set_real_num_rx_queues(net_dev, num_queues);
3991         if (err) {
3992                 dev_err(dev, "netif_set_real_num_rx_queues() failed\n");
3993                 return err;
3994         }
3995
3996         /* Capabilities listing */
3997         supported |= IFF_LIVE_ADDR_CHANGE;
3998
3999         if (options & DPNI_OPT_NO_MAC_FILTER)
4000                 not_supported |= IFF_UNICAST_FLT;
4001         else
4002                 supported |= IFF_UNICAST_FLT;
4003
4004         net_dev->priv_flags |= supported;
4005         net_dev->priv_flags &= ~not_supported;
4006
4007         /* Features */
4008         net_dev->features = NETIF_F_RXCSUM |
4009                             NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4010                             NETIF_F_SG | NETIF_F_HIGHDMA |
4011                             NETIF_F_LLTX | NETIF_F_HW_TC;
4012         net_dev->hw_features = net_dev->features;
4013
4014         return 0;
4015 }
4016
4017 static int dpaa2_eth_poll_link_state(void *arg)
4018 {
4019         struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg;
4020         int err;
4021
4022         while (!kthread_should_stop()) {
4023                 err = dpaa2_eth_link_state_update(priv);
4024                 if (unlikely(err))
4025                         return err;
4026
4027                 msleep(DPAA2_ETH_LINK_STATE_REFRESH);
4028         }
4029
4030         return 0;
4031 }
4032
4033 static int dpaa2_eth_connect_mac(struct dpaa2_eth_priv *priv)
4034 {
4035         struct fsl_mc_device *dpni_dev, *dpmac_dev;
4036         struct dpaa2_mac *mac;
4037         int err;
4038
4039         dpni_dev = to_fsl_mc_device(priv->net_dev->dev.parent);
4040         dpmac_dev = fsl_mc_get_endpoint(dpni_dev);
4041         if (IS_ERR_OR_NULL(dpmac_dev) || dpmac_dev->dev.type != &fsl_mc_bus_dpmac_type)
4042                 return 0;
4043
4044         if (dpaa2_mac_is_type_fixed(dpmac_dev, priv->mc_io))
4045                 return 0;
4046
4047         mac = kzalloc(sizeof(struct dpaa2_mac), GFP_KERNEL);
4048         if (!mac)
4049                 return -ENOMEM;
4050
4051         mac->mc_dev = dpmac_dev;
4052         mac->mc_io = priv->mc_io;
4053         mac->net_dev = priv->net_dev;
4054
4055         err = dpaa2_mac_connect(mac);
4056         if (err) {
4057                 netdev_err(priv->net_dev, "Error connecting to the MAC endpoint\n");
4058                 kfree(mac);
4059                 return err;
4060         }
4061         priv->mac = mac;
4062
4063         return 0;
4064 }
4065
4066 static void dpaa2_eth_disconnect_mac(struct dpaa2_eth_priv *priv)
4067 {
4068         if (!priv->mac)
4069                 return;
4070
4071         dpaa2_mac_disconnect(priv->mac);
4072         kfree(priv->mac);
4073         priv->mac = NULL;
4074 }
4075
4076 static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
4077 {
4078         u32 status = ~0;
4079         struct device *dev = (struct device *)arg;
4080         struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
4081         struct net_device *net_dev = dev_get_drvdata(dev);
4082         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
4083         int err;
4084
4085         err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
4086                                   DPNI_IRQ_INDEX, &status);
4087         if (unlikely(err)) {
4088                 netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
4089                 return IRQ_HANDLED;
4090         }
4091
4092         if (status & DPNI_IRQ_EVENT_LINK_CHANGED)
4093                 dpaa2_eth_link_state_update(netdev_priv(net_dev));
4094
4095         if (status & DPNI_IRQ_EVENT_ENDPOINT_CHANGED) {
4096                 dpaa2_eth_set_mac_addr(netdev_priv(net_dev));
4097                 dpaa2_eth_update_tx_fqids(priv);
4098
4099                 rtnl_lock();
4100                 if (priv->mac)
4101                         dpaa2_eth_disconnect_mac(priv);
4102                 else
4103                         dpaa2_eth_connect_mac(priv);
4104                 rtnl_unlock();
4105         }
4106
4107         return IRQ_HANDLED;
4108 }
4109
4110 static int dpaa2_eth_setup_irqs(struct fsl_mc_device *ls_dev)
4111 {
4112         int err = 0;
4113         struct fsl_mc_device_irq *irq;
4114
4115         err = fsl_mc_allocate_irqs(ls_dev);
4116         if (err) {
4117                 dev_err(&ls_dev->dev, "MC irqs allocation failed\n");
4118                 return err;
4119         }
4120
4121         irq = ls_dev->irqs[0];
4122         err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq,
4123                                         NULL, dpni_irq0_handler_thread,
4124                                         IRQF_NO_SUSPEND | IRQF_ONESHOT,
4125                                         dev_name(&ls_dev->dev), &ls_dev->dev);
4126         if (err < 0) {
4127                 dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err);
4128                 goto free_mc_irq;
4129         }
4130
4131         err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle,
4132                                 DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED |
4133                                 DPNI_IRQ_EVENT_ENDPOINT_CHANGED);
4134         if (err < 0) {
4135                 dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err);
4136                 goto free_irq;
4137         }
4138
4139         err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle,
4140                                   DPNI_IRQ_INDEX, 1);
4141         if (err < 0) {
4142                 dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err);
4143                 goto free_irq;
4144         }
4145
4146         return 0;
4147
4148 free_irq:
4149         devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev);
4150 free_mc_irq:
4151         fsl_mc_free_irqs(ls_dev);
4152
4153         return err;
4154 }
4155
4156 static void dpaa2_eth_add_ch_napi(struct dpaa2_eth_priv *priv)
4157 {
4158         int i;
4159         struct dpaa2_eth_channel *ch;
4160
4161         for (i = 0; i < priv->num_channels; i++) {
4162                 ch = priv->channel[i];
4163                 /* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */
4164                 netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll,
4165                                NAPI_POLL_WEIGHT);
4166         }
4167 }
4168
4169 static void dpaa2_eth_del_ch_napi(struct dpaa2_eth_priv *priv)
4170 {
4171         int i;
4172         struct dpaa2_eth_channel *ch;
4173
4174         for (i = 0; i < priv->num_channels; i++) {
4175                 ch = priv->channel[i];
4176                 netif_napi_del(&ch->napi);
4177         }
4178 }
4179
4180 static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
4181 {
4182         struct device *dev;
4183         struct net_device *net_dev = NULL;
4184         struct dpaa2_eth_priv *priv = NULL;
4185         int err = 0;
4186
4187         dev = &dpni_dev->dev;
4188
4189         /* Net device */
4190         net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_NETDEV_QUEUES);
4191         if (!net_dev) {
4192                 dev_err(dev, "alloc_etherdev_mq() failed\n");
4193                 return -ENOMEM;
4194         }
4195
4196         SET_NETDEV_DEV(net_dev, dev);
4197         dev_set_drvdata(dev, net_dev);
4198
4199         priv = netdev_priv(net_dev);
4200         priv->net_dev = net_dev;
4201
4202         priv->iommu_domain = iommu_get_domain_for_dev(dev);
4203
4204         priv->tx_tstamp_type = HWTSTAMP_TX_OFF;
4205         priv->rx_tstamp = false;
4206
4207         priv->dpaa2_ptp_wq = alloc_workqueue("dpaa2_ptp_wq", 0, 0);
4208         if (!priv->dpaa2_ptp_wq) {
4209                 err = -ENOMEM;
4210                 goto err_wq_alloc;
4211         }
4212
4213         INIT_WORK(&priv->tx_onestep_tstamp, dpaa2_eth_tx_onestep_tstamp);
4214
4215         skb_queue_head_init(&priv->tx_skbs);
4216
4217         /* Obtain a MC portal */
4218         err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
4219                                      &priv->mc_io);
4220         if (err) {
4221                 if (err == -ENXIO)
4222                         err = -EPROBE_DEFER;
4223                 else
4224                         dev_err(dev, "MC portal allocation failed\n");
4225                 goto err_portal_alloc;
4226         }
4227
4228         /* MC objects initialization and configuration */
4229         err = dpaa2_eth_setup_dpni(dpni_dev);
4230         if (err)
4231                 goto err_dpni_setup;
4232
4233         err = dpaa2_eth_setup_dpio(priv);
4234         if (err)
4235                 goto err_dpio_setup;
4236
4237         dpaa2_eth_setup_fqs(priv);
4238
4239         err = dpaa2_eth_setup_dpbp(priv);
4240         if (err)
4241                 goto err_dpbp_setup;
4242
4243         err = dpaa2_eth_bind_dpni(priv);
4244         if (err)
4245                 goto err_bind;
4246
4247         /* Add a NAPI context for each channel */
4248         dpaa2_eth_add_ch_napi(priv);
4249
4250         /* Percpu statistics */
4251         priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
4252         if (!priv->percpu_stats) {
4253                 dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
4254                 err = -ENOMEM;
4255                 goto err_alloc_percpu_stats;
4256         }
4257         priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
4258         if (!priv->percpu_extras) {
4259                 dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
4260                 err = -ENOMEM;
4261                 goto err_alloc_percpu_extras;
4262         }
4263
4264         priv->sgt_cache = alloc_percpu(*priv->sgt_cache);
4265         if (!priv->sgt_cache) {
4266                 dev_err(dev, "alloc_percpu(sgt_cache) failed\n");
4267                 err = -ENOMEM;
4268                 goto err_alloc_sgt_cache;
4269         }
4270
4271         err = dpaa2_eth_netdev_init(net_dev);
4272         if (err)
4273                 goto err_netdev_init;
4274
4275         /* Configure checksum offload based on current interface flags */
4276         err = dpaa2_eth_set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
4277         if (err)
4278                 goto err_csum;
4279
4280         err = dpaa2_eth_set_tx_csum(priv,
4281                                     !!(net_dev->features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
4282         if (err)
4283                 goto err_csum;
4284
4285         err = dpaa2_eth_alloc_rings(priv);
4286         if (err)
4287                 goto err_alloc_rings;
4288
4289 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
4290         if (dpaa2_eth_has_pause_support(priv) && priv->vlan_cls_enabled) {
4291                 priv->dcbx_mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4292                 net_dev->dcbnl_ops = &dpaa2_eth_dcbnl_ops;
4293         } else {
4294                 dev_dbg(dev, "PFC not supported\n");
4295         }
4296 #endif
4297
4298         err = dpaa2_eth_setup_irqs(dpni_dev);
4299         if (err) {
4300                 netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n");
4301                 priv->poll_thread = kthread_run(dpaa2_eth_poll_link_state, priv,
4302                                                 "%s_poll_link", net_dev->name);
4303                 if (IS_ERR(priv->poll_thread)) {
4304                         dev_err(dev, "Error starting polling thread\n");
4305                         goto err_poll_thread;
4306                 }
4307                 priv->do_link_poll = true;
4308         }
4309
4310         err = dpaa2_eth_connect_mac(priv);
4311         if (err)
4312                 goto err_connect_mac;
4313
4314         err = dpaa2_eth_dl_register(priv);
4315         if (err)
4316                 goto err_dl_register;
4317
4318         err = dpaa2_eth_dl_traps_register(priv);
4319         if (err)
4320                 goto err_dl_trap_register;
4321
4322         err = dpaa2_eth_dl_port_add(priv);
4323         if (err)
4324                 goto err_dl_port_add;
4325
4326         err = register_netdev(net_dev);
4327         if (err < 0) {
4328                 dev_err(dev, "register_netdev() failed\n");
4329                 goto err_netdev_reg;
4330         }
4331
4332 #ifdef CONFIG_DEBUG_FS
4333         dpaa2_dbg_add(priv);
4334 #endif
4335
4336         dev_info(dev, "Probed interface %s\n", net_dev->name);
4337         return 0;
4338
4339 err_netdev_reg:
4340         dpaa2_eth_dl_port_del(priv);
4341 err_dl_port_add:
4342         dpaa2_eth_dl_traps_unregister(priv);
4343 err_dl_trap_register:
4344         dpaa2_eth_dl_unregister(priv);
4345 err_dl_register:
4346         dpaa2_eth_disconnect_mac(priv);
4347 err_connect_mac:
4348         if (priv->do_link_poll)
4349                 kthread_stop(priv->poll_thread);
4350         else
4351                 fsl_mc_free_irqs(dpni_dev);
4352 err_poll_thread:
4353         dpaa2_eth_free_rings(priv);
4354 err_alloc_rings:
4355 err_csum:
4356 err_netdev_init:
4357         free_percpu(priv->sgt_cache);
4358 err_alloc_sgt_cache:
4359         free_percpu(priv->percpu_extras);
4360 err_alloc_percpu_extras:
4361         free_percpu(priv->percpu_stats);
4362 err_alloc_percpu_stats:
4363         dpaa2_eth_del_ch_napi(priv);
4364 err_bind:
4365         dpaa2_eth_free_dpbp(priv);
4366 err_dpbp_setup:
4367         dpaa2_eth_free_dpio(priv);
4368 err_dpio_setup:
4369         dpaa2_eth_free_dpni(priv);
4370 err_dpni_setup:
4371         fsl_mc_portal_free(priv->mc_io);
4372 err_portal_alloc:
4373         destroy_workqueue(priv->dpaa2_ptp_wq);
4374 err_wq_alloc:
4375         dev_set_drvdata(dev, NULL);
4376         free_netdev(net_dev);
4377
4378         return err;
4379 }
4380
4381 static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
4382 {
4383         struct device *dev;
4384         struct net_device *net_dev;
4385         struct dpaa2_eth_priv *priv;
4386
4387         dev = &ls_dev->dev;
4388         net_dev = dev_get_drvdata(dev);
4389         priv = netdev_priv(net_dev);
4390
4391 #ifdef CONFIG_DEBUG_FS
4392         dpaa2_dbg_remove(priv);
4393 #endif
4394         rtnl_lock();
4395         dpaa2_eth_disconnect_mac(priv);
4396         rtnl_unlock();
4397
4398         unregister_netdev(net_dev);
4399
4400         dpaa2_eth_dl_port_del(priv);
4401         dpaa2_eth_dl_traps_unregister(priv);
4402         dpaa2_eth_dl_unregister(priv);
4403
4404         if (priv->do_link_poll)
4405                 kthread_stop(priv->poll_thread);
4406         else
4407                 fsl_mc_free_irqs(ls_dev);
4408
4409         dpaa2_eth_free_rings(priv);
4410         free_percpu(priv->sgt_cache);
4411         free_percpu(priv->percpu_stats);
4412         free_percpu(priv->percpu_extras);
4413
4414         dpaa2_eth_del_ch_napi(priv);
4415         dpaa2_eth_free_dpbp(priv);
4416         dpaa2_eth_free_dpio(priv);
4417         dpaa2_eth_free_dpni(priv);
4418
4419         fsl_mc_portal_free(priv->mc_io);
4420
4421         free_netdev(net_dev);
4422
4423         dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
4424
4425         return 0;
4426 }
4427
4428 static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = {
4429         {
4430                 .vendor = FSL_MC_VENDOR_FREESCALE,
4431                 .obj_type = "dpni",
4432         },
4433         { .vendor = 0x0 }
4434 };
4435 MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table);
4436
4437 static struct fsl_mc_driver dpaa2_eth_driver = {
4438         .driver = {
4439                 .name = KBUILD_MODNAME,
4440                 .owner = THIS_MODULE,
4441         },
4442         .probe = dpaa2_eth_probe,
4443         .remove = dpaa2_eth_remove,
4444         .match_id_table = dpaa2_eth_match_id_table
4445 };
4446
4447 static int __init dpaa2_eth_driver_init(void)
4448 {
4449         int err;
4450
4451         dpaa2_eth_dbg_init();
4452         err = fsl_mc_driver_register(&dpaa2_eth_driver);
4453         if (err) {
4454                 dpaa2_eth_dbg_exit();
4455                 return err;
4456         }
4457
4458         return 0;
4459 }
4460
4461 static void __exit dpaa2_eth_driver_exit(void)
4462 {
4463         dpaa2_eth_dbg_exit();
4464         fsl_mc_driver_unregister(&dpaa2_eth_driver);
4465 }
4466
4467 module_init(dpaa2_eth_driver_init);
4468 module_exit(dpaa2_eth_driver_exit);