1 // SPDX-License-Identifier: GPL-2.0
2 /* Ethernet device driver for Cortina Systems Gemini SoC
3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
4 * Net Engine and Gigabit Ethernet MAC (GMAC)
5 * This hardware contains a TCP Offload Engine (TOE) but currently the
6 * driver does not make use of it.
9 * Linus Walleij <linus.walleij@linaro.org>
10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT)
11 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
12 * Paulius Zaleckas <paulius.zaleckas@gmail.com>
13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it>
14 * Gary Chen & Ch Hsu Storlink Semiconductor
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/slab.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/cache.h>
24 #include <linux/interrupt.h>
25 #include <linux/reset.h>
26 #include <linux/clk.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/of_platform.h>
31 #include <linux/etherdevice.h>
32 #include <linux/if_vlan.h>
33 #include <linux/skbuff.h>
34 #include <linux/phy.h>
35 #include <linux/crc32.h>
36 #include <linux/ethtool.h>
37 #include <linux/tcp.h>
38 #include <linux/u64_stats_sync.h>
42 #include <linux/ipv6.h>
46 #define DRV_NAME "gmac-gemini"
48 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
49 static int debug = -1;
50 module_param(debug, int, 0);
51 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
57 #define HBURST_SINGLE 0x00
58 #define HBURST_INCR 0x01
59 #define HBURST_INCR4 0x02
60 #define HBURST_INCR8 0x03
62 #define HPROT_DATA_CACHE BIT(0)
63 #define HPROT_PRIVILIGED BIT(1)
64 #define HPROT_BUFFERABLE BIT(2)
65 #define HPROT_CACHABLE BIT(3)
67 #define DEFAULT_RX_COALESCE_NSECS 0
68 #define DEFAULT_GMAC_RXQ_ORDER 9
69 #define DEFAULT_GMAC_TXQ_ORDER 8
70 #define DEFAULT_RX_BUF_ORDER 11
71 #define DEFAULT_NAPI_WEIGHT 64
72 #define TX_MAX_FRAGS 16
73 #define TX_QUEUE_NUM 1 /* max: 6 */
74 #define RX_MAX_ALLOC_ORDER 2
76 #define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
77 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
78 #define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
79 GMAC0_SWTQ00_FIN_INT_BIT)
80 #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
82 #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
83 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
84 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
87 * struct gmac_queue_page - page buffer per-page info
88 * @page: the page struct
89 * @mapping: the dma address handle
91 struct gmac_queue_page {
97 struct gmac_txdesc *ring;
100 unsigned int noirq_packets;
103 struct gemini_ethernet;
105 struct gemini_ethernet_port {
108 struct gemini_ethernet *geth;
109 struct net_device *netdev;
111 void __iomem *dma_base;
112 void __iomem *gmac_base;
114 struct reset_control *reset;
118 void __iomem *rxq_rwptr;
119 struct gmac_rxdesc *rxq_ring;
120 unsigned int rxq_order;
122 struct napi_struct napi;
123 struct hrtimer rx_coalesce_timer;
124 unsigned int rx_coalesce_nsecs;
125 unsigned int freeq_refill;
126 struct gmac_txq txq[TX_QUEUE_NUM];
127 unsigned int txq_order;
128 unsigned int irq_every_tx_packets;
130 dma_addr_t rxq_dma_base;
131 dma_addr_t txq_dma_base;
133 unsigned int msg_enable;
134 spinlock_t config_lock; /* Locks config register */
136 struct u64_stats_sync tx_stats_syncp;
137 struct u64_stats_sync rx_stats_syncp;
138 struct u64_stats_sync ir_stats_syncp;
140 struct rtnl_link_stats64 stats;
141 u64 hw_stats[RX_STATS_NUM];
142 u64 rx_stats[RX_STATUS_NUM];
143 u64 rx_csum_stats[RX_CHKSUM_NUM];
145 u64 tx_frag_stats[TX_MAX_FRAGS];
146 u64 tx_frags_linearized;
150 struct gemini_ethernet {
153 struct gemini_ethernet_port *port0;
154 struct gemini_ethernet_port *port1;
157 spinlock_t irq_lock; /* Locks IRQ-related registers */
158 unsigned int freeq_order;
159 unsigned int freeq_frag_order;
160 struct gmac_rxdesc *freeq_ring;
161 dma_addr_t freeq_dma_base;
162 struct gmac_queue_page *freeq_pages;
163 unsigned int num_freeq_pages;
164 spinlock_t freeq_lock; /* Locks queue from reentrance */
167 #define GMAC_STATS_NUM ( \
168 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
171 static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
178 "RX_STATUS_GOOD_FRAME",
179 "RX_STATUS_TOO_LONG_GOOD_CRC",
180 "RX_STATUS_RUNT_FRAME",
181 "RX_STATUS_SFD_NOT_FOUND",
182 "RX_STATUS_CRC_ERROR",
183 "RX_STATUS_TOO_LONG_BAD_CRC",
184 "RX_STATUS_ALIGNMENT_ERROR",
185 "RX_STATUS_TOO_LONG_BAD_ALIGN",
187 "RX_STATUS_DA_FILTERED",
188 "RX_STATUS_BUFFER_FULL",
194 "RX_CHKSUM_IP_UDP_TCP_OK",
195 "RX_CHKSUM_IP_OK_ONLY",
198 "RX_CHKSUM_IP_ERR_UNKNOWN",
200 "RX_CHKSUM_TCP_UDP_ERR",
219 "TX_FRAGS_LINEARIZED",
223 static void gmac_dump_dma_state(struct net_device *netdev);
225 static void gmac_update_config0_reg(struct net_device *netdev,
228 struct gemini_ethernet_port *port = netdev_priv(netdev);
232 spin_lock_irqsave(&port->config_lock, flags);
234 reg = readl(port->gmac_base + GMAC_CONFIG0);
235 reg = (reg & ~vmask) | val;
236 writel(reg, port->gmac_base + GMAC_CONFIG0);
238 spin_unlock_irqrestore(&port->config_lock, flags);
241 static void gmac_enable_tx_rx(struct net_device *netdev)
243 struct gemini_ethernet_port *port = netdev_priv(netdev);
247 spin_lock_irqsave(&port->config_lock, flags);
249 reg = readl(port->gmac_base + GMAC_CONFIG0);
250 reg &= ~CONFIG0_TX_RX_DISABLE;
251 writel(reg, port->gmac_base + GMAC_CONFIG0);
253 spin_unlock_irqrestore(&port->config_lock, flags);
256 static void gmac_disable_tx_rx(struct net_device *netdev)
258 struct gemini_ethernet_port *port = netdev_priv(netdev);
262 spin_lock_irqsave(&port->config_lock, flags);
264 val = readl(port->gmac_base + GMAC_CONFIG0);
265 val |= CONFIG0_TX_RX_DISABLE;
266 writel(val, port->gmac_base + GMAC_CONFIG0);
268 spin_unlock_irqrestore(&port->config_lock, flags);
270 mdelay(10); /* let GMAC consume packet */
273 static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
275 struct gemini_ethernet_port *port = netdev_priv(netdev);
279 spin_lock_irqsave(&port->config_lock, flags);
281 val = readl(port->gmac_base + GMAC_CONFIG0);
282 val &= ~CONFIG0_FLOW_CTL;
284 val |= CONFIG0_FLOW_TX;
286 val |= CONFIG0_FLOW_RX;
287 writel(val, port->gmac_base + GMAC_CONFIG0);
289 spin_unlock_irqrestore(&port->config_lock, flags);
292 static void gmac_speed_set(struct net_device *netdev)
294 struct gemini_ethernet_port *port = netdev_priv(netdev);
295 struct phy_device *phydev = netdev->phydev;
296 union gmac_status status, old_status;
300 status.bits32 = readl(port->gmac_base + GMAC_STATUS);
301 old_status.bits32 = status.bits32;
302 status.bits.link = phydev->link;
303 status.bits.duplex = phydev->duplex;
305 switch (phydev->speed) {
307 status.bits.speed = GMAC_SPEED_1000;
308 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
309 status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
310 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n",
311 phydev_name(phydev));
314 status.bits.speed = GMAC_SPEED_100;
315 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
316 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
317 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n",
318 phydev_name(phydev));
321 status.bits.speed = GMAC_SPEED_10;
322 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
323 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
324 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n",
325 phydev_name(phydev));
328 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n",
329 phydev->speed, phydev_name(phydev));
332 if (phydev->duplex == DUPLEX_FULL) {
333 u16 lcladv = phy_read(phydev, MII_ADVERTISE);
334 u16 rmtadv = phy_read(phydev, MII_LPA);
335 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
337 if (cap & FLOW_CTRL_RX)
339 if (cap & FLOW_CTRL_TX)
343 gmac_set_flow_control(netdev, pause_tx, pause_rx);
345 if (old_status.bits32 == status.bits32)
348 if (netif_msg_link(port)) {
349 phy_print_status(phydev);
350 netdev_info(netdev, "link flow control: %s\n",
352 ? (phydev->asym_pause ? "tx" : "both")
353 : (phydev->asym_pause ? "rx" : "none")
357 gmac_disable_tx_rx(netdev);
358 writel(status.bits32, port->gmac_base + GMAC_STATUS);
359 gmac_enable_tx_rx(netdev);
362 static int gmac_setup_phy(struct net_device *netdev)
364 struct gemini_ethernet_port *port = netdev_priv(netdev);
365 union gmac_status status = { .bits32 = 0 };
366 struct device *dev = port->dev;
367 struct phy_device *phy;
369 phy = of_phy_get_and_connect(netdev,
374 netdev->phydev = phy;
376 phy_set_max_speed(phy, SPEED_1000);
377 phy_support_asym_pause(phy);
379 /* set PHY interface type */
380 switch (phy->interface) {
381 case PHY_INTERFACE_MODE_MII:
383 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n");
384 status.bits.mii_rmii = GMAC_PHY_MII;
386 case PHY_INTERFACE_MODE_GMII:
388 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n");
389 status.bits.mii_rmii = GMAC_PHY_GMII;
391 case PHY_INTERFACE_MODE_RGMII:
393 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n");
394 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
397 netdev_err(netdev, "Unsupported MII interface\n");
399 netdev->phydev = NULL;
402 writel(status.bits32, port->gmac_base + GMAC_STATUS);
404 if (netif_msg_link(port))
405 phy_attached_info(phy);
410 /* The maximum frame length is not logically enumerated in the
411 * hardware, so we do a table lookup to find the applicable max
414 struct gmac_max_framelen {
415 unsigned int max_l3_len;
419 static const struct gmac_max_framelen gmac_maxlens[] = {
422 .val = CONFIG0_MAXLEN_1518,
426 .val = CONFIG0_MAXLEN_1522,
430 .val = CONFIG0_MAXLEN_1536,
434 .val = CONFIG0_MAXLEN_1542,
438 .val = CONFIG0_MAXLEN_9k,
442 .val = CONFIG0_MAXLEN_10k,
446 static int gmac_pick_rx_max_len(unsigned int max_l3_len)
448 const struct gmac_max_framelen *maxlen;
452 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN;
454 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) {
455 maxlen = &gmac_maxlens[i];
456 if (maxtot <= maxlen->max_l3_len)
463 static int gmac_init(struct net_device *netdev)
465 struct gemini_ethernet_port *port = netdev_priv(netdev);
466 union gmac_config0 config0 = { .bits = {
477 .port0_chk_classq = 1,
478 .port1_chk_classq = 1,
480 union gmac_ahb_weight ahb_weight = { .bits = {
485 .tq_dv_threshold = 0,
487 union gmac_tx_wcr0 hw_weigh = { .bits = {
493 union gmac_tx_wcr1 sw_weigh = { .bits = {
501 union gmac_config1 config1 = { .bits = {
505 union gmac_config2 config2 = { .bits = {
509 union gmac_config3 config3 = { .bits = {
513 union gmac_config0 tmp;
515 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
516 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
517 config0.bits.reserved = tmp.bits.reserved;
518 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
519 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
520 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
521 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
523 readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
524 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
526 writel(hw_weigh.bits32,
527 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
528 writel(sw_weigh.bits32,
529 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
531 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
532 port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
533 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
535 /* Mark every quarter of the queue a packet for interrupt
536 * in order to be able to wake up the queue if it was stopped
538 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
543 static int gmac_setup_txqs(struct net_device *netdev)
545 struct gemini_ethernet_port *port = netdev_priv(netdev);
546 unsigned int n_txq = netdev->num_tx_queues;
547 struct gemini_ethernet *geth = port->geth;
548 size_t entries = 1 << port->txq_order;
549 struct gmac_txq *txq = port->txq;
550 struct gmac_txdesc *desc_ring;
551 size_t len = n_txq * entries;
552 struct sk_buff **skb_tab;
553 void __iomem *rwptr_reg;
557 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
559 skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
563 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
564 &port->txq_dma_base, GFP_KERNEL);
571 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
572 dev_warn(geth->dev, "TX queue base is not aligned\n");
573 dma_free_coherent(geth->dev, len * sizeof(*desc_ring),
574 desc_ring, port->txq_dma_base);
579 writel(port->txq_dma_base | port->txq_order,
580 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
582 for (i = 0; i < n_txq; i++) {
583 txq->ring = desc_ring;
585 txq->noirq_packets = 0;
587 r = readw(rwptr_reg);
589 writew(r, rwptr_reg);
594 desc_ring += entries;
601 static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
604 struct gemini_ethernet_port *port = netdev_priv(netdev);
605 unsigned int m = (1 << port->txq_order) - 1;
606 struct gemini_ethernet *geth = port->geth;
607 unsigned int c = txq->cptr;
608 union gmac_txdesc_0 word0;
609 union gmac_txdesc_1 word1;
610 unsigned int hwchksum = 0;
611 unsigned long bytes = 0;
612 struct gmac_txdesc *txd;
613 unsigned short nfrags;
614 unsigned int errs = 0;
615 unsigned int pkts = 0;
626 mapping = txd->word2.buf_adr;
627 word3 = txd->word3.bits32;
629 dma_unmap_single(geth->dev, mapping,
630 word0.bits.buffer_size, DMA_TO_DEVICE);
633 dev_kfree_skb(txq->skb[c]);
638 if (!(word3 & SOF_BIT))
641 if (!word0.bits.status_tx_ok) {
647 bytes += txd->word1.bits.byte_count;
649 if (word1.bits32 & TSS_CHECKUM_ENABLE)
652 nfrags = word0.bits.desc_count - 1;
654 if (nfrags >= TX_MAX_FRAGS)
655 nfrags = TX_MAX_FRAGS - 1;
657 u64_stats_update_begin(&port->tx_stats_syncp);
658 port->tx_frag_stats[nfrags]++;
659 u64_stats_update_end(&port->tx_stats_syncp);
663 u64_stats_update_begin(&port->ir_stats_syncp);
664 port->stats.tx_errors += errs;
665 port->stats.tx_packets += pkts;
666 port->stats.tx_bytes += bytes;
667 port->tx_hw_csummed += hwchksum;
668 u64_stats_update_end(&port->ir_stats_syncp);
673 static void gmac_cleanup_txqs(struct net_device *netdev)
675 struct gemini_ethernet_port *port = netdev_priv(netdev);
676 unsigned int n_txq = netdev->num_tx_queues;
677 struct gemini_ethernet *geth = port->geth;
678 void __iomem *rwptr_reg;
681 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
683 for (i = 0; i < n_txq; i++) {
684 r = readw(rwptr_reg);
686 writew(r, rwptr_reg);
689 gmac_clean_txq(netdev, port->txq + i, r);
691 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
693 kfree(port->txq->skb);
694 dma_free_coherent(geth->dev,
695 n_txq * sizeof(*port->txq->ring) << port->txq_order,
696 port->txq->ring, port->txq_dma_base);
699 static int gmac_setup_rxq(struct net_device *netdev)
701 struct gemini_ethernet_port *port = netdev_priv(netdev);
702 struct gemini_ethernet *geth = port->geth;
703 struct nontoe_qhdr __iomem *qhdr;
705 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
706 port->rxq_rwptr = &qhdr->word1;
708 /* Remap a slew of memory to use for the RX queue */
709 port->rxq_ring = dma_alloc_coherent(geth->dev,
710 sizeof(*port->rxq_ring) << port->rxq_order,
711 &port->rxq_dma_base, GFP_KERNEL);
714 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
715 dev_warn(geth->dev, "RX queue base is not aligned\n");
719 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
720 writel(0, port->rxq_rwptr);
724 static struct gmac_queue_page *
725 gmac_get_queue_page(struct gemini_ethernet *geth,
726 struct gemini_ethernet_port *port,
729 struct gmac_queue_page *gpage;
733 /* Only look for even pages */
734 mapping = addr & PAGE_MASK;
736 if (!geth->freeq_pages) {
737 dev_err(geth->dev, "try to get page with no page list\n");
741 /* Look up a ring buffer page from virtual mapping */
742 for (i = 0; i < geth->num_freeq_pages; i++) {
743 gpage = &geth->freeq_pages[i];
744 if (gpage->mapping == mapping)
751 static void gmac_cleanup_rxq(struct net_device *netdev)
753 struct gemini_ethernet_port *port = netdev_priv(netdev);
754 struct gemini_ethernet *geth = port->geth;
755 struct gmac_rxdesc *rxd = port->rxq_ring;
756 static struct gmac_queue_page *gpage;
757 struct nontoe_qhdr __iomem *qhdr;
758 void __iomem *dma_reg;
759 void __iomem *ptr_reg;
765 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
766 dma_reg = &qhdr->word0;
767 ptr_reg = &qhdr->word1;
769 rw.bits32 = readl(ptr_reg);
772 writew(r, ptr_reg + 2);
776 /* Loop from read pointer to write pointer of the RX queue
777 * and free up all pages by the queue.
780 mapping = rxd[r].word2.buf_adr;
782 r &= ((1 << port->rxq_order) - 1);
787 /* Freeq pointers are one page off */
788 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
790 dev_err(geth->dev, "could not find page\n");
793 /* Release the RX queue reference to the page */
794 put_page(gpage->page);
797 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
798 port->rxq_ring, port->rxq_dma_base);
801 static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
804 struct gmac_rxdesc *freeq_entry;
805 struct gmac_queue_page *gpage;
806 unsigned int fpp_order;
807 unsigned int frag_len;
812 /* First allocate and DMA map a single page */
813 page = alloc_page(GFP_ATOMIC);
817 mapping = dma_map_single(geth->dev, page_address(page),
818 PAGE_SIZE, DMA_FROM_DEVICE);
819 if (dma_mapping_error(geth->dev, mapping)) {
824 /* The assign the page mapping (physical address) to the buffer address
825 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
826 * 4k), and the default RX frag order is 11 (fragments are up 20 2048
827 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
828 * each page normally needs two entries in the queue.
830 frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
831 fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
832 freeq_entry = geth->freeq_ring + (pn << fpp_order);
833 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
834 pn, frag_len, (1 << fpp_order), freeq_entry);
835 for (i = (1 << fpp_order); i > 0; i--) {
836 freeq_entry->word2.buf_adr = mapping;
841 /* If the freeq entry already has a page mapped, then unmap it. */
842 gpage = &geth->freeq_pages[pn];
844 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
845 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
846 /* This should be the last reference to the page so it gets
849 put_page(gpage->page);
852 /* Then put our new mapping into the page table */
853 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
854 pn, (unsigned int)mapping, page);
855 gpage->mapping = mapping;
862 * geth_fill_freeq() - Fill the freeq with empty fragments to use
863 * @geth: the ethernet adapter
864 * @refill: whether to reset the queue by filling in all freeq entries or
865 * just refill it, usually the interrupt to refill the queue happens when
866 * the queue is half empty.
868 static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
870 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
871 unsigned int count = 0;
872 unsigned int pn, epn;
878 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
880 spin_lock_irqsave(&geth->freeq_lock, flags);
882 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
883 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
884 epn = (rw.bits.rptr >> fpp_order) - 1;
887 /* Loop over the freeq ring buffer entries */
889 struct gmac_queue_page *gpage;
892 gpage = &geth->freeq_pages[pn];
895 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
896 pn, page_ref_count(page), 1 << fpp_order);
898 if (page_ref_count(page) > 1) {
899 unsigned int fl = (pn - epn) & m_pn;
901 if (fl > 64 >> fpp_order)
904 page = geth_freeq_alloc_map_page(geth, pn);
909 /* Add one reference per fragment in the page */
910 page_ref_add(page, 1 << fpp_order);
911 count += 1 << fpp_order;
916 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
918 spin_unlock_irqrestore(&geth->freeq_lock, flags);
923 static int geth_setup_freeq(struct gemini_ethernet *geth)
925 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
926 unsigned int frag_len = 1 << geth->freeq_frag_order;
927 unsigned int len = 1 << geth->freeq_order;
928 unsigned int pages = len >> fpp_order;
929 union queue_threshold qt;
930 union dma_skb_size skbsz;
934 geth->freeq_ring = dma_alloc_coherent(geth->dev,
935 sizeof(*geth->freeq_ring) << geth->freeq_order,
936 &geth->freeq_dma_base, GFP_KERNEL);
937 if (!geth->freeq_ring)
939 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
940 dev_warn(geth->dev, "queue ring base is not aligned\n");
944 /* Allocate a mapping to page look-up index */
945 geth->freeq_pages = kcalloc(pages, sizeof(*geth->freeq_pages),
947 if (!geth->freeq_pages)
949 geth->num_freeq_pages = pages;
951 dev_info(geth->dev, "allocate %d pages for queue\n", pages);
952 for (pn = 0; pn < pages; pn++)
953 if (!geth_freeq_alloc_map_page(geth, pn))
954 goto err_freeq_alloc;
956 filled = geth_fill_freeq(geth, false);
958 goto err_freeq_alloc;
960 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
961 qt.bits.swfq_empty = 32;
962 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
964 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
965 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
966 writel(geth->freeq_dma_base | geth->freeq_order,
967 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
973 struct gmac_queue_page *gpage;
977 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
978 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
979 gpage = &geth->freeq_pages[pn];
980 put_page(gpage->page);
983 kfree(geth->freeq_pages);
985 dma_free_coherent(geth->dev,
986 sizeof(*geth->freeq_ring) << geth->freeq_order,
987 geth->freeq_ring, geth->freeq_dma_base);
988 geth->freeq_ring = NULL;
993 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
994 * @geth: the Gemini global ethernet state
996 static void geth_cleanup_freeq(struct gemini_ethernet *geth)
998 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
999 unsigned int frag_len = 1 << geth->freeq_frag_order;
1000 unsigned int len = 1 << geth->freeq_order;
1001 unsigned int pages = len >> fpp_order;
1004 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
1005 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
1006 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1008 for (pn = 0; pn < pages; pn++) {
1009 struct gmac_queue_page *gpage;
1012 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
1013 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
1015 gpage = &geth->freeq_pages[pn];
1016 while (page_ref_count(gpage->page) > 0)
1017 put_page(gpage->page);
1020 kfree(geth->freeq_pages);
1022 dma_free_coherent(geth->dev,
1023 sizeof(*geth->freeq_ring) << geth->freeq_order,
1024 geth->freeq_ring, geth->freeq_dma_base);
1028 * geth_resize_freeq() - resize the software queue depth
1029 * @port: the port requesting the change
1031 * This gets called at least once during probe() so the device queue gets
1032 * "resized" from the hardware defaults. Since both ports/net devices share
1033 * the same hardware queue, some synchronization between the ports is
1036 static int geth_resize_freeq(struct gemini_ethernet_port *port)
1038 struct gemini_ethernet *geth = port->geth;
1039 struct net_device *netdev = port->netdev;
1040 struct gemini_ethernet_port *other_port;
1041 struct net_device *other_netdev;
1042 unsigned int new_size = 0;
1043 unsigned int new_order;
1044 unsigned long flags;
1048 if (netdev->dev_id == 0)
1049 other_netdev = geth->port1->netdev;
1051 other_netdev = geth->port0->netdev;
1053 if (other_netdev && netif_running(other_netdev))
1056 new_size = 1 << (port->rxq_order + 1);
1057 netdev_dbg(netdev, "port %d size: %d order %d\n",
1062 other_port = netdev_priv(other_netdev);
1063 new_size += 1 << (other_port->rxq_order + 1);
1064 netdev_dbg(other_netdev, "port %d size: %d order %d\n",
1065 other_netdev->dev_id,
1066 (1 << (other_port->rxq_order + 1)),
1067 other_port->rxq_order);
1070 new_order = min(15, ilog2(new_size - 1) + 1);
1071 dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
1072 new_size, new_order);
1073 if (geth->freeq_order == new_order)
1076 spin_lock_irqsave(&geth->irq_lock, flags);
1078 /* Disable the software queue IRQs */
1079 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1080 en &= ~SWFQ_EMPTY_INT_BIT;
1081 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1082 spin_unlock_irqrestore(&geth->irq_lock, flags);
1084 /* Drop the old queue */
1085 if (geth->freeq_ring)
1086 geth_cleanup_freeq(geth);
1088 /* Allocate a new queue with the desired order */
1089 geth->freeq_order = new_order;
1090 ret = geth_setup_freeq(geth);
1092 /* Restart the interrupts - NOTE if this is the first resize
1093 * after probe(), this is where the interrupts get turned on
1094 * in the first place.
1096 spin_lock_irqsave(&geth->irq_lock, flags);
1097 en |= SWFQ_EMPTY_INT_BIT;
1098 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1099 spin_unlock_irqrestore(&geth->irq_lock, flags);
1104 static void gmac_tx_irq_enable(struct net_device *netdev,
1105 unsigned int txq, int en)
1107 struct gemini_ethernet_port *port = netdev_priv(netdev);
1108 struct gemini_ethernet *geth = port->geth;
1111 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
1113 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
1116 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1118 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1119 val = en ? val | mask : val & ~mask;
1120 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1123 static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
1125 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
1127 gmac_tx_irq_enable(netdev, txq_num, 0);
1128 netif_tx_wake_queue(ntxq);
1131 static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
1132 struct gmac_txq *txq, unsigned short *desc)
1134 struct gemini_ethernet_port *port = netdev_priv(netdev);
1135 struct skb_shared_info *skb_si = skb_shinfo(skb);
1136 unsigned short m = (1 << port->txq_order) - 1;
1137 short frag, last_frag = skb_si->nr_frags - 1;
1138 struct gemini_ethernet *geth = port->geth;
1139 unsigned int word1, word3, buflen;
1140 unsigned short w = *desc;
1141 struct gmac_txdesc *txd;
1142 skb_frag_t *skb_frag;
1149 if (skb->protocol == htons(ETH_P_8021Q))
1156 word1 |= TSS_MTU_ENABLE_BIT;
1160 if (skb->ip_summed != CHECKSUM_NONE) {
1163 if (skb->protocol == htons(ETH_P_IP)) {
1164 word1 |= TSS_IP_CHKSUM_BIT;
1165 tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1167 word1 |= TSS_IPV6_ENABLE_BIT;
1168 tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1171 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1175 while (frag <= last_frag) {
1178 buflen = skb_headlen(skb);
1180 skb_frag = skb_si->frags + frag;
1181 buffer = skb_frag_address(skb_frag);
1182 buflen = skb_frag_size(skb_frag);
1185 if (frag == last_frag) {
1190 mapping = dma_map_single(geth->dev, buffer, buflen,
1192 if (dma_mapping_error(geth->dev, mapping))
1195 txd = txq->ring + w;
1196 txd->word0.bits32 = buflen;
1197 txd->word1.bits32 = word1;
1198 txd->word2.buf_adr = mapping;
1199 txd->word3.bits32 = word3;
1201 word3 &= MTU_SIZE_BIT_MASK;
1211 while (w != *desc) {
1215 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
1216 txq->ring[w].word0.bits.buffer_size,
1222 static netdev_tx_t gmac_start_xmit(struct sk_buff *skb,
1223 struct net_device *netdev)
1225 struct gemini_ethernet_port *port = netdev_priv(netdev);
1226 unsigned short m = (1 << port->txq_order) - 1;
1227 struct netdev_queue *ntxq;
1228 unsigned short r, w, d;
1229 void __iomem *ptr_reg;
1230 struct gmac_txq *txq;
1231 int txq_num, nfrags;
1234 if (skb->len >= 0x10000)
1237 txq_num = skb_get_queue_mapping(skb);
1238 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1239 txq = &port->txq[txq_num];
1240 ntxq = netdev_get_tx_queue(netdev, txq_num);
1241 nfrags = skb_shinfo(skb)->nr_frags;
1243 rw.bits32 = readl(ptr_reg);
1247 d = txq->cptr - w - 1;
1250 if (d < nfrags + 2) {
1251 gmac_clean_txq(netdev, txq, r);
1252 d = txq->cptr - w - 1;
1255 if (d < nfrags + 2) {
1256 netif_tx_stop_queue(ntxq);
1258 d = txq->cptr + nfrags + 16;
1260 txq->ring[d].word3.bits.eofie = 1;
1261 gmac_tx_irq_enable(netdev, txq_num, 1);
1263 u64_stats_update_begin(&port->tx_stats_syncp);
1264 netdev->stats.tx_fifo_errors++;
1265 u64_stats_update_end(&port->tx_stats_syncp);
1266 return NETDEV_TX_BUSY;
1270 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
1271 if (skb_linearize(skb))
1274 u64_stats_update_begin(&port->tx_stats_syncp);
1275 port->tx_frags_linearized++;
1276 u64_stats_update_end(&port->tx_stats_syncp);
1278 if (gmac_map_tx_bufs(netdev, skb, txq, &w))
1282 writew(w, ptr_reg + 2);
1284 gmac_clean_txq(netdev, txq, r);
1285 return NETDEV_TX_OK;
1290 u64_stats_update_begin(&port->tx_stats_syncp);
1291 port->stats.tx_dropped++;
1292 u64_stats_update_end(&port->tx_stats_syncp);
1293 return NETDEV_TX_OK;
1296 static void gmac_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1298 netdev_err(netdev, "Tx timeout\n");
1299 gmac_dump_dma_state(netdev);
1302 static void gmac_enable_irq(struct net_device *netdev, int enable)
1304 struct gemini_ethernet_port *port = netdev_priv(netdev);
1305 struct gemini_ethernet *geth = port->geth;
1306 unsigned long flags;
1309 netdev_dbg(netdev, "%s device %d %s\n", __func__,
1310 netdev->dev_id, enable ? "enable" : "disable");
1311 spin_lock_irqsave(&geth->irq_lock, flags);
1313 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
1314 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1315 val = enable ? (val | mask) : (val & ~mask);
1316 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1318 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1319 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1320 val = enable ? (val | mask) : (val & ~mask);
1321 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1323 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
1324 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1325 val = enable ? (val | mask) : (val & ~mask);
1326 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1328 spin_unlock_irqrestore(&geth->irq_lock, flags);
1331 static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
1333 struct gemini_ethernet_port *port = netdev_priv(netdev);
1334 struct gemini_ethernet *geth = port->geth;
1335 unsigned long flags;
1338 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
1339 enable ? "enable" : "disable");
1340 spin_lock_irqsave(&geth->irq_lock, flags);
1341 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1343 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1344 val = enable ? (val | mask) : (val & ~mask);
1345 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1347 spin_unlock_irqrestore(&geth->irq_lock, flags);
1350 static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
1351 union gmac_rxdesc_0 word0,
1352 unsigned int frame_len)
1354 unsigned int rx_csum = word0.bits.chksum_status;
1355 unsigned int rx_status = word0.bits.status;
1356 struct sk_buff *skb = NULL;
1358 port->rx_stats[rx_status]++;
1359 port->rx_csum_stats[rx_csum]++;
1361 if (word0.bits.derr || word0.bits.perr ||
1362 rx_status || frame_len < ETH_ZLEN ||
1363 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1364 port->stats.rx_errors++;
1366 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1367 port->stats.rx_length_errors++;
1368 if (RX_ERROR_OVER(rx_status))
1369 port->stats.rx_over_errors++;
1370 if (RX_ERROR_CRC(rx_status))
1371 port->stats.rx_crc_errors++;
1372 if (RX_ERROR_FRAME(rx_status))
1373 port->stats.rx_frame_errors++;
1377 skb = napi_get_frags(&port->napi);
1381 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1382 skb->ip_summed = CHECKSUM_UNNECESSARY;
1385 port->stats.rx_bytes += frame_len;
1386 port->stats.rx_packets++;
1390 static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
1392 struct gemini_ethernet_port *port = netdev_priv(netdev);
1393 unsigned short m = (1 << port->rxq_order) - 1;
1394 struct gemini_ethernet *geth = port->geth;
1395 void __iomem *ptr_reg = port->rxq_rwptr;
1396 unsigned int frame_len, frag_len;
1397 struct gmac_rxdesc *rx = NULL;
1398 struct gmac_queue_page *gpage;
1399 static struct sk_buff *skb;
1400 union gmac_rxdesc_0 word0;
1401 union gmac_rxdesc_1 word1;
1402 union gmac_rxdesc_3 word3;
1403 struct page *page = NULL;
1404 unsigned int page_offs;
1405 unsigned short r, w;
1410 rw.bits32 = readl(ptr_reg);
1411 /* Reset interrupt as all packages until here are taken into account */
1412 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
1413 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1417 while (budget && w != r) {
1418 rx = port->rxq_ring + r;
1421 mapping = rx->word2.buf_adr;
1427 frag_len = word0.bits.buffer_size;
1428 frame_len = word1.bits.byte_count;
1429 page_offs = mapping & ~PAGE_MASK;
1433 "rxq[%u]: HW BUG: zero DMA desc\n", r);
1437 /* Freeq pointers are one page off */
1438 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
1440 dev_err(geth->dev, "could not find mapping\n");
1445 if (word3.bits32 & SOF_BIT) {
1447 napi_free_frags(&port->napi);
1448 port->stats.rx_dropped++;
1451 skb = gmac_skb_if_good_frame(port, word0, frame_len);
1455 page_offs += NET_IP_ALIGN;
1456 frag_len -= NET_IP_ALIGN;
1464 if (word3.bits32 & EOF_BIT)
1465 frag_len = frame_len - skb->len;
1467 /* append page frag to skb */
1468 if (frag_nr == MAX_SKB_FRAGS)
1472 netdev_err(netdev, "Received fragment with len = 0\n");
1474 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1475 skb->len += frag_len;
1476 skb->data_len += frag_len;
1477 skb->truesize += frag_len;
1480 if (word3.bits32 & EOF_BIT) {
1481 napi_gro_frags(&port->napi);
1489 napi_free_frags(&port->napi);
1496 port->stats.rx_dropped++;
1503 static int gmac_napi_poll(struct napi_struct *napi, int budget)
1505 struct gemini_ethernet_port *port = netdev_priv(napi->dev);
1506 struct gemini_ethernet *geth = port->geth;
1507 unsigned int freeq_threshold;
1508 unsigned int received;
1510 freeq_threshold = 1 << (geth->freeq_order - 1);
1511 u64_stats_update_begin(&port->rx_stats_syncp);
1513 received = gmac_rx(napi->dev, budget);
1514 if (received < budget) {
1515 napi_gro_flush(napi, false);
1516 napi_complete_done(napi, received);
1517 gmac_enable_rx_irq(napi->dev, 1);
1518 ++port->rx_napi_exits;
1521 port->freeq_refill += (budget - received);
1522 if (port->freeq_refill > freeq_threshold) {
1523 port->freeq_refill -= freeq_threshold;
1524 geth_fill_freeq(geth, true);
1527 u64_stats_update_end(&port->rx_stats_syncp);
1531 static void gmac_dump_dma_state(struct net_device *netdev)
1533 struct gemini_ethernet_port *port = netdev_priv(netdev);
1534 struct gemini_ethernet *geth = port->geth;
1535 void __iomem *ptr_reg;
1538 /* Interrupt status */
1539 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1540 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1541 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
1542 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
1543 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1544 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1545 reg[0], reg[1], reg[2], reg[3], reg[4]);
1547 /* Interrupt enable */
1548 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1549 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1550 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1551 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1552 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1553 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1554 reg[0], reg[1], reg[2], reg[3], reg[4]);
1557 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
1558 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
1559 reg[2] = GET_RPTR(port->rxq_rwptr);
1560 reg[3] = GET_WPTR(port->rxq_rwptr);
1561 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1562 reg[0], reg[1], reg[2], reg[3]);
1564 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
1565 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
1566 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
1567 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
1568 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1569 reg[0], reg[1], reg[2], reg[3]);
1572 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
1574 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
1575 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
1576 reg[2] = GET_RPTR(ptr_reg);
1577 reg[3] = GET_WPTR(ptr_reg);
1578 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1579 reg[0], reg[1], reg[2], reg[3]);
1581 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
1582 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
1583 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
1584 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
1585 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1586 reg[0], reg[1], reg[2], reg[3]);
1588 /* FREE queues status */
1589 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
1591 reg[0] = GET_RPTR(ptr_reg);
1592 reg[1] = GET_WPTR(ptr_reg);
1594 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
1596 reg[2] = GET_RPTR(ptr_reg);
1597 reg[3] = GET_WPTR(ptr_reg);
1598 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1599 reg[0], reg[1], reg[2], reg[3]);
1602 static void gmac_update_hw_stats(struct net_device *netdev)
1604 struct gemini_ethernet_port *port = netdev_priv(netdev);
1605 unsigned int rx_discards, rx_mcast, rx_bcast;
1606 struct gemini_ethernet *geth = port->geth;
1607 unsigned long flags;
1609 spin_lock_irqsave(&geth->irq_lock, flags);
1610 u64_stats_update_begin(&port->ir_stats_syncp);
1612 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
1613 port->hw_stats[0] += rx_discards;
1614 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
1615 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
1616 port->hw_stats[2] += rx_mcast;
1617 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
1618 port->hw_stats[3] += rx_bcast;
1619 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
1620 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
1622 port->stats.rx_missed_errors += rx_discards;
1623 port->stats.multicast += rx_mcast;
1624 port->stats.multicast += rx_bcast;
1626 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
1627 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1629 u64_stats_update_end(&port->ir_stats_syncp);
1630 spin_unlock_irqrestore(&geth->irq_lock, flags);
1634 * gmac_get_intr_flags() - get interrupt status flags for a port from
1635 * @netdev: the net device for the port to get flags from
1636 * @i: the interrupt status register 0..4
1638 static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
1640 struct gemini_ethernet_port *port = netdev_priv(netdev);
1641 struct gemini_ethernet *geth = port->geth;
1642 void __iomem *irqif_reg, *irqen_reg;
1643 unsigned int offs, val;
1645 /* Calculate the offset using the stride of the status registers */
1646 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
1647 GLOBAL_INTERRUPT_STATUS_0_REG);
1649 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1650 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1652 val = readl(irqif_reg) & readl(irqen_reg);
1656 static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
1658 struct gemini_ethernet_port *port =
1659 container_of(timer, struct gemini_ethernet_port,
1662 napi_schedule(&port->napi);
1663 return HRTIMER_NORESTART;
1666 static irqreturn_t gmac_irq(int irq, void *data)
1668 struct gemini_ethernet_port *port;
1669 struct net_device *netdev = data;
1670 struct gemini_ethernet *geth;
1673 port = netdev_priv(netdev);
1676 val = gmac_get_intr_flags(netdev, 0);
1679 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
1681 netdev_err(netdev, "hw failure/sw bug\n");
1682 gmac_dump_dma_state(netdev);
1684 /* don't know how to recover, just reduce losses */
1685 gmac_enable_irq(netdev, 0);
1689 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
1690 gmac_tx_irq(netdev, 0);
1692 val = gmac_get_intr_flags(netdev, 1);
1695 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
1696 gmac_enable_rx_irq(netdev, 0);
1698 if (!port->rx_coalesce_nsecs) {
1699 napi_schedule(&port->napi);
1703 ktime = ktime_set(0, port->rx_coalesce_nsecs);
1704 hrtimer_start(&port->rx_coalesce_timer, ktime,
1709 val = gmac_get_intr_flags(netdev, 4);
1712 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
1713 gmac_update_hw_stats(netdev);
1715 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
1716 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
1717 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1719 spin_lock(&geth->irq_lock);
1720 u64_stats_update_begin(&port->ir_stats_syncp);
1721 ++port->stats.rx_fifo_errors;
1722 u64_stats_update_end(&port->ir_stats_syncp);
1723 spin_unlock(&geth->irq_lock);
1726 return orr ? IRQ_HANDLED : IRQ_NONE;
1729 static void gmac_start_dma(struct gemini_ethernet_port *port)
1731 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1732 union gmac_dma_ctrl dma_ctrl;
1734 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1735 dma_ctrl.bits.rd_enable = 1;
1736 dma_ctrl.bits.td_enable = 1;
1737 dma_ctrl.bits.loopback = 0;
1738 dma_ctrl.bits.drop_small_ack = 0;
1739 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1740 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1741 dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1742 dma_ctrl.bits.rd_bus = HSIZE_8;
1743 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1744 dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1745 dma_ctrl.bits.td_bus = HSIZE_8;
1747 writel(dma_ctrl.bits32, dma_ctrl_reg);
1750 static void gmac_stop_dma(struct gemini_ethernet_port *port)
1752 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1753 union gmac_dma_ctrl dma_ctrl;
1755 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1756 dma_ctrl.bits.rd_enable = 0;
1757 dma_ctrl.bits.td_enable = 0;
1758 writel(dma_ctrl.bits32, dma_ctrl_reg);
1761 static int gmac_open(struct net_device *netdev)
1763 struct gemini_ethernet_port *port = netdev_priv(netdev);
1766 err = request_irq(netdev->irq, gmac_irq,
1767 IRQF_SHARED, netdev->name, netdev);
1769 netdev_err(netdev, "no IRQ\n");
1773 netif_carrier_off(netdev);
1774 phy_start(netdev->phydev);
1776 err = geth_resize_freeq(port);
1777 /* It's fine if it's just busy, the other port has set up
1778 * the freeq in that case.
1780 if (err && (err != -EBUSY)) {
1781 netdev_err(netdev, "could not resize freeq\n");
1785 err = gmac_setup_rxq(netdev);
1787 netdev_err(netdev, "could not setup RXQ\n");
1791 err = gmac_setup_txqs(netdev);
1793 netdev_err(netdev, "could not setup TXQs\n");
1794 gmac_cleanup_rxq(netdev);
1798 napi_enable(&port->napi);
1800 gmac_start_dma(port);
1801 gmac_enable_irq(netdev, 1);
1802 gmac_enable_tx_rx(netdev);
1803 netif_tx_start_all_queues(netdev);
1805 hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
1807 port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1809 netdev_dbg(netdev, "opened\n");
1814 phy_stop(netdev->phydev);
1815 free_irq(netdev->irq, netdev);
1819 static int gmac_stop(struct net_device *netdev)
1821 struct gemini_ethernet_port *port = netdev_priv(netdev);
1823 hrtimer_cancel(&port->rx_coalesce_timer);
1824 netif_tx_stop_all_queues(netdev);
1825 gmac_disable_tx_rx(netdev);
1826 gmac_stop_dma(port);
1827 napi_disable(&port->napi);
1829 gmac_enable_irq(netdev, 0);
1830 gmac_cleanup_rxq(netdev);
1831 gmac_cleanup_txqs(netdev);
1833 phy_stop(netdev->phydev);
1834 free_irq(netdev->irq, netdev);
1836 gmac_update_hw_stats(netdev);
1840 static void gmac_set_rx_mode(struct net_device *netdev)
1842 struct gemini_ethernet_port *port = netdev_priv(netdev);
1843 union gmac_rx_fltr filter = { .bits = {
1848 struct netdev_hw_addr *ha;
1849 unsigned int bit_nr;
1855 if (netdev->flags & IFF_PROMISC) {
1856 filter.bits.error = 1;
1857 filter.bits.promiscuous = 1;
1860 } else if (netdev->flags & IFF_ALLMULTI) {
1864 netdev_for_each_mc_addr(ha, netdev) {
1865 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1866 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1870 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
1871 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
1872 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
1875 static void gmac_write_mac_address(struct net_device *netdev)
1877 struct gemini_ethernet_port *port = netdev_priv(netdev);
1880 memset(addr, 0, sizeof(addr));
1881 memcpy(addr, netdev->dev_addr, ETH_ALEN);
1883 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
1884 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
1885 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
1888 static int gmac_set_mac_address(struct net_device *netdev, void *addr)
1890 struct sockaddr *sa = addr;
1892 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
1893 gmac_write_mac_address(netdev);
1898 static void gmac_clear_hw_stats(struct net_device *netdev)
1900 struct gemini_ethernet_port *port = netdev_priv(netdev);
1902 readl(port->gmac_base + GMAC_IN_DISCARDS);
1903 readl(port->gmac_base + GMAC_IN_ERRORS);
1904 readl(port->gmac_base + GMAC_IN_MCAST);
1905 readl(port->gmac_base + GMAC_IN_BCAST);
1906 readl(port->gmac_base + GMAC_IN_MAC1);
1907 readl(port->gmac_base + GMAC_IN_MAC2);
1910 static void gmac_get_stats64(struct net_device *netdev,
1911 struct rtnl_link_stats64 *stats)
1913 struct gemini_ethernet_port *port = netdev_priv(netdev);
1916 gmac_update_hw_stats(netdev);
1918 /* Racing with RX NAPI */
1920 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
1922 stats->rx_packets = port->stats.rx_packets;
1923 stats->rx_bytes = port->stats.rx_bytes;
1924 stats->rx_errors = port->stats.rx_errors;
1925 stats->rx_dropped = port->stats.rx_dropped;
1927 stats->rx_length_errors = port->stats.rx_length_errors;
1928 stats->rx_over_errors = port->stats.rx_over_errors;
1929 stats->rx_crc_errors = port->stats.rx_crc_errors;
1930 stats->rx_frame_errors = port->stats.rx_frame_errors;
1932 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
1934 /* Racing with MIB and TX completion interrupts */
1936 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
1938 stats->tx_errors = port->stats.tx_errors;
1939 stats->tx_packets = port->stats.tx_packets;
1940 stats->tx_bytes = port->stats.tx_bytes;
1942 stats->multicast = port->stats.multicast;
1943 stats->rx_missed_errors = port->stats.rx_missed_errors;
1944 stats->rx_fifo_errors = port->stats.rx_fifo_errors;
1946 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
1948 /* Racing with hard_start_xmit */
1950 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
1952 stats->tx_dropped = port->stats.tx_dropped;
1954 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
1956 stats->rx_dropped += stats->rx_missed_errors;
1959 static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
1961 int max_len = gmac_pick_rx_max_len(new_mtu);
1966 gmac_disable_tx_rx(netdev);
1968 netdev->mtu = new_mtu;
1969 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
1970 CONFIG0_MAXLEN_MASK);
1972 netdev_update_features(netdev);
1974 gmac_enable_tx_rx(netdev);
1979 static netdev_features_t gmac_fix_features(struct net_device *netdev,
1980 netdev_features_t features)
1982 if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
1983 features &= ~GMAC_OFFLOAD_FEATURES;
1988 static int gmac_set_features(struct net_device *netdev,
1989 netdev_features_t features)
1991 struct gemini_ethernet_port *port = netdev_priv(netdev);
1992 int enable = features & NETIF_F_RXCSUM;
1993 unsigned long flags;
1996 spin_lock_irqsave(&port->config_lock, flags);
1998 reg = readl(port->gmac_base + GMAC_CONFIG0);
1999 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
2000 writel(reg, port->gmac_base + GMAC_CONFIG0);
2002 spin_unlock_irqrestore(&port->config_lock, flags);
2006 static int gmac_get_sset_count(struct net_device *netdev, int sset)
2008 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
2011 static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2013 if (stringset != ETH_SS_STATS)
2016 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
2019 static void gmac_get_ethtool_stats(struct net_device *netdev,
2020 struct ethtool_stats *estats, u64 *values)
2022 struct gemini_ethernet_port *port = netdev_priv(netdev);
2027 gmac_update_hw_stats(netdev);
2029 /* Racing with MIB interrupt */
2032 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
2034 for (i = 0; i < RX_STATS_NUM; i++)
2035 *p++ = port->hw_stats[i];
2037 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
2040 /* Racing with RX NAPI */
2043 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
2045 for (i = 0; i < RX_STATUS_NUM; i++)
2046 *p++ = port->rx_stats[i];
2047 for (i = 0; i < RX_CHKSUM_NUM; i++)
2048 *p++ = port->rx_csum_stats[i];
2049 *p++ = port->rx_napi_exits;
2051 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
2054 /* Racing with TX start_xmit */
2057 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
2059 for (i = 0; i < TX_MAX_FRAGS; i++) {
2060 *values++ = port->tx_frag_stats[i];
2061 port->tx_frag_stats[i] = 0;
2063 *values++ = port->tx_frags_linearized;
2064 *values++ = port->tx_hw_csummed;
2066 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
2069 static int gmac_get_ksettings(struct net_device *netdev,
2070 struct ethtool_link_ksettings *cmd)
2072 if (!netdev->phydev)
2074 phy_ethtool_ksettings_get(netdev->phydev, cmd);
2079 static int gmac_set_ksettings(struct net_device *netdev,
2080 const struct ethtool_link_ksettings *cmd)
2082 if (!netdev->phydev)
2084 return phy_ethtool_ksettings_set(netdev->phydev, cmd);
2087 static int gmac_nway_reset(struct net_device *netdev)
2089 if (!netdev->phydev)
2091 return phy_start_aneg(netdev->phydev);
2094 static void gmac_get_pauseparam(struct net_device *netdev,
2095 struct ethtool_pauseparam *pparam)
2097 struct gemini_ethernet_port *port = netdev_priv(netdev);
2098 union gmac_config0 config0;
2100 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2102 pparam->rx_pause = config0.bits.rx_fc_en;
2103 pparam->tx_pause = config0.bits.tx_fc_en;
2104 pparam->autoneg = true;
2107 static void gmac_get_ringparam(struct net_device *netdev,
2108 struct ethtool_ringparam *rp)
2110 struct gemini_ethernet_port *port = netdev_priv(netdev);
2112 readl(port->gmac_base + GMAC_CONFIG0);
2114 rp->rx_max_pending = 1 << 15;
2115 rp->rx_mini_max_pending = 0;
2116 rp->rx_jumbo_max_pending = 0;
2117 rp->tx_max_pending = 1 << 15;
2119 rp->rx_pending = 1 << port->rxq_order;
2120 rp->rx_mini_pending = 0;
2121 rp->rx_jumbo_pending = 0;
2122 rp->tx_pending = 1 << port->txq_order;
2125 static int gmac_set_ringparam(struct net_device *netdev,
2126 struct ethtool_ringparam *rp)
2128 struct gemini_ethernet_port *port = netdev_priv(netdev);
2131 if (netif_running(netdev))
2134 if (rp->rx_pending) {
2135 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2136 err = geth_resize_freeq(port);
2138 if (rp->tx_pending) {
2139 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2140 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
2146 static int gmac_get_coalesce(struct net_device *netdev,
2147 struct ethtool_coalesce *ecmd,
2148 struct kernel_ethtool_coalesce *kernel_coal,
2149 struct netlink_ext_ack *extack)
2151 struct gemini_ethernet_port *port = netdev_priv(netdev);
2153 ecmd->rx_max_coalesced_frames = 1;
2154 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
2155 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
2160 static int gmac_set_coalesce(struct net_device *netdev,
2161 struct ethtool_coalesce *ecmd,
2162 struct kernel_ethtool_coalesce *kernel_coal,
2163 struct netlink_ext_ack *extack)
2165 struct gemini_ethernet_port *port = netdev_priv(netdev);
2167 if (ecmd->tx_max_coalesced_frames < 1)
2169 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
2172 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2173 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2178 static u32 gmac_get_msglevel(struct net_device *netdev)
2180 struct gemini_ethernet_port *port = netdev_priv(netdev);
2182 return port->msg_enable;
2185 static void gmac_set_msglevel(struct net_device *netdev, u32 level)
2187 struct gemini_ethernet_port *port = netdev_priv(netdev);
2189 port->msg_enable = level;
2192 static void gmac_get_drvinfo(struct net_device *netdev,
2193 struct ethtool_drvinfo *info)
2195 strcpy(info->driver, DRV_NAME);
2196 strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
2199 static const struct net_device_ops gmac_351x_ops = {
2200 .ndo_init = gmac_init,
2201 .ndo_open = gmac_open,
2202 .ndo_stop = gmac_stop,
2203 .ndo_start_xmit = gmac_start_xmit,
2204 .ndo_tx_timeout = gmac_tx_timeout,
2205 .ndo_set_rx_mode = gmac_set_rx_mode,
2206 .ndo_set_mac_address = gmac_set_mac_address,
2207 .ndo_get_stats64 = gmac_get_stats64,
2208 .ndo_change_mtu = gmac_change_mtu,
2209 .ndo_fix_features = gmac_fix_features,
2210 .ndo_set_features = gmac_set_features,
2213 static const struct ethtool_ops gmac_351x_ethtool_ops = {
2214 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
2215 ETHTOOL_COALESCE_MAX_FRAMES,
2216 .get_sset_count = gmac_get_sset_count,
2217 .get_strings = gmac_get_strings,
2218 .get_ethtool_stats = gmac_get_ethtool_stats,
2219 .get_link = ethtool_op_get_link,
2220 .get_link_ksettings = gmac_get_ksettings,
2221 .set_link_ksettings = gmac_set_ksettings,
2222 .nway_reset = gmac_nway_reset,
2223 .get_pauseparam = gmac_get_pauseparam,
2224 .get_ringparam = gmac_get_ringparam,
2225 .set_ringparam = gmac_set_ringparam,
2226 .get_coalesce = gmac_get_coalesce,
2227 .set_coalesce = gmac_set_coalesce,
2228 .get_msglevel = gmac_get_msglevel,
2229 .set_msglevel = gmac_set_msglevel,
2230 .get_drvinfo = gmac_get_drvinfo,
2233 static irqreturn_t gemini_port_irq_thread(int irq, void *data)
2235 unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2236 struct gemini_ethernet_port *port = data;
2237 struct gemini_ethernet *geth;
2238 unsigned long flags;
2241 /* The queue is half empty so refill it */
2242 geth_fill_freeq(geth, true);
2244 spin_lock_irqsave(&geth->irq_lock, flags);
2245 /* ACK queue interrupt */
2246 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2247 /* Enable queue interrupt again */
2248 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2249 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2250 spin_unlock_irqrestore(&geth->irq_lock, flags);
2255 static irqreturn_t gemini_port_irq(int irq, void *data)
2257 struct gemini_ethernet_port *port = data;
2258 struct gemini_ethernet *geth;
2259 irqreturn_t ret = IRQ_NONE;
2263 spin_lock(&geth->irq_lock);
2265 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2266 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2268 if (val & en & SWFQ_EMPTY_INT_BIT) {
2269 /* Disable the queue empty interrupt while we work on
2270 * processing the queue. Also disable overrun interrupts
2271 * as there is not much we can do about it here.
2273 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2274 | GMAC1_RX_OVERRUN_INT_BIT);
2275 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2276 ret = IRQ_WAKE_THREAD;
2279 spin_unlock(&geth->irq_lock);
2284 static void gemini_port_remove(struct gemini_ethernet_port *port)
2287 phy_disconnect(port->netdev->phydev);
2288 unregister_netdev(port->netdev);
2290 clk_disable_unprepare(port->pclk);
2291 geth_cleanup_freeq(port->geth);
2294 static void gemini_ethernet_init(struct gemini_ethernet *geth)
2296 /* Only do this once both ports are online */
2297 if (geth->initialized)
2299 if (geth->port0 && geth->port1)
2300 geth->initialized = true;
2304 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
2305 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
2306 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
2307 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
2308 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2310 /* Interrupt config:
2312 * GMAC0 intr bits ------> int0 ----> eth0
2313 * GMAC1 intr bits ------> int1 ----> eth1
2314 * TOE intr -------------> int1 ----> eth1
2315 * Classification Intr --> int0 ----> eth0
2316 * Default Q0 -----------> int0 ----> eth0
2317 * Default Q1 -----------> int1 ----> eth1
2318 * FreeQ intr -----------> int1 ----> eth1
2320 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
2321 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
2322 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
2323 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
2324 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
2326 /* edge-triggered interrupts packed to level-triggered one... */
2327 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
2328 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
2329 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
2330 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
2331 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2334 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2335 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2336 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
2337 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
2339 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2340 /* This makes the queue resize on probe() so that we
2341 * set up and enable the queue IRQ. FIXME: fragile.
2343 geth->freeq_order = 1;
2346 static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
2349 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
2351 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
2353 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
2356 static int gemini_ethernet_port_probe(struct platform_device *pdev)
2358 char *port_names[2] = { "ethernet0", "ethernet1" };
2359 struct gemini_ethernet_port *port;
2360 struct device *dev = &pdev->dev;
2361 struct gemini_ethernet *geth;
2362 struct net_device *netdev;
2363 struct device *parent;
2368 parent = dev->parent;
2369 geth = dev_get_drvdata(parent);
2371 if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
2373 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
2378 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
2380 netdev = devm_alloc_etherdev_mqs(dev, sizeof(*port), TX_QUEUE_NUM, TX_QUEUE_NUM);
2382 dev_err(dev, "Can't allocate ethernet device #%d\n", id);
2386 port = netdev_priv(netdev);
2387 SET_NETDEV_DEV(netdev, dev);
2388 port->netdev = netdev;
2392 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2395 port->dma_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
2396 if (IS_ERR(port->dma_base)) {
2397 dev_err(dev, "get DMA address failed\n");
2398 return PTR_ERR(port->dma_base);
2401 /* GMAC config memory */
2402 port->gmac_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
2403 if (IS_ERR(port->gmac_base)) {
2404 dev_err(dev, "get GMAC address failed\n");
2405 return PTR_ERR(port->gmac_base);
2409 irq = platform_get_irq(pdev, 0);
2411 return irq ? irq : -ENODEV;
2414 /* Clock the port */
2415 port->pclk = devm_clk_get(dev, "PCLK");
2416 if (IS_ERR(port->pclk)) {
2417 dev_err(dev, "no PCLK\n");
2418 return PTR_ERR(port->pclk);
2420 ret = clk_prepare_enable(port->pclk);
2424 /* Maybe there is a nice ethernet address we should use */
2425 gemini_port_save_mac_addr(port);
2427 /* Reset the port */
2428 port->reset = devm_reset_control_get_exclusive(dev, NULL);
2429 if (IS_ERR(port->reset)) {
2430 dev_err(dev, "no reset\n");
2431 ret = PTR_ERR(port->reset);
2434 reset_control_reset(port->reset);
2435 usleep_range(100, 500);
2437 /* Assign pointer in the main state container */
2443 /* This will just be done once both ports are up and reset */
2444 gemini_ethernet_init(geth);
2446 platform_set_drvdata(pdev, port);
2448 /* Set up and register the netdev */
2449 netdev->dev_id = port->id;
2451 netdev->netdev_ops = &gmac_351x_ops;
2452 netdev->ethtool_ops = &gmac_351x_ethtool_ops;
2454 spin_lock_init(&port->config_lock);
2455 gmac_clear_hw_stats(netdev);
2457 netdev->hw_features = GMAC_OFFLOAD_FEATURES;
2458 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
2459 /* We can handle jumbo frames up to 10236 bytes so, let's accept
2460 * payloads of 10236 bytes minus VLAN and ethernet header
2462 netdev->min_mtu = ETH_MIN_MTU;
2463 netdev->max_mtu = 10236 - VLAN_ETH_HLEN;
2465 port->freeq_refill = 0;
2466 netif_napi_add(netdev, &port->napi, gmac_napi_poll,
2467 DEFAULT_NAPI_WEIGHT);
2469 if (is_valid_ether_addr((void *)port->mac_addr)) {
2470 memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
2472 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
2473 port->mac_addr[0], port->mac_addr[1],
2475 dev_info(dev, "using a random ethernet address\n");
2476 eth_random_addr(netdev->dev_addr);
2478 gmac_write_mac_address(netdev);
2480 ret = devm_request_threaded_irq(port->dev,
2483 gemini_port_irq_thread,
2485 port_names[port->id],
2490 ret = gmac_setup_phy(netdev);
2493 "PHY init failed\n");
2497 ret = register_netdev(netdev);
2504 clk_disable_unprepare(port->pclk);
2508 static int gemini_ethernet_port_remove(struct platform_device *pdev)
2510 struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
2512 gemini_port_remove(port);
2517 static const struct of_device_id gemini_ethernet_port_of_match[] = {
2519 .compatible = "cortina,gemini-ethernet-port",
2523 MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
2525 static struct platform_driver gemini_ethernet_port_driver = {
2527 .name = "gemini-ethernet-port",
2528 .of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
2530 .probe = gemini_ethernet_port_probe,
2531 .remove = gemini_ethernet_port_remove,
2534 static int gemini_ethernet_probe(struct platform_device *pdev)
2536 struct device *dev = &pdev->dev;
2537 struct gemini_ethernet *geth;
2538 unsigned int retry = 5;
2541 /* Global registers */
2542 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
2545 geth->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
2546 if (IS_ERR(geth->base))
2547 return PTR_ERR(geth->base);
2550 /* Wait for ports to stabilize */
2553 val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
2555 } while (!val && --retry);
2557 dev_err(dev, "failed to reset ethernet\n");
2560 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
2561 (val >> 4) & 0xFFFU, val & 0xFU);
2563 spin_lock_init(&geth->irq_lock);
2564 spin_lock_init(&geth->freeq_lock);
2566 /* The children will use this */
2567 platform_set_drvdata(pdev, geth);
2569 /* Spawn child devices for the two ports */
2570 return devm_of_platform_populate(dev);
2573 static int gemini_ethernet_remove(struct platform_device *pdev)
2575 struct gemini_ethernet *geth = platform_get_drvdata(pdev);
2577 geth_cleanup_freeq(geth);
2578 geth->initialized = false;
2583 static const struct of_device_id gemini_ethernet_of_match[] = {
2585 .compatible = "cortina,gemini-ethernet",
2589 MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
2591 static struct platform_driver gemini_ethernet_driver = {
2594 .of_match_table = of_match_ptr(gemini_ethernet_of_match),
2596 .probe = gemini_ethernet_probe,
2597 .remove = gemini_ethernet_remove,
2600 static int __init gemini_ethernet_module_init(void)
2604 ret = platform_driver_register(&gemini_ethernet_port_driver);
2608 ret = platform_driver_register(&gemini_ethernet_driver);
2610 platform_driver_unregister(&gemini_ethernet_port_driver);
2616 module_init(gemini_ethernet_module_init);
2618 static void __exit gemini_ethernet_module_exit(void)
2620 platform_driver_unregister(&gemini_ethernet_driver);
2621 platform_driver_unregister(&gemini_ethernet_port_driver);
2623 module_exit(gemini_ethernet_module_exit);
2625 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
2626 MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
2627 MODULE_LICENSE("GPL");
2628 MODULE_ALIAS("platform:" DRV_NAME);