2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
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18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/skbuff.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/prefetch.h>
46 #include "t4vf_common.h"
47 #include "t4vf_defs.h"
49 #include "../cxgb4/t4_regs.h"
50 #include "../cxgb4/t4_values.h"
51 #include "../cxgb4/t4fw_api.h"
52 #include "../cxgb4/t4_msg.h"
59 * Egress Queue sizes, producer and consumer indices are all in units
60 * of Egress Context Units bytes. Note that as far as the hardware is
61 * concerned, the free list is an Egress Queue (the host produces free
62 * buffers which the hardware consumes) and free list entries are
63 * 64-bit PCI DMA addresses.
65 EQ_UNIT = SGE_EQ_IDXSIZE,
66 FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
67 TXD_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
70 * Max number of TX descriptors we clean up at a time. Should be
71 * modest as freeing skbs isn't cheap and it happens while holding
72 * locks. We just need to free packets faster than they arrive, we
73 * eventually catch up and keep the amortized cost reasonable.
78 * Max number of Rx buffers we replenish at a time. Again keep this
79 * modest, allocating buffers isn't cheap either.
84 * Period of the Rx queue check timer. This timer is infrequent as it
85 * has something to do only when the system experiences severe memory
88 RX_QCHECK_PERIOD = (HZ / 2),
91 * Period of the TX queue check timer and the maximum number of TX
92 * descriptors to be reclaimed by the TX timer.
94 TX_QCHECK_PERIOD = (HZ / 2),
95 MAX_TIMER_TX_RECLAIM = 100,
98 * Suspend an Ethernet TX queue with fewer available descriptors than
99 * this. We always want to have room for a maximum sized packet:
100 * inline immediate data + MAX_SKB_FRAGS. This is the same as
101 * calc_tx_flits() for a TSO packet with nr_frags == MAX_SKB_FRAGS
102 * (see that function and its helpers for a description of the
105 ETHTXQ_MAX_FRAGS = MAX_SKB_FRAGS + 1,
106 ETHTXQ_MAX_SGL_LEN = ((3 * (ETHTXQ_MAX_FRAGS-1))/2 +
107 ((ETHTXQ_MAX_FRAGS-1) & 1) +
109 ETHTXQ_MAX_HDR = (sizeof(struct fw_eth_tx_pkt_vm_wr) +
110 sizeof(struct cpl_tx_pkt_lso_core) +
111 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64),
112 ETHTXQ_MAX_FLITS = ETHTXQ_MAX_SGL_LEN + ETHTXQ_MAX_HDR,
114 ETHTXQ_STOP_THRES = 1 + DIV_ROUND_UP(ETHTXQ_MAX_FLITS, TXD_PER_EQ_UNIT),
117 * Max TX descriptor space we allow for an Ethernet packet to be
118 * inlined into a WR. This is limited by the maximum value which
119 * we can specify for immediate data in the firmware Ethernet TX
122 MAX_IMM_TX_PKT_LEN = FW_WR_IMMDLEN_M,
125 * Max size of a WR sent through a control TX queue.
127 MAX_CTRL_WR_LEN = 256,
130 * Maximum amount of data which we'll ever need to inline into a
131 * TX ring: max(MAX_IMM_TX_PKT_LEN, MAX_CTRL_WR_LEN).
133 MAX_IMM_TX_LEN = (MAX_IMM_TX_PKT_LEN > MAX_CTRL_WR_LEN
138 * For incoming packets less than RX_COPY_THRES, we copy the data into
139 * an skb rather than referencing the data. We allocate enough
140 * in-line room in skb's to accommodate pulling in RX_PULL_LEN bytes
141 * of the data (header).
147 * Main body length for sk_buffs used for RX Ethernet packets with
148 * fragments. Should be >= RX_PULL_LEN but possibly bigger to give
149 * pskb_may_pull() some room.
155 * Software state per TX descriptor.
158 struct sk_buff *skb; /* socket buffer of TX data source */
159 struct ulptx_sgl *sgl; /* scatter/gather list in TX Queue */
163 * Software state per RX Free List descriptor. We keep track of the allocated
164 * FL page, its size, and its PCI DMA address (if the page is mapped). The FL
165 * page size and its PCI DMA mapped state are stored in the low bits of the
166 * PCI DMA address as per below.
169 struct page *page; /* Free List page buffer */
170 dma_addr_t dma_addr; /* PCI DMA address (if mapped) */
171 /* and flags (see below) */
175 * The low bits of rx_sw_desc.dma_addr have special meaning. Note that the
176 * SGE also uses the low 4 bits to determine the size of the buffer. It uses
177 * those bits to index into the SGE_FL_BUFFER_SIZE[index] register array.
178 * Since we only use SGE_FL_BUFFER_SIZE0 and SGE_FL_BUFFER_SIZE1, these low 4
179 * bits can only contain a 0 or a 1 to indicate which size buffer we're giving
180 * to the SGE. Thus, our software state of "is the buffer mapped for DMA" is
181 * maintained in an inverse sense so the hardware never sees that bit high.
184 RX_LARGE_BUF = 1 << 0, /* buffer is SGE_FL_BUFFER_SIZE[1] */
185 RX_UNMAPPED_BUF = 1 << 1, /* buffer is not mapped */
189 * get_buf_addr - return DMA buffer address of software descriptor
190 * @sdesc: pointer to the software buffer descriptor
192 * Return the DMA buffer address of a software descriptor (stripping out
193 * our low-order flag bits).
195 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *sdesc)
197 return sdesc->dma_addr & ~(dma_addr_t)(RX_LARGE_BUF | RX_UNMAPPED_BUF);
201 * is_buf_mapped - is buffer mapped for DMA?
202 * @sdesc: pointer to the software buffer descriptor
204 * Determine whether the buffer associated with a software descriptor in
205 * mapped for DMA or not.
207 static inline bool is_buf_mapped(const struct rx_sw_desc *sdesc)
209 return !(sdesc->dma_addr & RX_UNMAPPED_BUF);
213 * need_skb_unmap - does the platform need unmapping of sk_buffs?
215 * Returns true if the platform needs sk_buff unmapping. The compiler
216 * optimizes away unnecessary code if this returns true.
218 static inline int need_skb_unmap(void)
220 #ifdef CONFIG_NEED_DMA_MAP_STATE
228 * txq_avail - return the number of available slots in a TX queue
231 * Returns the number of available descriptors in a TX queue.
233 static inline unsigned int txq_avail(const struct sge_txq *tq)
235 return tq->size - 1 - tq->in_use;
239 * fl_cap - return the capacity of a Free List
242 * Returns the capacity of a Free List. The capacity is less than the
243 * size because an Egress Queue Index Unit worth of descriptors needs to
244 * be left unpopulated, otherwise the Producer and Consumer indices PIDX
245 * and CIDX will match and the hardware will think the FL is empty.
247 static inline unsigned int fl_cap(const struct sge_fl *fl)
249 return fl->size - FL_PER_EQ_UNIT;
253 * fl_starving - return whether a Free List is starving.
254 * @adapter: pointer to the adapter
257 * Tests specified Free List to see whether the number of buffers
258 * available to the hardware has falled below our "starvation"
261 static inline bool fl_starving(const struct adapter *adapter,
262 const struct sge_fl *fl)
264 const struct sge *s = &adapter->sge;
266 return fl->avail - fl->pend_cred <= s->fl_starve_thres;
270 * map_skb - map an skb for DMA to the device
271 * @dev: the egress net device
272 * @skb: the packet to map
273 * @addr: a pointer to the base of the DMA mapping array
275 * Map an skb for DMA to the device and return an array of DMA addresses.
277 static int map_skb(struct device *dev, const struct sk_buff *skb,
280 const skb_frag_t *fp, *end;
281 const struct skb_shared_info *si;
283 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
284 if (dma_mapping_error(dev, *addr))
287 si = skb_shinfo(skb);
288 end = &si->frags[si->nr_frags];
289 for (fp = si->frags; fp < end; fp++) {
290 *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp),
292 if (dma_mapping_error(dev, *addr))
298 while (fp-- > si->frags)
299 dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE);
300 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
306 static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
307 const struct ulptx_sgl *sgl, const struct sge_txq *tq)
309 const struct ulptx_sge_pair *p;
310 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
312 if (likely(skb_headlen(skb)))
313 dma_unmap_single(dev, be64_to_cpu(sgl->addr0),
314 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
316 dma_unmap_page(dev, be64_to_cpu(sgl->addr0),
317 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
322 * the complexity below is because of the possibility of a wrap-around
323 * in the middle of an SGL
325 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
326 if (likely((u8 *)(p + 1) <= (u8 *)tq->stat)) {
328 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
329 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
330 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
331 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
333 } else if ((u8 *)p == (u8 *)tq->stat) {
334 p = (const struct ulptx_sge_pair *)tq->desc;
336 } else if ((u8 *)p + 8 == (u8 *)tq->stat) {
337 const __be64 *addr = (const __be64 *)tq->desc;
339 dma_unmap_page(dev, be64_to_cpu(addr[0]),
340 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
341 dma_unmap_page(dev, be64_to_cpu(addr[1]),
342 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
343 p = (const struct ulptx_sge_pair *)&addr[2];
345 const __be64 *addr = (const __be64 *)tq->desc;
347 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
348 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
349 dma_unmap_page(dev, be64_to_cpu(addr[0]),
350 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
351 p = (const struct ulptx_sge_pair *)&addr[1];
357 if ((u8 *)p == (u8 *)tq->stat)
358 p = (const struct ulptx_sge_pair *)tq->desc;
359 addr = ((u8 *)p + 16 <= (u8 *)tq->stat
361 : *(const __be64 *)tq->desc);
362 dma_unmap_page(dev, be64_to_cpu(addr), be32_to_cpu(p->len[0]),
368 * free_tx_desc - reclaims TX descriptors and their buffers
369 * @adapter: the adapter
370 * @tq: the TX queue to reclaim descriptors from
371 * @n: the number of descriptors to reclaim
372 * @unmap: whether the buffers should be unmapped for DMA
374 * Reclaims TX descriptors from an SGE TX queue and frees the associated
375 * TX buffers. Called with the TX queue lock held.
377 static void free_tx_desc(struct adapter *adapter, struct sge_txq *tq,
378 unsigned int n, bool unmap)
380 struct tx_sw_desc *sdesc;
381 unsigned int cidx = tq->cidx;
382 struct device *dev = adapter->pdev_dev;
384 const int need_unmap = need_skb_unmap() && unmap;
386 sdesc = &tq->sdesc[cidx];
389 * If we kept a reference to the original TX skb, we need to
390 * unmap it from PCI DMA space (if required) and free it.
394 unmap_sgl(dev, sdesc->skb, sdesc->sgl, tq);
395 dev_consume_skb_any(sdesc->skb);
400 if (++cidx == tq->size) {
409 * Return the number of reclaimable descriptors in a TX queue.
411 static inline int reclaimable(const struct sge_txq *tq)
413 int hw_cidx = be16_to_cpu(tq->stat->cidx);
414 int reclaimable = hw_cidx - tq->cidx;
416 reclaimable += tq->size;
421 * reclaim_completed_tx - reclaims completed TX descriptors
422 * @adapter: the adapter
423 * @tq: the TX queue to reclaim completed descriptors from
424 * @unmap: whether the buffers should be unmapped for DMA
426 * Reclaims TX descriptors that the SGE has indicated it has processed,
427 * and frees the associated buffers if possible. Called with the TX
430 static inline void reclaim_completed_tx(struct adapter *adapter,
434 int avail = reclaimable(tq);
438 * Limit the amount of clean up work we do at a time to keep
439 * the TX lock hold time O(1).
441 if (avail > MAX_TX_RECLAIM)
442 avail = MAX_TX_RECLAIM;
444 free_tx_desc(adapter, tq, avail, unmap);
450 * get_buf_size - return the size of an RX Free List buffer.
451 * @adapter: pointer to the associated adapter
452 * @sdesc: pointer to the software buffer descriptor
454 static inline int get_buf_size(const struct adapter *adapter,
455 const struct rx_sw_desc *sdesc)
457 const struct sge *s = &adapter->sge;
459 return (s->fl_pg_order > 0 && (sdesc->dma_addr & RX_LARGE_BUF)
460 ? (PAGE_SIZE << s->fl_pg_order) : PAGE_SIZE);
464 * free_rx_bufs - free RX buffers on an SGE Free List
465 * @adapter: the adapter
466 * @fl: the SGE Free List to free buffers from
467 * @n: how many buffers to free
469 * Release the next @n buffers on an SGE Free List RX queue. The
470 * buffers must be made inaccessible to hardware before calling this
473 static void free_rx_bufs(struct adapter *adapter, struct sge_fl *fl, int n)
476 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
478 if (is_buf_mapped(sdesc))
479 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
480 get_buf_size(adapter, sdesc),
482 put_page(sdesc->page);
484 if (++fl->cidx == fl->size)
491 * unmap_rx_buf - unmap the current RX buffer on an SGE Free List
492 * @adapter: the adapter
493 * @fl: the SGE Free List
495 * Unmap the current buffer on an SGE Free List RX queue. The
496 * buffer must be made inaccessible to HW before calling this function.
498 * This is similar to @free_rx_bufs above but does not free the buffer.
499 * Do note that the FL still loses any further access to the buffer.
500 * This is used predominantly to "transfer ownership" of an FL buffer
501 * to another entity (typically an skb's fragment list).
503 static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl)
505 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
507 if (is_buf_mapped(sdesc))
508 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
509 get_buf_size(adapter, sdesc),
512 if (++fl->cidx == fl->size)
518 * ring_fl_db - righ doorbell on free list
519 * @adapter: the adapter
520 * @fl: the Free List whose doorbell should be rung ...
522 * Tell the Scatter Gather Engine that there are new free list entries
525 static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
527 u32 val = adapter->params.arch.sge_fl_db;
529 /* The SGE keeps track of its Producer and Consumer Indices in terms
530 * of Egress Queue Units so we can only tell it about integral numbers
531 * of multiples of Free List Entries per Egress Queue Units ...
533 if (fl->pend_cred >= FL_PER_EQ_UNIT) {
534 if (is_t4(adapter->params.chip))
535 val |= PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT);
537 val |= PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT);
539 /* Make sure all memory writes to the Free List queue are
540 * committed before we tell the hardware about them.
544 /* If we don't have access to the new User Doorbell (T5+), use
545 * the old doorbell mechanism; otherwise use the new BAR2
548 if (unlikely(fl->bar2_addr == NULL)) {
549 t4_write_reg(adapter,
550 T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
551 QID_V(fl->cntxt_id) | val);
553 writel(val | QID_V(fl->bar2_qid),
554 fl->bar2_addr + SGE_UDB_KDOORBELL);
556 /* This Write memory Barrier will force the write to
557 * the User Doorbell area to be flushed.
561 fl->pend_cred %= FL_PER_EQ_UNIT;
566 * set_rx_sw_desc - initialize software RX buffer descriptor
567 * @sdesc: pointer to the softwore RX buffer descriptor
568 * @page: pointer to the page data structure backing the RX buffer
569 * @dma_addr: PCI DMA address (possibly with low-bit flags)
571 static inline void set_rx_sw_desc(struct rx_sw_desc *sdesc, struct page *page,
575 sdesc->dma_addr = dma_addr;
579 * Support for poisoning RX buffers ...
581 #define POISON_BUF_VAL -1
583 static inline void poison_buf(struct page *page, size_t sz)
585 #if POISON_BUF_VAL >= 0
586 memset(page_address(page), POISON_BUF_VAL, sz);
591 * refill_fl - refill an SGE RX buffer ring
592 * @adapter: the adapter
593 * @fl: the Free List ring to refill
594 * @n: the number of new buffers to allocate
595 * @gfp: the gfp flags for the allocations
597 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
598 * allocated with the supplied gfp flags. The caller must assure that
599 * @n does not exceed the queue's capacity -- i.e. (cidx == pidx) _IN
600 * EGRESS QUEUE UNITS_ indicates an empty Free List! Returns the number
601 * of buffers allocated. If afterwards the queue is found critically low,
602 * mark it as starving in the bitmap of starving FLs.
604 static unsigned int refill_fl(struct adapter *adapter, struct sge_fl *fl,
607 struct sge *s = &adapter->sge;
610 unsigned int cred = fl->avail;
611 __be64 *d = &fl->desc[fl->pidx];
612 struct rx_sw_desc *sdesc = &fl->sdesc[fl->pidx];
615 * Sanity: ensure that the result of adding n Free List buffers
616 * won't result in wrapping the SGE's Producer Index around to
617 * it's Consumer Index thereby indicating an empty Free List ...
619 BUG_ON(fl->avail + n > fl->size - FL_PER_EQ_UNIT);
624 * If we support large pages, prefer large buffers and fail over to
625 * small pages if we can't allocate large pages to satisfy the refill.
626 * If we don't support large pages, drop directly into the small page
629 if (s->fl_pg_order == 0)
630 goto alloc_small_pages;
633 page = __dev_alloc_pages(gfp, s->fl_pg_order);
634 if (unlikely(!page)) {
636 * We've failed inour attempt to allocate a "large
637 * page". Fail over to the "small page" allocation
640 fl->large_alloc_failed++;
643 poison_buf(page, PAGE_SIZE << s->fl_pg_order);
645 dma_addr = dma_map_page(adapter->pdev_dev, page, 0,
646 PAGE_SIZE << s->fl_pg_order,
648 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
650 * We've run out of DMA mapping space. Free up the
651 * buffer and return with what we've managed to put
652 * into the free list. We don't want to fail over to
653 * the small page allocation below in this case
654 * because DMA mapping resources are typically
655 * critical resources once they become scarse.
657 __free_pages(page, s->fl_pg_order);
660 dma_addr |= RX_LARGE_BUF;
661 *d++ = cpu_to_be64(dma_addr);
663 set_rx_sw_desc(sdesc, page, dma_addr);
667 if (++fl->pidx == fl->size) {
677 page = __dev_alloc_page(gfp);
678 if (unlikely(!page)) {
682 poison_buf(page, PAGE_SIZE);
684 dma_addr = dma_map_page(adapter->pdev_dev, page, 0, PAGE_SIZE,
686 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
690 *d++ = cpu_to_be64(dma_addr);
692 set_rx_sw_desc(sdesc, page, dma_addr);
696 if (++fl->pidx == fl->size) {
705 * Update our accounting state to incorporate the new Free List
706 * buffers, tell the hardware about them and return the number of
707 * buffers which we were able to allocate.
709 cred = fl->avail - cred;
710 fl->pend_cred += cred;
711 ring_fl_db(adapter, fl);
713 if (unlikely(fl_starving(adapter, fl))) {
715 set_bit(fl->cntxt_id, adapter->sge.starving_fl);
722 * Refill a Free List to its capacity or the Maximum Refill Increment,
723 * whichever is smaller ...
725 static inline void __refill_fl(struct adapter *adapter, struct sge_fl *fl)
727 refill_fl(adapter, fl,
728 min((unsigned int)MAX_RX_REFILL, fl_cap(fl) - fl->avail),
733 * alloc_ring - allocate resources for an SGE descriptor ring
734 * @dev: the PCI device's core device
735 * @nelem: the number of descriptors
736 * @hwsize: the size of each hardware descriptor
737 * @swsize: the size of each software descriptor
738 * @busaddrp: the physical PCI bus address of the allocated ring
739 * @swringp: return address pointer for software ring
740 * @stat_size: extra space in hardware ring for status information
742 * Allocates resources for an SGE descriptor ring, such as TX queues,
743 * free buffer lists, response queues, etc. Each SGE ring requires
744 * space for its hardware descriptors plus, optionally, space for software
745 * state associated with each hardware entry (the metadata). The function
746 * returns three values: the virtual address for the hardware ring (the
747 * return value of the function), the PCI bus address of the hardware
748 * ring (in *busaddrp), and the address of the software ring (in swringp).
749 * Both the hardware and software rings are returned zeroed out.
751 static void *alloc_ring(struct device *dev, size_t nelem, size_t hwsize,
752 size_t swsize, dma_addr_t *busaddrp, void *swringp,
756 * Allocate the hardware ring and PCI DMA bus address space for said.
758 size_t hwlen = nelem * hwsize + stat_size;
759 void *hwring = dma_alloc_coherent(dev, hwlen, busaddrp, GFP_KERNEL);
765 * If the caller wants a software ring, allocate it and return a
766 * pointer to it in *swringp.
768 BUG_ON((swsize != 0) != (swringp != NULL));
770 void *swring = kcalloc(nelem, swsize, GFP_KERNEL);
773 dma_free_coherent(dev, hwlen, hwring, *busaddrp);
776 *(void **)swringp = swring;
780 * Zero out the hardware ring and return its address as our function
783 memset(hwring, 0, hwlen);
788 * sgl_len - calculates the size of an SGL of the given capacity
789 * @n: the number of SGL entries
791 * Calculates the number of flits (8-byte units) needed for a Direct
792 * Scatter/Gather List that can hold the given number of entries.
794 static inline unsigned int sgl_len(unsigned int n)
797 * A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
798 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
799 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
800 * repeated sequences of { Length[i], Length[i+1], Address[i],
801 * Address[i+1] } (this ensures that all addresses are on 64-bit
802 * boundaries). If N is even, then Length[N+1] should be set to 0 and
803 * Address[N+1] is omitted.
805 * The following calculation incorporates all of the above. It's
806 * somewhat hard to follow but, briefly: the "+2" accounts for the
807 * first two flits which include the DSGL header, Length0 and
808 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
809 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
810 * finally the "+((n-1)&1)" adds the one remaining flit needed if
814 return (3 * n) / 2 + (n & 1) + 2;
818 * flits_to_desc - returns the num of TX descriptors for the given flits
819 * @flits: the number of flits
821 * Returns the number of TX descriptors needed for the supplied number
824 static inline unsigned int flits_to_desc(unsigned int flits)
826 BUG_ON(flits > SGE_MAX_WR_LEN / sizeof(__be64));
827 return DIV_ROUND_UP(flits, TXD_PER_EQ_UNIT);
831 * is_eth_imm - can an Ethernet packet be sent as immediate data?
834 * Returns whether an Ethernet packet is small enough to fit completely as
837 static inline int is_eth_imm(const struct sk_buff *skb)
840 * The VF Driver uses the FW_ETH_TX_PKT_VM_WR firmware Work Request
841 * which does not accommodate immediate data. We could dike out all
842 * of the support code for immediate data but that would tie our hands
843 * too much if we ever want to enhace the firmware. It would also
844 * create more differences between the PF and VF Drivers.
850 * calc_tx_flits - calculate the number of flits for a packet TX WR
853 * Returns the number of flits needed for a TX Work Request for the
854 * given Ethernet packet, including the needed WR and CPL headers.
856 static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
861 * If the skb is small enough, we can pump it out as a work request
862 * with only immediate data. In that case we just have to have the
863 * TX Packet header plus the skb data in the Work Request.
866 return DIV_ROUND_UP(skb->len + sizeof(struct cpl_tx_pkt),
870 * Otherwise, we're going to have to construct a Scatter gather list
871 * of the skb body and fragments. We also include the flits necessary
872 * for the TX Packet Work Request and CPL. We always have a firmware
873 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
874 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
875 * message or, if we're doing a Large Send Offload, an LSO CPL message
876 * with an embedded TX Packet Write CPL message.
878 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
879 if (skb_shinfo(skb)->gso_size)
880 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
881 sizeof(struct cpl_tx_pkt_lso_core) +
882 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
884 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
885 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
890 * write_sgl - populate a Scatter/Gather List for a packet
892 * @tq: the TX queue we are writing into
893 * @sgl: starting location for writing the SGL
894 * @end: points right after the end of the SGL
895 * @start: start offset into skb main-body data to include in the SGL
896 * @addr: the list of DMA bus addresses for the SGL elements
898 * Generates a Scatter/Gather List for the buffers that make up a packet.
899 * The caller must provide adequate space for the SGL that will be written.
900 * The SGL includes all of the packet's page fragments and the data in its
901 * main body except for the first @start bytes. @pos must be 16-byte
902 * aligned and within a TX descriptor with available space. @end points
903 * write after the end of the SGL but does not account for any potential
904 * wrap around, i.e., @end > @tq->stat.
906 static void write_sgl(const struct sk_buff *skb, struct sge_txq *tq,
907 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
908 const dma_addr_t *addr)
911 struct ulptx_sge_pair *to;
912 const struct skb_shared_info *si = skb_shinfo(skb);
913 unsigned int nfrags = si->nr_frags;
914 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
916 len = skb_headlen(skb) - start;
918 sgl->len0 = htonl(len);
919 sgl->addr0 = cpu_to_be64(addr[0] + start);
922 sgl->len0 = htonl(skb_frag_size(&si->frags[0]));
923 sgl->addr0 = cpu_to_be64(addr[1]);
926 sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
927 ULPTX_NSGE_V(nfrags));
928 if (likely(--nfrags == 0))
931 * Most of the complexity below deals with the possibility we hit the
932 * end of the queue in the middle of writing the SGL. For this case
933 * only we create the SGL in a temporary buffer and then copy it.
935 to = (u8 *)end > (u8 *)tq->stat ? buf : sgl->sge;
937 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
938 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
939 to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i]));
940 to->addr[0] = cpu_to_be64(addr[i]);
941 to->addr[1] = cpu_to_be64(addr[++i]);
944 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
945 to->len[1] = cpu_to_be32(0);
946 to->addr[0] = cpu_to_be64(addr[i + 1]);
948 if (unlikely((u8 *)end > (u8 *)tq->stat)) {
949 unsigned int part0 = (u8 *)tq->stat - (u8 *)sgl->sge, part1;
952 memcpy(sgl->sge, buf, part0);
953 part1 = (u8 *)end - (u8 *)tq->stat;
954 memcpy(tq->desc, (u8 *)buf + part0, part1);
955 end = (void *)tq->desc + part1;
957 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
962 * check_ring_tx_db - check and potentially ring a TX queue's doorbell
963 * @adapter: the adapter
965 * @n: number of new descriptors to give to HW
967 * Ring the doorbel for a TX queue.
969 static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
972 /* Make sure that all writes to the TX Descriptors are committed
973 * before we tell the hardware about them.
977 /* If we don't have access to the new User Doorbell (T5+), use the old
978 * doorbell mechanism; otherwise use the new BAR2 mechanism.
980 if (unlikely(tq->bar2_addr == NULL)) {
983 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
984 QID_V(tq->cntxt_id) | val);
986 u32 val = PIDX_T5_V(n);
988 /* T4 and later chips share the same PIDX field offset within
989 * the doorbell, but T5 and later shrank the field in order to
990 * gain a bit for Doorbell Priority. The field was absurdly
991 * large in the first place (14 bits) so we just use the T5
992 * and later limits and warn if a Queue ID is too large.
994 WARN_ON(val & DBPRIO_F);
996 /* If we're only writing a single Egress Unit and the BAR2
997 * Queue ID is 0, we can use the Write Combining Doorbell
998 * Gather Buffer; otherwise we use the simple doorbell.
1000 if (n == 1 && tq->bar2_qid == 0) {
1001 unsigned int index = (tq->pidx
1004 __be64 *src = (__be64 *)&tq->desc[index];
1005 __be64 __iomem *dst = (__be64 __iomem *)(tq->bar2_addr +
1006 SGE_UDB_WCDOORBELL);
1007 unsigned int count = EQ_UNIT / sizeof(__be64);
1009 /* Copy the TX Descriptor in a tight loop in order to
1010 * try to get it to the adapter in a single Write
1011 * Combined transfer on the PCI-E Bus. If the Write
1012 * Combine fails (say because of an interrupt, etc.)
1013 * the hardware will simply take the last write as a
1014 * simple doorbell write with a PIDX Increment of 1
1015 * and will fetch the TX Descriptor from memory via
1019 /* the (__force u64) is because the compiler
1020 * doesn't understand the endian swizzling
1023 writeq((__force u64)*src, dst);
1029 writel(val | QID_V(tq->bar2_qid),
1030 tq->bar2_addr + SGE_UDB_KDOORBELL);
1032 /* This Write Memory Barrier will force the write to the User
1033 * Doorbell area to be flushed. This is needed to prevent
1034 * writes on different CPUs for the same queue from hitting
1035 * the adapter out of order. This is required when some Work
1036 * Requests take the Write Combine Gather Buffer path (user
1037 * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some
1038 * take the traditional path where we simply increment the
1039 * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the
1040 * hardware DMA read the actual Work Request.
1047 * inline_tx_skb - inline a packet's data into TX descriptors
1049 * @tq: the TX queue where the packet will be inlined
1050 * @pos: starting position in the TX queue to inline the packet
1052 * Inline a packet's contents directly into TX descriptors, starting at
1053 * the given position within the TX DMA ring.
1054 * Most of the complexity of this operation is dealing with wrap arounds
1055 * in the middle of the packet we want to inline.
1057 static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *tq,
1061 int left = (void *)tq->stat - pos;
1063 if (likely(skb->len <= left)) {
1064 if (likely(!skb->data_len))
1065 skb_copy_from_linear_data(skb, pos, skb->len);
1067 skb_copy_bits(skb, 0, pos, skb->len);
1070 skb_copy_bits(skb, 0, pos, left);
1071 skb_copy_bits(skb, left, tq->desc, skb->len - left);
1072 pos = (void *)tq->desc + (skb->len - left);
1075 /* 0-pad to multiple of 16 */
1076 p = PTR_ALIGN(pos, 8);
1077 if ((uintptr_t)p & 8)
1082 * Figure out what HW csum a packet wants and return the appropriate control
1085 static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb)
1088 const struct iphdr *iph = ip_hdr(skb);
1090 if (iph->version == 4) {
1091 if (iph->protocol == IPPROTO_TCP)
1092 csum_type = TX_CSUM_TCPIP;
1093 else if (iph->protocol == IPPROTO_UDP)
1094 csum_type = TX_CSUM_UDPIP;
1098 * unknown protocol, disable HW csum
1099 * and hope a bad packet is detected
1101 return TXPKT_L4CSUM_DIS_F;
1105 * this doesn't work with extension headers
1107 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
1109 if (ip6h->nexthdr == IPPROTO_TCP)
1110 csum_type = TX_CSUM_TCPIP6;
1111 else if (ip6h->nexthdr == IPPROTO_UDP)
1112 csum_type = TX_CSUM_UDPIP6;
1117 if (likely(csum_type >= TX_CSUM_TCPIP)) {
1118 u64 hdr_len = TXPKT_IPHDR_LEN_V(skb_network_header_len(skb));
1119 int eth_hdr_len = skb_network_offset(skb) - ETH_HLEN;
1121 if (chip <= CHELSIO_T5)
1122 hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1124 hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1125 return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len;
1127 int start = skb_transport_offset(skb);
1129 return TXPKT_CSUM_TYPE_V(csum_type) |
1130 TXPKT_CSUM_START_V(start) |
1131 TXPKT_CSUM_LOC_V(start + skb->csum_offset);
1136 * Stop an Ethernet TX queue and record that state change.
1138 static void txq_stop(struct sge_eth_txq *txq)
1140 netif_tx_stop_queue(txq->txq);
1145 * Advance our software state for a TX queue by adding n in use descriptors.
1147 static inline void txq_advance(struct sge_txq *tq, unsigned int n)
1151 if (tq->pidx >= tq->size)
1152 tq->pidx -= tq->size;
1156 * t4vf_eth_xmit - add a packet to an Ethernet TX queue
1158 * @dev: the egress net device
1160 * Add a packet to an SGE Ethernet TX queue. Runs with softirqs disabled.
1162 int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1166 int qidx, credits, max_pkt_len;
1167 unsigned int flits, ndesc;
1168 struct adapter *adapter;
1169 struct sge_eth_txq *txq;
1170 const struct port_info *pi;
1171 struct fw_eth_tx_pkt_vm_wr *wr;
1172 struct cpl_tx_pkt_core *cpl;
1173 const struct skb_shared_info *ssi;
1174 dma_addr_t addr[MAX_SKB_FRAGS + 1];
1175 const size_t fw_hdr_copy_len = (sizeof(wr->ethmacdst) +
1176 sizeof(wr->ethmacsrc) +
1177 sizeof(wr->ethtype) +
1178 sizeof(wr->vlantci));
1181 * The chip minimum packet length is 10 octets but the firmware
1182 * command that we are using requires that we copy the Ethernet header
1183 * (including the VLAN tag) into the header so we reject anything
1184 * smaller than that ...
1186 if (unlikely(skb->len < fw_hdr_copy_len))
1189 /* Discard the packet if the length is greater than mtu */
1190 max_pkt_len = ETH_HLEN + dev->mtu;
1191 if (skb_vlan_tagged(skb))
1192 max_pkt_len += VLAN_HLEN;
1193 if (!skb_shinfo(skb)->gso_size && (unlikely(skb->len > max_pkt_len)))
1197 * Figure out which TX Queue we're going to use.
1199 pi = netdev_priv(dev);
1200 adapter = pi->adapter;
1201 qidx = skb_get_queue_mapping(skb);
1202 BUG_ON(qidx >= pi->nqsets);
1203 txq = &adapter->sge.ethtxq[pi->first_qset + qidx];
1206 * Take this opportunity to reclaim any TX Descriptors whose DMA
1207 * transfers have completed.
1209 reclaim_completed_tx(adapter, &txq->q, true);
1212 * Calculate the number of flits and TX Descriptors we're going to
1213 * need along with how many TX Descriptors will be left over after
1214 * we inject our Work Request.
1216 flits = calc_tx_flits(skb);
1217 ndesc = flits_to_desc(flits);
1218 credits = txq_avail(&txq->q) - ndesc;
1220 if (unlikely(credits < 0)) {
1222 * Not enough room for this packet's Work Request. Stop the
1223 * TX Queue and return a "busy" condition. The queue will get
1224 * started later on when the firmware informs us that space
1228 dev_err(adapter->pdev_dev,
1229 "%s: TX ring %u full while queue awake!\n",
1231 return NETDEV_TX_BUSY;
1234 if (!is_eth_imm(skb) &&
1235 unlikely(map_skb(adapter->pdev_dev, skb, addr) < 0)) {
1237 * We need to map the skb into PCI DMA space (because it can't
1238 * be in-lined directly into the Work Request) and the mapping
1239 * operation failed. Record the error and drop the packet.
1245 wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
1246 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1248 * After we're done injecting the Work Request for this
1249 * packet, we'll be below our "stop threshold" so stop the TX
1250 * Queue now and schedule a request for an SGE Egress Queue
1251 * Update message. The queue will get started later on when
1252 * the firmware processes this Work Request and sends us an
1253 * Egress Queue Status Update message indicating that space
1257 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
1261 * Start filling in our Work Request. Note that we do _not_ handle
1262 * the WR Header wrapping around the TX Descriptor Ring. If our
1263 * maximum header size ever exceeds one TX Descriptor, we'll need to
1264 * do something else here.
1266 BUG_ON(DIV_ROUND_UP(ETHTXQ_MAX_HDR, TXD_PER_EQ_UNIT) > 1);
1267 wr = (void *)&txq->q.desc[txq->q.pidx];
1268 wr->equiq_to_len16 = cpu_to_be32(wr_mid);
1269 wr->r3[0] = cpu_to_be32(0);
1270 wr->r3[1] = cpu_to_be32(0);
1271 skb_copy_from_linear_data(skb, (void *)wr->ethmacdst, fw_hdr_copy_len);
1272 end = (u64 *)wr + flits;
1275 * If this is a Large Send Offload packet we'll put in an LSO CPL
1276 * message with an encapsulated TX Packet CPL message. Otherwise we
1277 * just use a TX Packet CPL message.
1279 ssi = skb_shinfo(skb);
1280 if (ssi->gso_size) {
1281 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
1282 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1283 int l3hdr_len = skb_network_header_len(skb);
1284 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1287 cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_PKT_VM_WR) |
1288 FW_WR_IMMDLEN_V(sizeof(*lso) +
1291 * Fill in the LSO CPL message.
1294 cpu_to_be32(LSO_OPCODE_V(CPL_TX_PKT_LSO) |
1298 LSO_ETHHDR_LEN_V(eth_xtra_len / 4) |
1299 LSO_IPHDR_LEN_V(l3hdr_len / 4) |
1300 LSO_TCPHDR_LEN_V(tcp_hdr(skb)->doff));
1301 lso->ipid_ofst = cpu_to_be16(0);
1302 lso->mss = cpu_to_be16(ssi->gso_size);
1303 lso->seqno_offset = cpu_to_be32(0);
1304 if (is_t4(adapter->params.chip))
1305 lso->len = cpu_to_be32(skb->len);
1307 lso->len = cpu_to_be32(LSO_T5_XFER_SIZE_V(skb->len));
1310 * Set up TX Packet CPL pointer, control word and perform
1313 cpl = (void *)(lso + 1);
1315 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
1316 cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1318 cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1320 cntrl |= TXPKT_CSUM_TYPE_V(v6 ?
1321 TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1322 TXPKT_IPHDR_LEN_V(l3hdr_len);
1324 txq->tx_cso += ssi->gso_segs;
1328 len = is_eth_imm(skb) ? skb->len + sizeof(*cpl) : sizeof(*cpl);
1330 cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_PKT_VM_WR) |
1331 FW_WR_IMMDLEN_V(len));
1334 * Set up TX Packet CPL pointer, control word and perform
1337 cpl = (void *)(wr + 1);
1338 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1339 cntrl = hwcsum(adapter->params.chip, skb) |
1343 cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
1347 * If there's a VLAN tag present, add that to the list of things to
1348 * do in this Work Request.
1350 if (skb_vlan_tag_present(skb)) {
1352 cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb));
1356 * Fill in the TX Packet CPL message header.
1358 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) |
1359 TXPKT_INTF_V(pi->port_id) |
1361 cpl->pack = cpu_to_be16(0);
1362 cpl->len = cpu_to_be16(skb->len);
1363 cpl->ctrl1 = cpu_to_be64(cntrl);
1366 T4_TRACE5(adapter->tb[txq->q.cntxt_id & 7],
1367 "eth_xmit: ndesc %u, credits %u, pidx %u, len %u, frags %u",
1368 ndesc, credits, txq->q.pidx, skb->len, ssi->nr_frags);
1372 * Fill in the body of the TX Packet CPL message with either in-lined
1373 * data or a Scatter/Gather List.
1375 if (is_eth_imm(skb)) {
1377 * In-line the packet's data and free the skb since we don't
1378 * need it any longer.
1380 inline_tx_skb(skb, &txq->q, cpl + 1);
1381 dev_consume_skb_any(skb);
1384 * Write the skb's Scatter/Gather list into the TX Packet CPL
1385 * message and retain a pointer to the skb so we can free it
1386 * later when its DMA completes. (We store the skb pointer
1387 * in the Software Descriptor corresponding to the last TX
1388 * Descriptor used by the Work Request.)
1390 * The retained skb will be freed when the corresponding TX
1391 * Descriptors are reclaimed after their DMAs complete.
1392 * However, this could take quite a while since, in general,
1393 * the hardware is set up to be lazy about sending DMA
1394 * completion notifications to us and we mostly perform TX
1395 * reclaims in the transmit routine.
1397 * This is good for performamce but means that we rely on new
1398 * TX packets arriving to run the destructors of completed
1399 * packets, which open up space in their sockets' send queues.
1400 * Sometimes we do not get such new packets causing TX to
1401 * stall. A single UDP transmitter is a good example of this
1402 * situation. We have a clean up timer that periodically
1403 * reclaims completed packets but it doesn't run often enough
1404 * (nor do we want it to) to prevent lengthy stalls. A
1405 * solution to this problem is to run the destructor early,
1406 * after the packet is queued but before it's DMAd. A con is
1407 * that we lie to socket memory accounting, but the amount of
1408 * extra memory is reasonable (limited by the number of TX
1409 * descriptors), the packets do actually get freed quickly by
1410 * new packets almost always, and for protocols like TCP that
1411 * wait for acks to really free up the data the extra memory
1412 * is even less. On the positive side we run the destructors
1413 * on the sending CPU rather than on a potentially different
1414 * completing CPU, usually a good thing.
1416 * Run the destructor before telling the DMA engine about the
1417 * packet to make sure it doesn't complete and get freed
1420 struct ulptx_sgl *sgl = (struct ulptx_sgl *)(cpl + 1);
1421 struct sge_txq *tq = &txq->q;
1425 * If the Work Request header was an exact multiple of our TX
1426 * Descriptor length, then it's possible that the starting SGL
1427 * pointer lines up exactly with the end of our TX Descriptor
1428 * ring. If that's the case, wrap around to the beginning
1431 if (unlikely((void *)sgl == (void *)tq->stat)) {
1432 sgl = (void *)tq->desc;
1433 end = ((void *)tq->desc + ((void *)end - (void *)tq->stat));
1436 write_sgl(skb, tq, sgl, end, 0, addr);
1439 last_desc = tq->pidx + ndesc - 1;
1440 if (last_desc >= tq->size)
1441 last_desc -= tq->size;
1442 tq->sdesc[last_desc].skb = skb;
1443 tq->sdesc[last_desc].sgl = sgl;
1447 * Advance our internal TX Queue state, tell the hardware about
1448 * the new TX descriptors and return success.
1450 txq_advance(&txq->q, ndesc);
1451 netif_trans_update(dev);
1452 ring_tx_db(adapter, &txq->q, ndesc);
1453 return NETDEV_TX_OK;
1457 * An error of some sort happened. Free the TX skb and tell the
1458 * OS that we've "dealt" with the packet ...
1460 dev_kfree_skb_any(skb);
1461 return NETDEV_TX_OK;
1465 * copy_frags - copy fragments from gather list into skb_shared_info
1466 * @skb: destination skb
1467 * @gl: source internal packet gather list
1468 * @offset: packet start offset in first page
1470 * Copy an internal packet gather list into a Linux skb_shared_info
1473 static inline void copy_frags(struct sk_buff *skb,
1474 const struct pkt_gl *gl,
1475 unsigned int offset)
1479 /* usually there's just one frag */
1480 __skb_fill_page_desc(skb, 0, gl->frags[0].page,
1481 gl->frags[0].offset + offset,
1482 gl->frags[0].size - offset);
1483 skb_shinfo(skb)->nr_frags = gl->nfrags;
1484 for (i = 1; i < gl->nfrags; i++)
1485 __skb_fill_page_desc(skb, i, gl->frags[i].page,
1486 gl->frags[i].offset,
1489 /* get a reference to the last page, we don't own it */
1490 get_page(gl->frags[gl->nfrags - 1].page);
1494 * t4vf_pktgl_to_skb - build an sk_buff from a packet gather list
1495 * @gl: the gather list
1496 * @skb_len: size of sk_buff main body if it carries fragments
1497 * @pull_len: amount of data to move to the sk_buff's main body
1499 * Builds an sk_buff from the given packet gather list. Returns the
1500 * sk_buff or %NULL if sk_buff allocation failed.
1502 static struct sk_buff *t4vf_pktgl_to_skb(const struct pkt_gl *gl,
1503 unsigned int skb_len,
1504 unsigned int pull_len)
1506 struct sk_buff *skb;
1509 * If the ingress packet is small enough, allocate an skb large enough
1510 * for all of the data and copy it inline. Otherwise, allocate an skb
1511 * with enough room to pull in the header and reference the rest of
1512 * the data via the skb fragment list.
1514 * Below we rely on RX_COPY_THRES being less than the smallest Rx
1515 * buff! size, which is expected since buffers are at least
1516 * PAGE_SIZEd. In this case packets up to RX_COPY_THRES have only one
1519 if (gl->tot_len <= RX_COPY_THRES) {
1520 /* small packets have only one fragment */
1521 skb = alloc_skb(gl->tot_len, GFP_ATOMIC);
1524 __skb_put(skb, gl->tot_len);
1525 skb_copy_to_linear_data(skb, gl->va, gl->tot_len);
1527 skb = alloc_skb(skb_len, GFP_ATOMIC);
1530 __skb_put(skb, pull_len);
1531 skb_copy_to_linear_data(skb, gl->va, pull_len);
1533 copy_frags(skb, gl, pull_len);
1534 skb->len = gl->tot_len;
1535 skb->data_len = skb->len - pull_len;
1536 skb->truesize += skb->data_len;
1544 * t4vf_pktgl_free - free a packet gather list
1545 * @gl: the gather list
1547 * Releases the pages of a packet gather list. We do not own the last
1548 * page on the list and do not free it.
1550 static void t4vf_pktgl_free(const struct pkt_gl *gl)
1554 frag = gl->nfrags - 1;
1556 put_page(gl->frags[frag].page);
1560 * do_gro - perform Generic Receive Offload ingress packet processing
1561 * @rxq: ingress RX Ethernet Queue
1562 * @gl: gather list for ingress packet
1563 * @pkt: CPL header for last packet fragment
1565 * Perform Generic Receive Offload (GRO) ingress packet processing.
1566 * We use the standard Linux GRO interfaces for this.
1568 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1569 const struct cpl_rx_pkt *pkt)
1571 struct adapter *adapter = rxq->rspq.adapter;
1572 struct sge *s = &adapter->sge;
1574 struct sk_buff *skb;
1576 skb = napi_get_frags(&rxq->rspq.napi);
1577 if (unlikely(!skb)) {
1578 t4vf_pktgl_free(gl);
1579 rxq->stats.rx_drops++;
1583 copy_frags(skb, gl, s->pktshift);
1584 skb->len = gl->tot_len - s->pktshift;
1585 skb->data_len = skb->len;
1586 skb->truesize += skb->data_len;
1587 skb->ip_summed = CHECKSUM_UNNECESSARY;
1588 skb_record_rx_queue(skb, rxq->rspq.idx);
1591 __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q),
1592 be16_to_cpu(pkt->vlan));
1593 rxq->stats.vlan_ex++;
1595 ret = napi_gro_frags(&rxq->rspq.napi);
1597 if (ret == GRO_HELD)
1598 rxq->stats.lro_pkts++;
1599 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1600 rxq->stats.lro_merged++;
1602 rxq->stats.rx_cso++;
1606 * t4vf_ethrx_handler - process an ingress ethernet packet
1607 * @rspq: the response queue that received the packet
1608 * @rsp: the response queue descriptor holding the RX_PKT message
1609 * @gl: the gather list of packet fragments
1611 * Process an ingress ethernet packet and deliver it to the stack.
1613 int t4vf_ethrx_handler(struct sge_rspq *rspq, const __be64 *rsp,
1614 const struct pkt_gl *gl)
1616 struct sk_buff *skb;
1617 const struct cpl_rx_pkt *pkt = (void *)rsp;
1618 bool csum_ok = pkt->csum_calc && !pkt->err_vec &&
1619 (rspq->netdev->features & NETIF_F_RXCSUM);
1620 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1621 struct adapter *adapter = rspq->adapter;
1622 struct sge *s = &adapter->sge;
1625 * If this is a good TCP packet and we have Generic Receive Offload
1626 * enabled, handle the packet in the GRO path.
1628 if ((pkt->l2info & cpu_to_be32(RXF_TCP_F)) &&
1629 (rspq->netdev->features & NETIF_F_GRO) && csum_ok &&
1631 do_gro(rxq, gl, pkt);
1636 * Convert the Packet Gather List into an skb.
1638 skb = t4vf_pktgl_to_skb(gl, RX_SKB_LEN, RX_PULL_LEN);
1639 if (unlikely(!skb)) {
1640 t4vf_pktgl_free(gl);
1641 rxq->stats.rx_drops++;
1644 __skb_pull(skb, s->pktshift);
1645 skb->protocol = eth_type_trans(skb, rspq->netdev);
1646 skb_record_rx_queue(skb, rspq->idx);
1649 if (csum_ok && !pkt->err_vec &&
1650 (be32_to_cpu(pkt->l2info) & (RXF_UDP_F | RXF_TCP_F))) {
1651 if (!pkt->ip_frag) {
1652 skb->ip_summed = CHECKSUM_UNNECESSARY;
1653 rxq->stats.rx_cso++;
1654 } else if (pkt->l2info & htonl(RXF_IP_F)) {
1655 __sum16 c = (__force __sum16)pkt->csum;
1656 skb->csum = csum_unfold(c);
1657 skb->ip_summed = CHECKSUM_COMPLETE;
1658 rxq->stats.rx_cso++;
1661 skb_checksum_none_assert(skb);
1664 rxq->stats.vlan_ex++;
1665 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(pkt->vlan));
1668 netif_receive_skb(skb);
1674 * is_new_response - check if a response is newly written
1675 * @rc: the response control descriptor
1676 * @rspq: the response queue
1678 * Returns true if a response descriptor contains a yet unprocessed
1681 static inline bool is_new_response(const struct rsp_ctrl *rc,
1682 const struct sge_rspq *rspq)
1684 return ((rc->type_gen >> RSPD_GEN_S) & 0x1) == rspq->gen;
1688 * restore_rx_bufs - put back a packet's RX buffers
1689 * @gl: the packet gather list
1690 * @fl: the SGE Free List
1691 * @nfrags: how many fragments in @si
1693 * Called when we find out that the current packet, @si, can't be
1694 * processed right away for some reason. This is a very rare event and
1695 * there's no effort to make this suspension/resumption process
1696 * particularly efficient.
1698 * We implement the suspension by putting all of the RX buffers associated
1699 * with the current packet back on the original Free List. The buffers
1700 * have already been unmapped and are left unmapped, we mark them as
1701 * unmapped in order to prevent further unmapping attempts. (Effectively
1702 * this function undoes the series of @unmap_rx_buf calls which were done
1703 * to create the current packet's gather list.) This leaves us ready to
1704 * restart processing of the packet the next time we start processing the
1707 static void restore_rx_bufs(const struct pkt_gl *gl, struct sge_fl *fl,
1710 struct rx_sw_desc *sdesc;
1714 fl->cidx = fl->size - 1;
1717 sdesc = &fl->sdesc[fl->cidx];
1718 sdesc->page = gl->frags[frags].page;
1719 sdesc->dma_addr |= RX_UNMAPPED_BUF;
1725 * rspq_next - advance to the next entry in a response queue
1728 * Updates the state of a response queue to advance it to the next entry.
1730 static inline void rspq_next(struct sge_rspq *rspq)
1732 rspq->cur_desc = (void *)rspq->cur_desc + rspq->iqe_len;
1733 if (unlikely(++rspq->cidx == rspq->size)) {
1736 rspq->cur_desc = rspq->desc;
1741 * process_responses - process responses from an SGE response queue
1742 * @rspq: the ingress response queue to process
1743 * @budget: how many responses can be processed in this round
1745 * Process responses from a Scatter Gather Engine response queue up to
1746 * the supplied budget. Responses include received packets as well as
1747 * control messages from firmware or hardware.
1749 * Additionally choose the interrupt holdoff time for the next interrupt
1750 * on this queue. If the system is under memory shortage use a fairly
1751 * long delay to help recovery.
1753 static int process_responses(struct sge_rspq *rspq, int budget)
1755 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1756 struct adapter *adapter = rspq->adapter;
1757 struct sge *s = &adapter->sge;
1758 int budget_left = budget;
1760 while (likely(budget_left)) {
1762 const struct rsp_ctrl *rc;
1764 rc = (void *)rspq->cur_desc + (rspq->iqe_len - sizeof(*rc));
1765 if (!is_new_response(rc, rspq))
1769 * Figure out what kind of response we've received from the
1773 rsp_type = RSPD_TYPE_G(rc->type_gen);
1774 if (likely(rsp_type == RSPD_TYPE_FLBUF_X)) {
1775 struct page_frag *fp;
1777 const struct rx_sw_desc *sdesc;
1779 u32 len = be32_to_cpu(rc->pldbuflen_qid);
1782 * If we get a "new buffer" message from the SGE we
1783 * need to move on to the next Free List buffer.
1785 if (len & RSPD_NEWBUF_F) {
1787 * We get one "new buffer" message when we
1788 * first start up a queue so we need to ignore
1789 * it when our offset into the buffer is 0.
1791 if (likely(rspq->offset > 0)) {
1792 free_rx_bufs(rspq->adapter, &rxq->fl,
1796 len = RSPD_LEN_G(len);
1801 * Gather packet fragments.
1803 for (frag = 0, fp = gl.frags; /**/; frag++, fp++) {
1804 BUG_ON(frag >= MAX_SKB_FRAGS);
1805 BUG_ON(rxq->fl.avail == 0);
1806 sdesc = &rxq->fl.sdesc[rxq->fl.cidx];
1807 bufsz = get_buf_size(adapter, sdesc);
1808 fp->page = sdesc->page;
1809 fp->offset = rspq->offset;
1810 fp->size = min(bufsz, len);
1814 unmap_rx_buf(rspq->adapter, &rxq->fl);
1819 * Last buffer remains mapped so explicitly make it
1820 * coherent for CPU access and start preloading first
1823 dma_sync_single_for_cpu(rspq->adapter->pdev_dev,
1824 get_buf_addr(sdesc),
1825 fp->size, DMA_FROM_DEVICE);
1826 gl.va = (page_address(gl.frags[0].page) +
1827 gl.frags[0].offset);
1831 * Hand the new ingress packet to the handler for
1832 * this Response Queue.
1834 ret = rspq->handler(rspq, rspq->cur_desc, &gl);
1835 if (likely(ret == 0))
1836 rspq->offset += ALIGN(fp->size, s->fl_align);
1838 restore_rx_bufs(&gl, &rxq->fl, frag);
1839 } else if (likely(rsp_type == RSPD_TYPE_CPL_X)) {
1840 ret = rspq->handler(rspq, rspq->cur_desc, NULL);
1842 WARN_ON(rsp_type > RSPD_TYPE_CPL_X);
1846 if (unlikely(ret)) {
1848 * Couldn't process descriptor, back off for recovery.
1849 * We use the SGE's last timer which has the longest
1850 * interrupt coalescing value ...
1852 const int NOMEM_TIMER_IDX = SGE_NTIMERS-1;
1853 rspq->next_intr_params =
1854 QINTR_TIMER_IDX_V(NOMEM_TIMER_IDX);
1863 * If this is a Response Queue with an associated Free List and
1864 * at least two Egress Queue units available in the Free List
1865 * for new buffer pointers, refill the Free List.
1867 if (rspq->offset >= 0 &&
1868 fl_cap(&rxq->fl) - rxq->fl.avail >= 2*FL_PER_EQ_UNIT)
1869 __refill_fl(rspq->adapter, &rxq->fl);
1870 return budget - budget_left;
1874 * napi_rx_handler - the NAPI handler for RX processing
1875 * @napi: the napi instance
1876 * @budget: how many packets we can process in this round
1878 * Handler for new data events when using NAPI. This does not need any
1879 * locking or protection from interrupts as data interrupts are off at
1880 * this point and other adapter interrupts do not interfere (the latter
1881 * in not a concern at all with MSI-X as non-data interrupts then have
1882 * a separate handler).
1884 static int napi_rx_handler(struct napi_struct *napi, int budget)
1886 unsigned int intr_params;
1887 struct sge_rspq *rspq = container_of(napi, struct sge_rspq, napi);
1888 int work_done = process_responses(rspq, budget);
1891 if (likely(work_done < budget)) {
1892 napi_complete_done(napi, work_done);
1893 intr_params = rspq->next_intr_params;
1894 rspq->next_intr_params = rspq->intr_params;
1896 intr_params = QINTR_TIMER_IDX_V(SGE_TIMER_UPD_CIDX);
1898 if (unlikely(work_done == 0))
1899 rspq->unhandled_irqs++;
1901 val = CIDXINC_V(work_done) | SEINTARM_V(intr_params);
1902 /* If we don't have access to the new User GTS (T5+), use the old
1903 * doorbell mechanism; otherwise use the new BAR2 mechanism.
1905 if (unlikely(!rspq->bar2_addr)) {
1906 t4_write_reg(rspq->adapter,
1907 T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1908 val | INGRESSQID_V((u32)rspq->cntxt_id));
1910 writel(val | INGRESSQID_V(rspq->bar2_qid),
1911 rspq->bar2_addr + SGE_UDB_GTS);
1918 * The MSI-X interrupt handler for an SGE response queue for the NAPI case
1919 * (i.e., response queue serviced by NAPI polling).
1921 irqreturn_t t4vf_sge_intr_msix(int irq, void *cookie)
1923 struct sge_rspq *rspq = cookie;
1925 napi_schedule(&rspq->napi);
1930 * Process the indirect interrupt entries in the interrupt queue and kick off
1931 * NAPI for each queue that has generated an entry.
1933 static unsigned int process_intrq(struct adapter *adapter)
1935 struct sge *s = &adapter->sge;
1936 struct sge_rspq *intrq = &s->intrq;
1937 unsigned int work_done;
1940 spin_lock(&adapter->sge.intrq_lock);
1941 for (work_done = 0; ; work_done++) {
1942 const struct rsp_ctrl *rc;
1943 unsigned int qid, iq_idx;
1944 struct sge_rspq *rspq;
1947 * Grab the next response from the interrupt queue and bail
1948 * out if it's not a new response.
1950 rc = (void *)intrq->cur_desc + (intrq->iqe_len - sizeof(*rc));
1951 if (!is_new_response(rc, intrq))
1955 * If the response isn't a forwarded interrupt message issue a
1956 * error and go on to the next response message. This should
1960 if (unlikely(RSPD_TYPE_G(rc->type_gen) != RSPD_TYPE_INTR_X)) {
1961 dev_err(adapter->pdev_dev,
1962 "Unexpected INTRQ response type %d\n",
1963 RSPD_TYPE_G(rc->type_gen));
1968 * Extract the Queue ID from the interrupt message and perform
1969 * sanity checking to make sure it really refers to one of our
1970 * Ingress Queues which is active and matches the queue's ID.
1971 * None of these error conditions should ever happen so we may
1972 * want to either make them fatal and/or conditionalized under
1975 qid = RSPD_QID_G(be32_to_cpu(rc->pldbuflen_qid));
1976 iq_idx = IQ_IDX(s, qid);
1977 if (unlikely(iq_idx >= MAX_INGQ)) {
1978 dev_err(adapter->pdev_dev,
1979 "Ingress QID %d out of range\n", qid);
1982 rspq = s->ingr_map[iq_idx];
1983 if (unlikely(rspq == NULL)) {
1984 dev_err(adapter->pdev_dev,
1985 "Ingress QID %d RSPQ=NULL\n", qid);
1988 if (unlikely(rspq->abs_id != qid)) {
1989 dev_err(adapter->pdev_dev,
1990 "Ingress QID %d refers to RSPQ %d\n",
1996 * Schedule NAPI processing on the indicated Response Queue
1997 * and move on to the next entry in the Forwarded Interrupt
2000 napi_schedule(&rspq->napi);
2004 val = CIDXINC_V(work_done) | SEINTARM_V(intrq->intr_params);
2005 /* If we don't have access to the new User GTS (T5+), use the old
2006 * doorbell mechanism; otherwise use the new BAR2 mechanism.
2008 if (unlikely(!intrq->bar2_addr)) {
2009 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
2010 val | INGRESSQID_V(intrq->cntxt_id));
2012 writel(val | INGRESSQID_V(intrq->bar2_qid),
2013 intrq->bar2_addr + SGE_UDB_GTS);
2017 spin_unlock(&adapter->sge.intrq_lock);
2023 * The MSI interrupt handler handles data events from SGE response queues as
2024 * well as error and other async events as they all use the same MSI vector.
2026 static irqreturn_t t4vf_intr_msi(int irq, void *cookie)
2028 struct adapter *adapter = cookie;
2030 process_intrq(adapter);
2035 * t4vf_intr_handler - select the top-level interrupt handler
2036 * @adapter: the adapter
2038 * Selects the top-level interrupt handler based on the type of interrupts
2041 irq_handler_t t4vf_intr_handler(struct adapter *adapter)
2043 BUG_ON((adapter->flags & (USING_MSIX|USING_MSI)) == 0);
2044 if (adapter->flags & USING_MSIX)
2045 return t4vf_sge_intr_msix;
2047 return t4vf_intr_msi;
2051 * sge_rx_timer_cb - perform periodic maintenance of SGE RX queues
2052 * @data: the adapter
2054 * Runs periodically from a timer to perform maintenance of SGE RX queues.
2056 * a) Replenishes RX queues that have run out due to memory shortage.
2057 * Normally new RX buffers are added when existing ones are consumed but
2058 * when out of memory a queue can become empty. We schedule NAPI to do
2059 * the actual refill.
2061 static void sge_rx_timer_cb(unsigned long data)
2063 struct adapter *adapter = (struct adapter *)data;
2064 struct sge *s = &adapter->sge;
2068 * Scan the "Starving Free Lists" flag array looking for any Free
2069 * Lists in need of more free buffers. If we find one and it's not
2070 * being actively polled, then bump its "starving" counter and attempt
2071 * to refill it. If we're successful in adding enough buffers to push
2072 * the Free List over the starving threshold, then we can clear its
2073 * "starving" status.
2075 for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++) {
2078 for (m = s->starving_fl[i]; m; m &= m - 1) {
2079 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
2080 struct sge_fl *fl = s->egr_map[id];
2082 clear_bit(id, s->starving_fl);
2083 smp_mb__after_atomic();
2086 * Since we are accessing fl without a lock there's a
2087 * small probability of a false positive where we
2088 * schedule napi but the FL is no longer starving.
2091 if (fl_starving(adapter, fl)) {
2092 struct sge_eth_rxq *rxq;
2094 rxq = container_of(fl, struct sge_eth_rxq, fl);
2095 if (napi_reschedule(&rxq->rspq.napi))
2098 set_bit(id, s->starving_fl);
2104 * Reschedule the next scan for starving Free Lists ...
2106 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
2110 * sge_tx_timer_cb - perform periodic maintenance of SGE Tx queues
2111 * @data: the adapter
2113 * Runs periodically from a timer to perform maintenance of SGE TX queues.
2115 * b) Reclaims completed Tx packets for the Ethernet queues. Normally
2116 * packets are cleaned up by new Tx packets, this timer cleans up packets
2117 * when no new packets are being submitted. This is essential for pktgen,
2120 static void sge_tx_timer_cb(unsigned long data)
2122 struct adapter *adapter = (struct adapter *)data;
2123 struct sge *s = &adapter->sge;
2124 unsigned int i, budget;
2126 budget = MAX_TIMER_TX_RECLAIM;
2127 i = s->ethtxq_rover;
2129 struct sge_eth_txq *txq = &s->ethtxq[i];
2131 if (reclaimable(&txq->q) && __netif_tx_trylock(txq->txq)) {
2132 int avail = reclaimable(&txq->q);
2137 free_tx_desc(adapter, &txq->q, avail, true);
2138 txq->q.in_use -= avail;
2139 __netif_tx_unlock(txq->txq);
2147 if (i >= s->ethqsets)
2149 } while (i != s->ethtxq_rover);
2150 s->ethtxq_rover = i;
2153 * If we found too many reclaimable packets schedule a timer in the
2154 * near future to continue where we left off. Otherwise the next timer
2155 * will be at its normal interval.
2157 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
2161 * bar2_address - return the BAR2 address for an SGE Queue's Registers
2162 * @adapter: the adapter
2163 * @qid: the SGE Queue ID
2164 * @qtype: the SGE Queue Type (Egress or Ingress)
2165 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
2167 * Returns the BAR2 address for the SGE Queue Registers associated with
2168 * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also
2169 * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE
2170 * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID"
2171 * Registers are supported (e.g. the Write Combining Doorbell Buffer).
2173 static void __iomem *bar2_address(struct adapter *adapter,
2175 enum t4_bar2_qtype qtype,
2176 unsigned int *pbar2_qid)
2181 ret = t4vf_bar2_sge_qregs(adapter, qid, qtype,
2182 &bar2_qoffset, pbar2_qid);
2186 return adapter->bar2 + bar2_qoffset;
2190 * t4vf_sge_alloc_rxq - allocate an SGE RX Queue
2191 * @adapter: the adapter
2192 * @rspq: pointer to to the new rxq's Response Queue to be filled in
2193 * @iqasynch: if 0, a normal rspq; if 1, an asynchronous event queue
2194 * @dev: the network device associated with the new rspq
2195 * @intr_dest: MSI-X vector index (overriden in MSI mode)
2196 * @fl: pointer to the new rxq's Free List to be filled in
2197 * @hnd: the interrupt handler to invoke for the rspq
2199 int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
2200 bool iqasynch, struct net_device *dev,
2202 struct sge_fl *fl, rspq_handler_t hnd)
2204 struct sge *s = &adapter->sge;
2205 struct port_info *pi = netdev_priv(dev);
2206 struct fw_iq_cmd cmd, rpl;
2207 int ret, iqandst, flsz = 0;
2210 * If we're using MSI interrupts and we're not initializing the
2211 * Forwarded Interrupt Queue itself, then set up this queue for
2212 * indirect interrupts to the Forwarded Interrupt Queue. Obviously
2213 * the Forwarded Interrupt Queue must be set up before any other
2216 if ((adapter->flags & USING_MSI) && rspq != &adapter->sge.intrq) {
2217 iqandst = SGE_INTRDST_IQ;
2218 intr_dest = adapter->sge.intrq.abs_id;
2220 iqandst = SGE_INTRDST_PCI;
2223 * Allocate the hardware ring for the Response Queue. The size needs
2224 * to be a multiple of 16 which includes the mandatory status entry
2225 * (regardless of whether the Status Page capabilities are enabled or
2228 rspq->size = roundup(rspq->size, 16);
2229 rspq->desc = alloc_ring(adapter->pdev_dev, rspq->size, rspq->iqe_len,
2230 0, &rspq->phys_addr, NULL, 0);
2235 * Fill in the Ingress Queue Command. Note: Ideally this code would
2236 * be in t4vf_hw.c but there are so many parameters and dependencies
2237 * on our Linux SGE state that we would end up having to pass tons of
2238 * parameters. We'll have to think about how this might be migrated
2239 * into OS-independent common code ...
2241 memset(&cmd, 0, sizeof(cmd));
2242 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) |
2246 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC_F |
2247 FW_IQ_CMD_IQSTART_F |
2249 cmd.type_to_iqandstindex =
2250 cpu_to_be32(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) |
2251 FW_IQ_CMD_IQASYNCH_V(iqasynch) |
2252 FW_IQ_CMD_VIID_V(pi->viid) |
2253 FW_IQ_CMD_IQANDST_V(iqandst) |
2254 FW_IQ_CMD_IQANUS_V(1) |
2255 FW_IQ_CMD_IQANUD_V(SGE_UPDATEDEL_INTR) |
2256 FW_IQ_CMD_IQANDSTINDEX_V(intr_dest));
2257 cmd.iqdroprss_to_iqesize =
2258 cpu_to_be16(FW_IQ_CMD_IQPCIECH_V(pi->port_id) |
2259 FW_IQ_CMD_IQGTSMODE_F |
2260 FW_IQ_CMD_IQINTCNTTHRESH_V(rspq->pktcnt_idx) |
2261 FW_IQ_CMD_IQESIZE_V(ilog2(rspq->iqe_len) - 4));
2262 cmd.iqsize = cpu_to_be16(rspq->size);
2263 cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
2266 enum chip_type chip =
2267 CHELSIO_CHIP_VERSION(adapter->params.chip);
2269 * Allocate the ring for the hardware free list (with space
2270 * for its status page) along with the associated software
2271 * descriptor ring. The free list size needs to be a multiple
2272 * of the Egress Queue Unit and at least 2 Egress Units larger
2273 * than the SGE's Egress Congrestion Threshold
2274 * (fl_starve_thres - 1).
2276 if (fl->size < s->fl_starve_thres - 1 + 2 * FL_PER_EQ_UNIT)
2277 fl->size = s->fl_starve_thres - 1 + 2 * FL_PER_EQ_UNIT;
2278 fl->size = roundup(fl->size, FL_PER_EQ_UNIT);
2279 fl->desc = alloc_ring(adapter->pdev_dev, fl->size,
2280 sizeof(__be64), sizeof(struct rx_sw_desc),
2281 &fl->addr, &fl->sdesc, s->stat_len);
2288 * Calculate the size of the hardware free list ring plus
2289 * Status Page (which the SGE will place after the end of the
2290 * free list ring) in Egress Queue Units.
2292 flsz = (fl->size / FL_PER_EQ_UNIT +
2293 s->stat_len / EQ_UNIT);
2296 * Fill in all the relevant firmware Ingress Queue Command
2297 * fields for the free list.
2299 cmd.iqns_to_fl0congen =
2301 FW_IQ_CMD_FL0HOSTFCMODE_V(SGE_HOSTFCMODE_NONE) |
2302 FW_IQ_CMD_FL0PACKEN_F |
2303 FW_IQ_CMD_FL0PADEN_F);
2305 /* In T6, for egress queue type FL there is internal overhead
2306 * of 16B for header going into FLM module. Hence the maximum
2307 * allowed burst size is 448 bytes. For T4/T5, the hardware
2308 * doesn't coalesce fetch requests if more than 64 bytes of
2309 * Free List pointers are provided, so we use a 128-byte Fetch
2310 * Burst Minimum there (T6 implements coalescing so we can use
2311 * the smaller 64-byte value there).
2313 cmd.fl0dcaen_to_fl0cidxfthresh =
2315 FW_IQ_CMD_FL0FBMIN_V(chip <= CHELSIO_T5 ?
2316 FETCHBURSTMIN_128B_X :
2317 FETCHBURSTMIN_64B_X) |
2318 FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
2319 FETCHBURSTMAX_512B_X :
2320 FETCHBURSTMAX_256B_X));
2321 cmd.fl0size = cpu_to_be16(flsz);
2322 cmd.fl0addr = cpu_to_be64(fl->addr);
2326 * Issue the firmware Ingress Queue Command and extract the results if
2327 * it completes successfully.
2329 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2333 netif_napi_add(dev, &rspq->napi, napi_rx_handler, 64);
2334 rspq->cur_desc = rspq->desc;
2337 rspq->next_intr_params = rspq->intr_params;
2338 rspq->cntxt_id = be16_to_cpu(rpl.iqid);
2339 rspq->bar2_addr = bar2_address(adapter,
2341 T4_BAR2_QTYPE_INGRESS,
2343 rspq->abs_id = be16_to_cpu(rpl.physiqid);
2344 rspq->size--; /* subtract status entry */
2345 rspq->adapter = adapter;
2347 rspq->handler = hnd;
2349 /* set offset to -1 to distinguish ingress queues without FL */
2350 rspq->offset = fl ? 0 : -1;
2353 fl->cntxt_id = be16_to_cpu(rpl.fl0id);
2358 fl->alloc_failed = 0;
2359 fl->large_alloc_failed = 0;
2362 /* Note, we must initialize the BAR2 Free List User Doorbell
2363 * information before refilling the Free List!
2365 fl->bar2_addr = bar2_address(adapter,
2367 T4_BAR2_QTYPE_EGRESS,
2370 refill_fl(adapter, fl, fl_cap(fl), GFP_KERNEL);
2377 * An error occurred. Clean up our partial allocation state and
2381 dma_free_coherent(adapter->pdev_dev, rspq->size * rspq->iqe_len,
2382 rspq->desc, rspq->phys_addr);
2385 if (fl && fl->desc) {
2388 dma_free_coherent(adapter->pdev_dev, flsz * EQ_UNIT,
2389 fl->desc, fl->addr);
2396 * t4vf_sge_alloc_eth_txq - allocate an SGE Ethernet TX Queue
2397 * @adapter: the adapter
2398 * @txq: pointer to the new txq to be filled in
2399 * @devq: the network TX queue associated with the new txq
2400 * @iqid: the relative ingress queue ID to which events relating to
2401 * the new txq should be directed
2403 int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
2404 struct net_device *dev, struct netdev_queue *devq,
2407 struct sge *s = &adapter->sge;
2409 struct fw_eq_eth_cmd cmd, rpl;
2410 struct port_info *pi = netdev_priv(dev);
2413 * Calculate the size of the hardware TX Queue (including the Status
2414 * Page on the end of the TX Queue) in units of TX Descriptors.
2416 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2419 * Allocate the hardware ring for the TX ring (with space for its
2420 * status page) along with the associated software descriptor ring.
2422 txq->q.desc = alloc_ring(adapter->pdev_dev, txq->q.size,
2423 sizeof(struct tx_desc),
2424 sizeof(struct tx_sw_desc),
2425 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len);
2430 * Fill in the Egress Queue Command. Note: As with the direct use of
2431 * the firmware Ingress Queue COmmand above in our RXQ allocation
2432 * routine, ideally, this code would be in t4vf_hw.c. Again, we'll
2433 * have to see if there's some reasonable way to parameterize it
2434 * into the common code ...
2436 memset(&cmd, 0, sizeof(cmd));
2437 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
2441 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC_F |
2442 FW_EQ_ETH_CMD_EQSTART_F |
2444 cmd.viid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_AUTOEQUEQE_F |
2445 FW_EQ_ETH_CMD_VIID_V(pi->viid));
2446 cmd.fetchszm_to_iqid =
2447 cpu_to_be32(FW_EQ_ETH_CMD_HOSTFCMODE_V(SGE_HOSTFCMODE_STPG) |
2448 FW_EQ_ETH_CMD_PCIECHN_V(pi->port_id) |
2449 FW_EQ_ETH_CMD_IQID_V(iqid));
2450 cmd.dcaen_to_eqsize =
2451 cpu_to_be32(FW_EQ_ETH_CMD_FBMIN_V(SGE_FETCHBURSTMIN_64B) |
2452 FW_EQ_ETH_CMD_FBMAX_V(SGE_FETCHBURSTMAX_512B) |
2453 FW_EQ_ETH_CMD_CIDXFTHRESH_V(
2454 SGE_CIDXFLUSHTHRESH_32) |
2455 FW_EQ_ETH_CMD_EQSIZE_V(nentries));
2456 cmd.eqaddr = cpu_to_be64(txq->q.phys_addr);
2459 * Issue the firmware Egress Queue Command and extract the results if
2460 * it completes successfully.
2462 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2465 * The girmware Ingress Queue Command failed for some reason.
2466 * Free up our partial allocation state and return the error.
2468 kfree(txq->q.sdesc);
2469 txq->q.sdesc = NULL;
2470 dma_free_coherent(adapter->pdev_dev,
2471 nentries * sizeof(struct tx_desc),
2472 txq->q.desc, txq->q.phys_addr);
2480 txq->q.stat = (void *)&txq->q.desc[txq->q.size];
2481 txq->q.cntxt_id = FW_EQ_ETH_CMD_EQID_G(be32_to_cpu(rpl.eqid_pkd));
2482 txq->q.bar2_addr = bar2_address(adapter,
2484 T4_BAR2_QTYPE_EGRESS,
2487 FW_EQ_ETH_CMD_PHYSEQID_G(be32_to_cpu(rpl.physeqid_pkd));
2493 txq->q.restarts = 0;
2494 txq->mapping_err = 0;
2499 * Free the DMA map resources associated with a TX queue.
2501 static void free_txq(struct adapter *adapter, struct sge_txq *tq)
2503 struct sge *s = &adapter->sge;
2505 dma_free_coherent(adapter->pdev_dev,
2506 tq->size * sizeof(*tq->desc) + s->stat_len,
2507 tq->desc, tq->phys_addr);
2514 * Free the resources associated with a response queue (possibly including a
2517 static void free_rspq_fl(struct adapter *adapter, struct sge_rspq *rspq,
2520 struct sge *s = &adapter->sge;
2521 unsigned int flid = fl ? fl->cntxt_id : 0xffff;
2523 t4vf_iq_free(adapter, FW_IQ_TYPE_FL_INT_CAP,
2524 rspq->cntxt_id, flid, 0xffff);
2525 dma_free_coherent(adapter->pdev_dev, (rspq->size + 1) * rspq->iqe_len,
2526 rspq->desc, rspq->phys_addr);
2527 netif_napi_del(&rspq->napi);
2528 rspq->netdev = NULL;
2534 free_rx_bufs(adapter, fl, fl->avail);
2535 dma_free_coherent(adapter->pdev_dev,
2536 fl->size * sizeof(*fl->desc) + s->stat_len,
2537 fl->desc, fl->addr);
2546 * t4vf_free_sge_resources - free SGE resources
2547 * @adapter: the adapter
2549 * Frees resources used by the SGE queue sets.
2551 void t4vf_free_sge_resources(struct adapter *adapter)
2553 struct sge *s = &adapter->sge;
2554 struct sge_eth_rxq *rxq = s->ethrxq;
2555 struct sge_eth_txq *txq = s->ethtxq;
2556 struct sge_rspq *evtq = &s->fw_evtq;
2557 struct sge_rspq *intrq = &s->intrq;
2560 for (qs = 0; qs < adapter->sge.ethqsets; qs++, rxq++, txq++) {
2562 free_rspq_fl(adapter, &rxq->rspq, &rxq->fl);
2564 t4vf_eth_eq_free(adapter, txq->q.cntxt_id);
2565 free_tx_desc(adapter, &txq->q, txq->q.in_use, true);
2566 kfree(txq->q.sdesc);
2567 free_txq(adapter, &txq->q);
2571 free_rspq_fl(adapter, evtq, NULL);
2573 free_rspq_fl(adapter, intrq, NULL);
2577 * t4vf_sge_start - enable SGE operation
2578 * @adapter: the adapter
2580 * Start tasklets and timers associated with the DMA engine.
2582 void t4vf_sge_start(struct adapter *adapter)
2584 adapter->sge.ethtxq_rover = 0;
2585 mod_timer(&adapter->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2586 mod_timer(&adapter->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2590 * t4vf_sge_stop - disable SGE operation
2591 * @adapter: the adapter
2593 * Stop tasklets and timers associated with the DMA engine. Note that
2594 * this is effective only if measures have been taken to disable any HW
2595 * events that may restart them.
2597 void t4vf_sge_stop(struct adapter *adapter)
2599 struct sge *s = &adapter->sge;
2601 if (s->rx_timer.function)
2602 del_timer_sync(&s->rx_timer);
2603 if (s->tx_timer.function)
2604 del_timer_sync(&s->tx_timer);
2608 * t4vf_sge_init - initialize SGE
2609 * @adapter: the adapter
2611 * Performs SGE initialization needed every time after a chip reset.
2612 * We do not initialize any of the queue sets here, instead the driver
2613 * top-level must request those individually. We also do not enable DMA
2614 * here, that should be done after the queues have been set up.
2616 int t4vf_sge_init(struct adapter *adapter)
2618 struct sge_params *sge_params = &adapter->params.sge;
2619 u32 fl0 = sge_params->sge_fl_buffer_size[0];
2620 u32 fl1 = sge_params->sge_fl_buffer_size[1];
2621 struct sge *s = &adapter->sge;
2624 * Start by vetting the basic SGE parameters which have been set up by
2625 * the Physical Function Driver. Ideally we should be able to deal
2626 * with _any_ configuration. Practice is different ...
2628 if (fl0 != PAGE_SIZE || (fl1 != 0 && fl1 <= fl0)) {
2629 dev_err(adapter->pdev_dev, "bad SGE FL buffer sizes [%d, %d]\n",
2633 if ((sge_params->sge_control & RXPKTCPLMODE_F) !=
2634 RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) {
2635 dev_err(adapter->pdev_dev, "bad SGE CPL MODE\n");
2640 * Now translate the adapter parameters into our internal forms.
2643 s->fl_pg_order = ilog2(fl1) - PAGE_SHIFT;
2644 s->stat_len = ((sge_params->sge_control & EGRSTATUSPAGESIZE_F)
2646 s->pktshift = PKTSHIFT_G(sge_params->sge_control);
2647 s->fl_align = t4vf_fl_pkt_align(adapter);
2649 /* A FL with <= fl_starve_thres buffers is starving and a periodic
2650 * timer will attempt to refill it. This needs to be larger than the
2651 * SGE's Egress Congestion Threshold. If it isn't, then we can get
2652 * stuck waiting for new packets while the SGE is waiting for us to
2653 * give it more Free List entries. (Note that the SGE's Egress
2654 * Congestion Threshold is in units of 2 Free List pointers.)
2656 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
2658 s->fl_starve_thres =
2659 EGRTHRESHOLD_G(sge_params->sge_congestion_control);
2662 s->fl_starve_thres =
2663 EGRTHRESHOLDPACKING_G(sge_params->sge_congestion_control);
2667 s->fl_starve_thres =
2668 T6_EGRTHRESHOLDPACKING_G(sge_params->sge_congestion_control);
2671 s->fl_starve_thres = s->fl_starve_thres * 2 + 1;
2674 * Set up tasklet timers.
2676 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adapter);
2677 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adapter);
2680 * Initialize Forwarded Interrupt Queue lock.
2682 spin_lock_init(&s->intrq_lock);