drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed successfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_FR_NSMR_TPTE_WR          = 0x20,
 104         FW_RI_RDMA_WRITE_CMPL_WR       = 0x21,
 105         FW_RI_INV_LSTAG_WR             = 0x1a,
 106         FW_ISCSI_TX_DATA_WR            = 0x45,
 107         FW_PTP_TX_PKT_WR               = 0x46,
 108         FW_TLSTX_DATA_WR               = 0x68,
 109         FW_CRYPTO_LOOKASIDE_WR         = 0X6d,
 110         FW_LASTC2E_WR                  = 0x70,
 111         FW_FILTER2_WR                  = 0x77
 112 };
 113
 114 struct fw_wr_hdr {
 115         __be32 hi;
 116         __be32 lo;
 117 };
 118
 119 /* work request opcode (hi) */
 120 #define FW_WR_OP_S      24
 121 #define FW_WR_OP_M      0xff
 122 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 123 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 124
 125 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 126 #define FW_WR_ATOMIC_S          23
 127 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 128
 129 /* flush flag (hi) - firmware flushes flushable work request buffered
 130  * in the flow context.
 131  */
 132 #define FW_WR_FLUSH_S     22
 133 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 134
 135 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 136 #define FW_WR_COMPL_S     21
 137 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 138 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 139
 140 /* work request immediate data length (hi) */
 141 #define FW_WR_IMMDLEN_S 0
 142 #define FW_WR_IMMDLEN_M 0xff
 143 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 144
 145 /* egress queue status update to associated ingress queue entry (lo) */
 146 #define FW_WR_EQUIQ_S           31
 147 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 148 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 149
 150 /* egress queue status update to egress queue status entry (lo) */
 151 #define FW_WR_EQUEQ_S           30
 152 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 153 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 154
 155 /* flow context identifier (lo) */
 156 #define FW_WR_FLOWID_S          8
 157 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 158
 159 /* length in units of 16-bytes (lo) */
 160 #define FW_WR_LEN16_S           0
 161 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 162
 163 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 164 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 165
 166 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 167 enum fw_filter_wr_cookie {
 168         FW_FILTER_WR_SUCCESS,
 169         FW_FILTER_WR_FLT_ADDED,
 170         FW_FILTER_WR_FLT_DELETED,
 171         FW_FILTER_WR_SMT_TBL_FULL,
 172         FW_FILTER_WR_EINVAL,
 173 };
 174
 175 struct fw_filter_wr {
 176         __be32 op_pkd;
 177         __be32 len16_pkd;
 178         __be64 r3;
 179         __be32 tid_to_iq;
 180         __be32 del_filter_to_l2tix;
 181         __be16 ethtype;
 182         __be16 ethtypem;
 183         __u8   frag_to_ovlan_vldm;
 184         __u8   smac_sel;
 185         __be16 rx_chan_rx_rpl_iq;
 186         __be32 maci_to_matchtypem;
 187         __u8   ptcl;
 188         __u8   ptclm;
 189         __u8   ttyp;
 190         __u8   ttypm;
 191         __be16 ivlan;
 192         __be16 ivlanm;
 193         __be16 ovlan;
 194         __be16 ovlanm;
 195         __u8   lip[16];
 196         __u8   lipm[16];
 197         __u8   fip[16];
 198         __u8   fipm[16];
 199         __be16 lp;
 200         __be16 lpm;
 201         __be16 fp;
 202         __be16 fpm;
 203         __be16 r7;
 204         __u8   sma[6];
 205 };
 206
 207 struct fw_filter2_wr {
 208         __be32 op_pkd;
 209         __be32 len16_pkd;
 210         __be64 r3;
 211         __be32 tid_to_iq;
 212         __be32 del_filter_to_l2tix;
 213         __be16 ethtype;
 214         __be16 ethtypem;
 215         __u8   frag_to_ovlan_vldm;
 216         __u8   smac_sel;
 217         __be16 rx_chan_rx_rpl_iq;
 218         __be32 maci_to_matchtypem;
 219         __u8   ptcl;
 220         __u8   ptclm;
 221         __u8   ttyp;
 222         __u8   ttypm;
 223         __be16 ivlan;
 224         __be16 ivlanm;
 225         __be16 ovlan;
 226         __be16 ovlanm;
 227         __u8   lip[16];
 228         __u8   lipm[16];
 229         __u8   fip[16];
 230         __u8   fipm[16];
 231         __be16 lp;
 232         __be16 lpm;
 233         __be16 fp;
 234         __be16 fpm;
 235         __be16 r7;
 236         __u8   sma[6];
 237         __be16 r8;
 238         __u8   filter_type_swapmac;
 239         __u8   natmode_to_ulp_type;
 240         __be16 newlport;
 241         __be16 newfport;
 242         __u8   newlip[16];
 243         __u8   newfip[16];
 244         __be32 natseqcheck;
 245         __be32 r9;
 246         __be64 r10;
 247         __be64 r11;
 248         __be64 r12;
 249         __be64 r13;
 250 };
 251
 252 #define FW_FILTER_WR_TID_S      12
 253 #define FW_FILTER_WR_TID_M      0xfffff
 254 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 255 #define FW_FILTER_WR_TID_G(x)   \
 256         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 257
 258 #define FW_FILTER_WR_RQTYPE_S           11
 259 #define FW_FILTER_WR_RQTYPE_M           0x1
 260 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 261 #define FW_FILTER_WR_RQTYPE_G(x)        \
 262         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 263 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 264
 265 #define FW_FILTER_WR_NOREPLY_S          10
 266 #define FW_FILTER_WR_NOREPLY_M          0x1
 267 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 268 #define FW_FILTER_WR_NOREPLY_G(x)       \
 269         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 270 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 271
 272 #define FW_FILTER_WR_IQ_S       0
 273 #define FW_FILTER_WR_IQ_M       0x3ff
 274 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 275 #define FW_FILTER_WR_IQ_G(x)    \
 276         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 277
 278 #define FW_FILTER_WR_DEL_FILTER_S       31
 279 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 280 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 281 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 282         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 283 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 284
 285 #define FW_FILTER_WR_RPTTID_S           25
 286 #define FW_FILTER_WR_RPTTID_M           0x1
 287 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 288 #define FW_FILTER_WR_RPTTID_G(x)        \
 289         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 290 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 291
 292 #define FW_FILTER_WR_DROP_S     24
 293 #define FW_FILTER_WR_DROP_M     0x1
 294 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 295 #define FW_FILTER_WR_DROP_G(x)  \
 296         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 297 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 298
 299 #define FW_FILTER_WR_DIRSTEER_S         23
 300 #define FW_FILTER_WR_DIRSTEER_M         0x1
 301 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 302 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 303         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 304 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 305
 306 #define FW_FILTER_WR_MASKHASH_S         22
 307 #define FW_FILTER_WR_MASKHASH_M         0x1
 308 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 309 #define FW_FILTER_WR_MASKHASH_G(x)      \
 310         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 311 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 312
 313 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 314 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 315 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 316 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 317         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 318 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 319
 320 #define FW_FILTER_WR_LPBK_S     20
 321 #define FW_FILTER_WR_LPBK_M     0x1
 322 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 323 #define FW_FILTER_WR_LPBK_G(x)  \
 324         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 325 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 326
 327 #define FW_FILTER_WR_DMAC_S     19
 328 #define FW_FILTER_WR_DMAC_M     0x1
 329 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 330 #define FW_FILTER_WR_DMAC_G(x)  \
 331         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 332 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 333
 334 #define FW_FILTER_WR_SMAC_S     18
 335 #define FW_FILTER_WR_SMAC_M     0x1
 336 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 337 #define FW_FILTER_WR_SMAC_G(x)  \
 338         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 339 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 340
 341 #define FW_FILTER_WR_INSVLAN_S          17
 342 #define FW_FILTER_WR_INSVLAN_M          0x1
 343 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 344 #define FW_FILTER_WR_INSVLAN_G(x)       \
 345         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 346 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 347
 348 #define FW_FILTER_WR_RMVLAN_S           16
 349 #define FW_FILTER_WR_RMVLAN_M           0x1
 350 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 351 #define FW_FILTER_WR_RMVLAN_G(x)        \
 352         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 353 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 354
 355 #define FW_FILTER_WR_HITCNTS_S          15
 356 #define FW_FILTER_WR_HITCNTS_M          0x1
 357 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 358 #define FW_FILTER_WR_HITCNTS_G(x)       \
 359         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 360 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 361
 362 #define FW_FILTER_WR_TXCHAN_S           13
 363 #define FW_FILTER_WR_TXCHAN_M           0x3
 364 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 365 #define FW_FILTER_WR_TXCHAN_G(x)        \
 366         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 367
 368 #define FW_FILTER_WR_PRIO_S     12
 369 #define FW_FILTER_WR_PRIO_M     0x1
 370 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 371 #define FW_FILTER_WR_PRIO_G(x)  \
 372         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 373 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 374
 375 #define FW_FILTER_WR_L2TIX_S    0
 376 #define FW_FILTER_WR_L2TIX_M    0xfff
 377 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 378 #define FW_FILTER_WR_L2TIX_G(x) \
 379         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 380
 381 #define FW_FILTER_WR_FRAG_S     7
 382 #define FW_FILTER_WR_FRAG_M     0x1
 383 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 384 #define FW_FILTER_WR_FRAG_G(x)  \
 385         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 386 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 387
 388 #define FW_FILTER_WR_FRAGM_S    6
 389 #define FW_FILTER_WR_FRAGM_M    0x1
 390 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 391 #define FW_FILTER_WR_FRAGM_G(x) \
 392         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 393 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 394
 395 #define FW_FILTER_WR_IVLAN_VLD_S        5
 396 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 397 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 398 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 399         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 400 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 401
 402 #define FW_FILTER_WR_OVLAN_VLD_S        4
 403 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 404 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 405 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 406         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 407 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 408
 409 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 410 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 411 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 412 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 413         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 414 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 415
 416 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 417 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 418 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 419 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 420         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 421 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 422
 423 #define FW_FILTER_WR_RX_CHAN_S          15
 424 #define FW_FILTER_WR_RX_CHAN_M          0x1
 425 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 426 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 427         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 428 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 429
 430 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 431 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 432 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 433 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 434         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 435
 436 #define FW_FILTER2_WR_FILTER_TYPE_S     1
 437 #define FW_FILTER2_WR_FILTER_TYPE_M     0x1
 438 #define FW_FILTER2_WR_FILTER_TYPE_V(x)  ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
 439 #define FW_FILTER2_WR_FILTER_TYPE_G(x)  \
 440         (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
 441 #define FW_FILTER2_WR_FILTER_TYPE_F     FW_FILTER2_WR_FILTER_TYPE_V(1U)
 442
 443 #define FW_FILTER2_WR_NATMODE_S         5
 444 #define FW_FILTER2_WR_NATMODE_M         0x7
 445 #define FW_FILTER2_WR_NATMODE_V(x)      ((x) << FW_FILTER2_WR_NATMODE_S)
 446 #define FW_FILTER2_WR_NATMODE_G(x)      \
 447         (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
 448
 449 #define FW_FILTER2_WR_NATFLAGCHECK_S    4
 450 #define FW_FILTER2_WR_NATFLAGCHECK_M    0x1
 451 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
 452 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
 453         (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
 454 #define FW_FILTER2_WR_NATFLAGCHECK_F    FW_FILTER2_WR_NATFLAGCHECK_V(1U)
 455
 456 #define FW_FILTER2_WR_ULP_TYPE_S        0
 457 #define FW_FILTER2_WR_ULP_TYPE_M        0xf
 458 #define FW_FILTER2_WR_ULP_TYPE_V(x)     ((x) << FW_FILTER2_WR_ULP_TYPE_S)
 459 #define FW_FILTER2_WR_ULP_TYPE_G(x)     \
 460         (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
 461
 462 #define FW_FILTER_WR_MACI_S     23
 463 #define FW_FILTER_WR_MACI_M     0x1ff
 464 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 465 #define FW_FILTER_WR_MACI_G(x)  \
 466         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 467
 468 #define FW_FILTER_WR_MACIM_S    14
 469 #define FW_FILTER_WR_MACIM_M    0x1ff
 470 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 471 #define FW_FILTER_WR_MACIM_G(x) \
 472         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 473
 474 #define FW_FILTER_WR_FCOE_S     13
 475 #define FW_FILTER_WR_FCOE_M     0x1
 476 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 477 #define FW_FILTER_WR_FCOE_G(x)  \
 478         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 479 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 480
 481 #define FW_FILTER_WR_FCOEM_S    12
 482 #define FW_FILTER_WR_FCOEM_M    0x1
 483 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 484 #define FW_FILTER_WR_FCOEM_G(x) \
 485         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 486 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 487
 488 #define FW_FILTER_WR_PORT_S     9
 489 #define FW_FILTER_WR_PORT_M     0x7
 490 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 491 #define FW_FILTER_WR_PORT_G(x)  \
 492         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 493
 494 #define FW_FILTER_WR_PORTM_S    6
 495 #define FW_FILTER_WR_PORTM_M    0x7
 496 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 497 #define FW_FILTER_WR_PORTM_G(x) \
 498         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 499
 500 #define FW_FILTER_WR_MATCHTYPE_S        3
 501 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 502 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 503 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 504         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 505
 506 #define FW_FILTER_WR_MATCHTYPEM_S       0
 507 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 508 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 509 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 510         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 511
 512 struct fw_ulptx_wr {
 513         __be32 op_to_compl;
 514         __be32 flowid_len16;
 515         u64 cookie;
 516 };
 517
 518 #define FW_ULPTX_WR_DATA_S      28
 519 #define FW_ULPTX_WR_DATA_M      0x1
 520 #define FW_ULPTX_WR_DATA_V(x)   ((x) << FW_ULPTX_WR_DATA_S)
 521 #define FW_ULPTX_WR_DATA_G(x)   \
 522         (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M)
 523 #define FW_ULPTX_WR_DATA_F      FW_ULPTX_WR_DATA_V(1U)
 524
 525 struct fw_tp_wr {
 526         __be32 op_to_immdlen;
 527         __be32 flowid_len16;
 528         u64 cookie;
 529 };
 530
 531 struct fw_eth_tx_pkt_wr {
 532         __be32 op_immdlen;
 533         __be32 equiq_to_len16;
 534         __be64 r3;
 535 };
 536
 537 struct fw_ofld_connection_wr {
 538         __be32 op_compl;
 539         __be32 len16_pkd;
 540         __u64  cookie;
 541         __be64 r2;
 542         __be64 r3;
 543         struct fw_ofld_connection_le {
 544                 __be32 version_cpl;
 545                 __be32 filter;
 546                 __be32 r1;
 547                 __be16 lport;
 548                 __be16 pport;
 549                 union fw_ofld_connection_leip {
 550                         struct fw_ofld_connection_le_ipv4 {
 551                                 __be32 pip;
 552                                 __be32 lip;
 553                                 __be64 r0;
 554                                 __be64 r1;
 555                                 __be64 r2;
 556                         } ipv4;
 557                         struct fw_ofld_connection_le_ipv6 {
 558                                 __be64 pip_hi;
 559                                 __be64 pip_lo;
 560                                 __be64 lip_hi;
 561                                 __be64 lip_lo;
 562                         } ipv6;
 563                 } u;
 564         } le;
 565         struct fw_ofld_connection_tcb {
 566                 __be32 t_state_to_astid;
 567                 __be16 cplrxdataack_cplpassacceptrpl;
 568                 __be16 rcv_adv;
 569                 __be32 rcv_nxt;
 570                 __be32 tx_max;
 571                 __be64 opt0;
 572                 __be32 opt2;
 573                 __be32 r1;
 574                 __be64 r2;
 575                 __be64 r3;
 576         } tcb;
 577 };
 578
 579 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 580 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 581 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 582         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 583 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 584         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 585         FW_OFLD_CONNECTION_WR_VERSION_M)
 586 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 587         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 588
 589 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 590 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 591 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 592 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 593         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 594 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 595
 596 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 597 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 598 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 599         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 600 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 601         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 602         FW_OFLD_CONNECTION_WR_T_STATE_M)
 603
 604 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 605 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 606 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 607         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 608 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 609         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 610         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 611
 612 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 613 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 614 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 615         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 616 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 617         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 618
 619 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 620 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 621 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 622         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 623 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 624         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 625         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 626 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 627         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 628
 629 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 630 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 631 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 632         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 633 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 634         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 635         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 636 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 637         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 638
 639 enum fw_flowc_mnem_tcpstate {
 640         FW_FLOWC_MNEM_TCPSTATE_CLOSED   = 0, /* illegal */
 641         FW_FLOWC_MNEM_TCPSTATE_LISTEN   = 1, /* illegal */
 642         FW_FLOWC_MNEM_TCPSTATE_SYNSENT  = 2, /* illegal */
 643         FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
 644         FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
 645         FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
 646         FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
 647                                               * will resend FIN - equiv ESTAB
 648                                               */
 649         FW_FLOWC_MNEM_TCPSTATE_CLOSING  = 7, /* haven't gotten ACK for FIN and
 650                                               * will resend FIN but have
 651                                               * received FIN
 652                                               */
 653         FW_FLOWC_MNEM_TCPSTATE_LASTACK  = 8, /* haven't gotten ACK for FIN and
 654                                               * will resend FIN but have
 655                                               * received FIN
 656                                               */
 657         FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
 658                                               * waiting for FIN
 659                                               */
 660         FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
 661 };
 662
 663 enum fw_flowc_mnem {
 664         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 665         FW_FLOWC_MNEM_CH,
 666         FW_FLOWC_MNEM_PORT,
 667         FW_FLOWC_MNEM_IQID,
 668         FW_FLOWC_MNEM_SNDNXT,
 669         FW_FLOWC_MNEM_RCVNXT,
 670         FW_FLOWC_MNEM_SNDBUF,
 671         FW_FLOWC_MNEM_MSS,
 672         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 673         FW_FLOWC_MNEM_TCPSTATE,
 674         FW_FLOWC_MNEM_EOSTATE,
 675         FW_FLOWC_MNEM_SCHEDCLASS,
 676         FW_FLOWC_MNEM_DCBPRIO,
 677         FW_FLOWC_MNEM_SND_SCALE,
 678         FW_FLOWC_MNEM_RCV_SCALE,
 679         FW_FLOWC_MNEM_ULD_MODE,
 680         FW_FLOWC_MNEM_MAX,
 681 };
 682
 683 struct fw_flowc_mnemval {
 684         u8 mnemonic;
 685         u8 r4[3];
 686         __be32 val;
 687 };
 688
 689 struct fw_flowc_wr {
 690         __be32 op_to_nparams;
 691         __be32 flowid_len16;
 692         struct fw_flowc_mnemval mnemval[0];
 693 };
 694
 695 #define FW_FLOWC_WR_NPARAMS_S           0
 696 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 697
 698 struct fw_ofld_tx_data_wr {
 699         __be32 op_to_immdlen;
 700         __be32 flowid_len16;
 701         __be32 plen;
 702         __be32 tunnel_to_proxy;
 703 };
 704
 705 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S   30
 706 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)
 707 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F   FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U)
 708
 709 #define FW_OFLD_TX_DATA_WR_SHOVE_S      29
 710 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 711 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 712
 713 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 714 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 715
 716 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 717 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 718
 719 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 720 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 721 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 722
 723 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 724 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 725
 726 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 727 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 728
 729 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 730 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 731
 732 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 733 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 734         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 735
 736 struct fw_cmd_wr {
 737         __be32 op_dma;
 738         __be32 len16_pkd;
 739         __be64 cookie_daddr;
 740 };
 741
 742 #define FW_CMD_WR_DMA_S         17
 743 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 744
 745 struct fw_eth_tx_pkt_vm_wr {
 746         __be32 op_immdlen;
 747         __be32 equiq_to_len16;
 748         __be32 r3[2];
 749         u8 ethmacdst[6];
 750         u8 ethmacsrc[6];
 751         __be16 ethtype;
 752         __be16 vlantci;
 753 };
 754
 755 #define FW_CMD_MAX_TIMEOUT 10000
 756
 757 /*
 758  * If a host driver does a HELLO and discovers that there's already a MASTER
 759  * selected, we may have to wait for that MASTER to finish issuing RESET,
 760  * configuration and INITIALIZE commands.  Also, there's a possibility that
 761  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 762  * RESET command, so we need to be willing to make a few retries of our HELLO.
 763  */
 764 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 765 #define FW_CMD_HELLO_RETRIES    3
 766
 767
 768 enum fw_cmd_opcodes {
 769         FW_LDST_CMD                    = 0x01,
 770         FW_RESET_CMD                   = 0x03,
 771         FW_HELLO_CMD                   = 0x04,
 772         FW_BYE_CMD                     = 0x05,
 773         FW_INITIALIZE_CMD              = 0x06,
 774         FW_CAPS_CONFIG_CMD             = 0x07,
 775         FW_PARAMS_CMD                  = 0x08,
 776         FW_PFVF_CMD                    = 0x09,
 777         FW_IQ_CMD                      = 0x10,
 778         FW_EQ_MNGT_CMD                 = 0x11,
 779         FW_EQ_ETH_CMD                  = 0x12,
 780         FW_EQ_CTRL_CMD                 = 0x13,
 781         FW_EQ_OFLD_CMD                 = 0x21,
 782         FW_VI_CMD                      = 0x14,
 783         FW_VI_MAC_CMD                  = 0x15,
 784         FW_VI_RXMODE_CMD               = 0x16,
 785         FW_VI_ENABLE_CMD               = 0x17,
 786         FW_ACL_MAC_CMD                 = 0x18,
 787         FW_ACL_VLAN_CMD                = 0x19,
 788         FW_VI_STATS_CMD                = 0x1a,
 789         FW_PORT_CMD                    = 0x1b,
 790         FW_PORT_STATS_CMD              = 0x1c,
 791         FW_PORT_LB_STATS_CMD           = 0x1d,
 792         FW_PORT_TRACE_CMD              = 0x1e,
 793         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 794         FW_RSS_IND_TBL_CMD             = 0x20,
 795         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 796         FW_RSS_VI_CONFIG_CMD           = 0x23,
 797         FW_SCHED_CMD                   = 0x24,
 798         FW_DEVLOG_CMD                  = 0x25,
 799         FW_CLIP_CMD                    = 0x28,
 800         FW_PTP_CMD                     = 0x3e,
 801         FW_HMA_CMD                     = 0x3f,
 802         FW_LASTC2E_CMD                 = 0x40,
 803         FW_ERROR_CMD                   = 0x80,
 804         FW_DEBUG_CMD                   = 0x81,
 805 };
 806
 807 enum fw_cmd_cap {
 808         FW_CMD_CAP_PF                  = 0x01,
 809         FW_CMD_CAP_DMAQ                = 0x02,
 810         FW_CMD_CAP_PORT                = 0x04,
 811         FW_CMD_CAP_PORTPROMISC         = 0x08,
 812         FW_CMD_CAP_PORTSTATS           = 0x10,
 813         FW_CMD_CAP_VF                  = 0x80,
 814 };
 815
 816 /*
 817  * Generic command header flit0
 818  */
 819 struct fw_cmd_hdr {
 820         __be32 hi;
 821         __be32 lo;
 822 };
 823
 824 #define FW_CMD_OP_S             24
 825 #define FW_CMD_OP_M             0xff
 826 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 827 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 828
 829 #define FW_CMD_REQUEST_S        23
 830 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 831 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 832
 833 #define FW_CMD_READ_S           22
 834 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 835 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 836
 837 #define FW_CMD_WRITE_S          21
 838 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 839 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 840
 841 #define FW_CMD_EXEC_S           20
 842 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 843 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 844
 845 #define FW_CMD_RAMASK_S         20
 846 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 847
 848 #define FW_CMD_RETVAL_S         8
 849 #define FW_CMD_RETVAL_M         0xff
 850 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 851 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 852
 853 #define FW_CMD_LEN16_S          0
 854 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 855
 856 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 857
 858 enum fw_ldst_addrspc {
 859         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 860         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 861         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 862         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 863         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 864         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 865         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 866         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 867         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 868         FW_LDST_ADDRSPC_MPS       = 0x0020,
 869         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 870         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 871         FW_LDST_ADDRSPC_I2C       = 0x0038,
 872 };
 873
 874 enum fw_ldst_mps_fid {
 875         FW_LDST_MPS_ATRB,
 876         FW_LDST_MPS_RPLC
 877 };
 878
 879 enum fw_ldst_func_access_ctl {
 880         FW_LDST_FUNC_ACC_CTL_VIID,
 881         FW_LDST_FUNC_ACC_CTL_FID
 882 };
 883
 884 enum fw_ldst_func_mod_index {
 885         FW_LDST_FUNC_MPS
 886 };
 887
 888 struct fw_ldst_cmd {
 889         __be32 op_to_addrspace;
 890         __be32 cycles_to_len16;
 891         union fw_ldst {
 892                 struct fw_ldst_addrval {
 893                         __be32 addr;
 894                         __be32 val;
 895                 } addrval;
 896                 struct fw_ldst_idctxt {
 897                         __be32 physid;
 898                         __be32 msg_ctxtflush;
 899                         __be32 ctxt_data7;
 900                         __be32 ctxt_data6;
 901                         __be32 ctxt_data5;
 902                         __be32 ctxt_data4;
 903                         __be32 ctxt_data3;
 904                         __be32 ctxt_data2;
 905                         __be32 ctxt_data1;
 906                         __be32 ctxt_data0;
 907                 } idctxt;
 908                 struct fw_ldst_mdio {
 909                         __be16 paddr_mmd;
 910                         __be16 raddr;
 911                         __be16 vctl;
 912                         __be16 rval;
 913                 } mdio;
 914                 struct fw_ldst_cim_rq {
 915                         u8 req_first64[8];
 916                         u8 req_second64[8];
 917                         u8 resp_first64[8];
 918                         u8 resp_second64[8];
 919                         __be32 r3[2];
 920                 } cim_rq;
 921                 union fw_ldst_mps {
 922                         struct fw_ldst_mps_rplc {
 923                                 __be16 fid_idx;
 924                                 __be16 rplcpf_pkd;
 925                                 __be32 rplc255_224;
 926                                 __be32 rplc223_192;
 927                                 __be32 rplc191_160;
 928                                 __be32 rplc159_128;
 929                                 __be32 rplc127_96;
 930                                 __be32 rplc95_64;
 931                                 __be32 rplc63_32;
 932                                 __be32 rplc31_0;
 933                         } rplc;
 934                         struct fw_ldst_mps_atrb {
 935                                 __be16 fid_mpsid;
 936                                 __be16 r2[3];
 937                                 __be32 r3[2];
 938                                 __be32 r4;
 939                                 __be32 atrb;
 940                                 __be16 vlan[16];
 941                         } atrb;
 942                 } mps;
 943                 struct fw_ldst_func {
 944                         u8 access_ctl;
 945                         u8 mod_index;
 946                         __be16 ctl_id;
 947                         __be32 offset;
 948                         __be64 data0;
 949                         __be64 data1;
 950                 } func;
 951                 struct fw_ldst_pcie {
 952                         u8 ctrl_to_fn;
 953                         u8 bnum;
 954                         u8 r;
 955                         u8 ext_r;
 956                         u8 select_naccess;
 957                         u8 pcie_fn;
 958                         __be16 nset_pkd;
 959                         __be32 data[12];
 960                 } pcie;
 961                 struct fw_ldst_i2c_deprecated {
 962                         u8 pid_pkd;
 963                         u8 base;
 964                         u8 boffset;
 965                         u8 data;
 966                         __be32 r9;
 967                 } i2c_deprecated;
 968                 struct fw_ldst_i2c {
 969                         u8 pid;
 970                         u8 did;
 971                         u8 boffset;
 972                         u8 blen;
 973                         __be32 r9;
 974                         __u8   data[48];
 975                 } i2c;
 976                 struct fw_ldst_le {
 977                         __be32 index;
 978                         __be32 r9;
 979                         u8 val[33];
 980                         u8 r11[7];
 981                 } le;
 982         } u;
 983 };
 984
 985 #define FW_LDST_CMD_ADDRSPACE_S         0
 986 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 987
 988 #define FW_LDST_CMD_MSG_S       31
 989 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 990
 991 #define FW_LDST_CMD_CTXTFLUSH_S         30
 992 #define FW_LDST_CMD_CTXTFLUSH_V(x)      ((x) << FW_LDST_CMD_CTXTFLUSH_S)
 993 #define FW_LDST_CMD_CTXTFLUSH_F         FW_LDST_CMD_CTXTFLUSH_V(1U)
 994
 995 #define FW_LDST_CMD_PADDR_S     8
 996 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 997
 998 #define FW_LDST_CMD_MMD_S       0
 999 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
1000
1001 #define FW_LDST_CMD_FID_S       15
1002 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
1003
1004 #define FW_LDST_CMD_IDX_S       0
1005 #define FW_LDST_CMD_IDX_V(x)    ((x) << FW_LDST_CMD_IDX_S)
1006
1007 #define FW_LDST_CMD_RPLCPF_S    0
1008 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
1009
1010 #define FW_LDST_CMD_LC_S        4
1011 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
1012 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
1013
1014 #define FW_LDST_CMD_FN_S        0
1015 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
1016
1017 #define FW_LDST_CMD_NACCESS_S           0
1018 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
1019
1020 struct fw_reset_cmd {
1021         __be32 op_to_write;
1022         __be32 retval_len16;
1023         __be32 val;
1024         __be32 halt_pkd;
1025 };
1026
1027 #define FW_RESET_CMD_HALT_S     31
1028 #define FW_RESET_CMD_HALT_M     0x1
1029 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
1030 #define FW_RESET_CMD_HALT_G(x)  \
1031         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
1032 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
1033
1034 enum fw_hellow_cmd {
1035         fw_hello_cmd_stage_os           = 0x0
1036 };
1037
1038 struct fw_hello_cmd {
1039         __be32 op_to_write;
1040         __be32 retval_len16;
1041         __be32 err_to_clearinit;
1042         __be32 fwrev;
1043 };
1044
1045 #define FW_HELLO_CMD_ERR_S      31
1046 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
1047 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
1048
1049 #define FW_HELLO_CMD_INIT_S     30
1050 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
1051 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
1052
1053 #define FW_HELLO_CMD_MASTERDIS_S        29
1054 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
1055
1056 #define FW_HELLO_CMD_MASTERFORCE_S      28
1057 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
1058
1059 #define FW_HELLO_CMD_MBMASTER_S         24
1060 #define FW_HELLO_CMD_MBMASTER_M         0xfU
1061 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
1062 #define FW_HELLO_CMD_MBMASTER_G(x)      \
1063         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
1064
1065 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
1066 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
1067
1068 #define FW_HELLO_CMD_MBASYNCNOT_S       20
1069 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
1070
1071 #define FW_HELLO_CMD_STAGE_S            17
1072 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
1073
1074 #define FW_HELLO_CMD_CLEARINIT_S        16
1075 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
1076 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
1077
1078 struct fw_bye_cmd {
1079         __be32 op_to_write;
1080         __be32 retval_len16;
1081         __be64 r3;
1082 };
1083
1084 struct fw_initialize_cmd {
1085         __be32 op_to_write;
1086         __be32 retval_len16;
1087         __be64 r3;
1088 };
1089
1090 enum fw_caps_config_hm {
1091         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
1092         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
1093         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
1094         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
1095         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
1096         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
1097         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
1098         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
1099         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
1100         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
1101         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
1102         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
1103         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
1104         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
1105         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
1106         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
1107         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
1108         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
1109         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
1110         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
1111         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
1112         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
1113         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
1114         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
1115 };
1116
1117 enum fw_caps_config_nbm {
1118         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
1119         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
1120 };
1121
1122 enum fw_caps_config_link {
1123         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
1124         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
1125         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
1126 };
1127
1128 enum fw_caps_config_switch {
1129         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
1130         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
1131 };
1132
1133 enum fw_caps_config_nic {
1134         FW_CAPS_CONFIG_NIC              = 0x00000001,
1135         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
1136         FW_CAPS_CONFIG_NIC_HASHFILTER   = 0x00000020,
1137 };
1138
1139 enum fw_caps_config_ofld {
1140         FW_CAPS_CONFIG_OFLD             = 0x00000001,
1141 };
1142
1143 enum fw_caps_config_rdma {
1144         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
1145         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
1146 };
1147
1148 enum fw_caps_config_iscsi {
1149         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1150         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1151         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1152         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1153 };
1154
1155 enum fw_caps_config_crypto {
1156         FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
1157         FW_CAPS_CONFIG_TLS_INLINE = 0x00000002,
1158         FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
1159 };
1160
1161 enum fw_caps_config_fcoe {
1162         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
1163         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
1164         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
1165 };
1166
1167 enum fw_memtype_cf {
1168         FW_MEMTYPE_CF_EDC0              = 0x0,
1169         FW_MEMTYPE_CF_EDC1              = 0x1,
1170         FW_MEMTYPE_CF_EXTMEM            = 0x2,
1171         FW_MEMTYPE_CF_FLASH             = 0x4,
1172         FW_MEMTYPE_CF_INTERNAL          = 0x5,
1173         FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1174         FW_MEMTYPE_CF_HMA               = 0x7,
1175 };
1176
1177 struct fw_caps_config_cmd {
1178         __be32 op_to_write;
1179         __be32 cfvalid_to_len16;
1180         __be32 r2;
1181         __be32 hwmbitmap;
1182         __be16 nbmcaps;
1183         __be16 linkcaps;
1184         __be16 switchcaps;
1185         __be16 r3;
1186         __be16 niccaps;
1187         __be16 ofldcaps;
1188         __be16 rdmacaps;
1189         __be16 cryptocaps;
1190         __be16 iscsicaps;
1191         __be16 fcoecaps;
1192         __be32 cfcsum;
1193         __be32 finiver;
1194         __be32 finicsum;
1195 };
1196
1197 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1198 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1199 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1200
1201 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1202 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1203         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1204
1205 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1206 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1207         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1208
1209 /*
1210  * params command mnemonics
1211  */
1212 enum fw_params_mnem {
1213         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1214         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1215         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1216         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1217         FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1218         FW_PARAMS_MNEM_LAST
1219 };
1220
1221 /*
1222  * device parameters
1223  */
1224 enum fw_params_param_dev {
1225         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1226         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1227         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1228                                                  * allocated by the device's
1229                                                  * Lookup Engine
1230                                                  */
1231         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1232         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1233         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1234         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1235         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1236         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1237         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1238         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1239         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1240         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1241         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1242         FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1243         FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1244         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1245         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1246         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1247         FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1248         FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
1249         FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
1250         FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR  = 0x1C,
1251         FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,
1252         FW_PARAMS_PARAM_DEV_MPSBGMAP    = 0x1E,
1253         FW_PARAMS_PARAM_DEV_HMA_SIZE    = 0x20,
1254         FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
1255         FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR    = 0x24,
1256         FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
1257 };
1258
1259 /*
1260  * physical and virtual function parameters
1261  */
1262 enum fw_params_param_pfvf {
1263         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1264         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1265         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1266         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1267         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1268         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1269         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1270         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1271         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1272         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1273         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1274         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1275         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1276         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1277         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1278         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1279         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1280         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1281         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1282         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1283         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1284         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1285         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1286         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1287         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1288         FW_PARAMS_PARAM_PFVF_SRQ_START  = 0x19,
1289         FW_PARAMS_PARAM_PFVF_SRQ_END    = 0x1A,
1290         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1291         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1292         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1293         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1294         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1295         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1296         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1297         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1298         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1299         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1300         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1301         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1302         FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
1303         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1304         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
1305         FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
1306         FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
1307         FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
1308         FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
1309         FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
1310         FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
1311         FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
1312         FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
1313 };
1314
1315 /*
1316  * dma queue parameters
1317  */
1318 enum fw_params_param_dmaq {
1319         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1320         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1321         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1322         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1323         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1324         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1325         FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1326 };
1327
1328 enum fw_params_param_dev_phyfw {
1329         FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1330         FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1331 };
1332
1333 enum fw_params_param_dev_diag {
1334         FW_PARAM_DEV_DIAG_TMP           = 0x00,
1335         FW_PARAM_DEV_DIAG_VDD           = 0x01,
1336         FW_PARAM_DEV_DIAG_MAXTMPTHRESH  = 0x02,
1337 };
1338
1339 enum fw_params_param_dev_fwcache {
1340         FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1341         FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1342 };
1343
1344 #define FW_PARAMS_MNEM_S        24
1345 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1346
1347 #define FW_PARAMS_PARAM_X_S     16
1348 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1349
1350 #define FW_PARAMS_PARAM_Y_S     8
1351 #define FW_PARAMS_PARAM_Y_M     0xffU
1352 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1353 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1354                 FW_PARAMS_PARAM_Y_M)
1355
1356 #define FW_PARAMS_PARAM_Z_S     0
1357 #define FW_PARAMS_PARAM_Z_M     0xffu
1358 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1359 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1360                 FW_PARAMS_PARAM_Z_M)
1361
1362 #define FW_PARAMS_PARAM_XYZ_S           0
1363 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1364
1365 #define FW_PARAMS_PARAM_YZ_S            0
1366 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1367
1368 struct fw_params_cmd {
1369         __be32 op_to_vfn;
1370         __be32 retval_len16;
1371         struct fw_params_param {
1372                 __be32 mnem;
1373                 __be32 val;
1374         } param[7];
1375 };
1376
1377 #define FW_PARAMS_CMD_PFN_S     8
1378 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1379
1380 #define FW_PARAMS_CMD_VFN_S     0
1381 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1382
1383 struct fw_pfvf_cmd {
1384         __be32 op_to_vfn;
1385         __be32 retval_len16;
1386         __be32 niqflint_niq;
1387         __be32 type_to_neq;
1388         __be32 tc_to_nexactf;
1389         __be32 r_caps_to_nethctrl;
1390         __be16 nricq;
1391         __be16 nriqp;
1392         __be32 r4;
1393 };
1394
1395 #define FW_PFVF_CMD_PFN_S       8
1396 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1397
1398 #define FW_PFVF_CMD_VFN_S       0
1399 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1400
1401 #define FW_PFVF_CMD_NIQFLINT_S          20
1402 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1403 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1404 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1405         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1406
1407 #define FW_PFVF_CMD_NIQ_S       0
1408 #define FW_PFVF_CMD_NIQ_M       0xfffff
1409 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1410 #define FW_PFVF_CMD_NIQ_G(x)    \
1411         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1412
1413 #define FW_PFVF_CMD_TYPE_S      31
1414 #define FW_PFVF_CMD_TYPE_M      0x1
1415 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1416 #define FW_PFVF_CMD_TYPE_G(x)   \
1417         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1418 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1419
1420 #define FW_PFVF_CMD_CMASK_S     24
1421 #define FW_PFVF_CMD_CMASK_M     0xf
1422 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1423 #define FW_PFVF_CMD_CMASK_G(x)  \
1424         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1425
1426 #define FW_PFVF_CMD_PMASK_S     20
1427 #define FW_PFVF_CMD_PMASK_M     0xf
1428 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1429 #define FW_PFVF_CMD_PMASK_G(x) \
1430         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1431
1432 #define FW_PFVF_CMD_NEQ_S       0
1433 #define FW_PFVF_CMD_NEQ_M       0xfffff
1434 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1435 #define FW_PFVF_CMD_NEQ_G(x)    \
1436         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1437
1438 #define FW_PFVF_CMD_TC_S        24
1439 #define FW_PFVF_CMD_TC_M        0xff
1440 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1441 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1442
1443 #define FW_PFVF_CMD_NVI_S       16
1444 #define FW_PFVF_CMD_NVI_M       0xff
1445 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1446 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1447
1448 #define FW_PFVF_CMD_NEXACTF_S           0
1449 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1450 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1451 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1452         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1453
1454 #define FW_PFVF_CMD_R_CAPS_S    24
1455 #define FW_PFVF_CMD_R_CAPS_M    0xff
1456 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1457 #define FW_PFVF_CMD_R_CAPS_G(x) \
1458         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1459
1460 #define FW_PFVF_CMD_WX_CAPS_S           16
1461 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1462 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1463 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1464         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1465
1466 #define FW_PFVF_CMD_NETHCTRL_S          0
1467 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1468 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1469 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1470         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1471
1472 enum fw_iq_type {
1473         FW_IQ_TYPE_FL_INT_CAP,
1474         FW_IQ_TYPE_NO_FL_INT_CAP
1475 };
1476
1477 enum fw_iq_iqtype {
1478         FW_IQ_IQTYPE_OTHER,
1479         FW_IQ_IQTYPE_NIC,
1480         FW_IQ_IQTYPE_OFLD,
1481 };
1482
1483 struct fw_iq_cmd {
1484         __be32 op_to_vfn;
1485         __be32 alloc_to_len16;
1486         __be16 physiqid;
1487         __be16 iqid;
1488         __be16 fl0id;
1489         __be16 fl1id;
1490         __be32 type_to_iqandstindex;
1491         __be16 iqdroprss_to_iqesize;
1492         __be16 iqsize;
1493         __be64 iqaddr;
1494         __be32 iqns_to_fl0congen;
1495         __be16 fl0dcaen_to_fl0cidxfthresh;
1496         __be16 fl0size;
1497         __be64 fl0addr;
1498         __be32 fl1cngchmap_to_fl1congen;
1499         __be16 fl1dcaen_to_fl1cidxfthresh;
1500         __be16 fl1size;
1501         __be64 fl1addr;
1502 };
1503
1504 #define FW_IQ_CMD_PFN_S         8
1505 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1506
1507 #define FW_IQ_CMD_VFN_S         0
1508 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1509
1510 #define FW_IQ_CMD_ALLOC_S       31
1511 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1512 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1513
1514 #define FW_IQ_CMD_FREE_S        30
1515 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1516 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1517
1518 #define FW_IQ_CMD_MODIFY_S      29
1519 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1520 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1521
1522 #define FW_IQ_CMD_IQSTART_S     28
1523 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1524 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1525
1526 #define FW_IQ_CMD_IQSTOP_S      27
1527 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1528 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1529
1530 #define FW_IQ_CMD_TYPE_S        29
1531 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1532
1533 #define FW_IQ_CMD_IQASYNCH_S    28
1534 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1535
1536 #define FW_IQ_CMD_VIID_S        16
1537 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1538
1539 #define FW_IQ_CMD_IQANDST_S     15
1540 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1541
1542 #define FW_IQ_CMD_IQANUS_S      14
1543 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1544
1545 #define FW_IQ_CMD_IQANUD_S      12
1546 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1547
1548 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1549 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1550
1551 #define FW_IQ_CMD_IQDROPRSS_S           15
1552 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1553 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1554
1555 #define FW_IQ_CMD_IQGTSMODE_S           14
1556 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1557 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1558
1559 #define FW_IQ_CMD_IQPCIECH_S    12
1560 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1561
1562 #define FW_IQ_CMD_IQDCAEN_S     11
1563 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1564
1565 #define FW_IQ_CMD_IQDCACPU_S    6
1566 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1567
1568 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1569 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1570
1571 #define FW_IQ_CMD_IQO_S         3
1572 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1573 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1574
1575 #define FW_IQ_CMD_IQCPRIO_S     2
1576 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1577
1578 #define FW_IQ_CMD_IQESIZE_S     0
1579 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1580
1581 #define FW_IQ_CMD_IQNS_S        31
1582 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1583
1584 #define FW_IQ_CMD_IQRO_S        30
1585 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1586
1587 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1588 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1589
1590 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1591 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1592 #define FW_IQ_CMD_IQFLINTCONGEN_F       FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1593
1594 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1595 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1596
1597 #define FW_IQ_CMD_IQTYPE_S              24
1598 #define FW_IQ_CMD_IQTYPE_M              0x3
1599 #define FW_IQ_CMD_IQTYPE_V(x)           ((x) << FW_IQ_CMD_IQTYPE_S)
1600 #define FW_IQ_CMD_IQTYPE_G(x)           \
1601         (((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M)
1602
1603 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1604 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1605
1606 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1607 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1608
1609 #define FW_IQ_CMD_FL0DBP_S      14
1610 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1611
1612 #define FW_IQ_CMD_FL0DATANS_S           13
1613 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1614
1615 #define FW_IQ_CMD_FL0DATARO_S           12
1616 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1617 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1618
1619 #define FW_IQ_CMD_FL0CONGCIF_S          11
1620 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1621 #define FW_IQ_CMD_FL0CONGCIF_F          FW_IQ_CMD_FL0CONGCIF_V(1U)
1622
1623 #define FW_IQ_CMD_FL0ONCHIP_S           10
1624 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1625
1626 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1627 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1628
1629 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1630 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1631
1632 #define FW_IQ_CMD_FL0FETCHNS_S          7
1633 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1634
1635 #define FW_IQ_CMD_FL0FETCHRO_S          6
1636 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1637 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1638
1639 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1640 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1641
1642 #define FW_IQ_CMD_FL0CPRIO_S    3
1643 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1644
1645 #define FW_IQ_CMD_FL0PADEN_S    2
1646 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1647 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1648
1649 #define FW_IQ_CMD_FL0PACKEN_S           1
1650 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1651 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1652
1653 #define FW_IQ_CMD_FL0CONGEN_S           0
1654 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1655 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1656
1657 #define FW_IQ_CMD_FL0DCAEN_S    15
1658 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1659
1660 #define FW_IQ_CMD_FL0DCACPU_S           10
1661 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1662
1663 #define FW_IQ_CMD_FL0FBMIN_S    7
1664 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1665
1666 #define FW_IQ_CMD_FL0FBMAX_S    4
1667 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1668
1669 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1670 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1671 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1672
1673 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1674 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1675
1676 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1677 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1678
1679 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1680 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1681
1682 #define FW_IQ_CMD_FL1DBP_S      14
1683 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1684
1685 #define FW_IQ_CMD_FL1DATANS_S           13
1686 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1687
1688 #define FW_IQ_CMD_FL1DATARO_S           12
1689 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1690
1691 #define FW_IQ_CMD_FL1CONGCIF_S          11
1692 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1693
1694 #define FW_IQ_CMD_FL1ONCHIP_S           10
1695 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1696
1697 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1698 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1699
1700 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1701 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1702
1703 #define FW_IQ_CMD_FL1FETCHNS_S          7
1704 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1705
1706 #define FW_IQ_CMD_FL1FETCHRO_S          6
1707 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1708
1709 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1710 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1711
1712 #define FW_IQ_CMD_FL1CPRIO_S    3
1713 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1714
1715 #define FW_IQ_CMD_FL1PADEN_S    2
1716 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1717 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1718
1719 #define FW_IQ_CMD_FL1PACKEN_S           1
1720 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1721 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1722
1723 #define FW_IQ_CMD_FL1CONGEN_S           0
1724 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1725 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1726
1727 #define FW_IQ_CMD_FL1DCAEN_S    15
1728 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1729
1730 #define FW_IQ_CMD_FL1DCACPU_S           10
1731 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1732
1733 #define FW_IQ_CMD_FL1FBMIN_S    7
1734 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1735
1736 #define FW_IQ_CMD_FL1FBMAX_S    4
1737 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1738
1739 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1740 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1741 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1742
1743 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1744 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1745
1746 struct fw_eq_eth_cmd {
1747         __be32 op_to_vfn;
1748         __be32 alloc_to_len16;
1749         __be32 eqid_pkd;
1750         __be32 physeqid_pkd;
1751         __be32 fetchszm_to_iqid;
1752         __be32 dcaen_to_eqsize;
1753         __be64 eqaddr;
1754         __be32 viid_pkd;
1755         __be32 r8_lo;
1756         __be64 r9;
1757 };
1758
1759 #define FW_EQ_ETH_CMD_PFN_S     8
1760 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1761
1762 #define FW_EQ_ETH_CMD_VFN_S     0
1763 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1764
1765 #define FW_EQ_ETH_CMD_ALLOC_S           31
1766 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1767 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1768
1769 #define FW_EQ_ETH_CMD_FREE_S    30
1770 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1771 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1772
1773 #define FW_EQ_ETH_CMD_MODIFY_S          29
1774 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1775 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1776
1777 #define FW_EQ_ETH_CMD_EQSTART_S         28
1778 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1779 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1780
1781 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1782 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1783 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1784
1785 #define FW_EQ_ETH_CMD_EQID_S    0
1786 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1787 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1788 #define FW_EQ_ETH_CMD_EQID_G(x) \
1789         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1790
1791 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1792 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1793 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1794 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1795         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1796
1797 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1798 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1799 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1800
1801 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1802 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1803
1804 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1805 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1806
1807 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1808 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1809
1810 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1811 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1812 #define FW_EQ_ETH_CMD_FETCHRO_F         FW_EQ_ETH_CMD_FETCHRO_V(1U)
1813
1814 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1815 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1816
1817 #define FW_EQ_ETH_CMD_CPRIO_S           19
1818 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1819
1820 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1821 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1822
1823 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1824 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1825
1826 #define FW_EQ_ETH_CMD_IQID_S    0
1827 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1828
1829 #define FW_EQ_ETH_CMD_DCAEN_S           31
1830 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1831
1832 #define FW_EQ_ETH_CMD_DCACPU_S          26
1833 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1834
1835 #define FW_EQ_ETH_CMD_FBMIN_S           23
1836 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1837
1838 #define FW_EQ_ETH_CMD_FBMAX_S           20
1839 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1840
1841 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1842 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1843
1844 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1845 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1846
1847 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1848 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1849
1850 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1851 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1852 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1853
1854 #define FW_EQ_ETH_CMD_VIID_S    16
1855 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1856
1857 struct fw_eq_ctrl_cmd {
1858         __be32 op_to_vfn;
1859         __be32 alloc_to_len16;
1860         __be32 cmpliqid_eqid;
1861         __be32 physeqid_pkd;
1862         __be32 fetchszm_to_iqid;
1863         __be32 dcaen_to_eqsize;
1864         __be64 eqaddr;
1865 };
1866
1867 #define FW_EQ_CTRL_CMD_PFN_S    8
1868 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1869
1870 #define FW_EQ_CTRL_CMD_VFN_S    0
1871 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1872
1873 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1874 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1875 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1876
1877 #define FW_EQ_CTRL_CMD_FREE_S           30
1878 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1879 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1880
1881 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1882 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1883 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1884
1885 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1886 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1887 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1888
1889 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1890 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1891 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1892
1893 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1894 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1895
1896 #define FW_EQ_CTRL_CMD_EQID_S           0
1897 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1898 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1899 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1900         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1901
1902 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1903 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1904 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1905         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1906
1907 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1908 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1909 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1910
1911 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1912 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1913 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1914
1915 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1916 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1917 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1918
1919 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1920 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1921 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1922
1923 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1924 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1925 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1926
1927 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1928 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1929
1930 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1931 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1932
1933 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1934 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1935
1936 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1937 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1938
1939 #define FW_EQ_CTRL_CMD_IQID_S           0
1940 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1941
1942 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1943 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1944
1945 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1946 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1947
1948 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1949 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1950
1951 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1952 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1953
1954 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1955 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1956         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1957
1958 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1959 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1960
1961 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1962 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1963
1964 struct fw_eq_ofld_cmd {
1965         __be32 op_to_vfn;
1966         __be32 alloc_to_len16;
1967         __be32 eqid_pkd;
1968         __be32 physeqid_pkd;
1969         __be32 fetchszm_to_iqid;
1970         __be32 dcaen_to_eqsize;
1971         __be64 eqaddr;
1972 };
1973
1974 #define FW_EQ_OFLD_CMD_PFN_S    8
1975 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1976
1977 #define FW_EQ_OFLD_CMD_VFN_S    0
1978 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1979
1980 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1981 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1982 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1983
1984 #define FW_EQ_OFLD_CMD_FREE_S           30
1985 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1986 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1987
1988 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1989 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1990 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1991
1992 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1993 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1994 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1995
1996 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1997 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1998 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1999
2000 #define FW_EQ_OFLD_CMD_EQID_S           0
2001 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
2002 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
2003 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
2004         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
2005
2006 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
2007 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
2008 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
2009         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
2010
2011 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
2012 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
2013
2014 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
2015 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
2016
2017 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
2018 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
2019
2020 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
2021 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
2022
2023 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
2024 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
2025 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
2026
2027 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
2028 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
2029
2030 #define FW_EQ_OFLD_CMD_CPRIO_S          19
2031 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
2032
2033 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
2034 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
2035
2036 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
2037 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
2038
2039 #define FW_EQ_OFLD_CMD_IQID_S           0
2040 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
2041
2042 #define FW_EQ_OFLD_CMD_DCAEN_S          31
2043 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
2044
2045 #define FW_EQ_OFLD_CMD_DCACPU_S         26
2046 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
2047
2048 #define FW_EQ_OFLD_CMD_FBMIN_S          23
2049 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
2050
2051 #define FW_EQ_OFLD_CMD_FBMAX_S          20
2052 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
2053
2054 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
2055 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
2056         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
2057
2058 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
2059 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
2060
2061 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
2062 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
2063
2064 /*
2065  * Macros for VIID parsing:
2066  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
2067  */
2068
2069 #define FW_VIID_PFN_S           8
2070 #define FW_VIID_PFN_M           0x7
2071 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
2072
2073 #define FW_VIID_VIVLD_S         7
2074 #define FW_VIID_VIVLD_M         0x1
2075 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
2076
2077 #define FW_VIID_VIN_S           0
2078 #define FW_VIID_VIN_M           0x7F
2079 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
2080
2081 struct fw_vi_cmd {
2082         __be32 op_to_vfn;
2083         __be32 alloc_to_len16;
2084         __be16 type_viid;
2085         u8 mac[6];
2086         u8 portid_pkd;
2087         u8 nmac;
2088         u8 nmac0[6];
2089         __be16 rsssize_pkd;
2090         u8 nmac1[6];
2091         __be16 idsiiq_pkd;
2092         u8 nmac2[6];
2093         __be16 idseiq_pkd;
2094         u8 nmac3[6];
2095         __be64 r9;
2096         __be64 r10;
2097 };
2098
2099 #define FW_VI_CMD_PFN_S         8
2100 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
2101
2102 #define FW_VI_CMD_VFN_S         0
2103 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
2104
2105 #define FW_VI_CMD_ALLOC_S       31
2106 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
2107 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
2108
2109 #define FW_VI_CMD_FREE_S        30
2110 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
2111 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
2112
2113 #define FW_VI_CMD_VFVLD_S       24
2114 #define FW_VI_CMD_VFVLD_M       0x1
2115 #define FW_VI_CMD_VFVLD_V(x)    ((x) << FW_VI_CMD_VFVLD_S)
2116 #define FW_VI_CMD_VFVLD_G(x)    \
2117         (((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M)
2118 #define FW_VI_CMD_VFVLD_F       FW_VI_CMD_VFVLD_V(1U)
2119
2120 #define FW_VI_CMD_VIN_S         16
2121 #define FW_VI_CMD_VIN_M         0xff
2122 #define FW_VI_CMD_VIN_V(x)      ((x) << FW_VI_CMD_VIN_S)
2123 #define FW_VI_CMD_VIN_G(x)      \
2124         (((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M)
2125
2126 #define FW_VI_CMD_VIID_S        0
2127 #define FW_VI_CMD_VIID_M        0xfff
2128 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
2129 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
2130
2131 #define FW_VI_CMD_PORTID_S      4
2132 #define FW_VI_CMD_PORTID_M      0xf
2133 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
2134 #define FW_VI_CMD_PORTID_G(x)   \
2135         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
2136
2137 #define FW_VI_CMD_RSSSIZE_S     0
2138 #define FW_VI_CMD_RSSSIZE_M     0x7ff
2139 #define FW_VI_CMD_RSSSIZE_G(x)  \
2140         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
2141
2142 /* Special VI_MAC command index ids */
2143 #define FW_VI_MAC_ADD_MAC               0x3FF
2144 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
2145 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
2146 #define FW_VI_MAC_ID_BASED_FREE         0x3FC
2147 #define FW_CLS_TCAM_NUM_ENTRIES         336
2148
2149 enum fw_vi_mac_smac {
2150         FW_VI_MAC_MPS_TCAM_ENTRY,
2151         FW_VI_MAC_MPS_TCAM_ONLY,
2152         FW_VI_MAC_SMT_ONLY,
2153         FW_VI_MAC_SMT_AND_MPSTCAM
2154 };
2155
2156 enum fw_vi_mac_result {
2157         FW_VI_MAC_R_SUCCESS,
2158         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
2159         FW_VI_MAC_R_SMAC_FAIL,
2160         FW_VI_MAC_R_F_ACL_CHECK
2161 };
2162
2163 enum fw_vi_mac_entry_types {
2164         FW_VI_MAC_TYPE_EXACTMAC,
2165         FW_VI_MAC_TYPE_HASHVEC,
2166         FW_VI_MAC_TYPE_RAW,
2167         FW_VI_MAC_TYPE_EXACTMAC_VNI,
2168 };
2169
2170 struct fw_vi_mac_cmd {
2171         __be32 op_to_viid;
2172         __be32 freemacs_to_len16;
2173         union fw_vi_mac {
2174                 struct fw_vi_mac_exact {
2175                         __be16 valid_to_idx;
2176                         u8 macaddr[6];
2177                 } exact[7];
2178                 struct fw_vi_mac_hash {
2179                         __be64 hashvec;
2180                 } hash;
2181                 struct fw_vi_mac_raw {
2182                         __be32 raw_idx_pkd;
2183                         __be32 data0_pkd;
2184                         __be32 data1[2];
2185                         __be64 data0m_pkd;
2186                         __be32 data1m[2];
2187                 } raw;
2188                 struct fw_vi_mac_vni {
2189                         __be16 valid_to_idx;
2190                         __u8 macaddr[6];
2191                         __be16 r7;
2192                         __u8 macaddr_mask[6];
2193                         __be32 lookup_type_to_vni;
2194                         __be32 vni_mask_pkd;
2195                 } exact_vni[2];
2196         } u;
2197 };
2198
2199 #define FW_VI_MAC_CMD_SMTID_S           12
2200 #define FW_VI_MAC_CMD_SMTID_M           0xff
2201 #define FW_VI_MAC_CMD_SMTID_V(x)        ((x) << FW_VI_MAC_CMD_SMTID_S)
2202 #define FW_VI_MAC_CMD_SMTID_G(x)        \
2203         (((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M)
2204
2205 #define FW_VI_MAC_CMD_VIID_S    0
2206 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2207
2208 #define FW_VI_MAC_CMD_FREEMACS_S        31
2209 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2210
2211 #define FW_VI_MAC_CMD_ENTRY_TYPE_S      23
2212 #define FW_VI_MAC_CMD_ENTRY_TYPE_M      0x7
2213 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x)   ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)
2214 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x)   \
2215         (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M)
2216
2217 #define FW_VI_MAC_CMD_HASHVECEN_S       23
2218 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2219 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
2220
2221 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
2222 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2223
2224 #define FW_VI_MAC_CMD_VALID_S           15
2225 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
2226 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
2227
2228 #define FW_VI_MAC_CMD_PRIO_S    12
2229 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2230
2231 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
2232 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
2233 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2234 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
2235         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2236
2237 #define FW_VI_MAC_CMD_IDX_S     0
2238 #define FW_VI_MAC_CMD_IDX_M     0x3ff
2239 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
2240 #define FW_VI_MAC_CMD_IDX_G(x)  \
2241         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2242
2243 #define FW_VI_MAC_CMD_RAW_IDX_S         16
2244 #define FW_VI_MAC_CMD_RAW_IDX_M         0xffff
2245 #define FW_VI_MAC_CMD_RAW_IDX_V(x)      ((x) << FW_VI_MAC_CMD_RAW_IDX_S)
2246 #define FW_VI_MAC_CMD_RAW_IDX_G(x)      \
2247         (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M)
2248
2249 #define FW_VI_MAC_CMD_LOOKUP_TYPE_S     31
2250 #define FW_VI_MAC_CMD_LOOKUP_TYPE_M     0x1
2251 #define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x)  ((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S)
2252 #define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x)  \
2253         (((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M)
2254 #define FW_VI_MAC_CMD_LOOKUP_TYPE_F     FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U)
2255
2256 #define FW_VI_MAC_CMD_DIP_HIT_S         30
2257 #define FW_VI_MAC_CMD_DIP_HIT_M         0x1
2258 #define FW_VI_MAC_CMD_DIP_HIT_V(x)      ((x) << FW_VI_MAC_CMD_DIP_HIT_S)
2259 #define FW_VI_MAC_CMD_DIP_HIT_G(x)      \
2260         (((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M)
2261 #define FW_VI_MAC_CMD_DIP_HIT_F         FW_VI_MAC_CMD_DIP_HIT_V(1U)
2262
2263 #define FW_VI_MAC_CMD_VNI_S             0
2264 #define FW_VI_MAC_CMD_VNI_M             0xffffff
2265 #define FW_VI_MAC_CMD_VNI_V(x)          ((x) << FW_VI_MAC_CMD_VNI_S)
2266 #define FW_VI_MAC_CMD_VNI_G(x)          \
2267         (((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M)
2268
2269 #define FW_VI_MAC_CMD_VNI_MASK_S        0
2270 #define FW_VI_MAC_CMD_VNI_MASK_M        0xffffff
2271 #define FW_VI_MAC_CMD_VNI_MASK_V(x)     ((x) << FW_VI_MAC_CMD_VNI_MASK_S)
2272 #define FW_VI_MAC_CMD_VNI_MASK_G(x)     \
2273         (((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M)
2274
2275 #define FW_RXMODE_MTU_NO_CHG    65535
2276
2277 struct fw_vi_rxmode_cmd {
2278         __be32 op_to_viid;
2279         __be32 retval_len16;
2280         __be32 mtu_to_vlanexen;
2281         __be32 r4_lo;
2282 };
2283
2284 #define FW_VI_RXMODE_CMD_VIID_S         0
2285 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
2286
2287 #define FW_VI_RXMODE_CMD_MTU_S          16
2288 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
2289 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
2290
2291 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
2292 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
2293 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2294
2295 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
2296 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
2297 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
2298         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2299
2300 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
2301 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
2302 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
2303         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2304
2305 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
2306 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
2307 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2308
2309 struct fw_vi_enable_cmd {
2310         __be32 op_to_viid;
2311         __be32 ien_to_len16;
2312         __be16 blinkdur;
2313         __be16 r3;
2314         __be32 r4;
2315 };
2316
2317 #define FW_VI_ENABLE_CMD_VIID_S         0
2318 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2319
2320 #define FW_VI_ENABLE_CMD_IEN_S          31
2321 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2322
2323 #define FW_VI_ENABLE_CMD_EEN_S          30
2324 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2325
2326 #define FW_VI_ENABLE_CMD_LED_S          29
2327 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2328 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2329
2330 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2331 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2332
2333 /* VI VF stats offset definitions */
2334 #define VI_VF_NUM_STATS 16
2335 enum fw_vi_stats_vf_index {
2336         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2337         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2338         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2339         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2340         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2341         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2342         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2343         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2344         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2345         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2346         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2347         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2348         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2349         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2350         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2351         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2352 };
2353
2354 /* VI PF stats offset definitions */
2355 #define VI_PF_NUM_STATS 17
2356 enum fw_vi_stats_pf_index {
2357         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2358         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2359         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2360         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2361         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2362         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2363         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2364         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2365         FW_VI_PF_STAT_RX_BYTES_IX,
2366         FW_VI_PF_STAT_RX_FRAMES_IX,
2367         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2368         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2369         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2370         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2371         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2372         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2373         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2374 };
2375
2376 struct fw_vi_stats_cmd {
2377         __be32 op_to_viid;
2378         __be32 retval_len16;
2379         union fw_vi_stats {
2380                 struct fw_vi_stats_ctl {
2381                         __be16 nstats_ix;
2382                         __be16 r6;
2383                         __be32 r7;
2384                         __be64 stat0;
2385                         __be64 stat1;
2386                         __be64 stat2;
2387                         __be64 stat3;
2388                         __be64 stat4;
2389                         __be64 stat5;
2390                 } ctl;
2391                 struct fw_vi_stats_pf {
2392                         __be64 tx_bcast_bytes;
2393                         __be64 tx_bcast_frames;
2394                         __be64 tx_mcast_bytes;
2395                         __be64 tx_mcast_frames;
2396                         __be64 tx_ucast_bytes;
2397                         __be64 tx_ucast_frames;
2398                         __be64 tx_offload_bytes;
2399                         __be64 tx_offload_frames;
2400                         __be64 rx_pf_bytes;
2401                         __be64 rx_pf_frames;
2402                         __be64 rx_bcast_bytes;
2403                         __be64 rx_bcast_frames;
2404                         __be64 rx_mcast_bytes;
2405                         __be64 rx_mcast_frames;
2406                         __be64 rx_ucast_bytes;
2407                         __be64 rx_ucast_frames;
2408                         __be64 rx_err_frames;
2409                 } pf;
2410                 struct fw_vi_stats_vf {
2411                         __be64 tx_bcast_bytes;
2412                         __be64 tx_bcast_frames;
2413                         __be64 tx_mcast_bytes;
2414                         __be64 tx_mcast_frames;
2415                         __be64 tx_ucast_bytes;
2416                         __be64 tx_ucast_frames;
2417                         __be64 tx_drop_frames;
2418                         __be64 tx_offload_bytes;
2419                         __be64 tx_offload_frames;
2420                         __be64 rx_bcast_bytes;
2421                         __be64 rx_bcast_frames;
2422                         __be64 rx_mcast_bytes;
2423                         __be64 rx_mcast_frames;
2424                         __be64 rx_ucast_bytes;
2425                         __be64 rx_ucast_frames;
2426                         __be64 rx_err_frames;
2427                 } vf;
2428         } u;
2429 };
2430
2431 #define FW_VI_STATS_CMD_VIID_S          0
2432 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2433
2434 #define FW_VI_STATS_CMD_NSTATS_S        12
2435 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2436
2437 #define FW_VI_STATS_CMD_IX_S    0
2438 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2439
2440 struct fw_acl_mac_cmd {
2441         __be32 op_to_vfn;
2442         __be32 en_to_len16;
2443         u8 nmac;
2444         u8 r3[7];
2445         __be16 r4;
2446         u8 macaddr0[6];
2447         __be16 r5;
2448         u8 macaddr1[6];
2449         __be16 r6;
2450         u8 macaddr2[6];
2451         __be16 r7;
2452         u8 macaddr3[6];
2453 };
2454
2455 #define FW_ACL_MAC_CMD_PFN_S    8
2456 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2457
2458 #define FW_ACL_MAC_CMD_VFN_S    0
2459 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2460
2461 #define FW_ACL_MAC_CMD_EN_S     31
2462 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2463
2464 struct fw_acl_vlan_cmd {
2465         __be32 op_to_vfn;
2466         __be32 en_to_len16;
2467         u8 nvlan;
2468         u8 dropnovlan_fm;
2469         u8 r3_lo[6];
2470         __be16 vlanid[16];
2471 };
2472
2473 #define FW_ACL_VLAN_CMD_PFN_S           8
2474 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2475
2476 #define FW_ACL_VLAN_CMD_VFN_S           0
2477 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2478
2479 #define FW_ACL_VLAN_CMD_EN_S            31
2480 #define FW_ACL_VLAN_CMD_EN_M            0x1
2481 #define FW_ACL_VLAN_CMD_EN_V(x)         ((x) << FW_ACL_VLAN_CMD_EN_S)
2482 #define FW_ACL_VLAN_CMD_EN_G(x)         \
2483         (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
2484 #define FW_ACL_VLAN_CMD_EN_F            FW_ACL_VLAN_CMD_EN_V(1U)
2485
2486 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2487 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2488 #define FW_ACL_VLAN_CMD_DROPNOVLAN_F    FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U)
2489
2490 #define FW_ACL_VLAN_CMD_FM_S            6
2491 #define FW_ACL_VLAN_CMD_FM_M            0x1
2492 #define FW_ACL_VLAN_CMD_FM_V(x)         ((x) << FW_ACL_VLAN_CMD_FM_S)
2493 #define FW_ACL_VLAN_CMD_FM_G(x)         \
2494         (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M)
2495 #define FW_ACL_VLAN_CMD_FM_F            FW_ACL_VLAN_CMD_FM_V(1U)
2496
2497 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
2498 enum fw_port_cap {
2499         FW_PORT_CAP_SPEED_100M          = 0x0001,
2500         FW_PORT_CAP_SPEED_1G            = 0x0002,
2501         FW_PORT_CAP_SPEED_25G           = 0x0004,
2502         FW_PORT_CAP_SPEED_10G           = 0x0008,
2503         FW_PORT_CAP_SPEED_40G           = 0x0010,
2504         FW_PORT_CAP_SPEED_100G          = 0x0020,
2505         FW_PORT_CAP_FC_RX               = 0x0040,
2506         FW_PORT_CAP_FC_TX               = 0x0080,
2507         FW_PORT_CAP_ANEG                = 0x0100,
2508         FW_PORT_CAP_MDIAUTO             = 0x0200,
2509         FW_PORT_CAP_MDISTRAIGHT         = 0x0400,
2510         FW_PORT_CAP_FEC_RS              = 0x0800,
2511         FW_PORT_CAP_FEC_BASER_RS        = 0x1000,
2512         FW_PORT_CAP_FORCE_PAUSE         = 0x2000,
2513         FW_PORT_CAP_802_3_PAUSE         = 0x4000,
2514         FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,
2515 };
2516
2517 #define FW_PORT_CAP_SPEED_S     0
2518 #define FW_PORT_CAP_SPEED_M     0x3f
2519 #define FW_PORT_CAP_SPEED_V(x)  ((x) << FW_PORT_CAP_SPEED_S)
2520 #define FW_PORT_CAP_SPEED_G(x) \
2521         (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2522
2523 enum fw_port_mdi {
2524         FW_PORT_CAP_MDI_UNCHANGED,
2525         FW_PORT_CAP_MDI_AUTO,
2526         FW_PORT_CAP_MDI_F_STRAIGHT,
2527         FW_PORT_CAP_MDI_F_CROSSOVER
2528 };
2529
2530 #define FW_PORT_CAP_MDI_S 9
2531 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2532
2533 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
2534 #define FW_PORT_CAP32_SPEED_100M        0x00000001UL
2535 #define FW_PORT_CAP32_SPEED_1G          0x00000002UL
2536 #define FW_PORT_CAP32_SPEED_10G         0x00000004UL
2537 #define FW_PORT_CAP32_SPEED_25G         0x00000008UL
2538 #define FW_PORT_CAP32_SPEED_40G         0x00000010UL
2539 #define FW_PORT_CAP32_SPEED_50G         0x00000020UL
2540 #define FW_PORT_CAP32_SPEED_100G        0x00000040UL
2541 #define FW_PORT_CAP32_SPEED_200G        0x00000080UL
2542 #define FW_PORT_CAP32_SPEED_400G        0x00000100UL
2543 #define FW_PORT_CAP32_SPEED_RESERVED1   0x00000200UL
2544 #define FW_PORT_CAP32_SPEED_RESERVED2   0x00000400UL
2545 #define FW_PORT_CAP32_SPEED_RESERVED3   0x00000800UL
2546 #define FW_PORT_CAP32_RESERVED1         0x0000f000UL
2547 #define FW_PORT_CAP32_FC_RX             0x00010000UL
2548 #define FW_PORT_CAP32_FC_TX             0x00020000UL
2549 #define FW_PORT_CAP32_802_3_PAUSE       0x00040000UL
2550 #define FW_PORT_CAP32_802_3_ASM_DIR     0x00080000UL
2551 #define FW_PORT_CAP32_ANEG              0x00100000UL
2552 #define FW_PORT_CAP32_MDIAUTO           0x00200000UL
2553 #define FW_PORT_CAP32_MDISTRAIGHT       0x00400000UL
2554 #define FW_PORT_CAP32_FEC_RS            0x00800000UL
2555 #define FW_PORT_CAP32_FEC_BASER_RS      0x01000000UL
2556 #define FW_PORT_CAP32_FEC_RESERVED1     0x02000000UL
2557 #define FW_PORT_CAP32_FEC_RESERVED2     0x04000000UL
2558 #define FW_PORT_CAP32_FEC_RESERVED3     0x08000000UL
2559 #define FW_PORT_CAP32_FORCE_PAUSE       0x10000000UL
2560 #define FW_PORT_CAP32_RESERVED2         0xe0000000UL
2561
2562 #define FW_PORT_CAP32_SPEED_S   0
2563 #define FW_PORT_CAP32_SPEED_M   0xfff
2564 #define FW_PORT_CAP32_SPEED_V(x)        ((x) << FW_PORT_CAP32_SPEED_S)
2565 #define FW_PORT_CAP32_SPEED_G(x) \
2566         (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)
2567
2568 #define FW_PORT_CAP32_FC_S      16
2569 #define FW_PORT_CAP32_FC_M      0x3
2570 #define FW_PORT_CAP32_FC_V(x)   ((x) << FW_PORT_CAP32_FC_S)
2571 #define FW_PORT_CAP32_FC_G(x) \
2572         (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)
2573
2574 #define FW_PORT_CAP32_802_3_S   18
2575 #define FW_PORT_CAP32_802_3_M   0x3
2576 #define FW_PORT_CAP32_802_3_V(x)        ((x) << FW_PORT_CAP32_802_3_S)
2577 #define FW_PORT_CAP32_802_3_G(x) \
2578         (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)
2579
2580 #define FW_PORT_CAP32_ANEG_S    20
2581 #define FW_PORT_CAP32_ANEG_M    0x1
2582 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S)
2583 #define FW_PORT_CAP32_ANEG_G(x) \
2584         (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)
2585
2586 enum fw_port_mdi32 {
2587         FW_PORT_CAP32_MDI_UNCHANGED,
2588         FW_PORT_CAP32_MDI_AUTO,
2589         FW_PORT_CAP32_MDI_F_STRAIGHT,
2590         FW_PORT_CAP32_MDI_F_CROSSOVER
2591 };
2592
2593 #define FW_PORT_CAP32_MDI_S 21
2594 #define FW_PORT_CAP32_MDI_M 3
2595 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)
2596 #define FW_PORT_CAP32_MDI_G(x) \
2597         (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)
2598
2599 #define FW_PORT_CAP32_FEC_S     23
2600 #define FW_PORT_CAP32_FEC_M     0x1f
2601 #define FW_PORT_CAP32_FEC_V(x)  ((x) << FW_PORT_CAP32_FEC_S)
2602 #define FW_PORT_CAP32_FEC_G(x) \
2603         (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)
2604
2605 /* macros to isolate various 32-bit Port Capabilities sub-fields */
2606 #define CAP32_SPEED(__cap32) \
2607         (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)
2608
2609 #define CAP32_FEC(__cap32) \
2610         (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)
2611
2612 enum fw_port_action {
2613         FW_PORT_ACTION_L1_CFG           = 0x0001,
2614         FW_PORT_ACTION_L2_CFG           = 0x0002,
2615         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2616         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2617         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2618         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2619         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2620         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2621         FW_PORT_ACTION_L1_CFG32         = 0x0009,
2622         FW_PORT_ACTION_GET_PORT_INFO32  = 0x000a,
2623         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2624         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2625         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2626         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2627         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2628         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2629         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2630         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2631         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2632         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2633         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2634         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2635         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2636         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2637         FW_PORT_ACTION_AN_RESET         = 0x0045
2638 };
2639
2640 enum fw_port_l2cfg_ctlbf {
2641         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2642         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2643         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2644         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2645         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2646         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2647 };
2648
2649 enum fw_port_dcb_versions {
2650         FW_PORT_DCB_VER_UNKNOWN,
2651         FW_PORT_DCB_VER_CEE1D0,
2652         FW_PORT_DCB_VER_CEE1D01,
2653         FW_PORT_DCB_VER_IEEE,
2654         FW_PORT_DCB_VER_AUTO = 7
2655 };
2656
2657 enum fw_port_dcb_cfg {
2658         FW_PORT_DCB_CFG_PG      = 0x01,
2659         FW_PORT_DCB_CFG_PFC     = 0x02,
2660         FW_PORT_DCB_CFG_APPL    = 0x04
2661 };
2662
2663 enum fw_port_dcb_cfg_rc {
2664         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2665         FW_PORT_DCB_CFG_ERROR   = 0x1
2666 };
2667
2668 enum fw_port_dcb_type {
2669         FW_PORT_DCB_TYPE_PGID           = 0x00,
2670         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2671         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2672         FW_PORT_DCB_TYPE_PFC            = 0x03,
2673         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2674         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2675 };
2676
2677 enum fw_port_dcb_feature_state {
2678         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2679         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2680         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2681         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2682 };
2683
2684 struct fw_port_cmd {
2685         __be32 op_to_portid;
2686         __be32 action_to_len16;
2687         union fw_port {
2688                 struct fw_port_l1cfg {
2689                         __be32 rcap;
2690                         __be32 r;
2691                 } l1cfg;
2692                 struct fw_port_l2cfg {
2693                         __u8   ctlbf;
2694                         __u8   ovlan3_to_ivlan0;
2695                         __be16 ivlantype;
2696                         __be16 txipg_force_pinfo;
2697                         __be16 mtu;
2698                         __be16 ovlan0mask;
2699                         __be16 ovlan0type;
2700                         __be16 ovlan1mask;
2701                         __be16 ovlan1type;
2702                         __be16 ovlan2mask;
2703                         __be16 ovlan2type;
2704                         __be16 ovlan3mask;
2705                         __be16 ovlan3type;
2706                 } l2cfg;
2707                 struct fw_port_info {
2708                         __be32 lstatus_to_modtype;
2709                         __be16 pcap;
2710                         __be16 acap;
2711                         __be16 mtu;
2712                         __u8   cbllen;
2713                         __u8   auxlinfo;
2714                         __u8   dcbxdis_pkd;
2715                         __u8   r8_lo;
2716                         __be16 lpacap;
2717                         __be64 r9;
2718                 } info;
2719                 struct fw_port_diags {
2720                         __u8   diagop;
2721                         __u8   r[3];
2722                         __be32 diagval;
2723                 } diags;
2724                 union fw_port_dcb {
2725                         struct fw_port_dcb_pgid {
2726                                 __u8   type;
2727                                 __u8   apply_pkd;
2728                                 __u8   r10_lo[2];
2729                                 __be32 pgid;
2730                                 __be64 r11;
2731                         } pgid;
2732                         struct fw_port_dcb_pgrate {
2733                                 __u8   type;
2734                                 __u8   apply_pkd;
2735                                 __u8   r10_lo[5];
2736                                 __u8   num_tcs_supported;
2737                                 __u8   pgrate[8];
2738                                 __u8   tsa[8];
2739                         } pgrate;
2740                         struct fw_port_dcb_priorate {
2741                                 __u8   type;
2742                                 __u8   apply_pkd;
2743                                 __u8   r10_lo[6];
2744                                 __u8   strict_priorate[8];
2745                         } priorate;
2746                         struct fw_port_dcb_pfc {
2747                                 __u8   type;
2748                                 __u8   pfcen;
2749                                 __u8   r10[5];
2750                                 __u8   max_pfc_tcs;
2751                                 __be64 r11;
2752                         } pfc;
2753                         struct fw_port_app_priority {
2754                                 __u8   type;
2755                                 __u8   r10[2];
2756                                 __u8   idx;
2757                                 __u8   user_prio_map;
2758                                 __u8   sel_field;
2759                                 __be16 protocolid;
2760                                 __be64 r12;
2761                         } app_priority;
2762                         struct fw_port_dcb_control {
2763                                 __u8   type;
2764                                 __u8   all_syncd_pkd;
2765                                 __be16 dcb_version_to_app_state;
2766                                 __be32 r11;
2767                                 __be64 r12;
2768                         } control;
2769                 } dcb;
2770                 struct fw_port_l1cfg32 {
2771                         __be32 rcap32;
2772                         __be32 r;
2773                 } l1cfg32;
2774                 struct fw_port_info32 {
2775                         __be32 lstatus32_to_cbllen32;
2776                         __be32 auxlinfo32_mtu32;
2777                         __be32 linkattr32;
2778                         __be32 pcaps32;
2779                         __be32 acaps32;
2780                         __be32 lpacaps32;
2781                 } info32;
2782         } u;
2783 };
2784
2785 #define FW_PORT_CMD_READ_S      22
2786 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2787 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2788
2789 #define FW_PORT_CMD_PORTID_S    0
2790 #define FW_PORT_CMD_PORTID_M    0xf
2791 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2792 #define FW_PORT_CMD_PORTID_G(x) \
2793         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2794
2795 #define FW_PORT_CMD_ACTION_S    16
2796 #define FW_PORT_CMD_ACTION_M    0xffff
2797 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2798 #define FW_PORT_CMD_ACTION_G(x) \
2799         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2800
2801 #define FW_PORT_CMD_OVLAN3_S    7
2802 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2803
2804 #define FW_PORT_CMD_OVLAN2_S    6
2805 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2806
2807 #define FW_PORT_CMD_OVLAN1_S    5
2808 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2809
2810 #define FW_PORT_CMD_OVLAN0_S    4
2811 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2812
2813 #define FW_PORT_CMD_IVLAN0_S    3
2814 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2815
2816 #define FW_PORT_CMD_TXIPG_S     3
2817 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2818
2819 #define FW_PORT_CMD_LSTATUS_S           31
2820 #define FW_PORT_CMD_LSTATUS_M           0x1
2821 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2822 #define FW_PORT_CMD_LSTATUS_G(x)        \
2823         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2824 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2825
2826 #define FW_PORT_CMD_LSPEED_S    24
2827 #define FW_PORT_CMD_LSPEED_M    0x3f
2828 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2829 #define FW_PORT_CMD_LSPEED_G(x) \
2830         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2831
2832 #define FW_PORT_CMD_TXPAUSE_S           23
2833 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2834 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2835
2836 #define FW_PORT_CMD_RXPAUSE_S           22
2837 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2838 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2839
2840 #define FW_PORT_CMD_MDIOCAP_S           21
2841 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2842 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2843
2844 #define FW_PORT_CMD_MDIOADDR_S          16
2845 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2846 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2847         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2848
2849 #define FW_PORT_CMD_LPTXPAUSE_S         15
2850 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2851 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2852
2853 #define FW_PORT_CMD_LPRXPAUSE_S         14
2854 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2855 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2856
2857 #define FW_PORT_CMD_PTYPE_S     8
2858 #define FW_PORT_CMD_PTYPE_M     0x1f
2859 #define FW_PORT_CMD_PTYPE_G(x)  \
2860         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2861
2862 #define FW_PORT_CMD_LINKDNRC_S          5
2863 #define FW_PORT_CMD_LINKDNRC_M          0x7
2864 #define FW_PORT_CMD_LINKDNRC_G(x)       \
2865         (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2866
2867 #define FW_PORT_CMD_MODTYPE_S           0
2868 #define FW_PORT_CMD_MODTYPE_M           0x1f
2869 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2870 #define FW_PORT_CMD_MODTYPE_G(x)        \
2871         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2872
2873 #define FW_PORT_CMD_DCBXDIS_S           7
2874 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2875 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2876
2877 #define FW_PORT_CMD_APPLY_S     7
2878 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2879 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2880
2881 #define FW_PORT_CMD_ALL_SYNCD_S         7
2882 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2883 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2884
2885 #define FW_PORT_CMD_DCB_VERSION_S       12
2886 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2887 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2888         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2889
2890 #define FW_PORT_CMD_LSTATUS32_S         31
2891 #define FW_PORT_CMD_LSTATUS32_M         0x1
2892 #define FW_PORT_CMD_LSTATUS32_V(x)      ((x) << FW_PORT_CMD_LSTATUS32_S)
2893 #define FW_PORT_CMD_LSTATUS32_G(x)      \
2894         (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)
2895 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U)
2896
2897 #define FW_PORT_CMD_LINKDNRC32_S        28
2898 #define FW_PORT_CMD_LINKDNRC32_M        0x7
2899 #define FW_PORT_CMD_LINKDNRC32_V(x)     ((x) << FW_PORT_CMD_LINKDNRC32_S)
2900 #define FW_PORT_CMD_LINKDNRC32_G(x)     \
2901         (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)
2902
2903 #define FW_PORT_CMD_DCBXDIS32_S         27
2904 #define FW_PORT_CMD_DCBXDIS32_M         0x1
2905 #define FW_PORT_CMD_DCBXDIS32_V(x)      ((x) << FW_PORT_CMD_DCBXDIS32_S)
2906 #define FW_PORT_CMD_DCBXDIS32_G(x)      \
2907         (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)
2908 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U)
2909
2910 #define FW_PORT_CMD_MDIOCAP32_S         26
2911 #define FW_PORT_CMD_MDIOCAP32_M         0x1
2912 #define FW_PORT_CMD_MDIOCAP32_V(x)      ((x) << FW_PORT_CMD_MDIOCAP32_S)
2913 #define FW_PORT_CMD_MDIOCAP32_G(x)      \
2914         (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)
2915 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U)
2916
2917 #define FW_PORT_CMD_MDIOADDR32_S        21
2918 #define FW_PORT_CMD_MDIOADDR32_M        0x1f
2919 #define FW_PORT_CMD_MDIOADDR32_V(x)     ((x) << FW_PORT_CMD_MDIOADDR32_S)
2920 #define FW_PORT_CMD_MDIOADDR32_G(x)     \
2921         (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)
2922
2923 #define FW_PORT_CMD_PORTTYPE32_S        13
2924 #define FW_PORT_CMD_PORTTYPE32_M        0xff
2925 #define FW_PORT_CMD_PORTTYPE32_V(x)     ((x) << FW_PORT_CMD_PORTTYPE32_S)
2926 #define FW_PORT_CMD_PORTTYPE32_G(x)     \
2927         (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)
2928
2929 #define FW_PORT_CMD_MODTYPE32_S         8
2930 #define FW_PORT_CMD_MODTYPE32_M         0x1f
2931 #define FW_PORT_CMD_MODTYPE32_V(x)      ((x) << FW_PORT_CMD_MODTYPE32_S)
2932 #define FW_PORT_CMD_MODTYPE32_G(x)      \
2933         (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)
2934
2935 #define FW_PORT_CMD_CBLLEN32_S          0
2936 #define FW_PORT_CMD_CBLLEN32_M          0xff
2937 #define FW_PORT_CMD_CBLLEN32_V(x)       ((x) << FW_PORT_CMD_CBLLEN32_S)
2938 #define FW_PORT_CMD_CBLLEN32_G(x)       \
2939         (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)
2940
2941 #define FW_PORT_CMD_AUXLINFO32_S        24
2942 #define FW_PORT_CMD_AUXLINFO32_M        0xff
2943 #define FW_PORT_CMD_AUXLINFO32_V(x)     ((x) << FW_PORT_CMD_AUXLINFO32_S)
2944 #define FW_PORT_CMD_AUXLINFO32_G(x)     \
2945         (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)
2946
2947 #define FW_PORT_AUXLINFO32_KX4_S        2
2948 #define FW_PORT_AUXLINFO32_KX4_M        0x1
2949 #define FW_PORT_AUXLINFO32_KX4_V(x) \
2950         ((x) << FW_PORT_AUXLINFO32_KX4_S)
2951 #define FW_PORT_AUXLINFO32_KX4_G(x) \
2952         (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)
2953 #define FW_PORT_AUXLINFO32_KX4_F        FW_PORT_AUXLINFO32_KX4_V(1U)
2954
2955 #define FW_PORT_AUXLINFO32_KR_S 1
2956 #define FW_PORT_AUXLINFO32_KR_M 0x1
2957 #define FW_PORT_AUXLINFO32_KR_V(x) \
2958         ((x) << FW_PORT_AUXLINFO32_KR_S)
2959 #define FW_PORT_AUXLINFO32_KR_G(x) \
2960         (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)
2961 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U)
2962
2963 #define FW_PORT_CMD_MTU32_S     0
2964 #define FW_PORT_CMD_MTU32_M     0xffff
2965 #define FW_PORT_CMD_MTU32_V(x)  ((x) << FW_PORT_CMD_MTU32_S)
2966 #define FW_PORT_CMD_MTU32_G(x)  \
2967         (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)
2968
2969 enum fw_port_type {
2970         FW_PORT_TYPE_FIBER_XFI,
2971         FW_PORT_TYPE_FIBER_XAUI,
2972         FW_PORT_TYPE_BT_SGMII,
2973         FW_PORT_TYPE_BT_XFI,
2974         FW_PORT_TYPE_BT_XAUI,
2975         FW_PORT_TYPE_KX4,
2976         FW_PORT_TYPE_CX4,
2977         FW_PORT_TYPE_KX,
2978         FW_PORT_TYPE_KR,
2979         FW_PORT_TYPE_SFP,
2980         FW_PORT_TYPE_BP_AP,
2981         FW_PORT_TYPE_BP4_AP,
2982         FW_PORT_TYPE_QSFP_10G,
2983         FW_PORT_TYPE_QSA,
2984         FW_PORT_TYPE_QSFP,
2985         FW_PORT_TYPE_BP40_BA,
2986         FW_PORT_TYPE_KR4_100G,
2987         FW_PORT_TYPE_CR4_QSFP,
2988         FW_PORT_TYPE_CR_QSFP,
2989         FW_PORT_TYPE_CR2_QSFP,
2990         FW_PORT_TYPE_SFP28,
2991         FW_PORT_TYPE_KR_SFP28,
2992         FW_PORT_TYPE_KR_XLAUI,
2993
2994         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2995 };
2996
2997 enum fw_port_module_type {
2998         FW_PORT_MOD_TYPE_NA,
2999         FW_PORT_MOD_TYPE_LR,
3000         FW_PORT_MOD_TYPE_SR,
3001         FW_PORT_MOD_TYPE_ER,
3002         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
3003         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
3004         FW_PORT_MOD_TYPE_LRM,
3005         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
3006         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
3007         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
3008
3009         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
3010 };
3011
3012 enum fw_port_mod_sub_type {
3013         FW_PORT_MOD_SUB_TYPE_NA,
3014         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
3015         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
3016         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
3017         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
3018         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
3019         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
3020
3021         /* The following will never been in the VPD.  They are TWINAX cable
3022          * lengths decoded from SFP+ module i2c PROMs.  These should
3023          * almost certainly go somewhere else ...
3024          */
3025         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
3026         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
3027         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
3028         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
3029 };
3030
3031 enum fw_port_stats_tx_index {
3032         FW_STAT_TX_PORT_BYTES_IX = 0,
3033         FW_STAT_TX_PORT_FRAMES_IX,
3034         FW_STAT_TX_PORT_BCAST_IX,
3035         FW_STAT_TX_PORT_MCAST_IX,
3036         FW_STAT_TX_PORT_UCAST_IX,
3037         FW_STAT_TX_PORT_ERROR_IX,
3038         FW_STAT_TX_PORT_64B_IX,
3039         FW_STAT_TX_PORT_65B_127B_IX,
3040         FW_STAT_TX_PORT_128B_255B_IX,
3041         FW_STAT_TX_PORT_256B_511B_IX,
3042         FW_STAT_TX_PORT_512B_1023B_IX,
3043         FW_STAT_TX_PORT_1024B_1518B_IX,
3044         FW_STAT_TX_PORT_1519B_MAX_IX,
3045         FW_STAT_TX_PORT_DROP_IX,
3046         FW_STAT_TX_PORT_PAUSE_IX,
3047         FW_STAT_TX_PORT_PPP0_IX,
3048         FW_STAT_TX_PORT_PPP1_IX,
3049         FW_STAT_TX_PORT_PPP2_IX,
3050         FW_STAT_TX_PORT_PPP3_IX,
3051         FW_STAT_TX_PORT_PPP4_IX,
3052         FW_STAT_TX_PORT_PPP5_IX,
3053         FW_STAT_TX_PORT_PPP6_IX,
3054         FW_STAT_TX_PORT_PPP7_IX,
3055         FW_NUM_PORT_TX_STATS
3056 };
3057
3058 enum fw_port_stat_rx_index {
3059         FW_STAT_RX_PORT_BYTES_IX = 0,
3060         FW_STAT_RX_PORT_FRAMES_IX,
3061         FW_STAT_RX_PORT_BCAST_IX,
3062         FW_STAT_RX_PORT_MCAST_IX,
3063         FW_STAT_RX_PORT_UCAST_IX,
3064         FW_STAT_RX_PORT_MTU_ERROR_IX,
3065         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
3066         FW_STAT_RX_PORT_CRC_ERROR_IX,
3067         FW_STAT_RX_PORT_LEN_ERROR_IX,
3068         FW_STAT_RX_PORT_SYM_ERROR_IX,
3069         FW_STAT_RX_PORT_64B_IX,
3070         FW_STAT_RX_PORT_65B_127B_IX,
3071         FW_STAT_RX_PORT_128B_255B_IX,
3072         FW_STAT_RX_PORT_256B_511B_IX,
3073         FW_STAT_RX_PORT_512B_1023B_IX,
3074         FW_STAT_RX_PORT_1024B_1518B_IX,
3075         FW_STAT_RX_PORT_1519B_MAX_IX,
3076         FW_STAT_RX_PORT_PAUSE_IX,
3077         FW_STAT_RX_PORT_PPP0_IX,
3078         FW_STAT_RX_PORT_PPP1_IX,
3079         FW_STAT_RX_PORT_PPP2_IX,
3080         FW_STAT_RX_PORT_PPP3_IX,
3081         FW_STAT_RX_PORT_PPP4_IX,
3082         FW_STAT_RX_PORT_PPP5_IX,
3083         FW_STAT_RX_PORT_PPP6_IX,
3084         FW_STAT_RX_PORT_PPP7_IX,
3085         FW_STAT_RX_PORT_LESS_64B_IX,
3086         FW_STAT_RX_PORT_MAC_ERROR_IX,
3087         FW_NUM_PORT_RX_STATS
3088 };
3089
3090 /* port stats */
3091 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
3092
3093 struct fw_port_stats_cmd {
3094         __be32 op_to_portid;
3095         __be32 retval_len16;
3096         union fw_port_stats {
3097                 struct fw_port_stats_ctl {
3098                         u8 nstats_bg_bm;
3099                         u8 tx_ix;
3100                         __be16 r6;
3101                         __be32 r7;
3102                         __be64 stat0;
3103                         __be64 stat1;
3104                         __be64 stat2;
3105                         __be64 stat3;
3106                         __be64 stat4;
3107                         __be64 stat5;
3108                 } ctl;
3109                 struct fw_port_stats_all {
3110                         __be64 tx_bytes;
3111                         __be64 tx_frames;
3112                         __be64 tx_bcast;
3113                         __be64 tx_mcast;
3114                         __be64 tx_ucast;
3115                         __be64 tx_error;
3116                         __be64 tx_64b;
3117                         __be64 tx_65b_127b;
3118                         __be64 tx_128b_255b;
3119                         __be64 tx_256b_511b;
3120                         __be64 tx_512b_1023b;
3121                         __be64 tx_1024b_1518b;
3122                         __be64 tx_1519b_max;
3123                         __be64 tx_drop;
3124                         __be64 tx_pause;
3125                         __be64 tx_ppp0;
3126                         __be64 tx_ppp1;
3127                         __be64 tx_ppp2;
3128                         __be64 tx_ppp3;
3129                         __be64 tx_ppp4;
3130                         __be64 tx_ppp5;
3131                         __be64 tx_ppp6;
3132                         __be64 tx_ppp7;
3133                         __be64 rx_bytes;
3134                         __be64 rx_frames;
3135                         __be64 rx_bcast;
3136                         __be64 rx_mcast;
3137                         __be64 rx_ucast;
3138                         __be64 rx_mtu_error;
3139                         __be64 rx_mtu_crc_error;
3140                         __be64 rx_crc_error;
3141                         __be64 rx_len_error;
3142                         __be64 rx_sym_error;
3143                         __be64 rx_64b;
3144                         __be64 rx_65b_127b;
3145                         __be64 rx_128b_255b;
3146                         __be64 rx_256b_511b;
3147                         __be64 rx_512b_1023b;
3148                         __be64 rx_1024b_1518b;
3149                         __be64 rx_1519b_max;
3150                         __be64 rx_pause;
3151                         __be64 rx_ppp0;
3152                         __be64 rx_ppp1;
3153                         __be64 rx_ppp2;
3154                         __be64 rx_ppp3;
3155                         __be64 rx_ppp4;
3156                         __be64 rx_ppp5;
3157                         __be64 rx_ppp6;
3158                         __be64 rx_ppp7;
3159                         __be64 rx_less_64b;
3160                         __be64 rx_bg_drop;
3161                         __be64 rx_bg_trunc;
3162                 } all;
3163         } u;
3164 };
3165
3166 /* port loopback stats */
3167 #define FW_NUM_LB_STATS 16
3168 enum fw_port_lb_stats_index {
3169         FW_STAT_LB_PORT_BYTES_IX,
3170         FW_STAT_LB_PORT_FRAMES_IX,
3171         FW_STAT_LB_PORT_BCAST_IX,
3172         FW_STAT_LB_PORT_MCAST_IX,
3173         FW_STAT_LB_PORT_UCAST_IX,
3174         FW_STAT_LB_PORT_ERROR_IX,
3175         FW_STAT_LB_PORT_64B_IX,
3176         FW_STAT_LB_PORT_65B_127B_IX,
3177         FW_STAT_LB_PORT_128B_255B_IX,
3178         FW_STAT_LB_PORT_256B_511B_IX,
3179         FW_STAT_LB_PORT_512B_1023B_IX,
3180         FW_STAT_LB_PORT_1024B_1518B_IX,
3181         FW_STAT_LB_PORT_1519B_MAX_IX,
3182         FW_STAT_LB_PORT_DROP_FRAMES_IX
3183 };
3184
3185 struct fw_port_lb_stats_cmd {
3186         __be32 op_to_lbport;
3187         __be32 retval_len16;
3188         union fw_port_lb_stats {
3189                 struct fw_port_lb_stats_ctl {
3190                         u8 nstats_bg_bm;
3191                         u8 ix_pkd;
3192                         __be16 r6;
3193                         __be32 r7;
3194                         __be64 stat0;
3195                         __be64 stat1;
3196                         __be64 stat2;
3197                         __be64 stat3;
3198                         __be64 stat4;
3199                         __be64 stat5;
3200                 } ctl;
3201                 struct fw_port_lb_stats_all {
3202                         __be64 tx_bytes;
3203                         __be64 tx_frames;
3204                         __be64 tx_bcast;
3205                         __be64 tx_mcast;
3206                         __be64 tx_ucast;
3207                         __be64 tx_error;
3208                         __be64 tx_64b;
3209                         __be64 tx_65b_127b;
3210                         __be64 tx_128b_255b;
3211                         __be64 tx_256b_511b;
3212                         __be64 tx_512b_1023b;
3213                         __be64 tx_1024b_1518b;
3214                         __be64 tx_1519b_max;
3215                         __be64 rx_lb_drop;
3216                         __be64 rx_lb_trunc;
3217                 } all;
3218         } u;
3219 };
3220
3221 enum fw_ptp_subop {
3222         /* none */
3223         FW_PTP_SC_INIT_TIMER            = 0x00,
3224         FW_PTP_SC_TX_TYPE               = 0x01,
3225         /* init */
3226         FW_PTP_SC_RXTIME_STAMP          = 0x08,
3227         FW_PTP_SC_RDRX_TYPE             = 0x09,
3228         /* ts */
3229         FW_PTP_SC_ADJ_FREQ              = 0x10,
3230         FW_PTP_SC_ADJ_TIME              = 0x11,
3231         FW_PTP_SC_ADJ_FTIME             = 0x12,
3232         FW_PTP_SC_WALL_CLOCK            = 0x13,
3233         FW_PTP_SC_GET_TIME              = 0x14,
3234         FW_PTP_SC_SET_TIME              = 0x15,
3235 };
3236
3237 struct fw_ptp_cmd {
3238         __be32 op_to_portid;
3239         __be32 retval_len16;
3240         union fw_ptp {
3241                 struct fw_ptp_sc {
3242                         __u8   sc;
3243                         __u8   r3[7];
3244                 } scmd;
3245                 struct fw_ptp_init {
3246                         __u8   sc;
3247                         __u8   txchan;
3248                         __be16 absid;
3249                         __be16 mode;
3250                         __be16 r3;
3251                 } init;
3252                 struct fw_ptp_ts {
3253                         __u8   sc;
3254                         __u8   sign;
3255                         __be16 r3;
3256                         __be32 ppb;
3257                         __be64 tm;
3258                 } ts;
3259         } u;
3260         __be64 r3;
3261 };
3262
3263 #define FW_PTP_CMD_PORTID_S             0
3264 #define FW_PTP_CMD_PORTID_M             0xf
3265 #define FW_PTP_CMD_PORTID_V(x)          ((x) << FW_PTP_CMD_PORTID_S)
3266 #define FW_PTP_CMD_PORTID_G(x)          \
3267         (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M)
3268
3269 struct fw_rss_ind_tbl_cmd {
3270         __be32 op_to_viid;
3271         __be32 retval_len16;
3272         __be16 niqid;
3273         __be16 startidx;
3274         __be32 r3;
3275         __be32 iq0_to_iq2;
3276         __be32 iq3_to_iq5;
3277         __be32 iq6_to_iq8;
3278         __be32 iq9_to_iq11;
3279         __be32 iq12_to_iq14;
3280         __be32 iq15_to_iq17;
3281         __be32 iq18_to_iq20;
3282         __be32 iq21_to_iq23;
3283         __be32 iq24_to_iq26;
3284         __be32 iq27_to_iq29;
3285         __be32 iq30_iq31;
3286         __be32 r15_lo;
3287 };
3288
3289 #define FW_RSS_IND_TBL_CMD_VIID_S       0
3290 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
3291
3292 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
3293 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
3294
3295 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
3296 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
3297
3298 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
3299 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
3300
3301 struct fw_rss_glb_config_cmd {
3302         __be32 op_to_write;
3303         __be32 retval_len16;
3304         union fw_rss_glb_config {
3305                 struct fw_rss_glb_config_manual {
3306                         __be32 mode_pkd;
3307                         __be32 r3;
3308                         __be64 r4;
3309                         __be64 r5;
3310                 } manual;
3311                 struct fw_rss_glb_config_basicvirtual {
3312                         __be32 mode_pkd;
3313                         __be32 synmapen_to_hashtoeplitz;
3314                         __be64 r8;
3315                         __be64 r9;
3316                 } basicvirtual;
3317         } u;
3318 };
3319
3320 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
3321 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
3322 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
3323 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
3324         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
3325
3326 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
3327 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
3328
3329 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
3330 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
3331         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
3332 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
3333         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
3334
3335 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
3336 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
3337         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
3338 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
3339         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
3340
3341 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
3342 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
3343         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
3344 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
3345         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
3346
3347 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
3348 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
3349         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
3350 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
3351         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
3352
3353 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
3354 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
3355         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
3356 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
3357         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
3358
3359 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
3360 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
3361         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
3362 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
3363         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
3364
3365 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
3366 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
3367         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
3368 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
3369         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
3370
3371 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
3372 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
3373         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
3374 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
3375         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
3376
3377 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
3378 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
3379         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
3380 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
3381         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
3382
3383 struct fw_rss_vi_config_cmd {
3384         __be32 op_to_viid;
3385 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
3386         __be32 retval_len16;
3387         union fw_rss_vi_config {
3388                 struct fw_rss_vi_config_manual {
3389                         __be64 r3;
3390                         __be64 r4;
3391                         __be64 r5;
3392                 } manual;
3393                 struct fw_rss_vi_config_basicvirtual {
3394                         __be32 r6;
3395                         __be32 defaultq_to_udpen;
3396                         __be64 r9;
3397                         __be64 r10;
3398                 } basicvirtual;
3399         } u;
3400 };
3401
3402 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
3403 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
3404
3405 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
3406 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
3407 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
3408         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
3409 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
3410         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
3411          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
3412
3413 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
3414 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
3415         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
3416 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
3417         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
3418
3419 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
3420 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
3421         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
3422 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
3423         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
3424
3425 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
3426 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
3427         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
3428 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
3429         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
3430
3431 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
3432 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
3433         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
3434 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
3435         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
3436
3437 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
3438 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
3439 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
3440
3441 enum fw_sched_sc {
3442         FW_SCHED_SC_PARAMS              = 1,
3443 };
3444
3445 struct fw_sched_cmd {
3446         __be32 op_to_write;
3447         __be32 retval_len16;
3448         union fw_sched {
3449                 struct fw_sched_config {
3450                         __u8   sc;
3451                         __u8   type;
3452                         __u8   minmaxen;
3453                         __u8   r3[5];
3454                         __u8   nclasses[4];
3455                         __be32 r4;
3456                 } config;
3457                 struct fw_sched_params {
3458                         __u8   sc;
3459                         __u8   type;
3460                         __u8   level;
3461                         __u8   mode;
3462                         __u8   unit;
3463                         __u8   rate;
3464                         __u8   ch;
3465                         __u8   cl;
3466                         __be32 min;
3467                         __be32 max;
3468                         __be16 weight;
3469                         __be16 pktsize;
3470                         __be16 burstsize;
3471                         __be16 r4;
3472                 } params;
3473         } u;
3474 };
3475
3476 struct fw_clip_cmd {
3477         __be32 op_to_write;
3478         __be32 alloc_to_len16;
3479         __be64 ip_hi;
3480         __be64 ip_lo;
3481         __be32 r4[2];
3482 };
3483
3484 #define FW_CLIP_CMD_ALLOC_S     31
3485 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
3486 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
3487
3488 #define FW_CLIP_CMD_FREE_S      30
3489 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
3490 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
3491
3492 enum fw_error_type {
3493         FW_ERROR_TYPE_EXCEPTION         = 0x0,
3494         FW_ERROR_TYPE_HWMODULE          = 0x1,
3495         FW_ERROR_TYPE_WR                = 0x2,
3496         FW_ERROR_TYPE_ACL               = 0x3,
3497 };
3498
3499 struct fw_error_cmd {
3500         __be32 op_to_type;
3501         __be32 len16_pkd;
3502         union fw_error {
3503                 struct fw_error_exception {
3504                         __be32 info[6];
3505                 } exception;
3506                 struct fw_error_hwmodule {
3507                         __be32 regaddr;
3508                         __be32 regval;
3509                 } hwmodule;
3510                 struct fw_error_wr {
3511                         __be16 cidx;
3512                         __be16 pfn_vfn;
3513                         __be32 eqid;
3514                         u8 wrhdr[16];
3515                 } wr;
3516                 struct fw_error_acl {
3517                         __be16 cidx;
3518                         __be16 pfn_vfn;
3519                         __be32 eqid;
3520                         __be16 mv_pkd;
3521                         u8 val[6];
3522                         __be64 r4;
3523                 } acl;
3524         } u;
3525 };
3526
3527 struct fw_debug_cmd {
3528         __be32 op_type;
3529         __be32 len16_pkd;
3530         union fw_debug {
3531                 struct fw_debug_assert {
3532                         __be32 fcid;
3533                         __be32 line;
3534                         __be32 x;
3535                         __be32 y;
3536                         u8 filename_0_7[8];
3537                         u8 filename_8_15[8];
3538                         __be64 r3;
3539                 } assert;
3540                 struct fw_debug_prt {
3541                         __be16 dprtstridx;
3542                         __be16 r3[3];
3543                         __be32 dprtstrparam0;
3544                         __be32 dprtstrparam1;
3545                         __be32 dprtstrparam2;
3546                         __be32 dprtstrparam3;
3547                 } prt;
3548         } u;
3549 };
3550
3551 #define FW_DEBUG_CMD_TYPE_S     0
3552 #define FW_DEBUG_CMD_TYPE_M     0xff
3553 #define FW_DEBUG_CMD_TYPE_G(x)  \
3554         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3555
3556 struct fw_hma_cmd {
3557         __be32 op_pkd;
3558         __be32 retval_len16;
3559         __be32 mode_to_pcie_params;
3560         __be32 naddr_size;
3561         __be32 addr_size_pkd;
3562         __be32 r6;
3563         __be64 phy_address[5];
3564 };
3565
3566 #define FW_HMA_CMD_MODE_S       31
3567 #define FW_HMA_CMD_MODE_M       0x1
3568 #define FW_HMA_CMD_MODE_V(x)    ((x) << FW_HMA_CMD_MODE_S)
3569 #define FW_HMA_CMD_MODE_G(x)    \
3570         (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M)
3571 #define FW_HMA_CMD_MODE_F       FW_HMA_CMD_MODE_V(1U)
3572
3573 #define FW_HMA_CMD_SOC_S        30
3574 #define FW_HMA_CMD_SOC_M        0x1
3575 #define FW_HMA_CMD_SOC_V(x)     ((x) << FW_HMA_CMD_SOC_S)
3576 #define FW_HMA_CMD_SOC_G(x)     (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)
3577 #define FW_HMA_CMD_SOC_F        FW_HMA_CMD_SOC_V(1U)
3578
3579 #define FW_HMA_CMD_EOC_S        29
3580 #define FW_HMA_CMD_EOC_M        0x1
3581 #define FW_HMA_CMD_EOC_V(x)     ((x) << FW_HMA_CMD_EOC_S)
3582 #define FW_HMA_CMD_EOC_G(x)     (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)
3583 #define FW_HMA_CMD_EOC_F        FW_HMA_CMD_EOC_V(1U)
3584
3585 #define FW_HMA_CMD_PCIE_PARAMS_S        0
3586 #define FW_HMA_CMD_PCIE_PARAMS_M        0x7ffffff
3587 #define FW_HMA_CMD_PCIE_PARAMS_V(x)     ((x) << FW_HMA_CMD_PCIE_PARAMS_S)
3588 #define FW_HMA_CMD_PCIE_PARAMS_G(x)     \
3589         (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M)
3590
3591 #define FW_HMA_CMD_NADDR_S      12
3592 #define FW_HMA_CMD_NADDR_M      0x3f
3593 #define FW_HMA_CMD_NADDR_V(x)   ((x) << FW_HMA_CMD_NADDR_S)
3594 #define FW_HMA_CMD_NADDR_G(x)   \
3595         (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M)
3596
3597 #define FW_HMA_CMD_SIZE_S       0
3598 #define FW_HMA_CMD_SIZE_M       0xfff
3599 #define FW_HMA_CMD_SIZE_V(x)    ((x) << FW_HMA_CMD_SIZE_S)
3600 #define FW_HMA_CMD_SIZE_G(x)    \
3601         (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M)
3602
3603 #define FW_HMA_CMD_ADDR_SIZE_S          11
3604 #define FW_HMA_CMD_ADDR_SIZE_M          0x1fffff
3605 #define FW_HMA_CMD_ADDR_SIZE_V(x)       ((x) << FW_HMA_CMD_ADDR_SIZE_S)
3606 #define FW_HMA_CMD_ADDR_SIZE_G(x)       \
3607         (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M)
3608
3609 enum pcie_fw_eval {
3610         PCIE_FW_EVAL_CRASH = 0,
3611 };
3612
3613 #define PCIE_FW_ERR_S           31
3614 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
3615 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
3616
3617 #define PCIE_FW_INIT_S          30
3618 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
3619 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
3620
3621 #define PCIE_FW_HALT_S          29
3622 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3623 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3624
3625 #define PCIE_FW_EVAL_S          24
3626 #define PCIE_FW_EVAL_M          0x7
3627 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3628
3629 #define PCIE_FW_MASTER_VLD_S    15
3630 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3631 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
3632
3633 #define PCIE_FW_MASTER_S        12
3634 #define PCIE_FW_MASTER_M        0x7
3635 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
3636 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3637
3638 struct fw_hdr {
3639         u8 ver;
3640         u8 chip;                        /* terminator chip type */
3641         __be16  len512;                 /* bin length in units of 512-bytes */
3642         __be32  fw_ver;                 /* firmware version */
3643         __be32  tp_microcode_ver;
3644         u8 intfver_nic;
3645         u8 intfver_vnic;
3646         u8 intfver_ofld;
3647         u8 intfver_ri;
3648         u8 intfver_iscsipdu;
3649         u8 intfver_iscsi;
3650         u8 intfver_fcoepdu;
3651         u8 intfver_fcoe;
3652         __u32   reserved2;
3653         __u32   reserved3;
3654         __u32   reserved4;
3655         __be32  flags;
3656         __be32  reserved6[23];
3657 };
3658
3659 enum fw_hdr_chip {
3660         FW_HDR_CHIP_T4,
3661         FW_HDR_CHIP_T5,
3662         FW_HDR_CHIP_T6
3663 };
3664
3665 #define FW_HDR_FW_VER_MAJOR_S   24
3666 #define FW_HDR_FW_VER_MAJOR_M   0xff
3667 #define FW_HDR_FW_VER_MAJOR_V(x) \
3668         ((x) << FW_HDR_FW_VER_MAJOR_S)
3669 #define FW_HDR_FW_VER_MAJOR_G(x) \
3670         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3671
3672 #define FW_HDR_FW_VER_MINOR_S   16
3673 #define FW_HDR_FW_VER_MINOR_M   0xff
3674 #define FW_HDR_FW_VER_MINOR_V(x) \
3675         ((x) << FW_HDR_FW_VER_MINOR_S)
3676 #define FW_HDR_FW_VER_MINOR_G(x) \
3677         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3678
3679 #define FW_HDR_FW_VER_MICRO_S   8
3680 #define FW_HDR_FW_VER_MICRO_M   0xff
3681 #define FW_HDR_FW_VER_MICRO_V(x) \
3682         ((x) << FW_HDR_FW_VER_MICRO_S)
3683 #define FW_HDR_FW_VER_MICRO_G(x) \
3684         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3685
3686 #define FW_HDR_FW_VER_BUILD_S   0
3687 #define FW_HDR_FW_VER_BUILD_M   0xff
3688 #define FW_HDR_FW_VER_BUILD_V(x) \
3689         ((x) << FW_HDR_FW_VER_BUILD_S)
3690 #define FW_HDR_FW_VER_BUILD_G(x) \
3691         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3692
3693 enum fw_hdr_intfver {
3694         FW_HDR_INTFVER_NIC      = 0x00,
3695         FW_HDR_INTFVER_VNIC     = 0x00,
3696         FW_HDR_INTFVER_OFLD     = 0x00,
3697         FW_HDR_INTFVER_RI       = 0x00,
3698         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3699         FW_HDR_INTFVER_ISCSI    = 0x00,
3700         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3701         FW_HDR_INTFVER_FCOE     = 0x00,
3702 };
3703
3704 enum fw_hdr_flags {
3705         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3706 };
3707
3708 /* length of the formatting string  */
3709 #define FW_DEVLOG_FMT_LEN       192
3710
3711 /* maximum number of the formatting string parameters */
3712 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3713
3714 /* priority levels */
3715 enum fw_devlog_level {
3716         FW_DEVLOG_LEVEL_EMERG   = 0x0,
3717         FW_DEVLOG_LEVEL_CRIT    = 0x1,
3718         FW_DEVLOG_LEVEL_ERR     = 0x2,
3719         FW_DEVLOG_LEVEL_NOTICE  = 0x3,
3720         FW_DEVLOG_LEVEL_INFO    = 0x4,
3721         FW_DEVLOG_LEVEL_DEBUG   = 0x5,
3722         FW_DEVLOG_LEVEL_MAX     = 0x5,
3723 };
3724
3725 /* facilities that may send a log message */
3726 enum fw_devlog_facility {
3727         FW_DEVLOG_FACILITY_CORE         = 0x00,
3728         FW_DEVLOG_FACILITY_CF           = 0x01,
3729         FW_DEVLOG_FACILITY_SCHED        = 0x02,
3730         FW_DEVLOG_FACILITY_TIMER        = 0x04,
3731         FW_DEVLOG_FACILITY_RES          = 0x06,
3732         FW_DEVLOG_FACILITY_HW           = 0x08,
3733         FW_DEVLOG_FACILITY_FLR          = 0x10,
3734         FW_DEVLOG_FACILITY_DMAQ         = 0x12,
3735         FW_DEVLOG_FACILITY_PHY          = 0x14,
3736         FW_DEVLOG_FACILITY_MAC          = 0x16,
3737         FW_DEVLOG_FACILITY_PORT         = 0x18,
3738         FW_DEVLOG_FACILITY_VI           = 0x1A,
3739         FW_DEVLOG_FACILITY_FILTER       = 0x1C,
3740         FW_DEVLOG_FACILITY_ACL          = 0x1E,
3741         FW_DEVLOG_FACILITY_TM           = 0x20,
3742         FW_DEVLOG_FACILITY_QFC          = 0x22,
3743         FW_DEVLOG_FACILITY_DCB          = 0x24,
3744         FW_DEVLOG_FACILITY_ETH          = 0x26,
3745         FW_DEVLOG_FACILITY_OFLD         = 0x28,
3746         FW_DEVLOG_FACILITY_RI           = 0x2A,
3747         FW_DEVLOG_FACILITY_ISCSI        = 0x2C,
3748         FW_DEVLOG_FACILITY_FCOE         = 0x2E,
3749         FW_DEVLOG_FACILITY_FOISCSI      = 0x30,
3750         FW_DEVLOG_FACILITY_FOFCOE       = 0x32,
3751         FW_DEVLOG_FACILITY_CHNET        = 0x34,
3752         FW_DEVLOG_FACILITY_MAX          = 0x34,
3753 };
3754
3755 /* log message format */
3756 struct fw_devlog_e {
3757         __be64  timestamp;
3758         __be32  seqno;
3759         __be16  reserved1;
3760         __u8    level;
3761         __u8    facility;
3762         __u8    fmt[FW_DEVLOG_FMT_LEN];
3763         __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];
3764         __be32  reserved3[4];
3765 };
3766
3767 struct fw_devlog_cmd {
3768         __be32 op_to_write;
3769         __be32 retval_len16;
3770         __u8   level;
3771         __u8   r2[7];
3772         __be32 memtype_devlog_memaddr16_devlog;
3773         __be32 memsize_devlog;
3774         __be32 r3[2];
3775 };
3776
3777 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S          28
3778 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M          0xf
3779 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)       \
3780         (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3781          FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3782
3783 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S        0
3784 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M        0xfffffff
3785 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)     \
3786         (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3787          FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3788
3789 /* P C I E   F W   P F 7   R E G I S T E R */
3790
3791 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3792  * access the "devlog" which needing to contact firmware.  The encoding is
3793  * mostly the same as that returned by the DEVLOG command except for the size
3794  * which is encoded as the number of entries in multiples-1 of 128 here rather
3795  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3796  * and 15 means 2048.  This of course in turn constrains the allowed values
3797  * for the devlog size ...
3798  */
3799 #define PCIE_FW_PF_DEVLOG               7
3800
3801 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3802 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3803 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3804         ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3805 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3806         (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3807          PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3808
3809 #define PCIE_FW_PF_DEVLOG_ADDR16_S      4
3810 #define PCIE_FW_PF_DEVLOG_ADDR16_M      0xffffff
3811 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)   ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3812 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3813         (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3814
3815 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S     0
3816 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M     0xf
3817 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)  ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3818 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3819         (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3820
3821 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3822
3823 struct fw_crypto_lookaside_wr {
3824         __be32 op_to_cctx_size;
3825         __be32 len16_pkd;
3826         __be32 session_id;
3827         __be32 rx_chid_to_rx_q_id;
3828         __be32 key_addr;
3829         __be32 pld_size_hash_size;
3830         __be64 cookie;
3831 };
3832
3833 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3834 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3835 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3836         ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3837 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3838         (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3839          FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3840
3841 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3842 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3843 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3844         ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3845 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3846         (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3847          FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3848 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3849
3850 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3851 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3852 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3853         ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3854 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3855         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3856          FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3857
3858 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3859 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3860 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3861         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3862 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3863         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3864          FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3865
3866 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3867 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3868 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3869         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3870 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3871         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3872          FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3873
3874 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3875 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3876 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3877         ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3878 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3879         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3880          FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3881
3882 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3883 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3884 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3885         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3886 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3887         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3888          FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3889
3890 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S  27
3891 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M  0x3
3892 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3893         ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3894 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3895         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3896
3897 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3898 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3899 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3900         ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3901 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3902         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3903          FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3904
3905 #define FW_CRYPTO_LOOKASIDE_WR_IV_S   23
3906 #define FW_CRYPTO_LOOKASIDE_WR_IV_M   0x3
3907 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3908         ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3909 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3910         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3911
3912 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S   15
3913 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M   0xff
3914 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
3915         ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
3916 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
3917         (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
3918          FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
3919
3920 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3921 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3922 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3923         ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3924 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3925         (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3926          FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3927
3928 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3929 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3930 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3931         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3932 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3933         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3934          FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3935
3936 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3937 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3938 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3939         ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3940 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3941         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3942          FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3943
3944 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
3945 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
3946 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
3947         ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
3948 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
3949         (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
3950          FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
3951
3952 struct fw_tlstx_data_wr {
3953         __be32 op_to_immdlen;
3954         __be32 flowid_len16;
3955         __be32 plen;
3956         __be32 lsodisable_to_flags;
3957         __be32 r5;
3958         __be32 ctxloc_to_exp;
3959         __be16 mfs;
3960         __be16 adjustedplen_pkd;
3961         __be16 expinplenmax_pkd;
3962         u8   pdusinplenmax_pkd;
3963         u8   r10;
3964 };
3965
3966 #define FW_TLSTX_DATA_WR_OPCODE_S       24
3967 #define FW_TLSTX_DATA_WR_OPCODE_M       0xff
3968 #define FW_TLSTX_DATA_WR_OPCODE_V(x)    ((x) << FW_TLSTX_DATA_WR_OPCODE_S)
3969 #define FW_TLSTX_DATA_WR_OPCODE_G(x)    \
3970         (((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M)
3971
3972 #define FW_TLSTX_DATA_WR_COMPL_S        21
3973 #define FW_TLSTX_DATA_WR_COMPL_M        0x1
3974 #define FW_TLSTX_DATA_WR_COMPL_V(x)     ((x) << FW_TLSTX_DATA_WR_COMPL_S)
3975 #define FW_TLSTX_DATA_WR_COMPL_G(x)     \
3976         (((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M)
3977 #define FW_TLSTX_DATA_WR_COMPL_F        FW_TLSTX_DATA_WR_COMPL_V(1U)
3978
3979 #define FW_TLSTX_DATA_WR_IMMDLEN_S      0
3980 #define FW_TLSTX_DATA_WR_IMMDLEN_M      0xff
3981 #define FW_TLSTX_DATA_WR_IMMDLEN_V(x)   ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S)
3982 #define FW_TLSTX_DATA_WR_IMMDLEN_G(x)   \
3983         (((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M)
3984
3985 #define FW_TLSTX_DATA_WR_FLOWID_S       8
3986 #define FW_TLSTX_DATA_WR_FLOWID_M       0xfffff
3987 #define FW_TLSTX_DATA_WR_FLOWID_V(x)    ((x) << FW_TLSTX_DATA_WR_FLOWID_S)
3988 #define FW_TLSTX_DATA_WR_FLOWID_G(x)    \
3989         (((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M)
3990
3991 #define FW_TLSTX_DATA_WR_LEN16_S        0
3992 #define FW_TLSTX_DATA_WR_LEN16_M        0xff
3993 #define FW_TLSTX_DATA_WR_LEN16_V(x)     ((x) << FW_TLSTX_DATA_WR_LEN16_S)
3994 #define FW_TLSTX_DATA_WR_LEN16_G(x)     \
3995         (((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M)
3996
3997 #define FW_TLSTX_DATA_WR_LSODISABLE_S   31
3998 #define FW_TLSTX_DATA_WR_LSODISABLE_M   0x1
3999 #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \
4000         ((x) << FW_TLSTX_DATA_WR_LSODISABLE_S)
4001 #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \
4002         (((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M)
4003 #define FW_TLSTX_DATA_WR_LSODISABLE_F   FW_TLSTX_DATA_WR_LSODISABLE_V(1U)
4004
4005 #define FW_TLSTX_DATA_WR_ALIGNPLD_S     30
4006 #define FW_TLSTX_DATA_WR_ALIGNPLD_M     0x1
4007 #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x)  ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S)
4008 #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x)  \
4009         (((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M)
4010 #define FW_TLSTX_DATA_WR_ALIGNPLD_F     FW_TLSTX_DATA_WR_ALIGNPLD_V(1U)
4011
4012 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29
4013 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1
4014 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \
4015         ((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S)
4016 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \
4017         (((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \
4018         FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M)
4019 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U)
4020
4021 #define FW_TLSTX_DATA_WR_FLAGS_S        0
4022 #define FW_TLSTX_DATA_WR_FLAGS_M        0xfffffff
4023 #define FW_TLSTX_DATA_WR_FLAGS_V(x)     ((x) << FW_TLSTX_DATA_WR_FLAGS_S)
4024 #define FW_TLSTX_DATA_WR_FLAGS_G(x)     \
4025         (((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M)
4026
4027 #define FW_TLSTX_DATA_WR_CTXLOC_S       30
4028 #define FW_TLSTX_DATA_WR_CTXLOC_M       0x3
4029 #define FW_TLSTX_DATA_WR_CTXLOC_V(x)    ((x) << FW_TLSTX_DATA_WR_CTXLOC_S)
4030 #define FW_TLSTX_DATA_WR_CTXLOC_G(x)    \
4031         (((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M)
4032
4033 #define FW_TLSTX_DATA_WR_IVDSGL_S       29
4034 #define FW_TLSTX_DATA_WR_IVDSGL_M       0x1
4035 #define FW_TLSTX_DATA_WR_IVDSGL_V(x)    ((x) << FW_TLSTX_DATA_WR_IVDSGL_S)
4036 #define FW_TLSTX_DATA_WR_IVDSGL_G(x)    \
4037         (((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M)
4038 #define FW_TLSTX_DATA_WR_IVDSGL_F       FW_TLSTX_DATA_WR_IVDSGL_V(1U)
4039
4040 #define FW_TLSTX_DATA_WR_KEYSIZE_S      24
4041 #define FW_TLSTX_DATA_WR_KEYSIZE_M      0x1f
4042 #define FW_TLSTX_DATA_WR_KEYSIZE_V(x)   ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S)
4043 #define FW_TLSTX_DATA_WR_KEYSIZE_G(x)   \
4044         (((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M)
4045
4046 #define FW_TLSTX_DATA_WR_NUMIVS_S       14
4047 #define FW_TLSTX_DATA_WR_NUMIVS_M       0xff
4048 #define FW_TLSTX_DATA_WR_NUMIVS_V(x)    ((x) << FW_TLSTX_DATA_WR_NUMIVS_S)
4049 #define FW_TLSTX_DATA_WR_NUMIVS_G(x)    \
4050         (((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M)
4051
4052 #define FW_TLSTX_DATA_WR_EXP_S          0
4053 #define FW_TLSTX_DATA_WR_EXP_M          0x3fff
4054 #define FW_TLSTX_DATA_WR_EXP_V(x)       ((x) << FW_TLSTX_DATA_WR_EXP_S)
4055 #define FW_TLSTX_DATA_WR_EXP_G(x)       \
4056         (((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M)
4057
4058 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1
4059 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \
4060         ((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S)
4061
4062 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4
4063 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \
4064         ((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S)
4065
4066 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2
4067 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \
4068         ((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S)
4069
4070 #endif /* _T4FW_INTERFACE_H_ */