drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F) {
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201                 adap->flags &= ~CXGB4_FW_OK;
 202         }
 203 }
 204
 205 /*
 206  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 207  */
 208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 209                          u32 mbox_addr)
 210 {
 211         for ( ; nflit; nflit--, mbox_addr += 8)
 212                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 213 }
 214
 215 /*
 216  * Handle a FW assertion reported in a mailbox.
 217  */
 218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 219 {
 220         struct fw_debug_cmd asrt;
 221
 222         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 223         dev_alert(adap->pdev_dev,
 224                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 225                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 226                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 227 }
 228
 229 /**
 230  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 231  *      @adapter: the adapter
 232  *      @cmd: the Firmware Mailbox Command or Reply
 233  *      @size: command length in bytes
 234  *      @access: the time (ms) needed to access the Firmware Mailbox
 235  *      @execute: the time (ms) the command spent being executed
 236  */
 237 static void t4_record_mbox(struct adapter *adapter,
 238                            const __be64 *cmd, unsigned int size,
 239                            int access, int execute)
 240 {
 241         struct mbox_cmd_log *log = adapter->mbox_log;
 242         struct mbox_cmd *entry;
 243         int i;
 244
 245         entry = mbox_cmd_log_entry(log, log->cursor++);
 246         if (log->cursor == log->size)
 247                 log->cursor = 0;
 248
 249         for (i = 0; i < size / 8; i++)
 250                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 251         while (i < MBOX_LEN / 8)
 252                 entry->cmd[i++] = 0;
 253         entry->timestamp = jiffies;
 254         entry->seqno = log->seqno++;
 255         entry->access = access;
 256         entry->execute = execute;
 257 }
 258
 259 /**
 260  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 261  *      @adap: the adapter
 262  *      @mbox: index of the mailbox to use
 263  *      @cmd: the command to write
 264  *      @size: command length in bytes
 265  *      @rpl: where to optionally store the reply
 266  *      @sleep_ok: if true we may sleep while awaiting command completion
 267  *      @timeout: time to wait for command to finish before timing out
 268  *
 269  *      Sends the given command to FW through the selected mailbox and waits
 270  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 271  *      store the FW's reply to the command.  The command and its optional
 272  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 273  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 274  *      the response.  If sleeping is allowed we use progressive backoff
 275  *      otherwise we spin.
 276  *
 277  *      The return value is 0 on success or a negative errno on failure.  A
 278  *      failure can happen either because we are not able to execute the
 279  *      command or FW executes it but signals an error.  In the latter case
 280  *      the return value is the error code indicated by FW (negated).
 281  */
 282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 283                             int size, void *rpl, bool sleep_ok, int timeout)
 284 {
 285         static const int delay[] = {
 286                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 287         };
 288
 289         struct mbox_list entry;
 290         u16 access = 0;
 291         u16 execute = 0;
 292         u32 v;
 293         u64 res;
 294         int i, ms, delay_idx, ret;
 295         const __be64 *p = cmd;
 296         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 297         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 298         __be64 cmd_rpl[MBOX_LEN / 8];
 299         u32 pcie_fw;
 300
 301         if ((size & 15) || size > MBOX_LEN)
 302                 return -EINVAL;
 303
 304         /*
 305          * If the device is off-line, as in EEH, commands will time out.
 306          * Fail them early so we don't waste time waiting.
 307          */
 308         if (adap->pdev->error_state != pci_channel_io_normal)
 309                 return -EIO;
 310
 311         /* If we have a negative timeout, that implies that we can't sleep. */
 312         if (timeout < 0) {
 313                 sleep_ok = false;
 314                 timeout = -timeout;
 315         }
 316
 317         /* Queue ourselves onto the mailbox access list.  When our entry is at
 318          * the front of the list, we have rights to access the mailbox.  So we
 319          * wait [for a while] till we're at the front [or bail out with an
 320          * EBUSY] ...
 321          */
 322         spin_lock_bh(&adap->mbox_lock);
 323         list_add_tail(&entry.list, &adap->mlist.list);
 324         spin_unlock_bh(&adap->mbox_lock);
 325
 326         delay_idx = 0;
 327         ms = delay[0];
 328
 329         for (i = 0; ; i += ms) {
 330                 /* If we've waited too long, return a busy indication.  This
 331                  * really ought to be based on our initial position in the
 332                  * mailbox access list but this is a start.  We very rarely
 333                  * contend on access to the mailbox ...
 334                  */
 335                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 336                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 337                         spin_lock_bh(&adap->mbox_lock);
 338                         list_del(&entry.list);
 339                         spin_unlock_bh(&adap->mbox_lock);
 340                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 341                         t4_record_mbox(adap, cmd, size, access, ret);
 342                         return ret;
 343                 }
 344
 345                 /* If we're at the head, break out and start the mailbox
 346                  * protocol.
 347                  */
 348                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 349                                      list) == &entry)
 350                         break;
 351
 352                 /* Delay for a bit before checking again ... */
 353                 if (sleep_ok) {
 354                         ms = delay[delay_idx];  /* last element may repeat */
 355                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 356                                 delay_idx++;
 357                         msleep(ms);
 358                 } else {
 359                         mdelay(ms);
 360                 }
 361         }
 362
 363         /* Loop trying to get ownership of the mailbox.  Return an error
 364          * if we can't gain ownership.
 365          */
 366         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 368                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 369         if (v != MBOX_OWNER_DRV) {
 370                 spin_lock_bh(&adap->mbox_lock);
 371                 list_del(&entry.list);
 372                 spin_unlock_bh(&adap->mbox_lock);
 373                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 374                 t4_record_mbox(adap, cmd, size, access, ret);
 375                 return ret;
 376         }
 377
 378         /* Copy in the new mailbox command and send it on its way ... */
 379         t4_record_mbox(adap, cmd, size, access, 0);
 380         for (i = 0; i < size; i += 8)
 381                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 382
 383         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 384         t4_read_reg(adap, ctl_reg);          /* flush write */
 385
 386         delay_idx = 0;
 387         ms = delay[0];
 388
 389         for (i = 0;
 390              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 391              i < timeout;
 392              i += ms) {
 393                 if (sleep_ok) {
 394                         ms = delay[delay_idx];  /* last element may repeat */
 395                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 396                                 delay_idx++;
 397                         msleep(ms);
 398                 } else
 399                         mdelay(ms);
 400
 401                 v = t4_read_reg(adap, ctl_reg);
 402                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 403                         if (!(v & MBMSGVALID_F)) {
 404                                 t4_write_reg(adap, ctl_reg, 0);
 405                                 continue;
 406                         }
 407
 408                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 409                         res = be64_to_cpu(cmd_rpl[0]);
 410
 411                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 412                                 fw_asrt(adap, data_reg);
 413                                 res = FW_CMD_RETVAL_V(EIO);
 414                         } else if (rpl) {
 415                                 memcpy(rpl, cmd_rpl, size);
 416                         }
 417
 418                         t4_write_reg(adap, ctl_reg, 0);
 419
 420                         execute = i + ms;
 421                         t4_record_mbox(adap, cmd_rpl,
 422                                        MBOX_LEN, access, execute);
 423                         spin_lock_bh(&adap->mbox_lock);
 424                         list_del(&entry.list);
 425                         spin_unlock_bh(&adap->mbox_lock);
 426                         return -FW_CMD_RETVAL_G((int)res);
 427                 }
 428         }
 429
 430         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 431         t4_record_mbox(adap, cmd, size, access, ret);
 432         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 433                 *(const u8 *)cmd, mbox);
 434         t4_report_fw_error(adap);
 435         spin_lock_bh(&adap->mbox_lock);
 436         list_del(&entry.list);
 437         spin_unlock_bh(&adap->mbox_lock);
 438         t4_fatal_err(adap);
 439         return ret;
 440 }
 441
 442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 443                     void *rpl, bool sleep_ok)
 444 {
 445         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 446                                        FW_CMD_MAX_TIMEOUT);
 447 }
 448
 449 static int t4_edc_err_read(struct adapter *adap, int idx)
 450 {
 451         u32 edc_ecc_err_addr_reg;
 452         u32 rdata_reg;
 453
 454         if (is_t4(adap->params.chip)) {
 455                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 456                 return 0;
 457         }
 458         if (idx != 0 && idx != 1) {
 459                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 460                 return 0;
 461         }
 462
 463         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 464         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 465
 466         CH_WARN(adap,
 467                 "edc%d err addr 0x%x: 0x%x.\n",
 468                 idx, edc_ecc_err_addr_reg,
 469                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 470         CH_WARN(adap,
 471                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 472                 rdata_reg,
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 480                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 481                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 482
 483         return 0;
 484 }
 485
 486 /**
 487  * t4_memory_rw_init - Get memory window relative offset, base, and size.
 488  * @adap: the adapter
 489  * @win: PCI-E Memory Window to use
 490  * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
 491  * @mem_off: memory relative offset with respect to @mtype.
 492  * @mem_base: configured memory base address.
 493  * @mem_aperture: configured memory window aperture.
 494  *
 495  * Get the configured memory window's relative offset, base, and size.
 496  */
 497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
 498                       u32 *mem_base, u32 *mem_aperture)
 499 {
 500         u32 edc_size, mc_size, mem_reg;
 501
 502         /* Offset into the region of memory which is being accessed
 503          * MEM_EDC0 = 0
 504          * MEM_EDC1 = 1
 505          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 506          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 507          * MEM_HMA  = 4
 508          */
 509         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 510         if (mtype == MEM_HMA) {
 511                 *mem_off = 2 * (edc_size * 1024 * 1024);
 512         } else if (mtype != MEM_MC1) {
 513                 *mem_off = (mtype * (edc_size * 1024 * 1024));
 514         } else {
 515                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 516                                                       MA_EXT_MEMORY0_BAR_A));
 517                 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 518         }
 519
 520         /* Each PCI-E Memory Window is programmed with a window size -- or
 521          * "aperture" -- which controls the granularity of its mapping onto
 522          * adapter memory.  We need to grab that aperture in order to know
 523          * how to use the specified window.  The window is also programmed
 524          * with the base address of the Memory Window in BAR0's address
 525          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 526          * the address is relative to BAR0.
 527          */
 528         mem_reg = t4_read_reg(adap,
 529                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 530                                                   win));
 531         /* a dead adapter will return 0xffffffff for PIO reads */
 532         if (mem_reg == 0xffffffff)
 533                 return -ENXIO;
 534
 535         *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 536         *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 537         if (is_t4(adap->params.chip))
 538                 *mem_base -= adap->t4_bar0;
 539
 540         return 0;
 541 }
 542
 543 /**
 544  * t4_memory_update_win - Move memory window to specified address.
 545  * @adap: the adapter
 546  * @win: PCI-E Memory Window to use
 547  * @addr: location to move.
 548  *
 549  * Move memory window to specified address.
 550  */
 551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
 552 {
 553         t4_write_reg(adap,
 554                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 555                      addr);
 556         /* Read it back to ensure that changes propagate before we
 557          * attempt to use the new value.
 558          */
 559         t4_read_reg(adap,
 560                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 561 }
 562
 563 /**
 564  * t4_memory_rw_residual - Read/Write residual data.
 565  * @adap: the adapter
 566  * @off: relative offset within residual to start read/write.
 567  * @addr: address within indicated memory type.
 568  * @buf: host memory buffer
 569  * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 570  *
 571  * Read/Write residual data less than 32-bits.
 572  */
 573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
 574                            int dir)
 575 {
 576         union {
 577                 u32 word;
 578                 char byte[4];
 579         } last;
 580         unsigned char *bp;
 581         int i;
 582
 583         if (dir == T4_MEMORY_READ) {
 584                 last.word = le32_to_cpu((__force __le32)
 585                                         t4_read_reg(adap, addr));
 586                 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
 587                         bp[i] = last.byte[i];
 588         } else {
 589                 last.word = *buf;
 590                 for (i = off; i < 4; i++)
 591                         last.byte[i] = 0;
 592                 t4_write_reg(adap, addr,
 593                              (__force u32)cpu_to_le32(last.word));
 594         }
 595 }
 596
 597 /**
 598  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 599  *      @adap: the adapter
 600  *      @win: PCI-E Memory Window to use
 601  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 602  *      @addr: address within indicated memory type
 603  *      @len: amount of memory to transfer
 604  *      @hbuf: host memory buffer
 605  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 606  *
 607  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 608  *      firmware memory address and host buffer must be aligned on 32-bit
 609  *      boundaries; the length may be arbitrary.  The memory is transferred as
 610  *      a raw byte sequence from/to the firmware's memory.  If this memory
 611  *      contains data structures which contain multi-byte integers, it's the
 612  *      caller's responsibility to perform appropriate byte order conversions.
 613  */
 614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 615                  u32 len, void *hbuf, int dir)
 616 {
 617         u32 pos, offset, resid, memoffset;
 618         u32 win_pf, mem_aperture, mem_base;
 619         u32 *buf;
 620         int ret;
 621
 622         /* Argument sanity checks ...
 623          */
 624         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 625                 return -EINVAL;
 626         buf = (u32 *)hbuf;
 627
 628         /* It's convenient to be able to handle lengths which aren't a
 629          * multiple of 32-bits because we often end up transferring files to
 630          * the firmware.  So we'll handle that by normalizing the length here
 631          * and then handling any residual transfer at the end.
 632          */
 633         resid = len & 0x3;
 634         len -= resid;
 635
 636         ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
 637                                 &mem_aperture);
 638         if (ret)
 639                 return ret;
 640
 641         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 642         addr = addr + memoffset;
 643
 644         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 645
 646         /* Calculate our initial PCI-E Memory Window Position and Offset into
 647          * that Window.
 648          */
 649         pos = addr & ~(mem_aperture - 1);
 650         offset = addr - pos;
 651
 652         /* Set up initial PCI-E Memory Window to cover the start of our
 653          * transfer.
 654          */
 655         t4_memory_update_win(adap, win, pos | win_pf);
 656
 657         /* Transfer data to/from the adapter as long as there's an integral
 658          * number of 32-bit transfers to complete.
 659          *
 660          * A note on Endianness issues:
 661          *
 662          * The "register" reads and writes below from/to the PCI-E Memory
 663          * Window invoke the standard adapter Big-Endian to PCI-E Link
 664          * Little-Endian "swizzel."  As a result, if we have the following
 665          * data in adapter memory:
 666          *
 667          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 668          *     Address:      i+0  i+1  i+2  i+3
 669          *
 670          * Then a read of the adapter memory via the PCI-E Memory Window
 671          * will yield:
 672          *
 673          *     x = readl(i)
 674          *         31                  0
 675          *         [ b3 | b2 | b1 | b0 ]
 676          *
 677          * If this value is stored into local memory on a Little-Endian system
 678          * it will show up correctly in local memory as:
 679          *
 680          *     ( ..., b0, b1, b2, b3, ... )
 681          *
 682          * But on a Big-Endian system, the store will show up in memory
 683          * incorrectly swizzled as:
 684          *
 685          *     ( ..., b3, b2, b1, b0, ... )
 686          *
 687          * So we need to account for this in the reads and writes to the
 688          * PCI-E Memory Window below by undoing the register read/write
 689          * swizzels.
 690          */
 691         while (len > 0) {
 692                 if (dir == T4_MEMORY_READ)
 693                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 694                                                 mem_base + offset));
 695                 else
 696                         t4_write_reg(adap, mem_base + offset,
 697                                      (__force u32)cpu_to_le32(*buf++));
 698                 offset += sizeof(__be32);
 699                 len -= sizeof(__be32);
 700
 701                 /* If we've reached the end of our current window aperture,
 702                  * move the PCI-E Memory Window on to the next.  Note that
 703                  * doing this here after "len" may be 0 allows us to set up
 704                  * the PCI-E Memory Window for a possible final residual
 705                  * transfer below ...
 706                  */
 707                 if (offset == mem_aperture) {
 708                         pos += mem_aperture;
 709                         offset = 0;
 710                         t4_memory_update_win(adap, win, pos | win_pf);
 711                 }
 712         }
 713
 714         /* If the original transfer had a length which wasn't a multiple of
 715          * 32-bits, now's where we need to finish off the transfer of the
 716          * residual amount.  The PCI-E Memory Window has already been moved
 717          * above (if necessary) to cover this final transfer.
 718          */
 719         if (resid)
 720                 t4_memory_rw_residual(adap, resid, mem_base + offset,
 721                                       (u8 *)buf, dir);
 722
 723         return 0;
 724 }
 725
 726 /* Return the specified PCI-E Configuration Space register from our Physical
 727  * Function.  We try first via a Firmware LDST Command since we prefer to let
 728  * the firmware own all of these registers, but if that fails we go for it
 729  * directly ourselves.
 730  */
 731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 732 {
 733         u32 val, ldst_addrspace;
 734
 735         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 736          * retrieve the specified PCI-E Configuration Space register.
 737          */
 738         struct fw_ldst_cmd ldst_cmd;
 739         int ret;
 740
 741         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 742         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 743         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 744                                                FW_CMD_REQUEST_F |
 745                                                FW_CMD_READ_F |
 746                                                ldst_addrspace);
 747         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 748         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 749         ldst_cmd.u.pcie.ctrl_to_fn =
 750                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 751         ldst_cmd.u.pcie.r = reg;
 752
 753         /* If the LDST Command succeeds, return the result, otherwise
 754          * fall through to reading it directly ourselves ...
 755          */
 756         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 757                          &ldst_cmd);
 758         if (ret == 0)
 759                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 760         else
 761                 /* Read the desired Configuration Space register via the PCI-E
 762                  * Backdoor mechanism.
 763                  */
 764                 t4_hw_pci_read_cfg4(adap, reg, &val);
 765         return val;
 766 }
 767
 768 /* Get the window based on base passed to it.
 769  * Window aperture is currently unhandled, but there is no use case for it
 770  * right now
 771  */
 772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 773                          u32 memwin_base)
 774 {
 775         u32 ret;
 776
 777         if (is_t4(adap->params.chip)) {
 778                 u32 bar0;
 779
 780                 /* Truncation intentional: we only read the bottom 32-bits of
 781                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 782                  * mechanism to read BAR0 instead of using
 783                  * pci_resource_start() because we could be operating from
 784                  * within a Virtual Machine which is trapping our accesses to
 785                  * our Configuration Space and we need to set up the PCI-E
 786                  * Memory Window decoders with the actual addresses which will
 787                  * be coming across the PCI-E link.
 788                  */
 789                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 790                 bar0 &= pci_mask;
 791                 adap->t4_bar0 = bar0;
 792
 793                 ret = bar0 + memwin_base;
 794         } else {
 795                 /* For T5, only relative offset inside the PCIe BAR is passed */
 796                 ret = memwin_base;
 797         }
 798         return ret;
 799 }
 800
 801 /* Get the default utility window (win0) used by everyone */
 802 u32 t4_get_util_window(struct adapter *adap)
 803 {
 804         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 805                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 806 }
 807
 808 /* Set up memory window for accessing adapter memory ranges.  (Read
 809  * back MA register to ensure that changes propagate before we attempt
 810  * to use the new values.)
 811  */
 812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 813 {
 814         t4_write_reg(adap,
 815                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 816                      memwin_base | BIR_V(0) |
 817                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 818         t4_read_reg(adap,
 819                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 820 }
 821
 822 /**
 823  *      t4_get_regs_len - return the size of the chips register set
 824  *      @adapter: the adapter
 825  *
 826  *      Returns the size of the chip's BAR0 register space.
 827  */
 828 unsigned int t4_get_regs_len(struct adapter *adapter)
 829 {
 830         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 831
 832         switch (chip_version) {
 833         case CHELSIO_T4:
 834                 return T4_REGMAP_SIZE;
 835
 836         case CHELSIO_T5:
 837         case CHELSIO_T6:
 838                 return T5_REGMAP_SIZE;
 839         }
 840
 841         dev_err(adapter->pdev_dev,
 842                 "Unsupported chip version %d\n", chip_version);
 843         return 0;
 844 }
 845
 846 /**
 847  *      t4_get_regs - read chip registers into provided buffer
 848  *      @adap: the adapter
 849  *      @buf: register buffer
 850  *      @buf_size: size (in bytes) of register buffer
 851  *
 852  *      If the provided register buffer isn't large enough for the chip's
 853  *      full register range, the register dump will be truncated to the
 854  *      register buffer's size.
 855  */
 856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 857 {
 858         static const unsigned int t4_reg_ranges[] = {
 859                 0x1008, 0x1108,
 860                 0x1180, 0x1184,
 861                 0x1190, 0x1194,
 862                 0x11a0, 0x11a4,
 863                 0x11b0, 0x11b4,
 864                 0x11fc, 0x123c,
 865                 0x1300, 0x173c,
 866                 0x1800, 0x18fc,
 867                 0x3000, 0x30d8,
 868                 0x30e0, 0x30e4,
 869                 0x30ec, 0x5910,
 870                 0x5920, 0x5924,
 871                 0x5960, 0x5960,
 872                 0x5968, 0x5968,
 873                 0x5970, 0x5970,
 874                 0x5978, 0x5978,
 875                 0x5980, 0x5980,
 876                 0x5988, 0x5988,
 877                 0x5990, 0x5990,
 878                 0x5998, 0x5998,
 879                 0x59a0, 0x59d4,
 880                 0x5a00, 0x5ae0,
 881                 0x5ae8, 0x5ae8,
 882                 0x5af0, 0x5af0,
 883                 0x5af8, 0x5af8,
 884                 0x6000, 0x6098,
 885                 0x6100, 0x6150,
 886                 0x6200, 0x6208,
 887                 0x6240, 0x6248,
 888                 0x6280, 0x62b0,
 889                 0x62c0, 0x6338,
 890                 0x6370, 0x638c,
 891                 0x6400, 0x643c,
 892                 0x6500, 0x6524,
 893                 0x6a00, 0x6a04,
 894                 0x6a14, 0x6a38,
 895                 0x6a60, 0x6a70,
 896                 0x6a78, 0x6a78,
 897                 0x6b00, 0x6b0c,
 898                 0x6b1c, 0x6b84,
 899                 0x6bf0, 0x6bf8,
 900                 0x6c00, 0x6c0c,
 901                 0x6c1c, 0x6c84,
 902                 0x6cf0, 0x6cf8,
 903                 0x6d00, 0x6d0c,
 904                 0x6d1c, 0x6d84,
 905                 0x6df0, 0x6df8,
 906                 0x6e00, 0x6e0c,
 907                 0x6e1c, 0x6e84,
 908                 0x6ef0, 0x6ef8,
 909                 0x6f00, 0x6f0c,
 910                 0x6f1c, 0x6f84,
 911                 0x6ff0, 0x6ff8,
 912                 0x7000, 0x700c,
 913                 0x701c, 0x7084,
 914                 0x70f0, 0x70f8,
 915                 0x7100, 0x710c,
 916                 0x711c, 0x7184,
 917                 0x71f0, 0x71f8,
 918                 0x7200, 0x720c,
 919                 0x721c, 0x7284,
 920                 0x72f0, 0x72f8,
 921                 0x7300, 0x730c,
 922                 0x731c, 0x7384,
 923                 0x73f0, 0x73f8,
 924                 0x7400, 0x7450,
 925                 0x7500, 0x7530,
 926                 0x7600, 0x760c,
 927                 0x7614, 0x761c,
 928                 0x7680, 0x76cc,
 929                 0x7700, 0x7798,
 930                 0x77c0, 0x77fc,
 931                 0x7900, 0x79fc,
 932                 0x7b00, 0x7b58,
 933                 0x7b60, 0x7b84,
 934                 0x7b8c, 0x7c38,
 935                 0x7d00, 0x7d38,
 936                 0x7d40, 0x7d80,
 937                 0x7d8c, 0x7ddc,
 938                 0x7de4, 0x7e04,
 939                 0x7e10, 0x7e1c,
 940                 0x7e24, 0x7e38,
 941                 0x7e40, 0x7e44,
 942                 0x7e4c, 0x7e78,
 943                 0x7e80, 0x7ea4,
 944                 0x7eac, 0x7edc,
 945                 0x7ee8, 0x7efc,
 946                 0x8dc0, 0x8e04,
 947                 0x8e10, 0x8e1c,
 948                 0x8e30, 0x8e78,
 949                 0x8ea0, 0x8eb8,
 950                 0x8ec0, 0x8f6c,
 951                 0x8fc0, 0x9008,
 952                 0x9010, 0x9058,
 953                 0x9060, 0x9060,
 954                 0x9068, 0x9074,
 955                 0x90fc, 0x90fc,
 956                 0x9400, 0x9408,
 957                 0x9410, 0x9458,
 958                 0x9600, 0x9600,
 959                 0x9608, 0x9638,
 960                 0x9640, 0x96bc,
 961                 0x9800, 0x9808,
 962                 0x9820, 0x983c,
 963                 0x9850, 0x9864,
 964                 0x9c00, 0x9c6c,
 965                 0x9c80, 0x9cec,
 966                 0x9d00, 0x9d6c,
 967                 0x9d80, 0x9dec,
 968                 0x9e00, 0x9e6c,
 969                 0x9e80, 0x9eec,
 970                 0x9f00, 0x9f6c,
 971                 0x9f80, 0x9fec,
 972                 0xd004, 0xd004,
 973                 0xd010, 0xd03c,
 974                 0xdfc0, 0xdfe0,
 975                 0xe000, 0xea7c,
 976                 0xf000, 0x11110,
 977                 0x11118, 0x11190,
 978                 0x19040, 0x1906c,
 979                 0x19078, 0x19080,
 980                 0x1908c, 0x190e4,
 981                 0x190f0, 0x190f8,
 982                 0x19100, 0x19110,
 983                 0x19120, 0x19124,
 984                 0x19150, 0x19194,
 985                 0x1919c, 0x191b0,
 986                 0x191d0, 0x191e8,
 987                 0x19238, 0x1924c,
 988                 0x193f8, 0x1943c,
 989                 0x1944c, 0x19474,
 990                 0x19490, 0x194e0,
 991                 0x194f0, 0x194f8,
 992                 0x19800, 0x19c08,
 993                 0x19c10, 0x19c90,
 994                 0x19ca0, 0x19ce4,
 995                 0x19cf0, 0x19d40,
 996                 0x19d50, 0x19d94,
 997                 0x19da0, 0x19de8,
 998                 0x19df0, 0x19e40,
 999                 0x19e50, 0x19e90,
1000                 0x19ea0, 0x19f4c,
1001                 0x1a000, 0x1a004,
1002                 0x1a010, 0x1a06c,
1003                 0x1a0b0, 0x1a0e4,
1004                 0x1a0ec, 0x1a0f4,
1005                 0x1a100, 0x1a108,
1006                 0x1a114, 0x1a120,
1007                 0x1a128, 0x1a130,
1008                 0x1a138, 0x1a138,
1009                 0x1a190, 0x1a1c4,
1010                 0x1a1fc, 0x1a1fc,
1011                 0x1e040, 0x1e04c,
1012                 0x1e284, 0x1e28c,
1013                 0x1e2c0, 0x1e2c0,
1014                 0x1e2e0, 0x1e2e0,
1015                 0x1e300, 0x1e384,
1016                 0x1e3c0, 0x1e3c8,
1017                 0x1e440, 0x1e44c,
1018                 0x1e684, 0x1e68c,
1019                 0x1e6c0, 0x1e6c0,
1020                 0x1e6e0, 0x1e6e0,
1021                 0x1e700, 0x1e784,
1022                 0x1e7c0, 0x1e7c8,
1023                 0x1e840, 0x1e84c,
1024                 0x1ea84, 0x1ea8c,
1025                 0x1eac0, 0x1eac0,
1026                 0x1eae0, 0x1eae0,
1027                 0x1eb00, 0x1eb84,
1028                 0x1ebc0, 0x1ebc8,
1029                 0x1ec40, 0x1ec4c,
1030                 0x1ee84, 0x1ee8c,
1031                 0x1eec0, 0x1eec0,
1032                 0x1eee0, 0x1eee0,
1033                 0x1ef00, 0x1ef84,
1034                 0x1efc0, 0x1efc8,
1035                 0x1f040, 0x1f04c,
1036                 0x1f284, 0x1f28c,
1037                 0x1f2c0, 0x1f2c0,
1038                 0x1f2e0, 0x1f2e0,
1039                 0x1f300, 0x1f384,
1040                 0x1f3c0, 0x1f3c8,
1041                 0x1f440, 0x1f44c,
1042                 0x1f684, 0x1f68c,
1043                 0x1f6c0, 0x1f6c0,
1044                 0x1f6e0, 0x1f6e0,
1045                 0x1f700, 0x1f784,
1046                 0x1f7c0, 0x1f7c8,
1047                 0x1f840, 0x1f84c,
1048                 0x1fa84, 0x1fa8c,
1049                 0x1fac0, 0x1fac0,
1050                 0x1fae0, 0x1fae0,
1051                 0x1fb00, 0x1fb84,
1052                 0x1fbc0, 0x1fbc8,
1053                 0x1fc40, 0x1fc4c,
1054                 0x1fe84, 0x1fe8c,
1055                 0x1fec0, 0x1fec0,
1056                 0x1fee0, 0x1fee0,
1057                 0x1ff00, 0x1ff84,
1058                 0x1ffc0, 0x1ffc8,
1059                 0x20000, 0x2002c,
1060                 0x20100, 0x2013c,
1061                 0x20190, 0x201a0,
1062                 0x201a8, 0x201b8,
1063                 0x201c4, 0x201c8,
1064                 0x20200, 0x20318,
1065                 0x20400, 0x204b4,
1066                 0x204c0, 0x20528,
1067                 0x20540, 0x20614,
1068                 0x21000, 0x21040,
1069                 0x2104c, 0x21060,
1070                 0x210c0, 0x210ec,
1071                 0x21200, 0x21268,
1072                 0x21270, 0x21284,
1073                 0x212fc, 0x21388,
1074                 0x21400, 0x21404,
1075                 0x21500, 0x21500,
1076                 0x21510, 0x21518,
1077                 0x2152c, 0x21530,
1078                 0x2153c, 0x2153c,
1079                 0x21550, 0x21554,
1080                 0x21600, 0x21600,
1081                 0x21608, 0x2161c,
1082                 0x21624, 0x21628,
1083                 0x21630, 0x21634,
1084                 0x2163c, 0x2163c,
1085                 0x21700, 0x2171c,
1086                 0x21780, 0x2178c,
1087                 0x21800, 0x21818,
1088                 0x21820, 0x21828,
1089                 0x21830, 0x21848,
1090                 0x21850, 0x21854,
1091                 0x21860, 0x21868,
1092                 0x21870, 0x21870,
1093                 0x21878, 0x21898,
1094                 0x218a0, 0x218a8,
1095                 0x218b0, 0x218c8,
1096                 0x218d0, 0x218d4,
1097                 0x218e0, 0x218e8,
1098                 0x218f0, 0x218f0,
1099                 0x218f8, 0x21a18,
1100                 0x21a20, 0x21a28,
1101                 0x21a30, 0x21a48,
1102                 0x21a50, 0x21a54,
1103                 0x21a60, 0x21a68,
1104                 0x21a70, 0x21a70,
1105                 0x21a78, 0x21a98,
1106                 0x21aa0, 0x21aa8,
1107                 0x21ab0, 0x21ac8,
1108                 0x21ad0, 0x21ad4,
1109                 0x21ae0, 0x21ae8,
1110                 0x21af0, 0x21af0,
1111                 0x21af8, 0x21c18,
1112                 0x21c20, 0x21c20,
1113                 0x21c28, 0x21c30,
1114                 0x21c38, 0x21c38,
1115                 0x21c80, 0x21c98,
1116                 0x21ca0, 0x21ca8,
1117                 0x21cb0, 0x21cc8,
1118                 0x21cd0, 0x21cd4,
1119                 0x21ce0, 0x21ce8,
1120                 0x21cf0, 0x21cf0,
1121                 0x21cf8, 0x21d7c,
1122                 0x21e00, 0x21e04,
1123                 0x22000, 0x2202c,
1124                 0x22100, 0x2213c,
1125                 0x22190, 0x221a0,
1126                 0x221a8, 0x221b8,
1127                 0x221c4, 0x221c8,
1128                 0x22200, 0x22318,
1129                 0x22400, 0x224b4,
1130                 0x224c0, 0x22528,
1131                 0x22540, 0x22614,
1132                 0x23000, 0x23040,
1133                 0x2304c, 0x23060,
1134                 0x230c0, 0x230ec,
1135                 0x23200, 0x23268,
1136                 0x23270, 0x23284,
1137                 0x232fc, 0x23388,
1138                 0x23400, 0x23404,
1139                 0x23500, 0x23500,
1140                 0x23510, 0x23518,
1141                 0x2352c, 0x23530,
1142                 0x2353c, 0x2353c,
1143                 0x23550, 0x23554,
1144                 0x23600, 0x23600,
1145                 0x23608, 0x2361c,
1146                 0x23624, 0x23628,
1147                 0x23630, 0x23634,
1148                 0x2363c, 0x2363c,
1149                 0x23700, 0x2371c,
1150                 0x23780, 0x2378c,
1151                 0x23800, 0x23818,
1152                 0x23820, 0x23828,
1153                 0x23830, 0x23848,
1154                 0x23850, 0x23854,
1155                 0x23860, 0x23868,
1156                 0x23870, 0x23870,
1157                 0x23878, 0x23898,
1158                 0x238a0, 0x238a8,
1159                 0x238b0, 0x238c8,
1160                 0x238d0, 0x238d4,
1161                 0x238e0, 0x238e8,
1162                 0x238f0, 0x238f0,
1163                 0x238f8, 0x23a18,
1164                 0x23a20, 0x23a28,
1165                 0x23a30, 0x23a48,
1166                 0x23a50, 0x23a54,
1167                 0x23a60, 0x23a68,
1168                 0x23a70, 0x23a70,
1169                 0x23a78, 0x23a98,
1170                 0x23aa0, 0x23aa8,
1171                 0x23ab0, 0x23ac8,
1172                 0x23ad0, 0x23ad4,
1173                 0x23ae0, 0x23ae8,
1174                 0x23af0, 0x23af0,
1175                 0x23af8, 0x23c18,
1176                 0x23c20, 0x23c20,
1177                 0x23c28, 0x23c30,
1178                 0x23c38, 0x23c38,
1179                 0x23c80, 0x23c98,
1180                 0x23ca0, 0x23ca8,
1181                 0x23cb0, 0x23cc8,
1182                 0x23cd0, 0x23cd4,
1183                 0x23ce0, 0x23ce8,
1184                 0x23cf0, 0x23cf0,
1185                 0x23cf8, 0x23d7c,
1186                 0x23e00, 0x23e04,
1187                 0x24000, 0x2402c,
1188                 0x24100, 0x2413c,
1189                 0x24190, 0x241a0,
1190                 0x241a8, 0x241b8,
1191                 0x241c4, 0x241c8,
1192                 0x24200, 0x24318,
1193                 0x24400, 0x244b4,
1194                 0x244c0, 0x24528,
1195                 0x24540, 0x24614,
1196                 0x25000, 0x25040,
1197                 0x2504c, 0x25060,
1198                 0x250c0, 0x250ec,
1199                 0x25200, 0x25268,
1200                 0x25270, 0x25284,
1201                 0x252fc, 0x25388,
1202                 0x25400, 0x25404,
1203                 0x25500, 0x25500,
1204                 0x25510, 0x25518,
1205                 0x2552c, 0x25530,
1206                 0x2553c, 0x2553c,
1207                 0x25550, 0x25554,
1208                 0x25600, 0x25600,
1209                 0x25608, 0x2561c,
1210                 0x25624, 0x25628,
1211                 0x25630, 0x25634,
1212                 0x2563c, 0x2563c,
1213                 0x25700, 0x2571c,
1214                 0x25780, 0x2578c,
1215                 0x25800, 0x25818,
1216                 0x25820, 0x25828,
1217                 0x25830, 0x25848,
1218                 0x25850, 0x25854,
1219                 0x25860, 0x25868,
1220                 0x25870, 0x25870,
1221                 0x25878, 0x25898,
1222                 0x258a0, 0x258a8,
1223                 0x258b0, 0x258c8,
1224                 0x258d0, 0x258d4,
1225                 0x258e0, 0x258e8,
1226                 0x258f0, 0x258f0,
1227                 0x258f8, 0x25a18,
1228                 0x25a20, 0x25a28,
1229                 0x25a30, 0x25a48,
1230                 0x25a50, 0x25a54,
1231                 0x25a60, 0x25a68,
1232                 0x25a70, 0x25a70,
1233                 0x25a78, 0x25a98,
1234                 0x25aa0, 0x25aa8,
1235                 0x25ab0, 0x25ac8,
1236                 0x25ad0, 0x25ad4,
1237                 0x25ae0, 0x25ae8,
1238                 0x25af0, 0x25af0,
1239                 0x25af8, 0x25c18,
1240                 0x25c20, 0x25c20,
1241                 0x25c28, 0x25c30,
1242                 0x25c38, 0x25c38,
1243                 0x25c80, 0x25c98,
1244                 0x25ca0, 0x25ca8,
1245                 0x25cb0, 0x25cc8,
1246                 0x25cd0, 0x25cd4,
1247                 0x25ce0, 0x25ce8,
1248                 0x25cf0, 0x25cf0,
1249                 0x25cf8, 0x25d7c,
1250                 0x25e00, 0x25e04,
1251                 0x26000, 0x2602c,
1252                 0x26100, 0x2613c,
1253                 0x26190, 0x261a0,
1254                 0x261a8, 0x261b8,
1255                 0x261c4, 0x261c8,
1256                 0x26200, 0x26318,
1257                 0x26400, 0x264b4,
1258                 0x264c0, 0x26528,
1259                 0x26540, 0x26614,
1260                 0x27000, 0x27040,
1261                 0x2704c, 0x27060,
1262                 0x270c0, 0x270ec,
1263                 0x27200, 0x27268,
1264                 0x27270, 0x27284,
1265                 0x272fc, 0x27388,
1266                 0x27400, 0x27404,
1267                 0x27500, 0x27500,
1268                 0x27510, 0x27518,
1269                 0x2752c, 0x27530,
1270                 0x2753c, 0x2753c,
1271                 0x27550, 0x27554,
1272                 0x27600, 0x27600,
1273                 0x27608, 0x2761c,
1274                 0x27624, 0x27628,
1275                 0x27630, 0x27634,
1276                 0x2763c, 0x2763c,
1277                 0x27700, 0x2771c,
1278                 0x27780, 0x2778c,
1279                 0x27800, 0x27818,
1280                 0x27820, 0x27828,
1281                 0x27830, 0x27848,
1282                 0x27850, 0x27854,
1283                 0x27860, 0x27868,
1284                 0x27870, 0x27870,
1285                 0x27878, 0x27898,
1286                 0x278a0, 0x278a8,
1287                 0x278b0, 0x278c8,
1288                 0x278d0, 0x278d4,
1289                 0x278e0, 0x278e8,
1290                 0x278f0, 0x278f0,
1291                 0x278f8, 0x27a18,
1292                 0x27a20, 0x27a28,
1293                 0x27a30, 0x27a48,
1294                 0x27a50, 0x27a54,
1295                 0x27a60, 0x27a68,
1296                 0x27a70, 0x27a70,
1297                 0x27a78, 0x27a98,
1298                 0x27aa0, 0x27aa8,
1299                 0x27ab0, 0x27ac8,
1300                 0x27ad0, 0x27ad4,
1301                 0x27ae0, 0x27ae8,
1302                 0x27af0, 0x27af0,
1303                 0x27af8, 0x27c18,
1304                 0x27c20, 0x27c20,
1305                 0x27c28, 0x27c30,
1306                 0x27c38, 0x27c38,
1307                 0x27c80, 0x27c98,
1308                 0x27ca0, 0x27ca8,
1309                 0x27cb0, 0x27cc8,
1310                 0x27cd0, 0x27cd4,
1311                 0x27ce0, 0x27ce8,
1312                 0x27cf0, 0x27cf0,
1313                 0x27cf8, 0x27d7c,
1314                 0x27e00, 0x27e04,
1315         };
1316
1317         static const unsigned int t5_reg_ranges[] = {
1318                 0x1008, 0x10c0,
1319                 0x10cc, 0x10f8,
1320                 0x1100, 0x1100,
1321                 0x110c, 0x1148,
1322                 0x1180, 0x1184,
1323                 0x1190, 0x1194,
1324                 0x11a0, 0x11a4,
1325                 0x11b0, 0x11b4,
1326                 0x11fc, 0x123c,
1327                 0x1280, 0x173c,
1328                 0x1800, 0x18fc,
1329                 0x3000, 0x3028,
1330                 0x3060, 0x30b0,
1331                 0x30b8, 0x30d8,
1332                 0x30e0, 0x30fc,
1333                 0x3140, 0x357c,
1334                 0x35a8, 0x35cc,
1335                 0x35ec, 0x35ec,
1336                 0x3600, 0x5624,
1337                 0x56cc, 0x56ec,
1338                 0x56f4, 0x5720,
1339                 0x5728, 0x575c,
1340                 0x580c, 0x5814,
1341                 0x5890, 0x589c,
1342                 0x58a4, 0x58ac,
1343                 0x58b8, 0x58bc,
1344                 0x5940, 0x59c8,
1345                 0x59d0, 0x59dc,
1346                 0x59fc, 0x5a18,
1347                 0x5a60, 0x5a70,
1348                 0x5a80, 0x5a9c,
1349                 0x5b94, 0x5bfc,
1350                 0x6000, 0x6020,
1351                 0x6028, 0x6040,
1352                 0x6058, 0x609c,
1353                 0x60a8, 0x614c,
1354                 0x7700, 0x7798,
1355                 0x77c0, 0x78fc,
1356                 0x7b00, 0x7b58,
1357                 0x7b60, 0x7b84,
1358                 0x7b8c, 0x7c54,
1359                 0x7d00, 0x7d38,
1360                 0x7d40, 0x7d80,
1361                 0x7d8c, 0x7ddc,
1362                 0x7de4, 0x7e04,
1363                 0x7e10, 0x7e1c,
1364                 0x7e24, 0x7e38,
1365                 0x7e40, 0x7e44,
1366                 0x7e4c, 0x7e78,
1367                 0x7e80, 0x7edc,
1368                 0x7ee8, 0x7efc,
1369                 0x8dc0, 0x8de0,
1370                 0x8df8, 0x8e04,
1371                 0x8e10, 0x8e84,
1372                 0x8ea0, 0x8f84,
1373                 0x8fc0, 0x9058,
1374                 0x9060, 0x9060,
1375                 0x9068, 0x90f8,
1376                 0x9400, 0x9408,
1377                 0x9410, 0x9470,
1378                 0x9600, 0x9600,
1379                 0x9608, 0x9638,
1380                 0x9640, 0x96f4,
1381                 0x9800, 0x9808,
1382                 0x9810, 0x9864,
1383                 0x9c00, 0x9c6c,
1384                 0x9c80, 0x9cec,
1385                 0x9d00, 0x9d6c,
1386                 0x9d80, 0x9dec,
1387                 0x9e00, 0x9e6c,
1388                 0x9e80, 0x9eec,
1389                 0x9f00, 0x9f6c,
1390                 0x9f80, 0xa020,
1391                 0xd000, 0xd004,
1392                 0xd010, 0xd03c,
1393                 0xdfc0, 0xdfe0,
1394                 0xe000, 0x1106c,
1395                 0x11074, 0x11088,
1396                 0x1109c, 0x1117c,
1397                 0x11190, 0x11204,
1398                 0x19040, 0x1906c,
1399                 0x19078, 0x19080,
1400                 0x1908c, 0x190e8,
1401                 0x190f0, 0x190f8,
1402                 0x19100, 0x19110,
1403                 0x19120, 0x19124,
1404                 0x19150, 0x19194,
1405                 0x1919c, 0x191b0,
1406                 0x191d0, 0x191e8,
1407                 0x19238, 0x19290,
1408                 0x193f8, 0x19428,
1409                 0x19430, 0x19444,
1410                 0x1944c, 0x1946c,
1411                 0x19474, 0x19474,
1412                 0x19490, 0x194cc,
1413                 0x194f0, 0x194f8,
1414                 0x19c00, 0x19c08,
1415                 0x19c10, 0x19c60,
1416                 0x19c94, 0x19ce4,
1417                 0x19cf0, 0x19d40,
1418                 0x19d50, 0x19d94,
1419                 0x19da0, 0x19de8,
1420                 0x19df0, 0x19e10,
1421                 0x19e50, 0x19e90,
1422                 0x19ea0, 0x19f24,
1423                 0x19f34, 0x19f34,
1424                 0x19f40, 0x19f50,
1425                 0x19f90, 0x19fb4,
1426                 0x19fc4, 0x19fe4,
1427                 0x1a000, 0x1a004,
1428                 0x1a010, 0x1a06c,
1429                 0x1a0b0, 0x1a0e4,
1430                 0x1a0ec, 0x1a0f8,
1431                 0x1a100, 0x1a108,
1432                 0x1a114, 0x1a130,
1433                 0x1a138, 0x1a1c4,
1434                 0x1a1fc, 0x1a1fc,
1435                 0x1e008, 0x1e00c,
1436                 0x1e040, 0x1e044,
1437                 0x1e04c, 0x1e04c,
1438                 0x1e284, 0x1e290,
1439                 0x1e2c0, 0x1e2c0,
1440                 0x1e2e0, 0x1e2e0,
1441                 0x1e300, 0x1e384,
1442                 0x1e3c0, 0x1e3c8,
1443                 0x1e408, 0x1e40c,
1444                 0x1e440, 0x1e444,
1445                 0x1e44c, 0x1e44c,
1446                 0x1e684, 0x1e690,
1447                 0x1e6c0, 0x1e6c0,
1448                 0x1e6e0, 0x1e6e0,
1449                 0x1e700, 0x1e784,
1450                 0x1e7c0, 0x1e7c8,
1451                 0x1e808, 0x1e80c,
1452                 0x1e840, 0x1e844,
1453                 0x1e84c, 0x1e84c,
1454                 0x1ea84, 0x1ea90,
1455                 0x1eac0, 0x1eac0,
1456                 0x1eae0, 0x1eae0,
1457                 0x1eb00, 0x1eb84,
1458                 0x1ebc0, 0x1ebc8,
1459                 0x1ec08, 0x1ec0c,
1460                 0x1ec40, 0x1ec44,
1461                 0x1ec4c, 0x1ec4c,
1462                 0x1ee84, 0x1ee90,
1463                 0x1eec0, 0x1eec0,
1464                 0x1eee0, 0x1eee0,
1465                 0x1ef00, 0x1ef84,
1466                 0x1efc0, 0x1efc8,
1467                 0x1f008, 0x1f00c,
1468                 0x1f040, 0x1f044,
1469                 0x1f04c, 0x1f04c,
1470                 0x1f284, 0x1f290,
1471                 0x1f2c0, 0x1f2c0,
1472                 0x1f2e0, 0x1f2e0,
1473                 0x1f300, 0x1f384,
1474                 0x1f3c0, 0x1f3c8,
1475                 0x1f408, 0x1f40c,
1476                 0x1f440, 0x1f444,
1477                 0x1f44c, 0x1f44c,
1478                 0x1f684, 0x1f690,
1479                 0x1f6c0, 0x1f6c0,
1480                 0x1f6e0, 0x1f6e0,
1481                 0x1f700, 0x1f784,
1482                 0x1f7c0, 0x1f7c8,
1483                 0x1f808, 0x1f80c,
1484                 0x1f840, 0x1f844,
1485                 0x1f84c, 0x1f84c,
1486                 0x1fa84, 0x1fa90,
1487                 0x1fac0, 0x1fac0,
1488                 0x1fae0, 0x1fae0,
1489                 0x1fb00, 0x1fb84,
1490                 0x1fbc0, 0x1fbc8,
1491                 0x1fc08, 0x1fc0c,
1492                 0x1fc40, 0x1fc44,
1493                 0x1fc4c, 0x1fc4c,
1494                 0x1fe84, 0x1fe90,
1495                 0x1fec0, 0x1fec0,
1496                 0x1fee0, 0x1fee0,
1497                 0x1ff00, 0x1ff84,
1498                 0x1ffc0, 0x1ffc8,
1499                 0x30000, 0x30030,
1500                 0x30100, 0x30144,
1501                 0x30190, 0x301a0,
1502                 0x301a8, 0x301b8,
1503                 0x301c4, 0x301c8,
1504                 0x301d0, 0x301d0,
1505                 0x30200, 0x30318,
1506                 0x30400, 0x304b4,
1507                 0x304c0, 0x3052c,
1508                 0x30540, 0x3061c,
1509                 0x30800, 0x30828,
1510                 0x30834, 0x30834,
1511                 0x308c0, 0x30908,
1512                 0x30910, 0x309ac,
1513                 0x30a00, 0x30a14,
1514                 0x30a1c, 0x30a2c,
1515                 0x30a44, 0x30a50,
1516                 0x30a74, 0x30a74,
1517                 0x30a7c, 0x30afc,
1518                 0x30b08, 0x30c24,
1519                 0x30d00, 0x30d00,
1520                 0x30d08, 0x30d14,
1521                 0x30d1c, 0x30d20,
1522                 0x30d3c, 0x30d3c,
1523                 0x30d48, 0x30d50,
1524                 0x31200, 0x3120c,
1525                 0x31220, 0x31220,
1526                 0x31240, 0x31240,
1527                 0x31600, 0x3160c,
1528                 0x31a00, 0x31a1c,
1529                 0x31e00, 0x31e20,
1530                 0x31e38, 0x31e3c,
1531                 0x31e80, 0x31e80,
1532                 0x31e88, 0x31ea8,
1533                 0x31eb0, 0x31eb4,
1534                 0x31ec8, 0x31ed4,
1535                 0x31fb8, 0x32004,
1536                 0x32200, 0x32200,
1537                 0x32208, 0x32240,
1538                 0x32248, 0x32280,
1539                 0x32288, 0x322c0,
1540                 0x322c8, 0x322fc,
1541                 0x32600, 0x32630,
1542                 0x32a00, 0x32abc,
1543                 0x32b00, 0x32b10,
1544                 0x32b20, 0x32b30,
1545                 0x32b40, 0x32b50,
1546                 0x32b60, 0x32b70,
1547                 0x33000, 0x33028,
1548                 0x33030, 0x33048,
1549                 0x33060, 0x33068,
1550                 0x33070, 0x3309c,
1551                 0x330f0, 0x33128,
1552                 0x33130, 0x33148,
1553                 0x33160, 0x33168,
1554                 0x33170, 0x3319c,
1555                 0x331f0, 0x33238,
1556                 0x33240, 0x33240,
1557                 0x33248, 0x33250,
1558                 0x3325c, 0x33264,
1559                 0x33270, 0x332b8,
1560                 0x332c0, 0x332e4,
1561                 0x332f8, 0x33338,
1562                 0x33340, 0x33340,
1563                 0x33348, 0x33350,
1564                 0x3335c, 0x33364,
1565                 0x33370, 0x333b8,
1566                 0x333c0, 0x333e4,
1567                 0x333f8, 0x33428,
1568                 0x33430, 0x33448,
1569                 0x33460, 0x33468,
1570                 0x33470, 0x3349c,
1571                 0x334f0, 0x33528,
1572                 0x33530, 0x33548,
1573                 0x33560, 0x33568,
1574                 0x33570, 0x3359c,
1575                 0x335f0, 0x33638,
1576                 0x33640, 0x33640,
1577                 0x33648, 0x33650,
1578                 0x3365c, 0x33664,
1579                 0x33670, 0x336b8,
1580                 0x336c0, 0x336e4,
1581                 0x336f8, 0x33738,
1582                 0x33740, 0x33740,
1583                 0x33748, 0x33750,
1584                 0x3375c, 0x33764,
1585                 0x33770, 0x337b8,
1586                 0x337c0, 0x337e4,
1587                 0x337f8, 0x337fc,
1588                 0x33814, 0x33814,
1589                 0x3382c, 0x3382c,
1590                 0x33880, 0x3388c,
1591                 0x338e8, 0x338ec,
1592                 0x33900, 0x33928,
1593                 0x33930, 0x33948,
1594                 0x33960, 0x33968,
1595                 0x33970, 0x3399c,
1596                 0x339f0, 0x33a38,
1597                 0x33a40, 0x33a40,
1598                 0x33a48, 0x33a50,
1599                 0x33a5c, 0x33a64,
1600                 0x33a70, 0x33ab8,
1601                 0x33ac0, 0x33ae4,
1602                 0x33af8, 0x33b10,
1603                 0x33b28, 0x33b28,
1604                 0x33b3c, 0x33b50,
1605                 0x33bf0, 0x33c10,
1606                 0x33c28, 0x33c28,
1607                 0x33c3c, 0x33c50,
1608                 0x33cf0, 0x33cfc,
1609                 0x34000, 0x34030,
1610                 0x34100, 0x34144,
1611                 0x34190, 0x341a0,
1612                 0x341a8, 0x341b8,
1613                 0x341c4, 0x341c8,
1614                 0x341d0, 0x341d0,
1615                 0x34200, 0x34318,
1616                 0x34400, 0x344b4,
1617                 0x344c0, 0x3452c,
1618                 0x34540, 0x3461c,
1619                 0x34800, 0x34828,
1620                 0x34834, 0x34834,
1621                 0x348c0, 0x34908,
1622                 0x34910, 0x349ac,
1623                 0x34a00, 0x34a14,
1624                 0x34a1c, 0x34a2c,
1625                 0x34a44, 0x34a50,
1626                 0x34a74, 0x34a74,
1627                 0x34a7c, 0x34afc,
1628                 0x34b08, 0x34c24,
1629                 0x34d00, 0x34d00,
1630                 0x34d08, 0x34d14,
1631                 0x34d1c, 0x34d20,
1632                 0x34d3c, 0x34d3c,
1633                 0x34d48, 0x34d50,
1634                 0x35200, 0x3520c,
1635                 0x35220, 0x35220,
1636                 0x35240, 0x35240,
1637                 0x35600, 0x3560c,
1638                 0x35a00, 0x35a1c,
1639                 0x35e00, 0x35e20,
1640                 0x35e38, 0x35e3c,
1641                 0x35e80, 0x35e80,
1642                 0x35e88, 0x35ea8,
1643                 0x35eb0, 0x35eb4,
1644                 0x35ec8, 0x35ed4,
1645                 0x35fb8, 0x36004,
1646                 0x36200, 0x36200,
1647                 0x36208, 0x36240,
1648                 0x36248, 0x36280,
1649                 0x36288, 0x362c0,
1650                 0x362c8, 0x362fc,
1651                 0x36600, 0x36630,
1652                 0x36a00, 0x36abc,
1653                 0x36b00, 0x36b10,
1654                 0x36b20, 0x36b30,
1655                 0x36b40, 0x36b50,
1656                 0x36b60, 0x36b70,
1657                 0x37000, 0x37028,
1658                 0x37030, 0x37048,
1659                 0x37060, 0x37068,
1660                 0x37070, 0x3709c,
1661                 0x370f0, 0x37128,
1662                 0x37130, 0x37148,
1663                 0x37160, 0x37168,
1664                 0x37170, 0x3719c,
1665                 0x371f0, 0x37238,
1666                 0x37240, 0x37240,
1667                 0x37248, 0x37250,
1668                 0x3725c, 0x37264,
1669                 0x37270, 0x372b8,
1670                 0x372c0, 0x372e4,
1671                 0x372f8, 0x37338,
1672                 0x37340, 0x37340,
1673                 0x37348, 0x37350,
1674                 0x3735c, 0x37364,
1675                 0x37370, 0x373b8,
1676                 0x373c0, 0x373e4,
1677                 0x373f8, 0x37428,
1678                 0x37430, 0x37448,
1679                 0x37460, 0x37468,
1680                 0x37470, 0x3749c,
1681                 0x374f0, 0x37528,
1682                 0x37530, 0x37548,
1683                 0x37560, 0x37568,
1684                 0x37570, 0x3759c,
1685                 0x375f0, 0x37638,
1686                 0x37640, 0x37640,
1687                 0x37648, 0x37650,
1688                 0x3765c, 0x37664,
1689                 0x37670, 0x376b8,
1690                 0x376c0, 0x376e4,
1691                 0x376f8, 0x37738,
1692                 0x37740, 0x37740,
1693                 0x37748, 0x37750,
1694                 0x3775c, 0x37764,
1695                 0x37770, 0x377b8,
1696                 0x377c0, 0x377e4,
1697                 0x377f8, 0x377fc,
1698                 0x37814, 0x37814,
1699                 0x3782c, 0x3782c,
1700                 0x37880, 0x3788c,
1701                 0x378e8, 0x378ec,
1702                 0x37900, 0x37928,
1703                 0x37930, 0x37948,
1704                 0x37960, 0x37968,
1705                 0x37970, 0x3799c,
1706                 0x379f0, 0x37a38,
1707                 0x37a40, 0x37a40,
1708                 0x37a48, 0x37a50,
1709                 0x37a5c, 0x37a64,
1710                 0x37a70, 0x37ab8,
1711                 0x37ac0, 0x37ae4,
1712                 0x37af8, 0x37b10,
1713                 0x37b28, 0x37b28,
1714                 0x37b3c, 0x37b50,
1715                 0x37bf0, 0x37c10,
1716                 0x37c28, 0x37c28,
1717                 0x37c3c, 0x37c50,
1718                 0x37cf0, 0x37cfc,
1719                 0x38000, 0x38030,
1720                 0x38100, 0x38144,
1721                 0x38190, 0x381a0,
1722                 0x381a8, 0x381b8,
1723                 0x381c4, 0x381c8,
1724                 0x381d0, 0x381d0,
1725                 0x38200, 0x38318,
1726                 0x38400, 0x384b4,
1727                 0x384c0, 0x3852c,
1728                 0x38540, 0x3861c,
1729                 0x38800, 0x38828,
1730                 0x38834, 0x38834,
1731                 0x388c0, 0x38908,
1732                 0x38910, 0x389ac,
1733                 0x38a00, 0x38a14,
1734                 0x38a1c, 0x38a2c,
1735                 0x38a44, 0x38a50,
1736                 0x38a74, 0x38a74,
1737                 0x38a7c, 0x38afc,
1738                 0x38b08, 0x38c24,
1739                 0x38d00, 0x38d00,
1740                 0x38d08, 0x38d14,
1741                 0x38d1c, 0x38d20,
1742                 0x38d3c, 0x38d3c,
1743                 0x38d48, 0x38d50,
1744                 0x39200, 0x3920c,
1745                 0x39220, 0x39220,
1746                 0x39240, 0x39240,
1747                 0x39600, 0x3960c,
1748                 0x39a00, 0x39a1c,
1749                 0x39e00, 0x39e20,
1750                 0x39e38, 0x39e3c,
1751                 0x39e80, 0x39e80,
1752                 0x39e88, 0x39ea8,
1753                 0x39eb0, 0x39eb4,
1754                 0x39ec8, 0x39ed4,
1755                 0x39fb8, 0x3a004,
1756                 0x3a200, 0x3a200,
1757                 0x3a208, 0x3a240,
1758                 0x3a248, 0x3a280,
1759                 0x3a288, 0x3a2c0,
1760                 0x3a2c8, 0x3a2fc,
1761                 0x3a600, 0x3a630,
1762                 0x3aa00, 0x3aabc,
1763                 0x3ab00, 0x3ab10,
1764                 0x3ab20, 0x3ab30,
1765                 0x3ab40, 0x3ab50,
1766                 0x3ab60, 0x3ab70,
1767                 0x3b000, 0x3b028,
1768                 0x3b030, 0x3b048,
1769                 0x3b060, 0x3b068,
1770                 0x3b070, 0x3b09c,
1771                 0x3b0f0, 0x3b128,
1772                 0x3b130, 0x3b148,
1773                 0x3b160, 0x3b168,
1774                 0x3b170, 0x3b19c,
1775                 0x3b1f0, 0x3b238,
1776                 0x3b240, 0x3b240,
1777                 0x3b248, 0x3b250,
1778                 0x3b25c, 0x3b264,
1779                 0x3b270, 0x3b2b8,
1780                 0x3b2c0, 0x3b2e4,
1781                 0x3b2f8, 0x3b338,
1782                 0x3b340, 0x3b340,
1783                 0x3b348, 0x3b350,
1784                 0x3b35c, 0x3b364,
1785                 0x3b370, 0x3b3b8,
1786                 0x3b3c0, 0x3b3e4,
1787                 0x3b3f8, 0x3b428,
1788                 0x3b430, 0x3b448,
1789                 0x3b460, 0x3b468,
1790                 0x3b470, 0x3b49c,
1791                 0x3b4f0, 0x3b528,
1792                 0x3b530, 0x3b548,
1793                 0x3b560, 0x3b568,
1794                 0x3b570, 0x3b59c,
1795                 0x3b5f0, 0x3b638,
1796                 0x3b640, 0x3b640,
1797                 0x3b648, 0x3b650,
1798                 0x3b65c, 0x3b664,
1799                 0x3b670, 0x3b6b8,
1800                 0x3b6c0, 0x3b6e4,
1801                 0x3b6f8, 0x3b738,
1802                 0x3b740, 0x3b740,
1803                 0x3b748, 0x3b750,
1804                 0x3b75c, 0x3b764,
1805                 0x3b770, 0x3b7b8,
1806                 0x3b7c0, 0x3b7e4,
1807                 0x3b7f8, 0x3b7fc,
1808                 0x3b814, 0x3b814,
1809                 0x3b82c, 0x3b82c,
1810                 0x3b880, 0x3b88c,
1811                 0x3b8e8, 0x3b8ec,
1812                 0x3b900, 0x3b928,
1813                 0x3b930, 0x3b948,
1814                 0x3b960, 0x3b968,
1815                 0x3b970, 0x3b99c,
1816                 0x3b9f0, 0x3ba38,
1817                 0x3ba40, 0x3ba40,
1818                 0x3ba48, 0x3ba50,
1819                 0x3ba5c, 0x3ba64,
1820                 0x3ba70, 0x3bab8,
1821                 0x3bac0, 0x3bae4,
1822                 0x3baf8, 0x3bb10,
1823                 0x3bb28, 0x3bb28,
1824                 0x3bb3c, 0x3bb50,
1825                 0x3bbf0, 0x3bc10,
1826                 0x3bc28, 0x3bc28,
1827                 0x3bc3c, 0x3bc50,
1828                 0x3bcf0, 0x3bcfc,
1829                 0x3c000, 0x3c030,
1830                 0x3c100, 0x3c144,
1831                 0x3c190, 0x3c1a0,
1832                 0x3c1a8, 0x3c1b8,
1833                 0x3c1c4, 0x3c1c8,
1834                 0x3c1d0, 0x3c1d0,
1835                 0x3c200, 0x3c318,
1836                 0x3c400, 0x3c4b4,
1837                 0x3c4c0, 0x3c52c,
1838                 0x3c540, 0x3c61c,
1839                 0x3c800, 0x3c828,
1840                 0x3c834, 0x3c834,
1841                 0x3c8c0, 0x3c908,
1842                 0x3c910, 0x3c9ac,
1843                 0x3ca00, 0x3ca14,
1844                 0x3ca1c, 0x3ca2c,
1845                 0x3ca44, 0x3ca50,
1846                 0x3ca74, 0x3ca74,
1847                 0x3ca7c, 0x3cafc,
1848                 0x3cb08, 0x3cc24,
1849                 0x3cd00, 0x3cd00,
1850                 0x3cd08, 0x3cd14,
1851                 0x3cd1c, 0x3cd20,
1852                 0x3cd3c, 0x3cd3c,
1853                 0x3cd48, 0x3cd50,
1854                 0x3d200, 0x3d20c,
1855                 0x3d220, 0x3d220,
1856                 0x3d240, 0x3d240,
1857                 0x3d600, 0x3d60c,
1858                 0x3da00, 0x3da1c,
1859                 0x3de00, 0x3de20,
1860                 0x3de38, 0x3de3c,
1861                 0x3de80, 0x3de80,
1862                 0x3de88, 0x3dea8,
1863                 0x3deb0, 0x3deb4,
1864                 0x3dec8, 0x3ded4,
1865                 0x3dfb8, 0x3e004,
1866                 0x3e200, 0x3e200,
1867                 0x3e208, 0x3e240,
1868                 0x3e248, 0x3e280,
1869                 0x3e288, 0x3e2c0,
1870                 0x3e2c8, 0x3e2fc,
1871                 0x3e600, 0x3e630,
1872                 0x3ea00, 0x3eabc,
1873                 0x3eb00, 0x3eb10,
1874                 0x3eb20, 0x3eb30,
1875                 0x3eb40, 0x3eb50,
1876                 0x3eb60, 0x3eb70,
1877                 0x3f000, 0x3f028,
1878                 0x3f030, 0x3f048,
1879                 0x3f060, 0x3f068,
1880                 0x3f070, 0x3f09c,
1881                 0x3f0f0, 0x3f128,
1882                 0x3f130, 0x3f148,
1883                 0x3f160, 0x3f168,
1884                 0x3f170, 0x3f19c,
1885                 0x3f1f0, 0x3f238,
1886                 0x3f240, 0x3f240,
1887                 0x3f248, 0x3f250,
1888                 0x3f25c, 0x3f264,
1889                 0x3f270, 0x3f2b8,
1890                 0x3f2c0, 0x3f2e4,
1891                 0x3f2f8, 0x3f338,
1892                 0x3f340, 0x3f340,
1893                 0x3f348, 0x3f350,
1894                 0x3f35c, 0x3f364,
1895                 0x3f370, 0x3f3b8,
1896                 0x3f3c0, 0x3f3e4,
1897                 0x3f3f8, 0x3f428,
1898                 0x3f430, 0x3f448,
1899                 0x3f460, 0x3f468,
1900                 0x3f470, 0x3f49c,
1901                 0x3f4f0, 0x3f528,
1902                 0x3f530, 0x3f548,
1903                 0x3f560, 0x3f568,
1904                 0x3f570, 0x3f59c,
1905                 0x3f5f0, 0x3f638,
1906                 0x3f640, 0x3f640,
1907                 0x3f648, 0x3f650,
1908                 0x3f65c, 0x3f664,
1909                 0x3f670, 0x3f6b8,
1910                 0x3f6c0, 0x3f6e4,
1911                 0x3f6f8, 0x3f738,
1912                 0x3f740, 0x3f740,
1913                 0x3f748, 0x3f750,
1914                 0x3f75c, 0x3f764,
1915                 0x3f770, 0x3f7b8,
1916                 0x3f7c0, 0x3f7e4,
1917                 0x3f7f8, 0x3f7fc,
1918                 0x3f814, 0x3f814,
1919                 0x3f82c, 0x3f82c,
1920                 0x3f880, 0x3f88c,
1921                 0x3f8e8, 0x3f8ec,
1922                 0x3f900, 0x3f928,
1923                 0x3f930, 0x3f948,
1924                 0x3f960, 0x3f968,
1925                 0x3f970, 0x3f99c,
1926                 0x3f9f0, 0x3fa38,
1927                 0x3fa40, 0x3fa40,
1928                 0x3fa48, 0x3fa50,
1929                 0x3fa5c, 0x3fa64,
1930                 0x3fa70, 0x3fab8,
1931                 0x3fac0, 0x3fae4,
1932                 0x3faf8, 0x3fb10,
1933                 0x3fb28, 0x3fb28,
1934                 0x3fb3c, 0x3fb50,
1935                 0x3fbf0, 0x3fc10,
1936                 0x3fc28, 0x3fc28,
1937                 0x3fc3c, 0x3fc50,
1938                 0x3fcf0, 0x3fcfc,
1939                 0x40000, 0x4000c,
1940                 0x40040, 0x40050,
1941                 0x40060, 0x40068,
1942                 0x4007c, 0x4008c,
1943                 0x40094, 0x400b0,
1944                 0x400c0, 0x40144,
1945                 0x40180, 0x4018c,
1946                 0x40200, 0x40254,
1947                 0x40260, 0x40264,
1948                 0x40270, 0x40288,
1949                 0x40290, 0x40298,
1950                 0x402ac, 0x402c8,
1951                 0x402d0, 0x402e0,
1952                 0x402f0, 0x402f0,
1953                 0x40300, 0x4033c,
1954                 0x403f8, 0x403fc,
1955                 0x41304, 0x413c4,
1956                 0x41400, 0x4140c,
1957                 0x41414, 0x4141c,
1958                 0x41480, 0x414d0,
1959                 0x44000, 0x44054,
1960                 0x4405c, 0x44078,
1961                 0x440c0, 0x44174,
1962                 0x44180, 0x441ac,
1963                 0x441b4, 0x441b8,
1964                 0x441c0, 0x44254,
1965                 0x4425c, 0x44278,
1966                 0x442c0, 0x44374,
1967                 0x44380, 0x443ac,
1968                 0x443b4, 0x443b8,
1969                 0x443c0, 0x44454,
1970                 0x4445c, 0x44478,
1971                 0x444c0, 0x44574,
1972                 0x44580, 0x445ac,
1973                 0x445b4, 0x445b8,
1974                 0x445c0, 0x44654,
1975                 0x4465c, 0x44678,
1976                 0x446c0, 0x44774,
1977                 0x44780, 0x447ac,
1978                 0x447b4, 0x447b8,
1979                 0x447c0, 0x44854,
1980                 0x4485c, 0x44878,
1981                 0x448c0, 0x44974,
1982                 0x44980, 0x449ac,
1983                 0x449b4, 0x449b8,
1984                 0x449c0, 0x449fc,
1985                 0x45000, 0x45004,
1986                 0x45010, 0x45030,
1987                 0x45040, 0x45060,
1988                 0x45068, 0x45068,
1989                 0x45080, 0x45084,
1990                 0x450a0, 0x450b0,
1991                 0x45200, 0x45204,
1992                 0x45210, 0x45230,
1993                 0x45240, 0x45260,
1994                 0x45268, 0x45268,
1995                 0x45280, 0x45284,
1996                 0x452a0, 0x452b0,
1997                 0x460c0, 0x460e4,
1998                 0x47000, 0x4703c,
1999                 0x47044, 0x4708c,
2000                 0x47200, 0x47250,
2001                 0x47400, 0x47408,
2002                 0x47414, 0x47420,
2003                 0x47600, 0x47618,
2004                 0x47800, 0x47814,
2005                 0x48000, 0x4800c,
2006                 0x48040, 0x48050,
2007                 0x48060, 0x48068,
2008                 0x4807c, 0x4808c,
2009                 0x48094, 0x480b0,
2010                 0x480c0, 0x48144,
2011                 0x48180, 0x4818c,
2012                 0x48200, 0x48254,
2013                 0x48260, 0x48264,
2014                 0x48270, 0x48288,
2015                 0x48290, 0x48298,
2016                 0x482ac, 0x482c8,
2017                 0x482d0, 0x482e0,
2018                 0x482f0, 0x482f0,
2019                 0x48300, 0x4833c,
2020                 0x483f8, 0x483fc,
2021                 0x49304, 0x493c4,
2022                 0x49400, 0x4940c,
2023                 0x49414, 0x4941c,
2024                 0x49480, 0x494d0,
2025                 0x4c000, 0x4c054,
2026                 0x4c05c, 0x4c078,
2027                 0x4c0c0, 0x4c174,
2028                 0x4c180, 0x4c1ac,
2029                 0x4c1b4, 0x4c1b8,
2030                 0x4c1c0, 0x4c254,
2031                 0x4c25c, 0x4c278,
2032                 0x4c2c0, 0x4c374,
2033                 0x4c380, 0x4c3ac,
2034                 0x4c3b4, 0x4c3b8,
2035                 0x4c3c0, 0x4c454,
2036                 0x4c45c, 0x4c478,
2037                 0x4c4c0, 0x4c574,
2038                 0x4c580, 0x4c5ac,
2039                 0x4c5b4, 0x4c5b8,
2040                 0x4c5c0, 0x4c654,
2041                 0x4c65c, 0x4c678,
2042                 0x4c6c0, 0x4c774,
2043                 0x4c780, 0x4c7ac,
2044                 0x4c7b4, 0x4c7b8,
2045                 0x4c7c0, 0x4c854,
2046                 0x4c85c, 0x4c878,
2047                 0x4c8c0, 0x4c974,
2048                 0x4c980, 0x4c9ac,
2049                 0x4c9b4, 0x4c9b8,
2050                 0x4c9c0, 0x4c9fc,
2051                 0x4d000, 0x4d004,
2052                 0x4d010, 0x4d030,
2053                 0x4d040, 0x4d060,
2054                 0x4d068, 0x4d068,
2055                 0x4d080, 0x4d084,
2056                 0x4d0a0, 0x4d0b0,
2057                 0x4d200, 0x4d204,
2058                 0x4d210, 0x4d230,
2059                 0x4d240, 0x4d260,
2060                 0x4d268, 0x4d268,
2061                 0x4d280, 0x4d284,
2062                 0x4d2a0, 0x4d2b0,
2063                 0x4e0c0, 0x4e0e4,
2064                 0x4f000, 0x4f03c,
2065                 0x4f044, 0x4f08c,
2066                 0x4f200, 0x4f250,
2067                 0x4f400, 0x4f408,
2068                 0x4f414, 0x4f420,
2069                 0x4f600, 0x4f618,
2070                 0x4f800, 0x4f814,
2071                 0x50000, 0x50084,
2072                 0x50090, 0x500cc,
2073                 0x50400, 0x50400,
2074                 0x50800, 0x50884,
2075                 0x50890, 0x508cc,
2076                 0x50c00, 0x50c00,
2077                 0x51000, 0x5101c,
2078                 0x51300, 0x51308,
2079         };
2080
2081         static const unsigned int t6_reg_ranges[] = {
2082                 0x1008, 0x101c,
2083                 0x1024, 0x10a8,
2084                 0x10b4, 0x10f8,
2085                 0x1100, 0x1114,
2086                 0x111c, 0x112c,
2087                 0x1138, 0x113c,
2088                 0x1144, 0x114c,
2089                 0x1180, 0x1184,
2090                 0x1190, 0x1194,
2091                 0x11a0, 0x11a4,
2092                 0x11b0, 0x11b4,
2093                 0x11fc, 0x1274,
2094                 0x1280, 0x133c,
2095                 0x1800, 0x18fc,
2096                 0x3000, 0x302c,
2097                 0x3060, 0x30b0,
2098                 0x30b8, 0x30d8,
2099                 0x30e0, 0x30fc,
2100                 0x3140, 0x357c,
2101                 0x35a8, 0x35cc,
2102                 0x35ec, 0x35ec,
2103                 0x3600, 0x5624,
2104                 0x56cc, 0x56ec,
2105                 0x56f4, 0x5720,
2106                 0x5728, 0x575c,
2107                 0x580c, 0x5814,
2108                 0x5890, 0x589c,
2109                 0x58a4, 0x58ac,
2110                 0x58b8, 0x58bc,
2111                 0x5940, 0x595c,
2112                 0x5980, 0x598c,
2113                 0x59b0, 0x59c8,
2114                 0x59d0, 0x59dc,
2115                 0x59fc, 0x5a18,
2116                 0x5a60, 0x5a6c,
2117                 0x5a80, 0x5a8c,
2118                 0x5a94, 0x5a9c,
2119                 0x5b94, 0x5bfc,
2120                 0x5c10, 0x5e48,
2121                 0x5e50, 0x5e94,
2122                 0x5ea0, 0x5eb0,
2123                 0x5ec0, 0x5ec0,
2124                 0x5ec8, 0x5ed0,
2125                 0x5ee0, 0x5ee0,
2126                 0x5ef0, 0x5ef0,
2127                 0x5f00, 0x5f00,
2128                 0x6000, 0x6020,
2129                 0x6028, 0x6040,
2130                 0x6058, 0x609c,
2131                 0x60a8, 0x619c,
2132                 0x7700, 0x7798,
2133                 0x77c0, 0x7880,
2134                 0x78cc, 0x78fc,
2135                 0x7b00, 0x7b58,
2136                 0x7b60, 0x7b84,
2137                 0x7b8c, 0x7c54,
2138                 0x7d00, 0x7d38,
2139                 0x7d40, 0x7d84,
2140                 0x7d8c, 0x7ddc,
2141                 0x7de4, 0x7e04,
2142                 0x7e10, 0x7e1c,
2143                 0x7e24, 0x7e38,
2144                 0x7e40, 0x7e44,
2145                 0x7e4c, 0x7e78,
2146                 0x7e80, 0x7edc,
2147                 0x7ee8, 0x7efc,
2148                 0x8dc0, 0x8de4,
2149                 0x8df8, 0x8e04,
2150                 0x8e10, 0x8e84,
2151                 0x8ea0, 0x8f88,
2152                 0x8fb8, 0x9058,
2153                 0x9060, 0x9060,
2154                 0x9068, 0x90f8,
2155                 0x9100, 0x9124,
2156                 0x9400, 0x9470,
2157                 0x9600, 0x9600,
2158                 0x9608, 0x9638,
2159                 0x9640, 0x9704,
2160                 0x9710, 0x971c,
2161                 0x9800, 0x9808,
2162                 0x9810, 0x9864,
2163                 0x9c00, 0x9c6c,
2164                 0x9c80, 0x9cec,
2165                 0x9d00, 0x9d6c,
2166                 0x9d80, 0x9dec,
2167                 0x9e00, 0x9e6c,
2168                 0x9e80, 0x9eec,
2169                 0x9f00, 0x9f6c,
2170                 0x9f80, 0xa020,
2171                 0xd000, 0xd03c,
2172                 0xd100, 0xd118,
2173                 0xd200, 0xd214,
2174                 0xd220, 0xd234,
2175                 0xd240, 0xd254,
2176                 0xd260, 0xd274,
2177                 0xd280, 0xd294,
2178                 0xd2a0, 0xd2b4,
2179                 0xd2c0, 0xd2d4,
2180                 0xd2e0, 0xd2f4,
2181                 0xd300, 0xd31c,
2182                 0xdfc0, 0xdfe0,
2183                 0xe000, 0xf008,
2184                 0xf010, 0xf018,
2185                 0xf020, 0xf028,
2186                 0x11000, 0x11014,
2187                 0x11048, 0x1106c,
2188                 0x11074, 0x11088,
2189                 0x11098, 0x11120,
2190                 0x1112c, 0x1117c,
2191                 0x11190, 0x112e0,
2192                 0x11300, 0x1130c,
2193                 0x12000, 0x1206c,
2194                 0x19040, 0x1906c,
2195                 0x19078, 0x19080,
2196                 0x1908c, 0x190e8,
2197                 0x190f0, 0x190f8,
2198                 0x19100, 0x19110,
2199                 0x19120, 0x19124,
2200                 0x19150, 0x19194,
2201                 0x1919c, 0x191b0,
2202                 0x191d0, 0x191e8,
2203                 0x19238, 0x19290,
2204                 0x192a4, 0x192b0,
2205                 0x192bc, 0x192bc,
2206                 0x19348, 0x1934c,
2207                 0x193f8, 0x19418,
2208                 0x19420, 0x19428,
2209                 0x19430, 0x19444,
2210                 0x1944c, 0x1946c,
2211                 0x19474, 0x19474,
2212                 0x19490, 0x194cc,
2213                 0x194f0, 0x194f8,
2214                 0x19c00, 0x19c48,
2215                 0x19c50, 0x19c80,
2216                 0x19c94, 0x19c98,
2217                 0x19ca0, 0x19cbc,
2218                 0x19ce4, 0x19ce4,
2219                 0x19cf0, 0x19cf8,
2220                 0x19d00, 0x19d28,
2221                 0x19d50, 0x19d78,
2222                 0x19d94, 0x19d98,
2223                 0x19da0, 0x19dc8,
2224                 0x19df0, 0x19e10,
2225                 0x19e50, 0x19e6c,
2226                 0x19ea0, 0x19ebc,
2227                 0x19ec4, 0x19ef4,
2228                 0x19f04, 0x19f2c,
2229                 0x19f34, 0x19f34,
2230                 0x19f40, 0x19f50,
2231                 0x19f90, 0x19fac,
2232                 0x19fc4, 0x19fc8,
2233                 0x19fd0, 0x19fe4,
2234                 0x1a000, 0x1a004,
2235                 0x1a010, 0x1a06c,
2236                 0x1a0b0, 0x1a0e4,
2237                 0x1a0ec, 0x1a0f8,
2238                 0x1a100, 0x1a108,
2239                 0x1a114, 0x1a130,
2240                 0x1a138, 0x1a1c4,
2241                 0x1a1fc, 0x1a1fc,
2242                 0x1e008, 0x1e00c,
2243                 0x1e040, 0x1e044,
2244                 0x1e04c, 0x1e04c,
2245                 0x1e284, 0x1e290,
2246                 0x1e2c0, 0x1e2c0,
2247                 0x1e2e0, 0x1e2e0,
2248                 0x1e300, 0x1e384,
2249                 0x1e3c0, 0x1e3c8,
2250                 0x1e408, 0x1e40c,
2251                 0x1e440, 0x1e444,
2252                 0x1e44c, 0x1e44c,
2253                 0x1e684, 0x1e690,
2254                 0x1e6c0, 0x1e6c0,
2255                 0x1e6e0, 0x1e6e0,
2256                 0x1e700, 0x1e784,
2257                 0x1e7c0, 0x1e7c8,
2258                 0x1e808, 0x1e80c,
2259                 0x1e840, 0x1e844,
2260                 0x1e84c, 0x1e84c,
2261                 0x1ea84, 0x1ea90,
2262                 0x1eac0, 0x1eac0,
2263                 0x1eae0, 0x1eae0,
2264                 0x1eb00, 0x1eb84,
2265                 0x1ebc0, 0x1ebc8,
2266                 0x1ec08, 0x1ec0c,
2267                 0x1ec40, 0x1ec44,
2268                 0x1ec4c, 0x1ec4c,
2269                 0x1ee84, 0x1ee90,
2270                 0x1eec0, 0x1eec0,
2271                 0x1eee0, 0x1eee0,
2272                 0x1ef00, 0x1ef84,
2273                 0x1efc0, 0x1efc8,
2274                 0x1f008, 0x1f00c,
2275                 0x1f040, 0x1f044,
2276                 0x1f04c, 0x1f04c,
2277                 0x1f284, 0x1f290,
2278                 0x1f2c0, 0x1f2c0,
2279                 0x1f2e0, 0x1f2e0,
2280                 0x1f300, 0x1f384,
2281                 0x1f3c0, 0x1f3c8,
2282                 0x1f408, 0x1f40c,
2283                 0x1f440, 0x1f444,
2284                 0x1f44c, 0x1f44c,
2285                 0x1f684, 0x1f690,
2286                 0x1f6c0, 0x1f6c0,
2287                 0x1f6e0, 0x1f6e0,
2288                 0x1f700, 0x1f784,
2289                 0x1f7c0, 0x1f7c8,
2290                 0x1f808, 0x1f80c,
2291                 0x1f840, 0x1f844,
2292                 0x1f84c, 0x1f84c,
2293                 0x1fa84, 0x1fa90,
2294                 0x1fac0, 0x1fac0,
2295                 0x1fae0, 0x1fae0,
2296                 0x1fb00, 0x1fb84,
2297                 0x1fbc0, 0x1fbc8,
2298                 0x1fc08, 0x1fc0c,
2299                 0x1fc40, 0x1fc44,
2300                 0x1fc4c, 0x1fc4c,
2301                 0x1fe84, 0x1fe90,
2302                 0x1fec0, 0x1fec0,
2303                 0x1fee0, 0x1fee0,
2304                 0x1ff00, 0x1ff84,
2305                 0x1ffc0, 0x1ffc8,
2306                 0x30000, 0x30030,
2307                 0x30100, 0x30168,
2308                 0x30190, 0x301a0,
2309                 0x301a8, 0x301b8,
2310                 0x301c4, 0x301c8,
2311                 0x301d0, 0x301d0,
2312                 0x30200, 0x30320,
2313                 0x30400, 0x304b4,
2314                 0x304c0, 0x3052c,
2315                 0x30540, 0x3061c,
2316                 0x30800, 0x308a0,
2317                 0x308c0, 0x30908,
2318                 0x30910, 0x309b8,
2319                 0x30a00, 0x30a04,
2320                 0x30a0c, 0x30a14,
2321                 0x30a1c, 0x30a2c,
2322                 0x30a44, 0x30a50,
2323                 0x30a74, 0x30a74,
2324                 0x30a7c, 0x30afc,
2325                 0x30b08, 0x30c24,
2326                 0x30d00, 0x30d14,
2327                 0x30d1c, 0x30d3c,
2328                 0x30d44, 0x30d4c,
2329                 0x30d54, 0x30d74,
2330                 0x30d7c, 0x30d7c,
2331                 0x30de0, 0x30de0,
2332                 0x30e00, 0x30ed4,
2333                 0x30f00, 0x30fa4,
2334                 0x30fc0, 0x30fc4,
2335                 0x31000, 0x31004,
2336                 0x31080, 0x310fc,
2337                 0x31208, 0x31220,
2338                 0x3123c, 0x31254,
2339                 0x31300, 0x31300,
2340                 0x31308, 0x3131c,
2341                 0x31338, 0x3133c,
2342                 0x31380, 0x31380,
2343                 0x31388, 0x313a8,
2344                 0x313b4, 0x313b4,
2345                 0x31400, 0x31420,
2346                 0x31438, 0x3143c,
2347                 0x31480, 0x31480,
2348                 0x314a8, 0x314a8,
2349                 0x314b0, 0x314b4,
2350                 0x314c8, 0x314d4,
2351                 0x31a40, 0x31a4c,
2352                 0x31af0, 0x31b20,
2353                 0x31b38, 0x31b3c,
2354                 0x31b80, 0x31b80,
2355                 0x31ba8, 0x31ba8,
2356                 0x31bb0, 0x31bb4,
2357                 0x31bc8, 0x31bd4,
2358                 0x32140, 0x3218c,
2359                 0x321f0, 0x321f4,
2360                 0x32200, 0x32200,
2361                 0x32218, 0x32218,
2362                 0x32400, 0x32400,
2363                 0x32408, 0x3241c,
2364                 0x32618, 0x32620,
2365                 0x32664, 0x32664,
2366                 0x326a8, 0x326a8,
2367                 0x326ec, 0x326ec,
2368                 0x32a00, 0x32abc,
2369                 0x32b00, 0x32b18,
2370                 0x32b20, 0x32b38,
2371                 0x32b40, 0x32b58,
2372                 0x32b60, 0x32b78,
2373                 0x32c00, 0x32c00,
2374                 0x32c08, 0x32c3c,
2375                 0x33000, 0x3302c,
2376                 0x33034, 0x33050,
2377                 0x33058, 0x33058,
2378                 0x33060, 0x3308c,
2379                 0x3309c, 0x330ac,
2380                 0x330c0, 0x330c0,
2381                 0x330c8, 0x330d0,
2382                 0x330d8, 0x330e0,
2383                 0x330ec, 0x3312c,
2384                 0x33134, 0x33150,
2385                 0x33158, 0x33158,
2386                 0x33160, 0x3318c,
2387                 0x3319c, 0x331ac,
2388                 0x331c0, 0x331c0,
2389                 0x331c8, 0x331d0,
2390                 0x331d8, 0x331e0,
2391                 0x331ec, 0x33290,
2392                 0x33298, 0x332c4,
2393                 0x332e4, 0x33390,
2394                 0x33398, 0x333c4,
2395                 0x333e4, 0x3342c,
2396                 0x33434, 0x33450,
2397                 0x33458, 0x33458,
2398                 0x33460, 0x3348c,
2399                 0x3349c, 0x334ac,
2400                 0x334c0, 0x334c0,
2401                 0x334c8, 0x334d0,
2402                 0x334d8, 0x334e0,
2403                 0x334ec, 0x3352c,
2404                 0x33534, 0x33550,
2405                 0x33558, 0x33558,
2406                 0x33560, 0x3358c,
2407                 0x3359c, 0x335ac,
2408                 0x335c0, 0x335c0,
2409                 0x335c8, 0x335d0,
2410                 0x335d8, 0x335e0,
2411                 0x335ec, 0x33690,
2412                 0x33698, 0x336c4,
2413                 0x336e4, 0x33790,
2414                 0x33798, 0x337c4,
2415                 0x337e4, 0x337fc,
2416                 0x33814, 0x33814,
2417                 0x33854, 0x33868,
2418                 0x33880, 0x3388c,
2419                 0x338c0, 0x338d0,
2420                 0x338e8, 0x338ec,
2421                 0x33900, 0x3392c,
2422                 0x33934, 0x33950,
2423                 0x33958, 0x33958,
2424                 0x33960, 0x3398c,
2425                 0x3399c, 0x339ac,
2426                 0x339c0, 0x339c0,
2427                 0x339c8, 0x339d0,
2428                 0x339d8, 0x339e0,
2429                 0x339ec, 0x33a90,
2430                 0x33a98, 0x33ac4,
2431                 0x33ae4, 0x33b10,
2432                 0x33b24, 0x33b28,
2433                 0x33b38, 0x33b50,
2434                 0x33bf0, 0x33c10,
2435                 0x33c24, 0x33c28,
2436                 0x33c38, 0x33c50,
2437                 0x33cf0, 0x33cfc,
2438                 0x34000, 0x34030,
2439                 0x34100, 0x34168,
2440                 0x34190, 0x341a0,
2441                 0x341a8, 0x341b8,
2442                 0x341c4, 0x341c8,
2443                 0x341d0, 0x341d0,
2444                 0x34200, 0x34320,
2445                 0x34400, 0x344b4,
2446                 0x344c0, 0x3452c,
2447                 0x34540, 0x3461c,
2448                 0x34800, 0x348a0,
2449                 0x348c0, 0x34908,
2450                 0x34910, 0x349b8,
2451                 0x34a00, 0x34a04,
2452                 0x34a0c, 0x34a14,
2453                 0x34a1c, 0x34a2c,
2454                 0x34a44, 0x34a50,
2455                 0x34a74, 0x34a74,
2456                 0x34a7c, 0x34afc,
2457                 0x34b08, 0x34c24,
2458                 0x34d00, 0x34d14,
2459                 0x34d1c, 0x34d3c,
2460                 0x34d44, 0x34d4c,
2461                 0x34d54, 0x34d74,
2462                 0x34d7c, 0x34d7c,
2463                 0x34de0, 0x34de0,
2464                 0x34e00, 0x34ed4,
2465                 0x34f00, 0x34fa4,
2466                 0x34fc0, 0x34fc4,
2467                 0x35000, 0x35004,
2468                 0x35080, 0x350fc,
2469                 0x35208, 0x35220,
2470                 0x3523c, 0x35254,
2471                 0x35300, 0x35300,
2472                 0x35308, 0x3531c,
2473                 0x35338, 0x3533c,
2474                 0x35380, 0x35380,
2475                 0x35388, 0x353a8,
2476                 0x353b4, 0x353b4,
2477                 0x35400, 0x35420,
2478                 0x35438, 0x3543c,
2479                 0x35480, 0x35480,
2480                 0x354a8, 0x354a8,
2481                 0x354b0, 0x354b4,
2482                 0x354c8, 0x354d4,
2483                 0x35a40, 0x35a4c,
2484                 0x35af0, 0x35b20,
2485                 0x35b38, 0x35b3c,
2486                 0x35b80, 0x35b80,
2487                 0x35ba8, 0x35ba8,
2488                 0x35bb0, 0x35bb4,
2489                 0x35bc8, 0x35bd4,
2490                 0x36140, 0x3618c,
2491                 0x361f0, 0x361f4,
2492                 0x36200, 0x36200,
2493                 0x36218, 0x36218,
2494                 0x36400, 0x36400,
2495                 0x36408, 0x3641c,
2496                 0x36618, 0x36620,
2497                 0x36664, 0x36664,
2498                 0x366a8, 0x366a8,
2499                 0x366ec, 0x366ec,
2500                 0x36a00, 0x36abc,
2501                 0x36b00, 0x36b18,
2502                 0x36b20, 0x36b38,
2503                 0x36b40, 0x36b58,
2504                 0x36b60, 0x36b78,
2505                 0x36c00, 0x36c00,
2506                 0x36c08, 0x36c3c,
2507                 0x37000, 0x3702c,
2508                 0x37034, 0x37050,
2509                 0x37058, 0x37058,
2510                 0x37060, 0x3708c,
2511                 0x3709c, 0x370ac,
2512                 0x370c0, 0x370c0,
2513                 0x370c8, 0x370d0,
2514                 0x370d8, 0x370e0,
2515                 0x370ec, 0x3712c,
2516                 0x37134, 0x37150,
2517                 0x37158, 0x37158,
2518                 0x37160, 0x3718c,
2519                 0x3719c, 0x371ac,
2520                 0x371c0, 0x371c0,
2521                 0x371c8, 0x371d0,
2522                 0x371d8, 0x371e0,
2523                 0x371ec, 0x37290,
2524                 0x37298, 0x372c4,
2525                 0x372e4, 0x37390,
2526                 0x37398, 0x373c4,
2527                 0x373e4, 0x3742c,
2528                 0x37434, 0x37450,
2529                 0x37458, 0x37458,
2530                 0x37460, 0x3748c,
2531                 0x3749c, 0x374ac,
2532                 0x374c0, 0x374c0,
2533                 0x374c8, 0x374d0,
2534                 0x374d8, 0x374e0,
2535                 0x374ec, 0x3752c,
2536                 0x37534, 0x37550,
2537                 0x37558, 0x37558,
2538                 0x37560, 0x3758c,
2539                 0x3759c, 0x375ac,
2540                 0x375c0, 0x375c0,
2541                 0x375c8, 0x375d0,
2542                 0x375d8, 0x375e0,
2543                 0x375ec, 0x37690,
2544                 0x37698, 0x376c4,
2545                 0x376e4, 0x37790,
2546                 0x37798, 0x377c4,
2547                 0x377e4, 0x377fc,
2548                 0x37814, 0x37814,
2549                 0x37854, 0x37868,
2550                 0x37880, 0x3788c,
2551                 0x378c0, 0x378d0,
2552                 0x378e8, 0x378ec,
2553                 0x37900, 0x3792c,
2554                 0x37934, 0x37950,
2555                 0x37958, 0x37958,
2556                 0x37960, 0x3798c,
2557                 0x3799c, 0x379ac,
2558                 0x379c0, 0x379c0,
2559                 0x379c8, 0x379d0,
2560                 0x379d8, 0x379e0,
2561                 0x379ec, 0x37a90,
2562                 0x37a98, 0x37ac4,
2563                 0x37ae4, 0x37b10,
2564                 0x37b24, 0x37b28,
2565                 0x37b38, 0x37b50,
2566                 0x37bf0, 0x37c10,
2567                 0x37c24, 0x37c28,
2568                 0x37c38, 0x37c50,
2569                 0x37cf0, 0x37cfc,
2570                 0x40040, 0x40040,
2571                 0x40080, 0x40084,
2572                 0x40100, 0x40100,
2573                 0x40140, 0x401bc,
2574                 0x40200, 0x40214,
2575                 0x40228, 0x40228,
2576                 0x40240, 0x40258,
2577                 0x40280, 0x40280,
2578                 0x40304, 0x40304,
2579                 0x40330, 0x4033c,
2580                 0x41304, 0x413c8,
2581                 0x413d0, 0x413dc,
2582                 0x413f0, 0x413f0,
2583                 0x41400, 0x4140c,
2584                 0x41414, 0x4141c,
2585                 0x41480, 0x414d0,
2586                 0x44000, 0x4407c,
2587                 0x440c0, 0x441ac,
2588                 0x441b4, 0x4427c,
2589                 0x442c0, 0x443ac,
2590                 0x443b4, 0x4447c,
2591                 0x444c0, 0x445ac,
2592                 0x445b4, 0x4467c,
2593                 0x446c0, 0x447ac,
2594                 0x447b4, 0x4487c,
2595                 0x448c0, 0x449ac,
2596                 0x449b4, 0x44a7c,
2597                 0x44ac0, 0x44bac,
2598                 0x44bb4, 0x44c7c,
2599                 0x44cc0, 0x44dac,
2600                 0x44db4, 0x44e7c,
2601                 0x44ec0, 0x44fac,
2602                 0x44fb4, 0x4507c,
2603                 0x450c0, 0x451ac,
2604                 0x451b4, 0x451fc,
2605                 0x45800, 0x45804,
2606                 0x45810, 0x45830,
2607                 0x45840, 0x45860,
2608                 0x45868, 0x45868,
2609                 0x45880, 0x45884,
2610                 0x458a0, 0x458b0,
2611                 0x45a00, 0x45a04,
2612                 0x45a10, 0x45a30,
2613                 0x45a40, 0x45a60,
2614                 0x45a68, 0x45a68,
2615                 0x45a80, 0x45a84,
2616                 0x45aa0, 0x45ab0,
2617                 0x460c0, 0x460e4,
2618                 0x47000, 0x4703c,
2619                 0x47044, 0x4708c,
2620                 0x47200, 0x47250,
2621                 0x47400, 0x47408,
2622                 0x47414, 0x47420,
2623                 0x47600, 0x47618,
2624                 0x47800, 0x47814,
2625                 0x47820, 0x4782c,
2626                 0x50000, 0x50084,
2627                 0x50090, 0x500cc,
2628                 0x50300, 0x50384,
2629                 0x50400, 0x50400,
2630                 0x50800, 0x50884,
2631                 0x50890, 0x508cc,
2632                 0x50b00, 0x50b84,
2633                 0x50c00, 0x50c00,
2634                 0x51000, 0x51020,
2635                 0x51028, 0x510b0,
2636                 0x51300, 0x51324,
2637         };
2638
2639         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2640         const unsigned int *reg_ranges;
2641         int reg_ranges_size, range;
2642         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2643
2644         /* Select the right set of register ranges to dump depending on the
2645          * adapter chip type.
2646          */
2647         switch (chip_version) {
2648         case CHELSIO_T4:
2649                 reg_ranges = t4_reg_ranges;
2650                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2651                 break;
2652
2653         case CHELSIO_T5:
2654                 reg_ranges = t5_reg_ranges;
2655                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2656                 break;
2657
2658         case CHELSIO_T6:
2659                 reg_ranges = t6_reg_ranges;
2660                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2661                 break;
2662
2663         default:
2664                 dev_err(adap->pdev_dev,
2665                         "Unsupported chip version %d\n", chip_version);
2666                 return;
2667         }
2668
2669         /* Clear the register buffer and insert the appropriate register
2670          * values selected by the above register ranges.
2671          */
2672         memset(buf, 0, buf_size);
2673         for (range = 0; range < reg_ranges_size; range += 2) {
2674                 unsigned int reg = reg_ranges[range];
2675                 unsigned int last_reg = reg_ranges[range + 1];
2676                 u32 *bufp = (u32 *)((char *)buf + reg);
2677
2678                 /* Iterate across the register range filling in the register
2679                  * buffer but don't write past the end of the register buffer.
2680                  */
2681                 while (reg <= last_reg && bufp < buf_end) {
2682                         *bufp++ = t4_read_reg(adap, reg);
2683                         reg += sizeof(u32);
2684                 }
2685         }
2686 }
2687
2688 #define EEPROM_STAT_ADDR   0x7bfc
2689 #define VPD_BASE           0x400
2690 #define VPD_BASE_OLD       0
2691 #define VPD_LEN            1024
2692 #define CHELSIO_VPD_UNIQUE_ID 0x82
2693
2694 /**
2695  * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2696  * @phys_addr: the physical EEPROM address
2697  * @fn: the PCI function number
2698  * @sz: size of function-specific area
2699  *
2700  * Translate a physical EEPROM address to virtual.  The first 1K is
2701  * accessed through virtual addresses starting at 31K, the rest is
2702  * accessed through virtual addresses starting at 0.
2703  *
2704  * The mapping is as follows:
2705  * [0..1K) -> [31K..32K)
2706  * [1K..1K+A) -> [31K-A..31K)
2707  * [1K+A..ES) -> [0..ES-A-1K)
2708  *
2709  * where A = @fn * @sz, and ES = EEPROM size.
2710  */
2711 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2712 {
2713         fn *= sz;
2714         if (phys_addr < 1024)
2715                 return phys_addr + (31 << 10);
2716         if (phys_addr < 1024 + fn)
2717                 return 31744 - fn + phys_addr - 1024;
2718         if (phys_addr < EEPROMSIZE)
2719                 return phys_addr - 1024 - fn;
2720         return -EINVAL;
2721 }
2722
2723 /**
2724  *      t4_seeprom_wp - enable/disable EEPROM write protection
2725  *      @adapter: the adapter
2726  *      @enable: whether to enable or disable write protection
2727  *
2728  *      Enables or disables write protection on the serial EEPROM.
2729  */
2730 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2731 {
2732         unsigned int v = enable ? 0xc : 0;
2733         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2734         return ret < 0 ? ret : 0;
2735 }
2736
2737 /**
2738  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2739  *      @adapter: adapter to read
2740  *      @p: where to store the parameters
2741  *
2742  *      Reads card parameters stored in VPD EEPROM.
2743  */
2744 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2745 {
2746         int i, ret = 0, addr;
2747         int ec, sn, pn, na;
2748         u8 *vpd, csum;
2749         unsigned int vpdr_len, kw_offset, id_len;
2750
2751         vpd = vmalloc(VPD_LEN);
2752         if (!vpd)
2753                 return -ENOMEM;
2754
2755         /* Card information normally starts at VPD_BASE but early cards had
2756          * it at 0.
2757          */
2758         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2759         if (ret < 0)
2760                 goto out;
2761
2762         /* The VPD shall have a unique identifier specified by the PCI SIG.
2763          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2764          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2765          * is expected to automatically put this entry at the
2766          * beginning of the VPD.
2767          */
2768         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2769
2770         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2771         if (ret < 0)
2772                 goto out;
2773
2774         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2775                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2776                 ret = -EINVAL;
2777                 goto out;
2778         }
2779
2780         id_len = pci_vpd_lrdt_size(vpd);
2781         if (id_len > ID_LEN)
2782                 id_len = ID_LEN;
2783
2784         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2785         if (i < 0) {
2786                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2787                 ret = -EINVAL;
2788                 goto out;
2789         }
2790
2791         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2792         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2793         if (vpdr_len + kw_offset > VPD_LEN) {
2794                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2795                 ret = -EINVAL;
2796                 goto out;
2797         }
2798
2799 #define FIND_VPD_KW(var, name) do { \
2800         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2801         if (var < 0) { \
2802                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2803                 ret = -EINVAL; \
2804                 goto out; \
2805         } \
2806         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2807 } while (0)
2808
2809         FIND_VPD_KW(i, "RV");
2810         for (csum = 0; i >= 0; i--)
2811                 csum += vpd[i];
2812
2813         if (csum) {
2814                 dev_err(adapter->pdev_dev,
2815                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2816                 ret = -EINVAL;
2817                 goto out;
2818         }
2819
2820         FIND_VPD_KW(ec, "EC");
2821         FIND_VPD_KW(sn, "SN");
2822         FIND_VPD_KW(pn, "PN");
2823         FIND_VPD_KW(na, "NA");
2824 #undef FIND_VPD_KW
2825
2826         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2827         strim(p->id);
2828         memcpy(p->ec, vpd + ec, EC_LEN);
2829         strim(p->ec);
2830         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2831         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2832         strim(p->sn);
2833         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2834         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2835         strim(p->pn);
2836         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2837         strim((char *)p->na);
2838
2839 out:
2840         vfree(vpd);
2841         return ret < 0 ? ret : 0;
2842 }
2843
2844 /**
2845  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2846  *      @adapter: adapter to read
2847  *      @p: where to store the parameters
2848  *
2849  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2850  *      Clock.  This can only be called after a connection to the firmware
2851  *      is established.
2852  */
2853 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2854 {
2855         u32 cclk_param, cclk_val;
2856         int ret;
2857
2858         /* Grab the raw VPD parameters.
2859          */
2860         ret = t4_get_raw_vpd_params(adapter, p);
2861         if (ret)
2862                 return ret;
2863
2864         /* Ask firmware for the Core Clock since it knows how to translate the
2865          * Reference Clock ('V2') VPD field into a Core Clock value ...
2866          */
2867         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2868                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2869         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2870                               1, &cclk_param, &cclk_val);
2871
2872         if (ret)
2873                 return ret;
2874         p->cclk = cclk_val;
2875
2876         return 0;
2877 }
2878
2879 /**
2880  *      t4_get_pfres - retrieve VF resource limits
2881  *      @adapter: the adapter
2882  *
2883  *      Retrieves configured resource limits and capabilities for a physical
2884  *      function.  The results are stored in @adapter->pfres.
2885  */
2886 int t4_get_pfres(struct adapter *adapter)
2887 {
2888         struct pf_resources *pfres = &adapter->params.pfres;
2889         struct fw_pfvf_cmd cmd, rpl;
2890         int v;
2891         u32 word;
2892
2893         /* Execute PFVF Read command to get VF resource limits; bail out early
2894          * with error on command failure.
2895          */
2896         memset(&cmd, 0, sizeof(cmd));
2897         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2898                                     FW_CMD_REQUEST_F |
2899                                     FW_CMD_READ_F |
2900                                     FW_PFVF_CMD_PFN_V(adapter->pf) |
2901                                     FW_PFVF_CMD_VFN_V(0));
2902         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2903         v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2904         if (v != FW_SUCCESS)
2905                 return v;
2906
2907         /* Extract PF resource limits and return success.
2908          */
2909         word = be32_to_cpu(rpl.niqflint_niq);
2910         pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2911         pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2912
2913         word = be32_to_cpu(rpl.type_to_neq);
2914         pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2915         pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2916
2917         word = be32_to_cpu(rpl.tc_to_nexactf);
2918         pfres->tc = FW_PFVF_CMD_TC_G(word);
2919         pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2920         pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2921
2922         word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2923         pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2924         pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2925         pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2926
2927         return 0;
2928 }
2929
2930 /* serial flash and firmware constants */
2931 enum {
2932         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2933
2934         /* flash command opcodes */
2935         SF_PROG_PAGE    = 2,          /* program page */
2936         SF_WR_DISABLE   = 4,          /* disable writes */
2937         SF_RD_STATUS    = 5,          /* read status register */
2938         SF_WR_ENABLE    = 6,          /* enable writes */
2939         SF_RD_DATA_FAST = 0xb,        /* read flash */
2940         SF_RD_ID        = 0x9f,       /* read ID */
2941         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2942 };
2943
2944 /**
2945  *      sf1_read - read data from the serial flash
2946  *      @adapter: the adapter
2947  *      @byte_cnt: number of bytes to read
2948  *      @cont: whether another operation will be chained
2949  *      @lock: whether to lock SF for PL access only
2950  *      @valp: where to store the read data
2951  *
2952  *      Reads up to 4 bytes of data from the serial flash.  The location of
2953  *      the read needs to be specified prior to calling this by issuing the
2954  *      appropriate commands to the serial flash.
2955  */
2956 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2957                     int lock, u32 *valp)
2958 {
2959         int ret;
2960
2961         if (!byte_cnt || byte_cnt > 4)
2962                 return -EINVAL;
2963         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2964                 return -EBUSY;
2965         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2966                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2967         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2968         if (!ret)
2969                 *valp = t4_read_reg(adapter, SF_DATA_A);
2970         return ret;
2971 }
2972
2973 /**
2974  *      sf1_write - write data to the serial flash
2975  *      @adapter: the adapter
2976  *      @byte_cnt: number of bytes to write
2977  *      @cont: whether another operation will be chained
2978  *      @lock: whether to lock SF for PL access only
2979  *      @val: value to write
2980  *
2981  *      Writes up to 4 bytes of data to the serial flash.  The location of
2982  *      the write needs to be specified prior to calling this by issuing the
2983  *      appropriate commands to the serial flash.
2984  */
2985 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2986                      int lock, u32 val)
2987 {
2988         if (!byte_cnt || byte_cnt > 4)
2989                 return -EINVAL;
2990         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2991                 return -EBUSY;
2992         t4_write_reg(adapter, SF_DATA_A, val);
2993         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2994                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2995         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2996 }
2997
2998 /**
2999  *      flash_wait_op - wait for a flash operation to complete
3000  *      @adapter: the adapter
3001  *      @attempts: max number of polls of the status register
3002  *      @delay: delay between polls in ms
3003  *
3004  *      Wait for a flash operation to complete by polling the status register.
3005  */
3006 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3007 {
3008         int ret;
3009         u32 status;
3010
3011         while (1) {
3012                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3013                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3014                         return ret;
3015                 if (!(status & 1))
3016                         return 0;
3017                 if (--attempts == 0)
3018                         return -EAGAIN;
3019                 if (delay)
3020                         msleep(delay);
3021         }
3022 }
3023
3024 /**
3025  *      t4_read_flash - read words from serial flash
3026  *      @adapter: the adapter
3027  *      @addr: the start address for the read
3028  *      @nwords: how many 32-bit words to read
3029  *      @data: where to store the read data
3030  *      @byte_oriented: whether to store data as bytes or as words
3031  *
3032  *      Read the specified number of 32-bit words from the serial flash.
3033  *      If @byte_oriented is set the read data is stored as a byte array
3034  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
3035  *      natural endianness.
3036  */
3037 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3038                   unsigned int nwords, u32 *data, int byte_oriented)
3039 {
3040         int ret;
3041
3042         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3043                 return -EINVAL;
3044
3045         addr = swab32(addr) | SF_RD_DATA_FAST;
3046
3047         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3048             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3049                 return ret;
3050
3051         for ( ; nwords; nwords--, data++) {
3052                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3053                 if (nwords == 1)
3054                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3055                 if (ret)
3056                         return ret;
3057                 if (byte_oriented)
3058                         *data = (__force __u32)(cpu_to_be32(*data));
3059         }
3060         return 0;
3061 }
3062
3063 /**
3064  *      t4_write_flash - write up to a page of data to the serial flash
3065  *      @adapter: the adapter
3066  *      @addr: the start address to write
3067  *      @n: length of data to write in bytes
3068  *      @data: the data to write
3069  *
3070  *      Writes up to a page of data (256 bytes) to the serial flash starting
3071  *      at the given address.  All the data must be written to the same page.
3072  */
3073 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3074                           unsigned int n, const u8 *data)
3075 {
3076         int ret;
3077         u32 buf[64];
3078         unsigned int i, c, left, val, offset = addr & 0xff;
3079
3080         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3081                 return -EINVAL;
3082
3083         val = swab32(addr) | SF_PROG_PAGE;
3084
3085         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3086             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3087                 goto unlock;
3088
3089         for (left = n; left; left -= c) {
3090                 c = min(left, 4U);
3091                 for (val = 0, i = 0; i < c; ++i)
3092                         val = (val << 8) + *data++;
3093
3094                 ret = sf1_write(adapter, c, c != left, 1, val);
3095                 if (ret)
3096                         goto unlock;
3097         }
3098         ret = flash_wait_op(adapter, 8, 1);
3099         if (ret)
3100                 goto unlock;
3101
3102         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3103
3104         /* Read the page to verify the write succeeded */
3105         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3106         if (ret)
3107                 return ret;
3108
3109         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3110                 dev_err(adapter->pdev_dev,
3111                         "failed to correctly write the flash page at %#x\n",
3112                         addr);
3113                 return -EIO;
3114         }
3115         return 0;
3116
3117 unlock:
3118         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3119         return ret;
3120 }
3121
3122 /**
3123  *      t4_get_fw_version - read the firmware version
3124  *      @adapter: the adapter
3125  *      @vers: where to place the version
3126  *
3127  *      Reads the FW version from flash.
3128  */
3129 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3130 {
3131         return t4_read_flash(adapter, FLASH_FW_START +
3132                              offsetof(struct fw_hdr, fw_ver), 1,
3133                              vers, 0);
3134 }
3135
3136 /**
3137  *      t4_get_bs_version - read the firmware bootstrap version
3138  *      @adapter: the adapter
3139  *      @vers: where to place the version
3140  *
3141  *      Reads the FW Bootstrap version from flash.
3142  */
3143 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3144 {
3145         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3146                              offsetof(struct fw_hdr, fw_ver), 1,
3147                              vers, 0);
3148 }
3149
3150 /**
3151  *      t4_get_tp_version - read the TP microcode version
3152  *      @adapter: the adapter
3153  *      @vers: where to place the version
3154  *
3155  *      Reads the TP microcode version from flash.
3156  */
3157 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3158 {
3159         return t4_read_flash(adapter, FLASH_FW_START +
3160                              offsetof(struct fw_hdr, tp_microcode_ver),
3161                              1, vers, 0);
3162 }
3163
3164 /**
3165  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3166  *      @adap: the adapter
3167  *      @vers: where to place the version
3168  *
3169  *      Reads the Expansion ROM header from FLASH and returns the version
3170  *      number (if present) through the @vers return value pointer.  We return
3171  *      this in the Firmware Version Format since it's convenient.  Return
3172  *      0 on success, -ENOENT if no Expansion ROM is present.
3173  */
3174 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3175 {
3176         struct exprom_header {
3177                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3178                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3179         } *hdr;
3180         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3181                                            sizeof(u32))];
3182         int ret;
3183
3184         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3185                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3186                             0);
3187         if (ret)
3188                 return ret;
3189
3190         hdr = (struct exprom_header *)exprom_header_buf;
3191         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3192                 return -ENOENT;
3193
3194         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3195                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3196                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3197                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3198         return 0;
3199 }
3200
3201 /**
3202  *      t4_get_vpd_version - return the VPD version
3203  *      @adapter: the adapter
3204  *      @vers: where to place the version
3205  *
3206  *      Reads the VPD via the Firmware interface (thus this can only be called
3207  *      once we're ready to issue Firmware commands).  The format of the
3208  *      VPD version is adapter specific.  Returns 0 on success, an error on
3209  *      failure.
3210  *
3211  *      Note that early versions of the Firmware didn't include the ability
3212  *      to retrieve the VPD version, so we zero-out the return-value parameter
3213  *      in that case to avoid leaving it with garbage in it.
3214  *
3215  *      Also note that the Firmware will return its cached copy of the VPD
3216  *      Revision ID, not the actual Revision ID as written in the Serial
3217  *      EEPROM.  This is only an issue if a new VPD has been written and the
3218  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3219  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3220  *      if the Host Driver will be performing a full adapter initialization.
3221  */
3222 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3223 {
3224         u32 vpdrev_param;
3225         int ret;
3226
3227         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3228                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3229         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3230                               1, &vpdrev_param, vers);
3231         if (ret)
3232                 *vers = 0;
3233         return ret;
3234 }
3235
3236 /**
3237  *      t4_get_scfg_version - return the Serial Configuration version
3238  *      @adapter: the adapter
3239  *      @vers: where to place the version
3240  *
3241  *      Reads the Serial Configuration Version via the Firmware interface
3242  *      (thus this can only be called once we're ready to issue Firmware
3243  *      commands).  The format of the Serial Configuration version is
3244  *      adapter specific.  Returns 0 on success, an error on failure.
3245  *
3246  *      Note that early versions of the Firmware didn't include the ability
3247  *      to retrieve the Serial Configuration version, so we zero-out the
3248  *      return-value parameter in that case to avoid leaving it with
3249  *      garbage in it.
3250  *
3251  *      Also note that the Firmware will return its cached copy of the Serial
3252  *      Initialization Revision ID, not the actual Revision ID as written in
3253  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3254  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3255  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3256  *      been issued if the Host Driver will be performing a full adapter
3257  *      initialization.
3258  */
3259 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3260 {
3261         u32 scfgrev_param;
3262         int ret;
3263
3264         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3265                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3266         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3267                               1, &scfgrev_param, vers);
3268         if (ret)
3269                 *vers = 0;
3270         return ret;
3271 }
3272
3273 /**
3274  *      t4_get_version_info - extract various chip/firmware version information
3275  *      @adapter: the adapter
3276  *
3277  *      Reads various chip/firmware version numbers and stores them into the
3278  *      adapter Adapter Parameters structure.  If any of the efforts fails
3279  *      the first failure will be returned, but all of the version numbers
3280  *      will be read.
3281  */
3282 int t4_get_version_info(struct adapter *adapter)
3283 {
3284         int ret = 0;
3285
3286         #define FIRST_RET(__getvinfo) \
3287         do { \
3288                 int __ret = __getvinfo; \
3289                 if (__ret && !ret) \
3290                         ret = __ret; \
3291         } while (0)
3292
3293         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3294         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3295         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3296         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3297         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3298         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3299
3300         #undef FIRST_RET
3301         return ret;
3302 }
3303
3304 /**
3305  *      t4_dump_version_info - dump all of the adapter configuration IDs
3306  *      @adapter: the adapter
3307  *
3308  *      Dumps all of the various bits of adapter configuration version/revision
3309  *      IDs information.  This is typically called at some point after
3310  *      t4_get_version_info() has been called.
3311  */
3312 void t4_dump_version_info(struct adapter *adapter)
3313 {
3314         /* Device information */
3315         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3316                  adapter->params.vpd.id,
3317                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3318         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3319                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3320
3321         /* Firmware Version */
3322         if (!adapter->params.fw_vers)
3323                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3324         else
3325                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3326                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3327                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3328                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3329                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3330
3331         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3332          * Firmware, so dev_info() is more appropriate here.)
3333          */
3334         if (!adapter->params.bs_vers)
3335                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3336         else
3337                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3338                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3339                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3340                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3341                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3342
3343         /* TP Microcode Version */
3344         if (!adapter->params.tp_vers)
3345                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3346         else
3347                 dev_info(adapter->pdev_dev,
3348                          "TP Microcode version: %u.%u.%u.%u\n",
3349                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3350                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3351                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3352                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3353
3354         /* Expansion ROM version */
3355         if (!adapter->params.er_vers)
3356                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3357         else
3358                 dev_info(adapter->pdev_dev,
3359                          "Expansion ROM version: %u.%u.%u.%u\n",
3360                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3361                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3362                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3363                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3364
3365         /* Serial Configuration version */
3366         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3367                  adapter->params.scfg_vers);
3368
3369         /* VPD Version */
3370         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3371                  adapter->params.vpd_vers);
3372 }
3373
3374 /**
3375  *      t4_check_fw_version - check if the FW is supported with this driver
3376  *      @adap: the adapter
3377  *
3378  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3379  *      if there's exact match, a negative error if the version could not be
3380  *      read or there's a major version mismatch
3381  */
3382 int t4_check_fw_version(struct adapter *adap)
3383 {
3384         int i, ret, major, minor, micro;
3385         int exp_major, exp_minor, exp_micro;
3386         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3387
3388         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3389         /* Try multiple times before returning error */
3390         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3391                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3392
3393         if (ret)
3394                 return ret;
3395
3396         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3397         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3398         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3399
3400         switch (chip_version) {
3401         case CHELSIO_T4:
3402                 exp_major = T4FW_MIN_VERSION_MAJOR;
3403                 exp_minor = T4FW_MIN_VERSION_MINOR;
3404                 exp_micro = T4FW_MIN_VERSION_MICRO;
3405                 break;
3406         case CHELSIO_T5:
3407                 exp_major = T5FW_MIN_VERSION_MAJOR;
3408                 exp_minor = T5FW_MIN_VERSION_MINOR;
3409                 exp_micro = T5FW_MIN_VERSION_MICRO;
3410                 break;
3411         case CHELSIO_T6:
3412                 exp_major = T6FW_MIN_VERSION_MAJOR;
3413                 exp_minor = T6FW_MIN_VERSION_MINOR;
3414                 exp_micro = T6FW_MIN_VERSION_MICRO;
3415                 break;
3416         default:
3417                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3418                         adap->chip);
3419                 return -EINVAL;
3420         }
3421
3422         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3423             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3424                 dev_err(adap->pdev_dev,
3425                         "Card has firmware version %u.%u.%u, minimum "
3426                         "supported firmware is %u.%u.%u.\n", major, minor,
3427                         micro, exp_major, exp_minor, exp_micro);
3428                 return -EFAULT;
3429         }
3430         return 0;
3431 }
3432
3433 /* Is the given firmware API compatible with the one the driver was compiled
3434  * with?
3435  */
3436 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3437 {
3438
3439         /* short circuit if it's the exact same firmware version */
3440         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3441                 return 1;
3442
3443 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3444         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3445             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3446                 return 1;
3447 #undef SAME_INTF
3448
3449         return 0;
3450 }
3451
3452 /* The firmware in the filesystem is usable, but should it be installed?
3453  * This routine explains itself in detail if it indicates the filesystem
3454  * firmware should be installed.
3455  */
3456 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3457                                 int k, int c)
3458 {
3459         const char *reason;
3460
3461         if (!card_fw_usable) {
3462                 reason = "incompatible or unusable";
3463                 goto install;
3464         }
3465
3466         if (k > c) {
3467                 reason = "older than the version supported with this driver";
3468                 goto install;
3469         }
3470
3471         return 0;
3472
3473 install:
3474         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3475                 "installing firmware %u.%u.%u.%u on card.\n",
3476                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3477                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3478                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3479                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3480
3481         return 1;
3482 }
3483
3484 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3485                const u8 *fw_data, unsigned int fw_size,
3486                struct fw_hdr *card_fw, enum dev_state state,
3487                int *reset)
3488 {
3489         int ret, card_fw_usable, fs_fw_usable;
3490         const struct fw_hdr *fs_fw;
3491         const struct fw_hdr *drv_fw;
3492
3493         drv_fw = &fw_info->fw_hdr;
3494
3495         /* Read the header of the firmware on the card */
3496         ret = t4_read_flash(adap, FLASH_FW_START,
3497                             sizeof(*card_fw) / sizeof(uint32_t),
3498                             (uint32_t *)card_fw, 1);
3499         if (ret == 0) {
3500                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3501         } else {
3502                 dev_err(adap->pdev_dev,
3503                         "Unable to read card's firmware header: %d\n", ret);
3504                 card_fw_usable = 0;
3505         }
3506
3507         if (fw_data != NULL) {
3508                 fs_fw = (const void *)fw_data;
3509                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3510         } else {
3511                 fs_fw = NULL;
3512                 fs_fw_usable = 0;
3513         }
3514
3515         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3516             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3517                 /* Common case: the firmware on the card is an exact match and
3518                  * the filesystem one is an exact match too, or the filesystem
3519                  * one is absent/incompatible.
3520                  */
3521         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3522                    should_install_fs_fw(adap, card_fw_usable,
3523                                         be32_to_cpu(fs_fw->fw_ver),
3524                                         be32_to_cpu(card_fw->fw_ver))) {
3525                 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3526                                     fw_size, 0);
3527                 if (ret != 0) {
3528                         dev_err(adap->pdev_dev,
3529                                 "failed to install firmware: %d\n", ret);
3530                         goto bye;
3531                 }
3532
3533                 /* Installed successfully, update the cached header too. */
3534                 *card_fw = *fs_fw;
3535                 card_fw_usable = 1;
3536                 *reset = 0;     /* already reset as part of load_fw */
3537         }
3538
3539         if (!card_fw_usable) {
3540                 uint32_t d, c, k;
3541
3542                 d = be32_to_cpu(drv_fw->fw_ver);
3543                 c = be32_to_cpu(card_fw->fw_ver);
3544                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3545
3546                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3547                         "chip state %d, "
3548                         "driver compiled with %d.%d.%d.%d, "
3549                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3550                         state,
3551                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3552                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3553                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3554                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3555                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3556                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3557                 ret = -EINVAL;
3558                 goto bye;
3559         }
3560
3561         /* We're using whatever's on the card and it's known to be good. */
3562         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3563         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3564
3565 bye:
3566         return ret;
3567 }
3568
3569 /**
3570  *      t4_flash_erase_sectors - erase a range of flash sectors
3571  *      @adapter: the adapter
3572  *      @start: the first sector to erase
3573  *      @end: the last sector to erase
3574  *
3575  *      Erases the sectors in the given inclusive range.
3576  */
3577 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3578 {
3579         int ret = 0;
3580
3581         if (end >= adapter->params.sf_nsec)
3582                 return -EINVAL;
3583
3584         while (start <= end) {
3585                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3586                     (ret = sf1_write(adapter, 4, 0, 1,
3587                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3588                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3589                         dev_err(adapter->pdev_dev,
3590                                 "erase of flash sector %d failed, error %d\n",
3591                                 start, ret);
3592                         break;
3593                 }
3594                 start++;
3595         }
3596         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3597         return ret;
3598 }
3599
3600 /**
3601  *      t4_flash_cfg_addr - return the address of the flash configuration file
3602  *      @adapter: the adapter
3603  *
3604  *      Return the address within the flash where the Firmware Configuration
3605  *      File is stored.
3606  */
3607 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3608 {
3609         if (adapter->params.sf_size == 0x100000)
3610                 return FLASH_FPGA_CFG_START;
3611         else
3612                 return FLASH_CFG_START;
3613 }
3614
3615 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3616  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3617  * and emit an error message for mismatched firmware to save our caller the
3618  * effort ...
3619  */
3620 static bool t4_fw_matches_chip(const struct adapter *adap,
3621                                const struct fw_hdr *hdr)
3622 {
3623         /* The expression below will return FALSE for any unsupported adapter
3624          * which will keep us "honest" in the future ...
3625          */
3626         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3627             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3628             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3629                 return true;
3630
3631         dev_err(adap->pdev_dev,
3632                 "FW image (%d) is not suitable for this adapter (%d)\n",
3633                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3634         return false;
3635 }
3636
3637 /**
3638  *      t4_load_fw - download firmware
3639  *      @adap: the adapter
3640  *      @fw_data: the firmware image to write
3641  *      @size: image size
3642  *
3643  *      Write the supplied firmware image to the card's serial flash.
3644  */
3645 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3646 {
3647         u32 csum;
3648         int ret, addr;
3649         unsigned int i;
3650         u8 first_page[SF_PAGE_SIZE];
3651         const __be32 *p = (const __be32 *)fw_data;
3652         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3653         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3654         unsigned int fw_start_sec = FLASH_FW_START_SEC;
3655         unsigned int fw_size = FLASH_FW_MAX_SIZE;
3656         unsigned int fw_start = FLASH_FW_START;
3657
3658         if (!size) {
3659                 dev_err(adap->pdev_dev, "FW image has no data\n");
3660                 return -EINVAL;
3661         }
3662         if (size & 511) {
3663                 dev_err(adap->pdev_dev,
3664                         "FW image size not multiple of 512 bytes\n");
3665                 return -EINVAL;
3666         }
3667         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3668                 dev_err(adap->pdev_dev,
3669                         "FW image size differs from size in FW header\n");
3670                 return -EINVAL;
3671         }
3672         if (size > fw_size) {
3673                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3674                         fw_size);
3675                 return -EFBIG;
3676         }
3677         if (!t4_fw_matches_chip(adap, hdr))
3678                 return -EINVAL;
3679
3680         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3681                 csum += be32_to_cpu(p[i]);
3682
3683         if (csum != 0xffffffff) {
3684                 dev_err(adap->pdev_dev,
3685                         "corrupted firmware image, checksum %#x\n", csum);
3686                 return -EINVAL;
3687         }
3688
3689         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3690         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3691         if (ret)
3692                 goto out;
3693
3694         /*
3695          * We write the correct version at the end so the driver can see a bad
3696          * version if the FW write fails.  Start by writing a copy of the
3697          * first page with a bad version.
3698          */
3699         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3700         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3701         ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page);
3702         if (ret)
3703                 goto out;
3704
3705         addr = fw_start;
3706         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3707                 addr += SF_PAGE_SIZE;
3708                 fw_data += SF_PAGE_SIZE;
3709                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3710                 if (ret)
3711                         goto out;
3712         }
3713
3714         ret = t4_write_flash(adap,
3715                              fw_start + offsetof(struct fw_hdr, fw_ver),
3716                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3717 out:
3718         if (ret)
3719                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3720                         ret);
3721         else
3722                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3723         return ret;
3724 }
3725
3726 /**
3727  *      t4_phy_fw_ver - return current PHY firmware version
3728  *      @adap: the adapter
3729  *      @phy_fw_ver: return value buffer for PHY firmware version
3730  *
3731  *      Returns the current version of external PHY firmware on the
3732  *      adapter.
3733  */
3734 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3735 {
3736         u32 param, val;
3737         int ret;
3738
3739         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3740                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3741                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3742                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3743         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3744                               &param, &val);
3745         if (ret)
3746                 return ret;
3747         *phy_fw_ver = val;
3748         return 0;
3749 }
3750
3751 /**
3752  *      t4_load_phy_fw - download port PHY firmware
3753  *      @adap: the adapter
3754  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3755  *      @phy_fw_version: function to check PHY firmware versions
3756  *      @phy_fw_data: the PHY firmware image to write
3757  *      @phy_fw_size: image size
3758  *
3759  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3760  *      @phy_fw_version is supplied, then it will be used to determine if
3761  *      it's necessary to perform the transfer by comparing the version
3762  *      of any existing adapter PHY firmware with that of the passed in
3763  *      PHY firmware image.
3764  *
3765  *      A negative error number will be returned if an error occurs.  If
3766  *      version number support is available and there's no need to upgrade
3767  *      the firmware, 0 will be returned.  If firmware is successfully
3768  *      transferred to the adapter, 1 will be returned.
3769  *
3770  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3771  *      a result, a RESET of the adapter would cause that RAM to lose its
3772  *      contents.  Thus, loading PHY firmware on such adapters must happen
3773  *      after any FW_RESET_CMDs ...
3774  */
3775 int t4_load_phy_fw(struct adapter *adap, int win,
3776                    int (*phy_fw_version)(const u8 *, size_t),
3777                    const u8 *phy_fw_data, size_t phy_fw_size)
3778 {
3779         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3780         unsigned long mtype = 0, maddr = 0;
3781         u32 param, val;
3782         int ret;
3783
3784         /* If we have version number support, then check to see if the adapter
3785          * already has up-to-date PHY firmware loaded.
3786          */
3787         if (phy_fw_version) {
3788                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3789                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3790                 if (ret < 0)
3791                         return ret;
3792
3793                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3794                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3795                                 "version %#x\n", cur_phy_fw_ver);
3796                         return 0;
3797                 }
3798         }
3799
3800         /* Ask the firmware where it wants us to copy the PHY firmware image.
3801          * The size of the file requires a special version of the READ command
3802          * which will pass the file size via the values field in PARAMS_CMD and
3803          * retrieve the return value from firmware and place it in the same
3804          * buffer values
3805          */
3806         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3807                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3808                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3809                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3810         val = phy_fw_size;
3811         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3812                                  &param, &val, 1, true);
3813         if (ret < 0)
3814                 return ret;
3815         mtype = val >> 8;
3816         maddr = (val & 0xff) << 16;
3817
3818         /* Copy the supplied PHY Firmware image to the adapter memory location
3819          * allocated by the adapter firmware.
3820          */
3821         ret = t4_memory_rw(adap, win, mtype, maddr,
3822                            phy_fw_size, (__be32 *)phy_fw_data,
3823                            T4_MEMORY_WRITE);
3824         if (ret)
3825                 return ret;
3826
3827         /* Tell the firmware that the PHY firmware image has been written to
3828          * RAM and it can now start copying it over to the PHYs.  The chip
3829          * firmware will RESET the affected PHYs as part of this operation
3830          * leaving them running the new PHY firmware image.
3831          */
3832         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3833                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3834                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3835                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3836         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3837                                     &param, &val, 30000);
3838
3839         /* If we have version number support, then check to see that the new
3840          * firmware got loaded properly.
3841          */
3842         if (phy_fw_version) {
3843                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3844                 if (ret < 0)
3845                         return ret;
3846
3847                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3848                         CH_WARN(adap, "PHY Firmware did not update: "
3849                                 "version on adapter %#x, "
3850                                 "version flashed %#x\n",
3851                                 cur_phy_fw_ver, new_phy_fw_vers);
3852                         return -ENXIO;
3853                 }
3854         }
3855
3856         return 1;
3857 }
3858
3859 /**
3860  *      t4_fwcache - firmware cache operation
3861  *      @adap: the adapter
3862  *      @op  : the operation (flush or flush and invalidate)
3863  */
3864 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3865 {
3866         struct fw_params_cmd c;
3867
3868         memset(&c, 0, sizeof(c));
3869         c.op_to_vfn =
3870                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3871                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3872                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3873                             FW_PARAMS_CMD_VFN_V(0));
3874         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3875         c.param[0].mnem =
3876                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3877                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3878         c.param[0].val = cpu_to_be32(op);
3879
3880         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3881 }
3882
3883 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3884                         unsigned int *pif_req_wrptr,
3885                         unsigned int *pif_rsp_wrptr)
3886 {
3887         int i, j;
3888         u32 cfg, val, req, rsp;
3889
3890         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3891         if (cfg & LADBGEN_F)
3892                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3893
3894         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3895         req = POLADBGWRPTR_G(val);
3896         rsp = PILADBGWRPTR_G(val);
3897         if (pif_req_wrptr)
3898                 *pif_req_wrptr = req;
3899         if (pif_rsp_wrptr)
3900                 *pif_rsp_wrptr = rsp;
3901
3902         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3903                 for (j = 0; j < 6; j++) {
3904                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3905                                      PILADBGRDPTR_V(rsp));
3906                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3907                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3908                         req++;
3909                         rsp++;
3910                 }
3911                 req = (req + 2) & POLADBGRDPTR_M;
3912                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3913         }
3914         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3915 }
3916
3917 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3918 {
3919         u32 cfg;
3920         int i, j, idx;
3921
3922         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3923         if (cfg & LADBGEN_F)
3924                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3925
3926         for (i = 0; i < CIM_MALA_SIZE; i++) {
3927                 for (j = 0; j < 5; j++) {
3928                         idx = 8 * i + j;
3929                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3930                                      PILADBGRDPTR_V(idx));
3931                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3932                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3933                 }
3934         }
3935         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3936 }
3937
3938 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3939 {
3940         unsigned int i, j;
3941
3942         for (i = 0; i < 8; i++) {
3943                 u32 *p = la_buf + i;
3944
3945                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3946                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3947                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3948                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3949                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3950         }
3951 }
3952
3953 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3954  * Capabilities which we control with separate controls -- see, for instance,
3955  * Pause Frames and Forward Error Correction.  In order to determine what the
3956  * full set of Advertised Port Capabilities are, the base Advertised Port
3957  * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3958  * Port Capabilities associated with those other controls.  See
3959  * t4_link_acaps() for how this is done.
3960  */
3961 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3962                      FW_PORT_CAP32_ANEG)
3963
3964 /**
3965  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3966  *      @caps16: a 16-bit Port Capabilities value
3967  *
3968  *      Returns the equivalent 32-bit Port Capabilities value.
3969  */
3970 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3971 {
3972         fw_port_cap32_t caps32 = 0;
3973
3974         #define CAP16_TO_CAP32(__cap) \
3975                 do { \
3976                         if (caps16 & FW_PORT_CAP_##__cap) \
3977                                 caps32 |= FW_PORT_CAP32_##__cap; \
3978                 } while (0)
3979
3980         CAP16_TO_CAP32(SPEED_100M);
3981         CAP16_TO_CAP32(SPEED_1G);
3982         CAP16_TO_CAP32(SPEED_25G);
3983         CAP16_TO_CAP32(SPEED_10G);
3984         CAP16_TO_CAP32(SPEED_40G);
3985         CAP16_TO_CAP32(SPEED_100G);
3986         CAP16_TO_CAP32(FC_RX);
3987         CAP16_TO_CAP32(FC_TX);
3988         CAP16_TO_CAP32(ANEG);
3989         CAP16_TO_CAP32(FORCE_PAUSE);
3990         CAP16_TO_CAP32(MDIAUTO);
3991         CAP16_TO_CAP32(MDISTRAIGHT);
3992         CAP16_TO_CAP32(FEC_RS);
3993         CAP16_TO_CAP32(FEC_BASER_RS);
3994         CAP16_TO_CAP32(802_3_PAUSE);
3995         CAP16_TO_CAP32(802_3_ASM_DIR);
3996
3997         #undef CAP16_TO_CAP32
3998
3999         return caps32;
4000 }
4001
4002 /**
4003  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4004  *      @caps32: a 32-bit Port Capabilities value
4005  *
4006  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
4007  *      not all 32-bit Port Capabilities can be represented in the 16-bit
4008  *      Port Capabilities and some fields/values may not make it.
4009  */
4010 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4011 {
4012         fw_port_cap16_t caps16 = 0;
4013
4014         #define CAP32_TO_CAP16(__cap) \
4015                 do { \
4016                         if (caps32 & FW_PORT_CAP32_##__cap) \
4017                                 caps16 |= FW_PORT_CAP_##__cap; \
4018                 } while (0)
4019
4020         CAP32_TO_CAP16(SPEED_100M);
4021         CAP32_TO_CAP16(SPEED_1G);
4022         CAP32_TO_CAP16(SPEED_10G);
4023         CAP32_TO_CAP16(SPEED_25G);
4024         CAP32_TO_CAP16(SPEED_40G);
4025         CAP32_TO_CAP16(SPEED_100G);
4026         CAP32_TO_CAP16(FC_RX);
4027         CAP32_TO_CAP16(FC_TX);
4028         CAP32_TO_CAP16(802_3_PAUSE);
4029         CAP32_TO_CAP16(802_3_ASM_DIR);
4030         CAP32_TO_CAP16(ANEG);
4031         CAP32_TO_CAP16(FORCE_PAUSE);
4032         CAP32_TO_CAP16(MDIAUTO);
4033         CAP32_TO_CAP16(MDISTRAIGHT);
4034         CAP32_TO_CAP16(FEC_RS);
4035         CAP32_TO_CAP16(FEC_BASER_RS);
4036
4037         #undef CAP32_TO_CAP16
4038
4039         return caps16;
4040 }
4041
4042 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4043 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4044 {
4045         enum cc_pause cc_pause = 0;
4046
4047         if (fw_pause & FW_PORT_CAP32_FC_RX)
4048                 cc_pause |= PAUSE_RX;
4049         if (fw_pause & FW_PORT_CAP32_FC_TX)
4050                 cc_pause |= PAUSE_TX;
4051
4052         return cc_pause;
4053 }
4054
4055 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4056 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4057 {
4058         /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4059          * commands, etc.
4060          */
4061         fw_port_cap32_t fw_pause = 0;
4062
4063         if (cc_pause & PAUSE_RX)
4064                 fw_pause |= FW_PORT_CAP32_FC_RX;
4065         if (cc_pause & PAUSE_TX)
4066                 fw_pause |= FW_PORT_CAP32_FC_TX;
4067         if (!(cc_pause & PAUSE_AUTONEG))
4068                 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4069
4070         /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4071          * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4072          * Note that these bits are ignored in L1 Configure commands.
4073          */
4074         if (cc_pause & PAUSE_RX) {
4075                 if (cc_pause & PAUSE_TX)
4076                         fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4077                 else
4078                         fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4079                                     FW_PORT_CAP32_802_3_PAUSE;
4080         } else if (cc_pause & PAUSE_TX) {
4081                 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4082         }
4083
4084         return fw_pause;
4085 }
4086
4087 /* Translate Firmware Forward Error Correction specification to Common Code */
4088 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4089 {
4090         enum cc_fec cc_fec = 0;
4091
4092         if (fw_fec & FW_PORT_CAP32_FEC_RS)
4093                 cc_fec |= FEC_RS;
4094         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4095                 cc_fec |= FEC_BASER_RS;
4096
4097         return cc_fec;
4098 }
4099
4100 /* Translate Common Code Forward Error Correction specification to Firmware */
4101 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4102 {
4103         fw_port_cap32_t fw_fec = 0;
4104
4105         if (cc_fec & FEC_RS)
4106                 fw_fec |= FW_PORT_CAP32_FEC_RS;
4107         if (cc_fec & FEC_BASER_RS)
4108                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4109
4110         return fw_fec;
4111 }
4112
4113 /**
4114  *      t4_link_acaps - compute Link Advertised Port Capabilities
4115  *      @adapter: the adapter
4116  *      @port: the Port ID
4117  *      @lc: the Port's Link Configuration
4118  *
4119  *      Synthesize the Advertised Port Capabilities we'll be using based on
4120  *      the base Advertised Port Capabilities (which have been filtered by
4121  *      ADVERT_MASK) plus the individual controls for things like Pause
4122  *      Frames, Forward Error Correction, MDI, etc.
4123  */
4124 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4125                               struct link_config *lc)
4126 {
4127         fw_port_cap32_t fw_fc, fw_fec, acaps;
4128         unsigned int fw_mdi;
4129         char cc_fec;
4130
4131         fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4132
4133         /* Convert driver coding of Pause Frame Flow Control settings into the
4134          * Firmware's API.
4135          */
4136         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4137
4138         /* Convert Common Code Forward Error Control settings into the
4139          * Firmware's API.  If the current Requested FEC has "Automatic"
4140          * (IEEE 802.3) specified, then we use whatever the Firmware
4141          * sent us as part of its IEEE 802.3-based interpretation of
4142          * the Transceiver Module EPROM FEC parameters.  Otherwise we
4143          * use whatever is in the current Requested FEC settings.
4144          */
4145         if (lc->requested_fec & FEC_AUTO)
4146                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4147         else
4148                 cc_fec = lc->requested_fec;
4149         fw_fec = cc_to_fwcap_fec(cc_fec);
4150
4151         /* Figure out what our Requested Port Capabilities are going to be.
4152          * Note parallel structure in t4_handle_get_port_info() and
4153          * init_link_config().
4154          */
4155         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4156                 acaps = lc->acaps | fw_fc | fw_fec;
4157                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4158                 lc->fec = cc_fec;
4159         } else if (lc->autoneg == AUTONEG_DISABLE) {
4160                 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4161                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4162                 lc->fec = cc_fec;
4163         } else {
4164                 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4165         }
4166
4167         /* Some Requested Port Capabilities are trivially wrong if they exceed
4168          * the Physical Port Capabilities.  We can check that here and provide
4169          * moderately useful feedback in the system log.
4170          *
4171          * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4172          * we need to exclude this from this check in order to maintain
4173          * compatibility ...
4174          */
4175         if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4176                 dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4177                         acaps, lc->pcaps);
4178                 return -EINVAL;
4179         }
4180
4181         return acaps;
4182 }
4183
4184 /**
4185  *      t4_link_l1cfg_core - apply link configuration to MAC/PHY
4186  *      @adapter: the adapter
4187  *      @mbox: the Firmware Mailbox to use
4188  *      @port: the Port ID
4189  *      @lc: the Port's Link Configuration
4190  *      @sleep_ok: if true we may sleep while awaiting command completion
4191  *      @timeout: time to wait for command to finish before timing out
4192  *              (negative implies @sleep_ok=false)
4193  *
4194  *      Set up a port's MAC and PHY according to a desired link configuration.
4195  *      - If the PHY can auto-negotiate first decide what to advertise, then
4196  *        enable/disable auto-negotiation as desired, and reset.
4197  *      - If the PHY does not auto-negotiate just reset it.
4198  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4199  *        otherwise do it later based on the outcome of auto-negotiation.
4200  */
4201 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4202                        unsigned int port, struct link_config *lc,
4203                        u8 sleep_ok, int timeout)
4204 {
4205         unsigned int fw_caps = adapter->params.fw_caps_support;
4206         struct fw_port_cmd cmd;
4207         fw_port_cap32_t rcap;
4208         int ret;
4209
4210         if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4211             lc->autoneg == AUTONEG_ENABLE) {
4212                 return -EINVAL;
4213         }
4214
4215         /* Compute our Requested Port Capabilities and send that on to the
4216          * Firmware.
4217          */
4218         rcap = t4_link_acaps(adapter, port, lc);
4219         memset(&cmd, 0, sizeof(cmd));
4220         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4221                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4222                                        FW_PORT_CMD_PORTID_V(port));
4223         cmd.action_to_len16 =
4224                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4225                                                  ? FW_PORT_ACTION_L1_CFG
4226                                                  : FW_PORT_ACTION_L1_CFG32) |
4227                                                  FW_LEN16(cmd));
4228         if (fw_caps == FW_CAPS16)
4229                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4230         else
4231                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4232
4233         ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4234                                       sleep_ok, timeout);
4235
4236         /* Unfortunately, even if the Requested Port Capabilities "fit" within
4237          * the Physical Port Capabilities, some combinations of features may
4238          * still not be legal.  For example, 40Gb/s and Reed-Solomon Forward
4239          * Error Correction.  So if the Firmware rejects the L1 Configure
4240          * request, flag that here.
4241          */
4242         if (ret) {
4243                 dev_err(adapter->pdev_dev,
4244                         "Requested Port Capabilities %#x rejected, error %d\n",
4245                         rcap, -ret);
4246                 return ret;
4247         }
4248         return 0;
4249 }
4250
4251 /**
4252  *      t4_restart_aneg - restart autonegotiation
4253  *      @adap: the adapter
4254  *      @mbox: mbox to use for the FW command
4255  *      @port: the port id
4256  *
4257  *      Restarts autonegotiation for the selected port.
4258  */
4259 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4260 {
4261         unsigned int fw_caps = adap->params.fw_caps_support;
4262         struct fw_port_cmd c;
4263
4264         memset(&c, 0, sizeof(c));
4265         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4266                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4267                                      FW_PORT_CMD_PORTID_V(port));
4268         c.action_to_len16 =
4269                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4270                                                  ? FW_PORT_ACTION_L1_CFG
4271                                                  : FW_PORT_ACTION_L1_CFG32) |
4272                             FW_LEN16(c));
4273         if (fw_caps == FW_CAPS16)
4274                 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4275         else
4276                 c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4277         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4278 }
4279
4280 typedef void (*int_handler_t)(struct adapter *adap);
4281
4282 struct intr_info {
4283         unsigned int mask;       /* bits to check in interrupt status */
4284         const char *msg;         /* message to print or NULL */
4285         short stat_idx;          /* stat counter to increment or -1 */
4286         unsigned short fatal;    /* whether the condition reported is fatal */
4287         int_handler_t int_handler; /* platform-specific int handler */
4288 };
4289
4290 /**
4291  *      t4_handle_intr_status - table driven interrupt handler
4292  *      @adapter: the adapter that generated the interrupt
4293  *      @reg: the interrupt status register to process
4294  *      @acts: table of interrupt actions
4295  *
4296  *      A table driven interrupt handler that applies a set of masks to an
4297  *      interrupt status word and performs the corresponding actions if the
4298  *      interrupts described by the mask have occurred.  The actions include
4299  *      optionally emitting a warning or alert message.  The table is terminated
4300  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4301  *      conditions.
4302  */
4303 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4304                                  const struct intr_info *acts)
4305 {
4306         int fatal = 0;
4307         unsigned int mask = 0;
4308         unsigned int status = t4_read_reg(adapter, reg);
4309
4310         for ( ; acts->mask; ++acts) {
4311                 if (!(status & acts->mask))
4312                         continue;
4313                 if (acts->fatal) {
4314                         fatal++;
4315                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4316                                   status & acts->mask);
4317                 } else if (acts->msg && printk_ratelimit())
4318                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4319                                  status & acts->mask);
4320                 if (acts->int_handler)
4321                         acts->int_handler(adapter);
4322                 mask |= acts->mask;
4323         }
4324         status &= mask;
4325         if (status)                           /* clear processed interrupts */
4326                 t4_write_reg(adapter, reg, status);
4327         return fatal;
4328 }
4329
4330 /*
4331  * Interrupt handler for the PCIE module.
4332  */
4333 static void pcie_intr_handler(struct adapter *adapter)
4334 {
4335         static const struct intr_info sysbus_intr_info[] = {
4336                 { RNPP_F, "RXNP array parity error", -1, 1 },
4337                 { RPCP_F, "RXPC array parity error", -1, 1 },
4338                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4339                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4340                 { RFTP_F, "RXFT array parity error", -1, 1 },
4341                 { 0 }
4342         };
4343         static const struct intr_info pcie_port_intr_info[] = {
4344                 { TPCP_F, "TXPC array parity error", -1, 1 },
4345                 { TNPP_F, "TXNP array parity error", -1, 1 },
4346                 { TFTP_F, "TXFT array parity error", -1, 1 },
4347                 { TCAP_F, "TXCA array parity error", -1, 1 },
4348                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4349                 { RCAP_F, "RXCA array parity error", -1, 1 },
4350                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4351                 { RDPE_F, "Rx data parity error", -1, 1 },
4352                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4353                 { 0 }
4354         };
4355         static const struct intr_info pcie_intr_info[] = {
4356                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4357                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4358                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4359                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4360                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4361                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4362                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4363                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4364                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4365                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4366                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4367                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4368                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4369                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4370                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4371                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4372                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4373                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4374                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4375                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4376                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4377                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4378                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4379                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4380                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4381                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4382                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4383                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4384                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4385                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4386                   -1, 0 },
4387                 { 0 }
4388         };
4389
4390         static struct intr_info t5_pcie_intr_info[] = {
4391                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4392                   -1, 1 },
4393                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4394                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4395                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4396                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4397                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4398                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4399                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4400                   -1, 1 },
4401                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4402                   -1, 1 },
4403                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4404                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4405                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4406                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4407                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4408                   -1, 1 },
4409                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4410                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4411                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4412                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4413                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4414                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4415                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4416                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4417                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4418                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4419                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4420                   -1, 1 },
4421                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4422                   -1, 1 },
4423                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4424                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4425                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4426                 { READRSPERR_F, "Outbound read error", -1, 0 },
4427                 { 0 }
4428         };
4429
4430         int fat;
4431
4432         if (is_t4(adapter->params.chip))
4433                 fat = t4_handle_intr_status(adapter,
4434                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4435                                 sysbus_intr_info) +
4436                         t4_handle_intr_status(adapter,
4437                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4438                                         pcie_port_intr_info) +
4439                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4440                                               pcie_intr_info);
4441         else
4442                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4443                                             t5_pcie_intr_info);
4444
4445         if (fat)
4446                 t4_fatal_err(adapter);
4447 }
4448
4449 /*
4450  * TP interrupt handler.
4451  */
4452 static void tp_intr_handler(struct adapter *adapter)
4453 {
4454         static const struct intr_info tp_intr_info[] = {
4455                 { 0x3fffffff, "TP parity error", -1, 1 },
4456                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4457                 { 0 }
4458         };
4459
4460         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4461                 t4_fatal_err(adapter);
4462 }
4463
4464 /*
4465  * SGE interrupt handler.
4466  */
4467 static void sge_intr_handler(struct adapter *adapter)
4468 {
4469         u32 v = 0, perr;
4470         u32 err;
4471
4472         static const struct intr_info sge_intr_info[] = {
4473                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4474                   "SGE received CPL exceeding IQE size", -1, 1 },
4475                 { ERR_INVALID_CIDX_INC_F,
4476                   "SGE GTS CIDX increment too large", -1, 0 },
4477                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4478                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4479                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4480                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4481                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4482                   0 },
4483                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4484                   0 },
4485                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4486                   0 },
4487                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4488                   0 },
4489                 { ERR_ING_CTXT_PRIO_F,
4490                   "SGE too many priority ingress contexts", -1, 0 },
4491                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4492                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4493                 { 0 }
4494         };
4495
4496         static struct intr_info t4t5_sge_intr_info[] = {
4497                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4498                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4499                 { ERR_EGR_CTXT_PRIO_F,
4500                   "SGE too many priority egress contexts", -1, 0 },
4501                 { 0 }
4502         };
4503
4504         perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4505         if (perr) {
4506                 v |= perr;
4507                 dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
4508                           perr);
4509         }
4510
4511         perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4512         if (perr) {
4513                 v |= perr;
4514                 dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
4515                           perr);
4516         }
4517
4518         if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
4519                 perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4520                 /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4521                 perr &= ~ERR_T_RXCRC_F;
4522                 if (perr) {
4523                         v |= perr;
4524                         dev_alert(adapter->pdev_dev,
4525                                   "SGE Cause5 Parity Error %#x\n", perr);
4526                 }
4527         }
4528
4529         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4530         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4531                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4532                                            t4t5_sge_intr_info);
4533
4534         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4535         if (err & ERROR_QID_VALID_F) {
4536                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4537                         ERROR_QID_G(err));
4538                 if (err & UNCAPTURED_ERROR_F)
4539                         dev_err(adapter->pdev_dev,
4540                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4541                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4542                              UNCAPTURED_ERROR_F);
4543         }
4544
4545         if (v != 0)
4546                 t4_fatal_err(adapter);
4547 }
4548
4549 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4550                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4551 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4552                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4553
4554 /*
4555  * CIM interrupt handler.
4556  */
4557 static void cim_intr_handler(struct adapter *adapter)
4558 {
4559         static const struct intr_info cim_intr_info[] = {
4560                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4561                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4562                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4563                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4564                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4565                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4566                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4567                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4568                 { 0 }
4569         };
4570         static const struct intr_info cim_upintr_info[] = {
4571                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4572                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4573                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4574                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4575                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4576                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4577                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4578                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4579                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4580                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4581                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4582                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4583                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4584                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4585                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4586                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4587                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4588                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4589                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4590                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4591                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4592                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4593                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4594                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4595                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4596                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4597                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4598                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4599                 { 0 }
4600         };
4601
4602         u32 val, fw_err;
4603         int fat;
4604
4605         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4606         if (fw_err & PCIE_FW_ERR_F)
4607                 t4_report_fw_error(adapter);
4608
4609         /* When the Firmware detects an internal error which normally
4610          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4611          * in order to make sure the Host sees the Firmware Crash.  So
4612          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4613          * ignore the Timer0 interrupt.
4614          */
4615
4616         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4617         if (val & TIMER0INT_F)
4618                 if (!(fw_err & PCIE_FW_ERR_F) ||
4619                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4620                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4621                                      TIMER0INT_F);
4622
4623         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4624                                     cim_intr_info) +
4625               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4626                                     cim_upintr_info);
4627         if (fat)
4628                 t4_fatal_err(adapter);
4629 }
4630
4631 /*
4632  * ULP RX interrupt handler.
4633  */
4634 static void ulprx_intr_handler(struct adapter *adapter)
4635 {
4636         static const struct intr_info ulprx_intr_info[] = {
4637                 { 0x1800000, "ULPRX context error", -1, 1 },
4638                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4639                 { 0 }
4640         };
4641
4642         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4643                 t4_fatal_err(adapter);
4644 }
4645
4646 /*
4647  * ULP TX interrupt handler.
4648  */
4649 static void ulptx_intr_handler(struct adapter *adapter)
4650 {
4651         static const struct intr_info ulptx_intr_info[] = {
4652                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4653                   0 },
4654                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4655                   0 },
4656                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4657                   0 },
4658                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4659                   0 },
4660                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4661                 { 0 }
4662         };
4663
4664         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4665                 t4_fatal_err(adapter);
4666 }
4667
4668 /*
4669  * PM TX interrupt handler.
4670  */
4671 static void pmtx_intr_handler(struct adapter *adapter)
4672 {
4673         static const struct intr_info pmtx_intr_info[] = {
4674                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4675                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4676                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4677                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4678                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4679                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4680                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4681                   -1, 1 },
4682                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4683                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4684                 { 0 }
4685         };
4686
4687         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4688                 t4_fatal_err(adapter);
4689 }
4690
4691 /*
4692  * PM RX interrupt handler.
4693  */
4694 static void pmrx_intr_handler(struct adapter *adapter)
4695 {
4696         static const struct intr_info pmrx_intr_info[] = {
4697                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4698                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4699                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4700                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4701                   -1, 1 },
4702                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4703                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4704                 { 0 }
4705         };
4706
4707         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4708                 t4_fatal_err(adapter);
4709 }
4710
4711 /*
4712  * CPL switch interrupt handler.
4713  */
4714 static void cplsw_intr_handler(struct adapter *adapter)
4715 {
4716         static const struct intr_info cplsw_intr_info[] = {
4717                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4718                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4719                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4720                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4721                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4722                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4723                 { 0 }
4724         };
4725
4726         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4727                 t4_fatal_err(adapter);
4728 }
4729
4730 /*
4731  * LE interrupt handler.
4732  */
4733 static void le_intr_handler(struct adapter *adap)
4734 {
4735         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4736         static const struct intr_info le_intr_info[] = {
4737                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4738                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4739                 { PARITYERR_F, "LE parity error", -1, 1 },
4740                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4741                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4742                 { 0 }
4743         };
4744
4745         static struct intr_info t6_le_intr_info[] = {
4746                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4747                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4748                 { CMDTIDERR_F, "LE cmd tid error", -1, 1 },
4749                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4750                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4751                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4752                 { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },
4753                 { 0 }
4754         };
4755
4756         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4757                                   (chip <= CHELSIO_T5) ?
4758                                   le_intr_info : t6_le_intr_info))
4759                 t4_fatal_err(adap);
4760 }
4761
4762 /*
4763  * MPS interrupt handler.
4764  */
4765 static void mps_intr_handler(struct adapter *adapter)
4766 {
4767         static const struct intr_info mps_rx_intr_info[] = {
4768                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4769                 { 0 }
4770         };
4771         static const struct intr_info mps_tx_intr_info[] = {
4772                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4773                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4774                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4775                   -1, 1 },
4776                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4777                   -1, 1 },
4778                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4779                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4780                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4781                 { 0 }
4782         };
4783         static const struct intr_info t6_mps_tx_intr_info[] = {
4784                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4785                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4786                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4787                   -1, 1 },
4788                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4789                   -1, 1 },
4790                 /* MPS Tx Bubble is normal for T6 */
4791                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4792                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4793                 { 0 }
4794         };
4795         static const struct intr_info mps_trc_intr_info[] = {
4796                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4797                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4798                   -1, 1 },
4799                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4800                 { 0 }
4801         };
4802         static const struct intr_info mps_stat_sram_intr_info[] = {
4803                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4804                 { 0 }
4805         };
4806         static const struct intr_info mps_stat_tx_intr_info[] = {
4807                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4808                 { 0 }
4809         };
4810         static const struct intr_info mps_stat_rx_intr_info[] = {
4811                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4812                 { 0 }
4813         };
4814         static const struct intr_info mps_cls_intr_info[] = {
4815                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4816                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4817                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4818                 { 0 }
4819         };
4820
4821         int fat;
4822
4823         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4824                                     mps_rx_intr_info) +
4825               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4826                                     is_t6(adapter->params.chip)
4827                                     ? t6_mps_tx_intr_info
4828                                     : mps_tx_intr_info) +
4829               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4830                                     mps_trc_intr_info) +
4831               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4832                                     mps_stat_sram_intr_info) +
4833               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4834                                     mps_stat_tx_intr_info) +
4835               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4836                                     mps_stat_rx_intr_info) +
4837               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4838                                     mps_cls_intr_info);
4839
4840         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4841         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4842         if (fat)
4843                 t4_fatal_err(adapter);
4844 }
4845
4846 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4847                       ECC_UE_INT_CAUSE_F)
4848
4849 /*
4850  * EDC/MC interrupt handler.
4851  */
4852 static void mem_intr_handler(struct adapter *adapter, int idx)
4853 {
4854         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4855
4856         unsigned int addr, cnt_addr, v;
4857
4858         if (idx <= MEM_EDC1) {
4859                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4860                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4861         } else if (idx == MEM_MC) {
4862                 if (is_t4(adapter->params.chip)) {
4863                         addr = MC_INT_CAUSE_A;
4864                         cnt_addr = MC_ECC_STATUS_A;
4865                 } else {
4866                         addr = MC_P_INT_CAUSE_A;
4867                         cnt_addr = MC_P_ECC_STATUS_A;
4868                 }
4869         } else {
4870                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4871                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4872         }
4873
4874         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4875         if (v & PERR_INT_CAUSE_F)
4876                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4877                           name[idx]);
4878         if (v & ECC_CE_INT_CAUSE_F) {
4879                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4880
4881                 t4_edc_err_read(adapter, idx);
4882
4883                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4884                 if (printk_ratelimit())
4885                         dev_warn(adapter->pdev_dev,
4886                                  "%u %s correctable ECC data error%s\n",
4887                                  cnt, name[idx], cnt > 1 ? "s" : "");
4888         }
4889         if (v & ECC_UE_INT_CAUSE_F)
4890                 dev_alert(adapter->pdev_dev,
4891                           "%s uncorrectable ECC data error\n", name[idx]);
4892
4893         t4_write_reg(adapter, addr, v);
4894         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4895                 t4_fatal_err(adapter);
4896 }
4897
4898 /*
4899  * MA interrupt handler.
4900  */
4901 static void ma_intr_handler(struct adapter *adap)
4902 {
4903         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4904
4905         if (status & MEM_PERR_INT_CAUSE_F) {
4906                 dev_alert(adap->pdev_dev,
4907                           "MA parity error, parity status %#x\n",
4908                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4909                 if (is_t5(adap->params.chip))
4910                         dev_alert(adap->pdev_dev,
4911                                   "MA parity error, parity status %#x\n",
4912                                   t4_read_reg(adap,
4913                                               MA_PARITY_ERROR_STATUS2_A));
4914         }
4915         if (status & MEM_WRAP_INT_CAUSE_F) {
4916                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4917                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4918                           "client %u to address %#x\n",
4919                           MEM_WRAP_CLIENT_NUM_G(v),
4920                           MEM_WRAP_ADDRESS_G(v) << 4);
4921         }
4922         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4923         t4_fatal_err(adap);
4924 }
4925
4926 /*
4927  * SMB interrupt handler.
4928  */
4929 static void smb_intr_handler(struct adapter *adap)
4930 {
4931         static const struct intr_info smb_intr_info[] = {
4932                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4933                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4934                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4935                 { 0 }
4936         };
4937
4938         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4939                 t4_fatal_err(adap);
4940 }
4941
4942 /*
4943  * NC-SI interrupt handler.
4944  */
4945 static void ncsi_intr_handler(struct adapter *adap)
4946 {
4947         static const struct intr_info ncsi_intr_info[] = {
4948                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4949                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4950                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4951                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4952                 { 0 }
4953         };
4954
4955         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4956                 t4_fatal_err(adap);
4957 }
4958
4959 /*
4960  * XGMAC interrupt handler.
4961  */
4962 static void xgmac_intr_handler(struct adapter *adap, int port)
4963 {
4964         u32 v, int_cause_reg;
4965
4966         if (is_t4(adap->params.chip))
4967                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4968         else
4969                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4970
4971         v = t4_read_reg(adap, int_cause_reg);
4972
4973         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4974         if (!v)
4975                 return;
4976
4977         if (v & TXFIFO_PRTY_ERR_F)
4978                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4979                           port);
4980         if (v & RXFIFO_PRTY_ERR_F)
4981                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4982                           port);
4983         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4984         t4_fatal_err(adap);
4985 }
4986
4987 /*
4988  * PL interrupt handler.
4989  */
4990 static void pl_intr_handler(struct adapter *adap)
4991 {
4992         static const struct intr_info pl_intr_info[] = {
4993                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4994                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4995                 { 0 }
4996         };
4997
4998         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4999                 t4_fatal_err(adap);
5000 }
5001
5002 #define PF_INTR_MASK (PFSW_F)
5003 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5004                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5005                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5006
5007 /**
5008  *      t4_slow_intr_handler - control path interrupt handler
5009  *      @adapter: the adapter
5010  *
5011  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
5012  *      The designation 'slow' is because it involves register reads, while
5013  *      data interrupts typically don't involve any MMIOs.
5014  */
5015 int t4_slow_intr_handler(struct adapter *adapter)
5016 {
5017         /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5018          * set when the corresponding PL_INT_ENABLE bit isn't set.  It's
5019          * easiest just to mask that case here.
5020          */
5021         u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5022         u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5023         u32 cause = raw_cause & enable;
5024
5025         if (!(cause & GLBL_INTR_MASK))
5026                 return 0;
5027         if (cause & CIM_F)
5028                 cim_intr_handler(adapter);
5029         if (cause & MPS_F)
5030                 mps_intr_handler(adapter);
5031         if (cause & NCSI_F)
5032                 ncsi_intr_handler(adapter);
5033         if (cause & PL_F)
5034                 pl_intr_handler(adapter);
5035         if (cause & SMB_F)
5036                 smb_intr_handler(adapter);
5037         if (cause & XGMAC0_F)
5038                 xgmac_intr_handler(adapter, 0);
5039         if (cause & XGMAC1_F)
5040                 xgmac_intr_handler(adapter, 1);
5041         if (cause & XGMAC_KR0_F)
5042                 xgmac_intr_handler(adapter, 2);
5043         if (cause & XGMAC_KR1_F)
5044                 xgmac_intr_handler(adapter, 3);
5045         if (cause & PCIE_F)
5046                 pcie_intr_handler(adapter);
5047         if (cause & MC_F)
5048                 mem_intr_handler(adapter, MEM_MC);
5049         if (is_t5(adapter->params.chip) && (cause & MC1_F))
5050                 mem_intr_handler(adapter, MEM_MC1);
5051         if (cause & EDC0_F)
5052                 mem_intr_handler(adapter, MEM_EDC0);
5053         if (cause & EDC1_F)
5054                 mem_intr_handler(adapter, MEM_EDC1);
5055         if (cause & LE_F)
5056                 le_intr_handler(adapter);
5057         if (cause & TP_F)
5058                 tp_intr_handler(adapter);
5059         if (cause & MA_F)
5060                 ma_intr_handler(adapter);
5061         if (cause & PM_TX_F)
5062                 pmtx_intr_handler(adapter);
5063         if (cause & PM_RX_F)
5064                 pmrx_intr_handler(adapter);
5065         if (cause & ULP_RX_F)
5066                 ulprx_intr_handler(adapter);
5067         if (cause & CPL_SWITCH_F)
5068                 cplsw_intr_handler(adapter);
5069         if (cause & SGE_F)
5070                 sge_intr_handler(adapter);
5071         if (cause & ULP_TX_F)
5072                 ulptx_intr_handler(adapter);
5073
5074         /* Clear the interrupts just processed for which we are the master. */
5075         t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
5076         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5077         return 1;
5078 }
5079
5080 /**
5081  *      t4_intr_enable - enable interrupts
5082  *      @adapter: the adapter whose interrupts should be enabled
5083  *
5084  *      Enable PF-specific interrupts for the calling function and the top-level
5085  *      interrupt concentrator for global interrupts.  Interrupts are already
5086  *      enabled at each module, here we just enable the roots of the interrupt
5087  *      hierarchies.
5088  *
5089  *      Note: this function should be called only when the driver manages
5090  *      non PF-specific interrupts from the various HW modules.  Only one PCI
5091  *      function at a time should be doing this.
5092  */
5093 void t4_intr_enable(struct adapter *adapter)
5094 {
5095         u32 val = 0;
5096         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5097         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5098                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5099
5100         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5101                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5102         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5103                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5104                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5105                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5106                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5107                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5108                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5109         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5110         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5111 }
5112
5113 /**
5114  *      t4_intr_disable - disable interrupts
5115  *      @adapter: the adapter whose interrupts should be disabled
5116  *
5117  *      Disable interrupts.  We only disable the top-level interrupt
5118  *      concentrators.  The caller must be a PCI function managing global
5119  *      interrupts.
5120  */
5121 void t4_intr_disable(struct adapter *adapter)
5122 {
5123         u32 whoami, pf;
5124
5125         if (pci_channel_offline(adapter->pdev))
5126                 return;
5127
5128         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5129         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5130                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5131
5132         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5133         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5134 }
5135
5136 unsigned int t4_chip_rss_size(struct adapter *adap)
5137 {
5138         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5139                 return RSS_NENTRIES;
5140         else
5141                 return T6_RSS_NENTRIES;
5142 }
5143
5144 /**
5145  *      t4_config_rss_range - configure a portion of the RSS mapping table
5146  *      @adapter: the adapter
5147  *      @mbox: mbox to use for the FW command
5148  *      @viid: virtual interface whose RSS subtable is to be written
5149  *      @start: start entry in the table to write
5150  *      @n: how many table entries to write
5151  *      @rspq: values for the response queue lookup table
5152  *      @nrspq: number of values in @rspq
5153  *
5154  *      Programs the selected part of the VI's RSS mapping table with the
5155  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
5156  *      until the full table range is populated.
5157  *
5158  *      The caller must ensure the values in @rspq are in the range allowed for
5159  *      @viid.
5160  */
5161 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5162                         int start, int n, const u16 *rspq, unsigned int nrspq)
5163 {
5164         int ret;
5165         const u16 *rsp = rspq;
5166         const u16 *rsp_end = rspq + nrspq;
5167         struct fw_rss_ind_tbl_cmd cmd;
5168
5169         memset(&cmd, 0, sizeof(cmd));
5170         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5171                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5172                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
5173         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5174
5175         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5176         while (n > 0) {
5177                 int nq = min(n, 32);
5178                 __be32 *qp = &cmd.iq0_to_iq2;
5179
5180                 cmd.niqid = cpu_to_be16(nq);
5181                 cmd.startidx = cpu_to_be16(start);
5182
5183                 start += nq;
5184                 n -= nq;
5185
5186                 while (nq > 0) {
5187                         unsigned int v;
5188
5189                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5190                         if (++rsp >= rsp_end)
5191                                 rsp = rspq;
5192                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5193                         if (++rsp >= rsp_end)
5194                                 rsp = rspq;
5195                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5196                         if (++rsp >= rsp_end)
5197                                 rsp = rspq;
5198
5199                         *qp++ = cpu_to_be32(v);
5200                         nq -= 3;
5201                 }
5202
5203                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5204                 if (ret)
5205                         return ret;
5206         }
5207         return 0;
5208 }
5209
5210 /**
5211  *      t4_config_glbl_rss - configure the global RSS mode
5212  *      @adapter: the adapter
5213  *      @mbox: mbox to use for the FW command
5214  *      @mode: global RSS mode
5215  *      @flags: mode-specific flags
5216  *
5217  *      Sets the global RSS mode.
5218  */
5219 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5220                        unsigned int flags)
5221 {
5222         struct fw_rss_glb_config_cmd c;
5223
5224         memset(&c, 0, sizeof(c));
5225         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5226                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5227         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5228         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5229                 c.u.manual.mode_pkd =
5230                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5231         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5232                 c.u.basicvirtual.mode_pkd =
5233                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5234                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5235         } else
5236                 return -EINVAL;
5237         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5238 }
5239
5240 /**
5241  *      t4_config_vi_rss - configure per VI RSS settings
5242  *      @adapter: the adapter
5243  *      @mbox: mbox to use for the FW command
5244  *      @viid: the VI id
5245  *      @flags: RSS flags
5246  *      @defq: id of the default RSS queue for the VI.
5247  *
5248  *      Configures VI-specific RSS properties.
5249  */
5250 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5251                      unsigned int flags, unsigned int defq)
5252 {
5253         struct fw_rss_vi_config_cmd c;
5254
5255         memset(&c, 0, sizeof(c));
5256         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5257                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5258                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5259         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5260         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5261                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5262         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5263 }
5264
5265 /* Read an RSS table row */
5266 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5267 {
5268         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5269         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5270                                    5, 0, val);
5271 }
5272
5273 /**
5274  *      t4_read_rss - read the contents of the RSS mapping table
5275  *      @adapter: the adapter
5276  *      @map: holds the contents of the RSS mapping table
5277  *
5278  *      Reads the contents of the RSS hash->queue mapping table.
5279  */
5280 int t4_read_rss(struct adapter *adapter, u16 *map)
5281 {
5282         int i, ret, nentries;
5283         u32 val;
5284
5285         nentries = t4_chip_rss_size(adapter);
5286         for (i = 0; i < nentries / 2; ++i) {
5287                 ret = rd_rss_row(adapter, i, &val);
5288                 if (ret)
5289                         return ret;
5290                 *map++ = LKPTBLQUEUE0_G(val);
5291                 *map++ = LKPTBLQUEUE1_G(val);
5292         }
5293         return 0;
5294 }
5295
5296 static unsigned int t4_use_ldst(struct adapter *adap)
5297 {
5298         return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5299 }
5300
5301 /**
5302  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5303  * @adap: the adapter
5304  * @cmd: TP fw ldst address space type
5305  * @vals: where the indirect register values are stored/written
5306  * @nregs: how many indirect registers to read/write
5307  * @start_index: index of first indirect register to read/write
5308  * @rw: Read (1) or Write (0)
5309  * @sleep_ok: if true we may sleep while awaiting command completion
5310  *
5311  * Access TP indirect registers through LDST
5312  */
5313 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5314                             unsigned int nregs, unsigned int start_index,
5315                             unsigned int rw, bool sleep_ok)
5316 {
5317         int ret = 0;
5318         unsigned int i;
5319         struct fw_ldst_cmd c;
5320
5321         for (i = 0; i < nregs; i++) {
5322                 memset(&c, 0, sizeof(c));
5323                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5324                                                 FW_CMD_REQUEST_F |
5325                                                 (rw ? FW_CMD_READ_F :
5326                                                       FW_CMD_WRITE_F) |
5327                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5328                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5329
5330                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5331                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5332                 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5333                                       sleep_ok);
5334                 if (ret)
5335                         return ret;
5336
5337                 if (rw)
5338                         vals[i] = be32_to_cpu(c.u.addrval.val);
5339         }
5340         return 0;
5341 }
5342
5343 /**
5344  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5345  * @adap: the adapter
5346  * @reg_addr: Address Register
5347  * @reg_data: Data register
5348  * @buff: where the indirect register values are stored/written
5349  * @nregs: how many indirect registers to read/write
5350  * @start_index: index of first indirect register to read/write
5351  * @rw: READ(1) or WRITE(0)
5352  * @sleep_ok: if true we may sleep while awaiting command completion
5353  *
5354  * Read/Write TP indirect registers through LDST if possible.
5355  * Else, use backdoor access
5356  **/
5357 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5358                               u32 *buff, u32 nregs, u32 start_index, int rw,
5359                               bool sleep_ok)
5360 {
5361         int rc = -EINVAL;
5362         int cmd;
5363
5364         switch (reg_addr) {
5365         case TP_PIO_ADDR_A:
5366                 cmd = FW_LDST_ADDRSPC_TP_PIO;
5367                 break;
5368         case TP_TM_PIO_ADDR_A:
5369                 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5370                 break;
5371         case TP_MIB_INDEX_A:
5372                 cmd = FW_LDST_ADDRSPC_TP_MIB;
5373                 break;
5374         default:
5375                 goto indirect_access;
5376         }
5377
5378         if (t4_use_ldst(adap))
5379                 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5380                                       sleep_ok);
5381
5382 indirect_access:
5383
5384         if (rc) {
5385                 if (rw)
5386                         t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5387                                          start_index);
5388                 else
5389                         t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5390                                           start_index);
5391         }
5392 }
5393
5394 /**
5395  * t4_tp_pio_read - Read TP PIO registers
5396  * @adap: the adapter
5397  * @buff: where the indirect register values are written
5398  * @nregs: how many indirect registers to read
5399  * @start_index: index of first indirect register to read
5400  * @sleep_ok: if true we may sleep while awaiting command completion
5401  *
5402  * Read TP PIO Registers
5403  **/
5404 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5405                     u32 start_index, bool sleep_ok)
5406 {
5407         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5408                           start_index, 1, sleep_ok);
5409 }
5410
5411 /**
5412  * t4_tp_pio_write - Write TP PIO registers
5413  * @adap: the adapter
5414  * @buff: where the indirect register values are stored
5415  * @nregs: how many indirect registers to write
5416  * @start_index: index of first indirect register to write
5417  * @sleep_ok: if true we may sleep while awaiting command completion
5418  *
5419  * Write TP PIO Registers
5420  **/
5421 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5422                             u32 start_index, bool sleep_ok)
5423 {
5424         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5425                           start_index, 0, sleep_ok);
5426 }
5427
5428 /**
5429  * t4_tp_tm_pio_read - Read TP TM PIO registers
5430  * @adap: the adapter
5431  * @buff: where the indirect register values are written
5432  * @nregs: how many indirect registers to read
5433  * @start_index: index of first indirect register to read
5434  * @sleep_ok: if true we may sleep while awaiting command completion
5435  *
5436  * Read TP TM PIO Registers
5437  **/
5438 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5439                        u32 start_index, bool sleep_ok)
5440 {
5441         t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5442                           nregs, start_index, 1, sleep_ok);
5443 }
5444
5445 /**
5446  * t4_tp_mib_read - Read TP MIB registers
5447  * @adap: the adapter
5448  * @buff: where the indirect register values are written
5449  * @nregs: how many indirect registers to read
5450  * @start_index: index of first indirect register to read
5451  * @sleep_ok: if true we may sleep while awaiting command completion
5452  *
5453  * Read TP MIB Registers
5454  **/
5455 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5456                     bool sleep_ok)
5457 {
5458         t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5459                           start_index, 1, sleep_ok);
5460 }
5461
5462 /**
5463  *      t4_read_rss_key - read the global RSS key
5464  *      @adap: the adapter
5465  *      @key: 10-entry array holding the 320-bit RSS key
5466  *      @sleep_ok: if true we may sleep while awaiting command completion
5467  *
5468  *      Reads the global 320-bit RSS key.
5469  */
5470 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5471 {
5472         t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5473 }
5474
5475 /**
5476  *      t4_write_rss_key - program one of the RSS keys
5477  *      @adap: the adapter
5478  *      @key: 10-entry array holding the 320-bit RSS key
5479  *      @idx: which RSS key to write
5480  *      @sleep_ok: if true we may sleep while awaiting command completion
5481  *
5482  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5483  *      0..15 the corresponding entry in the RSS key table is written,
5484  *      otherwise the global RSS key is written.
5485  */
5486 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5487                       bool sleep_ok)
5488 {
5489         u8 rss_key_addr_cnt = 16;
5490         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5491
5492         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5493          * allows access to key addresses 16-63 by using KeyWrAddrX
5494          * as index[5:4](upper 2) into key table
5495          */
5496         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5497             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5498                 rss_key_addr_cnt = 32;
5499
5500         t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5501
5502         if (idx >= 0 && idx < rss_key_addr_cnt) {
5503                 if (rss_key_addr_cnt > 16)
5504                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5505                                      KEYWRADDRX_V(idx >> 4) |
5506                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5507                 else
5508                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5509                                      KEYWRADDR_V(idx) | KEYWREN_F);
5510         }
5511 }
5512
5513 /**
5514  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5515  *      @adapter: the adapter
5516  *      @index: the entry in the PF RSS table to read
5517  *      @valp: where to store the returned value
5518  *      @sleep_ok: if true we may sleep while awaiting command completion
5519  *
5520  *      Reads the PF RSS Configuration Table at the specified index and returns
5521  *      the value found there.
5522  */
5523 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5524                            u32 *valp, bool sleep_ok)
5525 {
5526         t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5527 }
5528
5529 /**
5530  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5531  *      @adapter: the adapter
5532  *      @index: the entry in the VF RSS table to read
5533  *      @vfl: where to store the returned VFL
5534  *      @vfh: where to store the returned VFH
5535  *      @sleep_ok: if true we may sleep while awaiting command completion
5536  *
5537  *      Reads the VF RSS Configuration Table at the specified index and returns
5538  *      the (VFL, VFH) values found there.
5539  */
5540 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5541                            u32 *vfl, u32 *vfh, bool sleep_ok)
5542 {
5543         u32 vrt, mask, data;
5544
5545         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5546                 mask = VFWRADDR_V(VFWRADDR_M);
5547                 data = VFWRADDR_V(index);
5548         } else {
5549                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5550                  data = T6_VFWRADDR_V(index);
5551         }
5552
5553         /* Request that the index'th VF Table values be read into VFL/VFH.
5554          */
5555         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5556         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5557         vrt |= data | VFRDEN_F;
5558         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5559
5560         /* Grab the VFL/VFH values ...
5561          */
5562         t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5563         t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5564 }
5565
5566 /**
5567  *      t4_read_rss_pf_map - read PF RSS Map
5568  *      @adapter: the adapter
5569  *      @sleep_ok: if true we may sleep while awaiting command completion
5570  *
5571  *      Reads the PF RSS Map register and returns its value.
5572  */
5573 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5574 {
5575         u32 pfmap;
5576
5577         t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5578         return pfmap;
5579 }
5580
5581 /**
5582  *      t4_read_rss_pf_mask - read PF RSS Mask
5583  *      @adapter: the adapter
5584  *      @sleep_ok: if true we may sleep while awaiting command completion
5585  *
5586  *      Reads the PF RSS Mask register and returns its value.
5587  */
5588 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5589 {
5590         u32 pfmask;
5591
5592         t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5593         return pfmask;
5594 }
5595
5596 /**
5597  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5598  *      @adap: the adapter
5599  *      @v4: holds the TCP/IP counter values
5600  *      @v6: holds the TCP/IPv6 counter values
5601  *      @sleep_ok: if true we may sleep while awaiting command completion
5602  *
5603  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5604  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5605  */
5606 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5607                          struct tp_tcp_stats *v6, bool sleep_ok)
5608 {
5609         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5610
5611 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5612 #define STAT(x)     val[STAT_IDX(x)]
5613 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5614
5615         if (v4) {
5616                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5617                                TP_MIB_TCP_OUT_RST_A, sleep_ok);
5618                 v4->tcp_out_rsts = STAT(OUT_RST);
5619                 v4->tcp_in_segs  = STAT64(IN_SEG);
5620                 v4->tcp_out_segs = STAT64(OUT_SEG);
5621                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5622         }
5623         if (v6) {
5624                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5625                                TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5626                 v6->tcp_out_rsts = STAT(OUT_RST);
5627                 v6->tcp_in_segs  = STAT64(IN_SEG);
5628                 v6->tcp_out_segs = STAT64(OUT_SEG);
5629                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5630         }
5631 #undef STAT64
5632 #undef STAT
5633 #undef STAT_IDX
5634 }
5635
5636 /**
5637  *      t4_tp_get_err_stats - read TP's error MIB counters
5638  *      @adap: the adapter
5639  *      @st: holds the counter values
5640  *      @sleep_ok: if true we may sleep while awaiting command completion
5641  *
5642  *      Returns the values of TP's error counters.
5643  */
5644 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5645                          bool sleep_ok)
5646 {
5647         int nchan = adap->params.arch.nchan;
5648
5649         t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5650                        sleep_ok);
5651         t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5652                        sleep_ok);
5653         t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5654                        sleep_ok);
5655         t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5656                        TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5657         t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5658                        TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5659         t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5660                        sleep_ok);
5661         t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5662                        TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5663         t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5664                        TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5665         t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5666                        sleep_ok);
5667 }
5668
5669 /**
5670  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5671  *      @adap: the adapter
5672  *      @st: holds the counter values
5673  *      @sleep_ok: if true we may sleep while awaiting command completion
5674  *
5675  *      Returns the values of TP's CPL counters.
5676  */
5677 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5678                          bool sleep_ok)
5679 {
5680         int nchan = adap->params.arch.nchan;
5681
5682         t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5683
5684         t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5685 }
5686
5687 /**
5688  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5689  *      @adap: the adapter
5690  *      @st: holds the counter values
5691  *      @sleep_ok: if true we may sleep while awaiting command completion
5692  *
5693  *      Returns the values of TP's RDMA counters.
5694  */
5695 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5696                           bool sleep_ok)
5697 {
5698         t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5699                        sleep_ok);
5700 }
5701
5702 /**
5703  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5704  *      @adap: the adapter
5705  *      @idx: the port index
5706  *      @st: holds the counter values
5707  *      @sleep_ok: if true we may sleep while awaiting command completion
5708  *
5709  *      Returns the values of TP's FCoE counters for the selected port.
5710  */
5711 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5712                        struct tp_fcoe_stats *st, bool sleep_ok)
5713 {
5714         u32 val[2];
5715
5716         t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5717                        sleep_ok);
5718
5719         t4_tp_mib_read(adap, &st->frames_drop, 1,
5720                        TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5721
5722         t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5723                        sleep_ok);
5724
5725         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5726 }
5727
5728 /**
5729  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5730  *      @adap: the adapter
5731  *      @st: holds the counter values
5732  *      @sleep_ok: if true we may sleep while awaiting command completion
5733  *
5734  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5735  */
5736 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5737                       bool sleep_ok)
5738 {
5739         u32 val[4];
5740
5741         t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5742         st->frames = val[0];
5743         st->drops = val[1];
5744         st->octets = ((u64)val[2] << 32) | val[3];
5745 }
5746
5747 /**
5748  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5749  *      @adap: the adapter
5750  *      @mtus: where to store the MTU values
5751  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5752  *
5753  *      Reads the HW path MTU table.
5754  */
5755 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5756 {
5757         u32 v;
5758         int i;
5759
5760         for (i = 0; i < NMTUS; ++i) {
5761                 t4_write_reg(adap, TP_MTU_TABLE_A,
5762                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5763                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5764                 mtus[i] = MTUVALUE_G(v);
5765                 if (mtu_log)
5766                         mtu_log[i] = MTUWIDTH_G(v);
5767         }
5768 }
5769
5770 /**
5771  *      t4_read_cong_tbl - reads the congestion control table
5772  *      @adap: the adapter
5773  *      @incr: where to store the alpha values
5774  *
5775  *      Reads the additive increments programmed into the HW congestion
5776  *      control table.
5777  */
5778 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5779 {
5780         unsigned int mtu, w;
5781
5782         for (mtu = 0; mtu < NMTUS; ++mtu)
5783                 for (w = 0; w < NCCTRL_WIN; ++w) {
5784                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5785                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5786                         incr[mtu][w] = (u16)t4_read_reg(adap,
5787                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5788                 }
5789 }
5790
5791 /**
5792  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5793  *      @adap: the adapter
5794  *      @addr: the indirect TP register address
5795  *      @mask: specifies the field within the register to modify
5796  *      @val: new value for the field
5797  *
5798  *      Sets a field of an indirect TP register to the given value.
5799  */
5800 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5801                             unsigned int mask, unsigned int val)
5802 {
5803         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5804         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5805         t4_write_reg(adap, TP_PIO_DATA_A, val);
5806 }
5807
5808 /**
5809  *      init_cong_ctrl - initialize congestion control parameters
5810  *      @a: the alpha values for congestion control
5811  *      @b: the beta values for congestion control
5812  *
5813  *      Initialize the congestion control parameters.
5814  */
5815 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5816 {
5817         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5818         a[9] = 2;
5819         a[10] = 3;
5820         a[11] = 4;
5821         a[12] = 5;
5822         a[13] = 6;
5823         a[14] = 7;
5824         a[15] = 8;
5825         a[16] = 9;
5826         a[17] = 10;
5827         a[18] = 14;
5828         a[19] = 17;
5829         a[20] = 21;
5830         a[21] = 25;
5831         a[22] = 30;
5832         a[23] = 35;
5833         a[24] = 45;
5834         a[25] = 60;
5835         a[26] = 80;
5836         a[27] = 100;
5837         a[28] = 200;
5838         a[29] = 300;
5839         a[30] = 400;
5840         a[31] = 500;
5841
5842         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5843         b[9] = b[10] = 1;
5844         b[11] = b[12] = 2;
5845         b[13] = b[14] = b[15] = b[16] = 3;
5846         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5847         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5848         b[28] = b[29] = 6;
5849         b[30] = b[31] = 7;
5850 }
5851
5852 /* The minimum additive increment value for the congestion control table */
5853 #define CC_MIN_INCR 2U
5854
5855 /**
5856  *      t4_load_mtus - write the MTU and congestion control HW tables
5857  *      @adap: the adapter
5858  *      @mtus: the values for the MTU table
5859  *      @alpha: the values for the congestion control alpha parameter
5860  *      @beta: the values for the congestion control beta parameter
5861  *
5862  *      Write the HW MTU table with the supplied MTUs and the high-speed
5863  *      congestion control table with the supplied alpha, beta, and MTUs.
5864  *      We write the two tables together because the additive increments
5865  *      depend on the MTUs.
5866  */
5867 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5868                   const unsigned short *alpha, const unsigned short *beta)
5869 {
5870         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5871                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5872                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5873                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5874         };
5875
5876         unsigned int i, w;
5877
5878         for (i = 0; i < NMTUS; ++i) {
5879                 unsigned int mtu = mtus[i];
5880                 unsigned int log2 = fls(mtu);
5881
5882                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5883                         log2--;
5884                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5885                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5886
5887                 for (w = 0; w < NCCTRL_WIN; ++w) {
5888                         unsigned int inc;
5889
5890                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5891                                   CC_MIN_INCR);
5892
5893                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5894                                      (w << 16) | (beta[w] << 13) | inc);
5895                 }
5896         }
5897 }
5898
5899 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5900  * clocks.  The formula is
5901  *
5902  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5903  *
5904  * which is equivalent to
5905  *
5906  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5907  */
5908 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5909 {
5910         u64 v = bytes256 * adap->params.vpd.cclk;
5911
5912         return v * 62 + v / 2;
5913 }
5914
5915 /**
5916  *      t4_get_chan_txrate - get the current per channel Tx rates
5917  *      @adap: the adapter
5918  *      @nic_rate: rates for NIC traffic
5919  *      @ofld_rate: rates for offloaded traffic
5920  *
5921  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5922  *      for each channel.
5923  */
5924 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5925 {
5926         u32 v;
5927
5928         v = t4_read_reg(adap, TP_TX_TRATE_A);
5929         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5930         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5931         if (adap->params.arch.nchan == NCHAN) {
5932                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5933                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5934         }
5935
5936         v = t4_read_reg(adap, TP_TX_ORATE_A);
5937         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5938         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5939         if (adap->params.arch.nchan == NCHAN) {
5940                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5941                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5942         }
5943 }
5944
5945 /**
5946  *      t4_set_trace_filter - configure one of the tracing filters
5947  *      @adap: the adapter
5948  *      @tp: the desired trace filter parameters
5949  *      @idx: which filter to configure
5950  *      @enable: whether to enable or disable the filter
5951  *
5952  *      Configures one of the tracing filters available in HW.  If @enable is
5953  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5954  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5955  */
5956 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5957                         int idx, int enable)
5958 {
5959         int i, ofst = idx * 4;
5960         u32 data_reg, mask_reg, cfg;
5961
5962         if (!enable) {
5963                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5964                 return 0;
5965         }
5966
5967         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5968         if (cfg & TRCMULTIFILTER_F) {
5969                 /* If multiple tracers are enabled, then maximum
5970                  * capture size is 2.5KB (FIFO size of a single channel)
5971                  * minus 2 flits for CPL_TRACE_PKT header.
5972                  */
5973                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5974                         return -EINVAL;
5975         } else {
5976                 /* If multiple tracers are disabled, to avoid deadlocks
5977                  * maximum packet capture size of 9600 bytes is recommended.
5978                  * Also in this mode, only trace0 can be enabled and running.
5979                  */
5980                 if (tp->snap_len > 9600 || idx)
5981                         return -EINVAL;
5982         }
5983
5984         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5985             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5986             tp->min_len > TFMINPKTSIZE_M)
5987                 return -EINVAL;
5988
5989         /* stop the tracer we'll be changing */
5990         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5991
5992         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5993         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5994         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5995
5996         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5997                 t4_write_reg(adap, data_reg, tp->data[i]);
5998                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5999         }
6000         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
6001                      TFCAPTUREMAX_V(tp->snap_len) |
6002                      TFMINPKTSIZE_V(tp->min_len));
6003         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
6004                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
6005                      (is_t4(adap->params.chip) ?
6006                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
6007                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
6008                      T5_TFINVERTMATCH_V(tp->invert)));
6009
6010         return 0;
6011 }
6012
6013 /**
6014  *      t4_get_trace_filter - query one of the tracing filters
6015  *      @adap: the adapter
6016  *      @tp: the current trace filter parameters
6017  *      @idx: which trace filter to query
6018  *      @enabled: non-zero if the filter is enabled
6019  *
6020  *      Returns the current settings of one of the HW tracing filters.
6021  */
6022 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6023                          int *enabled)
6024 {
6025         u32 ctla, ctlb;
6026         int i, ofst = idx * 4;
6027         u32 data_reg, mask_reg;
6028
6029         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6030         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6031
6032         if (is_t4(adap->params.chip)) {
6033                 *enabled = !!(ctla & TFEN_F);
6034                 tp->port =  TFPORT_G(ctla);
6035                 tp->invert = !!(ctla & TFINVERTMATCH_F);
6036         } else {
6037                 *enabled = !!(ctla & T5_TFEN_F);
6038                 tp->port = T5_TFPORT_G(ctla);
6039                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
6040         }
6041         tp->snap_len = TFCAPTUREMAX_G(ctlb);
6042         tp->min_len = TFMINPKTSIZE_G(ctlb);
6043         tp->skip_ofst = TFOFFSET_G(ctla);
6044         tp->skip_len = TFLENGTH_G(ctla);
6045
6046         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
6047         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
6048         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
6049
6050         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6051                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6052                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6053         }
6054 }
6055
6056 /**
6057  *      t4_pmtx_get_stats - returns the HW stats from PMTX
6058  *      @adap: the adapter
6059  *      @cnt: where to store the count statistics
6060  *      @cycles: where to store the cycle statistics
6061  *
6062  *      Returns performance statistics from PMTX.
6063  */
6064 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6065 {
6066         int i;
6067         u32 data[2];
6068
6069         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6070                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6071                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6072                 if (is_t4(adap->params.chip)) {
6073                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6074                 } else {
6075                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6076                                          PM_TX_DBG_DATA_A, data, 2,
6077                                          PM_TX_DBG_STAT_MSB_A);
6078                         cycles[i] = (((u64)data[0] << 32) | data[1]);
6079                 }
6080         }
6081 }
6082
6083 /**
6084  *      t4_pmrx_get_stats - returns the HW stats from PMRX
6085  *      @adap: the adapter
6086  *      @cnt: where to store the count statistics
6087  *      @cycles: where to store the cycle statistics
6088  *
6089  *      Returns performance statistics from PMRX.
6090  */
6091 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6092 {
6093         int i;
6094         u32 data[2];
6095
6096         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6097                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6098                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6099                 if (is_t4(adap->params.chip)) {
6100                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6101                 } else {
6102                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6103                                          PM_RX_DBG_DATA_A, data, 2,
6104                                          PM_RX_DBG_STAT_MSB_A);
6105                         cycles[i] = (((u64)data[0] << 32) | data[1]);
6106                 }
6107         }
6108 }
6109
6110 /**
6111  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6112  *      @adapter: the adapter
6113  *      @pidx: the port index
6114  *
6115  *      Computes and returns a bitmap indicating which MPS buffer groups are
6116  *      associated with the given Port.  Bit i is set if buffer group i is
6117  *      used by the Port.
6118  */
6119 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6120                                               int pidx)
6121 {
6122         unsigned int chip_version, nports;
6123
6124         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6125         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6126
6127         switch (chip_version) {
6128         case CHELSIO_T4:
6129         case CHELSIO_T5:
6130                 switch (nports) {
6131                 case 1: return 0xf;
6132                 case 2: return 3 << (2 * pidx);
6133                 case 4: return 1 << pidx;
6134                 }
6135                 break;
6136
6137         case CHELSIO_T6:
6138                 switch (nports) {
6139                 case 2: return 1 << (2 * pidx);
6140                 }
6141                 break;
6142         }
6143
6144         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6145                 chip_version, nports);
6146
6147         return 0;
6148 }
6149
6150 /**
6151  *      t4_get_mps_bg_map - return the buffer groups associated with a port
6152  *      @adapter: the adapter
6153  *      @pidx: the port index
6154  *
6155  *      Returns a bitmap indicating which MPS buffer groups are associated
6156  *      with the given Port.  Bit i is set if buffer group i is used by the
6157  *      Port.
6158  */
6159 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6160 {
6161         u8 *mps_bg_map;
6162         unsigned int nports;
6163
6164         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6165         if (pidx >= nports) {
6166                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6167                         pidx, nports);
6168                 return 0;
6169         }
6170
6171         /* If we've already retrieved/computed this, just return the result.
6172          */
6173         mps_bg_map = adapter->params.mps_bg_map;
6174         if (mps_bg_map[pidx])
6175                 return mps_bg_map[pidx];
6176
6177         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6178          * If we're talking to such Firmware, let it tell us.  If the new
6179          * API isn't supported, revert back to old hardcoded way.  The value
6180          * obtained from Firmware is encoded in below format:
6181          *
6182          * val = (( MPSBGMAP[Port 3] << 24 ) |
6183          *        ( MPSBGMAP[Port 2] << 16 ) |
6184          *        ( MPSBGMAP[Port 1] <<  8 ) |
6185          *        ( MPSBGMAP[Port 0] <<  0 ))
6186          */
6187         if (adapter->flags & CXGB4_FW_OK) {
6188                 u32 param, val;
6189                 int ret;
6190
6191                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6192                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6193                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6194                                          0, 1, &param, &val);
6195                 if (!ret) {
6196                         int p;
6197
6198                         /* Store the BG Map for all of the Ports in order to
6199                          * avoid more calls to the Firmware in the future.
6200                          */
6201                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6202                                 mps_bg_map[p] = val & 0xff;
6203
6204                         return mps_bg_map[pidx];
6205                 }
6206         }
6207
6208         /* Either we're not talking to the Firmware or we're dealing with
6209          * older Firmware which doesn't support the new API to get the MPS
6210          * Buffer Group Map.  Fall back to computing it ourselves.
6211          */
6212         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6213         return mps_bg_map[pidx];
6214 }
6215
6216 /**
6217  *      t4_get_tp_e2c_map - return the E2C channel map associated with a port
6218  *      @adapter: the adapter
6219  *      @pidx: the port index
6220  */
6221 static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
6222 {
6223         unsigned int nports;
6224         u32 param, val = 0;
6225         int ret;
6226
6227         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6228         if (pidx >= nports) {
6229                 CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
6230                         pidx, nports);
6231                 return 0;
6232         }
6233
6234         /* FW version >= 1.16.44.0 can determine E2C channel map using
6235          * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6236          */
6237         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6238                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
6239         ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6240                                  0, 1, &param, &val);
6241         if (!ret)
6242                 return (val >> (8 * pidx)) & 0xff;
6243
6244         return 0;
6245 }
6246
6247 /**
6248  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
6249  *      @adap: the adapter
6250  *      @pidx: the port index
6251  *
6252  *      Returns a bitmap indicating which TP Ingress Channels are associated
6253  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
6254  *      the Port.
6255  */
6256 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6257 {
6258         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6259         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6260
6261         if (pidx >= nports) {
6262                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6263                          pidx, nports);
6264                 return 0;
6265         }
6266
6267         switch (chip_version) {
6268         case CHELSIO_T4:
6269         case CHELSIO_T5:
6270                 /* Note that this happens to be the same values as the MPS
6271                  * Buffer Group Map for these Chips.  But we replicate the code
6272                  * here because they're really separate concepts.
6273                  */
6274                 switch (nports) {
6275                 case 1: return 0xf;
6276                 case 2: return 3 << (2 * pidx);
6277                 case 4: return 1 << pidx;
6278                 }
6279                 break;
6280
6281         case CHELSIO_T6:
6282                 switch (nports) {
6283                 case 1:
6284                 case 2: return 1 << pidx;
6285                 }
6286                 break;
6287         }
6288
6289         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6290                 chip_version, nports);
6291         return 0;
6292 }
6293
6294 /**
6295  *      t4_get_port_type_description - return Port Type string description
6296  *      @port_type: firmware Port Type enumeration
6297  */
6298 const char *t4_get_port_type_description(enum fw_port_type port_type)
6299 {
6300         static const char *const port_type_description[] = {
6301                 "Fiber_XFI",
6302                 "Fiber_XAUI",
6303                 "BT_SGMII",
6304                 "BT_XFI",
6305                 "BT_XAUI",
6306                 "KX4",
6307                 "CX4",
6308                 "KX",
6309                 "KR",
6310                 "SFP",
6311                 "BP_AP",
6312                 "BP4_AP",
6313                 "QSFP_10G",
6314                 "QSA",
6315                 "QSFP",
6316                 "BP40_BA",
6317                 "KR4_100G",
6318                 "CR4_QSFP",
6319                 "CR_QSFP",
6320                 "CR2_QSFP",
6321                 "SFP28",
6322                 "KR_SFP28",
6323                 "KR_XLAUI"
6324         };
6325
6326         if (port_type < ARRAY_SIZE(port_type_description))
6327                 return port_type_description[port_type];
6328         return "UNKNOWN";
6329 }
6330
6331 /**
6332  *      t4_get_port_stats_offset - collect port stats relative to a previous
6333  *                                 snapshot
6334  *      @adap: The adapter
6335  *      @idx: The port
6336  *      @stats: Current stats to fill
6337  *      @offset: Previous stats snapshot
6338  */
6339 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6340                               struct port_stats *stats,
6341                               struct port_stats *offset)
6342 {
6343         u64 *s, *o;
6344         int i;
6345
6346         t4_get_port_stats(adap, idx, stats);
6347         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6348                         i < (sizeof(struct port_stats) / sizeof(u64));
6349                         i++, s++, o++)
6350                 *s -= *o;
6351 }
6352
6353 /**
6354  *      t4_get_port_stats - collect port statistics
6355  *      @adap: the adapter
6356  *      @idx: the port index
6357  *      @p: the stats structure to fill
6358  *
6359  *      Collect statistics related to the given port from HW.
6360  */
6361 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6362 {
6363         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6364         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6365
6366 #define GET_STAT(name) \
6367         t4_read_reg64(adap, \
6368         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6369         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6370 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6371
6372         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
6373         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
6374         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
6375         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
6376         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
6377         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
6378         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
6379         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
6380         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
6381         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
6382         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
6383         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6384         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
6385         p->tx_drop             = GET_STAT(TX_PORT_DROP);
6386         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
6387         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
6388         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
6389         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
6390         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
6391         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
6392         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
6393         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
6394         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
6395
6396         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6397                 if (stat_ctl & COUNTPAUSESTATTX_F)
6398                         p->tx_frames_64 -= p->tx_pause;
6399                 if (stat_ctl & COUNTPAUSEMCTX_F)
6400                         p->tx_mcast_frames -= p->tx_pause;
6401         }
6402         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6403         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6404         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6405         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6406         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6407         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6408         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6409         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6410         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6411         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6412         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6413         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6414         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6415         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6416         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6417         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6418         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6419         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6420         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6421         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6422         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6423         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6424         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6425         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6426         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6427         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6428         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6429
6430         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6431                 if (stat_ctl & COUNTPAUSESTATRX_F)
6432                         p->rx_frames_64 -= p->rx_pause;
6433                 if (stat_ctl & COUNTPAUSEMCRX_F)
6434                         p->rx_mcast_frames -= p->rx_pause;
6435         }
6436
6437         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6438         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6439         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6440         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6441         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6442         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6443         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6444         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6445
6446 #undef GET_STAT
6447 #undef GET_STAT_COM
6448 }
6449
6450 /**
6451  *      t4_get_lb_stats - collect loopback port statistics
6452  *      @adap: the adapter
6453  *      @idx: the loopback port index
6454  *      @p: the stats structure to fill
6455  *
6456  *      Return HW statistics for the given loopback port.
6457  */
6458 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6459 {
6460         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6461
6462 #define GET_STAT(name) \
6463         t4_read_reg64(adap, \
6464         (is_t4(adap->params.chip) ? \
6465         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6466         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6467 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6468
6469         p->octets           = GET_STAT(BYTES);
6470         p->frames           = GET_STAT(FRAMES);
6471         p->bcast_frames     = GET_STAT(BCAST);
6472         p->mcast_frames     = GET_STAT(MCAST);
6473         p->ucast_frames     = GET_STAT(UCAST);
6474         p->error_frames     = GET_STAT(ERROR);
6475
6476         p->frames_64        = GET_STAT(64B);
6477         p->frames_65_127    = GET_STAT(65B_127B);
6478         p->frames_128_255   = GET_STAT(128B_255B);
6479         p->frames_256_511   = GET_STAT(256B_511B);
6480         p->frames_512_1023  = GET_STAT(512B_1023B);
6481         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6482         p->frames_1519_max  = GET_STAT(1519B_MAX);
6483         p->drop             = GET_STAT(DROP_FRAMES);
6484
6485         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6486         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6487         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6488         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6489         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6490         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6491         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6492         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6493
6494 #undef GET_STAT
6495 #undef GET_STAT_COM
6496 }
6497
6498 /*     t4_mk_filtdelwr - create a delete filter WR
6499  *     @ftid: the filter ID
6500  *     @wr: the filter work request to populate
6501  *     @qid: ingress queue to receive the delete notification
6502  *
6503  *     Creates a filter work request to delete the supplied filter.  If @qid is
6504  *     negative the delete notification is suppressed.
6505  */
6506 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6507 {
6508         memset(wr, 0, sizeof(*wr));
6509         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6510         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6511         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6512                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6513         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6514         if (qid >= 0)
6515                 wr->rx_chan_rx_rpl_iq =
6516                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6517 }
6518
6519 #define INIT_CMD(var, cmd, rd_wr) do { \
6520         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6521                                         FW_CMD_REQUEST_F | \
6522                                         FW_CMD_##rd_wr##_F); \
6523         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6524 } while (0)
6525
6526 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6527                           u32 addr, u32 val)
6528 {
6529         u32 ldst_addrspace;
6530         struct fw_ldst_cmd c;
6531
6532         memset(&c, 0, sizeof(c));
6533         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6534         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6535                                         FW_CMD_REQUEST_F |
6536                                         FW_CMD_WRITE_F |
6537                                         ldst_addrspace);
6538         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6539         c.u.addrval.addr = cpu_to_be32(addr);
6540         c.u.addrval.val = cpu_to_be32(val);
6541
6542         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6543 }
6544
6545 /**
6546  *      t4_mdio_rd - read a PHY register through MDIO
6547  *      @adap: the adapter
6548  *      @mbox: mailbox to use for the FW command
6549  *      @phy_addr: the PHY address
6550  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6551  *      @reg: the register to read
6552  *      @valp: where to store the value
6553  *
6554  *      Issues a FW command through the given mailbox to read a PHY register.
6555  */
6556 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6557                unsigned int mmd, unsigned int reg, u16 *valp)
6558 {
6559         int ret;
6560         u32 ldst_addrspace;
6561         struct fw_ldst_cmd c;
6562
6563         memset(&c, 0, sizeof(c));
6564         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6565         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6566                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6567                                         ldst_addrspace);
6568         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6569         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6570                                          FW_LDST_CMD_MMD_V(mmd));
6571         c.u.mdio.raddr = cpu_to_be16(reg);
6572
6573         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6574         if (ret == 0)
6575                 *valp = be16_to_cpu(c.u.mdio.rval);
6576         return ret;
6577 }
6578
6579 /**
6580  *      t4_mdio_wr - write a PHY register through MDIO
6581  *      @adap: the adapter
6582  *      @mbox: mailbox to use for the FW command
6583  *      @phy_addr: the PHY address
6584  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6585  *      @reg: the register to write
6586  *      @val: value to write
6587  *
6588  *      Issues a FW command through the given mailbox to write a PHY register.
6589  */
6590 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6591                unsigned int mmd, unsigned int reg, u16 val)
6592 {
6593         u32 ldst_addrspace;
6594         struct fw_ldst_cmd c;
6595
6596         memset(&c, 0, sizeof(c));
6597         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6598         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6599                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6600                                         ldst_addrspace);
6601         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6602         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6603                                          FW_LDST_CMD_MMD_V(mmd));
6604         c.u.mdio.raddr = cpu_to_be16(reg);
6605         c.u.mdio.rval = cpu_to_be16(val);
6606
6607         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6608 }
6609
6610 /**
6611  *      t4_sge_decode_idma_state - decode the idma state
6612  *      @adapter: the adapter
6613  *      @state: the state idma is stuck in
6614  */
6615 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6616 {
6617         static const char * const t4_decode[] = {
6618                 "IDMA_IDLE",
6619                 "IDMA_PUSH_MORE_CPL_FIFO",
6620                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6621                 "Not used",
6622                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6623                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6624                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6625                 "IDMA_SEND_FIFO_TO_IMSG",
6626                 "IDMA_FL_REQ_DATA_FL_PREP",
6627                 "IDMA_FL_REQ_DATA_FL",
6628                 "IDMA_FL_DROP",
6629                 "IDMA_FL_H_REQ_HEADER_FL",
6630                 "IDMA_FL_H_SEND_PCIEHDR",
6631                 "IDMA_FL_H_PUSH_CPL_FIFO",
6632                 "IDMA_FL_H_SEND_CPL",
6633                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6634                 "IDMA_FL_H_SEND_IP_HDR",
6635                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6636                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6637                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6638                 "IDMA_FL_D_SEND_PCIEHDR",
6639                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6640                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6641                 "IDMA_FL_SEND_PCIEHDR",
6642                 "IDMA_FL_PUSH_CPL_FIFO",
6643                 "IDMA_FL_SEND_CPL",
6644                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6645                 "IDMA_FL_SEND_PAYLOAD",
6646                 "IDMA_FL_REQ_NEXT_DATA_FL",
6647                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6648                 "IDMA_FL_SEND_PADDING",
6649                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6650                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6651                 "IDMA_FL_REQ_DATAFL_DONE",
6652                 "IDMA_FL_REQ_HEADERFL_DONE",
6653         };
6654         static const char * const t5_decode[] = {
6655                 "IDMA_IDLE",
6656                 "IDMA_ALMOST_IDLE",
6657                 "IDMA_PUSH_MORE_CPL_FIFO",
6658                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6659                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6660                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6661                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6662                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6663                 "IDMA_SEND_FIFO_TO_IMSG",
6664                 "IDMA_FL_REQ_DATA_FL",
6665                 "IDMA_FL_DROP",
6666                 "IDMA_FL_DROP_SEND_INC",
6667                 "IDMA_FL_H_REQ_HEADER_FL",
6668                 "IDMA_FL_H_SEND_PCIEHDR",
6669                 "IDMA_FL_H_PUSH_CPL_FIFO",
6670                 "IDMA_FL_H_SEND_CPL",
6671                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6672                 "IDMA_FL_H_SEND_IP_HDR",
6673                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6674                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6675                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6676                 "IDMA_FL_D_SEND_PCIEHDR",
6677                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6678                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6679                 "IDMA_FL_SEND_PCIEHDR",
6680                 "IDMA_FL_PUSH_CPL_FIFO",
6681                 "IDMA_FL_SEND_CPL",
6682                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6683                 "IDMA_FL_SEND_PAYLOAD",
6684                 "IDMA_FL_REQ_NEXT_DATA_FL",
6685                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6686                 "IDMA_FL_SEND_PADDING",
6687                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6688         };
6689         static const char * const t6_decode[] = {
6690                 "IDMA_IDLE",
6691                 "IDMA_PUSH_MORE_CPL_FIFO",
6692                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6693                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6694                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6695                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6696                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6697                 "IDMA_FL_REQ_DATA_FL",
6698                 "IDMA_FL_DROP",
6699                 "IDMA_FL_DROP_SEND_INC",
6700                 "IDMA_FL_H_REQ_HEADER_FL",
6701                 "IDMA_FL_H_SEND_PCIEHDR",
6702                 "IDMA_FL_H_PUSH_CPL_FIFO",
6703                 "IDMA_FL_H_SEND_CPL",
6704                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6705                 "IDMA_FL_H_SEND_IP_HDR",
6706                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6707                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6708                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6709                 "IDMA_FL_D_SEND_PCIEHDR",
6710                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6711                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6712                 "IDMA_FL_SEND_PCIEHDR",
6713                 "IDMA_FL_PUSH_CPL_FIFO",
6714                 "IDMA_FL_SEND_CPL",
6715                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6716                 "IDMA_FL_SEND_PAYLOAD",
6717                 "IDMA_FL_REQ_NEXT_DATA_FL",
6718                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6719                 "IDMA_FL_SEND_PADDING",
6720                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6721         };
6722         static const u32 sge_regs[] = {
6723                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6724                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6725                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6726         };
6727         const char **sge_idma_decode;
6728         int sge_idma_decode_nstates;
6729         int i;
6730         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6731
6732         /* Select the right set of decode strings to dump depending on the
6733          * adapter chip type.
6734          */
6735         switch (chip_version) {
6736         case CHELSIO_T4:
6737                 sge_idma_decode = (const char **)t4_decode;
6738                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6739                 break;
6740
6741         case CHELSIO_T5:
6742                 sge_idma_decode = (const char **)t5_decode;
6743                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6744                 break;
6745
6746         case CHELSIO_T6:
6747                 sge_idma_decode = (const char **)t6_decode;
6748                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6749                 break;
6750
6751         default:
6752                 dev_err(adapter->pdev_dev,
6753                         "Unsupported chip version %d\n", chip_version);
6754                 return;
6755         }
6756
6757         if (is_t4(adapter->params.chip)) {
6758                 sge_idma_decode = (const char **)t4_decode;
6759                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6760         } else {
6761                 sge_idma_decode = (const char **)t5_decode;
6762                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6763         }
6764
6765         if (state < sge_idma_decode_nstates)
6766                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6767         else
6768                 CH_WARN(adapter, "idma state %d unknown\n", state);
6769
6770         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6771                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6772                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6773 }
6774
6775 /**
6776  *      t4_sge_ctxt_flush - flush the SGE context cache
6777  *      @adap: the adapter
6778  *      @mbox: mailbox to use for the FW command
6779  *      @ctxt_type: Egress or Ingress
6780  *
6781  *      Issues a FW command through the given mailbox to flush the
6782  *      SGE context cache.
6783  */
6784 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6785 {
6786         int ret;
6787         u32 ldst_addrspace;
6788         struct fw_ldst_cmd c;
6789
6790         memset(&c, 0, sizeof(c));
6791         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6792                                                  FW_LDST_ADDRSPC_SGE_EGRC :
6793                                                  FW_LDST_ADDRSPC_SGE_INGC);
6794         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6795                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6796                                         ldst_addrspace);
6797         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6798         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6799
6800         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6801         return ret;
6802 }
6803
6804 /**
6805  *      t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6806  *      @adap: the adapter
6807  *      @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6808  *      @dbqtimers: SGE Doorbell Queue Timer table
6809  *
6810  *      Reads the SGE Doorbell Queue Timer values into the provided table.
6811  *      Returns 0 on success (Firmware and Hardware support this feature),
6812  *      an error on failure.
6813  */
6814 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6815                           u16 *dbqtimers)
6816 {
6817         int ret, dbqtimerix;
6818
6819         ret = 0;
6820         dbqtimerix = 0;
6821         while (dbqtimerix < ndbqtimers) {
6822                 int nparams, param;
6823                 u32 params[7], vals[7];
6824
6825                 nparams = ndbqtimers - dbqtimerix;
6826                 if (nparams > ARRAY_SIZE(params))
6827                         nparams = ARRAY_SIZE(params);
6828
6829                 for (param = 0; param < nparams; param++)
6830                         params[param] =
6831                           (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6832                            FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
6833                            FW_PARAMS_PARAM_Y_V(dbqtimerix + param));
6834                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6835                                       nparams, params, vals);
6836                 if (ret)
6837                         break;
6838
6839                 for (param = 0; param < nparams; param++)
6840                         dbqtimers[dbqtimerix++] = vals[param];
6841         }
6842         return ret;
6843 }
6844
6845 /**
6846  *      t4_fw_hello - establish communication with FW
6847  *      @adap: the adapter
6848  *      @mbox: mailbox to use for the FW command
6849  *      @evt_mbox: mailbox to receive async FW events
6850  *      @master: specifies the caller's willingness to be the device master
6851  *      @state: returns the current device state (if non-NULL)
6852  *
6853  *      Issues a command to establish communication with FW.  Returns either
6854  *      an error (negative integer) or the mailbox of the Master PF.
6855  */
6856 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6857                 enum dev_master master, enum dev_state *state)
6858 {
6859         int ret;
6860         struct fw_hello_cmd c;
6861         u32 v;
6862         unsigned int master_mbox;
6863         int retries = FW_CMD_HELLO_RETRIES;
6864
6865 retry:
6866         memset(&c, 0, sizeof(c));
6867         INIT_CMD(c, HELLO, WRITE);
6868         c.err_to_clearinit = cpu_to_be32(
6869                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6870                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6871                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6872                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6873                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6874                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6875                 FW_HELLO_CMD_CLEARINIT_F);
6876
6877         /*
6878          * Issue the HELLO command to the firmware.  If it's not successful
6879          * but indicates that we got a "busy" or "timeout" condition, retry
6880          * the HELLO until we exhaust our retry limit.  If we do exceed our
6881          * retry limit, check to see if the firmware left us any error
6882          * information and report that if so.
6883          */
6884         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6885         if (ret < 0) {
6886                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6887                         goto retry;
6888                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6889                         t4_report_fw_error(adap);
6890                 return ret;
6891         }
6892
6893         v = be32_to_cpu(c.err_to_clearinit);
6894         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6895         if (state) {
6896                 if (v & FW_HELLO_CMD_ERR_F)
6897                         *state = DEV_STATE_ERR;
6898                 else if (v & FW_HELLO_CMD_INIT_F)
6899                         *state = DEV_STATE_INIT;
6900                 else
6901                         *state = DEV_STATE_UNINIT;
6902         }
6903
6904         /*
6905          * If we're not the Master PF then we need to wait around for the
6906          * Master PF Driver to finish setting up the adapter.
6907          *
6908          * Note that we also do this wait if we're a non-Master-capable PF and
6909          * there is no current Master PF; a Master PF may show up momentarily
6910          * and we wouldn't want to fail pointlessly.  (This can happen when an
6911          * OS loads lots of different drivers rapidly at the same time).  In
6912          * this case, the Master PF returned by the firmware will be
6913          * PCIE_FW_MASTER_M so the test below will work ...
6914          */
6915         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6916             master_mbox != mbox) {
6917                 int waiting = FW_CMD_HELLO_TIMEOUT;
6918
6919                 /*
6920                  * Wait for the firmware to either indicate an error or
6921                  * initialized state.  If we see either of these we bail out
6922                  * and report the issue to the caller.  If we exhaust the
6923                  * "hello timeout" and we haven't exhausted our retries, try
6924                  * again.  Otherwise bail with a timeout error.
6925                  */
6926                 for (;;) {
6927                         u32 pcie_fw;
6928
6929                         msleep(50);
6930                         waiting -= 50;
6931
6932                         /*
6933                          * If neither Error nor Initialized are indicated
6934                          * by the firmware keep waiting till we exhaust our
6935                          * timeout ... and then retry if we haven't exhausted
6936                          * our retries ...
6937                          */
6938                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6939                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6940                                 if (waiting <= 0) {
6941                                         if (retries-- > 0)
6942                                                 goto retry;
6943
6944                                         return -ETIMEDOUT;
6945                                 }
6946                                 continue;
6947                         }
6948
6949                         /*
6950                          * We either have an Error or Initialized condition
6951                          * report errors preferentially.
6952                          */
6953                         if (state) {
6954                                 if (pcie_fw & PCIE_FW_ERR_F)
6955                                         *state = DEV_STATE_ERR;
6956                                 else if (pcie_fw & PCIE_FW_INIT_F)
6957                                         *state = DEV_STATE_INIT;
6958                         }
6959
6960                         /*
6961                          * If we arrived before a Master PF was selected and
6962                          * there's not a valid Master PF, grab its identity
6963                          * for our caller.
6964                          */
6965                         if (master_mbox == PCIE_FW_MASTER_M &&
6966                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6967                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6968                         break;
6969                 }
6970         }
6971
6972         return master_mbox;
6973 }
6974
6975 /**
6976  *      t4_fw_bye - end communication with FW
6977  *      @adap: the adapter
6978  *      @mbox: mailbox to use for the FW command
6979  *
6980  *      Issues a command to terminate communication with FW.
6981  */
6982 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6983 {
6984         struct fw_bye_cmd c;
6985
6986         memset(&c, 0, sizeof(c));
6987         INIT_CMD(c, BYE, WRITE);
6988         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6989 }
6990
6991 /**
6992  *      t4_init_cmd - ask FW to initialize the device
6993  *      @adap: the adapter
6994  *      @mbox: mailbox to use for the FW command
6995  *
6996  *      Issues a command to FW to partially initialize the device.  This
6997  *      performs initialization that generally doesn't depend on user input.
6998  */
6999 int t4_early_init(struct adapter *adap, unsigned int mbox)
7000 {
7001         struct fw_initialize_cmd c;
7002
7003         memset(&c, 0, sizeof(c));
7004         INIT_CMD(c, INITIALIZE, WRITE);
7005         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7006 }
7007
7008 /**
7009  *      t4_fw_reset - issue a reset to FW
7010  *      @adap: the adapter
7011  *      @mbox: mailbox to use for the FW command
7012  *      @reset: specifies the type of reset to perform
7013  *
7014  *      Issues a reset command of the specified type to FW.
7015  */
7016 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7017 {
7018         struct fw_reset_cmd c;
7019
7020         memset(&c, 0, sizeof(c));
7021         INIT_CMD(c, RESET, WRITE);
7022         c.val = cpu_to_be32(reset);
7023         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7024 }
7025
7026 /**
7027  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7028  *      @adap: the adapter
7029  *      @mbox: mailbox to use for the FW RESET command (if desired)
7030  *      @force: force uP into RESET even if FW RESET command fails
7031  *
7032  *      Issues a RESET command to firmware (if desired) with a HALT indication
7033  *      and then puts the microprocessor into RESET state.  The RESET command
7034  *      will only be issued if a legitimate mailbox is provided (mbox <=
7035  *      PCIE_FW_MASTER_M).
7036  *
7037  *      This is generally used in order for the host to safely manipulate the
7038  *      adapter without fear of conflicting with whatever the firmware might
7039  *      be doing.  The only way out of this state is to RESTART the firmware
7040  *      ...
7041  */
7042 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7043 {
7044         int ret = 0;
7045
7046         /*
7047          * If a legitimate mailbox is provided, issue a RESET command
7048          * with a HALT indication.
7049          */
7050         if (mbox <= PCIE_FW_MASTER_M) {
7051                 struct fw_reset_cmd c;
7052
7053                 memset(&c, 0, sizeof(c));
7054                 INIT_CMD(c, RESET, WRITE);
7055                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
7056                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
7057                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7058         }
7059
7060         /*
7061          * Normally we won't complete the operation if the firmware RESET
7062          * command fails but if our caller insists we'll go ahead and put the
7063          * uP into RESET.  This can be useful if the firmware is hung or even
7064          * missing ...  We'll have to take the risk of putting the uP into
7065          * RESET without the cooperation of firmware in that case.
7066          *
7067          * We also force the firmware's HALT flag to be on in case we bypassed
7068          * the firmware RESET command above or we're dealing with old firmware
7069          * which doesn't have the HALT capability.  This will serve as a flag
7070          * for the incoming firmware to know that it's coming out of a HALT
7071          * rather than a RESET ... if it's new enough to understand that ...
7072          */
7073         if (ret == 0 || force) {
7074                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7075                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7076                                  PCIE_FW_HALT_F);
7077         }
7078
7079         /*
7080          * And we always return the result of the firmware RESET command
7081          * even when we force the uP into RESET ...
7082          */
7083         return ret;
7084 }
7085
7086 /**
7087  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
7088  *      @adap: the adapter
7089  *      @mbox: mailbox to use for the FW command
7090  *      @reset: if we want to do a RESET to restart things
7091  *
7092  *      Restart firmware previously halted by t4_fw_halt().  On successful
7093  *      return the previous PF Master remains as the new PF Master and there
7094  *      is no need to issue a new HELLO command, etc.
7095  *
7096  *      We do this in two ways:
7097  *
7098  *       1. If we're dealing with newer firmware we'll simply want to take
7099  *          the chip's microprocessor out of RESET.  This will cause the
7100  *          firmware to start up from its start vector.  And then we'll loop
7101  *          until the firmware indicates it's started again (PCIE_FW.HALT
7102  *          reset to 0) or we timeout.
7103  *
7104  *       2. If we're dealing with older firmware then we'll need to RESET
7105  *          the chip since older firmware won't recognize the PCIE_FW.HALT
7106  *          flag and automatically RESET itself on startup.
7107  */
7108 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7109 {
7110         if (reset) {
7111                 /*
7112                  * Since we're directing the RESET instead of the firmware
7113                  * doing it automatically, we need to clear the PCIE_FW.HALT
7114                  * bit.
7115                  */
7116                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7117
7118                 /*
7119                  * If we've been given a valid mailbox, first try to get the
7120                  * firmware to do the RESET.  If that works, great and we can
7121                  * return success.  Otherwise, if we haven't been given a
7122                  * valid mailbox or the RESET command failed, fall back to
7123                  * hitting the chip with a hammer.
7124                  */
7125                 if (mbox <= PCIE_FW_MASTER_M) {
7126                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7127                         msleep(100);
7128                         if (t4_fw_reset(adap, mbox,
7129                                         PIORST_F | PIORSTMODE_F) == 0)
7130                                 return 0;
7131                 }
7132
7133                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7134                 msleep(2000);
7135         } else {
7136                 int ms;
7137
7138                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7139                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7140                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7141                                 return 0;
7142                         msleep(100);
7143                         ms += 100;
7144                 }
7145                 return -ETIMEDOUT;
7146         }
7147         return 0;
7148 }
7149
7150 /**
7151  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7152  *      @adap: the adapter
7153  *      @mbox: mailbox to use for the FW RESET command (if desired)
7154  *      @fw_data: the firmware image to write
7155  *      @size: image size
7156  *      @force: force upgrade even if firmware doesn't cooperate
7157  *
7158  *      Perform all of the steps necessary for upgrading an adapter's
7159  *      firmware image.  Normally this requires the cooperation of the
7160  *      existing firmware in order to halt all existing activities
7161  *      but if an invalid mailbox token is passed in we skip that step
7162  *      (though we'll still put the adapter microprocessor into RESET in
7163  *      that case).
7164  *
7165  *      On successful return the new firmware will have been loaded and
7166  *      the adapter will have been fully RESET losing all previous setup
7167  *      state.  On unsuccessful return the adapter may be completely hosed ...
7168  *      positive errno indicates that the adapter is ~probably~ intact, a
7169  *      negative errno indicates that things are looking bad ...
7170  */
7171 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7172                   const u8 *fw_data, unsigned int size, int force)
7173 {
7174         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7175         int reset, ret;
7176
7177         if (!t4_fw_matches_chip(adap, fw_hdr))
7178                 return -EINVAL;
7179
7180         /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7181          * set wont be sent when we are flashing FW.
7182          */
7183         adap->flags &= ~CXGB4_FW_OK;
7184
7185         ret = t4_fw_halt(adap, mbox, force);
7186         if (ret < 0 && !force)
7187                 goto out;
7188
7189         ret = t4_load_fw(adap, fw_data, size);
7190         if (ret < 0)
7191                 goto out;
7192
7193         /*
7194          * If there was a Firmware Configuration File stored in FLASH,
7195          * there's a good chance that it won't be compatible with the new
7196          * Firmware.  In order to prevent difficult to diagnose adapter
7197          * initialization issues, we clear out the Firmware Configuration File
7198          * portion of the FLASH .  The user will need to re-FLASH a new
7199          * Firmware Configuration File which is compatible with the new
7200          * Firmware if that's desired.
7201          */
7202         (void)t4_load_cfg(adap, NULL, 0);
7203
7204         /*
7205          * Older versions of the firmware don't understand the new
7206          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7207          * restart.  So for newly loaded older firmware we'll have to do the
7208          * RESET for it so it starts up on a clean slate.  We can tell if
7209          * the newly loaded firmware will handle this right by checking
7210          * its header flags to see if it advertises the capability.
7211          */
7212         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7213         ret = t4_fw_restart(adap, mbox, reset);
7214
7215         /* Grab potentially new Firmware Device Log parameters so we can see
7216          * how healthy the new Firmware is.  It's okay to contact the new
7217          * Firmware for these parameters even though, as far as it's
7218          * concerned, we've never said "HELLO" to it ...
7219          */
7220         (void)t4_init_devlog_params(adap);
7221 out:
7222         adap->flags |= CXGB4_FW_OK;
7223         return ret;
7224 }
7225
7226 /**
7227  *      t4_fl_pkt_align - return the fl packet alignment
7228  *      @adap: the adapter
7229  *
7230  *      T4 has a single field to specify the packing and padding boundary.
7231  *      T5 onwards has separate fields for this and hence the alignment for
7232  *      next packet offset is maximum of these two.
7233  *
7234  */
7235 int t4_fl_pkt_align(struct adapter *adap)
7236 {
7237         u32 sge_control, sge_control2;
7238         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7239
7240         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7241
7242         /* T4 uses a single control field to specify both the PCIe Padding and
7243          * Packing Boundary.  T5 introduced the ability to specify these
7244          * separately.  The actual Ingress Packet Data alignment boundary
7245          * within Packed Buffer Mode is the maximum of these two
7246          * specifications.  (Note that it makes no real practical sense to
7247          * have the Padding Boundary be larger than the Packing Boundary but you
7248          * could set the chip up that way and, in fact, legacy T4 code would
7249          * end doing this because it would initialize the Padding Boundary and
7250          * leave the Packing Boundary initialized to 0 (16 bytes).)
7251          * Padding Boundary values in T6 starts from 8B,
7252          * where as it is 32B for T4 and T5.
7253          */
7254         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7255                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7256         else
7257                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7258
7259         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7260
7261         fl_align = ingpadboundary;
7262         if (!is_t4(adap->params.chip)) {
7263                 /* T5 has a weird interpretation of one of the PCIe Packing
7264                  * Boundary values.  No idea why ...
7265                  */
7266                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7267                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7268                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7269                         ingpackboundary = 16;
7270                 else
7271                         ingpackboundary = 1 << (ingpackboundary +
7272                                                 INGPACKBOUNDARY_SHIFT_X);
7273
7274                 fl_align = max(ingpadboundary, ingpackboundary);
7275         }
7276         return fl_align;
7277 }
7278
7279 /**
7280  *      t4_fixup_host_params - fix up host-dependent parameters
7281  *      @adap: the adapter
7282  *      @page_size: the host's Base Page Size
7283  *      @cache_line_size: the host's Cache Line Size
7284  *
7285  *      Various registers in T4 contain values which are dependent on the
7286  *      host's Base Page and Cache Line Sizes.  This function will fix all of
7287  *      those registers with the appropriate values as passed in ...
7288  */
7289 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7290                          unsigned int cache_line_size)
7291 {
7292         unsigned int page_shift = fls(page_size) - 1;
7293         unsigned int sge_hps = page_shift - 10;
7294         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7295         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7296         unsigned int fl_align_log = fls(fl_align) - 1;
7297
7298         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7299                      HOSTPAGESIZEPF0_V(sge_hps) |
7300                      HOSTPAGESIZEPF1_V(sge_hps) |
7301                      HOSTPAGESIZEPF2_V(sge_hps) |
7302                      HOSTPAGESIZEPF3_V(sge_hps) |
7303                      HOSTPAGESIZEPF4_V(sge_hps) |
7304                      HOSTPAGESIZEPF5_V(sge_hps) |
7305                      HOSTPAGESIZEPF6_V(sge_hps) |
7306                      HOSTPAGESIZEPF7_V(sge_hps));
7307
7308         if (is_t4(adap->params.chip)) {
7309                 t4_set_reg_field(adap, SGE_CONTROL_A,
7310                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7311                                  EGRSTATUSPAGESIZE_F,
7312                                  INGPADBOUNDARY_V(fl_align_log -
7313                                                   INGPADBOUNDARY_SHIFT_X) |
7314                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7315         } else {
7316                 unsigned int pack_align;
7317                 unsigned int ingpad, ingpack;
7318
7319                 /* T5 introduced the separation of the Free List Padding and
7320                  * Packing Boundaries.  Thus, we can select a smaller Padding
7321                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
7322                  * Bandwidth, and use a Packing Boundary which is large enough
7323                  * to avoid false sharing between CPUs, etc.
7324                  *
7325                  * For the PCI Link, the smaller the Padding Boundary the
7326                  * better.  For the Memory Controller, a smaller Padding
7327                  * Boundary is better until we cross under the Memory Line
7328                  * Size (the minimum unit of transfer to/from Memory).  If we
7329                  * have a Padding Boundary which is smaller than the Memory
7330                  * Line Size, that'll involve a Read-Modify-Write cycle on the
7331                  * Memory Controller which is never good.
7332                  */
7333
7334                 /* We want the Packing Boundary to be based on the Cache Line
7335                  * Size in order to help avoid False Sharing performance
7336                  * issues between CPUs, etc.  We also want the Packing
7337                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
7338                  * get best performance when the Packing Boundary is a
7339                  * multiple of the Maximum Payload Size.
7340                  */
7341                 pack_align = fl_align;
7342                 if (pci_is_pcie(adap->pdev)) {
7343                         unsigned int mps, mps_log;
7344                         u16 devctl;
7345
7346                         /* The PCIe Device Control Maximum Payload Size field
7347                          * [bits 7:5] encodes sizes as powers of 2 starting at
7348                          * 128 bytes.
7349                          */
7350                         pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7351                                                   &devctl);
7352                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7353                         mps = 1 << mps_log;
7354                         if (mps > pack_align)
7355                                 pack_align = mps;
7356                 }
7357
7358                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7359                  * value for the Packing Boundary.  This corresponds to 16
7360                  * bytes instead of the expected 32 bytes.  So if we want 32
7361                  * bytes, the best we can really do is 64 bytes ...
7362                  */
7363                 if (pack_align <= 16) {
7364                         ingpack = INGPACKBOUNDARY_16B_X;
7365                         fl_align = 16;
7366                 } else if (pack_align == 32) {
7367                         ingpack = INGPACKBOUNDARY_64B_X;
7368                         fl_align = 64;
7369                 } else {
7370                         unsigned int pack_align_log = fls(pack_align) - 1;
7371
7372                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7373                         fl_align = pack_align;
7374                 }
7375
7376                 /* Use the smallest Ingress Padding which isn't smaller than
7377                  * the Memory Controller Read/Write Size.  We'll take that as
7378                  * being 8 bytes since we don't know of any system with a
7379                  * wider Memory Controller Bus Width.
7380                  */
7381                 if (is_t5(adap->params.chip))
7382                         ingpad = INGPADBOUNDARY_32B_X;
7383                 else
7384                         ingpad = T6_INGPADBOUNDARY_8B_X;
7385
7386                 t4_set_reg_field(adap, SGE_CONTROL_A,
7387                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7388                                  EGRSTATUSPAGESIZE_F,
7389                                  INGPADBOUNDARY_V(ingpad) |
7390                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7391                 t4_set_reg_field(adap, SGE_CONTROL2_A,
7392                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7393                                  INGPACKBOUNDARY_V(ingpack));
7394         }
7395         /*
7396          * Adjust various SGE Free List Host Buffer Sizes.
7397          *
7398          * This is something of a crock since we're using fixed indices into
7399          * the array which are also known by the sge.c code and the T4
7400          * Firmware Configuration File.  We need to come up with a much better
7401          * approach to managing this array.  For now, the first four entries
7402          * are:
7403          *
7404          *   0: Host Page Size
7405          *   1: 64KB
7406          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7407          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7408          *
7409          * For the single-MTU buffers in unpacked mode we need to include
7410          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7411          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7412          * Padding boundary.  All of these are accommodated in the Factory
7413          * Default Firmware Configuration File but we need to adjust it for
7414          * this host's cache line size.
7415          */
7416         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7417         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7418                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7419                      & ~(fl_align-1));
7420         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7421                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7422                      & ~(fl_align-1));
7423
7424         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7425
7426         return 0;
7427 }
7428
7429 /**
7430  *      t4_fw_initialize - ask FW to initialize the device
7431  *      @adap: the adapter
7432  *      @mbox: mailbox to use for the FW command
7433  *
7434  *      Issues a command to FW to partially initialize the device.  This
7435  *      performs initialization that generally doesn't depend on user input.
7436  */
7437 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7438 {
7439         struct fw_initialize_cmd c;
7440
7441         memset(&c, 0, sizeof(c));
7442         INIT_CMD(c, INITIALIZE, WRITE);
7443         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7444 }
7445
7446 /**
7447  *      t4_query_params_rw - query FW or device parameters
7448  *      @adap: the adapter
7449  *      @mbox: mailbox to use for the FW command
7450  *      @pf: the PF
7451  *      @vf: the VF
7452  *      @nparams: the number of parameters
7453  *      @params: the parameter names
7454  *      @val: the parameter values
7455  *      @rw: Write and read flag
7456  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7457  *
7458  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7459  *      queried at once.
7460  */
7461 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7462                        unsigned int vf, unsigned int nparams, const u32 *params,
7463                        u32 *val, int rw, bool sleep_ok)
7464 {
7465         int i, ret;
7466         struct fw_params_cmd c;
7467         __be32 *p = &c.param[0].mnem;
7468
7469         if (nparams > 7)
7470                 return -EINVAL;
7471
7472         memset(&c, 0, sizeof(c));
7473         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7474                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7475                                   FW_PARAMS_CMD_PFN_V(pf) |
7476                                   FW_PARAMS_CMD_VFN_V(vf));
7477         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7478
7479         for (i = 0; i < nparams; i++) {
7480                 *p++ = cpu_to_be32(*params++);
7481                 if (rw)
7482                         *p = cpu_to_be32(*(val + i));
7483                 p++;
7484         }
7485
7486         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7487         if (ret == 0)
7488                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7489                         *val++ = be32_to_cpu(*p);
7490         return ret;
7491 }
7492
7493 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7494                     unsigned int vf, unsigned int nparams, const u32 *params,
7495                     u32 *val)
7496 {
7497         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7498                                   true);
7499 }
7500
7501 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7502                        unsigned int vf, unsigned int nparams, const u32 *params,
7503                        u32 *val)
7504 {
7505         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7506                                   false);
7507 }
7508
7509 /**
7510  *      t4_set_params_timeout - sets FW or device parameters
7511  *      @adap: the adapter
7512  *      @mbox: mailbox to use for the FW command
7513  *      @pf: the PF
7514  *      @vf: the VF
7515  *      @nparams: the number of parameters
7516  *      @params: the parameter names
7517  *      @val: the parameter values
7518  *      @timeout: the timeout time
7519  *
7520  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7521  *      specified at once.
7522  */
7523 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7524                           unsigned int pf, unsigned int vf,
7525                           unsigned int nparams, const u32 *params,
7526                           const u32 *val, int timeout)
7527 {
7528         struct fw_params_cmd c;
7529         __be32 *p = &c.param[0].mnem;
7530
7531         if (nparams > 7)
7532                 return -EINVAL;
7533
7534         memset(&c, 0, sizeof(c));
7535         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7536                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7537                                   FW_PARAMS_CMD_PFN_V(pf) |
7538                                   FW_PARAMS_CMD_VFN_V(vf));
7539         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7540
7541         while (nparams--) {
7542                 *p++ = cpu_to_be32(*params++);
7543                 *p++ = cpu_to_be32(*val++);
7544         }
7545
7546         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7547 }
7548
7549 /**
7550  *      t4_set_params - sets FW or device parameters
7551  *      @adap: the adapter
7552  *      @mbox: mailbox to use for the FW command
7553  *      @pf: the PF
7554  *      @vf: the VF
7555  *      @nparams: the number of parameters
7556  *      @params: the parameter names
7557  *      @val: the parameter values
7558  *
7559  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7560  *      specified at once.
7561  */
7562 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7563                   unsigned int vf, unsigned int nparams, const u32 *params,
7564                   const u32 *val)
7565 {
7566         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7567                                      FW_CMD_MAX_TIMEOUT);
7568 }
7569
7570 /**
7571  *      t4_cfg_pfvf - configure PF/VF resource limits
7572  *      @adap: the adapter
7573  *      @mbox: mailbox to use for the FW command
7574  *      @pf: the PF being configured
7575  *      @vf: the VF being configured
7576  *      @txq: the max number of egress queues
7577  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7578  *      @rxqi: the max number of interrupt-capable ingress queues
7579  *      @rxq: the max number of interruptless ingress queues
7580  *      @tc: the PCI traffic class
7581  *      @vi: the max number of virtual interfaces
7582  *      @cmask: the channel access rights mask for the PF/VF
7583  *      @pmask: the port access rights mask for the PF/VF
7584  *      @nexact: the maximum number of exact MPS filters
7585  *      @rcaps: read capabilities
7586  *      @wxcaps: write/execute capabilities
7587  *
7588  *      Configures resource limits and capabilities for a physical or virtual
7589  *      function.
7590  */
7591 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7592                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7593                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7594                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7595                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7596 {
7597         struct fw_pfvf_cmd c;
7598
7599         memset(&c, 0, sizeof(c));
7600         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7601                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7602                                   FW_PFVF_CMD_VFN_V(vf));
7603         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7604         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7605                                      FW_PFVF_CMD_NIQ_V(rxq));
7606         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7607                                     FW_PFVF_CMD_PMASK_V(pmask) |
7608                                     FW_PFVF_CMD_NEQ_V(txq));
7609         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7610                                       FW_PFVF_CMD_NVI_V(vi) |
7611                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7612         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7613                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7614                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7615         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7616 }
7617
7618 /**
7619  *      t4_alloc_vi - allocate a virtual interface
7620  *      @adap: the adapter
7621  *      @mbox: mailbox to use for the FW command
7622  *      @port: physical port associated with the VI
7623  *      @pf: the PF owning the VI
7624  *      @vf: the VF owning the VI
7625  *      @nmac: number of MAC addresses needed (1 to 5)
7626  *      @mac: the MAC addresses of the VI
7627  *      @rss_size: size of RSS table slice associated with this VI
7628  *      @vivld: the destination to store the VI Valid value.
7629  *      @vin: the destination to store the VIN value.
7630  *
7631  *      Allocates a virtual interface for the given physical port.  If @mac is
7632  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7633  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7634  *      stored consecutively so the space needed is @nmac * 6 bytes.
7635  *      Returns a negative error number or the non-negative VI id.
7636  */
7637 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7638                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7639                 unsigned int *rss_size, u8 *vivld, u8 *vin)
7640 {
7641         int ret;
7642         struct fw_vi_cmd c;
7643
7644         memset(&c, 0, sizeof(c));
7645         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7646                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7647                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7648         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7649         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7650         c.nmac = nmac - 1;
7651
7652         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7653         if (ret)
7654                 return ret;
7655
7656         if (mac) {
7657                 memcpy(mac, c.mac, sizeof(c.mac));
7658                 switch (nmac) {
7659                 case 5:
7660                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7661                         fallthrough;
7662                 case 4:
7663                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7664                         fallthrough;
7665                 case 3:
7666                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7667                         fallthrough;
7668                 case 2:
7669                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7670                 }
7671         }
7672         if (rss_size)
7673                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7674
7675         if (vivld)
7676                 *vivld = FW_VI_CMD_VFVLD_G(be32_to_cpu(c.alloc_to_len16));
7677
7678         if (vin)
7679                 *vin = FW_VI_CMD_VIN_G(be32_to_cpu(c.alloc_to_len16));
7680
7681         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7682 }
7683
7684 /**
7685  *      t4_free_vi - free a virtual interface
7686  *      @adap: the adapter
7687  *      @mbox: mailbox to use for the FW command
7688  *      @pf: the PF owning the VI
7689  *      @vf: the VF owning the VI
7690  *      @viid: virtual interface identifiler
7691  *
7692  *      Free a previously allocated virtual interface.
7693  */
7694 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7695                unsigned int vf, unsigned int viid)
7696 {
7697         struct fw_vi_cmd c;
7698
7699         memset(&c, 0, sizeof(c));
7700         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7701                                   FW_CMD_REQUEST_F |
7702                                   FW_CMD_EXEC_F |
7703                                   FW_VI_CMD_PFN_V(pf) |
7704                                   FW_VI_CMD_VFN_V(vf));
7705         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7706         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7707
7708         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7709 }
7710
7711 /**
7712  *      t4_set_rxmode - set Rx properties of a virtual interface
7713  *      @adap: the adapter
7714  *      @mbox: mailbox to use for the FW command
7715  *      @viid: the VI id
7716  *      @viid_mirror: the mirror VI id
7717  *      @mtu: the new MTU or -1
7718  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7719  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7720  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7721  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7722  *      @sleep_ok: if true we may sleep while awaiting command completion
7723  *
7724  *      Sets Rx properties of a virtual interface.
7725  */
7726 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7727                   unsigned int viid_mirror, int mtu, int promisc, int all_multi,
7728                   int bcast, int vlanex, bool sleep_ok)
7729 {
7730         struct fw_vi_rxmode_cmd c, c_mirror;
7731         int ret;
7732
7733         /* convert to FW values */
7734         if (mtu < 0)
7735                 mtu = FW_RXMODE_MTU_NO_CHG;
7736         if (promisc < 0)
7737                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7738         if (all_multi < 0)
7739                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7740         if (bcast < 0)
7741                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7742         if (vlanex < 0)
7743                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7744
7745         memset(&c, 0, sizeof(c));
7746         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7747                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7748                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7749         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7750         c.mtu_to_vlanexen =
7751                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7752                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7753                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7754                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7755                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7756
7757         if (viid_mirror) {
7758                 memcpy(&c_mirror, &c, sizeof(c_mirror));
7759                 c_mirror.op_to_viid =
7760                         cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7761                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7762                                     FW_VI_RXMODE_CMD_VIID_V(viid_mirror));
7763         }
7764
7765         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7766         if (ret)
7767                 return ret;
7768
7769         if (viid_mirror)
7770                 ret = t4_wr_mbox_meat(adap, mbox, &c_mirror, sizeof(c_mirror),
7771                                       NULL, sleep_ok);
7772
7773         return ret;
7774 }
7775
7776 /**
7777  *      t4_free_encap_mac_filt - frees MPS entry at given index
7778  *      @adap: the adapter
7779  *      @viid: the VI id
7780  *      @idx: index of MPS entry to be freed
7781  *      @sleep_ok: call is allowed to sleep
7782  *
7783  *      Frees the MPS entry at supplied index
7784  *
7785  *      Returns a negative error number or zero on success
7786  */
7787 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7788                            int idx, bool sleep_ok)
7789 {
7790         struct fw_vi_mac_exact *p;
7791         u8 addr[] = {0, 0, 0, 0, 0, 0};
7792         struct fw_vi_mac_cmd c;
7793         int ret = 0;
7794         u32 exact;
7795
7796         memset(&c, 0, sizeof(c));
7797         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7798                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7799                                    FW_CMD_EXEC_V(0) |
7800                                    FW_VI_MAC_CMD_VIID_V(viid));
7801         exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7802         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7803                                           exact |
7804                                           FW_CMD_LEN16_V(1));
7805         p = c.u.exact;
7806         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7807                                       FW_VI_MAC_CMD_IDX_V(idx));
7808         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7809         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7810         return ret;
7811 }
7812
7813 /**
7814  *      t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7815  *      @adap: the adapter
7816  *      @viid: the VI id
7817  *      @addr: the MAC address
7818  *      @mask: the mask
7819  *      @idx: index of the entry in mps tcam
7820  *      @lookup_type: MAC address for inner (1) or outer (0) header
7821  *      @port_id: the port index
7822  *      @sleep_ok: call is allowed to sleep
7823  *
7824  *      Removes the mac entry at the specified index using raw mac interface.
7825  *
7826  *      Returns a negative error number on failure.
7827  */
7828 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7829                          const u8 *addr, const u8 *mask, unsigned int idx,
7830                          u8 lookup_type, u8 port_id, bool sleep_ok)
7831 {
7832         struct fw_vi_mac_cmd c;
7833         struct fw_vi_mac_raw *p = &c.u.raw;
7834         u32 val;
7835
7836         memset(&c, 0, sizeof(c));
7837         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7838                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7839                                    FW_CMD_EXEC_V(0) |
7840                                    FW_VI_MAC_CMD_VIID_V(viid));
7841         val = FW_CMD_LEN16_V(1) |
7842               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7843         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7844                                           FW_CMD_LEN16_V(val));
7845
7846         p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7847                                      FW_VI_MAC_ID_BASED_FREE);
7848
7849         /* Lookup Type. Outer header: 0, Inner header: 1 */
7850         p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7851                                    DATAPORTNUM_V(port_id));
7852         /* Lookup mask and port mask */
7853         p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7854                                     DATAPORTNUM_V(DATAPORTNUM_M));
7855
7856         /* Copy the address and the mask */
7857         memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7858         memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7859
7860         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7861 }
7862
7863 /**
7864  *      t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7865  *      @adap: the adapter
7866  *      @viid: the VI id
7867  *      @addr: the MAC address
7868  *      @mask: the mask
7869  *      @vni: the VNI id for the tunnel protocol
7870  *      @vni_mask: mask for the VNI id
7871  *      @dip_hit: to enable DIP match for the MPS entry
7872  *      @lookup_type: MAC address for inner (1) or outer (0) header
7873  *      @sleep_ok: call is allowed to sleep
7874  *
7875  *      Allocates an MPS entry with specified MAC address and VNI value.
7876  *
7877  *      Returns a negative error number or the allocated index for this mac.
7878  */
7879 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7880                             const u8 *addr, const u8 *mask, unsigned int vni,
7881                             unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7882                             bool sleep_ok)
7883 {
7884         struct fw_vi_mac_cmd c;
7885         struct fw_vi_mac_vni *p = c.u.exact_vni;
7886         int ret = 0;
7887         u32 val;
7888
7889         memset(&c, 0, sizeof(c));
7890         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7891                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7892                                    FW_VI_MAC_CMD_VIID_V(viid));
7893         val = FW_CMD_LEN16_V(1) |
7894               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7895         c.freemacs_to_len16 = cpu_to_be32(val);
7896         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7897                                       FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7898         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7899         memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7900
7901         p->lookup_type_to_vni =
7902                 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7903                             FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7904                             FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7905         p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7906         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7907         if (ret == 0)
7908                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7909         return ret;
7910 }
7911
7912 /**
7913  *      t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7914  *      @adap: the adapter
7915  *      @viid: the VI id
7916  *      @addr: the MAC address
7917  *      @mask: the mask
7918  *      @idx: index at which to add this entry
7919  *      @lookup_type: MAC address for inner (1) or outer (0) header
7920  *      @port_id: the port index
7921  *      @sleep_ok: call is allowed to sleep
7922  *
7923  *      Adds the mac entry at the specified index using raw mac interface.
7924  *
7925  *      Returns a negative error number or the allocated index for this mac.
7926  */
7927 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7928                           const u8 *addr, const u8 *mask, unsigned int idx,
7929                           u8 lookup_type, u8 port_id, bool sleep_ok)
7930 {
7931         int ret = 0;
7932         struct fw_vi_mac_cmd c;
7933         struct fw_vi_mac_raw *p = &c.u.raw;
7934         u32 val;
7935
7936         memset(&c, 0, sizeof(c));
7937         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7938                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7939                                    FW_VI_MAC_CMD_VIID_V(viid));
7940         val = FW_CMD_LEN16_V(1) |
7941               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7942         c.freemacs_to_len16 = cpu_to_be32(val);
7943
7944         /* Specify that this is an inner mac address */
7945         p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7946
7947         /* Lookup Type. Outer header: 0, Inner header: 1 */
7948         p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7949                                    DATAPORTNUM_V(port_id));
7950         /* Lookup mask and port mask */
7951         p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7952                                     DATAPORTNUM_V(DATAPORTNUM_M));
7953
7954         /* Copy the address and the mask */
7955         memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7956         memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7957
7958         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7959         if (ret == 0) {
7960                 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7961                 if (ret != idx)
7962                         ret = -ENOMEM;
7963         }
7964
7965         return ret;
7966 }
7967
7968 /**
7969  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7970  *      @adap: the adapter
7971  *      @mbox: mailbox to use for the FW command
7972  *      @viid: the VI id
7973  *      @free: if true any existing filters for this VI id are first removed
7974  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7975  *      @addr: the MAC address(es)
7976  *      @idx: where to store the index of each allocated filter
7977  *      @hash: pointer to hash address filter bitmap
7978  *      @sleep_ok: call is allowed to sleep
7979  *
7980  *      Allocates an exact-match filter for each of the supplied addresses and
7981  *      sets it to the corresponding address.  If @idx is not %NULL it should
7982  *      have at least @naddr entries, each of which will be set to the index of
7983  *      the filter allocated for the corresponding MAC address.  If a filter
7984  *      could not be allocated for an address its index is set to 0xffff.
7985  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7986  *      are hashed and update the hash filter bitmap pointed at by @hash.
7987  *
7988  *      Returns a negative error number or the number of filters allocated.
7989  */
7990 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7991                       unsigned int viid, bool free, unsigned int naddr,
7992                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7993 {
7994         int offset, ret = 0;
7995         struct fw_vi_mac_cmd c;
7996         unsigned int nfilters = 0;
7997         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7998         unsigned int rem = naddr;
7999
8000         if (naddr > max_naddr)
8001                 return -EINVAL;
8002
8003         for (offset = 0; offset < naddr ; /**/) {
8004                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
8005                                          rem : ARRAY_SIZE(c.u.exact));
8006                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8007                                                      u.exact[fw_naddr]), 16);
8008                 struct fw_vi_mac_exact *p;
8009                 int i;
8010
8011                 memset(&c, 0, sizeof(c));
8012                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8013                                            FW_CMD_REQUEST_F |
8014                                            FW_CMD_WRITE_F |
8015                                            FW_CMD_EXEC_V(free) |
8016                                            FW_VI_MAC_CMD_VIID_V(viid));
8017                 c.freemacs_to_len16 =
8018                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
8019                                     FW_CMD_LEN16_V(len16));
8020
8021                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8022                         p->valid_to_idx =
8023                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8024                                             FW_VI_MAC_CMD_IDX_V(
8025                                                     FW_VI_MAC_ADD_MAC));
8026                         memcpy(p->macaddr, addr[offset + i],
8027                                sizeof(p->macaddr));
8028                 }
8029
8030                 /* It's okay if we run out of space in our MAC address arena.
8031                  * Some of the addresses we submit may get stored so we need
8032                  * to run through the reply to see what the results were ...
8033                  */
8034                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8035                 if (ret && ret != -FW_ENOMEM)
8036                         break;
8037
8038                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8039                         u16 index = FW_VI_MAC_CMD_IDX_G(
8040                                         be16_to_cpu(p->valid_to_idx));
8041
8042                         if (idx)
8043                                 idx[offset + i] = (index >= max_naddr ?
8044                                                    0xffff : index);
8045                         if (index < max_naddr)
8046                                 nfilters++;
8047                         else if (hash)
8048                                 *hash |= (1ULL <<
8049                                           hash_mac_addr(addr[offset + i]));
8050                 }
8051
8052                 free = false;
8053                 offset += fw_naddr;
8054                 rem -= fw_naddr;
8055         }
8056
8057         if (ret == 0 || ret == -FW_ENOMEM)
8058                 ret = nfilters;
8059         return ret;
8060 }
8061
8062 /**
8063  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
8064  *      @adap: the adapter
8065  *      @mbox: mailbox to use for the FW command
8066  *      @viid: the VI id
8067  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
8068  *      @addr: the MAC address(es)
8069  *      @sleep_ok: call is allowed to sleep
8070  *
8071  *      Frees the exact-match filter for each of the supplied addresses
8072  *
8073  *      Returns a negative error number or the number of filters freed.
8074  */
8075 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8076                      unsigned int viid, unsigned int naddr,
8077                      const u8 **addr, bool sleep_ok)
8078 {
8079         int offset, ret = 0;
8080         struct fw_vi_mac_cmd c;
8081         unsigned int nfilters = 0;
8082         unsigned int max_naddr = is_t4(adap->params.chip) ?
8083                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
8084                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8085         unsigned int rem = naddr;
8086
8087         if (naddr > max_naddr)
8088                 return -EINVAL;
8089
8090         for (offset = 0; offset < (int)naddr ; /**/) {
8091                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8092                                          ? rem
8093                                          : ARRAY_SIZE(c.u.exact));
8094                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8095                                                      u.exact[fw_naddr]), 16);
8096                 struct fw_vi_mac_exact *p;
8097                 int i;
8098
8099                 memset(&c, 0, sizeof(c));
8100                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8101                                      FW_CMD_REQUEST_F |
8102                                      FW_CMD_WRITE_F |
8103                                      FW_CMD_EXEC_V(0) |
8104                                      FW_VI_MAC_CMD_VIID_V(viid));
8105                 c.freemacs_to_len16 =
8106                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8107                                             FW_CMD_LEN16_V(len16));
8108
8109                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8110                         p->valid_to_idx = cpu_to_be16(
8111                                 FW_VI_MAC_CMD_VALID_F |
8112                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
8113                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8114                 }
8115
8116                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8117                 if (ret)
8118                         break;
8119
8120                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8121                         u16 index = FW_VI_MAC_CMD_IDX_G(
8122                                                 be16_to_cpu(p->valid_to_idx));
8123
8124                         if (index < max_naddr)
8125                                 nfilters++;
8126                 }
8127
8128                 offset += fw_naddr;
8129                 rem -= fw_naddr;
8130         }
8131
8132         if (ret == 0)
8133                 ret = nfilters;
8134         return ret;
8135 }
8136
8137 /**
8138  *      t4_change_mac - modifies the exact-match filter for a MAC address
8139  *      @adap: the adapter
8140  *      @mbox: mailbox to use for the FW command
8141  *      @viid: the VI id
8142  *      @idx: index of existing filter for old value of MAC address, or -1
8143  *      @addr: the new MAC address value
8144  *      @persist: whether a new MAC allocation should be persistent
8145  *      @smt_idx: the destination to store the new SMT index.
8146  *
8147  *      Modifies an exact-match filter and sets it to the new MAC address.
8148  *      Note that in general it is not possible to modify the value of a given
8149  *      filter so the generic way to modify an address filter is to free the one
8150  *      being used by the old address value and allocate a new filter for the
8151  *      new address value.  @idx can be -1 if the address is a new addition.
8152  *
8153  *      Returns a negative error number or the index of the filter with the new
8154  *      MAC value.
8155  */
8156 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8157                   int idx, const u8 *addr, bool persist, u8 *smt_idx)
8158 {
8159         int ret, mode;
8160         struct fw_vi_mac_cmd c;
8161         struct fw_vi_mac_exact *p = c.u.exact;
8162         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8163
8164         if (idx < 0)                             /* new allocation */
8165                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8166         mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8167
8168         memset(&c, 0, sizeof(c));
8169         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8170                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8171                                    FW_VI_MAC_CMD_VIID_V(viid));
8172         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
8173         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8174                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
8175                                       FW_VI_MAC_CMD_IDX_V(idx));
8176         memcpy(p->macaddr, addr, sizeof(p->macaddr));
8177
8178         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8179         if (ret == 0) {
8180                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8181                 if (ret >= max_mac_addr)
8182                         ret = -ENOMEM;
8183                 if (smt_idx) {
8184                         if (adap->params.viid_smt_extn_support) {
8185                                 *smt_idx = FW_VI_MAC_CMD_SMTID_G
8186                                                     (be32_to_cpu(c.op_to_viid));
8187                         } else {
8188                                 /* In T4/T5, SMT contains 256 SMAC entries
8189                                  * organized in 128 rows of 2 entries each.
8190                                  * In T6, SMT contains 256 SMAC entries in
8191                                  * 256 rows.
8192                                  */
8193                                 if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8194                                                                      CHELSIO_T5)
8195                                         *smt_idx = (viid & FW_VIID_VIN_M) << 1;
8196                                 else
8197                                         *smt_idx = (viid & FW_VIID_VIN_M);
8198                         }
8199                 }
8200         }
8201         return ret;
8202 }
8203
8204 /**
8205  *      t4_set_addr_hash - program the MAC inexact-match hash filter
8206  *      @adap: the adapter
8207  *      @mbox: mailbox to use for the FW command
8208  *      @viid: the VI id
8209  *      @ucast: whether the hash filter should also match unicast addresses
8210  *      @vec: the value to be written to the hash filter
8211  *      @sleep_ok: call is allowed to sleep
8212  *
8213  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
8214  */
8215 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8216                      bool ucast, u64 vec, bool sleep_ok)
8217 {
8218         struct fw_vi_mac_cmd c;
8219
8220         memset(&c, 0, sizeof(c));
8221         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8222                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8223                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8224         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8225                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8226                                           FW_CMD_LEN16_V(1));
8227         c.u.hash.hashvec = cpu_to_be64(vec);
8228         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8229 }
8230
8231 /**
8232  *      t4_enable_vi_params - enable/disable a virtual interface
8233  *      @adap: the adapter
8234  *      @mbox: mailbox to use for the FW command
8235  *      @viid: the VI id
8236  *      @rx_en: 1=enable Rx, 0=disable Rx
8237  *      @tx_en: 1=enable Tx, 0=disable Tx
8238  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8239  *
8240  *      Enables/disables a virtual interface.  Note that setting DCB Enable
8241  *      only makes sense when enabling a Virtual Interface ...
8242  */
8243 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8244                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8245 {
8246         struct fw_vi_enable_cmd c;
8247
8248         memset(&c, 0, sizeof(c));
8249         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8250                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8251                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8252         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8253                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8254                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8255                                      FW_LEN16(c));
8256         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8257 }
8258
8259 /**
8260  *      t4_enable_vi - enable/disable a virtual interface
8261  *      @adap: the adapter
8262  *      @mbox: mailbox to use for the FW command
8263  *      @viid: the VI id
8264  *      @rx_en: 1=enable Rx, 0=disable Rx
8265  *      @tx_en: 1=enable Tx, 0=disable Tx
8266  *
8267  *      Enables/disables a virtual interface.
8268  */
8269 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8270                  bool rx_en, bool tx_en)
8271 {
8272         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8273 }
8274
8275 /**
8276  *      t4_enable_pi_params - enable/disable a Port's Virtual Interface
8277  *      @adap: the adapter
8278  *      @mbox: mailbox to use for the FW command
8279  *      @pi: the Port Information structure
8280  *      @rx_en: 1=enable Rx, 0=disable Rx
8281  *      @tx_en: 1=enable Tx, 0=disable Tx
8282  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8283  *
8284  *      Enables/disables a Port's Virtual Interface.  Note that setting DCB
8285  *      Enable only makes sense when enabling a Virtual Interface ...
8286  *      If the Virtual Interface enable/disable operation is successful,
8287  *      we notify the OS-specific code of a potential Link Status change
8288  *      via the OS Contract API t4_os_link_changed().
8289  */
8290 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8291                         struct port_info *pi,
8292                         bool rx_en, bool tx_en, bool dcb_en)
8293 {
8294         int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8295                                       rx_en, tx_en, dcb_en);
8296         if (ret)
8297                 return ret;
8298         t4_os_link_changed(adap, pi->port_id,
8299                            rx_en && tx_en && pi->link_cfg.link_ok);
8300         return 0;
8301 }
8302
8303 /**
8304  *      t4_identify_port - identify a VI's port by blinking its LED
8305  *      @adap: the adapter
8306  *      @mbox: mailbox to use for the FW command
8307  *      @viid: the VI id
8308  *      @nblinks: how many times to blink LED at 2.5 Hz
8309  *
8310  *      Identifies a VI's port by blinking its LED.
8311  */
8312 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8313                      unsigned int nblinks)
8314 {
8315         struct fw_vi_enable_cmd c;
8316
8317         memset(&c, 0, sizeof(c));
8318         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8319                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8320                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8321         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8322         c.blinkdur = cpu_to_be16(nblinks);
8323         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8324 }
8325
8326 /**
8327  *      t4_iq_stop - stop an ingress queue and its FLs
8328  *      @adap: the adapter
8329  *      @mbox: mailbox to use for the FW command
8330  *      @pf: the PF owning the queues
8331  *      @vf: the VF owning the queues
8332  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8333  *      @iqid: ingress queue id
8334  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
8335  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
8336  *
8337  *      Stops an ingress queue and its associated FLs, if any.  This causes
8338  *      any current or future data/messages destined for these queues to be
8339  *      tossed.
8340  */
8341 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8342                unsigned int vf, unsigned int iqtype, unsigned int iqid,
8343                unsigned int fl0id, unsigned int fl1id)
8344 {
8345         struct fw_iq_cmd c;
8346
8347         memset(&c, 0, sizeof(c));
8348         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8349                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8350                                   FW_IQ_CMD_VFN_V(vf));
8351         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8352         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8353         c.iqid = cpu_to_be16(iqid);
8354         c.fl0id = cpu_to_be16(fl0id);
8355         c.fl1id = cpu_to_be16(fl1id);
8356         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8357 }
8358
8359 /**
8360  *      t4_iq_free - free an ingress queue and its FLs
8361  *      @adap: the adapter
8362  *      @mbox: mailbox to use for the FW command
8363  *      @pf: the PF owning the queues
8364  *      @vf: the VF owning the queues
8365  *      @iqtype: the ingress queue type
8366  *      @iqid: ingress queue id
8367  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
8368  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
8369  *
8370  *      Frees an ingress queue and its associated FLs, if any.
8371  */
8372 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8373                unsigned int vf, unsigned int iqtype, unsigned int iqid,
8374                unsigned int fl0id, unsigned int fl1id)
8375 {
8376         struct fw_iq_cmd c;
8377
8378         memset(&c, 0, sizeof(c));
8379         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8380                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8381                                   FW_IQ_CMD_VFN_V(vf));
8382         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8383         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8384         c.iqid = cpu_to_be16(iqid);
8385         c.fl0id = cpu_to_be16(fl0id);
8386         c.fl1id = cpu_to_be16(fl1id);
8387         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8388 }
8389
8390 /**
8391  *      t4_eth_eq_free - free an Ethernet egress queue
8392  *      @adap: the adapter
8393  *      @mbox: mailbox to use for the FW command
8394  *      @pf: the PF owning the queue
8395  *      @vf: the VF owning the queue
8396  *      @eqid: egress queue id
8397  *
8398  *      Frees an Ethernet egress queue.
8399  */
8400 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8401                    unsigned int vf, unsigned int eqid)
8402 {
8403         struct fw_eq_eth_cmd c;
8404
8405         memset(&c, 0, sizeof(c));
8406         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8407                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8408                                   FW_EQ_ETH_CMD_PFN_V(pf) |
8409                                   FW_EQ_ETH_CMD_VFN_V(vf));
8410         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8411         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8412         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8413 }
8414
8415 /**
8416  *      t4_ctrl_eq_free - free a control egress queue
8417  *      @adap: the adapter
8418  *      @mbox: mailbox to use for the FW command
8419  *      @pf: the PF owning the queue
8420  *      @vf: the VF owning the queue
8421  *      @eqid: egress queue id
8422  *
8423  *      Frees a control egress queue.
8424  */
8425 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8426                     unsigned int vf, unsigned int eqid)
8427 {
8428         struct fw_eq_ctrl_cmd c;
8429
8430         memset(&c, 0, sizeof(c));
8431         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8432                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8433                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
8434                                   FW_EQ_CTRL_CMD_VFN_V(vf));
8435         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8436         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8437         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8438 }
8439
8440 /**
8441  *      t4_ofld_eq_free - free an offload egress queue
8442  *      @adap: the adapter
8443  *      @mbox: mailbox to use for the FW command
8444  *      @pf: the PF owning the queue
8445  *      @vf: the VF owning the queue
8446  *      @eqid: egress queue id
8447  *
8448  *      Frees a control egress queue.
8449  */
8450 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8451                     unsigned int vf, unsigned int eqid)
8452 {
8453         struct fw_eq_ofld_cmd c;
8454
8455         memset(&c, 0, sizeof(c));
8456         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8457                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8458                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
8459                                   FW_EQ_OFLD_CMD_VFN_V(vf));
8460         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8461         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8462         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8463 }
8464
8465 /**
8466  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
8467  *      @link_down_rc: Link Down Reason Code
8468  *
8469  *      Returns a string representation of the Link Down Reason Code.
8470  */
8471 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8472 {
8473         static const char * const reason[] = {
8474                 "Link Down",
8475                 "Remote Fault",
8476                 "Auto-negotiation Failure",
8477                 "Reserved",
8478                 "Insufficient Airflow",
8479                 "Unable To Determine Reason",
8480                 "No RX Signal Detected",
8481                 "Reserved",
8482         };
8483
8484         if (link_down_rc >= ARRAY_SIZE(reason))
8485                 return "Bad Reason Code";
8486
8487         return reason[link_down_rc];
8488 }
8489
8490 /* Return the highest speed set in the port capabilities, in Mb/s. */
8491 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8492 {
8493         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8494                 do { \
8495                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8496                                 return __speed; \
8497                 } while (0)
8498
8499         TEST_SPEED_RETURN(400G, 400000);
8500         TEST_SPEED_RETURN(200G, 200000);
8501         TEST_SPEED_RETURN(100G, 100000);
8502         TEST_SPEED_RETURN(50G,   50000);
8503         TEST_SPEED_RETURN(40G,   40000);
8504         TEST_SPEED_RETURN(25G,   25000);
8505         TEST_SPEED_RETURN(10G,   10000);
8506         TEST_SPEED_RETURN(1G,     1000);
8507         TEST_SPEED_RETURN(100M,    100);
8508
8509         #undef TEST_SPEED_RETURN
8510
8511         return 0;
8512 }
8513
8514 /**
8515  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
8516  *      @acaps: advertised Port Capabilities
8517  *
8518  *      Get the highest speed for the port from the advertised Port
8519  *      Capabilities.  It will be either the highest speed from the list of
8520  *      speeds or whatever user has set using ethtool.
8521  */
8522 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8523 {
8524         #define TEST_SPEED_RETURN(__caps_speed) \
8525                 do { \
8526                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8527                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8528                 } while (0)
8529
8530         TEST_SPEED_RETURN(400G);
8531         TEST_SPEED_RETURN(200G);
8532         TEST_SPEED_RETURN(100G);
8533         TEST_SPEED_RETURN(50G);
8534         TEST_SPEED_RETURN(40G);
8535         TEST_SPEED_RETURN(25G);
8536         TEST_SPEED_RETURN(10G);
8537         TEST_SPEED_RETURN(1G);
8538         TEST_SPEED_RETURN(100M);
8539
8540         #undef TEST_SPEED_RETURN
8541
8542         return 0;
8543 }
8544
8545 /**
8546  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8547  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8548  *
8549  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8550  *      32-bit Port Capabilities value.
8551  */
8552 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8553 {
8554         fw_port_cap32_t linkattr = 0;
8555
8556         /* Unfortunately the format of the Link Status in the old
8557          * 16-bit Port Information message isn't the same as the
8558          * 16-bit Port Capabilities bitfield used everywhere else ...
8559          */
8560         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8561                 linkattr |= FW_PORT_CAP32_FC_RX;
8562         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8563                 linkattr |= FW_PORT_CAP32_FC_TX;
8564         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8565                 linkattr |= FW_PORT_CAP32_SPEED_100M;
8566         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8567                 linkattr |= FW_PORT_CAP32_SPEED_1G;
8568         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8569                 linkattr |= FW_PORT_CAP32_SPEED_10G;
8570         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8571                 linkattr |= FW_PORT_CAP32_SPEED_25G;
8572         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8573                 linkattr |= FW_PORT_CAP32_SPEED_40G;
8574         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8575                 linkattr |= FW_PORT_CAP32_SPEED_100G;
8576
8577         return linkattr;
8578 }
8579
8580 /**
8581  *      t4_handle_get_port_info - process a FW reply message
8582  *      @pi: the port info
8583  *      @rpl: start of the FW message
8584  *
8585  *      Processes a GET_PORT_INFO FW reply message.
8586  */
8587 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8588 {
8589         const struct fw_port_cmd *cmd = (const void *)rpl;
8590         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8591         struct link_config *lc = &pi->link_cfg;
8592         struct adapter *adapter = pi->adapter;
8593         unsigned int speed, fc, fec, adv_fc;
8594         enum fw_port_module_type mod_type;
8595         int action, link_ok, linkdnrc;
8596         enum fw_port_type port_type;
8597
8598         /* Extract the various fields from the Port Information message.
8599          */
8600         action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8601         switch (action) {
8602         case FW_PORT_ACTION_GET_PORT_INFO: {
8603                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8604
8605                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8606                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8607                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8608                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8609                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8610                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8611                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8612                 linkattr = lstatus_to_fwcap(lstatus);
8613                 break;
8614         }
8615
8616         case FW_PORT_ACTION_GET_PORT_INFO32: {
8617                 u32 lstatus32;
8618
8619                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8620                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8621                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8622                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8623                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8624                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8625                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8626                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8627                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8628                 break;
8629         }
8630
8631         default:
8632                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8633                         be32_to_cpu(cmd->action_to_len16));
8634                 return;
8635         }
8636
8637         fec = fwcap_to_cc_fec(acaps);
8638         adv_fc = fwcap_to_cc_pause(acaps);
8639         fc = fwcap_to_cc_pause(linkattr);
8640         speed = fwcap_to_speed(linkattr);
8641
8642         /* Reset state for communicating new Transceiver Module status and
8643          * whether the OS-dependent layer wants us to redo the current
8644          * "sticky" L1 Configure Link Parameters.
8645          */
8646         lc->new_module = false;
8647         lc->redo_l1cfg = false;
8648
8649         if (mod_type != pi->mod_type) {
8650                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8651                  * various fundamental Port Capabilities which used to be
8652                  * immutable can now change radically.  We can now have
8653                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8654                  * all change based on what Transceiver Module is inserted.
8655                  * So we need to record the Physical "Port" Capabilities on
8656                  * every Transceiver Module change.
8657                  */
8658                 lc->pcaps = pcaps;
8659
8660                 /* When a new Transceiver Module is inserted, the Firmware
8661                  * will examine its i2c EPROM to determine its type and
8662                  * general operating parameters including things like Forward
8663                  * Error Control, etc.  Various IEEE 802.3 standards dictate
8664                  * how to interpret these i2c values to determine default
8665                  * "sutomatic" settings.  We record these for future use when
8666                  * the user explicitly requests these standards-based values.
8667                  */
8668                 lc->def_acaps = acaps;
8669
8670                 /* Some versions of the early T6 Firmware "cheated" when
8671                  * handling different Transceiver Modules by changing the
8672                  * underlaying Port Type reported to the Host Drivers.  As
8673                  * such we need to capture whatever Port Type the Firmware
8674                  * sends us and record it in case it's different from what we
8675                  * were told earlier.  Unfortunately, since Firmware is
8676                  * forever, we'll need to keep this code here forever, but in
8677                  * later T6 Firmware it should just be an assignment of the
8678                  * same value already recorded.
8679                  */
8680                 pi->port_type = port_type;
8681
8682                 /* Record new Module Type information.
8683                  */
8684                 pi->mod_type = mod_type;
8685
8686                 /* Let the OS-dependent layer know if we have a new
8687                  * Transceiver Module inserted.
8688                  */
8689                 lc->new_module = t4_is_inserted_mod_type(mod_type);
8690
8691                 t4_os_portmod_changed(adapter, pi->port_id);
8692         }
8693
8694         if (link_ok != lc->link_ok || speed != lc->speed ||
8695             fc != lc->fc || adv_fc != lc->advertised_fc ||
8696             fec != lc->fec) {
8697                 /* something changed */
8698                 if (!link_ok && lc->link_ok) {
8699                         lc->link_down_rc = linkdnrc;
8700                         dev_warn_ratelimited(adapter->pdev_dev,
8701                                              "Port %d link down, reason: %s\n",
8702                                              pi->tx_chan,
8703                                              t4_link_down_rc_str(linkdnrc));
8704                 }
8705                 lc->link_ok = link_ok;
8706                 lc->speed = speed;
8707                 lc->advertised_fc = adv_fc;
8708                 lc->fc = fc;
8709                 lc->fec = fec;
8710
8711                 lc->lpacaps = lpacaps;
8712                 lc->acaps = acaps & ADVERT_MASK;
8713
8714                 /* If we're not physically capable of Auto-Negotiation, note
8715                  * this as Auto-Negotiation disabled.  Otherwise, we track
8716                  * what Auto-Negotiation settings we have.  Note parallel
8717                  * structure in t4_link_l1cfg_core() and init_link_config().
8718                  */
8719                 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8720                         lc->autoneg = AUTONEG_DISABLE;
8721                 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8722                         lc->autoneg = AUTONEG_ENABLE;
8723                 } else {
8724                         /* When Autoneg is disabled, user needs to set
8725                          * single speed.
8726                          * Similar to cxgb4_ethtool.c: set_link_ksettings
8727                          */
8728                         lc->acaps = 0;
8729                         lc->speed_caps = fwcap_to_fwspeed(acaps);
8730                         lc->autoneg = AUTONEG_DISABLE;
8731                 }
8732
8733                 t4_os_link_changed(adapter, pi->port_id, link_ok);
8734         }
8735
8736         /* If we have a new Transceiver Module and the OS-dependent code has
8737          * told us that it wants us to redo whatever "sticky" L1 Configuration
8738          * Link Parameters are set, do that now.
8739          */
8740         if (lc->new_module && lc->redo_l1cfg) {
8741                 struct link_config old_lc;
8742                 int ret;
8743
8744                 /* Save the current L1 Configuration and restore it if an
8745                  * error occurs.  We probably should fix the l1_cfg*()
8746                  * routines not to change the link_config when an error
8747                  * occurs ...
8748                  */
8749                 old_lc = *lc;
8750                 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8751                 if (ret) {
8752                         *lc = old_lc;
8753                         dev_warn(adapter->pdev_dev,
8754                                  "Attempt to update new Transceiver Module settings failed\n");
8755                 }
8756         }
8757         lc->new_module = false;
8758         lc->redo_l1cfg = false;
8759 }
8760
8761 /**
8762  *      t4_update_port_info - retrieve and update port information if changed
8763  *      @pi: the port_info
8764  *
8765  *      We issue a Get Port Information Command to the Firmware and, if
8766  *      successful, we check to see if anything is different from what we
8767  *      last recorded and update things accordingly.
8768  */
8769 int t4_update_port_info(struct port_info *pi)
8770 {
8771         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8772         struct fw_port_cmd port_cmd;
8773         int ret;
8774
8775         memset(&port_cmd, 0, sizeof(port_cmd));
8776         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8777                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8778                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8779         port_cmd.action_to_len16 = cpu_to_be32(
8780                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8781                                      ? FW_PORT_ACTION_GET_PORT_INFO
8782                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8783                 FW_LEN16(port_cmd));
8784         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8785                          &port_cmd, sizeof(port_cmd), &port_cmd);
8786         if (ret)
8787                 return ret;
8788
8789         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8790         return 0;
8791 }
8792
8793 /**
8794  *      t4_get_link_params - retrieve basic link parameters for given port
8795  *      @pi: the port
8796  *      @link_okp: value return pointer for link up/down
8797  *      @speedp: value return pointer for speed (Mb/s)
8798  *      @mtup: value return pointer for mtu
8799  *
8800  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8801  *      and MTU for a specified port.  A negative error is returned on
8802  *      failure; 0 on success.
8803  */
8804 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8805                        unsigned int *speedp, unsigned int *mtup)
8806 {
8807         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8808         unsigned int action, link_ok, mtu;
8809         struct fw_port_cmd port_cmd;
8810         fw_port_cap32_t linkattr;
8811         int ret;
8812
8813         memset(&port_cmd, 0, sizeof(port_cmd));
8814         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8815                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8816                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8817         action = (fw_caps == FW_CAPS16
8818                   ? FW_PORT_ACTION_GET_PORT_INFO
8819                   : FW_PORT_ACTION_GET_PORT_INFO32);
8820         port_cmd.action_to_len16 = cpu_to_be32(
8821                 FW_PORT_CMD_ACTION_V(action) |
8822                 FW_LEN16(port_cmd));
8823         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8824                          &port_cmd, sizeof(port_cmd), &port_cmd);
8825         if (ret)
8826                 return ret;
8827
8828         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8829                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8830
8831                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8832                 linkattr = lstatus_to_fwcap(lstatus);
8833                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8834         } else {
8835                 u32 lstatus32 =
8836                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8837
8838                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8839                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8840                 mtu = FW_PORT_CMD_MTU32_G(
8841                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8842         }
8843
8844         if (link_okp)
8845                 *link_okp = link_ok;
8846         if (speedp)
8847                 *speedp = fwcap_to_speed(linkattr);
8848         if (mtup)
8849                 *mtup = mtu;
8850
8851         return 0;
8852 }
8853
8854 /**
8855  *      t4_handle_fw_rpl - process a FW reply message
8856  *      @adap: the adapter
8857  *      @rpl: start of the FW message
8858  *
8859  *      Processes a FW message, such as link state change messages.
8860  */
8861 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8862 {
8863         u8 opcode = *(const u8 *)rpl;
8864
8865         /* This might be a port command ... this simplifies the following
8866          * conditionals ...  We can get away with pre-dereferencing
8867          * action_to_len16 because it's in the first 16 bytes and all messages
8868          * will be at least that long.
8869          */
8870         const struct fw_port_cmd *p = (const void *)rpl;
8871         unsigned int action =
8872                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8873
8874         if (opcode == FW_PORT_CMD &&
8875             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8876              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8877                 int i;
8878                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8879                 struct port_info *pi = NULL;
8880
8881                 for_each_port(adap, i) {
8882                         pi = adap2pinfo(adap, i);
8883                         if (pi->tx_chan == chan)
8884                                 break;
8885                 }
8886
8887                 t4_handle_get_port_info(pi, rpl);
8888         } else {
8889                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8890                          opcode);
8891                 return -EINVAL;
8892         }
8893         return 0;
8894 }
8895
8896 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8897 {
8898         u16 val;
8899
8900         if (pci_is_pcie(adapter->pdev)) {
8901                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8902                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8903                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8904         }
8905 }
8906
8907 /**
8908  *      init_link_config - initialize a link's SW state
8909  *      @lc: pointer to structure holding the link state
8910  *      @pcaps: link Port Capabilities
8911  *      @acaps: link current Advertised Port Capabilities
8912  *
8913  *      Initializes the SW state maintained for each link, including the link's
8914  *      capabilities and default speed/flow-control/autonegotiation settings.
8915  */
8916 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8917                              fw_port_cap32_t acaps)
8918 {
8919         lc->pcaps = pcaps;
8920         lc->def_acaps = acaps;
8921         lc->lpacaps = 0;
8922         lc->speed_caps = 0;
8923         lc->speed = 0;
8924         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8925
8926         /* For Forward Error Control, we default to whatever the Firmware
8927          * tells us the Link is currently advertising.
8928          */
8929         lc->requested_fec = FEC_AUTO;
8930         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8931
8932         /* If the Port is capable of Auto-Negtotiation, initialize it as
8933          * "enabled" and copy over all of the Physical Port Capabilities
8934          * to the Advertised Port Capabilities.  Otherwise mark it as
8935          * Auto-Negotiate disabled and select the highest supported speed
8936          * for the link.  Note parallel structure in t4_link_l1cfg_core()
8937          * and t4_handle_get_port_info().
8938          */
8939         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8940                 lc->acaps = lc->pcaps & ADVERT_MASK;
8941                 lc->autoneg = AUTONEG_ENABLE;
8942                 lc->requested_fc |= PAUSE_AUTONEG;
8943         } else {
8944                 lc->acaps = 0;
8945                 lc->autoneg = AUTONEG_DISABLE;
8946                 lc->speed_caps = fwcap_to_fwspeed(acaps);
8947         }
8948 }
8949
8950 #define CIM_PF_NOACCESS 0xeeeeeeee
8951
8952 int t4_wait_dev_ready(void __iomem *regs)
8953 {
8954         u32 whoami;
8955
8956         whoami = readl(regs + PL_WHOAMI_A);
8957         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8958                 return 0;
8959
8960         msleep(500);
8961         whoami = readl(regs + PL_WHOAMI_A);
8962         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8963 }
8964
8965 struct flash_desc {
8966         u32 vendor_and_model_id;
8967         u32 size_mb;
8968 };
8969
8970 static int t4_get_flash_params(struct adapter *adap)
8971 {
8972         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8973          * to the preexisting code.  All flash parts have 64KB sectors.
8974          */
8975         static struct flash_desc supported_flash[] = {
8976                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8977         };
8978
8979         unsigned int part, manufacturer;
8980         unsigned int density, size = 0;
8981         u32 flashid = 0;
8982         int ret;
8983
8984         /* Issue a Read ID Command to the Flash part.  We decode supported
8985          * Flash parts and their sizes from this.  There's a newer Query
8986          * Command which can retrieve detailed geometry information but many
8987          * Flash parts don't support it.
8988          */
8989
8990         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8991         if (!ret)
8992                 ret = sf1_read(adap, 3, 0, 1, &flashid);
8993         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8994         if (ret)
8995                 return ret;
8996
8997         /* Check to see if it's one of our non-standard supported Flash parts.
8998          */
8999         for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
9000                 if (supported_flash[part].vendor_and_model_id == flashid) {
9001                         adap->params.sf_size = supported_flash[part].size_mb;
9002                         adap->params.sf_nsec =
9003                                 adap->params.sf_size / SF_SEC_SIZE;
9004                         goto found;
9005                 }
9006
9007         /* Decode Flash part size.  The code below looks repetitive with
9008          * common encodings, but that's not guaranteed in the JEDEC
9009          * specification for the Read JEDEC ID command.  The only thing that
9010          * we're guaranteed by the JEDEC specification is where the
9011          * Manufacturer ID is in the returned result.  After that each
9012          * Manufacturer ~could~ encode things completely differently.
9013          * Note, all Flash parts must have 64KB sectors.
9014          */
9015         manufacturer = flashid & 0xff;
9016         switch (manufacturer) {
9017         case 0x20: { /* Micron/Numonix */
9018                 /* This Density -> Size decoding table is taken from Micron
9019                  * Data Sheets.
9020                  */
9021                 density = (flashid >> 16) & 0xff;
9022                 switch (density) {
9023                 case 0x14: /* 1MB */
9024                         size = 1 << 20;
9025                         break;
9026                 case 0x15: /* 2MB */
9027                         size = 1 << 21;
9028                         break;
9029                 case 0x16: /* 4MB */
9030                         size = 1 << 22;
9031                         break;
9032                 case 0x17: /* 8MB */
9033                         size = 1 << 23;
9034                         break;
9035                 case 0x18: /* 16MB */
9036                         size = 1 << 24;
9037                         break;
9038                 case 0x19: /* 32MB */
9039                         size = 1 << 25;
9040                         break;
9041                 case 0x20: /* 64MB */
9042                         size = 1 << 26;
9043                         break;
9044                 case 0x21: /* 128MB */
9045                         size = 1 << 27;
9046                         break;
9047                 case 0x22: /* 256MB */
9048                         size = 1 << 28;
9049                         break;
9050                 }
9051                 break;
9052         }
9053         case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9054                 /* This Density -> Size decoding table is taken from ISSI
9055                  * Data Sheets.
9056                  */
9057                 density = (flashid >> 16) & 0xff;
9058                 switch (density) {
9059                 case 0x16: /* 32 MB */
9060                         size = 1 << 25;
9061                         break;
9062                 case 0x17: /* 64MB */
9063                         size = 1 << 26;
9064                         break;
9065                 }
9066                 break;
9067         }
9068         case 0xc2: { /* Macronix */
9069                 /* This Density -> Size decoding table is taken from Macronix
9070                  * Data Sheets.
9071                  */
9072                 density = (flashid >> 16) & 0xff;
9073                 switch (density) {
9074                 case 0x17: /* 8MB */
9075                         size = 1 << 23;
9076                         break;
9077                 case 0x18: /* 16MB */
9078                         size = 1 << 24;
9079                         break;
9080                 }
9081                 break;
9082         }
9083         case 0xef: { /* Winbond */
9084                 /* This Density -> Size decoding table is taken from Winbond
9085                  * Data Sheets.
9086                  */
9087                 density = (flashid >> 16) & 0xff;
9088                 switch (density) {
9089                 case 0x17: /* 8MB */
9090                         size = 1 << 23;
9091                         break;
9092                 case 0x18: /* 16MB */
9093                         size = 1 << 24;
9094                         break;
9095                 }
9096                 break;
9097         }
9098         }
9099
9100         /* If we didn't recognize the FLASH part, that's no real issue: the
9101          * Hardware/Software contract says that Hardware will _*ALWAYS*_
9102          * use a FLASH part which is at least 4MB in size and has 64KB
9103          * sectors.  The unrecognized FLASH part is likely to be much larger
9104          * than 4MB, but that's all we really need.
9105          */
9106         if (size == 0) {
9107                 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9108                          flashid);
9109                 size = 1 << 22;
9110         }
9111
9112         /* Store decoded Flash size and fall through into vetting code. */
9113         adap->params.sf_size = size;
9114         adap->params.sf_nsec = size / SF_SEC_SIZE;
9115
9116 found:
9117         if (adap->params.sf_size < FLASH_MIN_SIZE)
9118                 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9119                          flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9120         return 0;
9121 }
9122
9123 /**
9124  *      t4_prep_adapter - prepare SW and HW for operation
9125  *      @adapter: the adapter
9126  *
9127  *      Initialize adapter SW state for the various HW modules, set initial
9128  *      values for some adapter tunables, take PHYs out of reset, and
9129  *      initialize the MDIO interface.
9130  */
9131 int t4_prep_adapter(struct adapter *adapter)
9132 {
9133         int ret, ver;
9134         uint16_t device_id;
9135         u32 pl_rev;
9136
9137         get_pci_mode(adapter, &adapter->params.pci);
9138         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9139
9140         ret = t4_get_flash_params(adapter);
9141         if (ret < 0) {
9142                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
9143                 return ret;
9144         }
9145
9146         /* Retrieve adapter's device ID
9147          */
9148         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
9149         ver = device_id >> 12;
9150         adapter->params.chip = 0;
9151         switch (ver) {
9152         case CHELSIO_T4:
9153                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
9154                 adapter->params.arch.sge_fl_db = DBPRIO_F;
9155                 adapter->params.arch.mps_tcam_size =
9156                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
9157                 adapter->params.arch.mps_rplc_size = 128;
9158                 adapter->params.arch.nchan = NCHAN;
9159                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9160                 adapter->params.arch.vfcount = 128;
9161                 /* Congestion map is for 4 channels so that
9162                  * MPS can have 4 priority per port.
9163                  */
9164                 adapter->params.arch.cng_ch_bits_log = 2;
9165                 break;
9166         case CHELSIO_T5:
9167                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
9168                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
9169                 adapter->params.arch.mps_tcam_size =
9170                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9171                 adapter->params.arch.mps_rplc_size = 128;
9172                 adapter->params.arch.nchan = NCHAN;
9173                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9174                 adapter->params.arch.vfcount = 128;
9175                 adapter->params.arch.cng_ch_bits_log = 2;
9176                 break;
9177         case CHELSIO_T6:
9178                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
9179                 adapter->params.arch.sge_fl_db = 0;
9180                 adapter->params.arch.mps_tcam_size =
9181                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9182                 adapter->params.arch.mps_rplc_size = 256;
9183                 adapter->params.arch.nchan = 2;
9184                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
9185                 adapter->params.arch.vfcount = 256;
9186                 /* Congestion map will be for 2 channels so that
9187                  * MPS can have 8 priority per port.
9188                  */
9189                 adapter->params.arch.cng_ch_bits_log = 3;
9190                 break;
9191         default:
9192                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
9193                         device_id);
9194                 return -EINVAL;
9195         }
9196
9197         adapter->params.cim_la_size = CIMLA_SIZE;
9198         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9199
9200         /*
9201          * Default port for debugging in case we can't reach FW.
9202          */
9203         adapter->params.nports = 1;
9204         adapter->params.portvec = 1;
9205         adapter->params.vpd.cclk = 50000;
9206
9207         /* Set PCIe completion timeout to 4 seconds. */
9208         pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
9209                                            PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
9210         return 0;
9211 }
9212
9213 /**
9214  *      t4_shutdown_adapter - shut down adapter, host & wire
9215  *      @adapter: the adapter
9216  *
9217  *      Perform an emergency shutdown of the adapter and stop it from
9218  *      continuing any further communication on the ports or DMA to the
9219  *      host.  This is typically used when the adapter and/or firmware
9220  *      have crashed and we want to prevent any further accidental
9221  *      communication with the rest of the world.  This will also force
9222  *      the port Link Status to go down -- if register writes work --
9223  *      which should help our peers figure out that we're down.
9224  */
9225 int t4_shutdown_adapter(struct adapter *adapter)
9226 {
9227         int port;
9228
9229         t4_intr_disable(adapter);
9230         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9231         for_each_port(adapter, port) {
9232                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
9233                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
9234                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
9235
9236                 t4_write_reg(adapter, a_port_cfg,
9237                              t4_read_reg(adapter, a_port_cfg)
9238                              & ~SIGNAL_DET_V(1));
9239         }
9240         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9241
9242         return 0;
9243 }
9244
9245 /**
9246  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9247  *      @adapter: the adapter
9248  *      @qid: the Queue ID
9249  *      @qtype: the Ingress or Egress type for @qid
9250  *      @user: true if this request is for a user mode queue
9251  *      @pbar2_qoffset: BAR2 Queue Offset
9252  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9253  *
9254  *      Returns the BAR2 SGE Queue Registers information associated with the
9255  *      indicated Absolute Queue ID.  These are passed back in return value
9256  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9257  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9258  *
9259  *      This may return an error which indicates that BAR2 SGE Queue
9260  *      registers aren't available.  If an error is not returned, then the
9261  *      following values are returned:
9262  *
9263  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9264  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9265  *
9266  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9267  *      require the "Inferred Queue ID" ability may be used.  E.g. the
9268  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9269  *      then these "Inferred Queue ID" register may not be used.
9270  */
9271 int t4_bar2_sge_qregs(struct adapter *adapter,
9272                       unsigned int qid,
9273                       enum t4_bar2_qtype qtype,
9274                       int user,
9275                       u64 *pbar2_qoffset,
9276                       unsigned int *pbar2_qid)
9277 {
9278         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9279         u64 bar2_page_offset, bar2_qoffset;
9280         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9281
9282         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9283         if (!user && is_t4(adapter->params.chip))
9284                 return -EINVAL;
9285
9286         /* Get our SGE Page Size parameters.
9287          */
9288         page_shift = adapter->params.sge.hps + 10;
9289         page_size = 1 << page_shift;
9290
9291         /* Get the right Queues per Page parameters for our Queue.
9292          */
9293         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9294                      ? adapter->params.sge.eq_qpp
9295                      : adapter->params.sge.iq_qpp);
9296         qpp_mask = (1 << qpp_shift) - 1;
9297
9298         /*  Calculate the basics of the BAR2 SGE Queue register area:
9299          *  o The BAR2 page the Queue registers will be in.
9300          *  o The BAR2 Queue ID.
9301          *  o The BAR2 Queue ID Offset into the BAR2 page.
9302          */
9303         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9304         bar2_qid = qid & qpp_mask;
9305         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9306
9307         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9308          * hardware will infer the Absolute Queue ID simply from the writes to
9309          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9310          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
9311          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9312          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9313          * from the BAR2 Page and BAR2 Queue ID.
9314          *
9315          * One important censequence of this is that some BAR2 SGE registers
9316          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9317          * there.  But other registers synthesize the SGE Queue ID purely
9318          * from the writes to the registers -- the Write Combined Doorbell
9319          * Buffer is a good example.  These BAR2 SGE Registers are only
9320          * available for those BAR2 SGE Register areas where the SGE Absolute
9321          * Queue ID can be inferred from simple writes.
9322          */
9323         bar2_qoffset = bar2_page_offset;
9324         bar2_qinferred = (bar2_qid_offset < page_size);
9325         if (bar2_qinferred) {
9326                 bar2_qoffset += bar2_qid_offset;
9327                 bar2_qid = 0;
9328         }
9329
9330         *pbar2_qoffset = bar2_qoffset;
9331         *pbar2_qid = bar2_qid;
9332         return 0;
9333 }
9334
9335 /**
9336  *      t4_init_devlog_params - initialize adapter->params.devlog
9337  *      @adap: the adapter
9338  *
9339  *      Initialize various fields of the adapter's Firmware Device Log
9340  *      Parameters structure.
9341  */
9342 int t4_init_devlog_params(struct adapter *adap)
9343 {
9344         struct devlog_params *dparams = &adap->params.devlog;
9345         u32 pf_dparams;
9346         unsigned int devlog_meminfo;
9347         struct fw_devlog_cmd devlog_cmd;
9348         int ret;
9349
9350         /* If we're dealing with newer firmware, the Device Log Parameters
9351          * are stored in a designated register which allows us to access the
9352          * Device Log even if we can't talk to the firmware.
9353          */
9354         pf_dparams =
9355                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9356         if (pf_dparams) {
9357                 unsigned int nentries, nentries128;
9358
9359                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9360                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9361
9362                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9363                 nentries = (nentries128 + 1) * 128;
9364                 dparams->size = nentries * sizeof(struct fw_devlog_e);
9365
9366                 return 0;
9367         }
9368
9369         /* Otherwise, ask the firmware for it's Device Log Parameters.
9370          */
9371         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9372         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9373                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
9374         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9375         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9376                          &devlog_cmd);
9377         if (ret)
9378                 return ret;
9379
9380         devlog_meminfo =
9381                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9382         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9383         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9384         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9385
9386         return 0;
9387 }
9388
9389 /**
9390  *      t4_init_sge_params - initialize adap->params.sge
9391  *      @adapter: the adapter
9392  *
9393  *      Initialize various fields of the adapter's SGE Parameters structure.
9394  */
9395 int t4_init_sge_params(struct adapter *adapter)
9396 {
9397         struct sge_params *sge_params = &adapter->params.sge;
9398         u32 hps, qpp;
9399         unsigned int s_hps, s_qpp;
9400
9401         /* Extract the SGE Page Size for our PF.
9402          */
9403         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9404         s_hps = (HOSTPAGESIZEPF0_S +
9405                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9406         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9407
9408         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9409          */
9410         s_qpp = (QUEUESPERPAGEPF0_S +
9411                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9412         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9413         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9414         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9415         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9416
9417         return 0;
9418 }
9419
9420 /**
9421  *      t4_init_tp_params - initialize adap->params.tp
9422  *      @adap: the adapter
9423  *      @sleep_ok: if true we may sleep while awaiting command completion
9424  *
9425  *      Initialize various fields of the adapter's TP Parameters structure.
9426  */
9427 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9428 {
9429         u32 param, val, v;
9430         int chan, ret;
9431
9432
9433         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9434         adap->params.tp.tre = TIMERRESOLUTION_G(v);
9435         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9436
9437         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9438         for (chan = 0; chan < NCHAN; chan++)
9439                 adap->params.tp.tx_modq[chan] = chan;
9440
9441         /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9442          * Configuration.
9443          */
9444         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
9445                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER) |
9446                  FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK));
9447
9448         /* Read current value */
9449         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9450                               &param, &val);
9451         if (ret == 0) {
9452                 dev_info(adap->pdev_dev,
9453                          "Current filter mode/mask 0x%x:0x%x\n",
9454                          FW_PARAMS_PARAM_FILTER_MODE_G(val),
9455                          FW_PARAMS_PARAM_FILTER_MASK_G(val));
9456                 adap->params.tp.vlan_pri_map =
9457                         FW_PARAMS_PARAM_FILTER_MODE_G(val);
9458                 adap->params.tp.filter_mask =
9459                         FW_PARAMS_PARAM_FILTER_MASK_G(val);
9460         } else {
9461                 dev_info(adap->pdev_dev,
9462                          "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9463
9464                 /* Incase of older-fw (which doesn't expose the api
9465                  * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9466                  * the fw api) combination, fall-back to older method of reading
9467                  * the filter mode from indirect-register
9468                  */
9469                 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9470                                TP_VLAN_PRI_MAP_A, sleep_ok);
9471
9472                 /* With the older-fw and newer-driver combination we might run
9473                  * into an issue when user wants to use hash filter region but
9474                  * the filter_mask is zero, in this case filter_mask validation
9475                  * is tough. To avoid that we set the filter_mask same as filter
9476                  * mode, which will behave exactly as the older way of ignoring
9477                  * the filter mask validation.
9478                  */
9479                 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9480         }
9481
9482         t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9483                        TP_INGRESS_CONFIG_A, sleep_ok);
9484
9485         /* For T6, cache the adapter's compressed error vector
9486          * and passing outer header info for encapsulated packets.
9487          */
9488         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9489                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9490                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9491         }
9492
9493         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9494          * shift positions of several elements of the Compressed Filter Tuple
9495          * for this adapter which we need frequently ...
9496          */
9497         adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9498         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9499         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9500         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9501         adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9502         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9503                                                                PROTOCOL_F);
9504         adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9505                                                                 ETHERTYPE_F);
9506         adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9507                                                                MACMATCH_F);
9508         adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9509                                                                 MPSHITTYPE_F);
9510         adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9511                                                            FRAGMENTATION_F);
9512
9513         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9514          * represents the presence of an Outer VLAN instead of a VNIC ID.
9515          */
9516         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9517                 adap->params.tp.vnic_shift = -1;
9518
9519         v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9520         adap->params.tp.hash_filter_mask = v;
9521         v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9522         adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9523         return 0;
9524 }
9525
9526 /**
9527  *      t4_filter_field_shift - calculate filter field shift
9528  *      @adap: the adapter
9529  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9530  *
9531  *      Return the shift position of a filter field within the Compressed
9532  *      Filter Tuple.  The filter field is specified via its selection bit
9533  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
9534  */
9535 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9536 {
9537         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9538         unsigned int sel;
9539         int field_shift;
9540
9541         if ((filter_mode & filter_sel) == 0)
9542                 return -1;
9543
9544         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9545                 switch (filter_mode & sel) {
9546                 case FCOE_F:
9547                         field_shift += FT_FCOE_W;
9548                         break;
9549                 case PORT_F:
9550                         field_shift += FT_PORT_W;
9551                         break;
9552                 case VNIC_ID_F:
9553                         field_shift += FT_VNIC_ID_W;
9554                         break;
9555                 case VLAN_F:
9556                         field_shift += FT_VLAN_W;
9557                         break;
9558                 case TOS_F:
9559                         field_shift += FT_TOS_W;
9560                         break;
9561                 case PROTOCOL_F:
9562                         field_shift += FT_PROTOCOL_W;
9563                         break;
9564                 case ETHERTYPE_F:
9565                         field_shift += FT_ETHERTYPE_W;
9566                         break;
9567                 case MACMATCH_F:
9568                         field_shift += FT_MACMATCH_W;
9569                         break;
9570                 case MPSHITTYPE_F:
9571                         field_shift += FT_MPSHITTYPE_W;
9572                         break;
9573                 case FRAGMENTATION_F:
9574                         field_shift += FT_FRAGMENTATION_W;
9575                         break;
9576                 }
9577         }
9578         return field_shift;
9579 }
9580
9581 int t4_init_rss_mode(struct adapter *adap, int mbox)
9582 {
9583         int i, ret;
9584         struct fw_rss_vi_config_cmd rvc;
9585
9586         memset(&rvc, 0, sizeof(rvc));
9587
9588         for_each_port(adap, i) {
9589                 struct port_info *p = adap2pinfo(adap, i);
9590
9591                 rvc.op_to_viid =
9592                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9593                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
9594                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9595                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9596                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9597                 if (ret)
9598                         return ret;
9599                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9600         }
9601         return 0;
9602 }
9603
9604 /**
9605  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
9606  *      @pi: the port_info
9607  *      @mbox: mailbox to use for the FW command
9608  *      @port: physical port associated with the VI
9609  *      @pf: the PF owning the VI
9610  *      @vf: the VF owning the VI
9611  *      @mac: the MAC address of the VI
9612  *
9613  *      Allocates a virtual interface for the given physical port.  If @mac is
9614  *      not %NULL it contains the MAC address of the VI as assigned by FW.
9615  *      @mac should be large enough to hold an Ethernet address.
9616  *      Returns < 0 on error.
9617  */
9618 int t4_init_portinfo(struct port_info *pi, int mbox,
9619                      int port, int pf, int vf, u8 mac[])
9620 {
9621         struct adapter *adapter = pi->adapter;
9622         unsigned int fw_caps = adapter->params.fw_caps_support;
9623         struct fw_port_cmd cmd;
9624         unsigned int rss_size;
9625         enum fw_port_type port_type;
9626         int mdio_addr;
9627         fw_port_cap32_t pcaps, acaps;
9628         u8 vivld = 0, vin = 0;
9629         int ret;
9630
9631         /* If we haven't yet determined whether we're talking to Firmware
9632          * which knows the new 32-bit Port Capabilities, it's time to find
9633          * out now.  This will also tell new Firmware to send us Port Status
9634          * Updates using the new 32-bit Port Capabilities version of the
9635          * Port Information message.
9636          */
9637         if (fw_caps == FW_CAPS_UNKNOWN) {
9638                 u32 param, val;
9639
9640                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9641                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9642                 val = 1;
9643                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
9644                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9645                 adapter->params.fw_caps_support = fw_caps;
9646         }
9647
9648         memset(&cmd, 0, sizeof(cmd));
9649         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9650                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
9651                                        FW_PORT_CMD_PORTID_V(port));
9652         cmd.action_to_len16 = cpu_to_be32(
9653                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9654                                      ? FW_PORT_ACTION_GET_PORT_INFO
9655                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
9656                 FW_LEN16(cmd));
9657         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9658         if (ret)
9659                 return ret;
9660
9661         /* Extract the various fields from the Port Information message.
9662          */
9663         if (fw_caps == FW_CAPS16) {
9664                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9665
9666                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9667                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9668                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9669                              : -1);
9670                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9671                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9672         } else {
9673                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9674
9675                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9676                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9677                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9678                              : -1);
9679                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9680                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9681         }
9682
9683         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size,
9684                           &vivld, &vin);
9685         if (ret < 0)
9686                 return ret;
9687
9688         pi->viid = ret;
9689         pi->tx_chan = port;
9690         pi->lport = port;
9691         pi->rss_size = rss_size;
9692         pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
9693
9694         /* If fw supports returning the VIN as part of FW_VI_CMD,
9695          * save the returned values.
9696          */
9697         if (adapter->params.viid_smt_extn_support) {
9698                 pi->vivld = vivld;
9699                 pi->vin = vin;
9700         } else {
9701                 /* Retrieve the values from VIID */
9702                 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
9703                 pi->vin =  FW_VIID_VIN_G(pi->viid);
9704         }
9705
9706         pi->port_type = port_type;
9707         pi->mdio_addr = mdio_addr;
9708         pi->mod_type = FW_PORT_MOD_TYPE_NA;
9709
9710         init_link_config(&pi->link_cfg, pcaps, acaps);
9711         return 0;
9712 }
9713
9714 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9715 {
9716         u8 addr[6];
9717         int ret, i, j = 0;
9718
9719         for_each_port(adap, i) {
9720                 struct port_info *pi = adap2pinfo(adap, i);
9721
9722                 while ((adap->params.portvec & (1 << j)) == 0)
9723                         j++;
9724
9725                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9726                 if (ret)
9727                         return ret;
9728
9729                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9730                 j++;
9731         }
9732         return 0;
9733 }
9734
9735 int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
9736                         u16 *mirror_viid)
9737 {
9738         int ret;
9739
9740         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL,
9741                           NULL, NULL);
9742         if (ret < 0)
9743                 return ret;
9744
9745         if (mirror_viid)
9746                 *mirror_viid = ret;
9747
9748         return 0;
9749 }
9750
9751 /**
9752  *      t4_read_cimq_cfg - read CIM queue configuration
9753  *      @adap: the adapter
9754  *      @base: holds the queue base addresses in bytes
9755  *      @size: holds the queue sizes in bytes
9756  *      @thres: holds the queue full thresholds in bytes
9757  *
9758  *      Returns the current configuration of the CIM queues, starting with
9759  *      the IBQs, then the OBQs.
9760  */
9761 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9762 {
9763         unsigned int i, v;
9764         int cim_num_obq = is_t4(adap->params.chip) ?
9765                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9766
9767         for (i = 0; i < CIM_NUM_IBQ; i++) {
9768                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9769                              QUENUMSELECT_V(i));
9770                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9771                 /* value is in 256-byte units */
9772                 *base++ = CIMQBASE_G(v) * 256;
9773                 *size++ = CIMQSIZE_G(v) * 256;
9774                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9775         }
9776         for (i = 0; i < cim_num_obq; i++) {
9777                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9778                              QUENUMSELECT_V(i));
9779                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9780                 /* value is in 256-byte units */
9781                 *base++ = CIMQBASE_G(v) * 256;
9782                 *size++ = CIMQSIZE_G(v) * 256;
9783         }
9784 }
9785
9786 /**
9787  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
9788  *      @adap: the adapter
9789  *      @qid: the queue index
9790  *      @data: where to store the queue contents
9791  *      @n: capacity of @data in 32-bit words
9792  *
9793  *      Reads the contents of the selected CIM queue starting at address 0 up
9794  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9795  *      error and the number of 32-bit words actually read on success.
9796  */
9797 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9798 {
9799         int i, err, attempts;
9800         unsigned int addr;
9801         const unsigned int nwords = CIM_IBQ_SIZE * 4;
9802
9803         if (qid > 5 || (n & 3))
9804                 return -EINVAL;
9805
9806         addr = qid * nwords;
9807         if (n > nwords)
9808                 n = nwords;
9809
9810         /* It might take 3-10ms before the IBQ debug read access is allowed.
9811          * Wait for 1 Sec with a delay of 1 usec.
9812          */
9813         attempts = 1000000;
9814
9815         for (i = 0; i < n; i++, addr++) {
9816                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9817                              IBQDBGEN_F);
9818                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9819                                       attempts, 1);
9820                 if (err)
9821                         return err;
9822                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9823         }
9824         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9825         return i;
9826 }
9827
9828 /**
9829  *      t4_read_cim_obq - read the contents of a CIM outbound queue
9830  *      @adap: the adapter
9831  *      @qid: the queue index
9832  *      @data: where to store the queue contents
9833  *      @n: capacity of @data in 32-bit words
9834  *
9835  *      Reads the contents of the selected CIM queue starting at address 0 up
9836  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9837  *      error and the number of 32-bit words actually read on success.
9838  */
9839 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9840 {
9841         int i, err;
9842         unsigned int addr, v, nwords;
9843         int cim_num_obq = is_t4(adap->params.chip) ?
9844                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9845
9846         if ((qid > (cim_num_obq - 1)) || (n & 3))
9847                 return -EINVAL;
9848
9849         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9850                      QUENUMSELECT_V(qid));
9851         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9852
9853         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
9854         nwords = CIMQSIZE_G(v) * 64;  /* same */
9855         if (n > nwords)
9856                 n = nwords;
9857
9858         for (i = 0; i < n; i++, addr++) {
9859                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9860                              OBQDBGEN_F);
9861                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9862                                       2, 1);
9863                 if (err)
9864                         return err;
9865                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9866         }
9867         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9868         return i;
9869 }
9870
9871 /**
9872  *      t4_cim_read - read a block from CIM internal address space
9873  *      @adap: the adapter
9874  *      @addr: the start address within the CIM address space
9875  *      @n: number of words to read
9876  *      @valp: where to store the result
9877  *
9878  *      Reads a block of 4-byte words from the CIM intenal address space.
9879  */
9880 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9881                 unsigned int *valp)
9882 {
9883         int ret = 0;
9884
9885         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9886                 return -EBUSY;
9887
9888         for ( ; !ret && n--; addr += 4) {
9889                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9890                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9891                                       0, 5, 2);
9892                 if (!ret)
9893                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9894         }
9895         return ret;
9896 }
9897
9898 /**
9899  *      t4_cim_write - write a block into CIM internal address space
9900  *      @adap: the adapter
9901  *      @addr: the start address within the CIM address space
9902  *      @n: number of words to write
9903  *      @valp: set of values to write
9904  *
9905  *      Writes a block of 4-byte words into the CIM intenal address space.
9906  */
9907 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9908                  const unsigned int *valp)
9909 {
9910         int ret = 0;
9911
9912         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9913                 return -EBUSY;
9914
9915         for ( ; !ret && n--; addr += 4) {
9916                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9917                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9918                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9919                                       0, 5, 2);
9920         }
9921         return ret;
9922 }
9923
9924 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9925                          unsigned int val)
9926 {
9927         return t4_cim_write(adap, addr, 1, &val);
9928 }
9929
9930 /**
9931  *      t4_cim_read_la - read CIM LA capture buffer
9932  *      @adap: the adapter
9933  *      @la_buf: where to store the LA data
9934  *      @wrptr: the HW write pointer within the capture buffer
9935  *
9936  *      Reads the contents of the CIM LA buffer with the most recent entry at
9937  *      the end of the returned data and with the entry at @wrptr first.
9938  *      We try to leave the LA in the running state we find it in.
9939  */
9940 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9941 {
9942         int i, ret;
9943         unsigned int cfg, val, idx;
9944
9945         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9946         if (ret)
9947                 return ret;
9948
9949         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9950                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9951                 if (ret)
9952                         return ret;
9953         }
9954
9955         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9956         if (ret)
9957                 goto restart;
9958
9959         idx = UPDBGLAWRPTR_G(val);
9960         if (wrptr)
9961                 *wrptr = idx;
9962
9963         for (i = 0; i < adap->params.cim_la_size; i++) {
9964                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9965                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9966                 if (ret)
9967                         break;
9968                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9969                 if (ret)
9970                         break;
9971                 if (val & UPDBGLARDEN_F) {
9972                         ret = -ETIMEDOUT;
9973                         break;
9974                 }
9975                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9976                 if (ret)
9977                         break;
9978
9979                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9980                  * identify the 32-bit portion of the full 312-bit data
9981                  */
9982                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9983                         idx = (idx & 0xff0) + 0x10;
9984                 else
9985                         idx++;
9986                 /* address can't exceed 0xfff */
9987                 idx &= UPDBGLARDPTR_M;
9988         }
9989 restart:
9990         if (cfg & UPDBGLAEN_F) {
9991                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9992                                       cfg & ~UPDBGLARDEN_F);
9993                 if (!ret)
9994                         ret = r;
9995         }
9996         return ret;
9997 }
9998
9999 /**
10000  *      t4_tp_read_la - read TP LA capture buffer
10001  *      @adap: the adapter
10002  *      @la_buf: where to store the LA data
10003  *      @wrptr: the HW write pointer within the capture buffer
10004  *
10005  *      Reads the contents of the TP LA buffer with the most recent entry at
10006  *      the end of the returned data and with the entry at @wrptr first.
10007  *      We leave the LA in the running state we find it in.
10008  */
10009 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
10010 {
10011         bool last_incomplete;
10012         unsigned int i, cfg, val, idx;
10013
10014         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
10015         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
10016                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10017                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
10018
10019         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
10020         idx = DBGLAWPTR_G(val);
10021         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
10022         if (last_incomplete)
10023                 idx = (idx + 1) & DBGLARPTR_M;
10024         if (wrptr)
10025                 *wrptr = idx;
10026
10027         val &= 0xffff;
10028         val &= ~DBGLARPTR_V(DBGLARPTR_M);
10029         val |= adap->params.tp.la_mask;
10030
10031         for (i = 0; i < TPLA_SIZE; i++) {
10032                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
10033                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
10034                 idx = (idx + 1) & DBGLARPTR_M;
10035         }
10036
10037         /* Wipe out last entry if it isn't valid */
10038         if (last_incomplete)
10039                 la_buf[TPLA_SIZE - 1] = ~0ULL;
10040
10041         if (cfg & DBGLAENABLE_F)                    /* restore running state */
10042                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10043                              cfg | adap->params.tp.la_mask);
10044 }
10045
10046 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10047  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
10048  * state for more than the Warning Threshold then we'll issue a warning about
10049  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
10050  * appears to be hung every Warning Repeat second till the situation clears.
10051  * If the situation clears, we'll note that as well.
10052  */
10053 #define SGE_IDMA_WARN_THRESH 1
10054 #define SGE_IDMA_WARN_REPEAT 300
10055
10056 /**
10057  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10058  *      @adapter: the adapter
10059  *      @idma: the adapter IDMA Monitor state
10060  *
10061  *      Initialize the state of an SGE Ingress DMA Monitor.
10062  */
10063 void t4_idma_monitor_init(struct adapter *adapter,
10064                           struct sge_idma_monitor_state *idma)
10065 {
10066         /* Initialize the state variables for detecting an SGE Ingress DMA
10067          * hang.  The SGE has internal counters which count up on each clock
10068          * tick whenever the SGE finds its Ingress DMA State Engines in the
10069          * same state they were on the previous clock tick.  The clock used is
10070          * the Core Clock so we have a limit on the maximum "time" they can
10071          * record; typically a very small number of seconds.  For instance,
10072          * with a 600MHz Core Clock, we can only count up to a bit more than
10073          * 7s.  So we'll synthesize a larger counter in order to not run the
10074          * risk of having the "timers" overflow and give us the flexibility to
10075          * maintain a Hung SGE State Machine of our own which operates across
10076          * a longer time frame.
10077          */
10078         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10079         idma->idma_stalled[0] = 0;
10080         idma->idma_stalled[1] = 0;
10081 }
10082
10083 /**
10084  *      t4_idma_monitor - monitor SGE Ingress DMA state
10085  *      @adapter: the adapter
10086  *      @idma: the adapter IDMA Monitor state
10087  *      @hz: number of ticks/second
10088  *      @ticks: number of ticks since the last IDMA Monitor call
10089  */
10090 void t4_idma_monitor(struct adapter *adapter,
10091                      struct sge_idma_monitor_state *idma,
10092                      int hz, int ticks)
10093 {
10094         int i, idma_same_state_cnt[2];
10095
10096          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
10097           * are counters inside the SGE which count up on each clock when the
10098           * SGE finds its Ingress DMA State Engines in the same states they
10099           * were in the previous clock.  The counters will peg out at
10100           * 0xffffffff without wrapping around so once they pass the 1s
10101           * threshold they'll stay above that till the IDMA state changes.
10102           */
10103         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
10104         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10105         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10106
10107         for (i = 0; i < 2; i++) {
10108                 u32 debug0, debug11;
10109
10110                 /* If the Ingress DMA Same State Counter ("timer") is less
10111                  * than 1s, then we can reset our synthesized Stall Timer and
10112                  * continue.  If we have previously emitted warnings about a
10113                  * potential stalled Ingress Queue, issue a note indicating
10114                  * that the Ingress Queue has resumed forward progress.
10115                  */
10116                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10117                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
10118                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
10119                                          "resumed after %d seconds\n",
10120                                          i, idma->idma_qid[i],
10121                                          idma->idma_stalled[i] / hz);
10122                         idma->idma_stalled[i] = 0;
10123                         continue;
10124                 }
10125
10126                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10127                  * domain.  The first time we get here it'll be because we
10128                  * passed the 1s Threshold; each additional time it'll be
10129                  * because the RX Timer Callback is being fired on its regular
10130                  * schedule.
10131                  *
10132                  * If the stall is below our Potential Hung Ingress Queue
10133                  * Warning Threshold, continue.
10134                  */
10135                 if (idma->idma_stalled[i] == 0) {
10136                         idma->idma_stalled[i] = hz;
10137                         idma->idma_warn[i] = 0;
10138                 } else {
10139                         idma->idma_stalled[i] += ticks;
10140                         idma->idma_warn[i] -= ticks;
10141                 }
10142
10143                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
10144                         continue;
10145
10146                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10147                  */
10148                 if (idma->idma_warn[i] > 0)
10149                         continue;
10150                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
10151
10152                 /* Read and save the SGE IDMA State and Queue ID information.
10153                  * We do this every time in case it changes across time ...
10154                  * can't be too careful ...
10155                  */
10156                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
10157                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10158                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10159
10160                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
10161                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10162                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10163
10164                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
10165                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10166                          i, idma->idma_qid[i], idma->idma_state[i],
10167                          idma->idma_stalled[i] / hz,
10168                          debug0, debug11);
10169                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10170         }
10171 }
10172
10173 /**
10174  *      t4_load_cfg - download config file
10175  *      @adap: the adapter
10176  *      @cfg_data: the cfg text file to write
10177  *      @size: text file size
10178  *
10179  *      Write the supplied config text file to the card's serial flash.
10180  */
10181 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10182 {
10183         int ret, i, n, cfg_addr;
10184         unsigned int addr;
10185         unsigned int flash_cfg_start_sec;
10186         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10187
10188         cfg_addr = t4_flash_cfg_addr(adap);
10189         if (cfg_addr < 0)
10190                 return cfg_addr;
10191
10192         addr = cfg_addr;
10193         flash_cfg_start_sec = addr / SF_SEC_SIZE;
10194
10195         if (size > FLASH_CFG_MAX_SIZE) {
10196                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10197                         FLASH_CFG_MAX_SIZE);
10198                 return -EFBIG;
10199         }
10200
10201         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
10202                          sf_sec_size);
10203         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10204                                      flash_cfg_start_sec + i - 1);
10205         /* If size == 0 then we're simply erasing the FLASH sectors associated
10206          * with the on-adapter Firmware Configuration File.
10207          */
10208         if (ret || size == 0)
10209                 goto out;
10210
10211         /* this will write to the flash up to SF_PAGE_SIZE at a time */
10212         for (i = 0; i < size; i += SF_PAGE_SIZE) {
10213                 if ((size - i) <  SF_PAGE_SIZE)
10214                         n = size - i;
10215                 else
10216                         n = SF_PAGE_SIZE;
10217                 ret = t4_write_flash(adap, addr, n, cfg_data);
10218                 if (ret)
10219                         goto out;
10220
10221                 addr += SF_PAGE_SIZE;
10222                 cfg_data += SF_PAGE_SIZE;
10223         }
10224
10225 out:
10226         if (ret)
10227                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
10228                         (size == 0 ? "clear" : "download"), ret);
10229         return ret;
10230 }
10231
10232 /**
10233  *      t4_set_vf_mac - Set MAC address for the specified VF
10234  *      @adapter: The adapter
10235  *      @vf: one of the VFs instantiated by the specified PF
10236  *      @naddr: the number of MAC addresses
10237  *      @addr: the MAC address(es) to be set to the specified VF
10238  */
10239 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
10240                       unsigned int naddr, u8 *addr)
10241 {
10242         struct fw_acl_mac_cmd cmd;
10243
10244         memset(&cmd, 0, sizeof(cmd));
10245         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
10246                                     FW_CMD_REQUEST_F |
10247                                     FW_CMD_WRITE_F |
10248                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
10249                                     FW_ACL_MAC_CMD_VFN_V(vf));
10250
10251         /* Note: Do not enable the ACL */
10252         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10253         cmd.nmac = naddr;
10254
10255         switch (adapter->pf) {
10256         case 3:
10257                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10258                 break;
10259         case 2:
10260                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10261                 break;
10262         case 1:
10263                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10264                 break;
10265         case 0:
10266                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10267                 break;
10268         }
10269
10270         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10271 }
10272
10273 /**
10274  * t4_read_pace_tbl - read the pace table
10275  * @adap: the adapter
10276  * @pace_vals: holds the returned values
10277  *
10278  * Returns the values of TP's pace table in microseconds.
10279  */
10280 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10281 {
10282         unsigned int i, v;
10283
10284         for (i = 0; i < NTX_SCHED; i++) {
10285                 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10286                 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10287                 pace_vals[i] = dack_ticks_to_usec(adap, v);
10288         }
10289 }
10290
10291 /**
10292  * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10293  * @adap: the adapter
10294  * @sched: the scheduler index
10295  * @kbps: the byte rate in Kbps
10296  * @ipg: the interpacket delay in tenths of nanoseconds
10297  * @sleep_ok: if true we may sleep while awaiting command completion
10298  *
10299  * Return the current configuration of a HW Tx scheduler.
10300  */
10301 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10302                      unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10303 {
10304         unsigned int v, addr, bpt, cpt;
10305
10306         if (kbps) {
10307                 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10308                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10309                 if (sched & 1)
10310                         v >>= 16;
10311                 bpt = (v >> 8) & 0xff;
10312                 cpt = v & 0xff;
10313                 if (!cpt) {
10314                         *kbps = 0;      /* scheduler disabled */
10315                 } else {
10316                         v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10317                         *kbps = (v * bpt) / 125;
10318                 }
10319         }
10320         if (ipg) {
10321                 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10322                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10323                 if (sched & 1)
10324                         v >>= 16;
10325                 v &= 0xffff;
10326                 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10327         }
10328 }
10329
10330 /* t4_sge_ctxt_rd - read an SGE context through FW
10331  * @adap: the adapter
10332  * @mbox: mailbox to use for the FW command
10333  * @cid: the context id
10334  * @ctype: the context type
10335  * @data: where to store the context data
10336  *
10337  * Issues a FW command through the given mailbox to read an SGE context.
10338  */
10339 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10340                    enum ctxt_type ctype, u32 *data)
10341 {
10342         struct fw_ldst_cmd c;
10343         int ret;
10344
10345         if (ctype == CTXT_FLM)
10346                 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10347         else
10348                 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10349
10350         memset(&c, 0, sizeof(c));
10351         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10352                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
10353                                         FW_LDST_CMD_ADDRSPACE_V(ret));
10354         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10355         c.u.idctxt.physid = cpu_to_be32(cid);
10356
10357         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10358         if (ret == 0) {
10359                 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10360                 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10361                 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10362                 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10363                 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10364                 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10365         }
10366         return ret;
10367 }
10368
10369 /**
10370  * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10371  * @adap: the adapter
10372  * @cid: the context id
10373  * @ctype: the context type
10374  * @data: where to store the context data
10375  *
10376  * Reads an SGE context directly, bypassing FW.  This is only for
10377  * debugging when FW is unavailable.
10378  */
10379 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10380                       enum ctxt_type ctype, u32 *data)
10381 {
10382         int i, ret;
10383
10384         t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10385         ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10386         if (!ret)
10387                 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10388                         *data++ = t4_read_reg(adap, i);
10389         return ret;
10390 }
10391
10392 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
10393                     u8 rateunit, u8 ratemode, u8 channel, u8 class,
10394                     u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
10395                     u16 burstsize)
10396 {
10397         struct fw_sched_cmd cmd;
10398
10399         memset(&cmd, 0, sizeof(cmd));
10400         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10401                                       FW_CMD_REQUEST_F |
10402                                       FW_CMD_WRITE_F);
10403         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10404
10405         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10406         cmd.u.params.type = type;
10407         cmd.u.params.level = level;
10408         cmd.u.params.mode = mode;
10409         cmd.u.params.ch = channel;
10410         cmd.u.params.cl = class;
10411         cmd.u.params.unit = rateunit;
10412         cmd.u.params.rate = ratemode;
10413         cmd.u.params.min = cpu_to_be32(minrate);
10414         cmd.u.params.max = cpu_to_be32(maxrate);
10415         cmd.u.params.weight = cpu_to_be16(weight);
10416         cmd.u.params.pktsize = cpu_to_be16(pktsize);
10417         cmd.u.params.burstsize = cpu_to_be16(burstsize);
10418
10419         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10420                                NULL, 1);
10421 }
10422
10423 /**
10424  *      t4_i2c_rd - read I2C data from adapter
10425  *      @adap: the adapter
10426  *      @mbox: mailbox to use for the FW command
10427  *      @port: Port number if per-port device; <0 if not
10428  *      @devid: per-port device ID or absolute device ID
10429  *      @offset: byte offset into device I2C space
10430  *      @len: byte length of I2C space data
10431  *      @buf: buffer in which to return I2C data
10432  *
10433  *      Reads the I2C data from the indicated device and location.
10434  */
10435 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10436               unsigned int devid, unsigned int offset,
10437               unsigned int len, u8 *buf)
10438 {
10439         struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10440         unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10441         int ret = 0;
10442
10443         if (len > I2C_PAGE_SIZE)
10444                 return -EINVAL;
10445
10446         /* Dont allow reads that spans multiple pages */
10447         if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10448                 return -EINVAL;
10449
10450         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10451         ldst_cmd.op_to_addrspace =
10452                 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10453                             FW_CMD_REQUEST_F |
10454                             FW_CMD_READ_F |
10455                             FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10456         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10457         ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10458         ldst_cmd.u.i2c.did = devid;
10459
10460         while (len > 0) {
10461                 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10462
10463                 ldst_cmd.u.i2c.boffset = offset;
10464                 ldst_cmd.u.i2c.blen = i2c_len;
10465
10466                 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10467                                  &ldst_rpl);
10468                 if (ret)
10469                         break;
10470
10471                 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10472                 offset += i2c_len;
10473                 buf += i2c_len;
10474                 len -= i2c_len;
10475         }
10476
10477         return ret;
10478 }
10479
10480 /**
10481  *      t4_set_vlan_acl - Set a VLAN id for the specified VF
10482  *      @adap: the adapter
10483  *      @mbox: mailbox to use for the FW command
10484  *      @vf: one of the VFs instantiated by the specified PF
10485  *      @vlan: The vlanid to be set
10486  */
10487 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10488                     u16 vlan)
10489 {
10490         struct fw_acl_vlan_cmd vlan_cmd;
10491         unsigned int enable;
10492
10493         enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10494         memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10495         vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10496                                          FW_CMD_REQUEST_F |
10497                                          FW_CMD_WRITE_F |
10498                                          FW_CMD_EXEC_F |
10499                                          FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10500                                          FW_ACL_VLAN_CMD_VFN_V(vf));
10501         vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10502         /* Drop all packets that donot match vlan id */
10503         vlan_cmd.dropnovlan_fm = (enable
10504                                   ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F |
10505                                      FW_ACL_VLAN_CMD_FM_F) : 0);
10506         if (enable != 0) {
10507                 vlan_cmd.nvlan = 1;
10508                 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10509         }
10510
10511         return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10512 }
10513
10514 /**
10515  *      modify_device_id - Modifies the device ID of the Boot BIOS image
10516  *      @device_id: the device ID to write.
10517  *      @boot_data: the boot image to modify.
10518  *
10519  *      Write the supplied device ID to the boot BIOS image.
10520  */
10521 static void modify_device_id(int device_id, u8 *boot_data)
10522 {
10523         struct cxgb4_pcir_data *pcir_header;
10524         struct legacy_pci_rom_hdr *header;
10525         u8 *cur_header = boot_data;
10526         u16 pcir_offset;
10527
10528          /* Loop through all chained images and change the device ID's */
10529         do {
10530                 header = (struct legacy_pci_rom_hdr *)cur_header;
10531                 pcir_offset = le16_to_cpu(header->pcir_offset);
10532                 pcir_header = (struct cxgb4_pcir_data *)(cur_header +
10533                               pcir_offset);
10534
10535                 /**
10536                  * Only modify the Device ID if code type is Legacy or HP.
10537                  * 0x00: Okay to modify
10538                  * 0x01: FCODE. Do not modify
10539                  * 0x03: Okay to modify
10540                  * 0x04-0xFF: Do not modify
10541                  */
10542                 if (pcir_header->code_type == CXGB4_HDR_CODE1) {
10543                         u8 csum = 0;
10544                         int i;
10545
10546                         /**
10547                          * Modify Device ID to match current adatper
10548                          */
10549                         pcir_header->device_id = cpu_to_le16(device_id);
10550
10551                         /**
10552                          * Set checksum temporarily to 0.
10553                          * We will recalculate it later.
10554                          */
10555                         header->cksum = 0x0;
10556
10557                         /**
10558                          * Calculate and update checksum
10559                          */
10560                         for (i = 0; i < (header->size512 * 512); i++)
10561                                 csum += cur_header[i];
10562
10563                         /**
10564                          * Invert summed value to create the checksum
10565                          * Writing new checksum value directly to the boot data
10566                          */
10567                         cur_header[7] = -csum;
10568
10569                 } else if (pcir_header->code_type == CXGB4_HDR_CODE2) {
10570                         /**
10571                          * Modify Device ID to match current adatper
10572                          */
10573                         pcir_header->device_id = cpu_to_le16(device_id);
10574                 }
10575
10576                 /**
10577                  * Move header pointer up to the next image in the ROM.
10578                  */
10579                 cur_header += header->size512 * 512;
10580         } while (!(pcir_header->indicator & CXGB4_HDR_INDI));
10581 }
10582
10583 /**
10584  *      t4_load_boot - download boot flash
10585  *      @adap: the adapter
10586  *      @boot_data: the boot image to write
10587  *      @boot_addr: offset in flash to write boot_data
10588  *      @size: image size
10589  *
10590  *      Write the supplied boot image to the card's serial flash.
10591  *      The boot image has the following sections: a 28-byte header and the
10592  *      boot image.
10593  */
10594 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10595                  unsigned int boot_addr, unsigned int size)
10596 {
10597         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10598         unsigned int boot_sector = (boot_addr * 1024);
10599         struct cxgb4_pci_exp_rom_header *header;
10600         struct cxgb4_pcir_data *pcir_header;
10601         int pcir_offset;
10602         unsigned int i;
10603         u16 device_id;
10604         int ret, addr;
10605
10606         /**
10607          * Make sure the boot image does not encroach on the firmware region
10608          */
10609         if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10610                 dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
10611                 return -EFBIG;
10612         }
10613
10614         /* Get boot header */
10615         header = (struct cxgb4_pci_exp_rom_header *)boot_data;
10616         pcir_offset = le16_to_cpu(header->pcir_offset);
10617         /* PCIR Data Structure */
10618         pcir_header = (struct cxgb4_pcir_data *)&boot_data[pcir_offset];
10619
10620         /**
10621          * Perform some primitive sanity testing to avoid accidentally
10622          * writing garbage over the boot sectors.  We ought to check for
10623          * more but it's not worth it for now ...
10624          */
10625         if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10626                 dev_err(adap->pdev_dev, "boot image too small/large\n");
10627                 return -EFBIG;
10628         }
10629
10630         if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) {
10631                 dev_err(adap->pdev_dev, "Boot image missing signature\n");
10632                 return -EINVAL;
10633         }
10634
10635         /* Check PCI header signature */
10636         if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) {
10637                 dev_err(adap->pdev_dev, "PCI header missing signature\n");
10638                 return -EINVAL;
10639         }
10640
10641         /* Check Vendor ID matches Chelsio ID*/
10642         if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) {
10643                 dev_err(adap->pdev_dev, "Vendor ID missing signature\n");
10644                 return -EINVAL;
10645         }
10646
10647         /**
10648          * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10649          * and Boot configuration data sections. These 3 boot sections span
10650          * sectors 0 to 7 in flash and live right before the FW image location.
10651          */
10652         i = DIV_ROUND_UP(size ? size : FLASH_FW_START,  sf_sec_size);
10653         ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10654                                      (boot_sector >> 16) + i - 1);
10655
10656         /**
10657          * If size == 0 then we're simply erasing the FLASH sectors associated
10658          * with the on-adapter option ROM file
10659          */
10660         if (ret || size == 0)
10661                 goto out;
10662         /* Retrieve adapter's device ID */
10663         pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id);
10664        /* Want to deal with PF 0 so I strip off PF 4 indicator */
10665         device_id = device_id & 0xf0ff;
10666
10667          /* Check PCIE Device ID */
10668         if (le16_to_cpu(pcir_header->device_id) != device_id) {
10669                 /**
10670                  * Change the device ID in the Boot BIOS image to match
10671                  * the Device ID of the current adapter.
10672                  */
10673                 modify_device_id(device_id, boot_data);
10674         }
10675
10676         /**
10677          * Skip over the first SF_PAGE_SIZE worth of data and write it after
10678          * we finish copying the rest of the boot image. This will ensure
10679          * that the BIOS boot header will only be written if the boot image
10680          * was written in full.
10681          */
10682         addr = boot_sector;
10683         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10684                 addr += SF_PAGE_SIZE;
10685                 boot_data += SF_PAGE_SIZE;
10686                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data);
10687                 if (ret)
10688                         goto out;
10689         }
10690
10691         ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10692                              (const u8 *)header);
10693
10694 out:
10695         if (ret)
10696                 dev_err(adap->pdev_dev, "boot image load failed, error %d\n",
10697                         ret);
10698         return ret;
10699 }
10700
10701 /**
10702  *      t4_flash_bootcfg_addr - return the address of the flash
10703  *      optionrom configuration
10704  *      @adapter: the adapter
10705  *
10706  *      Return the address within the flash where the OptionROM Configuration
10707  *      is stored, or an error if the device FLASH is too small to contain
10708  *      a OptionROM Configuration.
10709  */
10710 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10711 {
10712         /**
10713          * If the device FLASH isn't large enough to hold a Firmware
10714          * Configuration File, return an error.
10715          */
10716         if (adapter->params.sf_size <
10717             FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10718                 return -ENOSPC;
10719
10720         return FLASH_BOOTCFG_START;
10721 }
10722
10723 int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10724 {
10725         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10726         struct cxgb4_bootcfg_data *header;
10727         unsigned int flash_cfg_start_sec;
10728         unsigned int addr, npad;
10729         int ret, i, n, cfg_addr;
10730
10731         cfg_addr = t4_flash_bootcfg_addr(adap);
10732         if (cfg_addr < 0)
10733                 return cfg_addr;
10734
10735         addr = cfg_addr;
10736         flash_cfg_start_sec = addr / SF_SEC_SIZE;
10737
10738         if (size > FLASH_BOOTCFG_MAX_SIZE) {
10739                 dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
10740                         FLASH_BOOTCFG_MAX_SIZE);
10741                 return -EFBIG;
10742         }
10743
10744         header = (struct cxgb4_bootcfg_data *)cfg_data;
10745         if (le16_to_cpu(header->signature) != BOOT_CFG_SIG) {
10746                 dev_err(adap->pdev_dev, "Wrong bootcfg signature\n");
10747                 ret = -EINVAL;
10748                 goto out;
10749         }
10750
10751         i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,
10752                          sf_sec_size);
10753         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10754                                      flash_cfg_start_sec + i - 1);
10755
10756         /**
10757          * If size == 0 then we're simply erasing the FLASH sectors associated
10758          * with the on-adapter OptionROM Configuration File.
10759          */
10760         if (ret || size == 0)
10761                 goto out;
10762
10763         /* this will write to the flash up to SF_PAGE_SIZE at a time */
10764         for (i = 0; i < size; i += SF_PAGE_SIZE) {
10765                 n = min_t(u32, size - i, SF_PAGE_SIZE);
10766
10767                 ret = t4_write_flash(adap, addr, n, cfg_data);
10768                 if (ret)
10769                         goto out;
10770
10771                 addr += SF_PAGE_SIZE;
10772                 cfg_data += SF_PAGE_SIZE;
10773         }
10774
10775         npad = ((size + 4 - 1) & ~3) - size;
10776         for (i = 0; i < npad; i++) {
10777                 u8 data = 0;
10778
10779                 ret = t4_write_flash(adap, cfg_addr + size + i, 1, &data);
10780                 if (ret)
10781                         goto out;
10782         }
10783
10784 out:
10785         if (ret)
10786                 dev_err(adap->pdev_dev, "boot config data %s failed %d\n",
10787                         (size == 0 ? "clear" : "download"), ret);
10788         return ret;
10789 }