2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
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10 * OpenIB.org BSD license below:
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20 * - Redistributions in binary form must reproduce the above
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23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F) {
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 adap->flags &= ~CXGB4_FW_OK;
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
211 for ( ; nflit; nflit--, mbox_addr += 8)
212 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
216 * Handle a FW assertion reported in a mailbox.
218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
220 struct fw_debug_cmd asrt;
222 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
223 dev_alert(adap->pdev_dev,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
226 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
237 static void t4_record_mbox(struct adapter *adapter,
238 const __be64 *cmd, unsigned int size,
239 int access, int execute)
241 struct mbox_cmd_log *log = adapter->mbox_log;
242 struct mbox_cmd *entry;
245 entry = mbox_cmd_log_entry(log, log->cursor++);
246 if (log->cursor == log->size)
249 for (i = 0; i < size / 8; i++)
250 entry->cmd[i] = be64_to_cpu(cmd[i]);
251 while (i < MBOX_LEN / 8)
253 entry->timestamp = jiffies;
254 entry->seqno = log->seqno++;
255 entry->access = access;
256 entry->execute = execute;
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
283 int size, void *rpl, bool sleep_ok, int timeout)
285 static const int delay[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
289 struct mbox_list entry;
294 int i, ms, delay_idx, ret;
295 const __be64 *p = cmd;
296 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
297 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
298 __be64 cmd_rpl[MBOX_LEN / 8];
301 if ((size & 15) || size > MBOX_LEN)
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
308 if (adap->pdev->error_state != pci_channel_io_normal)
311 /* If we have a negative timeout, that implies that we can't sleep. */
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
322 spin_lock_bh(&adap->mbox_lock);
323 list_add_tail(&entry.list, &adap->mlist.list);
324 spin_unlock_bh(&adap->mbox_lock);
329 for (i = 0; ; i += ms) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rarely
333 * contend on access to the mailbox ...
335 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
336 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
337 spin_lock_bh(&adap->mbox_lock);
338 list_del(&entry.list);
339 spin_unlock_bh(&adap->mbox_lock);
340 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
341 t4_record_mbox(adap, cmd, size, access, ret);
345 /* If we're at the head, break out and start the mailbox
348 if (list_first_entry(&adap->mlist.list, struct mbox_list,
352 /* Delay for a bit before checking again ... */
354 ms = delay[delay_idx]; /* last element may repeat */
355 if (delay_idx < ARRAY_SIZE(delay) - 1)
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
368 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
369 if (v != MBOX_OWNER_DRV) {
370 spin_lock_bh(&adap->mbox_lock);
371 list_del(&entry.list);
372 spin_unlock_bh(&adap->mbox_lock);
373 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
374 t4_record_mbox(adap, cmd, size, access, ret);
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap, cmd, size, access, 0);
380 for (i = 0; i < size; i += 8)
381 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
383 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
384 t4_read_reg(adap, ctl_reg); /* flush write */
390 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
394 ms = delay[delay_idx]; /* last element may repeat */
395 if (delay_idx < ARRAY_SIZE(delay) - 1)
401 v = t4_read_reg(adap, ctl_reg);
402 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
403 if (!(v & MBMSGVALID_F)) {
404 t4_write_reg(adap, ctl_reg, 0);
408 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
409 res = be64_to_cpu(cmd_rpl[0]);
411 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
412 fw_asrt(adap, data_reg);
413 res = FW_CMD_RETVAL_V(EIO);
415 memcpy(rpl, cmd_rpl, size);
418 t4_write_reg(adap, ctl_reg, 0);
421 t4_record_mbox(adap, cmd_rpl,
422 MBOX_LEN, access, execute);
423 spin_lock_bh(&adap->mbox_lock);
424 list_del(&entry.list);
425 spin_unlock_bh(&adap->mbox_lock);
426 return -FW_CMD_RETVAL_G((int)res);
430 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
431 t4_record_mbox(adap, cmd, size, access, ret);
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
433 *(const u8 *)cmd, mbox);
434 t4_report_fw_error(adap);
435 spin_lock_bh(&adap->mbox_lock);
436 list_del(&entry.list);
437 spin_unlock_bh(&adap->mbox_lock);
442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
443 void *rpl, bool sleep_ok)
445 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
449 static int t4_edc_err_read(struct adapter *adap, int idx)
451 u32 edc_ecc_err_addr_reg;
454 if (is_t4(adap->params.chip)) {
455 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
458 if (idx != 0 && idx != 1) {
459 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
463 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
464 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx, edc_ecc_err_addr_reg,
469 t4_read_reg(adap, edc_ecc_err_addr_reg));
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 (unsigned long long)t4_read_reg64(adap, rdata_reg),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
480 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
481 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
495 * Get the configured memory window's relative offset, base, and size.
497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
498 u32 *mem_base, u32 *mem_aperture)
500 u32 edc_size, mc_size, mem_reg;
502 /* Offset into the region of memory which is being accessed
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
509 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
510 if (mtype == MEM_HMA) {
511 *mem_off = 2 * (edc_size * 1024 * 1024);
512 } else if (mtype != MEM_MC1) {
513 *mem_off = (mtype * (edc_size * 1024 * 1024));
515 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
516 MA_EXT_MEMORY0_BAR_A));
517 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
528 mem_reg = t4_read_reg(adap,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg == 0xffffffff)
535 *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
536 *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
537 if (is_t4(adap->params.chip))
538 *mem_base -= adap->t4_bar0;
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
549 * Move memory window to specified address.
551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
564 * t4_memory_rw_residual - Read/Write residual data.
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
583 if (dir == T4_MEMORY_READ) {
584 last.word = le32_to_cpu((__force __le32)
585 t4_read_reg(adap, addr));
586 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
587 bp[i] = last.byte[i];
590 for (i = off; i < 4; i++)
592 t4_write_reg(adap, addr,
593 (__force u32)cpu_to_le32(last.word));
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boundaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
615 u32 len, void *hbuf, int dir)
617 u32 pos, offset, resid, memoffset;
618 u32 win_pf, mem_aperture, mem_base;
622 /* Argument sanity checks ...
624 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
636 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr = addr + memoffset;
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
649 pos = addr & ~(mem_aperture - 1);
652 /* Set up initial PCI-E Memory Window to cover the start of our
655 t4_memory_update_win(adap, win, pos | win_pf);
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
660 * A note on Endianness issues:
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
670 * Then a read of the adapter memory via the PCI-E Memory Window
675 * [ b3 | b2 | b1 | b0 ]
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
680 * ( ..., b0, b1, b2, b3, ... )
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
685 * ( ..., b3, b2, b1, b0, ... )
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
692 if (dir == T4_MEMORY_READ)
693 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
696 t4_write_reg(adap, mem_base + offset,
697 (__force u32)cpu_to_le32(*buf++));
698 offset += sizeof(__be32);
699 len -= sizeof(__be32);
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
707 if (offset == mem_aperture) {
710 t4_memory_update_win(adap, win, pos | win_pf);
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
720 t4_memory_rw_residual(adap, resid, mem_base + offset,
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
733 u32 val, ldst_addrspace;
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
738 struct fw_ldst_cmd ldst_cmd;
741 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
742 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
743 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
747 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
748 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd.u.pcie.ctrl_to_fn =
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
751 ldst_cmd.u.pcie.r = reg;
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
759 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
764 t4_hw_pci_read_cfg4(adap, reg, &val);
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
777 if (is_t4(adap->params.chip)) {
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
789 bar0 = t4_read_pcie_cfg4(adap, pci_base);
791 adap->t4_bar0 = bar0;
793 ret = bar0 + memwin_base;
795 /* For T5, only relative offset inside the PCIe BAR is passed */
801 /* Get the default utility window (win0) used by everyone */
802 u32 t4_get_util_window(struct adapter *adap)
804 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
805 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
816 memwin_base | BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
826 * Returns the size of the chip's BAR0 register space.
828 unsigned int t4_get_regs_len(struct adapter *adapter)
830 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
832 switch (chip_version) {
834 return T4_REGMAP_SIZE;
838 return T5_REGMAP_SIZE;
841 dev_err(adapter->pdev_dev,
842 "Unsupported chip version %d\n", chip_version);
847 * t4_get_regs - read chip registers into provided buffer
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
858 static const unsigned int t4_reg_ranges[] = {
1317 static const unsigned int t5_reg_ranges[] = {
2081 static const unsigned int t6_reg_ranges[] = {
2640 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2641 const unsigned int *reg_ranges;
2642 int reg_ranges_size, range;
2643 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2645 /* Select the right set of register ranges to dump depending on the
2646 * adapter chip type.
2648 switch (chip_version) {
2650 reg_ranges = t4_reg_ranges;
2651 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2655 reg_ranges = t5_reg_ranges;
2656 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2660 reg_ranges = t6_reg_ranges;
2661 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2665 dev_err(adap->pdev_dev,
2666 "Unsupported chip version %d\n", chip_version);
2670 /* Clear the register buffer and insert the appropriate register
2671 * values selected by the above register ranges.
2673 memset(buf, 0, buf_size);
2674 for (range = 0; range < reg_ranges_size; range += 2) {
2675 unsigned int reg = reg_ranges[range];
2676 unsigned int last_reg = reg_ranges[range + 1];
2677 u32 *bufp = (u32 *)((char *)buf + reg);
2679 /* Iterate across the register range filling in the register
2680 * buffer but don't write past the end of the register buffer.
2682 while (reg <= last_reg && bufp < buf_end) {
2683 *bufp++ = t4_read_reg(adap, reg);
2689 #define EEPROM_STAT_ADDR 0x7bfc
2690 #define VPD_BASE 0x400
2691 #define VPD_BASE_OLD 0
2692 #define VPD_LEN 1024
2695 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2696 * @phys_addr: the physical EEPROM address
2697 * @fn: the PCI function number
2698 * @sz: size of function-specific area
2700 * Translate a physical EEPROM address to virtual. The first 1K is
2701 * accessed through virtual addresses starting at 31K, the rest is
2702 * accessed through virtual addresses starting at 0.
2704 * The mapping is as follows:
2705 * [0..1K) -> [31K..32K)
2706 * [1K..1K+A) -> [31K-A..31K)
2707 * [1K+A..ES) -> [0..ES-A-1K)
2709 * where A = @fn * @sz, and ES = EEPROM size.
2711 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2714 if (phys_addr < 1024)
2715 return phys_addr + (31 << 10);
2716 if (phys_addr < 1024 + fn)
2717 return 31744 - fn + phys_addr - 1024;
2718 if (phys_addr < EEPROMSIZE)
2719 return phys_addr - 1024 - fn;
2724 * t4_seeprom_wp - enable/disable EEPROM write protection
2725 * @adapter: the adapter
2726 * @enable: whether to enable or disable write protection
2728 * Enables or disables write protection on the serial EEPROM.
2730 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2732 unsigned int v = enable ? 0xc : 0;
2733 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2734 return ret < 0 ? ret : 0;
2738 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2739 * @adapter: adapter to read
2740 * @p: where to store the parameters
2742 * Reads card parameters stored in VPD EEPROM.
2744 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2746 int i, ret = 0, addr;
2748 u8 *vpd, csum, base_val = 0;
2749 unsigned int vpdr_len, kw_offset, id_len;
2751 vpd = vmalloc(VPD_LEN);
2755 /* Card information normally starts at VPD_BASE but early cards had
2758 ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val);
2762 addr = base_val == PCI_VPD_LRDT_ID_STRING ? VPD_BASE : VPD_BASE_OLD;
2764 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2768 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2769 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2774 id_len = pci_vpd_lrdt_size(vpd);
2775 if (id_len > ID_LEN)
2778 i = pci_vpd_find_tag(vpd, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2780 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2785 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2786 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2787 if (vpdr_len + kw_offset > VPD_LEN) {
2788 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2793 #define FIND_VPD_KW(var, name) do { \
2794 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2796 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2800 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2803 FIND_VPD_KW(i, "RV");
2804 for (csum = 0; i >= 0; i--)
2808 dev_err(adapter->pdev_dev,
2809 "corrupted VPD EEPROM, actual csum %u\n", csum);
2814 FIND_VPD_KW(ec, "EC");
2815 FIND_VPD_KW(sn, "SN");
2816 FIND_VPD_KW(pn, "PN");
2817 FIND_VPD_KW(na, "NA");
2820 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2822 memcpy(p->ec, vpd + ec, EC_LEN);
2824 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2825 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2827 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2828 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2830 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2831 strim((char *)p->na);
2835 return ret < 0 ? ret : 0;
2839 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2840 * @adapter: adapter to read
2841 * @p: where to store the parameters
2843 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2844 * Clock. This can only be called after a connection to the firmware
2847 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2849 u32 cclk_param, cclk_val;
2852 /* Grab the raw VPD parameters.
2854 ret = t4_get_raw_vpd_params(adapter, p);
2858 /* Ask firmware for the Core Clock since it knows how to translate the
2859 * Reference Clock ('V2') VPD field into a Core Clock value ...
2861 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2862 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2863 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2864 1, &cclk_param, &cclk_val);
2874 * t4_get_pfres - retrieve VF resource limits
2875 * @adapter: the adapter
2877 * Retrieves configured resource limits and capabilities for a physical
2878 * function. The results are stored in @adapter->pfres.
2880 int t4_get_pfres(struct adapter *adapter)
2882 struct pf_resources *pfres = &adapter->params.pfres;
2883 struct fw_pfvf_cmd cmd, rpl;
2887 /* Execute PFVF Read command to get VF resource limits; bail out early
2888 * with error on command failure.
2890 memset(&cmd, 0, sizeof(cmd));
2891 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2894 FW_PFVF_CMD_PFN_V(adapter->pf) |
2895 FW_PFVF_CMD_VFN_V(0));
2896 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2897 v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2898 if (v != FW_SUCCESS)
2901 /* Extract PF resource limits and return success.
2903 word = be32_to_cpu(rpl.niqflint_niq);
2904 pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2905 pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2907 word = be32_to_cpu(rpl.type_to_neq);
2908 pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2909 pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2911 word = be32_to_cpu(rpl.tc_to_nexactf);
2912 pfres->tc = FW_PFVF_CMD_TC_G(word);
2913 pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2914 pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2916 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2917 pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2918 pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2919 pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2924 /* serial flash and firmware constants */
2926 SF_ATTEMPTS = 10, /* max retries for SF operations */
2928 /* flash command opcodes */
2929 SF_PROG_PAGE = 2, /* program page */
2930 SF_WR_DISABLE = 4, /* disable writes */
2931 SF_RD_STATUS = 5, /* read status register */
2932 SF_WR_ENABLE = 6, /* enable writes */
2933 SF_RD_DATA_FAST = 0xb, /* read flash */
2934 SF_RD_ID = 0x9f, /* read ID */
2935 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2939 * sf1_read - read data from the serial flash
2940 * @adapter: the adapter
2941 * @byte_cnt: number of bytes to read
2942 * @cont: whether another operation will be chained
2943 * @lock: whether to lock SF for PL access only
2944 * @valp: where to store the read data
2946 * Reads up to 4 bytes of data from the serial flash. The location of
2947 * the read needs to be specified prior to calling this by issuing the
2948 * appropriate commands to the serial flash.
2950 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2951 int lock, u32 *valp)
2955 if (!byte_cnt || byte_cnt > 4)
2957 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2959 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2960 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2961 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2963 *valp = t4_read_reg(adapter, SF_DATA_A);
2968 * sf1_write - write data to the serial flash
2969 * @adapter: the adapter
2970 * @byte_cnt: number of bytes to write
2971 * @cont: whether another operation will be chained
2972 * @lock: whether to lock SF for PL access only
2973 * @val: value to write
2975 * Writes up to 4 bytes of data to the serial flash. The location of
2976 * the write needs to be specified prior to calling this by issuing the
2977 * appropriate commands to the serial flash.
2979 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2982 if (!byte_cnt || byte_cnt > 4)
2984 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2986 t4_write_reg(adapter, SF_DATA_A, val);
2987 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2988 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2989 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2993 * flash_wait_op - wait for a flash operation to complete
2994 * @adapter: the adapter
2995 * @attempts: max number of polls of the status register
2996 * @delay: delay between polls in ms
2998 * Wait for a flash operation to complete by polling the status register.
3000 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3006 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3007 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3011 if (--attempts == 0)
3019 * t4_read_flash - read words from serial flash
3020 * @adapter: the adapter
3021 * @addr: the start address for the read
3022 * @nwords: how many 32-bit words to read
3023 * @data: where to store the read data
3024 * @byte_oriented: whether to store data as bytes or as words
3026 * Read the specified number of 32-bit words from the serial flash.
3027 * If @byte_oriented is set the read data is stored as a byte array
3028 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3029 * natural endianness.
3031 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3032 unsigned int nwords, u32 *data, int byte_oriented)
3036 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3039 addr = swab32(addr) | SF_RD_DATA_FAST;
3041 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3042 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3045 for ( ; nwords; nwords--, data++) {
3046 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3048 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3052 *data = (__force __u32)(cpu_to_be32(*data));
3058 * t4_write_flash - write up to a page of data to the serial flash
3059 * @adapter: the adapter
3060 * @addr: the start address to write
3061 * @n: length of data to write in bytes
3062 * @data: the data to write
3063 * @byte_oriented: whether to store data as bytes or as words
3065 * Writes up to a page of data (256 bytes) to the serial flash starting
3066 * at the given address. All the data must be written to the same page.
3067 * If @byte_oriented is set the write data is stored as byte stream
3068 * (i.e. matches what on disk), otherwise in big-endian.
3070 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3071 unsigned int n, const u8 *data, bool byte_oriented)
3073 unsigned int i, c, left, val, offset = addr & 0xff;
3077 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3080 val = swab32(addr) | SF_PROG_PAGE;
3082 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3083 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3086 for (left = n; left; left -= c, data += c) {
3088 for (val = 0, i = 0; i < c; ++i) {
3090 val = (val << 8) + data[i];
3092 val = (val << 8) + data[c - i - 1];
3095 ret = sf1_write(adapter, c, c != left, 1, val);
3099 ret = flash_wait_op(adapter, 8, 1);
3103 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3105 /* Read the page to verify the write succeeded */
3106 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3111 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3112 dev_err(adapter->pdev_dev,
3113 "failed to correctly write the flash page at %#x\n",
3120 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3125 * t4_get_fw_version - read the firmware version
3126 * @adapter: the adapter
3127 * @vers: where to place the version
3129 * Reads the FW version from flash.
3131 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3133 return t4_read_flash(adapter, FLASH_FW_START +
3134 offsetof(struct fw_hdr, fw_ver), 1,
3139 * t4_get_bs_version - read the firmware bootstrap version
3140 * @adapter: the adapter
3141 * @vers: where to place the version
3143 * Reads the FW Bootstrap version from flash.
3145 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3147 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3148 offsetof(struct fw_hdr, fw_ver), 1,
3153 * t4_get_tp_version - read the TP microcode version
3154 * @adapter: the adapter
3155 * @vers: where to place the version
3157 * Reads the TP microcode version from flash.
3159 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3161 return t4_read_flash(adapter, FLASH_FW_START +
3162 offsetof(struct fw_hdr, tp_microcode_ver),
3167 * t4_get_exprom_version - return the Expansion ROM version (if any)
3168 * @adap: the adapter
3169 * @vers: where to place the version
3171 * Reads the Expansion ROM header from FLASH and returns the version
3172 * number (if present) through the @vers return value pointer. We return
3173 * this in the Firmware Version Format since it's convenient. Return
3174 * 0 on success, -ENOENT if no Expansion ROM is present.
3176 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3178 struct exprom_header {
3179 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3180 unsigned char hdr_ver[4]; /* Expansion ROM version */
3182 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3186 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3187 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3192 hdr = (struct exprom_header *)exprom_header_buf;
3193 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3196 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3197 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3198 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3199 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3204 * t4_get_vpd_version - return the VPD version
3205 * @adapter: the adapter
3206 * @vers: where to place the version
3208 * Reads the VPD via the Firmware interface (thus this can only be called
3209 * once we're ready to issue Firmware commands). The format of the
3210 * VPD version is adapter specific. Returns 0 on success, an error on
3213 * Note that early versions of the Firmware didn't include the ability
3214 * to retrieve the VPD version, so we zero-out the return-value parameter
3215 * in that case to avoid leaving it with garbage in it.
3217 * Also note that the Firmware will return its cached copy of the VPD
3218 * Revision ID, not the actual Revision ID as written in the Serial
3219 * EEPROM. This is only an issue if a new VPD has been written and the
3220 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3221 * to defer calling this routine till after a FW_RESET_CMD has been issued
3222 * if the Host Driver will be performing a full adapter initialization.
3224 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3229 vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3230 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3231 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3232 1, &vpdrev_param, vers);
3239 * t4_get_scfg_version - return the Serial Configuration version
3240 * @adapter: the adapter
3241 * @vers: where to place the version
3243 * Reads the Serial Configuration Version via the Firmware interface
3244 * (thus this can only be called once we're ready to issue Firmware
3245 * commands). The format of the Serial Configuration version is
3246 * adapter specific. Returns 0 on success, an error on failure.
3248 * Note that early versions of the Firmware didn't include the ability
3249 * to retrieve the Serial Configuration version, so we zero-out the
3250 * return-value parameter in that case to avoid leaving it with
3253 * Also note that the Firmware will return its cached copy of the Serial
3254 * Initialization Revision ID, not the actual Revision ID as written in
3255 * the Serial EEPROM. This is only an issue if a new VPD has been written
3256 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3257 * it's best to defer calling this routine till after a FW_RESET_CMD has
3258 * been issued if the Host Driver will be performing a full adapter
3261 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3266 scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3267 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3268 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3269 1, &scfgrev_param, vers);
3276 * t4_get_version_info - extract various chip/firmware version information
3277 * @adapter: the adapter
3279 * Reads various chip/firmware version numbers and stores them into the
3280 * adapter Adapter Parameters structure. If any of the efforts fails
3281 * the first failure will be returned, but all of the version numbers
3284 int t4_get_version_info(struct adapter *adapter)
3288 #define FIRST_RET(__getvinfo) \
3290 int __ret = __getvinfo; \
3291 if (__ret && !ret) \
3295 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3296 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3297 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3298 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3299 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3300 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3307 * t4_dump_version_info - dump all of the adapter configuration IDs
3308 * @adapter: the adapter
3310 * Dumps all of the various bits of adapter configuration version/revision
3311 * IDs information. This is typically called at some point after
3312 * t4_get_version_info() has been called.
3314 void t4_dump_version_info(struct adapter *adapter)
3316 /* Device information */
3317 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3318 adapter->params.vpd.id,
3319 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3320 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3321 adapter->params.vpd.sn, adapter->params.vpd.pn);
3323 /* Firmware Version */
3324 if (!adapter->params.fw_vers)
3325 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3327 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3328 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3329 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3330 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3331 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3333 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3334 * Firmware, so dev_info() is more appropriate here.)
3336 if (!adapter->params.bs_vers)
3337 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3339 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3340 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3341 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3342 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3343 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3345 /* TP Microcode Version */
3346 if (!adapter->params.tp_vers)
3347 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3349 dev_info(adapter->pdev_dev,
3350 "TP Microcode version: %u.%u.%u.%u\n",
3351 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3352 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3353 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3354 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3356 /* Expansion ROM version */
3357 if (!adapter->params.er_vers)
3358 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3360 dev_info(adapter->pdev_dev,
3361 "Expansion ROM version: %u.%u.%u.%u\n",
3362 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3363 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3364 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3365 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3367 /* Serial Configuration version */
3368 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3369 adapter->params.scfg_vers);
3372 dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3373 adapter->params.vpd_vers);
3377 * t4_check_fw_version - check if the FW is supported with this driver
3378 * @adap: the adapter
3380 * Checks if an adapter's FW is compatible with the driver. Returns 0
3381 * if there's exact match, a negative error if the version could not be
3382 * read or there's a major version mismatch
3384 int t4_check_fw_version(struct adapter *adap)
3386 int i, ret, major, minor, micro;
3387 int exp_major, exp_minor, exp_micro;
3388 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3390 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3391 /* Try multiple times before returning error */
3392 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3393 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3398 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3399 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3400 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3402 switch (chip_version) {
3404 exp_major = T4FW_MIN_VERSION_MAJOR;
3405 exp_minor = T4FW_MIN_VERSION_MINOR;
3406 exp_micro = T4FW_MIN_VERSION_MICRO;
3409 exp_major = T5FW_MIN_VERSION_MAJOR;
3410 exp_minor = T5FW_MIN_VERSION_MINOR;
3411 exp_micro = T5FW_MIN_VERSION_MICRO;
3414 exp_major = T6FW_MIN_VERSION_MAJOR;
3415 exp_minor = T6FW_MIN_VERSION_MINOR;
3416 exp_micro = T6FW_MIN_VERSION_MICRO;
3419 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3424 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3425 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3426 dev_err(adap->pdev_dev,
3427 "Card has firmware version %u.%u.%u, minimum "
3428 "supported firmware is %u.%u.%u.\n", major, minor,
3429 micro, exp_major, exp_minor, exp_micro);
3435 /* Is the given firmware API compatible with the one the driver was compiled
3438 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3441 /* short circuit if it's the exact same firmware version */
3442 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3445 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3446 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3447 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3454 /* The firmware in the filesystem is usable, but should it be installed?
3455 * This routine explains itself in detail if it indicates the filesystem
3456 * firmware should be installed.
3458 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3463 if (!card_fw_usable) {
3464 reason = "incompatible or unusable";
3469 reason = "older than the version supported with this driver";
3476 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3477 "installing firmware %u.%u.%u.%u on card.\n",
3478 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3479 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3480 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3481 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3486 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3487 const u8 *fw_data, unsigned int fw_size,
3488 struct fw_hdr *card_fw, enum dev_state state,
3491 int ret, card_fw_usable, fs_fw_usable;
3492 const struct fw_hdr *fs_fw;
3493 const struct fw_hdr *drv_fw;
3495 drv_fw = &fw_info->fw_hdr;
3497 /* Read the header of the firmware on the card */
3498 ret = t4_read_flash(adap, FLASH_FW_START,
3499 sizeof(*card_fw) / sizeof(uint32_t),
3500 (uint32_t *)card_fw, 1);
3502 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3504 dev_err(adap->pdev_dev,
3505 "Unable to read card's firmware header: %d\n", ret);
3509 if (fw_data != NULL) {
3510 fs_fw = (const void *)fw_data;
3511 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3517 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3518 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3519 /* Common case: the firmware on the card is an exact match and
3520 * the filesystem one is an exact match too, or the filesystem
3521 * one is absent/incompatible.
3523 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3524 should_install_fs_fw(adap, card_fw_usable,
3525 be32_to_cpu(fs_fw->fw_ver),
3526 be32_to_cpu(card_fw->fw_ver))) {
3527 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3530 dev_err(adap->pdev_dev,
3531 "failed to install firmware: %d\n", ret);
3535 /* Installed successfully, update the cached header too. */
3538 *reset = 0; /* already reset as part of load_fw */
3541 if (!card_fw_usable) {
3544 d = be32_to_cpu(drv_fw->fw_ver);
3545 c = be32_to_cpu(card_fw->fw_ver);
3546 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3548 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3550 "driver compiled with %d.%d.%d.%d, "
3551 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3553 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3554 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3555 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3556 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3557 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3558 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3563 /* We're using whatever's on the card and it's known to be good. */
3564 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3565 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3572 * t4_flash_erase_sectors - erase a range of flash sectors
3573 * @adapter: the adapter
3574 * @start: the first sector to erase
3575 * @end: the last sector to erase
3577 * Erases the sectors in the given inclusive range.
3579 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3583 if (end >= adapter->params.sf_nsec)
3586 while (start <= end) {
3587 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3588 (ret = sf1_write(adapter, 4, 0, 1,
3589 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3590 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3591 dev_err(adapter->pdev_dev,
3592 "erase of flash sector %d failed, error %d\n",
3598 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3603 * t4_flash_cfg_addr - return the address of the flash configuration file
3604 * @adapter: the adapter
3606 * Return the address within the flash where the Firmware Configuration
3609 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3611 if (adapter->params.sf_size == 0x100000)
3612 return FLASH_FPGA_CFG_START;
3614 return FLASH_CFG_START;
3617 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3618 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3619 * and emit an error message for mismatched firmware to save our caller the
3622 static bool t4_fw_matches_chip(const struct adapter *adap,
3623 const struct fw_hdr *hdr)
3625 /* The expression below will return FALSE for any unsupported adapter
3626 * which will keep us "honest" in the future ...
3628 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3629 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3630 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3633 dev_err(adap->pdev_dev,
3634 "FW image (%d) is not suitable for this adapter (%d)\n",
3635 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3640 * t4_load_fw - download firmware
3641 * @adap: the adapter
3642 * @fw_data: the firmware image to write
3645 * Write the supplied firmware image to the card's serial flash.
3647 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3652 u8 first_page[SF_PAGE_SIZE];
3653 const __be32 *p = (const __be32 *)fw_data;
3654 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3655 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3656 unsigned int fw_start_sec = FLASH_FW_START_SEC;
3657 unsigned int fw_size = FLASH_FW_MAX_SIZE;
3658 unsigned int fw_start = FLASH_FW_START;
3661 dev_err(adap->pdev_dev, "FW image has no data\n");
3665 dev_err(adap->pdev_dev,
3666 "FW image size not multiple of 512 bytes\n");
3669 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3670 dev_err(adap->pdev_dev,
3671 "FW image size differs from size in FW header\n");
3674 if (size > fw_size) {
3675 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3679 if (!t4_fw_matches_chip(adap, hdr))
3682 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3683 csum += be32_to_cpu(p[i]);
3685 if (csum != 0xffffffff) {
3686 dev_err(adap->pdev_dev,
3687 "corrupted firmware image, checksum %#x\n", csum);
3691 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3692 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3697 * We write the correct version at the end so the driver can see a bad
3698 * version if the FW write fails. Start by writing a copy of the
3699 * first page with a bad version.
3701 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3702 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3703 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, true);
3708 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3709 addr += SF_PAGE_SIZE;
3710 fw_data += SF_PAGE_SIZE;
3711 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, true);
3716 ret = t4_write_flash(adap, fw_start + offsetof(struct fw_hdr, fw_ver),
3717 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver,
3721 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3724 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3729 * t4_phy_fw_ver - return current PHY firmware version
3730 * @adap: the adapter
3731 * @phy_fw_ver: return value buffer for PHY firmware version
3733 * Returns the current version of external PHY firmware on the
3736 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3741 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3742 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3743 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3744 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3745 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3754 * t4_load_phy_fw - download port PHY firmware
3755 * @adap: the adapter
3756 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3757 * @phy_fw_version: function to check PHY firmware versions
3758 * @phy_fw_data: the PHY firmware image to write
3759 * @phy_fw_size: image size
3761 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3762 * @phy_fw_version is supplied, then it will be used to determine if
3763 * it's necessary to perform the transfer by comparing the version
3764 * of any existing adapter PHY firmware with that of the passed in
3765 * PHY firmware image.
3767 * A negative error number will be returned if an error occurs. If
3768 * version number support is available and there's no need to upgrade
3769 * the firmware, 0 will be returned. If firmware is successfully
3770 * transferred to the adapter, 1 will be returned.
3772 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3773 * a result, a RESET of the adapter would cause that RAM to lose its
3774 * contents. Thus, loading PHY firmware on such adapters must happen
3775 * after any FW_RESET_CMDs ...
3777 int t4_load_phy_fw(struct adapter *adap, int win,
3778 int (*phy_fw_version)(const u8 *, size_t),
3779 const u8 *phy_fw_data, size_t phy_fw_size)
3781 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3782 unsigned long mtype = 0, maddr = 0;
3786 /* If we have version number support, then check to see if the adapter
3787 * already has up-to-date PHY firmware loaded.
3789 if (phy_fw_version) {
3790 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3791 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3795 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3796 CH_WARN(adap, "PHY Firmware already up-to-date, "
3797 "version %#x\n", cur_phy_fw_ver);
3802 /* Ask the firmware where it wants us to copy the PHY firmware image.
3803 * The size of the file requires a special version of the READ command
3804 * which will pass the file size via the values field in PARAMS_CMD and
3805 * retrieve the return value from firmware and place it in the same
3808 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3809 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3810 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3811 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3813 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3814 ¶m, &val, 1, true);
3818 maddr = (val & 0xff) << 16;
3820 /* Copy the supplied PHY Firmware image to the adapter memory location
3821 * allocated by the adapter firmware.
3823 spin_lock_bh(&adap->win0_lock);
3824 ret = t4_memory_rw(adap, win, mtype, maddr,
3825 phy_fw_size, (__be32 *)phy_fw_data,
3827 spin_unlock_bh(&adap->win0_lock);
3831 /* Tell the firmware that the PHY firmware image has been written to
3832 * RAM and it can now start copying it over to the PHYs. The chip
3833 * firmware will RESET the affected PHYs as part of this operation
3834 * leaving them running the new PHY firmware image.
3836 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3837 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3838 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3839 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3840 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3841 ¶m, &val, 30000);
3843 /* If we have version number support, then check to see that the new
3844 * firmware got loaded properly.
3846 if (phy_fw_version) {
3847 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3851 if (cur_phy_fw_ver != new_phy_fw_vers) {
3852 CH_WARN(adap, "PHY Firmware did not update: "
3853 "version on adapter %#x, "
3854 "version flashed %#x\n",
3855 cur_phy_fw_ver, new_phy_fw_vers);
3864 * t4_fwcache - firmware cache operation
3865 * @adap: the adapter
3866 * @op : the operation (flush or flush and invalidate)
3868 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3870 struct fw_params_cmd c;
3872 memset(&c, 0, sizeof(c));
3874 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3875 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3876 FW_PARAMS_CMD_PFN_V(adap->pf) |
3877 FW_PARAMS_CMD_VFN_V(0));
3878 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3880 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3881 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3882 c.param[0].val = cpu_to_be32(op);
3884 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3887 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3888 unsigned int *pif_req_wrptr,
3889 unsigned int *pif_rsp_wrptr)
3892 u32 cfg, val, req, rsp;
3894 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3895 if (cfg & LADBGEN_F)
3896 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3898 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3899 req = POLADBGWRPTR_G(val);
3900 rsp = PILADBGWRPTR_G(val);
3902 *pif_req_wrptr = req;
3904 *pif_rsp_wrptr = rsp;
3906 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3907 for (j = 0; j < 6; j++) {
3908 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3909 PILADBGRDPTR_V(rsp));
3910 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3911 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3915 req = (req + 2) & POLADBGRDPTR_M;
3916 rsp = (rsp + 2) & PILADBGRDPTR_M;
3918 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3921 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3926 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3927 if (cfg & LADBGEN_F)
3928 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3930 for (i = 0; i < CIM_MALA_SIZE; i++) {
3931 for (j = 0; j < 5; j++) {
3933 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3934 PILADBGRDPTR_V(idx));
3935 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3936 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3939 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3942 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3946 for (i = 0; i < 8; i++) {
3947 u32 *p = la_buf + i;
3949 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3950 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3951 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3952 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3953 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3957 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3958 * Capabilities which we control with separate controls -- see, for instance,
3959 * Pause Frames and Forward Error Correction. In order to determine what the
3960 * full set of Advertised Port Capabilities are, the base Advertised Port
3961 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3962 * Port Capabilities associated with those other controls. See
3963 * t4_link_acaps() for how this is done.
3965 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3969 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3970 * @caps16: a 16-bit Port Capabilities value
3972 * Returns the equivalent 32-bit Port Capabilities value.
3974 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3976 fw_port_cap32_t caps32 = 0;
3978 #define CAP16_TO_CAP32(__cap) \
3980 if (caps16 & FW_PORT_CAP_##__cap) \
3981 caps32 |= FW_PORT_CAP32_##__cap; \
3984 CAP16_TO_CAP32(SPEED_100M);
3985 CAP16_TO_CAP32(SPEED_1G);
3986 CAP16_TO_CAP32(SPEED_25G);
3987 CAP16_TO_CAP32(SPEED_10G);
3988 CAP16_TO_CAP32(SPEED_40G);
3989 CAP16_TO_CAP32(SPEED_100G);
3990 CAP16_TO_CAP32(FC_RX);
3991 CAP16_TO_CAP32(FC_TX);
3992 CAP16_TO_CAP32(ANEG);
3993 CAP16_TO_CAP32(FORCE_PAUSE);
3994 CAP16_TO_CAP32(MDIAUTO);
3995 CAP16_TO_CAP32(MDISTRAIGHT);
3996 CAP16_TO_CAP32(FEC_RS);
3997 CAP16_TO_CAP32(FEC_BASER_RS);
3998 CAP16_TO_CAP32(802_3_PAUSE);
3999 CAP16_TO_CAP32(802_3_ASM_DIR);
4001 #undef CAP16_TO_CAP32
4007 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4008 * @caps32: a 32-bit Port Capabilities value
4010 * Returns the equivalent 16-bit Port Capabilities value. Note that
4011 * not all 32-bit Port Capabilities can be represented in the 16-bit
4012 * Port Capabilities and some fields/values may not make it.
4014 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4016 fw_port_cap16_t caps16 = 0;
4018 #define CAP32_TO_CAP16(__cap) \
4020 if (caps32 & FW_PORT_CAP32_##__cap) \
4021 caps16 |= FW_PORT_CAP_##__cap; \
4024 CAP32_TO_CAP16(SPEED_100M);
4025 CAP32_TO_CAP16(SPEED_1G);
4026 CAP32_TO_CAP16(SPEED_10G);
4027 CAP32_TO_CAP16(SPEED_25G);
4028 CAP32_TO_CAP16(SPEED_40G);
4029 CAP32_TO_CAP16(SPEED_100G);
4030 CAP32_TO_CAP16(FC_RX);
4031 CAP32_TO_CAP16(FC_TX);
4032 CAP32_TO_CAP16(802_3_PAUSE);
4033 CAP32_TO_CAP16(802_3_ASM_DIR);
4034 CAP32_TO_CAP16(ANEG);
4035 CAP32_TO_CAP16(FORCE_PAUSE);
4036 CAP32_TO_CAP16(MDIAUTO);
4037 CAP32_TO_CAP16(MDISTRAIGHT);
4038 CAP32_TO_CAP16(FEC_RS);
4039 CAP32_TO_CAP16(FEC_BASER_RS);
4041 #undef CAP32_TO_CAP16
4046 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4047 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4049 enum cc_pause cc_pause = 0;
4051 if (fw_pause & FW_PORT_CAP32_FC_RX)
4052 cc_pause |= PAUSE_RX;
4053 if (fw_pause & FW_PORT_CAP32_FC_TX)
4054 cc_pause |= PAUSE_TX;
4059 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4060 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4062 /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4065 fw_port_cap32_t fw_pause = 0;
4067 if (cc_pause & PAUSE_RX)
4068 fw_pause |= FW_PORT_CAP32_FC_RX;
4069 if (cc_pause & PAUSE_TX)
4070 fw_pause |= FW_PORT_CAP32_FC_TX;
4071 if (!(cc_pause & PAUSE_AUTONEG))
4072 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4074 /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4075 * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4076 * Note that these bits are ignored in L1 Configure commands.
4078 if (cc_pause & PAUSE_RX) {
4079 if (cc_pause & PAUSE_TX)
4080 fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4082 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4083 FW_PORT_CAP32_802_3_PAUSE;
4084 } else if (cc_pause & PAUSE_TX) {
4085 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4091 /* Translate Firmware Forward Error Correction specification to Common Code */
4092 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4094 enum cc_fec cc_fec = 0;
4096 if (fw_fec & FW_PORT_CAP32_FEC_RS)
4098 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4099 cc_fec |= FEC_BASER_RS;
4104 /* Translate Common Code Forward Error Correction specification to Firmware */
4105 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4107 fw_port_cap32_t fw_fec = 0;
4109 if (cc_fec & FEC_RS)
4110 fw_fec |= FW_PORT_CAP32_FEC_RS;
4111 if (cc_fec & FEC_BASER_RS)
4112 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4118 * t4_link_acaps - compute Link Advertised Port Capabilities
4119 * @adapter: the adapter
4120 * @port: the Port ID
4121 * @lc: the Port's Link Configuration
4123 * Synthesize the Advertised Port Capabilities we'll be using based on
4124 * the base Advertised Port Capabilities (which have been filtered by
4125 * ADVERT_MASK) plus the individual controls for things like Pause
4126 * Frames, Forward Error Correction, MDI, etc.
4128 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4129 struct link_config *lc)
4131 fw_port_cap32_t fw_fc, fw_fec, acaps;
4132 unsigned int fw_mdi;
4135 fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4137 /* Convert driver coding of Pause Frame Flow Control settings into the
4140 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4142 /* Convert Common Code Forward Error Control settings into the
4143 * Firmware's API. If the current Requested FEC has "Automatic"
4144 * (IEEE 802.3) specified, then we use whatever the Firmware
4145 * sent us as part of its IEEE 802.3-based interpretation of
4146 * the Transceiver Module EPROM FEC parameters. Otherwise we
4147 * use whatever is in the current Requested FEC settings.
4149 if (lc->requested_fec & FEC_AUTO)
4150 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4152 cc_fec = lc->requested_fec;
4153 fw_fec = cc_to_fwcap_fec(cc_fec);
4155 /* Figure out what our Requested Port Capabilities are going to be.
4156 * Note parallel structure in t4_handle_get_port_info() and
4157 * init_link_config().
4159 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4160 acaps = lc->acaps | fw_fc | fw_fec;
4161 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4163 } else if (lc->autoneg == AUTONEG_DISABLE) {
4164 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4165 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4168 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4171 /* Some Requested Port Capabilities are trivially wrong if they exceed
4172 * the Physical Port Capabilities. We can check that here and provide
4173 * moderately useful feedback in the system log.
4175 * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4176 * we need to exclude this from this check in order to maintain
4179 if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4180 dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4189 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4190 * @adapter: the adapter
4191 * @mbox: the Firmware Mailbox to use
4192 * @port: the Port ID
4193 * @lc: the Port's Link Configuration
4194 * @sleep_ok: if true we may sleep while awaiting command completion
4195 * @timeout: time to wait for command to finish before timing out
4196 * (negative implies @sleep_ok=false)
4198 * Set up a port's MAC and PHY according to a desired link configuration.
4199 * - If the PHY can auto-negotiate first decide what to advertise, then
4200 * enable/disable auto-negotiation as desired, and reset.
4201 * - If the PHY does not auto-negotiate just reset it.
4202 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4203 * otherwise do it later based on the outcome of auto-negotiation.
4205 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4206 unsigned int port, struct link_config *lc,
4207 u8 sleep_ok, int timeout)
4209 unsigned int fw_caps = adapter->params.fw_caps_support;
4210 struct fw_port_cmd cmd;
4211 fw_port_cap32_t rcap;
4214 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4215 lc->autoneg == AUTONEG_ENABLE) {
4219 /* Compute our Requested Port Capabilities and send that on to the
4222 rcap = t4_link_acaps(adapter, port, lc);
4223 memset(&cmd, 0, sizeof(cmd));
4224 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4225 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4226 FW_PORT_CMD_PORTID_V(port));
4227 cmd.action_to_len16 =
4228 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4229 ? FW_PORT_ACTION_L1_CFG
4230 : FW_PORT_ACTION_L1_CFG32) |
4232 if (fw_caps == FW_CAPS16)
4233 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4235 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4237 ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4240 /* Unfortunately, even if the Requested Port Capabilities "fit" within
4241 * the Physical Port Capabilities, some combinations of features may
4242 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
4243 * Error Correction. So if the Firmware rejects the L1 Configure
4244 * request, flag that here.
4247 dev_err(adapter->pdev_dev,
4248 "Requested Port Capabilities %#x rejected, error %d\n",
4256 * t4_restart_aneg - restart autonegotiation
4257 * @adap: the adapter
4258 * @mbox: mbox to use for the FW command
4259 * @port: the port id
4261 * Restarts autonegotiation for the selected port.
4263 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4265 unsigned int fw_caps = adap->params.fw_caps_support;
4266 struct fw_port_cmd c;
4268 memset(&c, 0, sizeof(c));
4269 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4270 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4271 FW_PORT_CMD_PORTID_V(port));
4273 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4274 ? FW_PORT_ACTION_L1_CFG
4275 : FW_PORT_ACTION_L1_CFG32) |
4277 if (fw_caps == FW_CAPS16)
4278 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4280 c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4281 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4284 typedef void (*int_handler_t)(struct adapter *adap);
4287 unsigned int mask; /* bits to check in interrupt status */
4288 const char *msg; /* message to print or NULL */
4289 short stat_idx; /* stat counter to increment or -1 */
4290 unsigned short fatal; /* whether the condition reported is fatal */
4291 int_handler_t int_handler; /* platform-specific int handler */
4295 * t4_handle_intr_status - table driven interrupt handler
4296 * @adapter: the adapter that generated the interrupt
4297 * @reg: the interrupt status register to process
4298 * @acts: table of interrupt actions
4300 * A table driven interrupt handler that applies a set of masks to an
4301 * interrupt status word and performs the corresponding actions if the
4302 * interrupts described by the mask have occurred. The actions include
4303 * optionally emitting a warning or alert message. The table is terminated
4304 * by an entry specifying mask 0. Returns the number of fatal interrupt
4307 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4308 const struct intr_info *acts)
4311 unsigned int mask = 0;
4312 unsigned int status = t4_read_reg(adapter, reg);
4314 for ( ; acts->mask; ++acts) {
4315 if (!(status & acts->mask))
4319 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4320 status & acts->mask);
4321 } else if (acts->msg && printk_ratelimit())
4322 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4323 status & acts->mask);
4324 if (acts->int_handler)
4325 acts->int_handler(adapter);
4329 if (status) /* clear processed interrupts */
4330 t4_write_reg(adapter, reg, status);
4335 * Interrupt handler for the PCIE module.
4337 static void pcie_intr_handler(struct adapter *adapter)
4339 static const struct intr_info sysbus_intr_info[] = {
4340 { RNPP_F, "RXNP array parity error", -1, 1 },
4341 { RPCP_F, "RXPC array parity error", -1, 1 },
4342 { RCIP_F, "RXCIF array parity error", -1, 1 },
4343 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4344 { RFTP_F, "RXFT array parity error", -1, 1 },
4347 static const struct intr_info pcie_port_intr_info[] = {
4348 { TPCP_F, "TXPC array parity error", -1, 1 },
4349 { TNPP_F, "TXNP array parity error", -1, 1 },
4350 { TFTP_F, "TXFT array parity error", -1, 1 },
4351 { TCAP_F, "TXCA array parity error", -1, 1 },
4352 { TCIP_F, "TXCIF array parity error", -1, 1 },
4353 { RCAP_F, "RXCA array parity error", -1, 1 },
4354 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4355 { RDPE_F, "Rx data parity error", -1, 1 },
4356 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4359 static const struct intr_info pcie_intr_info[] = {
4360 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4361 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4362 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4363 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4364 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4365 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4366 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4367 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4368 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4369 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4370 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4371 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4372 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4373 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4374 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4375 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4376 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4377 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4378 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4379 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4380 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4381 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4382 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4383 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4384 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4385 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4386 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4387 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4388 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4389 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4394 static struct intr_info t5_pcie_intr_info[] = {
4395 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4397 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4398 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4399 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4400 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4401 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4402 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4403 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4405 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4407 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4408 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4409 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4410 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4411 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4413 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4414 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4415 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4416 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4417 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4418 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4419 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4420 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4421 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4422 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4423 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4425 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4427 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4428 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4429 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4430 { READRSPERR_F, "Outbound read error", -1, 0 },
4436 if (is_t4(adapter->params.chip))
4437 fat = t4_handle_intr_status(adapter,
4438 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4440 t4_handle_intr_status(adapter,
4441 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4442 pcie_port_intr_info) +
4443 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4446 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4450 t4_fatal_err(adapter);
4454 * TP interrupt handler.
4456 static void tp_intr_handler(struct adapter *adapter)
4458 static const struct intr_info tp_intr_info[] = {
4459 { 0x3fffffff, "TP parity error", -1, 1 },
4460 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4464 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4465 t4_fatal_err(adapter);
4469 * SGE interrupt handler.
4471 static void sge_intr_handler(struct adapter *adapter)
4476 static const struct intr_info sge_intr_info[] = {
4477 { ERR_CPL_EXCEED_IQE_SIZE_F,
4478 "SGE received CPL exceeding IQE size", -1, 1 },
4479 { ERR_INVALID_CIDX_INC_F,
4480 "SGE GTS CIDX increment too large", -1, 0 },
4481 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4482 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4483 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4484 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4485 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4487 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4489 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4491 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4493 { ERR_ING_CTXT_PRIO_F,
4494 "SGE too many priority ingress contexts", -1, 0 },
4495 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4496 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4500 static struct intr_info t4t5_sge_intr_info[] = {
4501 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4502 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4503 { ERR_EGR_CTXT_PRIO_F,
4504 "SGE too many priority egress contexts", -1, 0 },
4508 perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4511 dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
4515 perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4518 dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
4522 if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
4523 perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4524 /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4525 perr &= ~ERR_T_RXCRC_F;
4528 dev_alert(adapter->pdev_dev,
4529 "SGE Cause5 Parity Error %#x\n", perr);
4533 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4534 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4535 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4536 t4t5_sge_intr_info);
4538 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4539 if (err & ERROR_QID_VALID_F) {
4540 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4542 if (err & UNCAPTURED_ERROR_F)
4543 dev_err(adapter->pdev_dev,
4544 "SGE UNCAPTURED_ERROR set (clearing)\n");
4545 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4546 UNCAPTURED_ERROR_F);
4550 t4_fatal_err(adapter);
4553 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4554 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4555 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4556 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4559 * CIM interrupt handler.
4561 static void cim_intr_handler(struct adapter *adapter)
4563 static const struct intr_info cim_intr_info[] = {
4564 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4565 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4566 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4567 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4568 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4569 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4570 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4571 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4574 static const struct intr_info cim_upintr_info[] = {
4575 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4576 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4577 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4578 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4579 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4580 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4581 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4582 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4583 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4584 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4585 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4586 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4587 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4588 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4589 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4590 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4591 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4592 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4593 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4594 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4595 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4596 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4597 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4598 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4599 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4600 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4601 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4602 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4609 fw_err = t4_read_reg(adapter, PCIE_FW_A);
4610 if (fw_err & PCIE_FW_ERR_F)
4611 t4_report_fw_error(adapter);
4613 /* When the Firmware detects an internal error which normally
4614 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4615 * in order to make sure the Host sees the Firmware Crash. So
4616 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4617 * ignore the Timer0 interrupt.
4620 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4621 if (val & TIMER0INT_F)
4622 if (!(fw_err & PCIE_FW_ERR_F) ||
4623 (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4624 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4627 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4629 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4632 t4_fatal_err(adapter);
4636 * ULP RX interrupt handler.
4638 static void ulprx_intr_handler(struct adapter *adapter)
4640 static const struct intr_info ulprx_intr_info[] = {
4641 { 0x1800000, "ULPRX context error", -1, 1 },
4642 { 0x7fffff, "ULPRX parity error", -1, 1 },
4646 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4647 t4_fatal_err(adapter);
4651 * ULP TX interrupt handler.
4653 static void ulptx_intr_handler(struct adapter *adapter)
4655 static const struct intr_info ulptx_intr_info[] = {
4656 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4658 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4660 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4662 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4664 { 0xfffffff, "ULPTX parity error", -1, 1 },
4668 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4669 t4_fatal_err(adapter);
4673 * PM TX interrupt handler.
4675 static void pmtx_intr_handler(struct adapter *adapter)
4677 static const struct intr_info pmtx_intr_info[] = {
4678 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4679 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4680 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4681 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4682 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4683 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4684 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4686 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4687 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4691 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4692 t4_fatal_err(adapter);
4696 * PM RX interrupt handler.
4698 static void pmrx_intr_handler(struct adapter *adapter)
4700 static const struct intr_info pmrx_intr_info[] = {
4701 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4702 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4703 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4704 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4706 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4707 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4711 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4712 t4_fatal_err(adapter);
4716 * CPL switch interrupt handler.
4718 static void cplsw_intr_handler(struct adapter *adapter)
4720 static const struct intr_info cplsw_intr_info[] = {
4721 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4722 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4723 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4724 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4725 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4726 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4730 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4731 t4_fatal_err(adapter);
4735 * LE interrupt handler.
4737 static void le_intr_handler(struct adapter *adap)
4739 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4740 static const struct intr_info le_intr_info[] = {
4741 { LIPMISS_F, "LE LIP miss", -1, 0 },
4742 { LIP0_F, "LE 0 LIP error", -1, 0 },
4743 { PARITYERR_F, "LE parity error", -1, 1 },
4744 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4745 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4749 static struct intr_info t6_le_intr_info[] = {
4750 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4751 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4752 { CMDTIDERR_F, "LE cmd tid error", -1, 1 },
4753 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4754 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4755 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4756 { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },
4760 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4761 (chip <= CHELSIO_T5) ?
4762 le_intr_info : t6_le_intr_info))
4767 * MPS interrupt handler.
4769 static void mps_intr_handler(struct adapter *adapter)
4771 static const struct intr_info mps_rx_intr_info[] = {
4772 { 0xffffff, "MPS Rx parity error", -1, 1 },
4775 static const struct intr_info mps_tx_intr_info[] = {
4776 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4777 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4778 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4780 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4782 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4783 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4784 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4787 static const struct intr_info t6_mps_tx_intr_info[] = {
4788 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4789 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4790 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4792 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4794 /* MPS Tx Bubble is normal for T6 */
4795 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4796 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4799 static const struct intr_info mps_trc_intr_info[] = {
4800 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4801 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4803 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4806 static const struct intr_info mps_stat_sram_intr_info[] = {
4807 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4810 static const struct intr_info mps_stat_tx_intr_info[] = {
4811 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4814 static const struct intr_info mps_stat_rx_intr_info[] = {
4815 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4818 static const struct intr_info mps_cls_intr_info[] = {
4819 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4820 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4821 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4827 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4829 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4830 is_t6(adapter->params.chip)
4831 ? t6_mps_tx_intr_info
4832 : mps_tx_intr_info) +
4833 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4834 mps_trc_intr_info) +
4835 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4836 mps_stat_sram_intr_info) +
4837 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4838 mps_stat_tx_intr_info) +
4839 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4840 mps_stat_rx_intr_info) +
4841 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4844 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4845 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4847 t4_fatal_err(adapter);
4850 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4854 * EDC/MC interrupt handler.
4856 static void mem_intr_handler(struct adapter *adapter, int idx)
4858 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4860 unsigned int addr, cnt_addr, v;
4862 if (idx <= MEM_EDC1) {
4863 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4864 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4865 } else if (idx == MEM_MC) {
4866 if (is_t4(adapter->params.chip)) {
4867 addr = MC_INT_CAUSE_A;
4868 cnt_addr = MC_ECC_STATUS_A;
4870 addr = MC_P_INT_CAUSE_A;
4871 cnt_addr = MC_P_ECC_STATUS_A;
4874 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4875 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4878 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4879 if (v & PERR_INT_CAUSE_F)
4880 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4882 if (v & ECC_CE_INT_CAUSE_F) {
4883 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4885 t4_edc_err_read(adapter, idx);
4887 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4888 if (printk_ratelimit())
4889 dev_warn(adapter->pdev_dev,
4890 "%u %s correctable ECC data error%s\n",
4891 cnt, name[idx], cnt > 1 ? "s" : "");
4893 if (v & ECC_UE_INT_CAUSE_F)
4894 dev_alert(adapter->pdev_dev,
4895 "%s uncorrectable ECC data error\n", name[idx]);
4897 t4_write_reg(adapter, addr, v);
4898 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4899 t4_fatal_err(adapter);
4903 * MA interrupt handler.
4905 static void ma_intr_handler(struct adapter *adap)
4907 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4909 if (status & MEM_PERR_INT_CAUSE_F) {
4910 dev_alert(adap->pdev_dev,
4911 "MA parity error, parity status %#x\n",
4912 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4913 if (is_t5(adap->params.chip))
4914 dev_alert(adap->pdev_dev,
4915 "MA parity error, parity status %#x\n",
4917 MA_PARITY_ERROR_STATUS2_A));
4919 if (status & MEM_WRAP_INT_CAUSE_F) {
4920 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4921 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4922 "client %u to address %#x\n",
4923 MEM_WRAP_CLIENT_NUM_G(v),
4924 MEM_WRAP_ADDRESS_G(v) << 4);
4926 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4931 * SMB interrupt handler.
4933 static void smb_intr_handler(struct adapter *adap)
4935 static const struct intr_info smb_intr_info[] = {
4936 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4937 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4938 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4942 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4947 * NC-SI interrupt handler.
4949 static void ncsi_intr_handler(struct adapter *adap)
4951 static const struct intr_info ncsi_intr_info[] = {
4952 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4953 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4954 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4955 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4959 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4964 * XGMAC interrupt handler.
4966 static void xgmac_intr_handler(struct adapter *adap, int port)
4968 u32 v, int_cause_reg;
4970 if (is_t4(adap->params.chip))
4971 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4973 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4975 v = t4_read_reg(adap, int_cause_reg);
4977 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4981 if (v & TXFIFO_PRTY_ERR_F)
4982 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4984 if (v & RXFIFO_PRTY_ERR_F)
4985 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4987 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4992 * PL interrupt handler.
4994 static void pl_intr_handler(struct adapter *adap)
4996 static const struct intr_info pl_intr_info[] = {
4997 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4998 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
5002 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
5006 #define PF_INTR_MASK (PFSW_F)
5007 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5008 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5009 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5012 * t4_slow_intr_handler - control path interrupt handler
5013 * @adapter: the adapter
5015 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5016 * The designation 'slow' is because it involves register reads, while
5017 * data interrupts typically don't involve any MMIOs.
5019 int t4_slow_intr_handler(struct adapter *adapter)
5021 /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5022 * set when the corresponding PL_INT_ENABLE bit isn't set. It's
5023 * easiest just to mask that case here.
5025 u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5026 u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5027 u32 cause = raw_cause & enable;
5029 if (!(cause & GLBL_INTR_MASK))
5032 cim_intr_handler(adapter);
5034 mps_intr_handler(adapter);
5036 ncsi_intr_handler(adapter);
5038 pl_intr_handler(adapter);
5040 smb_intr_handler(adapter);
5041 if (cause & XGMAC0_F)
5042 xgmac_intr_handler(adapter, 0);
5043 if (cause & XGMAC1_F)
5044 xgmac_intr_handler(adapter, 1);
5045 if (cause & XGMAC_KR0_F)
5046 xgmac_intr_handler(adapter, 2);
5047 if (cause & XGMAC_KR1_F)
5048 xgmac_intr_handler(adapter, 3);
5050 pcie_intr_handler(adapter);
5052 mem_intr_handler(adapter, MEM_MC);
5053 if (is_t5(adapter->params.chip) && (cause & MC1_F))
5054 mem_intr_handler(adapter, MEM_MC1);
5056 mem_intr_handler(adapter, MEM_EDC0);
5058 mem_intr_handler(adapter, MEM_EDC1);
5060 le_intr_handler(adapter);
5062 tp_intr_handler(adapter);
5064 ma_intr_handler(adapter);
5065 if (cause & PM_TX_F)
5066 pmtx_intr_handler(adapter);
5067 if (cause & PM_RX_F)
5068 pmrx_intr_handler(adapter);
5069 if (cause & ULP_RX_F)
5070 ulprx_intr_handler(adapter);
5071 if (cause & CPL_SWITCH_F)
5072 cplsw_intr_handler(adapter);
5074 sge_intr_handler(adapter);
5075 if (cause & ULP_TX_F)
5076 ulptx_intr_handler(adapter);
5078 /* Clear the interrupts just processed for which we are the master. */
5079 t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
5080 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5085 * t4_intr_enable - enable interrupts
5086 * @adapter: the adapter whose interrupts should be enabled
5088 * Enable PF-specific interrupts for the calling function and the top-level
5089 * interrupt concentrator for global interrupts. Interrupts are already
5090 * enabled at each module, here we just enable the roots of the interrupt
5093 * Note: this function should be called only when the driver manages
5094 * non PF-specific interrupts from the various HW modules. Only one PCI
5095 * function at a time should be doing this.
5097 void t4_intr_enable(struct adapter *adapter)
5100 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5101 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5102 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5104 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5105 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5106 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5107 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5108 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5109 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5110 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5111 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5112 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5113 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5114 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5118 * t4_intr_disable - disable interrupts
5119 * @adapter: the adapter whose interrupts should be disabled
5121 * Disable interrupts. We only disable the top-level interrupt
5122 * concentrators. The caller must be a PCI function managing global
5125 void t4_intr_disable(struct adapter *adapter)
5129 if (pci_channel_offline(adapter->pdev))
5132 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5133 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5134 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5136 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5137 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5140 unsigned int t4_chip_rss_size(struct adapter *adap)
5142 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5143 return RSS_NENTRIES;
5145 return T6_RSS_NENTRIES;
5149 * t4_config_rss_range - configure a portion of the RSS mapping table
5150 * @adapter: the adapter
5151 * @mbox: mbox to use for the FW command
5152 * @viid: virtual interface whose RSS subtable is to be written
5153 * @start: start entry in the table to write
5154 * @n: how many table entries to write
5155 * @rspq: values for the response queue lookup table
5156 * @nrspq: number of values in @rspq
5158 * Programs the selected part of the VI's RSS mapping table with the
5159 * provided values. If @nrspq < @n the supplied values are used repeatedly
5160 * until the full table range is populated.
5162 * The caller must ensure the values in @rspq are in the range allowed for
5165 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5166 int start, int n, const u16 *rspq, unsigned int nrspq)
5169 const u16 *rsp = rspq;
5170 const u16 *rsp_end = rspq + nrspq;
5171 struct fw_rss_ind_tbl_cmd cmd;
5173 memset(&cmd, 0, sizeof(cmd));
5174 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5175 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5176 FW_RSS_IND_TBL_CMD_VIID_V(viid));
5177 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5179 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5181 int nq = min(n, 32);
5182 __be32 *qp = &cmd.iq0_to_iq2;
5184 cmd.niqid = cpu_to_be16(nq);
5185 cmd.startidx = cpu_to_be16(start);
5193 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5194 if (++rsp >= rsp_end)
5196 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5197 if (++rsp >= rsp_end)
5199 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5200 if (++rsp >= rsp_end)
5203 *qp++ = cpu_to_be32(v);
5207 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5215 * t4_config_glbl_rss - configure the global RSS mode
5216 * @adapter: the adapter
5217 * @mbox: mbox to use for the FW command
5218 * @mode: global RSS mode
5219 * @flags: mode-specific flags
5221 * Sets the global RSS mode.
5223 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5226 struct fw_rss_glb_config_cmd c;
5228 memset(&c, 0, sizeof(c));
5229 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5230 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5231 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5232 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5233 c.u.manual.mode_pkd =
5234 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5235 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5236 c.u.basicvirtual.mode_pkd =
5237 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5238 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5241 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5245 * t4_config_vi_rss - configure per VI RSS settings
5246 * @adapter: the adapter
5247 * @mbox: mbox to use for the FW command
5250 * @defq: id of the default RSS queue for the VI.
5252 * Configures VI-specific RSS properties.
5254 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5255 unsigned int flags, unsigned int defq)
5257 struct fw_rss_vi_config_cmd c;
5259 memset(&c, 0, sizeof(c));
5260 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5261 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5262 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5263 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5264 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5265 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5266 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5269 /* Read an RSS table row */
5270 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5272 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5273 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5278 * t4_read_rss - read the contents of the RSS mapping table
5279 * @adapter: the adapter
5280 * @map: holds the contents of the RSS mapping table
5282 * Reads the contents of the RSS hash->queue mapping table.
5284 int t4_read_rss(struct adapter *adapter, u16 *map)
5286 int i, ret, nentries;
5289 nentries = t4_chip_rss_size(adapter);
5290 for (i = 0; i < nentries / 2; ++i) {
5291 ret = rd_rss_row(adapter, i, &val);
5294 *map++ = LKPTBLQUEUE0_G(val);
5295 *map++ = LKPTBLQUEUE1_G(val);
5300 static unsigned int t4_use_ldst(struct adapter *adap)
5302 return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5306 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5307 * @adap: the adapter
5308 * @cmd: TP fw ldst address space type
5309 * @vals: where the indirect register values are stored/written
5310 * @nregs: how many indirect registers to read/write
5311 * @start_index: index of first indirect register to read/write
5312 * @rw: Read (1) or Write (0)
5313 * @sleep_ok: if true we may sleep while awaiting command completion
5315 * Access TP indirect registers through LDST
5317 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5318 unsigned int nregs, unsigned int start_index,
5319 unsigned int rw, bool sleep_ok)
5323 struct fw_ldst_cmd c;
5325 for (i = 0; i < nregs; i++) {
5326 memset(&c, 0, sizeof(c));
5327 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5329 (rw ? FW_CMD_READ_F :
5331 FW_LDST_CMD_ADDRSPACE_V(cmd));
5332 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5334 c.u.addrval.addr = cpu_to_be32(start_index + i);
5335 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5336 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5342 vals[i] = be32_to_cpu(c.u.addrval.val);
5348 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5349 * @adap: the adapter
5350 * @reg_addr: Address Register
5351 * @reg_data: Data register
5352 * @buff: where the indirect register values are stored/written
5353 * @nregs: how many indirect registers to read/write
5354 * @start_index: index of first indirect register to read/write
5355 * @rw: READ(1) or WRITE(0)
5356 * @sleep_ok: if true we may sleep while awaiting command completion
5358 * Read/Write TP indirect registers through LDST if possible.
5359 * Else, use backdoor access
5361 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5362 u32 *buff, u32 nregs, u32 start_index, int rw,
5370 cmd = FW_LDST_ADDRSPC_TP_PIO;
5372 case TP_TM_PIO_ADDR_A:
5373 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5375 case TP_MIB_INDEX_A:
5376 cmd = FW_LDST_ADDRSPC_TP_MIB;
5379 goto indirect_access;
5382 if (t4_use_ldst(adap))
5383 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5390 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5393 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5399 * t4_tp_pio_read - Read TP PIO registers
5400 * @adap: the adapter
5401 * @buff: where the indirect register values are written
5402 * @nregs: how many indirect registers to read
5403 * @start_index: index of first indirect register to read
5404 * @sleep_ok: if true we may sleep while awaiting command completion
5406 * Read TP PIO Registers
5408 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5409 u32 start_index, bool sleep_ok)
5411 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5412 start_index, 1, sleep_ok);
5416 * t4_tp_pio_write - Write TP PIO registers
5417 * @adap: the adapter
5418 * @buff: where the indirect register values are stored
5419 * @nregs: how many indirect registers to write
5420 * @start_index: index of first indirect register to write
5421 * @sleep_ok: if true we may sleep while awaiting command completion
5423 * Write TP PIO Registers
5425 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5426 u32 start_index, bool sleep_ok)
5428 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5429 start_index, 0, sleep_ok);
5433 * t4_tp_tm_pio_read - Read TP TM PIO registers
5434 * @adap: the adapter
5435 * @buff: where the indirect register values are written
5436 * @nregs: how many indirect registers to read
5437 * @start_index: index of first indirect register to read
5438 * @sleep_ok: if true we may sleep while awaiting command completion
5440 * Read TP TM PIO Registers
5442 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5443 u32 start_index, bool sleep_ok)
5445 t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5446 nregs, start_index, 1, sleep_ok);
5450 * t4_tp_mib_read - Read TP MIB registers
5451 * @adap: the adapter
5452 * @buff: where the indirect register values are written
5453 * @nregs: how many indirect registers to read
5454 * @start_index: index of first indirect register to read
5455 * @sleep_ok: if true we may sleep while awaiting command completion
5457 * Read TP MIB Registers
5459 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5462 t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5463 start_index, 1, sleep_ok);
5467 * t4_read_rss_key - read the global RSS key
5468 * @adap: the adapter
5469 * @key: 10-entry array holding the 320-bit RSS key
5470 * @sleep_ok: if true we may sleep while awaiting command completion
5472 * Reads the global 320-bit RSS key.
5474 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5476 t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5480 * t4_write_rss_key - program one of the RSS keys
5481 * @adap: the adapter
5482 * @key: 10-entry array holding the 320-bit RSS key
5483 * @idx: which RSS key to write
5484 * @sleep_ok: if true we may sleep while awaiting command completion
5486 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5487 * 0..15 the corresponding entry in the RSS key table is written,
5488 * otherwise the global RSS key is written.
5490 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5493 u8 rss_key_addr_cnt = 16;
5494 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5496 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5497 * allows access to key addresses 16-63 by using KeyWrAddrX
5498 * as index[5:4](upper 2) into key table
5500 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5501 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5502 rss_key_addr_cnt = 32;
5504 t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5506 if (idx >= 0 && idx < rss_key_addr_cnt) {
5507 if (rss_key_addr_cnt > 16)
5508 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5509 KEYWRADDRX_V(idx >> 4) |
5510 T6_VFWRADDR_V(idx) | KEYWREN_F);
5512 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5513 KEYWRADDR_V(idx) | KEYWREN_F);
5518 * t4_read_rss_pf_config - read PF RSS Configuration Table
5519 * @adapter: the adapter
5520 * @index: the entry in the PF RSS table to read
5521 * @valp: where to store the returned value
5522 * @sleep_ok: if true we may sleep while awaiting command completion
5524 * Reads the PF RSS Configuration Table at the specified index and returns
5525 * the value found there.
5527 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5528 u32 *valp, bool sleep_ok)
5530 t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5534 * t4_read_rss_vf_config - read VF RSS Configuration Table
5535 * @adapter: the adapter
5536 * @index: the entry in the VF RSS table to read
5537 * @vfl: where to store the returned VFL
5538 * @vfh: where to store the returned VFH
5539 * @sleep_ok: if true we may sleep while awaiting command completion
5541 * Reads the VF RSS Configuration Table at the specified index and returns
5542 * the (VFL, VFH) values found there.
5544 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5545 u32 *vfl, u32 *vfh, bool sleep_ok)
5547 u32 vrt, mask, data;
5549 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5550 mask = VFWRADDR_V(VFWRADDR_M);
5551 data = VFWRADDR_V(index);
5553 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
5554 data = T6_VFWRADDR_V(index);
5557 /* Request that the index'th VF Table values be read into VFL/VFH.
5559 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5560 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5561 vrt |= data | VFRDEN_F;
5562 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5564 /* Grab the VFL/VFH values ...
5566 t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5567 t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5571 * t4_read_rss_pf_map - read PF RSS Map
5572 * @adapter: the adapter
5573 * @sleep_ok: if true we may sleep while awaiting command completion
5575 * Reads the PF RSS Map register and returns its value.
5577 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5581 t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5586 * t4_read_rss_pf_mask - read PF RSS Mask
5587 * @adapter: the adapter
5588 * @sleep_ok: if true we may sleep while awaiting command completion
5590 * Reads the PF RSS Mask register and returns its value.
5592 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5596 t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5601 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5602 * @adap: the adapter
5603 * @v4: holds the TCP/IP counter values
5604 * @v6: holds the TCP/IPv6 counter values
5605 * @sleep_ok: if true we may sleep while awaiting command completion
5607 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5608 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5610 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5611 struct tp_tcp_stats *v6, bool sleep_ok)
5613 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5615 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5616 #define STAT(x) val[STAT_IDX(x)]
5617 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5620 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5621 TP_MIB_TCP_OUT_RST_A, sleep_ok);
5622 v4->tcp_out_rsts = STAT(OUT_RST);
5623 v4->tcp_in_segs = STAT64(IN_SEG);
5624 v4->tcp_out_segs = STAT64(OUT_SEG);
5625 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5628 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5629 TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5630 v6->tcp_out_rsts = STAT(OUT_RST);
5631 v6->tcp_in_segs = STAT64(IN_SEG);
5632 v6->tcp_out_segs = STAT64(OUT_SEG);
5633 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5641 * t4_tp_get_err_stats - read TP's error MIB counters
5642 * @adap: the adapter
5643 * @st: holds the counter values
5644 * @sleep_ok: if true we may sleep while awaiting command completion
5646 * Returns the values of TP's error counters.
5648 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5651 int nchan = adap->params.arch.nchan;
5653 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5655 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5657 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5659 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5660 TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5661 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5662 TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5663 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5665 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5666 TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5667 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5668 TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5669 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5674 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5675 * @adap: the adapter
5676 * @st: holds the counter values
5677 * @sleep_ok: if true we may sleep while awaiting command completion
5679 * Returns the values of TP's CPL counters.
5681 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5684 int nchan = adap->params.arch.nchan;
5686 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5688 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5692 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5693 * @adap: the adapter
5694 * @st: holds the counter values
5695 * @sleep_ok: if true we may sleep while awaiting command completion
5697 * Returns the values of TP's RDMA counters.
5699 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5702 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5707 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5708 * @adap: the adapter
5709 * @idx: the port index
5710 * @st: holds the counter values
5711 * @sleep_ok: if true we may sleep while awaiting command completion
5713 * Returns the values of TP's FCoE counters for the selected port.
5715 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5716 struct tp_fcoe_stats *st, bool sleep_ok)
5720 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5723 t4_tp_mib_read(adap, &st->frames_drop, 1,
5724 TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5726 t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5729 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5733 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5734 * @adap: the adapter
5735 * @st: holds the counter values
5736 * @sleep_ok: if true we may sleep while awaiting command completion
5738 * Returns the values of TP's counters for non-TCP directly-placed packets.
5740 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5745 t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5746 st->frames = val[0];
5748 st->octets = ((u64)val[2] << 32) | val[3];
5752 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5753 * @adap: the adapter
5754 * @mtus: where to store the MTU values
5755 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5757 * Reads the HW path MTU table.
5759 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5764 for (i = 0; i < NMTUS; ++i) {
5765 t4_write_reg(adap, TP_MTU_TABLE_A,
5766 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5767 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5768 mtus[i] = MTUVALUE_G(v);
5770 mtu_log[i] = MTUWIDTH_G(v);
5775 * t4_read_cong_tbl - reads the congestion control table
5776 * @adap: the adapter
5777 * @incr: where to store the alpha values
5779 * Reads the additive increments programmed into the HW congestion
5782 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5784 unsigned int mtu, w;
5786 for (mtu = 0; mtu < NMTUS; ++mtu)
5787 for (w = 0; w < NCCTRL_WIN; ++w) {
5788 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5789 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5790 incr[mtu][w] = (u16)t4_read_reg(adap,
5791 TP_CCTRL_TABLE_A) & 0x1fff;
5796 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5797 * @adap: the adapter
5798 * @addr: the indirect TP register address
5799 * @mask: specifies the field within the register to modify
5800 * @val: new value for the field
5802 * Sets a field of an indirect TP register to the given value.
5804 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5805 unsigned int mask, unsigned int val)
5807 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5808 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5809 t4_write_reg(adap, TP_PIO_DATA_A, val);
5813 * init_cong_ctrl - initialize congestion control parameters
5814 * @a: the alpha values for congestion control
5815 * @b: the beta values for congestion control
5817 * Initialize the congestion control parameters.
5819 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5821 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5846 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5849 b[13] = b[14] = b[15] = b[16] = 3;
5850 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5851 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5856 /* The minimum additive increment value for the congestion control table */
5857 #define CC_MIN_INCR 2U
5860 * t4_load_mtus - write the MTU and congestion control HW tables
5861 * @adap: the adapter
5862 * @mtus: the values for the MTU table
5863 * @alpha: the values for the congestion control alpha parameter
5864 * @beta: the values for the congestion control beta parameter
5866 * Write the HW MTU table with the supplied MTUs and the high-speed
5867 * congestion control table with the supplied alpha, beta, and MTUs.
5868 * We write the two tables together because the additive increments
5869 * depend on the MTUs.
5871 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5872 const unsigned short *alpha, const unsigned short *beta)
5874 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5875 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5876 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5877 28672, 40960, 57344, 81920, 114688, 163840, 229376
5882 for (i = 0; i < NMTUS; ++i) {
5883 unsigned int mtu = mtus[i];
5884 unsigned int log2 = fls(mtu);
5886 if (!(mtu & ((1 << log2) >> 2))) /* round */
5888 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5889 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5891 for (w = 0; w < NCCTRL_WIN; ++w) {
5894 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5897 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5898 (w << 16) | (beta[w] << 13) | inc);
5903 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5904 * clocks. The formula is
5906 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5908 * which is equivalent to
5910 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5912 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5914 u64 v = bytes256 * adap->params.vpd.cclk;
5916 return v * 62 + v / 2;
5920 * t4_get_chan_txrate - get the current per channel Tx rates
5921 * @adap: the adapter
5922 * @nic_rate: rates for NIC traffic
5923 * @ofld_rate: rates for offloaded traffic
5925 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5928 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5932 v = t4_read_reg(adap, TP_TX_TRATE_A);
5933 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5934 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5935 if (adap->params.arch.nchan == NCHAN) {
5936 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5937 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5940 v = t4_read_reg(adap, TP_TX_ORATE_A);
5941 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5942 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5943 if (adap->params.arch.nchan == NCHAN) {
5944 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5945 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5950 * t4_set_trace_filter - configure one of the tracing filters
5951 * @adap: the adapter
5952 * @tp: the desired trace filter parameters
5953 * @idx: which filter to configure
5954 * @enable: whether to enable or disable the filter
5956 * Configures one of the tracing filters available in HW. If @enable is
5957 * %0 @tp is not examined and may be %NULL. The user is responsible to
5958 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5960 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5961 int idx, int enable)
5963 int i, ofst = idx * 4;
5964 u32 data_reg, mask_reg, cfg;
5967 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5971 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5972 if (cfg & TRCMULTIFILTER_F) {
5973 /* If multiple tracers are enabled, then maximum
5974 * capture size is 2.5KB (FIFO size of a single channel)
5975 * minus 2 flits for CPL_TRACE_PKT header.
5977 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5980 /* If multiple tracers are disabled, to avoid deadlocks
5981 * maximum packet capture size of 9600 bytes is recommended.
5982 * Also in this mode, only trace0 can be enabled and running.
5984 if (tp->snap_len > 9600 || idx)
5988 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5989 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5990 tp->min_len > TFMINPKTSIZE_M)
5993 /* stop the tracer we'll be changing */
5994 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5996 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5997 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5998 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
6000 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6001 t4_write_reg(adap, data_reg, tp->data[i]);
6002 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6004 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
6005 TFCAPTUREMAX_V(tp->snap_len) |
6006 TFMINPKTSIZE_V(tp->min_len));
6007 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
6008 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
6009 (is_t4(adap->params.chip) ?
6010 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
6011 T5_TFPORT_V(tp->port) | T5_TFEN_F |
6012 T5_TFINVERTMATCH_V(tp->invert)));
6018 * t4_get_trace_filter - query one of the tracing filters
6019 * @adap: the adapter
6020 * @tp: the current trace filter parameters
6021 * @idx: which trace filter to query
6022 * @enabled: non-zero if the filter is enabled
6024 * Returns the current settings of one of the HW tracing filters.
6026 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6030 int i, ofst = idx * 4;
6031 u32 data_reg, mask_reg;
6033 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6034 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6036 if (is_t4(adap->params.chip)) {
6037 *enabled = !!(ctla & TFEN_F);
6038 tp->port = TFPORT_G(ctla);
6039 tp->invert = !!(ctla & TFINVERTMATCH_F);
6041 *enabled = !!(ctla & T5_TFEN_F);
6042 tp->port = T5_TFPORT_G(ctla);
6043 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
6045 tp->snap_len = TFCAPTUREMAX_G(ctlb);
6046 tp->min_len = TFMINPKTSIZE_G(ctlb);
6047 tp->skip_ofst = TFOFFSET_G(ctla);
6048 tp->skip_len = TFLENGTH_G(ctla);
6050 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
6051 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
6052 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
6054 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6055 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6056 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6061 * t4_pmtx_get_stats - returns the HW stats from PMTX
6062 * @adap: the adapter
6063 * @cnt: where to store the count statistics
6064 * @cycles: where to store the cycle statistics
6066 * Returns performance statistics from PMTX.
6068 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6073 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6074 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6075 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6076 if (is_t4(adap->params.chip)) {
6077 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6079 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6080 PM_TX_DBG_DATA_A, data, 2,
6081 PM_TX_DBG_STAT_MSB_A);
6082 cycles[i] = (((u64)data[0] << 32) | data[1]);
6088 * t4_pmrx_get_stats - returns the HW stats from PMRX
6089 * @adap: the adapter
6090 * @cnt: where to store the count statistics
6091 * @cycles: where to store the cycle statistics
6093 * Returns performance statistics from PMRX.
6095 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6100 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6101 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6102 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6103 if (is_t4(adap->params.chip)) {
6104 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6106 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6107 PM_RX_DBG_DATA_A, data, 2,
6108 PM_RX_DBG_STAT_MSB_A);
6109 cycles[i] = (((u64)data[0] << 32) | data[1]);
6115 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6116 * @adapter: the adapter
6117 * @pidx: the port index
6119 * Computes and returns a bitmap indicating which MPS buffer groups are
6120 * associated with the given Port. Bit i is set if buffer group i is
6123 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6126 unsigned int chip_version, nports;
6128 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6129 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6131 switch (chip_version) {
6136 case 2: return 3 << (2 * pidx);
6137 case 4: return 1 << pidx;
6143 case 2: return 1 << (2 * pidx);
6148 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6149 chip_version, nports);
6155 * t4_get_mps_bg_map - return the buffer groups associated with a port
6156 * @adapter: the adapter
6157 * @pidx: the port index
6159 * Returns a bitmap indicating which MPS buffer groups are associated
6160 * with the given Port. Bit i is set if buffer group i is used by the
6163 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6166 unsigned int nports;
6168 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6169 if (pidx >= nports) {
6170 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6175 /* If we've already retrieved/computed this, just return the result.
6177 mps_bg_map = adapter->params.mps_bg_map;
6178 if (mps_bg_map[pidx])
6179 return mps_bg_map[pidx];
6181 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6182 * If we're talking to such Firmware, let it tell us. If the new
6183 * API isn't supported, revert back to old hardcoded way. The value
6184 * obtained from Firmware is encoded in below format:
6186 * val = (( MPSBGMAP[Port 3] << 24 ) |
6187 * ( MPSBGMAP[Port 2] << 16 ) |
6188 * ( MPSBGMAP[Port 1] << 8 ) |
6189 * ( MPSBGMAP[Port 0] << 0 ))
6191 if (adapter->flags & CXGB4_FW_OK) {
6195 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6196 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6197 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6198 0, 1, ¶m, &val);
6202 /* Store the BG Map for all of the Ports in order to
6203 * avoid more calls to the Firmware in the future.
6205 for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6206 mps_bg_map[p] = val & 0xff;
6208 return mps_bg_map[pidx];
6212 /* Either we're not talking to the Firmware or we're dealing with
6213 * older Firmware which doesn't support the new API to get the MPS
6214 * Buffer Group Map. Fall back to computing it ourselves.
6216 mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6217 return mps_bg_map[pidx];
6221 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6222 * @adapter: the adapter
6223 * @pidx: the port index
6225 static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
6227 unsigned int nports;
6231 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6232 if (pidx >= nports) {
6233 CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
6238 /* FW version >= 1.16.44.0 can determine E2C channel map using
6239 * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6241 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6242 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
6243 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6244 0, 1, ¶m, &val);
6246 return (val >> (8 * pidx)) & 0xff;
6252 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6253 * @adap: the adapter
6254 * @pidx: the port index
6256 * Returns a bitmap indicating which TP Ingress Channels are associated
6257 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6260 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6262 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6263 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6265 if (pidx >= nports) {
6266 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6271 switch (chip_version) {
6274 /* Note that this happens to be the same values as the MPS
6275 * Buffer Group Map for these Chips. But we replicate the code
6276 * here because they're really separate concepts.
6280 case 2: return 3 << (2 * pidx);
6281 case 4: return 1 << pidx;
6288 case 2: return 1 << pidx;
6293 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6294 chip_version, nports);
6299 * t4_get_port_type_description - return Port Type string description
6300 * @port_type: firmware Port Type enumeration
6302 const char *t4_get_port_type_description(enum fw_port_type port_type)
6304 static const char *const port_type_description[] = {
6330 if (port_type < ARRAY_SIZE(port_type_description))
6331 return port_type_description[port_type];
6336 * t4_get_port_stats_offset - collect port stats relative to a previous
6338 * @adap: The adapter
6340 * @stats: Current stats to fill
6341 * @offset: Previous stats snapshot
6343 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6344 struct port_stats *stats,
6345 struct port_stats *offset)
6350 t4_get_port_stats(adap, idx, stats);
6351 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6352 i < (sizeof(struct port_stats) / sizeof(u64));
6358 * t4_get_port_stats - collect port statistics
6359 * @adap: the adapter
6360 * @idx: the port index
6361 * @p: the stats structure to fill
6363 * Collect statistics related to the given port from HW.
6365 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6367 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6368 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6370 #define GET_STAT(name) \
6371 t4_read_reg64(adap, \
6372 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6373 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6374 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6376 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6377 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6378 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6379 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6380 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6381 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6382 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6383 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6384 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6385 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6386 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6387 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6388 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6389 p->tx_drop = GET_STAT(TX_PORT_DROP);
6390 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6391 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6392 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6393 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6394 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6395 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6396 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6397 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6398 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6400 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6401 if (stat_ctl & COUNTPAUSESTATTX_F)
6402 p->tx_frames_64 -= p->tx_pause;
6403 if (stat_ctl & COUNTPAUSEMCTX_F)
6404 p->tx_mcast_frames -= p->tx_pause;
6406 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6407 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6408 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6409 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6410 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6411 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6412 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6413 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6414 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6415 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6416 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6417 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6418 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6419 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6420 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6421 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6422 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6423 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6424 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6425 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6426 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6427 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6428 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6429 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6430 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6431 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6432 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6434 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6435 if (stat_ctl & COUNTPAUSESTATRX_F)
6436 p->rx_frames_64 -= p->rx_pause;
6437 if (stat_ctl & COUNTPAUSEMCRX_F)
6438 p->rx_mcast_frames -= p->rx_pause;
6441 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6442 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6443 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6444 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6445 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6446 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6447 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6448 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6455 * t4_get_lb_stats - collect loopback port statistics
6456 * @adap: the adapter
6457 * @idx: the loopback port index
6458 * @p: the stats structure to fill
6460 * Return HW statistics for the given loopback port.
6462 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6464 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6466 #define GET_STAT(name) \
6467 t4_read_reg64(adap, \
6468 (is_t4(adap->params.chip) ? \
6469 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6470 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6471 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6473 p->octets = GET_STAT(BYTES);
6474 p->frames = GET_STAT(FRAMES);
6475 p->bcast_frames = GET_STAT(BCAST);
6476 p->mcast_frames = GET_STAT(MCAST);
6477 p->ucast_frames = GET_STAT(UCAST);
6478 p->error_frames = GET_STAT(ERROR);
6480 p->frames_64 = GET_STAT(64B);
6481 p->frames_65_127 = GET_STAT(65B_127B);
6482 p->frames_128_255 = GET_STAT(128B_255B);
6483 p->frames_256_511 = GET_STAT(256B_511B);
6484 p->frames_512_1023 = GET_STAT(512B_1023B);
6485 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6486 p->frames_1519_max = GET_STAT(1519B_MAX);
6487 p->drop = GET_STAT(DROP_FRAMES);
6489 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6490 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6491 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6492 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6493 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6494 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6495 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6496 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6502 /* t4_mk_filtdelwr - create a delete filter WR
6503 * @ftid: the filter ID
6504 * @wr: the filter work request to populate
6505 * @qid: ingress queue to receive the delete notification
6507 * Creates a filter work request to delete the supplied filter. If @qid is
6508 * negative the delete notification is suppressed.
6510 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6512 memset(wr, 0, sizeof(*wr));
6513 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6514 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6515 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6516 FW_FILTER_WR_NOREPLY_V(qid < 0));
6517 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6519 wr->rx_chan_rx_rpl_iq =
6520 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6523 #define INIT_CMD(var, cmd, rd_wr) do { \
6524 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6525 FW_CMD_REQUEST_F | \
6526 FW_CMD_##rd_wr##_F); \
6527 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6530 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6534 struct fw_ldst_cmd c;
6536 memset(&c, 0, sizeof(c));
6537 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6538 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6542 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6543 c.u.addrval.addr = cpu_to_be32(addr);
6544 c.u.addrval.val = cpu_to_be32(val);
6546 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6550 * t4_mdio_rd - read a PHY register through MDIO
6551 * @adap: the adapter
6552 * @mbox: mailbox to use for the FW command
6553 * @phy_addr: the PHY address
6554 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6555 * @reg: the register to read
6556 * @valp: where to store the value
6558 * Issues a FW command through the given mailbox to read a PHY register.
6560 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6561 unsigned int mmd, unsigned int reg, u16 *valp)
6565 struct fw_ldst_cmd c;
6567 memset(&c, 0, sizeof(c));
6568 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6569 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6570 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6572 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6573 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6574 FW_LDST_CMD_MMD_V(mmd));
6575 c.u.mdio.raddr = cpu_to_be16(reg);
6577 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6579 *valp = be16_to_cpu(c.u.mdio.rval);
6584 * t4_mdio_wr - write a PHY register through MDIO
6585 * @adap: the adapter
6586 * @mbox: mailbox to use for the FW command
6587 * @phy_addr: the PHY address
6588 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6589 * @reg: the register to write
6590 * @val: value to write
6592 * Issues a FW command through the given mailbox to write a PHY register.
6594 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6595 unsigned int mmd, unsigned int reg, u16 val)
6598 struct fw_ldst_cmd c;
6600 memset(&c, 0, sizeof(c));
6601 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6602 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6603 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6605 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6606 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6607 FW_LDST_CMD_MMD_V(mmd));
6608 c.u.mdio.raddr = cpu_to_be16(reg);
6609 c.u.mdio.rval = cpu_to_be16(val);
6611 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6615 * t4_sge_decode_idma_state - decode the idma state
6616 * @adapter: the adapter
6617 * @state: the state idma is stuck in
6619 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6621 static const char * const t4_decode[] = {
6623 "IDMA_PUSH_MORE_CPL_FIFO",
6624 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6626 "IDMA_PHYSADDR_SEND_PCIEHDR",
6627 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6628 "IDMA_PHYSADDR_SEND_PAYLOAD",
6629 "IDMA_SEND_FIFO_TO_IMSG",
6630 "IDMA_FL_REQ_DATA_FL_PREP",
6631 "IDMA_FL_REQ_DATA_FL",
6633 "IDMA_FL_H_REQ_HEADER_FL",
6634 "IDMA_FL_H_SEND_PCIEHDR",
6635 "IDMA_FL_H_PUSH_CPL_FIFO",
6636 "IDMA_FL_H_SEND_CPL",
6637 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6638 "IDMA_FL_H_SEND_IP_HDR",
6639 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6640 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6641 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6642 "IDMA_FL_D_SEND_PCIEHDR",
6643 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6644 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6645 "IDMA_FL_SEND_PCIEHDR",
6646 "IDMA_FL_PUSH_CPL_FIFO",
6648 "IDMA_FL_SEND_PAYLOAD_FIRST",
6649 "IDMA_FL_SEND_PAYLOAD",
6650 "IDMA_FL_REQ_NEXT_DATA_FL",
6651 "IDMA_FL_SEND_NEXT_PCIEHDR",
6652 "IDMA_FL_SEND_PADDING",
6653 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6654 "IDMA_FL_SEND_FIFO_TO_IMSG",
6655 "IDMA_FL_REQ_DATAFL_DONE",
6656 "IDMA_FL_REQ_HEADERFL_DONE",
6658 static const char * const t5_decode[] = {
6661 "IDMA_PUSH_MORE_CPL_FIFO",
6662 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6663 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6664 "IDMA_PHYSADDR_SEND_PCIEHDR",
6665 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6666 "IDMA_PHYSADDR_SEND_PAYLOAD",
6667 "IDMA_SEND_FIFO_TO_IMSG",
6668 "IDMA_FL_REQ_DATA_FL",
6670 "IDMA_FL_DROP_SEND_INC",
6671 "IDMA_FL_H_REQ_HEADER_FL",
6672 "IDMA_FL_H_SEND_PCIEHDR",
6673 "IDMA_FL_H_PUSH_CPL_FIFO",
6674 "IDMA_FL_H_SEND_CPL",
6675 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6676 "IDMA_FL_H_SEND_IP_HDR",
6677 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6678 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6679 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6680 "IDMA_FL_D_SEND_PCIEHDR",
6681 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6682 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6683 "IDMA_FL_SEND_PCIEHDR",
6684 "IDMA_FL_PUSH_CPL_FIFO",
6686 "IDMA_FL_SEND_PAYLOAD_FIRST",
6687 "IDMA_FL_SEND_PAYLOAD",
6688 "IDMA_FL_REQ_NEXT_DATA_FL",
6689 "IDMA_FL_SEND_NEXT_PCIEHDR",
6690 "IDMA_FL_SEND_PADDING",
6691 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6693 static const char * const t6_decode[] = {
6695 "IDMA_PUSH_MORE_CPL_FIFO",
6696 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6697 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6698 "IDMA_PHYSADDR_SEND_PCIEHDR",
6699 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6700 "IDMA_PHYSADDR_SEND_PAYLOAD",
6701 "IDMA_FL_REQ_DATA_FL",
6703 "IDMA_FL_DROP_SEND_INC",
6704 "IDMA_FL_H_REQ_HEADER_FL",
6705 "IDMA_FL_H_SEND_PCIEHDR",
6706 "IDMA_FL_H_PUSH_CPL_FIFO",
6707 "IDMA_FL_H_SEND_CPL",
6708 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6709 "IDMA_FL_H_SEND_IP_HDR",
6710 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6711 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6712 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6713 "IDMA_FL_D_SEND_PCIEHDR",
6714 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6715 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6716 "IDMA_FL_SEND_PCIEHDR",
6717 "IDMA_FL_PUSH_CPL_FIFO",
6719 "IDMA_FL_SEND_PAYLOAD_FIRST",
6720 "IDMA_FL_SEND_PAYLOAD",
6721 "IDMA_FL_REQ_NEXT_DATA_FL",
6722 "IDMA_FL_SEND_NEXT_PCIEHDR",
6723 "IDMA_FL_SEND_PADDING",
6724 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6726 static const u32 sge_regs[] = {
6727 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6728 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6729 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6731 const char **sge_idma_decode;
6732 int sge_idma_decode_nstates;
6734 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6736 /* Select the right set of decode strings to dump depending on the
6737 * adapter chip type.
6739 switch (chip_version) {
6741 sge_idma_decode = (const char **)t4_decode;
6742 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6746 sge_idma_decode = (const char **)t5_decode;
6747 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6751 sge_idma_decode = (const char **)t6_decode;
6752 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6756 dev_err(adapter->pdev_dev,
6757 "Unsupported chip version %d\n", chip_version);
6761 if (is_t4(adapter->params.chip)) {
6762 sge_idma_decode = (const char **)t4_decode;
6763 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6765 sge_idma_decode = (const char **)t5_decode;
6766 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6769 if (state < sge_idma_decode_nstates)
6770 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6772 CH_WARN(adapter, "idma state %d unknown\n", state);
6774 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6775 CH_WARN(adapter, "SGE register %#x value %#x\n",
6776 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6780 * t4_sge_ctxt_flush - flush the SGE context cache
6781 * @adap: the adapter
6782 * @mbox: mailbox to use for the FW command
6783 * @ctxt_type: Egress or Ingress
6785 * Issues a FW command through the given mailbox to flush the
6786 * SGE context cache.
6788 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6792 struct fw_ldst_cmd c;
6794 memset(&c, 0, sizeof(c));
6795 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6796 FW_LDST_ADDRSPC_SGE_EGRC :
6797 FW_LDST_ADDRSPC_SGE_INGC);
6798 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6799 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6801 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6802 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6804 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6809 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6810 * @adap: the adapter
6811 * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6812 * @dbqtimers: SGE Doorbell Queue Timer table
6814 * Reads the SGE Doorbell Queue Timer values into the provided table.
6815 * Returns 0 on success (Firmware and Hardware support this feature),
6816 * an error on failure.
6818 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6821 int ret, dbqtimerix;
6825 while (dbqtimerix < ndbqtimers) {
6827 u32 params[7], vals[7];
6829 nparams = ndbqtimers - dbqtimerix;
6830 if (nparams > ARRAY_SIZE(params))
6831 nparams = ARRAY_SIZE(params);
6833 for (param = 0; param < nparams; param++)
6835 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6836 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
6837 FW_PARAMS_PARAM_Y_V(dbqtimerix + param));
6838 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6839 nparams, params, vals);
6843 for (param = 0; param < nparams; param++)
6844 dbqtimers[dbqtimerix++] = vals[param];
6850 * t4_fw_hello - establish communication with FW
6851 * @adap: the adapter
6852 * @mbox: mailbox to use for the FW command
6853 * @evt_mbox: mailbox to receive async FW events
6854 * @master: specifies the caller's willingness to be the device master
6855 * @state: returns the current device state (if non-NULL)
6857 * Issues a command to establish communication with FW. Returns either
6858 * an error (negative integer) or the mailbox of the Master PF.
6860 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6861 enum dev_master master, enum dev_state *state)
6864 struct fw_hello_cmd c;
6866 unsigned int master_mbox;
6867 int retries = FW_CMD_HELLO_RETRIES;
6870 memset(&c, 0, sizeof(c));
6871 INIT_CMD(c, HELLO, WRITE);
6872 c.err_to_clearinit = cpu_to_be32(
6873 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6874 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6875 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6876 mbox : FW_HELLO_CMD_MBMASTER_M) |
6877 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6878 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6879 FW_HELLO_CMD_CLEARINIT_F);
6882 * Issue the HELLO command to the firmware. If it's not successful
6883 * but indicates that we got a "busy" or "timeout" condition, retry
6884 * the HELLO until we exhaust our retry limit. If we do exceed our
6885 * retry limit, check to see if the firmware left us any error
6886 * information and report that if so.
6888 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6890 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6892 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6893 t4_report_fw_error(adap);
6897 v = be32_to_cpu(c.err_to_clearinit);
6898 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6900 if (v & FW_HELLO_CMD_ERR_F)
6901 *state = DEV_STATE_ERR;
6902 else if (v & FW_HELLO_CMD_INIT_F)
6903 *state = DEV_STATE_INIT;
6905 *state = DEV_STATE_UNINIT;
6909 * If we're not the Master PF then we need to wait around for the
6910 * Master PF Driver to finish setting up the adapter.
6912 * Note that we also do this wait if we're a non-Master-capable PF and
6913 * there is no current Master PF; a Master PF may show up momentarily
6914 * and we wouldn't want to fail pointlessly. (This can happen when an
6915 * OS loads lots of different drivers rapidly at the same time). In
6916 * this case, the Master PF returned by the firmware will be
6917 * PCIE_FW_MASTER_M so the test below will work ...
6919 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6920 master_mbox != mbox) {
6921 int waiting = FW_CMD_HELLO_TIMEOUT;
6924 * Wait for the firmware to either indicate an error or
6925 * initialized state. If we see either of these we bail out
6926 * and report the issue to the caller. If we exhaust the
6927 * "hello timeout" and we haven't exhausted our retries, try
6928 * again. Otherwise bail with a timeout error.
6937 * If neither Error nor Initialized are indicated
6938 * by the firmware keep waiting till we exhaust our
6939 * timeout ... and then retry if we haven't exhausted
6942 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6943 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6954 * We either have an Error or Initialized condition
6955 * report errors preferentially.
6958 if (pcie_fw & PCIE_FW_ERR_F)
6959 *state = DEV_STATE_ERR;
6960 else if (pcie_fw & PCIE_FW_INIT_F)
6961 *state = DEV_STATE_INIT;
6965 * If we arrived before a Master PF was selected and
6966 * there's not a valid Master PF, grab its identity
6969 if (master_mbox == PCIE_FW_MASTER_M &&
6970 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6971 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6980 * t4_fw_bye - end communication with FW
6981 * @adap: the adapter
6982 * @mbox: mailbox to use for the FW command
6984 * Issues a command to terminate communication with FW.
6986 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6988 struct fw_bye_cmd c;
6990 memset(&c, 0, sizeof(c));
6991 INIT_CMD(c, BYE, WRITE);
6992 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6996 * t4_init_cmd - ask FW to initialize the device
6997 * @adap: the adapter
6998 * @mbox: mailbox to use for the FW command
7000 * Issues a command to FW to partially initialize the device. This
7001 * performs initialization that generally doesn't depend on user input.
7003 int t4_early_init(struct adapter *adap, unsigned int mbox)
7005 struct fw_initialize_cmd c;
7007 memset(&c, 0, sizeof(c));
7008 INIT_CMD(c, INITIALIZE, WRITE);
7009 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7013 * t4_fw_reset - issue a reset to FW
7014 * @adap: the adapter
7015 * @mbox: mailbox to use for the FW command
7016 * @reset: specifies the type of reset to perform
7018 * Issues a reset command of the specified type to FW.
7020 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7022 struct fw_reset_cmd c;
7024 memset(&c, 0, sizeof(c));
7025 INIT_CMD(c, RESET, WRITE);
7026 c.val = cpu_to_be32(reset);
7027 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7031 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7032 * @adap: the adapter
7033 * @mbox: mailbox to use for the FW RESET command (if desired)
7034 * @force: force uP into RESET even if FW RESET command fails
7036 * Issues a RESET command to firmware (if desired) with a HALT indication
7037 * and then puts the microprocessor into RESET state. The RESET command
7038 * will only be issued if a legitimate mailbox is provided (mbox <=
7039 * PCIE_FW_MASTER_M).
7041 * This is generally used in order for the host to safely manipulate the
7042 * adapter without fear of conflicting with whatever the firmware might
7043 * be doing. The only way out of this state is to RESTART the firmware
7046 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7051 * If a legitimate mailbox is provided, issue a RESET command
7052 * with a HALT indication.
7054 if (mbox <= PCIE_FW_MASTER_M) {
7055 struct fw_reset_cmd c;
7057 memset(&c, 0, sizeof(c));
7058 INIT_CMD(c, RESET, WRITE);
7059 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
7060 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
7061 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7065 * Normally we won't complete the operation if the firmware RESET
7066 * command fails but if our caller insists we'll go ahead and put the
7067 * uP into RESET. This can be useful if the firmware is hung or even
7068 * missing ... We'll have to take the risk of putting the uP into
7069 * RESET without the cooperation of firmware in that case.
7071 * We also force the firmware's HALT flag to be on in case we bypassed
7072 * the firmware RESET command above or we're dealing with old firmware
7073 * which doesn't have the HALT capability. This will serve as a flag
7074 * for the incoming firmware to know that it's coming out of a HALT
7075 * rather than a RESET ... if it's new enough to understand that ...
7077 if (ret == 0 || force) {
7078 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7079 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7084 * And we always return the result of the firmware RESET command
7085 * even when we force the uP into RESET ...
7091 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7092 * @adap: the adapter
7093 * @mbox: mailbox to use for the FW command
7094 * @reset: if we want to do a RESET to restart things
7096 * Restart firmware previously halted by t4_fw_halt(). On successful
7097 * return the previous PF Master remains as the new PF Master and there
7098 * is no need to issue a new HELLO command, etc.
7100 * We do this in two ways:
7102 * 1. If we're dealing with newer firmware we'll simply want to take
7103 * the chip's microprocessor out of RESET. This will cause the
7104 * firmware to start up from its start vector. And then we'll loop
7105 * until the firmware indicates it's started again (PCIE_FW.HALT
7106 * reset to 0) or we timeout.
7108 * 2. If we're dealing with older firmware then we'll need to RESET
7109 * the chip since older firmware won't recognize the PCIE_FW.HALT
7110 * flag and automatically RESET itself on startup.
7112 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7116 * Since we're directing the RESET instead of the firmware
7117 * doing it automatically, we need to clear the PCIE_FW.HALT
7120 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7123 * If we've been given a valid mailbox, first try to get the
7124 * firmware to do the RESET. If that works, great and we can
7125 * return success. Otherwise, if we haven't been given a
7126 * valid mailbox or the RESET command failed, fall back to
7127 * hitting the chip with a hammer.
7129 if (mbox <= PCIE_FW_MASTER_M) {
7130 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7132 if (t4_fw_reset(adap, mbox,
7133 PIORST_F | PIORSTMODE_F) == 0)
7137 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7142 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7143 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7144 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7155 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7156 * @adap: the adapter
7157 * @mbox: mailbox to use for the FW RESET command (if desired)
7158 * @fw_data: the firmware image to write
7160 * @force: force upgrade even if firmware doesn't cooperate
7162 * Perform all of the steps necessary for upgrading an adapter's
7163 * firmware image. Normally this requires the cooperation of the
7164 * existing firmware in order to halt all existing activities
7165 * but if an invalid mailbox token is passed in we skip that step
7166 * (though we'll still put the adapter microprocessor into RESET in
7169 * On successful return the new firmware will have been loaded and
7170 * the adapter will have been fully RESET losing all previous setup
7171 * state. On unsuccessful return the adapter may be completely hosed ...
7172 * positive errno indicates that the adapter is ~probably~ intact, a
7173 * negative errno indicates that things are looking bad ...
7175 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7176 const u8 *fw_data, unsigned int size, int force)
7178 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7181 if (!t4_fw_matches_chip(adap, fw_hdr))
7184 /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7185 * set wont be sent when we are flashing FW.
7187 adap->flags &= ~CXGB4_FW_OK;
7189 ret = t4_fw_halt(adap, mbox, force);
7190 if (ret < 0 && !force)
7193 ret = t4_load_fw(adap, fw_data, size);
7198 * If there was a Firmware Configuration File stored in FLASH,
7199 * there's a good chance that it won't be compatible with the new
7200 * Firmware. In order to prevent difficult to diagnose adapter
7201 * initialization issues, we clear out the Firmware Configuration File
7202 * portion of the FLASH . The user will need to re-FLASH a new
7203 * Firmware Configuration File which is compatible with the new
7204 * Firmware if that's desired.
7206 (void)t4_load_cfg(adap, NULL, 0);
7209 * Older versions of the firmware don't understand the new
7210 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7211 * restart. So for newly loaded older firmware we'll have to do the
7212 * RESET for it so it starts up on a clean slate. We can tell if
7213 * the newly loaded firmware will handle this right by checking
7214 * its header flags to see if it advertises the capability.
7216 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7217 ret = t4_fw_restart(adap, mbox, reset);
7219 /* Grab potentially new Firmware Device Log parameters so we can see
7220 * how healthy the new Firmware is. It's okay to contact the new
7221 * Firmware for these parameters even though, as far as it's
7222 * concerned, we've never said "HELLO" to it ...
7224 (void)t4_init_devlog_params(adap);
7226 adap->flags |= CXGB4_FW_OK;
7231 * t4_fl_pkt_align - return the fl packet alignment
7232 * @adap: the adapter
7234 * T4 has a single field to specify the packing and padding boundary.
7235 * T5 onwards has separate fields for this and hence the alignment for
7236 * next packet offset is maximum of these two.
7239 int t4_fl_pkt_align(struct adapter *adap)
7241 u32 sge_control, sge_control2;
7242 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7244 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7246 /* T4 uses a single control field to specify both the PCIe Padding and
7247 * Packing Boundary. T5 introduced the ability to specify these
7248 * separately. The actual Ingress Packet Data alignment boundary
7249 * within Packed Buffer Mode is the maximum of these two
7250 * specifications. (Note that it makes no real practical sense to
7251 * have the Padding Boundary be larger than the Packing Boundary but you
7252 * could set the chip up that way and, in fact, legacy T4 code would
7253 * end doing this because it would initialize the Padding Boundary and
7254 * leave the Packing Boundary initialized to 0 (16 bytes).)
7255 * Padding Boundary values in T6 starts from 8B,
7256 * where as it is 32B for T4 and T5.
7258 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7259 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7261 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7263 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7265 fl_align = ingpadboundary;
7266 if (!is_t4(adap->params.chip)) {
7267 /* T5 has a weird interpretation of one of the PCIe Packing
7268 * Boundary values. No idea why ...
7270 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7271 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7272 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7273 ingpackboundary = 16;
7275 ingpackboundary = 1 << (ingpackboundary +
7276 INGPACKBOUNDARY_SHIFT_X);
7278 fl_align = max(ingpadboundary, ingpackboundary);
7284 * t4_fixup_host_params - fix up host-dependent parameters
7285 * @adap: the adapter
7286 * @page_size: the host's Base Page Size
7287 * @cache_line_size: the host's Cache Line Size
7289 * Various registers in T4 contain values which are dependent on the
7290 * host's Base Page and Cache Line Sizes. This function will fix all of
7291 * those registers with the appropriate values as passed in ...
7293 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7294 unsigned int cache_line_size)
7296 unsigned int page_shift = fls(page_size) - 1;
7297 unsigned int sge_hps = page_shift - 10;
7298 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7299 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7300 unsigned int fl_align_log = fls(fl_align) - 1;
7302 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7303 HOSTPAGESIZEPF0_V(sge_hps) |
7304 HOSTPAGESIZEPF1_V(sge_hps) |
7305 HOSTPAGESIZEPF2_V(sge_hps) |
7306 HOSTPAGESIZEPF3_V(sge_hps) |
7307 HOSTPAGESIZEPF4_V(sge_hps) |
7308 HOSTPAGESIZEPF5_V(sge_hps) |
7309 HOSTPAGESIZEPF6_V(sge_hps) |
7310 HOSTPAGESIZEPF7_V(sge_hps));
7312 if (is_t4(adap->params.chip)) {
7313 t4_set_reg_field(adap, SGE_CONTROL_A,
7314 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7315 EGRSTATUSPAGESIZE_F,
7316 INGPADBOUNDARY_V(fl_align_log -
7317 INGPADBOUNDARY_SHIFT_X) |
7318 EGRSTATUSPAGESIZE_V(stat_len != 64));
7320 unsigned int pack_align;
7321 unsigned int ingpad, ingpack;
7323 /* T5 introduced the separation of the Free List Padding and
7324 * Packing Boundaries. Thus, we can select a smaller Padding
7325 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7326 * Bandwidth, and use a Packing Boundary which is large enough
7327 * to avoid false sharing between CPUs, etc.
7329 * For the PCI Link, the smaller the Padding Boundary the
7330 * better. For the Memory Controller, a smaller Padding
7331 * Boundary is better until we cross under the Memory Line
7332 * Size (the minimum unit of transfer to/from Memory). If we
7333 * have a Padding Boundary which is smaller than the Memory
7334 * Line Size, that'll involve a Read-Modify-Write cycle on the
7335 * Memory Controller which is never good.
7338 /* We want the Packing Boundary to be based on the Cache Line
7339 * Size in order to help avoid False Sharing performance
7340 * issues between CPUs, etc. We also want the Packing
7341 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7342 * get best performance when the Packing Boundary is a
7343 * multiple of the Maximum Payload Size.
7345 pack_align = fl_align;
7346 if (pci_is_pcie(adap->pdev)) {
7347 unsigned int mps, mps_log;
7350 /* The PCIe Device Control Maximum Payload Size field
7351 * [bits 7:5] encodes sizes as powers of 2 starting at
7354 pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7356 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7358 if (mps > pack_align)
7362 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7363 * value for the Packing Boundary. This corresponds to 16
7364 * bytes instead of the expected 32 bytes. So if we want 32
7365 * bytes, the best we can really do is 64 bytes ...
7367 if (pack_align <= 16) {
7368 ingpack = INGPACKBOUNDARY_16B_X;
7370 } else if (pack_align == 32) {
7371 ingpack = INGPACKBOUNDARY_64B_X;
7374 unsigned int pack_align_log = fls(pack_align) - 1;
7376 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7377 fl_align = pack_align;
7380 /* Use the smallest Ingress Padding which isn't smaller than
7381 * the Memory Controller Read/Write Size. We'll take that as
7382 * being 8 bytes since we don't know of any system with a
7383 * wider Memory Controller Bus Width.
7385 if (is_t5(adap->params.chip))
7386 ingpad = INGPADBOUNDARY_32B_X;
7388 ingpad = T6_INGPADBOUNDARY_8B_X;
7390 t4_set_reg_field(adap, SGE_CONTROL_A,
7391 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7392 EGRSTATUSPAGESIZE_F,
7393 INGPADBOUNDARY_V(ingpad) |
7394 EGRSTATUSPAGESIZE_V(stat_len != 64));
7395 t4_set_reg_field(adap, SGE_CONTROL2_A,
7396 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7397 INGPACKBOUNDARY_V(ingpack));
7400 * Adjust various SGE Free List Host Buffer Sizes.
7402 * This is something of a crock since we're using fixed indices into
7403 * the array which are also known by the sge.c code and the T4
7404 * Firmware Configuration File. We need to come up with a much better
7405 * approach to managing this array. For now, the first four entries
7410 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7411 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7413 * For the single-MTU buffers in unpacked mode we need to include
7414 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7415 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7416 * Padding boundary. All of these are accommodated in the Factory
7417 * Default Firmware Configuration File but we need to adjust it for
7418 * this host's cache line size.
7420 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7421 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7422 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7424 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7425 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7428 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7434 * t4_fw_initialize - ask FW to initialize the device
7435 * @adap: the adapter
7436 * @mbox: mailbox to use for the FW command
7438 * Issues a command to FW to partially initialize the device. This
7439 * performs initialization that generally doesn't depend on user input.
7441 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7443 struct fw_initialize_cmd c;
7445 memset(&c, 0, sizeof(c));
7446 INIT_CMD(c, INITIALIZE, WRITE);
7447 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7451 * t4_query_params_rw - query FW or device parameters
7452 * @adap: the adapter
7453 * @mbox: mailbox to use for the FW command
7456 * @nparams: the number of parameters
7457 * @params: the parameter names
7458 * @val: the parameter values
7459 * @rw: Write and read flag
7460 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7462 * Reads the value of FW or device parameters. Up to 7 parameters can be
7465 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7466 unsigned int vf, unsigned int nparams, const u32 *params,
7467 u32 *val, int rw, bool sleep_ok)
7470 struct fw_params_cmd c;
7471 __be32 *p = &c.param[0].mnem;
7476 memset(&c, 0, sizeof(c));
7477 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7478 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7479 FW_PARAMS_CMD_PFN_V(pf) |
7480 FW_PARAMS_CMD_VFN_V(vf));
7481 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7483 for (i = 0; i < nparams; i++) {
7484 *p++ = cpu_to_be32(*params++);
7486 *p = cpu_to_be32(*(val + i));
7490 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7492 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7493 *val++ = be32_to_cpu(*p);
7497 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7498 unsigned int vf, unsigned int nparams, const u32 *params,
7501 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7505 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7506 unsigned int vf, unsigned int nparams, const u32 *params,
7509 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7514 * t4_set_params_timeout - sets FW or device parameters
7515 * @adap: the adapter
7516 * @mbox: mailbox to use for the FW command
7519 * @nparams: the number of parameters
7520 * @params: the parameter names
7521 * @val: the parameter values
7522 * @timeout: the timeout time
7524 * Sets the value of FW or device parameters. Up to 7 parameters can be
7525 * specified at once.
7527 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7528 unsigned int pf, unsigned int vf,
7529 unsigned int nparams, const u32 *params,
7530 const u32 *val, int timeout)
7532 struct fw_params_cmd c;
7533 __be32 *p = &c.param[0].mnem;
7538 memset(&c, 0, sizeof(c));
7539 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7540 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7541 FW_PARAMS_CMD_PFN_V(pf) |
7542 FW_PARAMS_CMD_VFN_V(vf));
7543 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7546 *p++ = cpu_to_be32(*params++);
7547 *p++ = cpu_to_be32(*val++);
7550 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7554 * t4_set_params - sets FW or device parameters
7555 * @adap: the adapter
7556 * @mbox: mailbox to use for the FW command
7559 * @nparams: the number of parameters
7560 * @params: the parameter names
7561 * @val: the parameter values
7563 * Sets the value of FW or device parameters. Up to 7 parameters can be
7564 * specified at once.
7566 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7567 unsigned int vf, unsigned int nparams, const u32 *params,
7570 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7571 FW_CMD_MAX_TIMEOUT);
7575 * t4_cfg_pfvf - configure PF/VF resource limits
7576 * @adap: the adapter
7577 * @mbox: mailbox to use for the FW command
7578 * @pf: the PF being configured
7579 * @vf: the VF being configured
7580 * @txq: the max number of egress queues
7581 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7582 * @rxqi: the max number of interrupt-capable ingress queues
7583 * @rxq: the max number of interruptless ingress queues
7584 * @tc: the PCI traffic class
7585 * @vi: the max number of virtual interfaces
7586 * @cmask: the channel access rights mask for the PF/VF
7587 * @pmask: the port access rights mask for the PF/VF
7588 * @nexact: the maximum number of exact MPS filters
7589 * @rcaps: read capabilities
7590 * @wxcaps: write/execute capabilities
7592 * Configures resource limits and capabilities for a physical or virtual
7595 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7596 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7597 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7598 unsigned int vi, unsigned int cmask, unsigned int pmask,
7599 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7601 struct fw_pfvf_cmd c;
7603 memset(&c, 0, sizeof(c));
7604 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7605 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7606 FW_PFVF_CMD_VFN_V(vf));
7607 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7608 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7609 FW_PFVF_CMD_NIQ_V(rxq));
7610 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7611 FW_PFVF_CMD_PMASK_V(pmask) |
7612 FW_PFVF_CMD_NEQ_V(txq));
7613 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7614 FW_PFVF_CMD_NVI_V(vi) |
7615 FW_PFVF_CMD_NEXACTF_V(nexact));
7616 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7617 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7618 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7619 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7623 * t4_alloc_vi - allocate a virtual interface
7624 * @adap: the adapter
7625 * @mbox: mailbox to use for the FW command
7626 * @port: physical port associated with the VI
7627 * @pf: the PF owning the VI
7628 * @vf: the VF owning the VI
7629 * @nmac: number of MAC addresses needed (1 to 5)
7630 * @mac: the MAC addresses of the VI
7631 * @rss_size: size of RSS table slice associated with this VI
7632 * @vivld: the destination to store the VI Valid value.
7633 * @vin: the destination to store the VIN value.
7635 * Allocates a virtual interface for the given physical port. If @mac is
7636 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7637 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7638 * stored consecutively so the space needed is @nmac * 6 bytes.
7639 * Returns a negative error number or the non-negative VI id.
7641 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7642 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7643 unsigned int *rss_size, u8 *vivld, u8 *vin)
7648 memset(&c, 0, sizeof(c));
7649 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7650 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7651 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7652 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7653 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7656 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7661 memcpy(mac, c.mac, sizeof(c.mac));
7664 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7667 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7670 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7673 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7677 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7680 *vivld = FW_VI_CMD_VFVLD_G(be32_to_cpu(c.alloc_to_len16));
7683 *vin = FW_VI_CMD_VIN_G(be32_to_cpu(c.alloc_to_len16));
7685 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7689 * t4_free_vi - free a virtual interface
7690 * @adap: the adapter
7691 * @mbox: mailbox to use for the FW command
7692 * @pf: the PF owning the VI
7693 * @vf: the VF owning the VI
7694 * @viid: virtual interface identifiler
7696 * Free a previously allocated virtual interface.
7698 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7699 unsigned int vf, unsigned int viid)
7703 memset(&c, 0, sizeof(c));
7704 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7707 FW_VI_CMD_PFN_V(pf) |
7708 FW_VI_CMD_VFN_V(vf));
7709 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7710 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7712 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7716 * t4_set_rxmode - set Rx properties of a virtual interface
7717 * @adap: the adapter
7718 * @mbox: mailbox to use for the FW command
7720 * @viid_mirror: the mirror VI id
7721 * @mtu: the new MTU or -1
7722 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7723 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7724 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7725 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7726 * @sleep_ok: if true we may sleep while awaiting command completion
7728 * Sets Rx properties of a virtual interface.
7730 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7731 unsigned int viid_mirror, int mtu, int promisc, int all_multi,
7732 int bcast, int vlanex, bool sleep_ok)
7734 struct fw_vi_rxmode_cmd c, c_mirror;
7737 /* convert to FW values */
7739 mtu = FW_RXMODE_MTU_NO_CHG;
7741 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7743 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7745 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7747 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7749 memset(&c, 0, sizeof(c));
7750 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7751 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7752 FW_VI_RXMODE_CMD_VIID_V(viid));
7753 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7755 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7756 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7757 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7758 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7759 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7762 memcpy(&c_mirror, &c, sizeof(c_mirror));
7763 c_mirror.op_to_viid =
7764 cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7765 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7766 FW_VI_RXMODE_CMD_VIID_V(viid_mirror));
7769 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7774 ret = t4_wr_mbox_meat(adap, mbox, &c_mirror, sizeof(c_mirror),
7781 * t4_free_encap_mac_filt - frees MPS entry at given index
7782 * @adap: the adapter
7784 * @idx: index of MPS entry to be freed
7785 * @sleep_ok: call is allowed to sleep
7787 * Frees the MPS entry at supplied index
7789 * Returns a negative error number or zero on success
7791 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7792 int idx, bool sleep_ok)
7794 struct fw_vi_mac_exact *p;
7795 u8 addr[] = {0, 0, 0, 0, 0, 0};
7796 struct fw_vi_mac_cmd c;
7800 memset(&c, 0, sizeof(c));
7801 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7802 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7804 FW_VI_MAC_CMD_VIID_V(viid));
7805 exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7806 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7810 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7811 FW_VI_MAC_CMD_IDX_V(idx));
7812 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7813 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7818 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7819 * @adap: the adapter
7821 * @addr: the MAC address
7823 * @idx: index of the entry in mps tcam
7824 * @lookup_type: MAC address for inner (1) or outer (0) header
7825 * @port_id: the port index
7826 * @sleep_ok: call is allowed to sleep
7828 * Removes the mac entry at the specified index using raw mac interface.
7830 * Returns a negative error number on failure.
7832 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7833 const u8 *addr, const u8 *mask, unsigned int idx,
7834 u8 lookup_type, u8 port_id, bool sleep_ok)
7836 struct fw_vi_mac_cmd c;
7837 struct fw_vi_mac_raw *p = &c.u.raw;
7840 memset(&c, 0, sizeof(c));
7841 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7842 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7844 FW_VI_MAC_CMD_VIID_V(viid));
7845 val = FW_CMD_LEN16_V(1) |
7846 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7847 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7848 FW_CMD_LEN16_V(val));
7850 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7851 FW_VI_MAC_ID_BASED_FREE);
7853 /* Lookup Type. Outer header: 0, Inner header: 1 */
7854 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7855 DATAPORTNUM_V(port_id));
7856 /* Lookup mask and port mask */
7857 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7858 DATAPORTNUM_V(DATAPORTNUM_M));
7860 /* Copy the address and the mask */
7861 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7862 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7864 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7868 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7869 * @adap: the adapter
7871 * @addr: the MAC address
7873 * @vni: the VNI id for the tunnel protocol
7874 * @vni_mask: mask for the VNI id
7875 * @dip_hit: to enable DIP match for the MPS entry
7876 * @lookup_type: MAC address for inner (1) or outer (0) header
7877 * @sleep_ok: call is allowed to sleep
7879 * Allocates an MPS entry with specified MAC address and VNI value.
7881 * Returns a negative error number or the allocated index for this mac.
7883 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7884 const u8 *addr, const u8 *mask, unsigned int vni,
7885 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7888 struct fw_vi_mac_cmd c;
7889 struct fw_vi_mac_vni *p = c.u.exact_vni;
7893 memset(&c, 0, sizeof(c));
7894 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7895 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7896 FW_VI_MAC_CMD_VIID_V(viid));
7897 val = FW_CMD_LEN16_V(1) |
7898 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7899 c.freemacs_to_len16 = cpu_to_be32(val);
7900 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7901 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7902 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7903 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7905 p->lookup_type_to_vni =
7906 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7907 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7908 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7909 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7910 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7912 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7917 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7918 * @adap: the adapter
7920 * @addr: the MAC address
7922 * @idx: index at which to add this entry
7923 * @lookup_type: MAC address for inner (1) or outer (0) header
7924 * @port_id: the port index
7925 * @sleep_ok: call is allowed to sleep
7927 * Adds the mac entry at the specified index using raw mac interface.
7929 * Returns a negative error number or the allocated index for this mac.
7931 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7932 const u8 *addr, const u8 *mask, unsigned int idx,
7933 u8 lookup_type, u8 port_id, bool sleep_ok)
7936 struct fw_vi_mac_cmd c;
7937 struct fw_vi_mac_raw *p = &c.u.raw;
7940 memset(&c, 0, sizeof(c));
7941 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7942 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7943 FW_VI_MAC_CMD_VIID_V(viid));
7944 val = FW_CMD_LEN16_V(1) |
7945 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7946 c.freemacs_to_len16 = cpu_to_be32(val);
7948 /* Specify that this is an inner mac address */
7949 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7951 /* Lookup Type. Outer header: 0, Inner header: 1 */
7952 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7953 DATAPORTNUM_V(port_id));
7954 /* Lookup mask and port mask */
7955 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7956 DATAPORTNUM_V(DATAPORTNUM_M));
7958 /* Copy the address and the mask */
7959 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7960 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7962 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7964 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7973 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7974 * @adap: the adapter
7975 * @mbox: mailbox to use for the FW command
7977 * @free: if true any existing filters for this VI id are first removed
7978 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7979 * @addr: the MAC address(es)
7980 * @idx: where to store the index of each allocated filter
7981 * @hash: pointer to hash address filter bitmap
7982 * @sleep_ok: call is allowed to sleep
7984 * Allocates an exact-match filter for each of the supplied addresses and
7985 * sets it to the corresponding address. If @idx is not %NULL it should
7986 * have at least @naddr entries, each of which will be set to the index of
7987 * the filter allocated for the corresponding MAC address. If a filter
7988 * could not be allocated for an address its index is set to 0xffff.
7989 * If @hash is not %NULL addresses that fail to allocate an exact filter
7990 * are hashed and update the hash filter bitmap pointed at by @hash.
7992 * Returns a negative error number or the number of filters allocated.
7994 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7995 unsigned int viid, bool free, unsigned int naddr,
7996 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7998 int offset, ret = 0;
7999 struct fw_vi_mac_cmd c;
8000 unsigned int nfilters = 0;
8001 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
8002 unsigned int rem = naddr;
8004 if (naddr > max_naddr)
8007 for (offset = 0; offset < naddr ; /**/) {
8008 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
8009 rem : ARRAY_SIZE(c.u.exact));
8010 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8011 u.exact[fw_naddr]), 16);
8012 struct fw_vi_mac_exact *p;
8015 memset(&c, 0, sizeof(c));
8016 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8019 FW_CMD_EXEC_V(free) |
8020 FW_VI_MAC_CMD_VIID_V(viid));
8021 c.freemacs_to_len16 =
8022 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
8023 FW_CMD_LEN16_V(len16));
8025 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8027 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8028 FW_VI_MAC_CMD_IDX_V(
8029 FW_VI_MAC_ADD_MAC));
8030 memcpy(p->macaddr, addr[offset + i],
8031 sizeof(p->macaddr));
8034 /* It's okay if we run out of space in our MAC address arena.
8035 * Some of the addresses we submit may get stored so we need
8036 * to run through the reply to see what the results were ...
8038 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8039 if (ret && ret != -FW_ENOMEM)
8042 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8043 u16 index = FW_VI_MAC_CMD_IDX_G(
8044 be16_to_cpu(p->valid_to_idx));
8047 idx[offset + i] = (index >= max_naddr ?
8049 if (index < max_naddr)
8053 hash_mac_addr(addr[offset + i]));
8061 if (ret == 0 || ret == -FW_ENOMEM)
8067 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8068 * @adap: the adapter
8069 * @mbox: mailbox to use for the FW command
8071 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8072 * @addr: the MAC address(es)
8073 * @sleep_ok: call is allowed to sleep
8075 * Frees the exact-match filter for each of the supplied addresses
8077 * Returns a negative error number or the number of filters freed.
8079 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8080 unsigned int viid, unsigned int naddr,
8081 const u8 **addr, bool sleep_ok)
8083 int offset, ret = 0;
8084 struct fw_vi_mac_cmd c;
8085 unsigned int nfilters = 0;
8086 unsigned int max_naddr = is_t4(adap->params.chip) ?
8087 NUM_MPS_CLS_SRAM_L_INSTANCES :
8088 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8089 unsigned int rem = naddr;
8091 if (naddr > max_naddr)
8094 for (offset = 0; offset < (int)naddr ; /**/) {
8095 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8097 : ARRAY_SIZE(c.u.exact));
8098 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8099 u.exact[fw_naddr]), 16);
8100 struct fw_vi_mac_exact *p;
8103 memset(&c, 0, sizeof(c));
8104 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8108 FW_VI_MAC_CMD_VIID_V(viid));
8109 c.freemacs_to_len16 =
8110 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8111 FW_CMD_LEN16_V(len16));
8113 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8114 p->valid_to_idx = cpu_to_be16(
8115 FW_VI_MAC_CMD_VALID_F |
8116 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
8117 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8120 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8124 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8125 u16 index = FW_VI_MAC_CMD_IDX_G(
8126 be16_to_cpu(p->valid_to_idx));
8128 if (index < max_naddr)
8142 * t4_change_mac - modifies the exact-match filter for a MAC address
8143 * @adap: the adapter
8144 * @mbox: mailbox to use for the FW command
8146 * @idx: index of existing filter for old value of MAC address, or -1
8147 * @addr: the new MAC address value
8148 * @persist: whether a new MAC allocation should be persistent
8149 * @smt_idx: the destination to store the new SMT index.
8151 * Modifies an exact-match filter and sets it to the new MAC address.
8152 * Note that in general it is not possible to modify the value of a given
8153 * filter so the generic way to modify an address filter is to free the one
8154 * being used by the old address value and allocate a new filter for the
8155 * new address value. @idx can be -1 if the address is a new addition.
8157 * Returns a negative error number or the index of the filter with the new
8160 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8161 int idx, const u8 *addr, bool persist, u8 *smt_idx)
8164 struct fw_vi_mac_cmd c;
8165 struct fw_vi_mac_exact *p = c.u.exact;
8166 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8168 if (idx < 0) /* new allocation */
8169 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8170 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8172 memset(&c, 0, sizeof(c));
8173 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8174 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8175 FW_VI_MAC_CMD_VIID_V(viid));
8176 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
8177 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8178 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
8179 FW_VI_MAC_CMD_IDX_V(idx));
8180 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8182 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8184 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8185 if (ret >= max_mac_addr)
8188 if (adap->params.viid_smt_extn_support) {
8189 *smt_idx = FW_VI_MAC_CMD_SMTID_G
8190 (be32_to_cpu(c.op_to_viid));
8192 /* In T4/T5, SMT contains 256 SMAC entries
8193 * organized in 128 rows of 2 entries each.
8194 * In T6, SMT contains 256 SMAC entries in
8197 if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8199 *smt_idx = (viid & FW_VIID_VIN_M) << 1;
8201 *smt_idx = (viid & FW_VIID_VIN_M);
8209 * t4_set_addr_hash - program the MAC inexact-match hash filter
8210 * @adap: the adapter
8211 * @mbox: mailbox to use for the FW command
8213 * @ucast: whether the hash filter should also match unicast addresses
8214 * @vec: the value to be written to the hash filter
8215 * @sleep_ok: call is allowed to sleep
8217 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8219 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8220 bool ucast, u64 vec, bool sleep_ok)
8222 struct fw_vi_mac_cmd c;
8224 memset(&c, 0, sizeof(c));
8225 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8226 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8227 FW_VI_ENABLE_CMD_VIID_V(viid));
8228 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8229 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8231 c.u.hash.hashvec = cpu_to_be64(vec);
8232 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8236 * t4_enable_vi_params - enable/disable a virtual interface
8237 * @adap: the adapter
8238 * @mbox: mailbox to use for the FW command
8240 * @rx_en: 1=enable Rx, 0=disable Rx
8241 * @tx_en: 1=enable Tx, 0=disable Tx
8242 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8244 * Enables/disables a virtual interface. Note that setting DCB Enable
8245 * only makes sense when enabling a Virtual Interface ...
8247 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8248 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8250 struct fw_vi_enable_cmd c;
8252 memset(&c, 0, sizeof(c));
8253 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8254 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8255 FW_VI_ENABLE_CMD_VIID_V(viid));
8256 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8257 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8258 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8260 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8264 * t4_enable_vi - enable/disable a virtual interface
8265 * @adap: the adapter
8266 * @mbox: mailbox to use for the FW command
8268 * @rx_en: 1=enable Rx, 0=disable Rx
8269 * @tx_en: 1=enable Tx, 0=disable Tx
8271 * Enables/disables a virtual interface.
8273 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8274 bool rx_en, bool tx_en)
8276 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8280 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8281 * @adap: the adapter
8282 * @mbox: mailbox to use for the FW command
8283 * @pi: the Port Information structure
8284 * @rx_en: 1=enable Rx, 0=disable Rx
8285 * @tx_en: 1=enable Tx, 0=disable Tx
8286 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8288 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8289 * Enable only makes sense when enabling a Virtual Interface ...
8290 * If the Virtual Interface enable/disable operation is successful,
8291 * we notify the OS-specific code of a potential Link Status change
8292 * via the OS Contract API t4_os_link_changed().
8294 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8295 struct port_info *pi,
8296 bool rx_en, bool tx_en, bool dcb_en)
8298 int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8299 rx_en, tx_en, dcb_en);
8302 t4_os_link_changed(adap, pi->port_id,
8303 rx_en && tx_en && pi->link_cfg.link_ok);
8308 * t4_identify_port - identify a VI's port by blinking its LED
8309 * @adap: the adapter
8310 * @mbox: mailbox to use for the FW command
8312 * @nblinks: how many times to blink LED at 2.5 Hz
8314 * Identifies a VI's port by blinking its LED.
8316 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8317 unsigned int nblinks)
8319 struct fw_vi_enable_cmd c;
8321 memset(&c, 0, sizeof(c));
8322 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8323 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8324 FW_VI_ENABLE_CMD_VIID_V(viid));
8325 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8326 c.blinkdur = cpu_to_be16(nblinks);
8327 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8331 * t4_iq_stop - stop an ingress queue and its FLs
8332 * @adap: the adapter
8333 * @mbox: mailbox to use for the FW command
8334 * @pf: the PF owning the queues
8335 * @vf: the VF owning the queues
8336 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8337 * @iqid: ingress queue id
8338 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8339 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8341 * Stops an ingress queue and its associated FLs, if any. This causes
8342 * any current or future data/messages destined for these queues to be
8345 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8346 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8347 unsigned int fl0id, unsigned int fl1id)
8351 memset(&c, 0, sizeof(c));
8352 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8353 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8354 FW_IQ_CMD_VFN_V(vf));
8355 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8356 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8357 c.iqid = cpu_to_be16(iqid);
8358 c.fl0id = cpu_to_be16(fl0id);
8359 c.fl1id = cpu_to_be16(fl1id);
8360 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8364 * t4_iq_free - free an ingress queue and its FLs
8365 * @adap: the adapter
8366 * @mbox: mailbox to use for the FW command
8367 * @pf: the PF owning the queues
8368 * @vf: the VF owning the queues
8369 * @iqtype: the ingress queue type
8370 * @iqid: ingress queue id
8371 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8372 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8374 * Frees an ingress queue and its associated FLs, if any.
8376 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8377 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8378 unsigned int fl0id, unsigned int fl1id)
8382 memset(&c, 0, sizeof(c));
8383 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8384 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8385 FW_IQ_CMD_VFN_V(vf));
8386 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8387 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8388 c.iqid = cpu_to_be16(iqid);
8389 c.fl0id = cpu_to_be16(fl0id);
8390 c.fl1id = cpu_to_be16(fl1id);
8391 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8395 * t4_eth_eq_free - free an Ethernet egress queue
8396 * @adap: the adapter
8397 * @mbox: mailbox to use for the FW command
8398 * @pf: the PF owning the queue
8399 * @vf: the VF owning the queue
8400 * @eqid: egress queue id
8402 * Frees an Ethernet egress queue.
8404 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8405 unsigned int vf, unsigned int eqid)
8407 struct fw_eq_eth_cmd c;
8409 memset(&c, 0, sizeof(c));
8410 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8411 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8412 FW_EQ_ETH_CMD_PFN_V(pf) |
8413 FW_EQ_ETH_CMD_VFN_V(vf));
8414 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8415 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8416 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8420 * t4_ctrl_eq_free - free a control egress queue
8421 * @adap: the adapter
8422 * @mbox: mailbox to use for the FW command
8423 * @pf: the PF owning the queue
8424 * @vf: the VF owning the queue
8425 * @eqid: egress queue id
8427 * Frees a control egress queue.
8429 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8430 unsigned int vf, unsigned int eqid)
8432 struct fw_eq_ctrl_cmd c;
8434 memset(&c, 0, sizeof(c));
8435 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8436 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8437 FW_EQ_CTRL_CMD_PFN_V(pf) |
8438 FW_EQ_CTRL_CMD_VFN_V(vf));
8439 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8440 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8441 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8445 * t4_ofld_eq_free - free an offload egress queue
8446 * @adap: the adapter
8447 * @mbox: mailbox to use for the FW command
8448 * @pf: the PF owning the queue
8449 * @vf: the VF owning the queue
8450 * @eqid: egress queue id
8452 * Frees a control egress queue.
8454 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8455 unsigned int vf, unsigned int eqid)
8457 struct fw_eq_ofld_cmd c;
8459 memset(&c, 0, sizeof(c));
8460 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8461 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8462 FW_EQ_OFLD_CMD_PFN_V(pf) |
8463 FW_EQ_OFLD_CMD_VFN_V(vf));
8464 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8465 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8466 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8470 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8471 * @link_down_rc: Link Down Reason Code
8473 * Returns a string representation of the Link Down Reason Code.
8475 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8477 static const char * const reason[] = {
8480 "Auto-negotiation Failure",
8482 "Insufficient Airflow",
8483 "Unable To Determine Reason",
8484 "No RX Signal Detected",
8488 if (link_down_rc >= ARRAY_SIZE(reason))
8489 return "Bad Reason Code";
8491 return reason[link_down_rc];
8494 /* Return the highest speed set in the port capabilities, in Mb/s. */
8495 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8497 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8499 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8503 TEST_SPEED_RETURN(400G, 400000);
8504 TEST_SPEED_RETURN(200G, 200000);
8505 TEST_SPEED_RETURN(100G, 100000);
8506 TEST_SPEED_RETURN(50G, 50000);
8507 TEST_SPEED_RETURN(40G, 40000);
8508 TEST_SPEED_RETURN(25G, 25000);
8509 TEST_SPEED_RETURN(10G, 10000);
8510 TEST_SPEED_RETURN(1G, 1000);
8511 TEST_SPEED_RETURN(100M, 100);
8513 #undef TEST_SPEED_RETURN
8519 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8520 * @acaps: advertised Port Capabilities
8522 * Get the highest speed for the port from the advertised Port
8523 * Capabilities. It will be either the highest speed from the list of
8524 * speeds or whatever user has set using ethtool.
8526 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8528 #define TEST_SPEED_RETURN(__caps_speed) \
8530 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8531 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8534 TEST_SPEED_RETURN(400G);
8535 TEST_SPEED_RETURN(200G);
8536 TEST_SPEED_RETURN(100G);
8537 TEST_SPEED_RETURN(50G);
8538 TEST_SPEED_RETURN(40G);
8539 TEST_SPEED_RETURN(25G);
8540 TEST_SPEED_RETURN(10G);
8541 TEST_SPEED_RETURN(1G);
8542 TEST_SPEED_RETURN(100M);
8544 #undef TEST_SPEED_RETURN
8550 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8551 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8553 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8554 * 32-bit Port Capabilities value.
8556 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8558 fw_port_cap32_t linkattr = 0;
8560 /* Unfortunately the format of the Link Status in the old
8561 * 16-bit Port Information message isn't the same as the
8562 * 16-bit Port Capabilities bitfield used everywhere else ...
8564 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8565 linkattr |= FW_PORT_CAP32_FC_RX;
8566 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8567 linkattr |= FW_PORT_CAP32_FC_TX;
8568 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8569 linkattr |= FW_PORT_CAP32_SPEED_100M;
8570 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8571 linkattr |= FW_PORT_CAP32_SPEED_1G;
8572 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8573 linkattr |= FW_PORT_CAP32_SPEED_10G;
8574 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8575 linkattr |= FW_PORT_CAP32_SPEED_25G;
8576 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8577 linkattr |= FW_PORT_CAP32_SPEED_40G;
8578 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8579 linkattr |= FW_PORT_CAP32_SPEED_100G;
8585 * t4_handle_get_port_info - process a FW reply message
8586 * @pi: the port info
8587 * @rpl: start of the FW message
8589 * Processes a GET_PORT_INFO FW reply message.
8591 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8593 const struct fw_port_cmd *cmd = (const void *)rpl;
8594 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8595 struct link_config *lc = &pi->link_cfg;
8596 struct adapter *adapter = pi->adapter;
8597 unsigned int speed, fc, fec, adv_fc;
8598 enum fw_port_module_type mod_type;
8599 int action, link_ok, linkdnrc;
8600 enum fw_port_type port_type;
8602 /* Extract the various fields from the Port Information message.
8604 action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8606 case FW_PORT_ACTION_GET_PORT_INFO: {
8607 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8609 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8610 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8611 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8612 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8613 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8614 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8615 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8616 linkattr = lstatus_to_fwcap(lstatus);
8620 case FW_PORT_ACTION_GET_PORT_INFO32: {
8623 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8624 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8625 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8626 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8627 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8628 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8629 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8630 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8631 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8636 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8637 be32_to_cpu(cmd->action_to_len16));
8641 fec = fwcap_to_cc_fec(acaps);
8642 adv_fc = fwcap_to_cc_pause(acaps);
8643 fc = fwcap_to_cc_pause(linkattr);
8644 speed = fwcap_to_speed(linkattr);
8646 /* Reset state for communicating new Transceiver Module status and
8647 * whether the OS-dependent layer wants us to redo the current
8648 * "sticky" L1 Configure Link Parameters.
8650 lc->new_module = false;
8651 lc->redo_l1cfg = false;
8653 if (mod_type != pi->mod_type) {
8654 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8655 * various fundamental Port Capabilities which used to be
8656 * immutable can now change radically. We can now have
8657 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8658 * all change based on what Transceiver Module is inserted.
8659 * So we need to record the Physical "Port" Capabilities on
8660 * every Transceiver Module change.
8664 /* When a new Transceiver Module is inserted, the Firmware
8665 * will examine its i2c EPROM to determine its type and
8666 * general operating parameters including things like Forward
8667 * Error Control, etc. Various IEEE 802.3 standards dictate
8668 * how to interpret these i2c values to determine default
8669 * "sutomatic" settings. We record these for future use when
8670 * the user explicitly requests these standards-based values.
8672 lc->def_acaps = acaps;
8674 /* Some versions of the early T6 Firmware "cheated" when
8675 * handling different Transceiver Modules by changing the
8676 * underlaying Port Type reported to the Host Drivers. As
8677 * such we need to capture whatever Port Type the Firmware
8678 * sends us and record it in case it's different from what we
8679 * were told earlier. Unfortunately, since Firmware is
8680 * forever, we'll need to keep this code here forever, but in
8681 * later T6 Firmware it should just be an assignment of the
8682 * same value already recorded.
8684 pi->port_type = port_type;
8686 /* Record new Module Type information.
8688 pi->mod_type = mod_type;
8690 /* Let the OS-dependent layer know if we have a new
8691 * Transceiver Module inserted.
8693 lc->new_module = t4_is_inserted_mod_type(mod_type);
8695 t4_os_portmod_changed(adapter, pi->port_id);
8698 if (link_ok != lc->link_ok || speed != lc->speed ||
8699 fc != lc->fc || adv_fc != lc->advertised_fc ||
8701 /* something changed */
8702 if (!link_ok && lc->link_ok) {
8703 lc->link_down_rc = linkdnrc;
8704 dev_warn_ratelimited(adapter->pdev_dev,
8705 "Port %d link down, reason: %s\n",
8707 t4_link_down_rc_str(linkdnrc));
8709 lc->link_ok = link_ok;
8711 lc->advertised_fc = adv_fc;
8715 lc->lpacaps = lpacaps;
8716 lc->acaps = acaps & ADVERT_MASK;
8718 /* If we're not physically capable of Auto-Negotiation, note
8719 * this as Auto-Negotiation disabled. Otherwise, we track
8720 * what Auto-Negotiation settings we have. Note parallel
8721 * structure in t4_link_l1cfg_core() and init_link_config().
8723 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8724 lc->autoneg = AUTONEG_DISABLE;
8725 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8726 lc->autoneg = AUTONEG_ENABLE;
8728 /* When Autoneg is disabled, user needs to set
8730 * Similar to cxgb4_ethtool.c: set_link_ksettings
8733 lc->speed_caps = fwcap_to_fwspeed(acaps);
8734 lc->autoneg = AUTONEG_DISABLE;
8737 t4_os_link_changed(adapter, pi->port_id, link_ok);
8740 /* If we have a new Transceiver Module and the OS-dependent code has
8741 * told us that it wants us to redo whatever "sticky" L1 Configuration
8742 * Link Parameters are set, do that now.
8744 if (lc->new_module && lc->redo_l1cfg) {
8745 struct link_config old_lc;
8748 /* Save the current L1 Configuration and restore it if an
8749 * error occurs. We probably should fix the l1_cfg*()
8750 * routines not to change the link_config when an error
8754 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8757 dev_warn(adapter->pdev_dev,
8758 "Attempt to update new Transceiver Module settings failed\n");
8761 lc->new_module = false;
8762 lc->redo_l1cfg = false;
8766 * t4_update_port_info - retrieve and update port information if changed
8767 * @pi: the port_info
8769 * We issue a Get Port Information Command to the Firmware and, if
8770 * successful, we check to see if anything is different from what we
8771 * last recorded and update things accordingly.
8773 int t4_update_port_info(struct port_info *pi)
8775 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8776 struct fw_port_cmd port_cmd;
8779 memset(&port_cmd, 0, sizeof(port_cmd));
8780 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8781 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8782 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8783 port_cmd.action_to_len16 = cpu_to_be32(
8784 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8785 ? FW_PORT_ACTION_GET_PORT_INFO
8786 : FW_PORT_ACTION_GET_PORT_INFO32) |
8787 FW_LEN16(port_cmd));
8788 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8789 &port_cmd, sizeof(port_cmd), &port_cmd);
8793 t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8798 * t4_get_link_params - retrieve basic link parameters for given port
8800 * @link_okp: value return pointer for link up/down
8801 * @speedp: value return pointer for speed (Mb/s)
8802 * @mtup: value return pointer for mtu
8804 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8805 * and MTU for a specified port. A negative error is returned on
8806 * failure; 0 on success.
8808 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8809 unsigned int *speedp, unsigned int *mtup)
8811 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8812 unsigned int action, link_ok, mtu;
8813 struct fw_port_cmd port_cmd;
8814 fw_port_cap32_t linkattr;
8817 memset(&port_cmd, 0, sizeof(port_cmd));
8818 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8819 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8820 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8821 action = (fw_caps == FW_CAPS16
8822 ? FW_PORT_ACTION_GET_PORT_INFO
8823 : FW_PORT_ACTION_GET_PORT_INFO32);
8824 port_cmd.action_to_len16 = cpu_to_be32(
8825 FW_PORT_CMD_ACTION_V(action) |
8826 FW_LEN16(port_cmd));
8827 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8828 &port_cmd, sizeof(port_cmd), &port_cmd);
8832 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8833 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8835 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8836 linkattr = lstatus_to_fwcap(lstatus);
8837 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8840 be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8842 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8843 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8844 mtu = FW_PORT_CMD_MTU32_G(
8845 be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8849 *link_okp = link_ok;
8851 *speedp = fwcap_to_speed(linkattr);
8859 * t4_handle_fw_rpl - process a FW reply message
8860 * @adap: the adapter
8861 * @rpl: start of the FW message
8863 * Processes a FW message, such as link state change messages.
8865 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8867 u8 opcode = *(const u8 *)rpl;
8869 /* This might be a port command ... this simplifies the following
8870 * conditionals ... We can get away with pre-dereferencing
8871 * action_to_len16 because it's in the first 16 bytes and all messages
8872 * will be at least that long.
8874 const struct fw_port_cmd *p = (const void *)rpl;
8875 unsigned int action =
8876 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8878 if (opcode == FW_PORT_CMD &&
8879 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8880 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8882 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8883 struct port_info *pi = NULL;
8885 for_each_port(adap, i) {
8886 pi = adap2pinfo(adap, i);
8887 if (pi->tx_chan == chan)
8891 t4_handle_get_port_info(pi, rpl);
8893 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8900 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8904 if (pci_is_pcie(adapter->pdev)) {
8905 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8906 p->speed = val & PCI_EXP_LNKSTA_CLS;
8907 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8912 * init_link_config - initialize a link's SW state
8913 * @lc: pointer to structure holding the link state
8914 * @pcaps: link Port Capabilities
8915 * @acaps: link current Advertised Port Capabilities
8917 * Initializes the SW state maintained for each link, including the link's
8918 * capabilities and default speed/flow-control/autonegotiation settings.
8920 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8921 fw_port_cap32_t acaps)
8924 lc->def_acaps = acaps;
8928 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8930 /* For Forward Error Control, we default to whatever the Firmware
8931 * tells us the Link is currently advertising.
8933 lc->requested_fec = FEC_AUTO;
8934 lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8936 /* If the Port is capable of Auto-Negtotiation, initialize it as
8937 * "enabled" and copy over all of the Physical Port Capabilities
8938 * to the Advertised Port Capabilities. Otherwise mark it as
8939 * Auto-Negotiate disabled and select the highest supported speed
8940 * for the link. Note parallel structure in t4_link_l1cfg_core()
8941 * and t4_handle_get_port_info().
8943 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8944 lc->acaps = lc->pcaps & ADVERT_MASK;
8945 lc->autoneg = AUTONEG_ENABLE;
8946 lc->requested_fc |= PAUSE_AUTONEG;
8949 lc->autoneg = AUTONEG_DISABLE;
8950 lc->speed_caps = fwcap_to_fwspeed(acaps);
8954 #define CIM_PF_NOACCESS 0xeeeeeeee
8956 int t4_wait_dev_ready(void __iomem *regs)
8960 whoami = readl(regs + PL_WHOAMI_A);
8961 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8965 whoami = readl(regs + PL_WHOAMI_A);
8966 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8970 u32 vendor_and_model_id;
8974 static int t4_get_flash_params(struct adapter *adap)
8976 /* Table for non-Numonix supported flash parts. Numonix parts are left
8977 * to the preexisting code. All flash parts have 64KB sectors.
8979 static struct flash_desc supported_flash[] = {
8980 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8983 unsigned int part, manufacturer;
8984 unsigned int density, size = 0;
8988 /* Issue a Read ID Command to the Flash part. We decode supported
8989 * Flash parts and their sizes from this. There's a newer Query
8990 * Command which can retrieve detailed geometry information but many
8991 * Flash parts don't support it.
8994 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8996 ret = sf1_read(adap, 3, 0, 1, &flashid);
8997 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
9001 /* Check to see if it's one of our non-standard supported Flash parts.
9003 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
9004 if (supported_flash[part].vendor_and_model_id == flashid) {
9005 adap->params.sf_size = supported_flash[part].size_mb;
9006 adap->params.sf_nsec =
9007 adap->params.sf_size / SF_SEC_SIZE;
9011 /* Decode Flash part size. The code below looks repetitive with
9012 * common encodings, but that's not guaranteed in the JEDEC
9013 * specification for the Read JEDEC ID command. The only thing that
9014 * we're guaranteed by the JEDEC specification is where the
9015 * Manufacturer ID is in the returned result. After that each
9016 * Manufacturer ~could~ encode things completely differently.
9017 * Note, all Flash parts must have 64KB sectors.
9019 manufacturer = flashid & 0xff;
9020 switch (manufacturer) {
9021 case 0x20: { /* Micron/Numonix */
9022 /* This Density -> Size decoding table is taken from Micron
9025 density = (flashid >> 16) & 0xff;
9027 case 0x14: /* 1MB */
9030 case 0x15: /* 2MB */
9033 case 0x16: /* 4MB */
9036 case 0x17: /* 8MB */
9039 case 0x18: /* 16MB */
9042 case 0x19: /* 32MB */
9045 case 0x20: /* 64MB */
9048 case 0x21: /* 128MB */
9051 case 0x22: /* 256MB */
9057 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9058 /* This Density -> Size decoding table is taken from ISSI
9061 density = (flashid >> 16) & 0xff;
9063 case 0x16: /* 32 MB */
9066 case 0x17: /* 64MB */
9072 case 0xc2: { /* Macronix */
9073 /* This Density -> Size decoding table is taken from Macronix
9076 density = (flashid >> 16) & 0xff;
9078 case 0x17: /* 8MB */
9081 case 0x18: /* 16MB */
9087 case 0xef: { /* Winbond */
9088 /* This Density -> Size decoding table is taken from Winbond
9091 density = (flashid >> 16) & 0xff;
9093 case 0x17: /* 8MB */
9096 case 0x18: /* 16MB */
9104 /* If we didn't recognize the FLASH part, that's no real issue: the
9105 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9106 * use a FLASH part which is at least 4MB in size and has 64KB
9107 * sectors. The unrecognized FLASH part is likely to be much larger
9108 * than 4MB, but that's all we really need.
9111 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9116 /* Store decoded Flash size and fall through into vetting code. */
9117 adap->params.sf_size = size;
9118 adap->params.sf_nsec = size / SF_SEC_SIZE;
9121 if (adap->params.sf_size < FLASH_MIN_SIZE)
9122 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9123 flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9128 * t4_prep_adapter - prepare SW and HW for operation
9129 * @adapter: the adapter
9131 * Initialize adapter SW state for the various HW modules, set initial
9132 * values for some adapter tunables, take PHYs out of reset, and
9133 * initialize the MDIO interface.
9135 int t4_prep_adapter(struct adapter *adapter)
9141 get_pci_mode(adapter, &adapter->params.pci);
9142 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9144 ret = t4_get_flash_params(adapter);
9146 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
9150 /* Retrieve adapter's device ID
9152 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
9153 ver = device_id >> 12;
9154 adapter->params.chip = 0;
9157 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
9158 adapter->params.arch.sge_fl_db = DBPRIO_F;
9159 adapter->params.arch.mps_tcam_size =
9160 NUM_MPS_CLS_SRAM_L_INSTANCES;
9161 adapter->params.arch.mps_rplc_size = 128;
9162 adapter->params.arch.nchan = NCHAN;
9163 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9164 adapter->params.arch.vfcount = 128;
9165 /* Congestion map is for 4 channels so that
9166 * MPS can have 4 priority per port.
9168 adapter->params.arch.cng_ch_bits_log = 2;
9171 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
9172 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
9173 adapter->params.arch.mps_tcam_size =
9174 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9175 adapter->params.arch.mps_rplc_size = 128;
9176 adapter->params.arch.nchan = NCHAN;
9177 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9178 adapter->params.arch.vfcount = 128;
9179 adapter->params.arch.cng_ch_bits_log = 2;
9182 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
9183 adapter->params.arch.sge_fl_db = 0;
9184 adapter->params.arch.mps_tcam_size =
9185 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9186 adapter->params.arch.mps_rplc_size = 256;
9187 adapter->params.arch.nchan = 2;
9188 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
9189 adapter->params.arch.vfcount = 256;
9190 /* Congestion map will be for 2 channels so that
9191 * MPS can have 8 priority per port.
9193 adapter->params.arch.cng_ch_bits_log = 3;
9196 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
9201 adapter->params.cim_la_size = CIMLA_SIZE;
9202 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9205 * Default port for debugging in case we can't reach FW.
9207 adapter->params.nports = 1;
9208 adapter->params.portvec = 1;
9209 adapter->params.vpd.cclk = 50000;
9211 /* Set PCIe completion timeout to 4 seconds. */
9212 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
9213 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
9218 * t4_shutdown_adapter - shut down adapter, host & wire
9219 * @adapter: the adapter
9221 * Perform an emergency shutdown of the adapter and stop it from
9222 * continuing any further communication on the ports or DMA to the
9223 * host. This is typically used when the adapter and/or firmware
9224 * have crashed and we want to prevent any further accidental
9225 * communication with the rest of the world. This will also force
9226 * the port Link Status to go down -- if register writes work --
9227 * which should help our peers figure out that we're down.
9229 int t4_shutdown_adapter(struct adapter *adapter)
9233 t4_intr_disable(adapter);
9234 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9235 for_each_port(adapter, port) {
9236 u32 a_port_cfg = is_t4(adapter->params.chip) ?
9237 PORT_REG(port, XGMAC_PORT_CFG_A) :
9238 T5_PORT_REG(port, MAC_PORT_CFG_A);
9240 t4_write_reg(adapter, a_port_cfg,
9241 t4_read_reg(adapter, a_port_cfg)
9242 & ~SIGNAL_DET_V(1));
9244 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9250 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9251 * @adapter: the adapter
9252 * @qid: the Queue ID
9253 * @qtype: the Ingress or Egress type for @qid
9254 * @user: true if this request is for a user mode queue
9255 * @pbar2_qoffset: BAR2 Queue Offset
9256 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9258 * Returns the BAR2 SGE Queue Registers information associated with the
9259 * indicated Absolute Queue ID. These are passed back in return value
9260 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9261 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9263 * This may return an error which indicates that BAR2 SGE Queue
9264 * registers aren't available. If an error is not returned, then the
9265 * following values are returned:
9267 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9268 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9270 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9271 * require the "Inferred Queue ID" ability may be used. E.g. the
9272 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9273 * then these "Inferred Queue ID" register may not be used.
9275 int t4_bar2_sge_qregs(struct adapter *adapter,
9277 enum t4_bar2_qtype qtype,
9280 unsigned int *pbar2_qid)
9282 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9283 u64 bar2_page_offset, bar2_qoffset;
9284 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9286 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9287 if (!user && is_t4(adapter->params.chip))
9290 /* Get our SGE Page Size parameters.
9292 page_shift = adapter->params.sge.hps + 10;
9293 page_size = 1 << page_shift;
9295 /* Get the right Queues per Page parameters for our Queue.
9297 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9298 ? adapter->params.sge.eq_qpp
9299 : adapter->params.sge.iq_qpp);
9300 qpp_mask = (1 << qpp_shift) - 1;
9302 /* Calculate the basics of the BAR2 SGE Queue register area:
9303 * o The BAR2 page the Queue registers will be in.
9304 * o The BAR2 Queue ID.
9305 * o The BAR2 Queue ID Offset into the BAR2 page.
9307 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9308 bar2_qid = qid & qpp_mask;
9309 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9311 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9312 * hardware will infer the Absolute Queue ID simply from the writes to
9313 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9314 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9315 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9316 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9317 * from the BAR2 Page and BAR2 Queue ID.
9319 * One important censequence of this is that some BAR2 SGE registers
9320 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9321 * there. But other registers synthesize the SGE Queue ID purely
9322 * from the writes to the registers -- the Write Combined Doorbell
9323 * Buffer is a good example. These BAR2 SGE Registers are only
9324 * available for those BAR2 SGE Register areas where the SGE Absolute
9325 * Queue ID can be inferred from simple writes.
9327 bar2_qoffset = bar2_page_offset;
9328 bar2_qinferred = (bar2_qid_offset < page_size);
9329 if (bar2_qinferred) {
9330 bar2_qoffset += bar2_qid_offset;
9334 *pbar2_qoffset = bar2_qoffset;
9335 *pbar2_qid = bar2_qid;
9340 * t4_init_devlog_params - initialize adapter->params.devlog
9341 * @adap: the adapter
9343 * Initialize various fields of the adapter's Firmware Device Log
9344 * Parameters structure.
9346 int t4_init_devlog_params(struct adapter *adap)
9348 struct devlog_params *dparams = &adap->params.devlog;
9350 unsigned int devlog_meminfo;
9351 struct fw_devlog_cmd devlog_cmd;
9354 /* If we're dealing with newer firmware, the Device Log Parameters
9355 * are stored in a designated register which allows us to access the
9356 * Device Log even if we can't talk to the firmware.
9359 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9361 unsigned int nentries, nentries128;
9363 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9364 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9366 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9367 nentries = (nentries128 + 1) * 128;
9368 dparams->size = nentries * sizeof(struct fw_devlog_e);
9373 /* Otherwise, ask the firmware for it's Device Log Parameters.
9375 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9376 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9377 FW_CMD_REQUEST_F | FW_CMD_READ_F);
9378 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9379 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9385 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9386 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9387 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9388 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9394 * t4_init_sge_params - initialize adap->params.sge
9395 * @adapter: the adapter
9397 * Initialize various fields of the adapter's SGE Parameters structure.
9399 int t4_init_sge_params(struct adapter *adapter)
9401 struct sge_params *sge_params = &adapter->params.sge;
9403 unsigned int s_hps, s_qpp;
9405 /* Extract the SGE Page Size for our PF.
9407 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9408 s_hps = (HOSTPAGESIZEPF0_S +
9409 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9410 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9412 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9414 s_qpp = (QUEUESPERPAGEPF0_S +
9415 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9416 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9417 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9418 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9419 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9425 * t4_init_tp_params - initialize adap->params.tp
9426 * @adap: the adapter
9427 * @sleep_ok: if true we may sleep while awaiting command completion
9429 * Initialize various fields of the adapter's TP Parameters structure.
9431 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9437 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9438 adap->params.tp.tre = TIMERRESOLUTION_G(v);
9439 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9441 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9442 for (chan = 0; chan < NCHAN; chan++)
9443 adap->params.tp.tx_modq[chan] = chan;
9445 /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9448 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
9449 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER) |
9450 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK));
9452 /* Read current value */
9453 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9456 dev_info(adap->pdev_dev,
9457 "Current filter mode/mask 0x%x:0x%x\n",
9458 FW_PARAMS_PARAM_FILTER_MODE_G(val),
9459 FW_PARAMS_PARAM_FILTER_MASK_G(val));
9460 adap->params.tp.vlan_pri_map =
9461 FW_PARAMS_PARAM_FILTER_MODE_G(val);
9462 adap->params.tp.filter_mask =
9463 FW_PARAMS_PARAM_FILTER_MASK_G(val);
9465 dev_info(adap->pdev_dev,
9466 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9468 /* Incase of older-fw (which doesn't expose the api
9469 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9470 * the fw api) combination, fall-back to older method of reading
9471 * the filter mode from indirect-register
9473 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9474 TP_VLAN_PRI_MAP_A, sleep_ok);
9476 /* With the older-fw and newer-driver combination we might run
9477 * into an issue when user wants to use hash filter region but
9478 * the filter_mask is zero, in this case filter_mask validation
9479 * is tough. To avoid that we set the filter_mask same as filter
9480 * mode, which will behave exactly as the older way of ignoring
9481 * the filter mask validation.
9483 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9486 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9487 TP_INGRESS_CONFIG_A, sleep_ok);
9489 /* For T6, cache the adapter's compressed error vector
9490 * and passing outer header info for encapsulated packets.
9492 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9493 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9494 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9497 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9498 * shift positions of several elements of the Compressed Filter Tuple
9499 * for this adapter which we need frequently ...
9501 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9502 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9503 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9504 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9505 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9506 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9508 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9510 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9512 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9514 adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9517 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9518 * represents the presence of an Outer VLAN instead of a VNIC ID.
9520 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9521 adap->params.tp.vnic_shift = -1;
9523 v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9524 adap->params.tp.hash_filter_mask = v;
9525 v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9526 adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9531 * t4_filter_field_shift - calculate filter field shift
9532 * @adap: the adapter
9533 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9535 * Return the shift position of a filter field within the Compressed
9536 * Filter Tuple. The filter field is specified via its selection bit
9537 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9539 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9541 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9545 if ((filter_mode & filter_sel) == 0)
9548 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9549 switch (filter_mode & sel) {
9551 field_shift += FT_FCOE_W;
9554 field_shift += FT_PORT_W;
9557 field_shift += FT_VNIC_ID_W;
9560 field_shift += FT_VLAN_W;
9563 field_shift += FT_TOS_W;
9566 field_shift += FT_PROTOCOL_W;
9569 field_shift += FT_ETHERTYPE_W;
9572 field_shift += FT_MACMATCH_W;
9575 field_shift += FT_MPSHITTYPE_W;
9577 case FRAGMENTATION_F:
9578 field_shift += FT_FRAGMENTATION_W;
9585 int t4_init_rss_mode(struct adapter *adap, int mbox)
9588 struct fw_rss_vi_config_cmd rvc;
9590 memset(&rvc, 0, sizeof(rvc));
9592 for_each_port(adap, i) {
9593 struct port_info *p = adap2pinfo(adap, i);
9596 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9597 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9598 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9599 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9600 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9603 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9609 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9610 * @pi: the port_info
9611 * @mbox: mailbox to use for the FW command
9612 * @port: physical port associated with the VI
9613 * @pf: the PF owning the VI
9614 * @vf: the VF owning the VI
9615 * @mac: the MAC address of the VI
9617 * Allocates a virtual interface for the given physical port. If @mac is
9618 * not %NULL it contains the MAC address of the VI as assigned by FW.
9619 * @mac should be large enough to hold an Ethernet address.
9620 * Returns < 0 on error.
9622 int t4_init_portinfo(struct port_info *pi, int mbox,
9623 int port, int pf, int vf, u8 mac[])
9625 struct adapter *adapter = pi->adapter;
9626 unsigned int fw_caps = adapter->params.fw_caps_support;
9627 struct fw_port_cmd cmd;
9628 unsigned int rss_size;
9629 enum fw_port_type port_type;
9631 fw_port_cap32_t pcaps, acaps;
9632 u8 vivld = 0, vin = 0;
9635 /* If we haven't yet determined whether we're talking to Firmware
9636 * which knows the new 32-bit Port Capabilities, it's time to find
9637 * out now. This will also tell new Firmware to send us Port Status
9638 * Updates using the new 32-bit Port Capabilities version of the
9639 * Port Information message.
9641 if (fw_caps == FW_CAPS_UNKNOWN) {
9644 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9645 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9647 ret = t4_set_params(adapter, mbox, pf, vf, 1, ¶m, &val);
9648 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9649 adapter->params.fw_caps_support = fw_caps;
9652 memset(&cmd, 0, sizeof(cmd));
9653 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9654 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9655 FW_PORT_CMD_PORTID_V(port));
9656 cmd.action_to_len16 = cpu_to_be32(
9657 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9658 ? FW_PORT_ACTION_GET_PORT_INFO
9659 : FW_PORT_ACTION_GET_PORT_INFO32) |
9661 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9665 /* Extract the various fields from the Port Information message.
9667 if (fw_caps == FW_CAPS16) {
9668 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9670 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9671 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9672 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9674 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9675 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9677 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9679 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9680 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9681 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9683 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9684 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9687 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size,
9695 pi->rss_size = rss_size;
9696 pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
9698 /* If fw supports returning the VIN as part of FW_VI_CMD,
9699 * save the returned values.
9701 if (adapter->params.viid_smt_extn_support) {
9705 /* Retrieve the values from VIID */
9706 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
9707 pi->vin = FW_VIID_VIN_G(pi->viid);
9710 pi->port_type = port_type;
9711 pi->mdio_addr = mdio_addr;
9712 pi->mod_type = FW_PORT_MOD_TYPE_NA;
9714 init_link_config(&pi->link_cfg, pcaps, acaps);
9718 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9723 for_each_port(adap, i) {
9724 struct port_info *pi = adap2pinfo(adap, i);
9726 while ((adap->params.portvec & (1 << j)) == 0)
9729 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9733 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9739 int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
9744 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL,
9756 * t4_read_cimq_cfg - read CIM queue configuration
9757 * @adap: the adapter
9758 * @base: holds the queue base addresses in bytes
9759 * @size: holds the queue sizes in bytes
9760 * @thres: holds the queue full thresholds in bytes
9762 * Returns the current configuration of the CIM queues, starting with
9763 * the IBQs, then the OBQs.
9765 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9768 int cim_num_obq = is_t4(adap->params.chip) ?
9769 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9771 for (i = 0; i < CIM_NUM_IBQ; i++) {
9772 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9774 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9775 /* value is in 256-byte units */
9776 *base++ = CIMQBASE_G(v) * 256;
9777 *size++ = CIMQSIZE_G(v) * 256;
9778 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9780 for (i = 0; i < cim_num_obq; i++) {
9781 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9783 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9784 /* value is in 256-byte units */
9785 *base++ = CIMQBASE_G(v) * 256;
9786 *size++ = CIMQSIZE_G(v) * 256;
9791 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9792 * @adap: the adapter
9793 * @qid: the queue index
9794 * @data: where to store the queue contents
9795 * @n: capacity of @data in 32-bit words
9797 * Reads the contents of the selected CIM queue starting at address 0 up
9798 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9799 * error and the number of 32-bit words actually read on success.
9801 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9803 int i, err, attempts;
9805 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9807 if (qid > 5 || (n & 3))
9810 addr = qid * nwords;
9814 /* It might take 3-10ms before the IBQ debug read access is allowed.
9815 * Wait for 1 Sec with a delay of 1 usec.
9819 for (i = 0; i < n; i++, addr++) {
9820 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9822 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9826 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9828 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9833 * t4_read_cim_obq - read the contents of a CIM outbound queue
9834 * @adap: the adapter
9835 * @qid: the queue index
9836 * @data: where to store the queue contents
9837 * @n: capacity of @data in 32-bit words
9839 * Reads the contents of the selected CIM queue starting at address 0 up
9840 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9841 * error and the number of 32-bit words actually read on success.
9843 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9846 unsigned int addr, v, nwords;
9847 int cim_num_obq = is_t4(adap->params.chip) ?
9848 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9850 if ((qid > (cim_num_obq - 1)) || (n & 3))
9853 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9854 QUENUMSELECT_V(qid));
9855 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9857 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
9858 nwords = CIMQSIZE_G(v) * 64; /* same */
9862 for (i = 0; i < n; i++, addr++) {
9863 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9865 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9869 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9871 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9876 * t4_cim_read - read a block from CIM internal address space
9877 * @adap: the adapter
9878 * @addr: the start address within the CIM address space
9879 * @n: number of words to read
9880 * @valp: where to store the result
9882 * Reads a block of 4-byte words from the CIM intenal address space.
9884 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9889 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9892 for ( ; !ret && n--; addr += 4) {
9893 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9894 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9897 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9903 * t4_cim_write - write a block into CIM internal address space
9904 * @adap: the adapter
9905 * @addr: the start address within the CIM address space
9906 * @n: number of words to write
9907 * @valp: set of values to write
9909 * Writes a block of 4-byte words into the CIM intenal address space.
9911 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9912 const unsigned int *valp)
9916 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9919 for ( ; !ret && n--; addr += 4) {
9920 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9921 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9922 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9928 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9931 return t4_cim_write(adap, addr, 1, &val);
9935 * t4_cim_read_la - read CIM LA capture buffer
9936 * @adap: the adapter
9937 * @la_buf: where to store the LA data
9938 * @wrptr: the HW write pointer within the capture buffer
9940 * Reads the contents of the CIM LA buffer with the most recent entry at
9941 * the end of the returned data and with the entry at @wrptr first.
9942 * We try to leave the LA in the running state we find it in.
9944 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9947 unsigned int cfg, val, idx;
9949 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9953 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
9954 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9959 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9963 idx = UPDBGLAWRPTR_G(val);
9967 for (i = 0; i < adap->params.cim_la_size; i++) {
9968 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9969 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9972 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9975 if (val & UPDBGLARDEN_F) {
9979 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9983 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9984 * identify the 32-bit portion of the full 312-bit data
9986 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9987 idx = (idx & 0xff0) + 0x10;
9990 /* address can't exceed 0xfff */
9991 idx &= UPDBGLARDPTR_M;
9994 if (cfg & UPDBGLAEN_F) {
9995 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9996 cfg & ~UPDBGLARDEN_F);
10004 * t4_tp_read_la - read TP LA capture buffer
10005 * @adap: the adapter
10006 * @la_buf: where to store the LA data
10007 * @wrptr: the HW write pointer within the capture buffer
10009 * Reads the contents of the TP LA buffer with the most recent entry at
10010 * the end of the returned data and with the entry at @wrptr first.
10011 * We leave the LA in the running state we find it in.
10013 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
10015 bool last_incomplete;
10016 unsigned int i, cfg, val, idx;
10018 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
10019 if (cfg & DBGLAENABLE_F) /* freeze LA */
10020 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10021 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
10023 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
10024 idx = DBGLAWPTR_G(val);
10025 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
10026 if (last_incomplete)
10027 idx = (idx + 1) & DBGLARPTR_M;
10032 val &= ~DBGLARPTR_V(DBGLARPTR_M);
10033 val |= adap->params.tp.la_mask;
10035 for (i = 0; i < TPLA_SIZE; i++) {
10036 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
10037 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
10038 idx = (idx + 1) & DBGLARPTR_M;
10041 /* Wipe out last entry if it isn't valid */
10042 if (last_incomplete)
10043 la_buf[TPLA_SIZE - 1] = ~0ULL;
10045 if (cfg & DBGLAENABLE_F) /* restore running state */
10046 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10047 cfg | adap->params.tp.la_mask);
10050 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10051 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10052 * state for more than the Warning Threshold then we'll issue a warning about
10053 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10054 * appears to be hung every Warning Repeat second till the situation clears.
10055 * If the situation clears, we'll note that as well.
10057 #define SGE_IDMA_WARN_THRESH 1
10058 #define SGE_IDMA_WARN_REPEAT 300
10061 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10062 * @adapter: the adapter
10063 * @idma: the adapter IDMA Monitor state
10065 * Initialize the state of an SGE Ingress DMA Monitor.
10067 void t4_idma_monitor_init(struct adapter *adapter,
10068 struct sge_idma_monitor_state *idma)
10070 /* Initialize the state variables for detecting an SGE Ingress DMA
10071 * hang. The SGE has internal counters which count up on each clock
10072 * tick whenever the SGE finds its Ingress DMA State Engines in the
10073 * same state they were on the previous clock tick. The clock used is
10074 * the Core Clock so we have a limit on the maximum "time" they can
10075 * record; typically a very small number of seconds. For instance,
10076 * with a 600MHz Core Clock, we can only count up to a bit more than
10077 * 7s. So we'll synthesize a larger counter in order to not run the
10078 * risk of having the "timers" overflow and give us the flexibility to
10079 * maintain a Hung SGE State Machine of our own which operates across
10080 * a longer time frame.
10082 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10083 idma->idma_stalled[0] = 0;
10084 idma->idma_stalled[1] = 0;
10088 * t4_idma_monitor - monitor SGE Ingress DMA state
10089 * @adapter: the adapter
10090 * @idma: the adapter IDMA Monitor state
10091 * @hz: number of ticks/second
10092 * @ticks: number of ticks since the last IDMA Monitor call
10094 void t4_idma_monitor(struct adapter *adapter,
10095 struct sge_idma_monitor_state *idma,
10098 int i, idma_same_state_cnt[2];
10100 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10101 * are counters inside the SGE which count up on each clock when the
10102 * SGE finds its Ingress DMA State Engines in the same states they
10103 * were in the previous clock. The counters will peg out at
10104 * 0xffffffff without wrapping around so once they pass the 1s
10105 * threshold they'll stay above that till the IDMA state changes.
10107 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
10108 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10109 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10111 for (i = 0; i < 2; i++) {
10112 u32 debug0, debug11;
10114 /* If the Ingress DMA Same State Counter ("timer") is less
10115 * than 1s, then we can reset our synthesized Stall Timer and
10116 * continue. If we have previously emitted warnings about a
10117 * potential stalled Ingress Queue, issue a note indicating
10118 * that the Ingress Queue has resumed forward progress.
10120 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10121 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
10122 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
10123 "resumed after %d seconds\n",
10124 i, idma->idma_qid[i],
10125 idma->idma_stalled[i] / hz);
10126 idma->idma_stalled[i] = 0;
10130 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10131 * domain. The first time we get here it'll be because we
10132 * passed the 1s Threshold; each additional time it'll be
10133 * because the RX Timer Callback is being fired on its regular
10136 * If the stall is below our Potential Hung Ingress Queue
10137 * Warning Threshold, continue.
10139 if (idma->idma_stalled[i] == 0) {
10140 idma->idma_stalled[i] = hz;
10141 idma->idma_warn[i] = 0;
10143 idma->idma_stalled[i] += ticks;
10144 idma->idma_warn[i] -= ticks;
10147 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
10150 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10152 if (idma->idma_warn[i] > 0)
10154 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
10156 /* Read and save the SGE IDMA State and Queue ID information.
10157 * We do this every time in case it changes across time ...
10158 * can't be too careful ...
10160 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
10161 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10162 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10164 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
10165 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10166 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10168 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
10169 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10170 i, idma->idma_qid[i], idma->idma_state[i],
10171 idma->idma_stalled[i] / hz,
10173 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10178 * t4_load_cfg - download config file
10179 * @adap: the adapter
10180 * @cfg_data: the cfg text file to write
10181 * @size: text file size
10183 * Write the supplied config text file to the card's serial flash.
10185 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10187 int ret, i, n, cfg_addr;
10189 unsigned int flash_cfg_start_sec;
10190 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10192 cfg_addr = t4_flash_cfg_addr(adap);
10197 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10199 if (size > FLASH_CFG_MAX_SIZE) {
10200 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10201 FLASH_CFG_MAX_SIZE);
10205 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
10207 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10208 flash_cfg_start_sec + i - 1);
10209 /* If size == 0 then we're simply erasing the FLASH sectors associated
10210 * with the on-adapter Firmware Configuration File.
10212 if (ret || size == 0)
10215 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10216 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10217 if ((size - i) < SF_PAGE_SIZE)
10221 ret = t4_write_flash(adap, addr, n, cfg_data, true);
10225 addr += SF_PAGE_SIZE;
10226 cfg_data += SF_PAGE_SIZE;
10231 dev_err(adap->pdev_dev, "config file %s failed %d\n",
10232 (size == 0 ? "clear" : "download"), ret);
10237 * t4_set_vf_mac - Set MAC address for the specified VF
10238 * @adapter: The adapter
10239 * @vf: one of the VFs instantiated by the specified PF
10240 * @naddr: the number of MAC addresses
10241 * @addr: the MAC address(es) to be set to the specified VF
10243 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
10244 unsigned int naddr, u8 *addr)
10246 struct fw_acl_mac_cmd cmd;
10248 memset(&cmd, 0, sizeof(cmd));
10249 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
10252 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
10253 FW_ACL_MAC_CMD_VFN_V(vf));
10255 /* Note: Do not enable the ACL */
10256 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10259 switch (adapter->pf) {
10261 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10264 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10267 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10270 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10274 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10278 * t4_read_pace_tbl - read the pace table
10279 * @adap: the adapter
10280 * @pace_vals: holds the returned values
10282 * Returns the values of TP's pace table in microseconds.
10284 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10288 for (i = 0; i < NTX_SCHED; i++) {
10289 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10290 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10291 pace_vals[i] = dack_ticks_to_usec(adap, v);
10296 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10297 * @adap: the adapter
10298 * @sched: the scheduler index
10299 * @kbps: the byte rate in Kbps
10300 * @ipg: the interpacket delay in tenths of nanoseconds
10301 * @sleep_ok: if true we may sleep while awaiting command completion
10303 * Return the current configuration of a HW Tx scheduler.
10305 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10306 unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10308 unsigned int v, addr, bpt, cpt;
10311 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10312 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10315 bpt = (v >> 8) & 0xff;
10318 *kbps = 0; /* scheduler disabled */
10320 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10321 *kbps = (v * bpt) / 125;
10325 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10326 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10330 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10334 /* t4_sge_ctxt_rd - read an SGE context through FW
10335 * @adap: the adapter
10336 * @mbox: mailbox to use for the FW command
10337 * @cid: the context id
10338 * @ctype: the context type
10339 * @data: where to store the context data
10341 * Issues a FW command through the given mailbox to read an SGE context.
10343 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10344 enum ctxt_type ctype, u32 *data)
10346 struct fw_ldst_cmd c;
10349 if (ctype == CTXT_FLM)
10350 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10352 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10354 memset(&c, 0, sizeof(c));
10355 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10356 FW_CMD_REQUEST_F | FW_CMD_READ_F |
10357 FW_LDST_CMD_ADDRSPACE_V(ret));
10358 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10359 c.u.idctxt.physid = cpu_to_be32(cid);
10361 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10363 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10364 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10365 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10366 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10367 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10368 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10374 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10375 * @adap: the adapter
10376 * @cid: the context id
10377 * @ctype: the context type
10378 * @data: where to store the context data
10380 * Reads an SGE context directly, bypassing FW. This is only for
10381 * debugging when FW is unavailable.
10383 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10384 enum ctxt_type ctype, u32 *data)
10388 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10389 ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10391 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10392 *data++ = t4_read_reg(adap, i);
10396 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
10397 u8 rateunit, u8 ratemode, u8 channel, u8 class,
10398 u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
10401 struct fw_sched_cmd cmd;
10403 memset(&cmd, 0, sizeof(cmd));
10404 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10407 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10409 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10410 cmd.u.params.type = type;
10411 cmd.u.params.level = level;
10412 cmd.u.params.mode = mode;
10413 cmd.u.params.ch = channel;
10414 cmd.u.params.cl = class;
10415 cmd.u.params.unit = rateunit;
10416 cmd.u.params.rate = ratemode;
10417 cmd.u.params.min = cpu_to_be32(minrate);
10418 cmd.u.params.max = cpu_to_be32(maxrate);
10419 cmd.u.params.weight = cpu_to_be16(weight);
10420 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10421 cmd.u.params.burstsize = cpu_to_be16(burstsize);
10423 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10428 * t4_i2c_rd - read I2C data from adapter
10429 * @adap: the adapter
10430 * @mbox: mailbox to use for the FW command
10431 * @port: Port number if per-port device; <0 if not
10432 * @devid: per-port device ID or absolute device ID
10433 * @offset: byte offset into device I2C space
10434 * @len: byte length of I2C space data
10435 * @buf: buffer in which to return I2C data
10437 * Reads the I2C data from the indicated device and location.
10439 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10440 unsigned int devid, unsigned int offset,
10441 unsigned int len, u8 *buf)
10443 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10444 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10447 if (len > I2C_PAGE_SIZE)
10450 /* Dont allow reads that spans multiple pages */
10451 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10454 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10455 ldst_cmd.op_to_addrspace =
10456 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10459 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10460 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10461 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10462 ldst_cmd.u.i2c.did = devid;
10465 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10467 ldst_cmd.u.i2c.boffset = offset;
10468 ldst_cmd.u.i2c.blen = i2c_len;
10470 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10475 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10485 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10486 * @adap: the adapter
10487 * @mbox: mailbox to use for the FW command
10488 * @vf: one of the VFs instantiated by the specified PF
10489 * @vlan: The vlanid to be set
10491 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10494 struct fw_acl_vlan_cmd vlan_cmd;
10495 unsigned int enable;
10497 enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10498 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10499 vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10503 FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10504 FW_ACL_VLAN_CMD_VFN_V(vf));
10505 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10506 /* Drop all packets that donot match vlan id */
10507 vlan_cmd.dropnovlan_fm = (enable
10508 ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F |
10509 FW_ACL_VLAN_CMD_FM_F) : 0);
10511 vlan_cmd.nvlan = 1;
10512 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10515 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10519 * modify_device_id - Modifies the device ID of the Boot BIOS image
10520 * @device_id: the device ID to write.
10521 * @boot_data: the boot image to modify.
10523 * Write the supplied device ID to the boot BIOS image.
10525 static void modify_device_id(int device_id, u8 *boot_data)
10527 struct cxgb4_pcir_data *pcir_header;
10528 struct legacy_pci_rom_hdr *header;
10529 u8 *cur_header = boot_data;
10532 /* Loop through all chained images and change the device ID's */
10534 header = (struct legacy_pci_rom_hdr *)cur_header;
10535 pcir_offset = le16_to_cpu(header->pcir_offset);
10536 pcir_header = (struct cxgb4_pcir_data *)(cur_header +
10540 * Only modify the Device ID if code type is Legacy or HP.
10541 * 0x00: Okay to modify
10542 * 0x01: FCODE. Do not modify
10543 * 0x03: Okay to modify
10544 * 0x04-0xFF: Do not modify
10546 if (pcir_header->code_type == CXGB4_HDR_CODE1) {
10551 * Modify Device ID to match current adatper
10553 pcir_header->device_id = cpu_to_le16(device_id);
10556 * Set checksum temporarily to 0.
10557 * We will recalculate it later.
10559 header->cksum = 0x0;
10562 * Calculate and update checksum
10564 for (i = 0; i < (header->size512 * 512); i++)
10565 csum += cur_header[i];
10568 * Invert summed value to create the checksum
10569 * Writing new checksum value directly to the boot data
10571 cur_header[7] = -csum;
10573 } else if (pcir_header->code_type == CXGB4_HDR_CODE2) {
10575 * Modify Device ID to match current adatper
10577 pcir_header->device_id = cpu_to_le16(device_id);
10581 * Move header pointer up to the next image in the ROM.
10583 cur_header += header->size512 * 512;
10584 } while (!(pcir_header->indicator & CXGB4_HDR_INDI));
10588 * t4_load_boot - download boot flash
10589 * @adap: the adapter
10590 * @boot_data: the boot image to write
10591 * @boot_addr: offset in flash to write boot_data
10592 * @size: image size
10594 * Write the supplied boot image to the card's serial flash.
10595 * The boot image has the following sections: a 28-byte header and the
10598 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10599 unsigned int boot_addr, unsigned int size)
10601 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10602 unsigned int boot_sector = (boot_addr * 1024);
10603 struct cxgb4_pci_exp_rom_header *header;
10604 struct cxgb4_pcir_data *pcir_header;
10611 * Make sure the boot image does not encroach on the firmware region
10613 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10614 dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
10618 /* Get boot header */
10619 header = (struct cxgb4_pci_exp_rom_header *)boot_data;
10620 pcir_offset = le16_to_cpu(header->pcir_offset);
10621 /* PCIR Data Structure */
10622 pcir_header = (struct cxgb4_pcir_data *)&boot_data[pcir_offset];
10625 * Perform some primitive sanity testing to avoid accidentally
10626 * writing garbage over the boot sectors. We ought to check for
10627 * more but it's not worth it for now ...
10629 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10630 dev_err(adap->pdev_dev, "boot image too small/large\n");
10634 if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) {
10635 dev_err(adap->pdev_dev, "Boot image missing signature\n");
10639 /* Check PCI header signature */
10640 if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) {
10641 dev_err(adap->pdev_dev, "PCI header missing signature\n");
10645 /* Check Vendor ID matches Chelsio ID*/
10646 if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) {
10647 dev_err(adap->pdev_dev, "Vendor ID missing signature\n");
10652 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10653 * and Boot configuration data sections. These 3 boot sections span
10654 * sectors 0 to 7 in flash and live right before the FW image location.
10656 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, sf_sec_size);
10657 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10658 (boot_sector >> 16) + i - 1);
10661 * If size == 0 then we're simply erasing the FLASH sectors associated
10662 * with the on-adapter option ROM file
10664 if (ret || size == 0)
10666 /* Retrieve adapter's device ID */
10667 pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id);
10668 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10669 device_id = device_id & 0xf0ff;
10671 /* Check PCIE Device ID */
10672 if (le16_to_cpu(pcir_header->device_id) != device_id) {
10674 * Change the device ID in the Boot BIOS image to match
10675 * the Device ID of the current adapter.
10677 modify_device_id(device_id, boot_data);
10681 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10682 * we finish copying the rest of the boot image. This will ensure
10683 * that the BIOS boot header will only be written if the boot image
10684 * was written in full.
10686 addr = boot_sector;
10687 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10688 addr += SF_PAGE_SIZE;
10689 boot_data += SF_PAGE_SIZE;
10690 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data,
10696 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10697 (const u8 *)header, false);
10701 dev_err(adap->pdev_dev, "boot image load failed, error %d\n",
10707 * t4_flash_bootcfg_addr - return the address of the flash
10708 * optionrom configuration
10709 * @adapter: the adapter
10711 * Return the address within the flash where the OptionROM Configuration
10712 * is stored, or an error if the device FLASH is too small to contain
10713 * a OptionROM Configuration.
10715 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10718 * If the device FLASH isn't large enough to hold a Firmware
10719 * Configuration File, return an error.
10721 if (adapter->params.sf_size <
10722 FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10725 return FLASH_BOOTCFG_START;
10728 int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10730 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10731 struct cxgb4_bootcfg_data *header;
10732 unsigned int flash_cfg_start_sec;
10733 unsigned int addr, npad;
10734 int ret, i, n, cfg_addr;
10736 cfg_addr = t4_flash_bootcfg_addr(adap);
10741 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10743 if (size > FLASH_BOOTCFG_MAX_SIZE) {
10744 dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
10745 FLASH_BOOTCFG_MAX_SIZE);
10749 header = (struct cxgb4_bootcfg_data *)cfg_data;
10750 if (le16_to_cpu(header->signature) != BOOT_CFG_SIG) {
10751 dev_err(adap->pdev_dev, "Wrong bootcfg signature\n");
10756 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,
10758 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10759 flash_cfg_start_sec + i - 1);
10762 * If size == 0 then we're simply erasing the FLASH sectors associated
10763 * with the on-adapter OptionROM Configuration File.
10765 if (ret || size == 0)
10768 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10769 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10770 n = min_t(u32, size - i, SF_PAGE_SIZE);
10772 ret = t4_write_flash(adap, addr, n, cfg_data, false);
10776 addr += SF_PAGE_SIZE;
10777 cfg_data += SF_PAGE_SIZE;
10780 npad = ((size + 4 - 1) & ~3) - size;
10781 for (i = 0; i < npad; i++) {
10784 ret = t4_write_flash(adap, cfg_addr + size + i, 1, &data,
10792 dev_err(adap->pdev_dev, "boot config data %s failed %d\n",
10793 (size == 0 ? "clear" : "download"), ret);