drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 /**
 228  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 229  *      @adapter: the adapter
 230  *      @cmd: the Firmware Mailbox Command or Reply
 231  *      @size: command length in bytes
 232  *      @access: the time (ms) needed to access the Firmware Mailbox
 233  *      @execute: the time (ms) the command spent being executed
 234  */
 235 static void t4_record_mbox(struct adapter *adapter,
 236                            const __be64 *cmd, unsigned int size,
 237                            int access, int execute)
 238 {
 239         struct mbox_cmd_log *log = adapter->mbox_log;
 240         struct mbox_cmd *entry;
 241         int i;
 242
 243         entry = mbox_cmd_log_entry(log, log->cursor++);
 244         if (log->cursor == log->size)
 245                 log->cursor = 0;
 246
 247         for (i = 0; i < size / 8; i++)
 248                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 249         while (i < MBOX_LEN / 8)
 250                 entry->cmd[i++] = 0;
 251         entry->timestamp = jiffies;
 252         entry->seqno = log->seqno++;
 253         entry->access = access;
 254         entry->execute = execute;
 255 }
 256
 257 /**
 258  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 259  *      @adap: the adapter
 260  *      @mbox: index of the mailbox to use
 261  *      @cmd: the command to write
 262  *      @size: command length in bytes
 263  *      @rpl: where to optionally store the reply
 264  *      @sleep_ok: if true we may sleep while awaiting command completion
 265  *      @timeout: time to wait for command to finish before timing out
 266  *
 267  *      Sends the given command to FW through the selected mailbox and waits
 268  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 269  *      store the FW's reply to the command.  The command and its optional
 270  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 271  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 272  *      the response.  If sleeping is allowed we use progressive backoff
 273  *      otherwise we spin.
 274  *
 275  *      The return value is 0 on success or a negative errno on failure.  A
 276  *      failure can happen either because we are not able to execute the
 277  *      command or FW executes it but signals an error.  In the latter case
 278  *      the return value is the error code indicated by FW (negated).
 279  */
 280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 281                             int size, void *rpl, bool sleep_ok, int timeout)
 282 {
 283         static const int delay[] = {
 284                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 285         };
 286
 287         struct mbox_list entry;
 288         u16 access = 0;
 289         u16 execute = 0;
 290         u32 v;
 291         u64 res;
 292         int i, ms, delay_idx, ret;
 293         const __be64 *p = cmd;
 294         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 295         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 296         __be64 cmd_rpl[MBOX_LEN / 8];
 297         u32 pcie_fw;
 298
 299         if ((size & 15) || size > MBOX_LEN)
 300                 return -EINVAL;
 301
 302         /*
 303          * If the device is off-line, as in EEH, commands will time out.
 304          * Fail them early so we don't waste time waiting.
 305          */
 306         if (adap->pdev->error_state != pci_channel_io_normal)
 307                 return -EIO;
 308
 309         /* If we have a negative timeout, that implies that we can't sleep. */
 310         if (timeout < 0) {
 311                 sleep_ok = false;
 312                 timeout = -timeout;
 313         }
 314
 315         /* Queue ourselves onto the mailbox access list.  When our entry is at
 316          * the front of the list, we have rights to access the mailbox.  So we
 317          * wait [for a while] till we're at the front [or bail out with an
 318          * EBUSY] ...
 319          */
 320         spin_lock(&adap->mbox_lock);
 321         list_add_tail(&entry.list, &adap->mlist.list);
 322         spin_unlock(&adap->mbox_lock);
 323
 324         delay_idx = 0;
 325         ms = delay[0];
 326
 327         for (i = 0; ; i += ms) {
 328                 /* If we've waited too long, return a busy indication.  This
 329                  * really ought to be based on our initial position in the
 330                  * mailbox access list but this is a start.  We very rearely
 331                  * contend on access to the mailbox ...
 332                  */
 333                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 334                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 335                         spin_lock(&adap->mbox_lock);
 336                         list_del(&entry.list);
 337                         spin_unlock(&adap->mbox_lock);
 338                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 339                         t4_record_mbox(adap, cmd, size, access, ret);
 340                         return ret;
 341                 }
 342
 343                 /* If we're at the head, break out and start the mailbox
 344                  * protocol.
 345                  */
 346                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 347                                      list) == &entry)
 348                         break;
 349
 350                 /* Delay for a bit before checking again ... */
 351                 if (sleep_ok) {
 352                         ms = delay[delay_idx];  /* last element may repeat */
 353                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 354                                 delay_idx++;
 355                         msleep(ms);
 356                 } else {
 357                         mdelay(ms);
 358                 }
 359         }
 360
 361         /* Loop trying to get ownership of the mailbox.  Return an error
 362          * if we can't gain ownership.
 363          */
 364         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 365         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 366                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         if (v != MBOX_OWNER_DRV) {
 368                 spin_lock(&adap->mbox_lock);
 369                 list_del(&entry.list);
 370                 spin_unlock(&adap->mbox_lock);
 371                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 372                 t4_record_mbox(adap, cmd, size, access, ret);
 373                 return ret;
 374         }
 375
 376         /* Copy in the new mailbox command and send it on its way ... */
 377         t4_record_mbox(adap, cmd, size, access, 0);
 378         for (i = 0; i < size; i += 8)
 379                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 380
 381         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 382         t4_read_reg(adap, ctl_reg);          /* flush write */
 383
 384         delay_idx = 0;
 385         ms = delay[0];
 386
 387         for (i = 0;
 388              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 389              i < timeout;
 390              i += ms) {
 391                 if (sleep_ok) {
 392                         ms = delay[delay_idx];  /* last element may repeat */
 393                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 394                                 delay_idx++;
 395                         msleep(ms);
 396                 } else
 397                         mdelay(ms);
 398
 399                 v = t4_read_reg(adap, ctl_reg);
 400                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 401                         if (!(v & MBMSGVALID_F)) {
 402                                 t4_write_reg(adap, ctl_reg, 0);
 403                                 continue;
 404                         }
 405
 406                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 407                         res = be64_to_cpu(cmd_rpl[0]);
 408
 409                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 410                                 fw_asrt(adap, data_reg);
 411                                 res = FW_CMD_RETVAL_V(EIO);
 412                         } else if (rpl) {
 413                                 memcpy(rpl, cmd_rpl, size);
 414                         }
 415
 416                         t4_write_reg(adap, ctl_reg, 0);
 417
 418                         execute = i + ms;
 419                         t4_record_mbox(adap, cmd_rpl,
 420                                        MBOX_LEN, access, execute);
 421                         spin_lock(&adap->mbox_lock);
 422                         list_del(&entry.list);
 423                         spin_unlock(&adap->mbox_lock);
 424                         return -FW_CMD_RETVAL_G((int)res);
 425                 }
 426         }
 427
 428         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 429         t4_record_mbox(adap, cmd, size, access, ret);
 430         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 431                 *(const u8 *)cmd, mbox);
 432         t4_report_fw_error(adap);
 433         spin_lock(&adap->mbox_lock);
 434         list_del(&entry.list);
 435         spin_unlock(&adap->mbox_lock);
 436         t4_fatal_err(adap);
 437         return ret;
 438 }
 439
 440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 441                     void *rpl, bool sleep_ok)
 442 {
 443         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 444                                        FW_CMD_MAX_TIMEOUT);
 445 }
 446
 447 static int t4_edc_err_read(struct adapter *adap, int idx)
 448 {
 449         u32 edc_ecc_err_addr_reg;
 450         u32 rdata_reg;
 451
 452         if (is_t4(adap->params.chip)) {
 453                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 454                 return 0;
 455         }
 456         if (idx != 0 && idx != 1) {
 457                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 458                 return 0;
 459         }
 460
 461         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 462         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 463
 464         CH_WARN(adap,
 465                 "edc%d err addr 0x%x: 0x%x.\n",
 466                 idx, edc_ecc_err_addr_reg,
 467                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 468         CH_WARN(adap,
 469                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 470                 rdata_reg,
 471                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 472                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 480
 481         return 0;
 482 }
 483
 484 /**
 485  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 486  *      @adap: the adapter
 487  *      @win: PCI-E Memory Window to use
 488  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 489  *      @addr: address within indicated memory type
 490  *      @len: amount of memory to transfer
 491  *      @hbuf: host memory buffer
 492  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 493  *
 494  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 495  *      firmware memory address and host buffer must be aligned on 32-bit
 496  *      boudaries; the length may be arbitrary.  The memory is transferred as
 497  *      a raw byte sequence from/to the firmware's memory.  If this memory
 498  *      contains data structures which contain multi-byte integers, it's the
 499  *      caller's responsibility to perform appropriate byte order conversions.
 500  */
 501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 502                  u32 len, void *hbuf, int dir)
 503 {
 504         u32 pos, offset, resid, memoffset;
 505         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 506         u32 *buf;
 507
 508         /* Argument sanity checks ...
 509          */
 510         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 511                 return -EINVAL;
 512         buf = (u32 *)hbuf;
 513
 514         /* It's convenient to be able to handle lengths which aren't a
 515          * multiple of 32-bits because we often end up transferring files to
 516          * the firmware.  So we'll handle that by normalizing the length here
 517          * and then handling any residual transfer at the end.
 518          */
 519         resid = len & 0x3;
 520         len -= resid;
 521
 522         /* Offset into the region of memory which is being accessed
 523          * MEM_EDC0 = 0
 524          * MEM_EDC1 = 1
 525          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 526          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 527          */
 528         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 529         if (mtype != MEM_MC1)
 530                 memoffset = (mtype * (edc_size * 1024 * 1024));
 531         else {
 532                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 533                                                       MA_EXT_MEMORY0_BAR_A));
 534                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 535         }
 536
 537         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 538         addr = addr + memoffset;
 539
 540         /* Each PCI-E Memory Window is programmed with a window size -- or
 541          * "aperture" -- which controls the granularity of its mapping onto
 542          * adapter memory.  We need to grab that aperture in order to know
 543          * how to use the specified window.  The window is also programmed
 544          * with the base address of the Memory Window in BAR0's address
 545          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 546          * the address is relative to BAR0.
 547          */
 548         mem_reg = t4_read_reg(adap,
 549                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 550                                                   win));
 551         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 552         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 553         if (is_t4(adap->params.chip))
 554                 mem_base -= adap->t4_bar0;
 555         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 556
 557         /* Calculate our initial PCI-E Memory Window Position and Offset into
 558          * that Window.
 559          */
 560         pos = addr & ~(mem_aperture-1);
 561         offset = addr - pos;
 562
 563         /* Set up initial PCI-E Memory Window to cover the start of our
 564          * transfer.  (Read it back to ensure that changes propagate before we
 565          * attempt to use the new value.)
 566          */
 567         t4_write_reg(adap,
 568                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 569                      pos | win_pf);
 570         t4_read_reg(adap,
 571                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 572
 573         /* Transfer data to/from the adapter as long as there's an integral
 574          * number of 32-bit transfers to complete.
 575          *
 576          * A note on Endianness issues:
 577          *
 578          * The "register" reads and writes below from/to the PCI-E Memory
 579          * Window invoke the standard adapter Big-Endian to PCI-E Link
 580          * Little-Endian "swizzel."  As a result, if we have the following
 581          * data in adapter memory:
 582          *
 583          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 584          *     Address:      i+0  i+1  i+2  i+3
 585          *
 586          * Then a read of the adapter memory via the PCI-E Memory Window
 587          * will yield:
 588          *
 589          *     x = readl(i)
 590          *         31                  0
 591          *         [ b3 | b2 | b1 | b0 ]
 592          *
 593          * If this value is stored into local memory on a Little-Endian system
 594          * it will show up correctly in local memory as:
 595          *
 596          *     ( ..., b0, b1, b2, b3, ... )
 597          *
 598          * But on a Big-Endian system, the store will show up in memory
 599          * incorrectly swizzled as:
 600          *
 601          *     ( ..., b3, b2, b1, b0, ... )
 602          *
 603          * So we need to account for this in the reads and writes to the
 604          * PCI-E Memory Window below by undoing the register read/write
 605          * swizzels.
 606          */
 607         while (len > 0) {
 608                 if (dir == T4_MEMORY_READ)
 609                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 610                                                 mem_base + offset));
 611                 else
 612                         t4_write_reg(adap, mem_base + offset,
 613                                      (__force u32)cpu_to_le32(*buf++));
 614                 offset += sizeof(__be32);
 615                 len -= sizeof(__be32);
 616
 617                 /* If we've reached the end of our current window aperture,
 618                  * move the PCI-E Memory Window on to the next.  Note that
 619                  * doing this here after "len" may be 0 allows us to set up
 620                  * the PCI-E Memory Window for a possible final residual
 621                  * transfer below ...
 622                  */
 623                 if (offset == mem_aperture) {
 624                         pos += mem_aperture;
 625                         offset = 0;
 626                         t4_write_reg(adap,
 627                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 628                                                     win), pos | win_pf);
 629                         t4_read_reg(adap,
 630                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 631                                                     win));
 632                 }
 633         }
 634
 635         /* If the original transfer had a length which wasn't a multiple of
 636          * 32-bits, now's where we need to finish off the transfer of the
 637          * residual amount.  The PCI-E Memory Window has already been moved
 638          * above (if necessary) to cover this final transfer.
 639          */
 640         if (resid) {
 641                 union {
 642                         u32 word;
 643                         char byte[4];
 644                 } last;
 645                 unsigned char *bp;
 646                 int i;
 647
 648                 if (dir == T4_MEMORY_READ) {
 649                         last.word = le32_to_cpu(
 650                                         (__force __le32)t4_read_reg(adap,
 651                                                 mem_base + offset));
 652                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 653                                 bp[i] = last.byte[i];
 654                 } else {
 655                         last.word = *buf;
 656                         for (i = resid; i < 4; i++)
 657                                 last.byte[i] = 0;
 658                         t4_write_reg(adap, mem_base + offset,
 659                                      (__force u32)cpu_to_le32(last.word));
 660                 }
 661         }
 662
 663         return 0;
 664 }
 665
 666 /* Return the specified PCI-E Configuration Space register from our Physical
 667  * Function.  We try first via a Firmware LDST Command since we prefer to let
 668  * the firmware own all of these registers, but if that fails we go for it
 669  * directly ourselves.
 670  */
 671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 672 {
 673         u32 val, ldst_addrspace;
 674
 675         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 676          * retrieve the specified PCI-E Configuration Space register.
 677          */
 678         struct fw_ldst_cmd ldst_cmd;
 679         int ret;
 680
 681         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 682         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 683         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 684                                                FW_CMD_REQUEST_F |
 685                                                FW_CMD_READ_F |
 686                                                ldst_addrspace);
 687         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 688         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 689         ldst_cmd.u.pcie.ctrl_to_fn =
 690                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 691         ldst_cmd.u.pcie.r = reg;
 692
 693         /* If the LDST Command succeeds, return the result, otherwise
 694          * fall through to reading it directly ourselves ...
 695          */
 696         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 697                          &ldst_cmd);
 698         if (ret == 0)
 699                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 700         else
 701                 /* Read the desired Configuration Space register via the PCI-E
 702                  * Backdoor mechanism.
 703                  */
 704                 t4_hw_pci_read_cfg4(adap, reg, &val);
 705         return val;
 706 }
 707
 708 /* Get the window based on base passed to it.
 709  * Window aperture is currently unhandled, but there is no use case for it
 710  * right now
 711  */
 712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 713                          u32 memwin_base)
 714 {
 715         u32 ret;
 716
 717         if (is_t4(adap->params.chip)) {
 718                 u32 bar0;
 719
 720                 /* Truncation intentional: we only read the bottom 32-bits of
 721                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 722                  * mechanism to read BAR0 instead of using
 723                  * pci_resource_start() because we could be operating from
 724                  * within a Virtual Machine which is trapping our accesses to
 725                  * our Configuration Space and we need to set up the PCI-E
 726                  * Memory Window decoders with the actual addresses which will
 727                  * be coming across the PCI-E link.
 728                  */
 729                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 730                 bar0 &= pci_mask;
 731                 adap->t4_bar0 = bar0;
 732
 733                 ret = bar0 + memwin_base;
 734         } else {
 735                 /* For T5, only relative offset inside the PCIe BAR is passed */
 736                 ret = memwin_base;
 737         }
 738         return ret;
 739 }
 740
 741 /* Get the default utility window (win0) used by everyone */
 742 u32 t4_get_util_window(struct adapter *adap)
 743 {
 744         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 745                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 746 }
 747
 748 /* Set up memory window for accessing adapter memory ranges.  (Read
 749  * back MA register to ensure that changes propagate before we attempt
 750  * to use the new values.)
 751  */
 752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 753 {
 754         t4_write_reg(adap,
 755                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 756                      memwin_base | BIR_V(0) |
 757                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 758         t4_read_reg(adap,
 759                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 760 }
 761
 762 /**
 763  *      t4_get_regs_len - return the size of the chips register set
 764  *      @adapter: the adapter
 765  *
 766  *      Returns the size of the chip's BAR0 register space.
 767  */
 768 unsigned int t4_get_regs_len(struct adapter *adapter)
 769 {
 770         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 771
 772         switch (chip_version) {
 773         case CHELSIO_T4:
 774                 return T4_REGMAP_SIZE;
 775
 776         case CHELSIO_T5:
 777         case CHELSIO_T6:
 778                 return T5_REGMAP_SIZE;
 779         }
 780
 781         dev_err(adapter->pdev_dev,
 782                 "Unsupported chip version %d\n", chip_version);
 783         return 0;
 784 }
 785
 786 /**
 787  *      t4_get_regs - read chip registers into provided buffer
 788  *      @adap: the adapter
 789  *      @buf: register buffer
 790  *      @buf_size: size (in bytes) of register buffer
 791  *
 792  *      If the provided register buffer isn't large enough for the chip's
 793  *      full register range, the register dump will be truncated to the
 794  *      register buffer's size.
 795  */
 796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 797 {
 798         static const unsigned int t4_reg_ranges[] = {
 799                 0x1008, 0x1108,
 800                 0x1180, 0x1184,
 801                 0x1190, 0x1194,
 802                 0x11a0, 0x11a4,
 803                 0x11b0, 0x11b4,
 804                 0x11fc, 0x123c,
 805                 0x1300, 0x173c,
 806                 0x1800, 0x18fc,
 807                 0x3000, 0x30d8,
 808                 0x30e0, 0x30e4,
 809                 0x30ec, 0x5910,
 810                 0x5920, 0x5924,
 811                 0x5960, 0x5960,
 812                 0x5968, 0x5968,
 813                 0x5970, 0x5970,
 814                 0x5978, 0x5978,
 815                 0x5980, 0x5980,
 816                 0x5988, 0x5988,
 817                 0x5990, 0x5990,
 818                 0x5998, 0x5998,
 819                 0x59a0, 0x59d4,
 820                 0x5a00, 0x5ae0,
 821                 0x5ae8, 0x5ae8,
 822                 0x5af0, 0x5af0,
 823                 0x5af8, 0x5af8,
 824                 0x6000, 0x6098,
 825                 0x6100, 0x6150,
 826                 0x6200, 0x6208,
 827                 0x6240, 0x6248,
 828                 0x6280, 0x62b0,
 829                 0x62c0, 0x6338,
 830                 0x6370, 0x638c,
 831                 0x6400, 0x643c,
 832                 0x6500, 0x6524,
 833                 0x6a00, 0x6a04,
 834                 0x6a14, 0x6a38,
 835                 0x6a60, 0x6a70,
 836                 0x6a78, 0x6a78,
 837                 0x6b00, 0x6b0c,
 838                 0x6b1c, 0x6b84,
 839                 0x6bf0, 0x6bf8,
 840                 0x6c00, 0x6c0c,
 841                 0x6c1c, 0x6c84,
 842                 0x6cf0, 0x6cf8,
 843                 0x6d00, 0x6d0c,
 844                 0x6d1c, 0x6d84,
 845                 0x6df0, 0x6df8,
 846                 0x6e00, 0x6e0c,
 847                 0x6e1c, 0x6e84,
 848                 0x6ef0, 0x6ef8,
 849                 0x6f00, 0x6f0c,
 850                 0x6f1c, 0x6f84,
 851                 0x6ff0, 0x6ff8,
 852                 0x7000, 0x700c,
 853                 0x701c, 0x7084,
 854                 0x70f0, 0x70f8,
 855                 0x7100, 0x710c,
 856                 0x711c, 0x7184,
 857                 0x71f0, 0x71f8,
 858                 0x7200, 0x720c,
 859                 0x721c, 0x7284,
 860                 0x72f0, 0x72f8,
 861                 0x7300, 0x730c,
 862                 0x731c, 0x7384,
 863                 0x73f0, 0x73f8,
 864                 0x7400, 0x7450,
 865                 0x7500, 0x7530,
 866                 0x7600, 0x760c,
 867                 0x7614, 0x761c,
 868                 0x7680, 0x76cc,
 869                 0x7700, 0x7798,
 870                 0x77c0, 0x77fc,
 871                 0x7900, 0x79fc,
 872                 0x7b00, 0x7b58,
 873                 0x7b60, 0x7b84,
 874                 0x7b8c, 0x7c38,
 875                 0x7d00, 0x7d38,
 876                 0x7d40, 0x7d80,
 877                 0x7d8c, 0x7ddc,
 878                 0x7de4, 0x7e04,
 879                 0x7e10, 0x7e1c,
 880                 0x7e24, 0x7e38,
 881                 0x7e40, 0x7e44,
 882                 0x7e4c, 0x7e78,
 883                 0x7e80, 0x7ea4,
 884                 0x7eac, 0x7edc,
 885                 0x7ee8, 0x7efc,
 886                 0x8dc0, 0x8e04,
 887                 0x8e10, 0x8e1c,
 888                 0x8e30, 0x8e78,
 889                 0x8ea0, 0x8eb8,
 890                 0x8ec0, 0x8f6c,
 891                 0x8fc0, 0x9008,
 892                 0x9010, 0x9058,
 893                 0x9060, 0x9060,
 894                 0x9068, 0x9074,
 895                 0x90fc, 0x90fc,
 896                 0x9400, 0x9408,
 897                 0x9410, 0x9458,
 898                 0x9600, 0x9600,
 899                 0x9608, 0x9638,
 900                 0x9640, 0x96bc,
 901                 0x9800, 0x9808,
 902                 0x9820, 0x983c,
 903                 0x9850, 0x9864,
 904                 0x9c00, 0x9c6c,
 905                 0x9c80, 0x9cec,
 906                 0x9d00, 0x9d6c,
 907                 0x9d80, 0x9dec,
 908                 0x9e00, 0x9e6c,
 909                 0x9e80, 0x9eec,
 910                 0x9f00, 0x9f6c,
 911                 0x9f80, 0x9fec,
 912                 0xd004, 0xd004,
 913                 0xd010, 0xd03c,
 914                 0xdfc0, 0xdfe0,
 915                 0xe000, 0xea7c,
 916                 0xf000, 0x11110,
 917                 0x11118, 0x11190,
 918                 0x19040, 0x1906c,
 919                 0x19078, 0x19080,
 920                 0x1908c, 0x190e4,
 921                 0x190f0, 0x190f8,
 922                 0x19100, 0x19110,
 923                 0x19120, 0x19124,
 924                 0x19150, 0x19194,
 925                 0x1919c, 0x191b0,
 926                 0x191d0, 0x191e8,
 927                 0x19238, 0x1924c,
 928                 0x193f8, 0x1943c,
 929                 0x1944c, 0x19474,
 930                 0x19490, 0x194e0,
 931                 0x194f0, 0x194f8,
 932                 0x19800, 0x19c08,
 933                 0x19c10, 0x19c90,
 934                 0x19ca0, 0x19ce4,
 935                 0x19cf0, 0x19d40,
 936                 0x19d50, 0x19d94,
 937                 0x19da0, 0x19de8,
 938                 0x19df0, 0x19e40,
 939                 0x19e50, 0x19e90,
 940                 0x19ea0, 0x19f4c,
 941                 0x1a000, 0x1a004,
 942                 0x1a010, 0x1a06c,
 943                 0x1a0b0, 0x1a0e4,
 944                 0x1a0ec, 0x1a0f4,
 945                 0x1a100, 0x1a108,
 946                 0x1a114, 0x1a120,
 947                 0x1a128, 0x1a130,
 948                 0x1a138, 0x1a138,
 949                 0x1a190, 0x1a1c4,
 950                 0x1a1fc, 0x1a1fc,
 951                 0x1e040, 0x1e04c,
 952                 0x1e284, 0x1e28c,
 953                 0x1e2c0, 0x1e2c0,
 954                 0x1e2e0, 0x1e2e0,
 955                 0x1e300, 0x1e384,
 956                 0x1e3c0, 0x1e3c8,
 957                 0x1e440, 0x1e44c,
 958                 0x1e684, 0x1e68c,
 959                 0x1e6c0, 0x1e6c0,
 960                 0x1e6e0, 0x1e6e0,
 961                 0x1e700, 0x1e784,
 962                 0x1e7c0, 0x1e7c8,
 963                 0x1e840, 0x1e84c,
 964                 0x1ea84, 0x1ea8c,
 965                 0x1eac0, 0x1eac0,
 966                 0x1eae0, 0x1eae0,
 967                 0x1eb00, 0x1eb84,
 968                 0x1ebc0, 0x1ebc8,
 969                 0x1ec40, 0x1ec4c,
 970                 0x1ee84, 0x1ee8c,
 971                 0x1eec0, 0x1eec0,
 972                 0x1eee0, 0x1eee0,
 973                 0x1ef00, 0x1ef84,
 974                 0x1efc0, 0x1efc8,
 975                 0x1f040, 0x1f04c,
 976                 0x1f284, 0x1f28c,
 977                 0x1f2c0, 0x1f2c0,
 978                 0x1f2e0, 0x1f2e0,
 979                 0x1f300, 0x1f384,
 980                 0x1f3c0, 0x1f3c8,
 981                 0x1f440, 0x1f44c,
 982                 0x1f684, 0x1f68c,
 983                 0x1f6c0, 0x1f6c0,
 984                 0x1f6e0, 0x1f6e0,
 985                 0x1f700, 0x1f784,
 986                 0x1f7c0, 0x1f7c8,
 987                 0x1f840, 0x1f84c,
 988                 0x1fa84, 0x1fa8c,
 989                 0x1fac0, 0x1fac0,
 990                 0x1fae0, 0x1fae0,
 991                 0x1fb00, 0x1fb84,
 992                 0x1fbc0, 0x1fbc8,
 993                 0x1fc40, 0x1fc4c,
 994                 0x1fe84, 0x1fe8c,
 995                 0x1fec0, 0x1fec0,
 996                 0x1fee0, 0x1fee0,
 997                 0x1ff00, 0x1ff84,
 998                 0x1ffc0, 0x1ffc8,
 999                 0x20000, 0x2002c,
1000                 0x20100, 0x2013c,
1001                 0x20190, 0x201a0,
1002                 0x201a8, 0x201b8,
1003                 0x201c4, 0x201c8,
1004                 0x20200, 0x20318,
1005                 0x20400, 0x204b4,
1006                 0x204c0, 0x20528,
1007                 0x20540, 0x20614,
1008                 0x21000, 0x21040,
1009                 0x2104c, 0x21060,
1010                 0x210c0, 0x210ec,
1011                 0x21200, 0x21268,
1012                 0x21270, 0x21284,
1013                 0x212fc, 0x21388,
1014                 0x21400, 0x21404,
1015                 0x21500, 0x21500,
1016                 0x21510, 0x21518,
1017                 0x2152c, 0x21530,
1018                 0x2153c, 0x2153c,
1019                 0x21550, 0x21554,
1020                 0x21600, 0x21600,
1021                 0x21608, 0x2161c,
1022                 0x21624, 0x21628,
1023                 0x21630, 0x21634,
1024                 0x2163c, 0x2163c,
1025                 0x21700, 0x2171c,
1026                 0x21780, 0x2178c,
1027                 0x21800, 0x21818,
1028                 0x21820, 0x21828,
1029                 0x21830, 0x21848,
1030                 0x21850, 0x21854,
1031                 0x21860, 0x21868,
1032                 0x21870, 0x21870,
1033                 0x21878, 0x21898,
1034                 0x218a0, 0x218a8,
1035                 0x218b0, 0x218c8,
1036                 0x218d0, 0x218d4,
1037                 0x218e0, 0x218e8,
1038                 0x218f0, 0x218f0,
1039                 0x218f8, 0x21a18,
1040                 0x21a20, 0x21a28,
1041                 0x21a30, 0x21a48,
1042                 0x21a50, 0x21a54,
1043                 0x21a60, 0x21a68,
1044                 0x21a70, 0x21a70,
1045                 0x21a78, 0x21a98,
1046                 0x21aa0, 0x21aa8,
1047                 0x21ab0, 0x21ac8,
1048                 0x21ad0, 0x21ad4,
1049                 0x21ae0, 0x21ae8,
1050                 0x21af0, 0x21af0,
1051                 0x21af8, 0x21c18,
1052                 0x21c20, 0x21c20,
1053                 0x21c28, 0x21c30,
1054                 0x21c38, 0x21c38,
1055                 0x21c80, 0x21c98,
1056                 0x21ca0, 0x21ca8,
1057                 0x21cb0, 0x21cc8,
1058                 0x21cd0, 0x21cd4,
1059                 0x21ce0, 0x21ce8,
1060                 0x21cf0, 0x21cf0,
1061                 0x21cf8, 0x21d7c,
1062                 0x21e00, 0x21e04,
1063                 0x22000, 0x2202c,
1064                 0x22100, 0x2213c,
1065                 0x22190, 0x221a0,
1066                 0x221a8, 0x221b8,
1067                 0x221c4, 0x221c8,
1068                 0x22200, 0x22318,
1069                 0x22400, 0x224b4,
1070                 0x224c0, 0x22528,
1071                 0x22540, 0x22614,
1072                 0x23000, 0x23040,
1073                 0x2304c, 0x23060,
1074                 0x230c0, 0x230ec,
1075                 0x23200, 0x23268,
1076                 0x23270, 0x23284,
1077                 0x232fc, 0x23388,
1078                 0x23400, 0x23404,
1079                 0x23500, 0x23500,
1080                 0x23510, 0x23518,
1081                 0x2352c, 0x23530,
1082                 0x2353c, 0x2353c,
1083                 0x23550, 0x23554,
1084                 0x23600, 0x23600,
1085                 0x23608, 0x2361c,
1086                 0x23624, 0x23628,
1087                 0x23630, 0x23634,
1088                 0x2363c, 0x2363c,
1089                 0x23700, 0x2371c,
1090                 0x23780, 0x2378c,
1091                 0x23800, 0x23818,
1092                 0x23820, 0x23828,
1093                 0x23830, 0x23848,
1094                 0x23850, 0x23854,
1095                 0x23860, 0x23868,
1096                 0x23870, 0x23870,
1097                 0x23878, 0x23898,
1098                 0x238a0, 0x238a8,
1099                 0x238b0, 0x238c8,
1100                 0x238d0, 0x238d4,
1101                 0x238e0, 0x238e8,
1102                 0x238f0, 0x238f0,
1103                 0x238f8, 0x23a18,
1104                 0x23a20, 0x23a28,
1105                 0x23a30, 0x23a48,
1106                 0x23a50, 0x23a54,
1107                 0x23a60, 0x23a68,
1108                 0x23a70, 0x23a70,
1109                 0x23a78, 0x23a98,
1110                 0x23aa0, 0x23aa8,
1111                 0x23ab0, 0x23ac8,
1112                 0x23ad0, 0x23ad4,
1113                 0x23ae0, 0x23ae8,
1114                 0x23af0, 0x23af0,
1115                 0x23af8, 0x23c18,
1116                 0x23c20, 0x23c20,
1117                 0x23c28, 0x23c30,
1118                 0x23c38, 0x23c38,
1119                 0x23c80, 0x23c98,
1120                 0x23ca0, 0x23ca8,
1121                 0x23cb0, 0x23cc8,
1122                 0x23cd0, 0x23cd4,
1123                 0x23ce0, 0x23ce8,
1124                 0x23cf0, 0x23cf0,
1125                 0x23cf8, 0x23d7c,
1126                 0x23e00, 0x23e04,
1127                 0x24000, 0x2402c,
1128                 0x24100, 0x2413c,
1129                 0x24190, 0x241a0,
1130                 0x241a8, 0x241b8,
1131                 0x241c4, 0x241c8,
1132                 0x24200, 0x24318,
1133                 0x24400, 0x244b4,
1134                 0x244c0, 0x24528,
1135                 0x24540, 0x24614,
1136                 0x25000, 0x25040,
1137                 0x2504c, 0x25060,
1138                 0x250c0, 0x250ec,
1139                 0x25200, 0x25268,
1140                 0x25270, 0x25284,
1141                 0x252fc, 0x25388,
1142                 0x25400, 0x25404,
1143                 0x25500, 0x25500,
1144                 0x25510, 0x25518,
1145                 0x2552c, 0x25530,
1146                 0x2553c, 0x2553c,
1147                 0x25550, 0x25554,
1148                 0x25600, 0x25600,
1149                 0x25608, 0x2561c,
1150                 0x25624, 0x25628,
1151                 0x25630, 0x25634,
1152                 0x2563c, 0x2563c,
1153                 0x25700, 0x2571c,
1154                 0x25780, 0x2578c,
1155                 0x25800, 0x25818,
1156                 0x25820, 0x25828,
1157                 0x25830, 0x25848,
1158                 0x25850, 0x25854,
1159                 0x25860, 0x25868,
1160                 0x25870, 0x25870,
1161                 0x25878, 0x25898,
1162                 0x258a0, 0x258a8,
1163                 0x258b0, 0x258c8,
1164                 0x258d0, 0x258d4,
1165                 0x258e0, 0x258e8,
1166                 0x258f0, 0x258f0,
1167                 0x258f8, 0x25a18,
1168                 0x25a20, 0x25a28,
1169                 0x25a30, 0x25a48,
1170                 0x25a50, 0x25a54,
1171                 0x25a60, 0x25a68,
1172                 0x25a70, 0x25a70,
1173                 0x25a78, 0x25a98,
1174                 0x25aa0, 0x25aa8,
1175                 0x25ab0, 0x25ac8,
1176                 0x25ad0, 0x25ad4,
1177                 0x25ae0, 0x25ae8,
1178                 0x25af0, 0x25af0,
1179                 0x25af8, 0x25c18,
1180                 0x25c20, 0x25c20,
1181                 0x25c28, 0x25c30,
1182                 0x25c38, 0x25c38,
1183                 0x25c80, 0x25c98,
1184                 0x25ca0, 0x25ca8,
1185                 0x25cb0, 0x25cc8,
1186                 0x25cd0, 0x25cd4,
1187                 0x25ce0, 0x25ce8,
1188                 0x25cf0, 0x25cf0,
1189                 0x25cf8, 0x25d7c,
1190                 0x25e00, 0x25e04,
1191                 0x26000, 0x2602c,
1192                 0x26100, 0x2613c,
1193                 0x26190, 0x261a0,
1194                 0x261a8, 0x261b8,
1195                 0x261c4, 0x261c8,
1196                 0x26200, 0x26318,
1197                 0x26400, 0x264b4,
1198                 0x264c0, 0x26528,
1199                 0x26540, 0x26614,
1200                 0x27000, 0x27040,
1201                 0x2704c, 0x27060,
1202                 0x270c0, 0x270ec,
1203                 0x27200, 0x27268,
1204                 0x27270, 0x27284,
1205                 0x272fc, 0x27388,
1206                 0x27400, 0x27404,
1207                 0x27500, 0x27500,
1208                 0x27510, 0x27518,
1209                 0x2752c, 0x27530,
1210                 0x2753c, 0x2753c,
1211                 0x27550, 0x27554,
1212                 0x27600, 0x27600,
1213                 0x27608, 0x2761c,
1214                 0x27624, 0x27628,
1215                 0x27630, 0x27634,
1216                 0x2763c, 0x2763c,
1217                 0x27700, 0x2771c,
1218                 0x27780, 0x2778c,
1219                 0x27800, 0x27818,
1220                 0x27820, 0x27828,
1221                 0x27830, 0x27848,
1222                 0x27850, 0x27854,
1223                 0x27860, 0x27868,
1224                 0x27870, 0x27870,
1225                 0x27878, 0x27898,
1226                 0x278a0, 0x278a8,
1227                 0x278b0, 0x278c8,
1228                 0x278d0, 0x278d4,
1229                 0x278e0, 0x278e8,
1230                 0x278f0, 0x278f0,
1231                 0x278f8, 0x27a18,
1232                 0x27a20, 0x27a28,
1233                 0x27a30, 0x27a48,
1234                 0x27a50, 0x27a54,
1235                 0x27a60, 0x27a68,
1236                 0x27a70, 0x27a70,
1237                 0x27a78, 0x27a98,
1238                 0x27aa0, 0x27aa8,
1239                 0x27ab0, 0x27ac8,
1240                 0x27ad0, 0x27ad4,
1241                 0x27ae0, 0x27ae8,
1242                 0x27af0, 0x27af0,
1243                 0x27af8, 0x27c18,
1244                 0x27c20, 0x27c20,
1245                 0x27c28, 0x27c30,
1246                 0x27c38, 0x27c38,
1247                 0x27c80, 0x27c98,
1248                 0x27ca0, 0x27ca8,
1249                 0x27cb0, 0x27cc8,
1250                 0x27cd0, 0x27cd4,
1251                 0x27ce0, 0x27ce8,
1252                 0x27cf0, 0x27cf0,
1253                 0x27cf8, 0x27d7c,
1254                 0x27e00, 0x27e04,
1255         };
1256
1257         static const unsigned int t5_reg_ranges[] = {
1258                 0x1008, 0x10c0,
1259                 0x10cc, 0x10f8,
1260                 0x1100, 0x1100,
1261                 0x110c, 0x1148,
1262                 0x1180, 0x1184,
1263                 0x1190, 0x1194,
1264                 0x11a0, 0x11a4,
1265                 0x11b0, 0x11b4,
1266                 0x11fc, 0x123c,
1267                 0x1280, 0x173c,
1268                 0x1800, 0x18fc,
1269                 0x3000, 0x3028,
1270                 0x3060, 0x30b0,
1271                 0x30b8, 0x30d8,
1272                 0x30e0, 0x30fc,
1273                 0x3140, 0x357c,
1274                 0x35a8, 0x35cc,
1275                 0x35ec, 0x35ec,
1276                 0x3600, 0x5624,
1277                 0x56cc, 0x56ec,
1278                 0x56f4, 0x5720,
1279                 0x5728, 0x575c,
1280                 0x580c, 0x5814,
1281                 0x5890, 0x589c,
1282                 0x58a4, 0x58ac,
1283                 0x58b8, 0x58bc,
1284                 0x5940, 0x59c8,
1285                 0x59d0, 0x59dc,
1286                 0x59fc, 0x5a18,
1287                 0x5a60, 0x5a70,
1288                 0x5a80, 0x5a9c,
1289                 0x5b94, 0x5bfc,
1290                 0x6000, 0x6020,
1291                 0x6028, 0x6040,
1292                 0x6058, 0x609c,
1293                 0x60a8, 0x614c,
1294                 0x7700, 0x7798,
1295                 0x77c0, 0x78fc,
1296                 0x7b00, 0x7b58,
1297                 0x7b60, 0x7b84,
1298                 0x7b8c, 0x7c54,
1299                 0x7d00, 0x7d38,
1300                 0x7d40, 0x7d80,
1301                 0x7d8c, 0x7ddc,
1302                 0x7de4, 0x7e04,
1303                 0x7e10, 0x7e1c,
1304                 0x7e24, 0x7e38,
1305                 0x7e40, 0x7e44,
1306                 0x7e4c, 0x7e78,
1307                 0x7e80, 0x7edc,
1308                 0x7ee8, 0x7efc,
1309                 0x8dc0, 0x8de0,
1310                 0x8df8, 0x8e04,
1311                 0x8e10, 0x8e84,
1312                 0x8ea0, 0x8f84,
1313                 0x8fc0, 0x9058,
1314                 0x9060, 0x9060,
1315                 0x9068, 0x90f8,
1316                 0x9400, 0x9408,
1317                 0x9410, 0x9470,
1318                 0x9600, 0x9600,
1319                 0x9608, 0x9638,
1320                 0x9640, 0x96f4,
1321                 0x9800, 0x9808,
1322                 0x9820, 0x983c,
1323                 0x9850, 0x9864,
1324                 0x9c00, 0x9c6c,
1325                 0x9c80, 0x9cec,
1326                 0x9d00, 0x9d6c,
1327                 0x9d80, 0x9dec,
1328                 0x9e00, 0x9e6c,
1329                 0x9e80, 0x9eec,
1330                 0x9f00, 0x9f6c,
1331                 0x9f80, 0xa020,
1332                 0xd004, 0xd004,
1333                 0xd010, 0xd03c,
1334                 0xdfc0, 0xdfe0,
1335                 0xe000, 0x1106c,
1336                 0x11074, 0x11088,
1337                 0x1109c, 0x1117c,
1338                 0x11190, 0x11204,
1339                 0x19040, 0x1906c,
1340                 0x19078, 0x19080,
1341                 0x1908c, 0x190e8,
1342                 0x190f0, 0x190f8,
1343                 0x19100, 0x19110,
1344                 0x19120, 0x19124,
1345                 0x19150, 0x19194,
1346                 0x1919c, 0x191b0,
1347                 0x191d0, 0x191e8,
1348                 0x19238, 0x19290,
1349                 0x193f8, 0x19428,
1350                 0x19430, 0x19444,
1351                 0x1944c, 0x1946c,
1352                 0x19474, 0x19474,
1353                 0x19490, 0x194cc,
1354                 0x194f0, 0x194f8,
1355                 0x19c00, 0x19c08,
1356                 0x19c10, 0x19c60,
1357                 0x19c94, 0x19ce4,
1358                 0x19cf0, 0x19d40,
1359                 0x19d50, 0x19d94,
1360                 0x19da0, 0x19de8,
1361                 0x19df0, 0x19e10,
1362                 0x19e50, 0x19e90,
1363                 0x19ea0, 0x19f24,
1364                 0x19f34, 0x19f34,
1365                 0x19f40, 0x19f50,
1366                 0x19f90, 0x19fb4,
1367                 0x19fc4, 0x19fe4,
1368                 0x1a000, 0x1a004,
1369                 0x1a010, 0x1a06c,
1370                 0x1a0b0, 0x1a0e4,
1371                 0x1a0ec, 0x1a0f8,
1372                 0x1a100, 0x1a108,
1373                 0x1a114, 0x1a120,
1374                 0x1a128, 0x1a130,
1375                 0x1a138, 0x1a138,
1376                 0x1a190, 0x1a1c4,
1377                 0x1a1fc, 0x1a1fc,
1378                 0x1e008, 0x1e00c,
1379                 0x1e040, 0x1e044,
1380                 0x1e04c, 0x1e04c,
1381                 0x1e284, 0x1e290,
1382                 0x1e2c0, 0x1e2c0,
1383                 0x1e2e0, 0x1e2e0,
1384                 0x1e300, 0x1e384,
1385                 0x1e3c0, 0x1e3c8,
1386                 0x1e408, 0x1e40c,
1387                 0x1e440, 0x1e444,
1388                 0x1e44c, 0x1e44c,
1389                 0x1e684, 0x1e690,
1390                 0x1e6c0, 0x1e6c0,
1391                 0x1e6e0, 0x1e6e0,
1392                 0x1e700, 0x1e784,
1393                 0x1e7c0, 0x1e7c8,
1394                 0x1e808, 0x1e80c,
1395                 0x1e840, 0x1e844,
1396                 0x1e84c, 0x1e84c,
1397                 0x1ea84, 0x1ea90,
1398                 0x1eac0, 0x1eac0,
1399                 0x1eae0, 0x1eae0,
1400                 0x1eb00, 0x1eb84,
1401                 0x1ebc0, 0x1ebc8,
1402                 0x1ec08, 0x1ec0c,
1403                 0x1ec40, 0x1ec44,
1404                 0x1ec4c, 0x1ec4c,
1405                 0x1ee84, 0x1ee90,
1406                 0x1eec0, 0x1eec0,
1407                 0x1eee0, 0x1eee0,
1408                 0x1ef00, 0x1ef84,
1409                 0x1efc0, 0x1efc8,
1410                 0x1f008, 0x1f00c,
1411                 0x1f040, 0x1f044,
1412                 0x1f04c, 0x1f04c,
1413                 0x1f284, 0x1f290,
1414                 0x1f2c0, 0x1f2c0,
1415                 0x1f2e0, 0x1f2e0,
1416                 0x1f300, 0x1f384,
1417                 0x1f3c0, 0x1f3c8,
1418                 0x1f408, 0x1f40c,
1419                 0x1f440, 0x1f444,
1420                 0x1f44c, 0x1f44c,
1421                 0x1f684, 0x1f690,
1422                 0x1f6c0, 0x1f6c0,
1423                 0x1f6e0, 0x1f6e0,
1424                 0x1f700, 0x1f784,
1425                 0x1f7c0, 0x1f7c8,
1426                 0x1f808, 0x1f80c,
1427                 0x1f840, 0x1f844,
1428                 0x1f84c, 0x1f84c,
1429                 0x1fa84, 0x1fa90,
1430                 0x1fac0, 0x1fac0,
1431                 0x1fae0, 0x1fae0,
1432                 0x1fb00, 0x1fb84,
1433                 0x1fbc0, 0x1fbc8,
1434                 0x1fc08, 0x1fc0c,
1435                 0x1fc40, 0x1fc44,
1436                 0x1fc4c, 0x1fc4c,
1437                 0x1fe84, 0x1fe90,
1438                 0x1fec0, 0x1fec0,
1439                 0x1fee0, 0x1fee0,
1440                 0x1ff00, 0x1ff84,
1441                 0x1ffc0, 0x1ffc8,
1442                 0x30000, 0x30030,
1443                 0x30100, 0x30144,
1444                 0x30190, 0x301a0,
1445                 0x301a8, 0x301b8,
1446                 0x301c4, 0x301c8,
1447                 0x301d0, 0x301d0,
1448                 0x30200, 0x30318,
1449                 0x30400, 0x304b4,
1450                 0x304c0, 0x3052c,
1451                 0x30540, 0x3061c,
1452                 0x30800, 0x30828,
1453                 0x30834, 0x30834,
1454                 0x308c0, 0x30908,
1455                 0x30910, 0x309ac,
1456                 0x30a00, 0x30a14,
1457                 0x30a1c, 0x30a2c,
1458                 0x30a44, 0x30a50,
1459                 0x30a74, 0x30a74,
1460                 0x30a7c, 0x30afc,
1461                 0x30b08, 0x30c24,
1462                 0x30d00, 0x30d00,
1463                 0x30d08, 0x30d14,
1464                 0x30d1c, 0x30d20,
1465                 0x30d3c, 0x30d3c,
1466                 0x30d48, 0x30d50,
1467                 0x31200, 0x3120c,
1468                 0x31220, 0x31220,
1469                 0x31240, 0x31240,
1470                 0x31600, 0x3160c,
1471                 0x31a00, 0x31a1c,
1472                 0x31e00, 0x31e20,
1473                 0x31e38, 0x31e3c,
1474                 0x31e80, 0x31e80,
1475                 0x31e88, 0x31ea8,
1476                 0x31eb0, 0x31eb4,
1477                 0x31ec8, 0x31ed4,
1478                 0x31fb8, 0x32004,
1479                 0x32200, 0x32200,
1480                 0x32208, 0x32240,
1481                 0x32248, 0x32280,
1482                 0x32288, 0x322c0,
1483                 0x322c8, 0x322fc,
1484                 0x32600, 0x32630,
1485                 0x32a00, 0x32abc,
1486                 0x32b00, 0x32b10,
1487                 0x32b20, 0x32b30,
1488                 0x32b40, 0x32b50,
1489                 0x32b60, 0x32b70,
1490                 0x33000, 0x33028,
1491                 0x33030, 0x33048,
1492                 0x33060, 0x33068,
1493                 0x33070, 0x3309c,
1494                 0x330f0, 0x33128,
1495                 0x33130, 0x33148,
1496                 0x33160, 0x33168,
1497                 0x33170, 0x3319c,
1498                 0x331f0, 0x33238,
1499                 0x33240, 0x33240,
1500                 0x33248, 0x33250,
1501                 0x3325c, 0x33264,
1502                 0x33270, 0x332b8,
1503                 0x332c0, 0x332e4,
1504                 0x332f8, 0x33338,
1505                 0x33340, 0x33340,
1506                 0x33348, 0x33350,
1507                 0x3335c, 0x33364,
1508                 0x33370, 0x333b8,
1509                 0x333c0, 0x333e4,
1510                 0x333f8, 0x33428,
1511                 0x33430, 0x33448,
1512                 0x33460, 0x33468,
1513                 0x33470, 0x3349c,
1514                 0x334f0, 0x33528,
1515                 0x33530, 0x33548,
1516                 0x33560, 0x33568,
1517                 0x33570, 0x3359c,
1518                 0x335f0, 0x33638,
1519                 0x33640, 0x33640,
1520                 0x33648, 0x33650,
1521                 0x3365c, 0x33664,
1522                 0x33670, 0x336b8,
1523                 0x336c0, 0x336e4,
1524                 0x336f8, 0x33738,
1525                 0x33740, 0x33740,
1526                 0x33748, 0x33750,
1527                 0x3375c, 0x33764,
1528                 0x33770, 0x337b8,
1529                 0x337c0, 0x337e4,
1530                 0x337f8, 0x337fc,
1531                 0x33814, 0x33814,
1532                 0x3382c, 0x3382c,
1533                 0x33880, 0x3388c,
1534                 0x338e8, 0x338ec,
1535                 0x33900, 0x33928,
1536                 0x33930, 0x33948,
1537                 0x33960, 0x33968,
1538                 0x33970, 0x3399c,
1539                 0x339f0, 0x33a38,
1540                 0x33a40, 0x33a40,
1541                 0x33a48, 0x33a50,
1542                 0x33a5c, 0x33a64,
1543                 0x33a70, 0x33ab8,
1544                 0x33ac0, 0x33ae4,
1545                 0x33af8, 0x33b10,
1546                 0x33b28, 0x33b28,
1547                 0x33b3c, 0x33b50,
1548                 0x33bf0, 0x33c10,
1549                 0x33c28, 0x33c28,
1550                 0x33c3c, 0x33c50,
1551                 0x33cf0, 0x33cfc,
1552                 0x34000, 0x34030,
1553                 0x34100, 0x34144,
1554                 0x34190, 0x341a0,
1555                 0x341a8, 0x341b8,
1556                 0x341c4, 0x341c8,
1557                 0x341d0, 0x341d0,
1558                 0x34200, 0x34318,
1559                 0x34400, 0x344b4,
1560                 0x344c0, 0x3452c,
1561                 0x34540, 0x3461c,
1562                 0x34800, 0x34828,
1563                 0x34834, 0x34834,
1564                 0x348c0, 0x34908,
1565                 0x34910, 0x349ac,
1566                 0x34a00, 0x34a14,
1567                 0x34a1c, 0x34a2c,
1568                 0x34a44, 0x34a50,
1569                 0x34a74, 0x34a74,
1570                 0x34a7c, 0x34afc,
1571                 0x34b08, 0x34c24,
1572                 0x34d00, 0x34d00,
1573                 0x34d08, 0x34d14,
1574                 0x34d1c, 0x34d20,
1575                 0x34d3c, 0x34d3c,
1576                 0x34d48, 0x34d50,
1577                 0x35200, 0x3520c,
1578                 0x35220, 0x35220,
1579                 0x35240, 0x35240,
1580                 0x35600, 0x3560c,
1581                 0x35a00, 0x35a1c,
1582                 0x35e00, 0x35e20,
1583                 0x35e38, 0x35e3c,
1584                 0x35e80, 0x35e80,
1585                 0x35e88, 0x35ea8,
1586                 0x35eb0, 0x35eb4,
1587                 0x35ec8, 0x35ed4,
1588                 0x35fb8, 0x36004,
1589                 0x36200, 0x36200,
1590                 0x36208, 0x36240,
1591                 0x36248, 0x36280,
1592                 0x36288, 0x362c0,
1593                 0x362c8, 0x362fc,
1594                 0x36600, 0x36630,
1595                 0x36a00, 0x36abc,
1596                 0x36b00, 0x36b10,
1597                 0x36b20, 0x36b30,
1598                 0x36b40, 0x36b50,
1599                 0x36b60, 0x36b70,
1600                 0x37000, 0x37028,
1601                 0x37030, 0x37048,
1602                 0x37060, 0x37068,
1603                 0x37070, 0x3709c,
1604                 0x370f0, 0x37128,
1605                 0x37130, 0x37148,
1606                 0x37160, 0x37168,
1607                 0x37170, 0x3719c,
1608                 0x371f0, 0x37238,
1609                 0x37240, 0x37240,
1610                 0x37248, 0x37250,
1611                 0x3725c, 0x37264,
1612                 0x37270, 0x372b8,
1613                 0x372c0, 0x372e4,
1614                 0x372f8, 0x37338,
1615                 0x37340, 0x37340,
1616                 0x37348, 0x37350,
1617                 0x3735c, 0x37364,
1618                 0x37370, 0x373b8,
1619                 0x373c0, 0x373e4,
1620                 0x373f8, 0x37428,
1621                 0x37430, 0x37448,
1622                 0x37460, 0x37468,
1623                 0x37470, 0x3749c,
1624                 0x374f0, 0x37528,
1625                 0x37530, 0x37548,
1626                 0x37560, 0x37568,
1627                 0x37570, 0x3759c,
1628                 0x375f0, 0x37638,
1629                 0x37640, 0x37640,
1630                 0x37648, 0x37650,
1631                 0x3765c, 0x37664,
1632                 0x37670, 0x376b8,
1633                 0x376c0, 0x376e4,
1634                 0x376f8, 0x37738,
1635                 0x37740, 0x37740,
1636                 0x37748, 0x37750,
1637                 0x3775c, 0x37764,
1638                 0x37770, 0x377b8,
1639                 0x377c0, 0x377e4,
1640                 0x377f8, 0x377fc,
1641                 0x37814, 0x37814,
1642                 0x3782c, 0x3782c,
1643                 0x37880, 0x3788c,
1644                 0x378e8, 0x378ec,
1645                 0x37900, 0x37928,
1646                 0x37930, 0x37948,
1647                 0x37960, 0x37968,
1648                 0x37970, 0x3799c,
1649                 0x379f0, 0x37a38,
1650                 0x37a40, 0x37a40,
1651                 0x37a48, 0x37a50,
1652                 0x37a5c, 0x37a64,
1653                 0x37a70, 0x37ab8,
1654                 0x37ac0, 0x37ae4,
1655                 0x37af8, 0x37b10,
1656                 0x37b28, 0x37b28,
1657                 0x37b3c, 0x37b50,
1658                 0x37bf0, 0x37c10,
1659                 0x37c28, 0x37c28,
1660                 0x37c3c, 0x37c50,
1661                 0x37cf0, 0x37cfc,
1662                 0x38000, 0x38030,
1663                 0x38100, 0x38144,
1664                 0x38190, 0x381a0,
1665                 0x381a8, 0x381b8,
1666                 0x381c4, 0x381c8,
1667                 0x381d0, 0x381d0,
1668                 0x38200, 0x38318,
1669                 0x38400, 0x384b4,
1670                 0x384c0, 0x3852c,
1671                 0x38540, 0x3861c,
1672                 0x38800, 0x38828,
1673                 0x38834, 0x38834,
1674                 0x388c0, 0x38908,
1675                 0x38910, 0x389ac,
1676                 0x38a00, 0x38a14,
1677                 0x38a1c, 0x38a2c,
1678                 0x38a44, 0x38a50,
1679                 0x38a74, 0x38a74,
1680                 0x38a7c, 0x38afc,
1681                 0x38b08, 0x38c24,
1682                 0x38d00, 0x38d00,
1683                 0x38d08, 0x38d14,
1684                 0x38d1c, 0x38d20,
1685                 0x38d3c, 0x38d3c,
1686                 0x38d48, 0x38d50,
1687                 0x39200, 0x3920c,
1688                 0x39220, 0x39220,
1689                 0x39240, 0x39240,
1690                 0x39600, 0x3960c,
1691                 0x39a00, 0x39a1c,
1692                 0x39e00, 0x39e20,
1693                 0x39e38, 0x39e3c,
1694                 0x39e80, 0x39e80,
1695                 0x39e88, 0x39ea8,
1696                 0x39eb0, 0x39eb4,
1697                 0x39ec8, 0x39ed4,
1698                 0x39fb8, 0x3a004,
1699                 0x3a200, 0x3a200,
1700                 0x3a208, 0x3a240,
1701                 0x3a248, 0x3a280,
1702                 0x3a288, 0x3a2c0,
1703                 0x3a2c8, 0x3a2fc,
1704                 0x3a600, 0x3a630,
1705                 0x3aa00, 0x3aabc,
1706                 0x3ab00, 0x3ab10,
1707                 0x3ab20, 0x3ab30,
1708                 0x3ab40, 0x3ab50,
1709                 0x3ab60, 0x3ab70,
1710                 0x3b000, 0x3b028,
1711                 0x3b030, 0x3b048,
1712                 0x3b060, 0x3b068,
1713                 0x3b070, 0x3b09c,
1714                 0x3b0f0, 0x3b128,
1715                 0x3b130, 0x3b148,
1716                 0x3b160, 0x3b168,
1717                 0x3b170, 0x3b19c,
1718                 0x3b1f0, 0x3b238,
1719                 0x3b240, 0x3b240,
1720                 0x3b248, 0x3b250,
1721                 0x3b25c, 0x3b264,
1722                 0x3b270, 0x3b2b8,
1723                 0x3b2c0, 0x3b2e4,
1724                 0x3b2f8, 0x3b338,
1725                 0x3b340, 0x3b340,
1726                 0x3b348, 0x3b350,
1727                 0x3b35c, 0x3b364,
1728                 0x3b370, 0x3b3b8,
1729                 0x3b3c0, 0x3b3e4,
1730                 0x3b3f8, 0x3b428,
1731                 0x3b430, 0x3b448,
1732                 0x3b460, 0x3b468,
1733                 0x3b470, 0x3b49c,
1734                 0x3b4f0, 0x3b528,
1735                 0x3b530, 0x3b548,
1736                 0x3b560, 0x3b568,
1737                 0x3b570, 0x3b59c,
1738                 0x3b5f0, 0x3b638,
1739                 0x3b640, 0x3b640,
1740                 0x3b648, 0x3b650,
1741                 0x3b65c, 0x3b664,
1742                 0x3b670, 0x3b6b8,
1743                 0x3b6c0, 0x3b6e4,
1744                 0x3b6f8, 0x3b738,
1745                 0x3b740, 0x3b740,
1746                 0x3b748, 0x3b750,
1747                 0x3b75c, 0x3b764,
1748                 0x3b770, 0x3b7b8,
1749                 0x3b7c0, 0x3b7e4,
1750                 0x3b7f8, 0x3b7fc,
1751                 0x3b814, 0x3b814,
1752                 0x3b82c, 0x3b82c,
1753                 0x3b880, 0x3b88c,
1754                 0x3b8e8, 0x3b8ec,
1755                 0x3b900, 0x3b928,
1756                 0x3b930, 0x3b948,
1757                 0x3b960, 0x3b968,
1758                 0x3b970, 0x3b99c,
1759                 0x3b9f0, 0x3ba38,
1760                 0x3ba40, 0x3ba40,
1761                 0x3ba48, 0x3ba50,
1762                 0x3ba5c, 0x3ba64,
1763                 0x3ba70, 0x3bab8,
1764                 0x3bac0, 0x3bae4,
1765                 0x3baf8, 0x3bb10,
1766                 0x3bb28, 0x3bb28,
1767                 0x3bb3c, 0x3bb50,
1768                 0x3bbf0, 0x3bc10,
1769                 0x3bc28, 0x3bc28,
1770                 0x3bc3c, 0x3bc50,
1771                 0x3bcf0, 0x3bcfc,
1772                 0x3c000, 0x3c030,
1773                 0x3c100, 0x3c144,
1774                 0x3c190, 0x3c1a0,
1775                 0x3c1a8, 0x3c1b8,
1776                 0x3c1c4, 0x3c1c8,
1777                 0x3c1d0, 0x3c1d0,
1778                 0x3c200, 0x3c318,
1779                 0x3c400, 0x3c4b4,
1780                 0x3c4c0, 0x3c52c,
1781                 0x3c540, 0x3c61c,
1782                 0x3c800, 0x3c828,
1783                 0x3c834, 0x3c834,
1784                 0x3c8c0, 0x3c908,
1785                 0x3c910, 0x3c9ac,
1786                 0x3ca00, 0x3ca14,
1787                 0x3ca1c, 0x3ca2c,
1788                 0x3ca44, 0x3ca50,
1789                 0x3ca74, 0x3ca74,
1790                 0x3ca7c, 0x3cafc,
1791                 0x3cb08, 0x3cc24,
1792                 0x3cd00, 0x3cd00,
1793                 0x3cd08, 0x3cd14,
1794                 0x3cd1c, 0x3cd20,
1795                 0x3cd3c, 0x3cd3c,
1796                 0x3cd48, 0x3cd50,
1797                 0x3d200, 0x3d20c,
1798                 0x3d220, 0x3d220,
1799                 0x3d240, 0x3d240,
1800                 0x3d600, 0x3d60c,
1801                 0x3da00, 0x3da1c,
1802                 0x3de00, 0x3de20,
1803                 0x3de38, 0x3de3c,
1804                 0x3de80, 0x3de80,
1805                 0x3de88, 0x3dea8,
1806                 0x3deb0, 0x3deb4,
1807                 0x3dec8, 0x3ded4,
1808                 0x3dfb8, 0x3e004,
1809                 0x3e200, 0x3e200,
1810                 0x3e208, 0x3e240,
1811                 0x3e248, 0x3e280,
1812                 0x3e288, 0x3e2c0,
1813                 0x3e2c8, 0x3e2fc,
1814                 0x3e600, 0x3e630,
1815                 0x3ea00, 0x3eabc,
1816                 0x3eb00, 0x3eb10,
1817                 0x3eb20, 0x3eb30,
1818                 0x3eb40, 0x3eb50,
1819                 0x3eb60, 0x3eb70,
1820                 0x3f000, 0x3f028,
1821                 0x3f030, 0x3f048,
1822                 0x3f060, 0x3f068,
1823                 0x3f070, 0x3f09c,
1824                 0x3f0f0, 0x3f128,
1825                 0x3f130, 0x3f148,
1826                 0x3f160, 0x3f168,
1827                 0x3f170, 0x3f19c,
1828                 0x3f1f0, 0x3f238,
1829                 0x3f240, 0x3f240,
1830                 0x3f248, 0x3f250,
1831                 0x3f25c, 0x3f264,
1832                 0x3f270, 0x3f2b8,
1833                 0x3f2c0, 0x3f2e4,
1834                 0x3f2f8, 0x3f338,
1835                 0x3f340, 0x3f340,
1836                 0x3f348, 0x3f350,
1837                 0x3f35c, 0x3f364,
1838                 0x3f370, 0x3f3b8,
1839                 0x3f3c0, 0x3f3e4,
1840                 0x3f3f8, 0x3f428,
1841                 0x3f430, 0x3f448,
1842                 0x3f460, 0x3f468,
1843                 0x3f470, 0x3f49c,
1844                 0x3f4f0, 0x3f528,
1845                 0x3f530, 0x3f548,
1846                 0x3f560, 0x3f568,
1847                 0x3f570, 0x3f59c,
1848                 0x3f5f0, 0x3f638,
1849                 0x3f640, 0x3f640,
1850                 0x3f648, 0x3f650,
1851                 0x3f65c, 0x3f664,
1852                 0x3f670, 0x3f6b8,
1853                 0x3f6c0, 0x3f6e4,
1854                 0x3f6f8, 0x3f738,
1855                 0x3f740, 0x3f740,
1856                 0x3f748, 0x3f750,
1857                 0x3f75c, 0x3f764,
1858                 0x3f770, 0x3f7b8,
1859                 0x3f7c0, 0x3f7e4,
1860                 0x3f7f8, 0x3f7fc,
1861                 0x3f814, 0x3f814,
1862                 0x3f82c, 0x3f82c,
1863                 0x3f880, 0x3f88c,
1864                 0x3f8e8, 0x3f8ec,
1865                 0x3f900, 0x3f928,
1866                 0x3f930, 0x3f948,
1867                 0x3f960, 0x3f968,
1868                 0x3f970, 0x3f99c,
1869                 0x3f9f0, 0x3fa38,
1870                 0x3fa40, 0x3fa40,
1871                 0x3fa48, 0x3fa50,
1872                 0x3fa5c, 0x3fa64,
1873                 0x3fa70, 0x3fab8,
1874                 0x3fac0, 0x3fae4,
1875                 0x3faf8, 0x3fb10,
1876                 0x3fb28, 0x3fb28,
1877                 0x3fb3c, 0x3fb50,
1878                 0x3fbf0, 0x3fc10,
1879                 0x3fc28, 0x3fc28,
1880                 0x3fc3c, 0x3fc50,
1881                 0x3fcf0, 0x3fcfc,
1882                 0x40000, 0x4000c,
1883                 0x40040, 0x40050,
1884                 0x40060, 0x40068,
1885                 0x4007c, 0x4008c,
1886                 0x40094, 0x400b0,
1887                 0x400c0, 0x40144,
1888                 0x40180, 0x4018c,
1889                 0x40200, 0x40254,
1890                 0x40260, 0x40264,
1891                 0x40270, 0x40288,
1892                 0x40290, 0x40298,
1893                 0x402ac, 0x402c8,
1894                 0x402d0, 0x402e0,
1895                 0x402f0, 0x402f0,
1896                 0x40300, 0x4033c,
1897                 0x403f8, 0x403fc,
1898                 0x41304, 0x413c4,
1899                 0x41400, 0x4140c,
1900                 0x41414, 0x4141c,
1901                 0x41480, 0x414d0,
1902                 0x44000, 0x44054,
1903                 0x4405c, 0x44078,
1904                 0x440c0, 0x44174,
1905                 0x44180, 0x441ac,
1906                 0x441b4, 0x441b8,
1907                 0x441c0, 0x44254,
1908                 0x4425c, 0x44278,
1909                 0x442c0, 0x44374,
1910                 0x44380, 0x443ac,
1911                 0x443b4, 0x443b8,
1912                 0x443c0, 0x44454,
1913                 0x4445c, 0x44478,
1914                 0x444c0, 0x44574,
1915                 0x44580, 0x445ac,
1916                 0x445b4, 0x445b8,
1917                 0x445c0, 0x44654,
1918                 0x4465c, 0x44678,
1919                 0x446c0, 0x44774,
1920                 0x44780, 0x447ac,
1921                 0x447b4, 0x447b8,
1922                 0x447c0, 0x44854,
1923                 0x4485c, 0x44878,
1924                 0x448c0, 0x44974,
1925                 0x44980, 0x449ac,
1926                 0x449b4, 0x449b8,
1927                 0x449c0, 0x449fc,
1928                 0x45000, 0x45004,
1929                 0x45010, 0x45030,
1930                 0x45040, 0x45060,
1931                 0x45068, 0x45068,
1932                 0x45080, 0x45084,
1933                 0x450a0, 0x450b0,
1934                 0x45200, 0x45204,
1935                 0x45210, 0x45230,
1936                 0x45240, 0x45260,
1937                 0x45268, 0x45268,
1938                 0x45280, 0x45284,
1939                 0x452a0, 0x452b0,
1940                 0x460c0, 0x460e4,
1941                 0x47000, 0x4703c,
1942                 0x47044, 0x4708c,
1943                 0x47200, 0x47250,
1944                 0x47400, 0x47408,
1945                 0x47414, 0x47420,
1946                 0x47600, 0x47618,
1947                 0x47800, 0x47814,
1948                 0x48000, 0x4800c,
1949                 0x48040, 0x48050,
1950                 0x48060, 0x48068,
1951                 0x4807c, 0x4808c,
1952                 0x48094, 0x480b0,
1953                 0x480c0, 0x48144,
1954                 0x48180, 0x4818c,
1955                 0x48200, 0x48254,
1956                 0x48260, 0x48264,
1957                 0x48270, 0x48288,
1958                 0x48290, 0x48298,
1959                 0x482ac, 0x482c8,
1960                 0x482d0, 0x482e0,
1961                 0x482f0, 0x482f0,
1962                 0x48300, 0x4833c,
1963                 0x483f8, 0x483fc,
1964                 0x49304, 0x493c4,
1965                 0x49400, 0x4940c,
1966                 0x49414, 0x4941c,
1967                 0x49480, 0x494d0,
1968                 0x4c000, 0x4c054,
1969                 0x4c05c, 0x4c078,
1970                 0x4c0c0, 0x4c174,
1971                 0x4c180, 0x4c1ac,
1972                 0x4c1b4, 0x4c1b8,
1973                 0x4c1c0, 0x4c254,
1974                 0x4c25c, 0x4c278,
1975                 0x4c2c0, 0x4c374,
1976                 0x4c380, 0x4c3ac,
1977                 0x4c3b4, 0x4c3b8,
1978                 0x4c3c0, 0x4c454,
1979                 0x4c45c, 0x4c478,
1980                 0x4c4c0, 0x4c574,
1981                 0x4c580, 0x4c5ac,
1982                 0x4c5b4, 0x4c5b8,
1983                 0x4c5c0, 0x4c654,
1984                 0x4c65c, 0x4c678,
1985                 0x4c6c0, 0x4c774,
1986                 0x4c780, 0x4c7ac,
1987                 0x4c7b4, 0x4c7b8,
1988                 0x4c7c0, 0x4c854,
1989                 0x4c85c, 0x4c878,
1990                 0x4c8c0, 0x4c974,
1991                 0x4c980, 0x4c9ac,
1992                 0x4c9b4, 0x4c9b8,
1993                 0x4c9c0, 0x4c9fc,
1994                 0x4d000, 0x4d004,
1995                 0x4d010, 0x4d030,
1996                 0x4d040, 0x4d060,
1997                 0x4d068, 0x4d068,
1998                 0x4d080, 0x4d084,
1999                 0x4d0a0, 0x4d0b0,
2000                 0x4d200, 0x4d204,
2001                 0x4d210, 0x4d230,
2002                 0x4d240, 0x4d260,
2003                 0x4d268, 0x4d268,
2004                 0x4d280, 0x4d284,
2005                 0x4d2a0, 0x4d2b0,
2006                 0x4e0c0, 0x4e0e4,
2007                 0x4f000, 0x4f03c,
2008                 0x4f044, 0x4f08c,
2009                 0x4f200, 0x4f250,
2010                 0x4f400, 0x4f408,
2011                 0x4f414, 0x4f420,
2012                 0x4f600, 0x4f618,
2013                 0x4f800, 0x4f814,
2014                 0x50000, 0x50084,
2015                 0x50090, 0x500cc,
2016                 0x50400, 0x50400,
2017                 0x50800, 0x50884,
2018                 0x50890, 0x508cc,
2019                 0x50c00, 0x50c00,
2020                 0x51000, 0x5101c,
2021                 0x51300, 0x51308,
2022         };
2023
2024         static const unsigned int t6_reg_ranges[] = {
2025                 0x1008, 0x101c,
2026                 0x1024, 0x10a8,
2027                 0x10b4, 0x10f8,
2028                 0x1100, 0x1114,
2029                 0x111c, 0x112c,
2030                 0x1138, 0x113c,
2031                 0x1144, 0x114c,
2032                 0x1180, 0x1184,
2033                 0x1190, 0x1194,
2034                 0x11a0, 0x11a4,
2035                 0x11b0, 0x11b4,
2036                 0x11fc, 0x1274,
2037                 0x1280, 0x133c,
2038                 0x1800, 0x18fc,
2039                 0x3000, 0x302c,
2040                 0x3060, 0x30b0,
2041                 0x30b8, 0x30d8,
2042                 0x30e0, 0x30fc,
2043                 0x3140, 0x357c,
2044                 0x35a8, 0x35cc,
2045                 0x35ec, 0x35ec,
2046                 0x3600, 0x5624,
2047                 0x56cc, 0x56ec,
2048                 0x56f4, 0x5720,
2049                 0x5728, 0x575c,
2050                 0x580c, 0x5814,
2051                 0x5890, 0x589c,
2052                 0x58a4, 0x58ac,
2053                 0x58b8, 0x58bc,
2054                 0x5940, 0x595c,
2055                 0x5980, 0x598c,
2056                 0x59b0, 0x59c8,
2057                 0x59d0, 0x59dc,
2058                 0x59fc, 0x5a18,
2059                 0x5a60, 0x5a6c,
2060                 0x5a80, 0x5a8c,
2061                 0x5a94, 0x5a9c,
2062                 0x5b94, 0x5bfc,
2063                 0x5c10, 0x5e48,
2064                 0x5e50, 0x5e94,
2065                 0x5ea0, 0x5eb0,
2066                 0x5ec0, 0x5ec0,
2067                 0x5ec8, 0x5ed0,
2068                 0x5ee0, 0x5ee0,
2069                 0x5ef0, 0x5ef0,
2070                 0x5f00, 0x5f00,
2071                 0x6000, 0x6020,
2072                 0x6028, 0x6040,
2073                 0x6058, 0x609c,
2074                 0x60a8, 0x619c,
2075                 0x7700, 0x7798,
2076                 0x77c0, 0x7880,
2077                 0x78cc, 0x78fc,
2078                 0x7b00, 0x7b58,
2079                 0x7b60, 0x7b84,
2080                 0x7b8c, 0x7c54,
2081                 0x7d00, 0x7d38,
2082                 0x7d40, 0x7d84,
2083                 0x7d8c, 0x7ddc,
2084                 0x7de4, 0x7e04,
2085                 0x7e10, 0x7e1c,
2086                 0x7e24, 0x7e38,
2087                 0x7e40, 0x7e44,
2088                 0x7e4c, 0x7e78,
2089                 0x7e80, 0x7edc,
2090                 0x7ee8, 0x7efc,
2091                 0x8dc0, 0x8de4,
2092                 0x8df8, 0x8e04,
2093                 0x8e10, 0x8e84,
2094                 0x8ea0, 0x8f88,
2095                 0x8fb8, 0x9058,
2096                 0x9060, 0x9060,
2097                 0x9068, 0x90f8,
2098                 0x9100, 0x9124,
2099                 0x9400, 0x9470,
2100                 0x9600, 0x9600,
2101                 0x9608, 0x9638,
2102                 0x9640, 0x9704,
2103                 0x9710, 0x971c,
2104                 0x9800, 0x9808,
2105                 0x9820, 0x983c,
2106                 0x9850, 0x9864,
2107                 0x9c00, 0x9c6c,
2108                 0x9c80, 0x9cec,
2109                 0x9d00, 0x9d6c,
2110                 0x9d80, 0x9dec,
2111                 0x9e00, 0x9e6c,
2112                 0x9e80, 0x9eec,
2113                 0x9f00, 0x9f6c,
2114                 0x9f80, 0xa020,
2115                 0xd004, 0xd03c,
2116                 0xd100, 0xd118,
2117                 0xd200, 0xd214,
2118                 0xd220, 0xd234,
2119                 0xd240, 0xd254,
2120                 0xd260, 0xd274,
2121                 0xd280, 0xd294,
2122                 0xd2a0, 0xd2b4,
2123                 0xd2c0, 0xd2d4,
2124                 0xd2e0, 0xd2f4,
2125                 0xd300, 0xd31c,
2126                 0xdfc0, 0xdfe0,
2127                 0xe000, 0xf008,
2128                 0xf010, 0xf018,
2129                 0xf020, 0xf028,
2130                 0x11000, 0x11014,
2131                 0x11048, 0x1106c,
2132                 0x11074, 0x11088,
2133                 0x11098, 0x11120,
2134                 0x1112c, 0x1117c,
2135                 0x11190, 0x112e0,
2136                 0x11300, 0x1130c,
2137                 0x12000, 0x1206c,
2138                 0x19040, 0x1906c,
2139                 0x19078, 0x19080,
2140                 0x1908c, 0x190e8,
2141                 0x190f0, 0x190f8,
2142                 0x19100, 0x19110,
2143                 0x19120, 0x19124,
2144                 0x19150, 0x19194,
2145                 0x1919c, 0x191b0,
2146                 0x191d0, 0x191e8,
2147                 0x19238, 0x19290,
2148                 0x192a4, 0x192b0,
2149                 0x192bc, 0x192bc,
2150                 0x19348, 0x1934c,
2151                 0x193f8, 0x19418,
2152                 0x19420, 0x19428,
2153                 0x19430, 0x19444,
2154                 0x1944c, 0x1946c,
2155                 0x19474, 0x19474,
2156                 0x19490, 0x194cc,
2157                 0x194f0, 0x194f8,
2158                 0x19c00, 0x19c48,
2159                 0x19c50, 0x19c80,
2160                 0x19c94, 0x19c98,
2161                 0x19ca0, 0x19cbc,
2162                 0x19ce4, 0x19ce4,
2163                 0x19cf0, 0x19cf8,
2164                 0x19d00, 0x19d28,
2165                 0x19d50, 0x19d78,
2166                 0x19d94, 0x19d98,
2167                 0x19da0, 0x19dc8,
2168                 0x19df0, 0x19e10,
2169                 0x19e50, 0x19e6c,
2170                 0x19ea0, 0x19ebc,
2171                 0x19ec4, 0x19ef4,
2172                 0x19f04, 0x19f2c,
2173                 0x19f34, 0x19f34,
2174                 0x19f40, 0x19f50,
2175                 0x19f90, 0x19fac,
2176                 0x19fc4, 0x19fc8,
2177                 0x19fd0, 0x19fe4,
2178                 0x1a000, 0x1a004,
2179                 0x1a010, 0x1a06c,
2180                 0x1a0b0, 0x1a0e4,
2181                 0x1a0ec, 0x1a0f8,
2182                 0x1a100, 0x1a108,
2183                 0x1a114, 0x1a120,
2184                 0x1a128, 0x1a130,
2185                 0x1a138, 0x1a138,
2186                 0x1a190, 0x1a1c4,
2187                 0x1a1fc, 0x1a1fc,
2188                 0x1e008, 0x1e00c,
2189                 0x1e040, 0x1e044,
2190                 0x1e04c, 0x1e04c,
2191                 0x1e284, 0x1e290,
2192                 0x1e2c0, 0x1e2c0,
2193                 0x1e2e0, 0x1e2e0,
2194                 0x1e300, 0x1e384,
2195                 0x1e3c0, 0x1e3c8,
2196                 0x1e408, 0x1e40c,
2197                 0x1e440, 0x1e444,
2198                 0x1e44c, 0x1e44c,
2199                 0x1e684, 0x1e690,
2200                 0x1e6c0, 0x1e6c0,
2201                 0x1e6e0, 0x1e6e0,
2202                 0x1e700, 0x1e784,
2203                 0x1e7c0, 0x1e7c8,
2204                 0x1e808, 0x1e80c,
2205                 0x1e840, 0x1e844,
2206                 0x1e84c, 0x1e84c,
2207                 0x1ea84, 0x1ea90,
2208                 0x1eac0, 0x1eac0,
2209                 0x1eae0, 0x1eae0,
2210                 0x1eb00, 0x1eb84,
2211                 0x1ebc0, 0x1ebc8,
2212                 0x1ec08, 0x1ec0c,
2213                 0x1ec40, 0x1ec44,
2214                 0x1ec4c, 0x1ec4c,
2215                 0x1ee84, 0x1ee90,
2216                 0x1eec0, 0x1eec0,
2217                 0x1eee0, 0x1eee0,
2218                 0x1ef00, 0x1ef84,
2219                 0x1efc0, 0x1efc8,
2220                 0x1f008, 0x1f00c,
2221                 0x1f040, 0x1f044,
2222                 0x1f04c, 0x1f04c,
2223                 0x1f284, 0x1f290,
2224                 0x1f2c0, 0x1f2c0,
2225                 0x1f2e0, 0x1f2e0,
2226                 0x1f300, 0x1f384,
2227                 0x1f3c0, 0x1f3c8,
2228                 0x1f408, 0x1f40c,
2229                 0x1f440, 0x1f444,
2230                 0x1f44c, 0x1f44c,
2231                 0x1f684, 0x1f690,
2232                 0x1f6c0, 0x1f6c0,
2233                 0x1f6e0, 0x1f6e0,
2234                 0x1f700, 0x1f784,
2235                 0x1f7c0, 0x1f7c8,
2236                 0x1f808, 0x1f80c,
2237                 0x1f840, 0x1f844,
2238                 0x1f84c, 0x1f84c,
2239                 0x1fa84, 0x1fa90,
2240                 0x1fac0, 0x1fac0,
2241                 0x1fae0, 0x1fae0,
2242                 0x1fb00, 0x1fb84,
2243                 0x1fbc0, 0x1fbc8,
2244                 0x1fc08, 0x1fc0c,
2245                 0x1fc40, 0x1fc44,
2246                 0x1fc4c, 0x1fc4c,
2247                 0x1fe84, 0x1fe90,
2248                 0x1fec0, 0x1fec0,
2249                 0x1fee0, 0x1fee0,
2250                 0x1ff00, 0x1ff84,
2251                 0x1ffc0, 0x1ffc8,
2252                 0x30000, 0x30030,
2253                 0x30100, 0x30168,
2254                 0x30190, 0x301a0,
2255                 0x301a8, 0x301b8,
2256                 0x301c4, 0x301c8,
2257                 0x301d0, 0x301d0,
2258                 0x30200, 0x30320,
2259                 0x30400, 0x304b4,
2260                 0x304c0, 0x3052c,
2261                 0x30540, 0x3061c,
2262                 0x30800, 0x308a0,
2263                 0x308c0, 0x30908,
2264                 0x30910, 0x309b8,
2265                 0x30a00, 0x30a04,
2266                 0x30a0c, 0x30a14,
2267                 0x30a1c, 0x30a2c,
2268                 0x30a44, 0x30a50,
2269                 0x30a74, 0x30a74,
2270                 0x30a7c, 0x30afc,
2271                 0x30b08, 0x30c24,
2272                 0x30d00, 0x30d14,
2273                 0x30d1c, 0x30d3c,
2274                 0x30d44, 0x30d4c,
2275                 0x30d54, 0x30d74,
2276                 0x30d7c, 0x30d7c,
2277                 0x30de0, 0x30de0,
2278                 0x30e00, 0x30ed4,
2279                 0x30f00, 0x30fa4,
2280                 0x30fc0, 0x30fc4,
2281                 0x31000, 0x31004,
2282                 0x31080, 0x310fc,
2283                 0x31208, 0x31220,
2284                 0x3123c, 0x31254,
2285                 0x31300, 0x31300,
2286                 0x31308, 0x3131c,
2287                 0x31338, 0x3133c,
2288                 0x31380, 0x31380,
2289                 0x31388, 0x313a8,
2290                 0x313b4, 0x313b4,
2291                 0x31400, 0x31420,
2292                 0x31438, 0x3143c,
2293                 0x31480, 0x31480,
2294                 0x314a8, 0x314a8,
2295                 0x314b0, 0x314b4,
2296                 0x314c8, 0x314d4,
2297                 0x31a40, 0x31a4c,
2298                 0x31af0, 0x31b20,
2299                 0x31b38, 0x31b3c,
2300                 0x31b80, 0x31b80,
2301                 0x31ba8, 0x31ba8,
2302                 0x31bb0, 0x31bb4,
2303                 0x31bc8, 0x31bd4,
2304                 0x32140, 0x3218c,
2305                 0x321f0, 0x321f4,
2306                 0x32200, 0x32200,
2307                 0x32218, 0x32218,
2308                 0x32400, 0x32400,
2309                 0x32408, 0x3241c,
2310                 0x32618, 0x32620,
2311                 0x32664, 0x32664,
2312                 0x326a8, 0x326a8,
2313                 0x326ec, 0x326ec,
2314                 0x32a00, 0x32abc,
2315                 0x32b00, 0x32b18,
2316                 0x32b20, 0x32b38,
2317                 0x32b40, 0x32b58,
2318                 0x32b60, 0x32b78,
2319                 0x32c00, 0x32c00,
2320                 0x32c08, 0x32c3c,
2321                 0x33000, 0x3302c,
2322                 0x33034, 0x33050,
2323                 0x33058, 0x33058,
2324                 0x33060, 0x3308c,
2325                 0x3309c, 0x330ac,
2326                 0x330c0, 0x330c0,
2327                 0x330c8, 0x330d0,
2328                 0x330d8, 0x330e0,
2329                 0x330ec, 0x3312c,
2330                 0x33134, 0x33150,
2331                 0x33158, 0x33158,
2332                 0x33160, 0x3318c,
2333                 0x3319c, 0x331ac,
2334                 0x331c0, 0x331c0,
2335                 0x331c8, 0x331d0,
2336                 0x331d8, 0x331e0,
2337                 0x331ec, 0x33290,
2338                 0x33298, 0x332c4,
2339                 0x332e4, 0x33390,
2340                 0x33398, 0x333c4,
2341                 0x333e4, 0x3342c,
2342                 0x33434, 0x33450,
2343                 0x33458, 0x33458,
2344                 0x33460, 0x3348c,
2345                 0x3349c, 0x334ac,
2346                 0x334c0, 0x334c0,
2347                 0x334c8, 0x334d0,
2348                 0x334d8, 0x334e0,
2349                 0x334ec, 0x3352c,
2350                 0x33534, 0x33550,
2351                 0x33558, 0x33558,
2352                 0x33560, 0x3358c,
2353                 0x3359c, 0x335ac,
2354                 0x335c0, 0x335c0,
2355                 0x335c8, 0x335d0,
2356                 0x335d8, 0x335e0,
2357                 0x335ec, 0x33690,
2358                 0x33698, 0x336c4,
2359                 0x336e4, 0x33790,
2360                 0x33798, 0x337c4,
2361                 0x337e4, 0x337fc,
2362                 0x33814, 0x33814,
2363                 0x33854, 0x33868,
2364                 0x33880, 0x3388c,
2365                 0x338c0, 0x338d0,
2366                 0x338e8, 0x338ec,
2367                 0x33900, 0x3392c,
2368                 0x33934, 0x33950,
2369                 0x33958, 0x33958,
2370                 0x33960, 0x3398c,
2371                 0x3399c, 0x339ac,
2372                 0x339c0, 0x339c0,
2373                 0x339c8, 0x339d0,
2374                 0x339d8, 0x339e0,
2375                 0x339ec, 0x33a90,
2376                 0x33a98, 0x33ac4,
2377                 0x33ae4, 0x33b10,
2378                 0x33b24, 0x33b28,
2379                 0x33b38, 0x33b50,
2380                 0x33bf0, 0x33c10,
2381                 0x33c24, 0x33c28,
2382                 0x33c38, 0x33c50,
2383                 0x33cf0, 0x33cfc,
2384                 0x34000, 0x34030,
2385                 0x34100, 0x34168,
2386                 0x34190, 0x341a0,
2387                 0x341a8, 0x341b8,
2388                 0x341c4, 0x341c8,
2389                 0x341d0, 0x341d0,
2390                 0x34200, 0x34320,
2391                 0x34400, 0x344b4,
2392                 0x344c0, 0x3452c,
2393                 0x34540, 0x3461c,
2394                 0x34800, 0x348a0,
2395                 0x348c0, 0x34908,
2396                 0x34910, 0x349b8,
2397                 0x34a00, 0x34a04,
2398                 0x34a0c, 0x34a14,
2399                 0x34a1c, 0x34a2c,
2400                 0x34a44, 0x34a50,
2401                 0x34a74, 0x34a74,
2402                 0x34a7c, 0x34afc,
2403                 0x34b08, 0x34c24,
2404                 0x34d00, 0x34d14,
2405                 0x34d1c, 0x34d3c,
2406                 0x34d44, 0x34d4c,
2407                 0x34d54, 0x34d74,
2408                 0x34d7c, 0x34d7c,
2409                 0x34de0, 0x34de0,
2410                 0x34e00, 0x34ed4,
2411                 0x34f00, 0x34fa4,
2412                 0x34fc0, 0x34fc4,
2413                 0x35000, 0x35004,
2414                 0x35080, 0x350fc,
2415                 0x35208, 0x35220,
2416                 0x3523c, 0x35254,
2417                 0x35300, 0x35300,
2418                 0x35308, 0x3531c,
2419                 0x35338, 0x3533c,
2420                 0x35380, 0x35380,
2421                 0x35388, 0x353a8,
2422                 0x353b4, 0x353b4,
2423                 0x35400, 0x35420,
2424                 0x35438, 0x3543c,
2425                 0x35480, 0x35480,
2426                 0x354a8, 0x354a8,
2427                 0x354b0, 0x354b4,
2428                 0x354c8, 0x354d4,
2429                 0x35a40, 0x35a4c,
2430                 0x35af0, 0x35b20,
2431                 0x35b38, 0x35b3c,
2432                 0x35b80, 0x35b80,
2433                 0x35ba8, 0x35ba8,
2434                 0x35bb0, 0x35bb4,
2435                 0x35bc8, 0x35bd4,
2436                 0x36140, 0x3618c,
2437                 0x361f0, 0x361f4,
2438                 0x36200, 0x36200,
2439                 0x36218, 0x36218,
2440                 0x36400, 0x36400,
2441                 0x36408, 0x3641c,
2442                 0x36618, 0x36620,
2443                 0x36664, 0x36664,
2444                 0x366a8, 0x366a8,
2445                 0x366ec, 0x366ec,
2446                 0x36a00, 0x36abc,
2447                 0x36b00, 0x36b18,
2448                 0x36b20, 0x36b38,
2449                 0x36b40, 0x36b58,
2450                 0x36b60, 0x36b78,
2451                 0x36c00, 0x36c00,
2452                 0x36c08, 0x36c3c,
2453                 0x37000, 0x3702c,
2454                 0x37034, 0x37050,
2455                 0x37058, 0x37058,
2456                 0x37060, 0x3708c,
2457                 0x3709c, 0x370ac,
2458                 0x370c0, 0x370c0,
2459                 0x370c8, 0x370d0,
2460                 0x370d8, 0x370e0,
2461                 0x370ec, 0x3712c,
2462                 0x37134, 0x37150,
2463                 0x37158, 0x37158,
2464                 0x37160, 0x3718c,
2465                 0x3719c, 0x371ac,
2466                 0x371c0, 0x371c0,
2467                 0x371c8, 0x371d0,
2468                 0x371d8, 0x371e0,
2469                 0x371ec, 0x37290,
2470                 0x37298, 0x372c4,
2471                 0x372e4, 0x37390,
2472                 0x37398, 0x373c4,
2473                 0x373e4, 0x3742c,
2474                 0x37434, 0x37450,
2475                 0x37458, 0x37458,
2476                 0x37460, 0x3748c,
2477                 0x3749c, 0x374ac,
2478                 0x374c0, 0x374c0,
2479                 0x374c8, 0x374d0,
2480                 0x374d8, 0x374e0,
2481                 0x374ec, 0x3752c,
2482                 0x37534, 0x37550,
2483                 0x37558, 0x37558,
2484                 0x37560, 0x3758c,
2485                 0x3759c, 0x375ac,
2486                 0x375c0, 0x375c0,
2487                 0x375c8, 0x375d0,
2488                 0x375d8, 0x375e0,
2489                 0x375ec, 0x37690,
2490                 0x37698, 0x376c4,
2491                 0x376e4, 0x37790,
2492                 0x37798, 0x377c4,
2493                 0x377e4, 0x377fc,
2494                 0x37814, 0x37814,
2495                 0x37854, 0x37868,
2496                 0x37880, 0x3788c,
2497                 0x378c0, 0x378d0,
2498                 0x378e8, 0x378ec,
2499                 0x37900, 0x3792c,
2500                 0x37934, 0x37950,
2501                 0x37958, 0x37958,
2502                 0x37960, 0x3798c,
2503                 0x3799c, 0x379ac,
2504                 0x379c0, 0x379c0,
2505                 0x379c8, 0x379d0,
2506                 0x379d8, 0x379e0,
2507                 0x379ec, 0x37a90,
2508                 0x37a98, 0x37ac4,
2509                 0x37ae4, 0x37b10,
2510                 0x37b24, 0x37b28,
2511                 0x37b38, 0x37b50,
2512                 0x37bf0, 0x37c10,
2513                 0x37c24, 0x37c28,
2514                 0x37c38, 0x37c50,
2515                 0x37cf0, 0x37cfc,
2516                 0x40040, 0x40040,
2517                 0x40080, 0x40084,
2518                 0x40100, 0x40100,
2519                 0x40140, 0x401bc,
2520                 0x40200, 0x40214,
2521                 0x40228, 0x40228,
2522                 0x40240, 0x40258,
2523                 0x40280, 0x40280,
2524                 0x40304, 0x40304,
2525                 0x40330, 0x4033c,
2526                 0x41304, 0x413c8,
2527                 0x413d0, 0x413dc,
2528                 0x413f0, 0x413f0,
2529                 0x41400, 0x4140c,
2530                 0x41414, 0x4141c,
2531                 0x41480, 0x414d0,
2532                 0x44000, 0x4407c,
2533                 0x440c0, 0x441ac,
2534                 0x441b4, 0x4427c,
2535                 0x442c0, 0x443ac,
2536                 0x443b4, 0x4447c,
2537                 0x444c0, 0x445ac,
2538                 0x445b4, 0x4467c,
2539                 0x446c0, 0x447ac,
2540                 0x447b4, 0x4487c,
2541                 0x448c0, 0x449ac,
2542                 0x449b4, 0x44a7c,
2543                 0x44ac0, 0x44bac,
2544                 0x44bb4, 0x44c7c,
2545                 0x44cc0, 0x44dac,
2546                 0x44db4, 0x44e7c,
2547                 0x44ec0, 0x44fac,
2548                 0x44fb4, 0x4507c,
2549                 0x450c0, 0x451ac,
2550                 0x451b4, 0x451fc,
2551                 0x45800, 0x45804,
2552                 0x45810, 0x45830,
2553                 0x45840, 0x45860,
2554                 0x45868, 0x45868,
2555                 0x45880, 0x45884,
2556                 0x458a0, 0x458b0,
2557                 0x45a00, 0x45a04,
2558                 0x45a10, 0x45a30,
2559                 0x45a40, 0x45a60,
2560                 0x45a68, 0x45a68,
2561                 0x45a80, 0x45a84,
2562                 0x45aa0, 0x45ab0,
2563                 0x460c0, 0x460e4,
2564                 0x47000, 0x4703c,
2565                 0x47044, 0x4708c,
2566                 0x47200, 0x47250,
2567                 0x47400, 0x47408,
2568                 0x47414, 0x47420,
2569                 0x47600, 0x47618,
2570                 0x47800, 0x47814,
2571                 0x47820, 0x4782c,
2572                 0x50000, 0x50084,
2573                 0x50090, 0x500cc,
2574                 0x50300, 0x50384,
2575                 0x50400, 0x50400,
2576                 0x50800, 0x50884,
2577                 0x50890, 0x508cc,
2578                 0x50b00, 0x50b84,
2579                 0x50c00, 0x50c00,
2580                 0x51000, 0x51020,
2581                 0x51028, 0x510b0,
2582                 0x51300, 0x51324,
2583         };
2584
2585         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2586         const unsigned int *reg_ranges;
2587         int reg_ranges_size, range;
2588         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2589
2590         /* Select the right set of register ranges to dump depending on the
2591          * adapter chip type.
2592          */
2593         switch (chip_version) {
2594         case CHELSIO_T4:
2595                 reg_ranges = t4_reg_ranges;
2596                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2597                 break;
2598
2599         case CHELSIO_T5:
2600                 reg_ranges = t5_reg_ranges;
2601                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2602                 break;
2603
2604         case CHELSIO_T6:
2605                 reg_ranges = t6_reg_ranges;
2606                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2607                 break;
2608
2609         default:
2610                 dev_err(adap->pdev_dev,
2611                         "Unsupported chip version %d\n", chip_version);
2612                 return;
2613         }
2614
2615         /* Clear the register buffer and insert the appropriate register
2616          * values selected by the above register ranges.
2617          */
2618         memset(buf, 0, buf_size);
2619         for (range = 0; range < reg_ranges_size; range += 2) {
2620                 unsigned int reg = reg_ranges[range];
2621                 unsigned int last_reg = reg_ranges[range + 1];
2622                 u32 *bufp = (u32 *)((char *)buf + reg);
2623
2624                 /* Iterate across the register range filling in the register
2625                  * buffer but don't write past the end of the register buffer.
2626                  */
2627                 while (reg <= last_reg && bufp < buf_end) {
2628                         *bufp++ = t4_read_reg(adap, reg);
2629                         reg += sizeof(u32);
2630                 }
2631         }
2632 }
2633
2634 #define EEPROM_STAT_ADDR   0x7bfc
2635 #define VPD_SIZE           0x800
2636 #define VPD_BASE           0x400
2637 #define VPD_BASE_OLD       0
2638 #define VPD_LEN            1024
2639 #define CHELSIO_VPD_UNIQUE_ID 0x82
2640
2641 /**
2642  *      t4_seeprom_wp - enable/disable EEPROM write protection
2643  *      @adapter: the adapter
2644  *      @enable: whether to enable or disable write protection
2645  *
2646  *      Enables or disables write protection on the serial EEPROM.
2647  */
2648 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2649 {
2650         unsigned int v = enable ? 0xc : 0;
2651         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2652         return ret < 0 ? ret : 0;
2653 }
2654
2655 /**
2656  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2657  *      @adapter: adapter to read
2658  *      @p: where to store the parameters
2659  *
2660  *      Reads card parameters stored in VPD EEPROM.
2661  */
2662 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2663 {
2664         int i, ret = 0, addr;
2665         int ec, sn, pn, na;
2666         u8 *vpd, csum;
2667         unsigned int vpdr_len, kw_offset, id_len;
2668
2669         vpd = vmalloc(VPD_LEN);
2670         if (!vpd)
2671                 return -ENOMEM;
2672
2673         /* We have two VPD data structures stored in the adapter VPD area.
2674          * By default, Linux calculates the size of the VPD area by traversing
2675          * the first VPD area at offset 0x0, so we need to tell the OS what
2676          * our real VPD size is.
2677          */
2678         ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2679         if (ret < 0)
2680                 goto out;
2681
2682         /* Card information normally starts at VPD_BASE but early cards had
2683          * it at 0.
2684          */
2685         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2686         if (ret < 0)
2687                 goto out;
2688
2689         /* The VPD shall have a unique identifier specified by the PCI SIG.
2690          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2691          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2692          * is expected to automatically put this entry at the
2693          * beginning of the VPD.
2694          */
2695         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2696
2697         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2698         if (ret < 0)
2699                 goto out;
2700
2701         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2702                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2703                 ret = -EINVAL;
2704                 goto out;
2705         }
2706
2707         id_len = pci_vpd_lrdt_size(vpd);
2708         if (id_len > ID_LEN)
2709                 id_len = ID_LEN;
2710
2711         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2712         if (i < 0) {
2713                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2714                 ret = -EINVAL;
2715                 goto out;
2716         }
2717
2718         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2719         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2720         if (vpdr_len + kw_offset > VPD_LEN) {
2721                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2722                 ret = -EINVAL;
2723                 goto out;
2724         }
2725
2726 #define FIND_VPD_KW(var, name) do { \
2727         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2728         if (var < 0) { \
2729                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2730                 ret = -EINVAL; \
2731                 goto out; \
2732         } \
2733         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2734 } while (0)
2735
2736         FIND_VPD_KW(i, "RV");
2737         for (csum = 0; i >= 0; i--)
2738                 csum += vpd[i];
2739
2740         if (csum) {
2741                 dev_err(adapter->pdev_dev,
2742                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2743                 ret = -EINVAL;
2744                 goto out;
2745         }
2746
2747         FIND_VPD_KW(ec, "EC");
2748         FIND_VPD_KW(sn, "SN");
2749         FIND_VPD_KW(pn, "PN");
2750         FIND_VPD_KW(na, "NA");
2751 #undef FIND_VPD_KW
2752
2753         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2754         strim(p->id);
2755         memcpy(p->ec, vpd + ec, EC_LEN);
2756         strim(p->ec);
2757         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2758         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2759         strim(p->sn);
2760         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2761         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2762         strim(p->pn);
2763         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2764         strim((char *)p->na);
2765
2766 out:
2767         vfree(vpd);
2768         return ret < 0 ? ret : 0;
2769 }
2770
2771 /**
2772  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2773  *      @adapter: adapter to read
2774  *      @p: where to store the parameters
2775  *
2776  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2777  *      Clock.  This can only be called after a connection to the firmware
2778  *      is established.
2779  */
2780 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2781 {
2782         u32 cclk_param, cclk_val;
2783         int ret;
2784
2785         /* Grab the raw VPD parameters.
2786          */
2787         ret = t4_get_raw_vpd_params(adapter, p);
2788         if (ret)
2789                 return ret;
2790
2791         /* Ask firmware for the Core Clock since it knows how to translate the
2792          * Reference Clock ('V2') VPD field into a Core Clock value ...
2793          */
2794         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2795                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2796         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2797                               1, &cclk_param, &cclk_val);
2798
2799         if (ret)
2800                 return ret;
2801         p->cclk = cclk_val;
2802
2803         return 0;
2804 }
2805
2806 /* serial flash and firmware constants */
2807 enum {
2808         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2809
2810         /* flash command opcodes */
2811         SF_PROG_PAGE    = 2,          /* program page */
2812         SF_WR_DISABLE   = 4,          /* disable writes */
2813         SF_RD_STATUS    = 5,          /* read status register */
2814         SF_WR_ENABLE    = 6,          /* enable writes */
2815         SF_RD_DATA_FAST = 0xb,        /* read flash */
2816         SF_RD_ID        = 0x9f,       /* read ID */
2817         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2818
2819         FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2820 };
2821
2822 /**
2823  *      sf1_read - read data from the serial flash
2824  *      @adapter: the adapter
2825  *      @byte_cnt: number of bytes to read
2826  *      @cont: whether another operation will be chained
2827  *      @lock: whether to lock SF for PL access only
2828  *      @valp: where to store the read data
2829  *
2830  *      Reads up to 4 bytes of data from the serial flash.  The location of
2831  *      the read needs to be specified prior to calling this by issuing the
2832  *      appropriate commands to the serial flash.
2833  */
2834 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2835                     int lock, u32 *valp)
2836 {
2837         int ret;
2838
2839         if (!byte_cnt || byte_cnt > 4)
2840                 return -EINVAL;
2841         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2842                 return -EBUSY;
2843         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2844                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2845         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2846         if (!ret)
2847                 *valp = t4_read_reg(adapter, SF_DATA_A);
2848         return ret;
2849 }
2850
2851 /**
2852  *      sf1_write - write data to the serial flash
2853  *      @adapter: the adapter
2854  *      @byte_cnt: number of bytes to write
2855  *      @cont: whether another operation will be chained
2856  *      @lock: whether to lock SF for PL access only
2857  *      @val: value to write
2858  *
2859  *      Writes up to 4 bytes of data to the serial flash.  The location of
2860  *      the write needs to be specified prior to calling this by issuing the
2861  *      appropriate commands to the serial flash.
2862  */
2863 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2864                      int lock, u32 val)
2865 {
2866         if (!byte_cnt || byte_cnt > 4)
2867                 return -EINVAL;
2868         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2869                 return -EBUSY;
2870         t4_write_reg(adapter, SF_DATA_A, val);
2871         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2872                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2873         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2874 }
2875
2876 /**
2877  *      flash_wait_op - wait for a flash operation to complete
2878  *      @adapter: the adapter
2879  *      @attempts: max number of polls of the status register
2880  *      @delay: delay between polls in ms
2881  *
2882  *      Wait for a flash operation to complete by polling the status register.
2883  */
2884 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2885 {
2886         int ret;
2887         u32 status;
2888
2889         while (1) {
2890                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2891                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2892                         return ret;
2893                 if (!(status & 1))
2894                         return 0;
2895                 if (--attempts == 0)
2896                         return -EAGAIN;
2897                 if (delay)
2898                         msleep(delay);
2899         }
2900 }
2901
2902 /**
2903  *      t4_read_flash - read words from serial flash
2904  *      @adapter: the adapter
2905  *      @addr: the start address for the read
2906  *      @nwords: how many 32-bit words to read
2907  *      @data: where to store the read data
2908  *      @byte_oriented: whether to store data as bytes or as words
2909  *
2910  *      Read the specified number of 32-bit words from the serial flash.
2911  *      If @byte_oriented is set the read data is stored as a byte array
2912  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2913  *      natural endianness.
2914  */
2915 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2916                   unsigned int nwords, u32 *data, int byte_oriented)
2917 {
2918         int ret;
2919
2920         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2921                 return -EINVAL;
2922
2923         addr = swab32(addr) | SF_RD_DATA_FAST;
2924
2925         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2926             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2927                 return ret;
2928
2929         for ( ; nwords; nwords--, data++) {
2930                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2931                 if (nwords == 1)
2932                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2933                 if (ret)
2934                         return ret;
2935                 if (byte_oriented)
2936                         *data = (__force __u32)(cpu_to_be32(*data));
2937         }
2938         return 0;
2939 }
2940
2941 /**
2942  *      t4_write_flash - write up to a page of data to the serial flash
2943  *      @adapter: the adapter
2944  *      @addr: the start address to write
2945  *      @n: length of data to write in bytes
2946  *      @data: the data to write
2947  *
2948  *      Writes up to a page of data (256 bytes) to the serial flash starting
2949  *      at the given address.  All the data must be written to the same page.
2950  */
2951 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2952                           unsigned int n, const u8 *data)
2953 {
2954         int ret;
2955         u32 buf[64];
2956         unsigned int i, c, left, val, offset = addr & 0xff;
2957
2958         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2959                 return -EINVAL;
2960
2961         val = swab32(addr) | SF_PROG_PAGE;
2962
2963         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2964             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2965                 goto unlock;
2966
2967         for (left = n; left; left -= c) {
2968                 c = min(left, 4U);
2969                 for (val = 0, i = 0; i < c; ++i)
2970                         val = (val << 8) + *data++;
2971
2972                 ret = sf1_write(adapter, c, c != left, 1, val);
2973                 if (ret)
2974                         goto unlock;
2975         }
2976         ret = flash_wait_op(adapter, 8, 1);
2977         if (ret)
2978                 goto unlock;
2979
2980         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2981
2982         /* Read the page to verify the write succeeded */
2983         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2984         if (ret)
2985                 return ret;
2986
2987         if (memcmp(data - n, (u8 *)buf + offset, n)) {
2988                 dev_err(adapter->pdev_dev,
2989                         "failed to correctly write the flash page at %#x\n",
2990                         addr);
2991                 return -EIO;
2992         }
2993         return 0;
2994
2995 unlock:
2996         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2997         return ret;
2998 }
2999
3000 /**
3001  *      t4_get_fw_version - read the firmware version
3002  *      @adapter: the adapter
3003  *      @vers: where to place the version
3004  *
3005  *      Reads the FW version from flash.
3006  */
3007 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3008 {
3009         return t4_read_flash(adapter, FLASH_FW_START +
3010                              offsetof(struct fw_hdr, fw_ver), 1,
3011                              vers, 0);
3012 }
3013
3014 /**
3015  *      t4_get_bs_version - read the firmware bootstrap version
3016  *      @adapter: the adapter
3017  *      @vers: where to place the version
3018  *
3019  *      Reads the FW Bootstrap version from flash.
3020  */
3021 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3022 {
3023         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3024                              offsetof(struct fw_hdr, fw_ver), 1,
3025                              vers, 0);
3026 }
3027
3028 /**
3029  *      t4_get_tp_version - read the TP microcode version
3030  *      @adapter: the adapter
3031  *      @vers: where to place the version
3032  *
3033  *      Reads the TP microcode version from flash.
3034  */
3035 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3036 {
3037         return t4_read_flash(adapter, FLASH_FW_START +
3038                              offsetof(struct fw_hdr, tp_microcode_ver),
3039                              1, vers, 0);
3040 }
3041
3042 /**
3043  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3044  *      @adapter: the adapter
3045  *      @vers: where to place the version
3046  *
3047  *      Reads the Expansion ROM header from FLASH and returns the version
3048  *      number (if present) through the @vers return value pointer.  We return
3049  *      this in the Firmware Version Format since it's convenient.  Return
3050  *      0 on success, -ENOENT if no Expansion ROM is present.
3051  */
3052 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3053 {
3054         struct exprom_header {
3055                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3056                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3057         } *hdr;
3058         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3059                                            sizeof(u32))];
3060         int ret;
3061
3062         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3063                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3064                             0);
3065         if (ret)
3066                 return ret;
3067
3068         hdr = (struct exprom_header *)exprom_header_buf;
3069         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3070                 return -ENOENT;
3071
3072         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3073                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3074                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3075                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3076         return 0;
3077 }
3078
3079 /**
3080  *      t4_get_vpd_version - return the VPD version
3081  *      @adapter: the adapter
3082  *      @vers: where to place the version
3083  *
3084  *      Reads the VPD via the Firmware interface (thus this can only be called
3085  *      once we're ready to issue Firmware commands).  The format of the
3086  *      VPD version is adapter specific.  Returns 0 on success, an error on
3087  *      failure.
3088  *
3089  *      Note that early versions of the Firmware didn't include the ability
3090  *      to retrieve the VPD version, so we zero-out the return-value parameter
3091  *      in that case to avoid leaving it with garbage in it.
3092  *
3093  *      Also note that the Firmware will return its cached copy of the VPD
3094  *      Revision ID, not the actual Revision ID as written in the Serial
3095  *      EEPROM.  This is only an issue if a new VPD has been written and the
3096  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3097  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3098  *      if the Host Driver will be performing a full adapter initialization.
3099  */
3100 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3101 {
3102         u32 vpdrev_param;
3103         int ret;
3104
3105         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3106                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3107         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3108                               1, &vpdrev_param, vers);
3109         if (ret)
3110                 *vers = 0;
3111         return ret;
3112 }
3113
3114 /**
3115  *      t4_get_scfg_version - return the Serial Configuration version
3116  *      @adapter: the adapter
3117  *      @vers: where to place the version
3118  *
3119  *      Reads the Serial Configuration Version via the Firmware interface
3120  *      (thus this can only be called once we're ready to issue Firmware
3121  *      commands).  The format of the Serial Configuration version is
3122  *      adapter specific.  Returns 0 on success, an error on failure.
3123  *
3124  *      Note that early versions of the Firmware didn't include the ability
3125  *      to retrieve the Serial Configuration version, so we zero-out the
3126  *      return-value parameter in that case to avoid leaving it with
3127  *      garbage in it.
3128  *
3129  *      Also note that the Firmware will return its cached copy of the Serial
3130  *      Initialization Revision ID, not the actual Revision ID as written in
3131  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3132  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3133  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3134  *      been issued if the Host Driver will be performing a full adapter
3135  *      initialization.
3136  */
3137 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3138 {
3139         u32 scfgrev_param;
3140         int ret;
3141
3142         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3143                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3144         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3145                               1, &scfgrev_param, vers);
3146         if (ret)
3147                 *vers = 0;
3148         return ret;
3149 }
3150
3151 /**
3152  *      t4_get_version_info - extract various chip/firmware version information
3153  *      @adapter: the adapter
3154  *
3155  *      Reads various chip/firmware version numbers and stores them into the
3156  *      adapter Adapter Parameters structure.  If any of the efforts fails
3157  *      the first failure will be returned, but all of the version numbers
3158  *      will be read.
3159  */
3160 int t4_get_version_info(struct adapter *adapter)
3161 {
3162         int ret = 0;
3163
3164         #define FIRST_RET(__getvinfo) \
3165         do { \
3166                 int __ret = __getvinfo; \
3167                 if (__ret && !ret) \
3168                         ret = __ret; \
3169         } while (0)
3170
3171         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3172         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3173         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3174         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3175         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3176         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3177
3178         #undef FIRST_RET
3179         return ret;
3180 }
3181
3182 /**
3183  *      t4_dump_version_info - dump all of the adapter configuration IDs
3184  *      @adapter: the adapter
3185  *
3186  *      Dumps all of the various bits of adapter configuration version/revision
3187  *      IDs information.  This is typically called at some point after
3188  *      t4_get_version_info() has been called.
3189  */
3190 void t4_dump_version_info(struct adapter *adapter)
3191 {
3192         /* Device information */
3193         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3194                  adapter->params.vpd.id,
3195                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3196         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3197                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3198
3199         /* Firmware Version */
3200         if (!adapter->params.fw_vers)
3201                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3202         else
3203                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3204                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3205                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3206                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3207                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3208
3209         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3210          * Firmware, so dev_info() is more appropriate here.)
3211          */
3212         if (!adapter->params.bs_vers)
3213                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3214         else
3215                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3216                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3217                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3218                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3219                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3220
3221         /* TP Microcode Version */
3222         if (!adapter->params.tp_vers)
3223                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3224         else
3225                 dev_info(adapter->pdev_dev,
3226                          "TP Microcode version: %u.%u.%u.%u\n",
3227                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3228                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3229                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3230                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3231
3232         /* Expansion ROM version */
3233         if (!adapter->params.er_vers)
3234                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3235         else
3236                 dev_info(adapter->pdev_dev,
3237                          "Expansion ROM version: %u.%u.%u.%u\n",
3238                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3239                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3240                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3241                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3242
3243         /* Serial Configuration version */
3244         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3245                  adapter->params.scfg_vers);
3246
3247         /* VPD Version */
3248         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3249                  adapter->params.vpd_vers);
3250 }
3251
3252 /**
3253  *      t4_check_fw_version - check if the FW is supported with this driver
3254  *      @adap: the adapter
3255  *
3256  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3257  *      if there's exact match, a negative error if the version could not be
3258  *      read or there's a major version mismatch
3259  */
3260 int t4_check_fw_version(struct adapter *adap)
3261 {
3262         int i, ret, major, minor, micro;
3263         int exp_major, exp_minor, exp_micro;
3264         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3265
3266         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3267         /* Try multiple times before returning error */
3268         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3269                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3270
3271         if (ret)
3272                 return ret;
3273
3274         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3275         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3276         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3277
3278         switch (chip_version) {
3279         case CHELSIO_T4:
3280                 exp_major = T4FW_MIN_VERSION_MAJOR;
3281                 exp_minor = T4FW_MIN_VERSION_MINOR;
3282                 exp_micro = T4FW_MIN_VERSION_MICRO;
3283                 break;
3284         case CHELSIO_T5:
3285                 exp_major = T5FW_MIN_VERSION_MAJOR;
3286                 exp_minor = T5FW_MIN_VERSION_MINOR;
3287                 exp_micro = T5FW_MIN_VERSION_MICRO;
3288                 break;
3289         case CHELSIO_T6:
3290                 exp_major = T6FW_MIN_VERSION_MAJOR;
3291                 exp_minor = T6FW_MIN_VERSION_MINOR;
3292                 exp_micro = T6FW_MIN_VERSION_MICRO;
3293                 break;
3294         default:
3295                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3296                         adap->chip);
3297                 return -EINVAL;
3298         }
3299
3300         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3301             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3302                 dev_err(adap->pdev_dev,
3303                         "Card has firmware version %u.%u.%u, minimum "
3304                         "supported firmware is %u.%u.%u.\n", major, minor,
3305                         micro, exp_major, exp_minor, exp_micro);
3306                 return -EFAULT;
3307         }
3308         return 0;
3309 }
3310
3311 /* Is the given firmware API compatible with the one the driver was compiled
3312  * with?
3313  */
3314 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3315 {
3316
3317         /* short circuit if it's the exact same firmware version */
3318         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3319                 return 1;
3320
3321 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3322         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3323             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3324                 return 1;
3325 #undef SAME_INTF
3326
3327         return 0;
3328 }
3329
3330 /* The firmware in the filesystem is usable, but should it be installed?
3331  * This routine explains itself in detail if it indicates the filesystem
3332  * firmware should be installed.
3333  */
3334 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3335                                 int k, int c)
3336 {
3337         const char *reason;
3338
3339         if (!card_fw_usable) {
3340                 reason = "incompatible or unusable";
3341                 goto install;
3342         }
3343
3344         if (k > c) {
3345                 reason = "older than the version supported with this driver";
3346                 goto install;
3347         }
3348
3349         return 0;
3350
3351 install:
3352         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3353                 "installing firmware %u.%u.%u.%u on card.\n",
3354                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3355                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3356                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3357                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3358
3359         return 1;
3360 }
3361
3362 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3363                const u8 *fw_data, unsigned int fw_size,
3364                struct fw_hdr *card_fw, enum dev_state state,
3365                int *reset)
3366 {
3367         int ret, card_fw_usable, fs_fw_usable;
3368         const struct fw_hdr *fs_fw;
3369         const struct fw_hdr *drv_fw;
3370
3371         drv_fw = &fw_info->fw_hdr;
3372
3373         /* Read the header of the firmware on the card */
3374         ret = -t4_read_flash(adap, FLASH_FW_START,
3375                             sizeof(*card_fw) / sizeof(uint32_t),
3376                             (uint32_t *)card_fw, 1);
3377         if (ret == 0) {
3378                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3379         } else {
3380                 dev_err(adap->pdev_dev,
3381                         "Unable to read card's firmware header: %d\n", ret);
3382                 card_fw_usable = 0;
3383         }
3384
3385         if (fw_data != NULL) {
3386                 fs_fw = (const void *)fw_data;
3387                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3388         } else {
3389                 fs_fw = NULL;
3390                 fs_fw_usable = 0;
3391         }
3392
3393         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3394             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3395                 /* Common case: the firmware on the card is an exact match and
3396                  * the filesystem one is an exact match too, or the filesystem
3397                  * one is absent/incompatible.
3398                  */
3399         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3400                    should_install_fs_fw(adap, card_fw_usable,
3401                                         be32_to_cpu(fs_fw->fw_ver),
3402                                         be32_to_cpu(card_fw->fw_ver))) {
3403                 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3404                                      fw_size, 0);
3405                 if (ret != 0) {
3406                         dev_err(adap->pdev_dev,
3407                                 "failed to install firmware: %d\n", ret);
3408                         goto bye;
3409                 }
3410
3411                 /* Installed successfully, update the cached header too. */
3412                 *card_fw = *fs_fw;
3413                 card_fw_usable = 1;
3414                 *reset = 0;     /* already reset as part of load_fw */
3415         }
3416
3417         if (!card_fw_usable) {
3418                 uint32_t d, c, k;
3419
3420                 d = be32_to_cpu(drv_fw->fw_ver);
3421                 c = be32_to_cpu(card_fw->fw_ver);
3422                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3423
3424                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3425                         "chip state %d, "
3426                         "driver compiled with %d.%d.%d.%d, "
3427                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3428                         state,
3429                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3430                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3431                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3432                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3433                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3434                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3435                 ret = EINVAL;
3436                 goto bye;
3437         }
3438
3439         /* We're using whatever's on the card and it's known to be good. */
3440         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3441         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3442
3443 bye:
3444         return ret;
3445 }
3446
3447 /**
3448  *      t4_flash_erase_sectors - erase a range of flash sectors
3449  *      @adapter: the adapter
3450  *      @start: the first sector to erase
3451  *      @end: the last sector to erase
3452  *
3453  *      Erases the sectors in the given inclusive range.
3454  */
3455 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3456 {
3457         int ret = 0;
3458
3459         if (end >= adapter->params.sf_nsec)
3460                 return -EINVAL;
3461
3462         while (start <= end) {
3463                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3464                     (ret = sf1_write(adapter, 4, 0, 1,
3465                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3466                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3467                         dev_err(adapter->pdev_dev,
3468                                 "erase of flash sector %d failed, error %d\n",
3469                                 start, ret);
3470                         break;
3471                 }
3472                 start++;
3473         }
3474         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3475         return ret;
3476 }
3477
3478 /**
3479  *      t4_flash_cfg_addr - return the address of the flash configuration file
3480  *      @adapter: the adapter
3481  *
3482  *      Return the address within the flash where the Firmware Configuration
3483  *      File is stored.
3484  */
3485 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3486 {
3487         if (adapter->params.sf_size == 0x100000)
3488                 return FLASH_FPGA_CFG_START;
3489         else
3490                 return FLASH_CFG_START;
3491 }
3492
3493 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3494  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3495  * and emit an error message for mismatched firmware to save our caller the
3496  * effort ...
3497  */
3498 static bool t4_fw_matches_chip(const struct adapter *adap,
3499                                const struct fw_hdr *hdr)
3500 {
3501         /* The expression below will return FALSE for any unsupported adapter
3502          * which will keep us "honest" in the future ...
3503          */
3504         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3505             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3506             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3507                 return true;
3508
3509         dev_err(adap->pdev_dev,
3510                 "FW image (%d) is not suitable for this adapter (%d)\n",
3511                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3512         return false;
3513 }
3514
3515 /**
3516  *      t4_load_fw - download firmware
3517  *      @adap: the adapter
3518  *      @fw_data: the firmware image to write
3519  *      @size: image size
3520  *
3521  *      Write the supplied firmware image to the card's serial flash.
3522  */
3523 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3524 {
3525         u32 csum;
3526         int ret, addr;
3527         unsigned int i;
3528         u8 first_page[SF_PAGE_SIZE];
3529         const __be32 *p = (const __be32 *)fw_data;
3530         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3531         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3532         unsigned int fw_img_start = adap->params.sf_fw_start;
3533         unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3534
3535         if (!size) {
3536                 dev_err(adap->pdev_dev, "FW image has no data\n");
3537                 return -EINVAL;
3538         }
3539         if (size & 511) {
3540                 dev_err(adap->pdev_dev,
3541                         "FW image size not multiple of 512 bytes\n");
3542                 return -EINVAL;
3543         }
3544         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3545                 dev_err(adap->pdev_dev,
3546                         "FW image size differs from size in FW header\n");
3547                 return -EINVAL;
3548         }
3549         if (size > FW_MAX_SIZE) {
3550                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3551                         FW_MAX_SIZE);
3552                 return -EFBIG;
3553         }
3554         if (!t4_fw_matches_chip(adap, hdr))
3555                 return -EINVAL;
3556
3557         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3558                 csum += be32_to_cpu(p[i]);
3559
3560         if (csum != 0xffffffff) {
3561                 dev_err(adap->pdev_dev,
3562                         "corrupted firmware image, checksum %#x\n", csum);
3563                 return -EINVAL;
3564         }
3565
3566         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3567         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3568         if (ret)
3569                 goto out;
3570
3571         /*
3572          * We write the correct version at the end so the driver can see a bad
3573          * version if the FW write fails.  Start by writing a copy of the
3574          * first page with a bad version.
3575          */
3576         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3577         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3578         ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3579         if (ret)
3580                 goto out;
3581
3582         addr = fw_img_start;
3583         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3584                 addr += SF_PAGE_SIZE;
3585                 fw_data += SF_PAGE_SIZE;
3586                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3587                 if (ret)
3588                         goto out;
3589         }
3590
3591         ret = t4_write_flash(adap,
3592                              fw_img_start + offsetof(struct fw_hdr, fw_ver),
3593                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3594 out:
3595         if (ret)
3596                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3597                         ret);
3598         else
3599                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3600         return ret;
3601 }
3602
3603 /**
3604  *      t4_phy_fw_ver - return current PHY firmware version
3605  *      @adap: the adapter
3606  *      @phy_fw_ver: return value buffer for PHY firmware version
3607  *
3608  *      Returns the current version of external PHY firmware on the
3609  *      adapter.
3610  */
3611 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3612 {
3613         u32 param, val;
3614         int ret;
3615
3616         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3617                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3618                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3619                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3620         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3621                               &param, &val);
3622         if (ret < 0)
3623                 return ret;
3624         *phy_fw_ver = val;
3625         return 0;
3626 }
3627
3628 /**
3629  *      t4_load_phy_fw - download port PHY firmware
3630  *      @adap: the adapter
3631  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3632  *      @win_lock: the lock to use to guard the memory copy
3633  *      @phy_fw_version: function to check PHY firmware versions
3634  *      @phy_fw_data: the PHY firmware image to write
3635  *      @phy_fw_size: image size
3636  *
3637  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3638  *      @phy_fw_version is supplied, then it will be used to determine if
3639  *      it's necessary to perform the transfer by comparing the version
3640  *      of any existing adapter PHY firmware with that of the passed in
3641  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3642  *      around the call to t4_memory_rw() which transfers the PHY firmware
3643  *      to the adapter.
3644  *
3645  *      A negative error number will be returned if an error occurs.  If
3646  *      version number support is available and there's no need to upgrade
3647  *      the firmware, 0 will be returned.  If firmware is successfully
3648  *      transferred to the adapter, 1 will be retured.
3649  *
3650  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3651  *      a result, a RESET of the adapter would cause that RAM to lose its
3652  *      contents.  Thus, loading PHY firmware on such adapters must happen
3653  *      after any FW_RESET_CMDs ...
3654  */
3655 int t4_load_phy_fw(struct adapter *adap,
3656                    int win, spinlock_t *win_lock,
3657                    int (*phy_fw_version)(const u8 *, size_t),
3658                    const u8 *phy_fw_data, size_t phy_fw_size)
3659 {
3660         unsigned long mtype = 0, maddr = 0;
3661         u32 param, val;
3662         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3663         int ret;
3664
3665         /* If we have version number support, then check to see if the adapter
3666          * already has up-to-date PHY firmware loaded.
3667          */
3668          if (phy_fw_version) {
3669                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3670                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3671                 if (ret < 0)
3672                         return ret;
3673
3674                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3675                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3676                                 "version %#x\n", cur_phy_fw_ver);
3677                         return 0;
3678                 }
3679         }
3680
3681         /* Ask the firmware where it wants us to copy the PHY firmware image.
3682          * The size of the file requires a special version of the READ coommand
3683          * which will pass the file size via the values field in PARAMS_CMD and
3684          * retrieve the return value from firmware and place it in the same
3685          * buffer values
3686          */
3687         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3688                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3689                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3690                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3691         val = phy_fw_size;
3692         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3693                                  &param, &val, 1, true);
3694         if (ret < 0)
3695                 return ret;
3696         mtype = val >> 8;
3697         maddr = (val & 0xff) << 16;
3698
3699         /* Copy the supplied PHY Firmware image to the adapter memory location
3700          * allocated by the adapter firmware.
3701          */
3702         if (win_lock)
3703                 spin_lock_bh(win_lock);
3704         ret = t4_memory_rw(adap, win, mtype, maddr,
3705                            phy_fw_size, (__be32 *)phy_fw_data,
3706                            T4_MEMORY_WRITE);
3707         if (win_lock)
3708                 spin_unlock_bh(win_lock);
3709         if (ret)
3710                 return ret;
3711
3712         /* Tell the firmware that the PHY firmware image has been written to
3713          * RAM and it can now start copying it over to the PHYs.  The chip
3714          * firmware will RESET the affected PHYs as part of this operation
3715          * leaving them running the new PHY firmware image.
3716          */
3717         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3718                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3719                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3720                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3721         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3722                                     &param, &val, 30000);
3723
3724         /* If we have version number support, then check to see that the new
3725          * firmware got loaded properly.
3726          */
3727         if (phy_fw_version) {
3728                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3729                 if (ret < 0)
3730                         return ret;
3731
3732                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3733                         CH_WARN(adap, "PHY Firmware did not update: "
3734                                 "version on adapter %#x, "
3735                                 "version flashed %#x\n",
3736                                 cur_phy_fw_ver, new_phy_fw_vers);
3737                         return -ENXIO;
3738                 }
3739         }
3740
3741         return 1;
3742 }
3743
3744 /**
3745  *      t4_fwcache - firmware cache operation
3746  *      @adap: the adapter
3747  *      @op  : the operation (flush or flush and invalidate)
3748  */
3749 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3750 {
3751         struct fw_params_cmd c;
3752
3753         memset(&c, 0, sizeof(c));
3754         c.op_to_vfn =
3755                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3756                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3757                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3758                             FW_PARAMS_CMD_VFN_V(0));
3759         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3760         c.param[0].mnem =
3761                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3762                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3763         c.param[0].val = (__force __be32)op;
3764
3765         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3766 }
3767
3768 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3769                         unsigned int *pif_req_wrptr,
3770                         unsigned int *pif_rsp_wrptr)
3771 {
3772         int i, j;
3773         u32 cfg, val, req, rsp;
3774
3775         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3776         if (cfg & LADBGEN_F)
3777                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3778
3779         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3780         req = POLADBGWRPTR_G(val);
3781         rsp = PILADBGWRPTR_G(val);
3782         if (pif_req_wrptr)
3783                 *pif_req_wrptr = req;
3784         if (pif_rsp_wrptr)
3785                 *pif_rsp_wrptr = rsp;
3786
3787         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3788                 for (j = 0; j < 6; j++) {
3789                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3790                                      PILADBGRDPTR_V(rsp));
3791                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3792                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3793                         req++;
3794                         rsp++;
3795                 }
3796                 req = (req + 2) & POLADBGRDPTR_M;
3797                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3798         }
3799         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3800 }
3801
3802 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3803 {
3804         u32 cfg;
3805         int i, j, idx;
3806
3807         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3808         if (cfg & LADBGEN_F)
3809                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3810
3811         for (i = 0; i < CIM_MALA_SIZE; i++) {
3812                 for (j = 0; j < 5; j++) {
3813                         idx = 8 * i + j;
3814                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3815                                      PILADBGRDPTR_V(idx));
3816                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3817                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3818                 }
3819         }
3820         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3821 }
3822
3823 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3824 {
3825         unsigned int i, j;
3826
3827         for (i = 0; i < 8; i++) {
3828                 u32 *p = la_buf + i;
3829
3830                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3831                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3832                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3833                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3834                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3835         }
3836 }
3837
3838 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3839                      FW_PORT_CAP32_ANEG)
3840
3841 /**
3842  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3843  *      @caps16: a 16-bit Port Capabilities value
3844  *
3845  *      Returns the equivalent 32-bit Port Capabilities value.
3846  */
3847 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3848 {
3849         fw_port_cap32_t caps32 = 0;
3850
3851         #define CAP16_TO_CAP32(__cap) \
3852                 do { \
3853                         if (caps16 & FW_PORT_CAP_##__cap) \
3854                                 caps32 |= FW_PORT_CAP32_##__cap; \
3855                 } while (0)
3856
3857         CAP16_TO_CAP32(SPEED_100M);
3858         CAP16_TO_CAP32(SPEED_1G);
3859         CAP16_TO_CAP32(SPEED_25G);
3860         CAP16_TO_CAP32(SPEED_10G);
3861         CAP16_TO_CAP32(SPEED_40G);
3862         CAP16_TO_CAP32(SPEED_100G);
3863         CAP16_TO_CAP32(FC_RX);
3864         CAP16_TO_CAP32(FC_TX);
3865         CAP16_TO_CAP32(ANEG);
3866         CAP16_TO_CAP32(MDIX);
3867         CAP16_TO_CAP32(MDIAUTO);
3868         CAP16_TO_CAP32(FEC_RS);
3869         CAP16_TO_CAP32(FEC_BASER_RS);
3870         CAP16_TO_CAP32(802_3_PAUSE);
3871         CAP16_TO_CAP32(802_3_ASM_DIR);
3872
3873         #undef CAP16_TO_CAP32
3874
3875         return caps32;
3876 }
3877
3878 /**
3879  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3880  *      @caps32: a 32-bit Port Capabilities value
3881  *
3882  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
3883  *      not all 32-bit Port Capabilities can be represented in the 16-bit
3884  *      Port Capabilities and some fields/values may not make it.
3885  */
3886 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3887 {
3888         fw_port_cap16_t caps16 = 0;
3889
3890         #define CAP32_TO_CAP16(__cap) \
3891                 do { \
3892                         if (caps32 & FW_PORT_CAP32_##__cap) \
3893                                 caps16 |= FW_PORT_CAP_##__cap; \
3894                 } while (0)
3895
3896         CAP32_TO_CAP16(SPEED_100M);
3897         CAP32_TO_CAP16(SPEED_1G);
3898         CAP32_TO_CAP16(SPEED_10G);
3899         CAP32_TO_CAP16(SPEED_25G);
3900         CAP32_TO_CAP16(SPEED_40G);
3901         CAP32_TO_CAP16(SPEED_100G);
3902         CAP32_TO_CAP16(FC_RX);
3903         CAP32_TO_CAP16(FC_TX);
3904         CAP32_TO_CAP16(802_3_PAUSE);
3905         CAP32_TO_CAP16(802_3_ASM_DIR);
3906         CAP32_TO_CAP16(ANEG);
3907         CAP32_TO_CAP16(MDIX);
3908         CAP32_TO_CAP16(MDIAUTO);
3909         CAP32_TO_CAP16(FEC_RS);
3910         CAP32_TO_CAP16(FEC_BASER_RS);
3911
3912         #undef CAP32_TO_CAP16
3913
3914         return caps16;
3915 }
3916
3917 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3918 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
3919 {
3920         enum cc_pause cc_pause = 0;
3921
3922         if (fw_pause & FW_PORT_CAP32_FC_RX)
3923                 cc_pause |= PAUSE_RX;
3924         if (fw_pause & FW_PORT_CAP32_FC_TX)
3925                 cc_pause |= PAUSE_TX;
3926
3927         return cc_pause;
3928 }
3929
3930 /* Translate Common Code Pause specification into Firmware Port Capabilities */
3931 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
3932 {
3933         fw_port_cap32_t fw_pause = 0;
3934
3935         if (cc_pause & PAUSE_RX)
3936                 fw_pause |= FW_PORT_CAP32_FC_RX;
3937         if (cc_pause & PAUSE_TX)
3938                 fw_pause |= FW_PORT_CAP32_FC_TX;
3939
3940         return fw_pause;
3941 }
3942
3943 /* Translate Firmware Forward Error Correction specification to Common Code */
3944 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
3945 {
3946         enum cc_fec cc_fec = 0;
3947
3948         if (fw_fec & FW_PORT_CAP32_FEC_RS)
3949                 cc_fec |= FEC_RS;
3950         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
3951                 cc_fec |= FEC_BASER_RS;
3952
3953         return cc_fec;
3954 }
3955
3956 /* Translate Common Code Forward Error Correction specification to Firmware */
3957 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
3958 {
3959         fw_port_cap32_t fw_fec = 0;
3960
3961         if (cc_fec & FEC_RS)
3962                 fw_fec |= FW_PORT_CAP32_FEC_RS;
3963         if (cc_fec & FEC_BASER_RS)
3964                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
3965
3966         return fw_fec;
3967 }
3968
3969 /**
3970  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3971  *      @adapter: the adapter
3972  *      @mbox: the Firmware Mailbox to use
3973  *      @port: the Port ID
3974  *      @lc: the Port's Link Configuration
3975  *
3976  *      Set up a port's MAC and PHY according to a desired link configuration.
3977  *      - If the PHY can auto-negotiate first decide what to advertise, then
3978  *        enable/disable auto-negotiation as desired, and reset.
3979  *      - If the PHY does not auto-negotiate just reset it.
3980  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3981  *        otherwise do it later based on the outcome of auto-negotiation.
3982  */
3983 int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
3984                   unsigned int port, struct link_config *lc)
3985 {
3986         unsigned int fw_caps = adapter->params.fw_caps_support;
3987         struct fw_port_cmd cmd;
3988         unsigned int fw_mdi = FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO);
3989         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
3990
3991         lc->link_ok = 0;
3992
3993         /* Convert driver coding of Pause Frame Flow Control settings into the
3994          * Firmware's API.
3995          */
3996         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
3997
3998         /* Convert Common Code Forward Error Control settings into the
3999          * Firmware's API.  If the current Requested FEC has "Automatic"
4000          * (IEEE 802.3) specified, then we use whatever the Firmware
4001          * sent us as part of it's IEEE 802.3-based interpratation of
4002          * the Transceiver Module EPROM FEC parameters.  Otherwise we
4003          * use whatever is in the current Requested FEC settings.
4004          */
4005         if (lc->requested_fec & FEC_AUTO)
4006                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4007         else
4008                 cc_fec = lc->requested_fec;
4009         fw_fec = cc_to_fwcap_fec(cc_fec);
4010
4011         /* Figure out what our Requested Port Capabilities are going to be.
4012          */
4013         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4014                 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
4015                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4016                 lc->fec = cc_fec;
4017         } else if (lc->autoneg == AUTONEG_DISABLE) {
4018                 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4019                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4020                 lc->fec = cc_fec;
4021         } else {
4022                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4023         }
4024
4025         /* And send that on to the Firmware ...
4026          */
4027         memset(&cmd, 0, sizeof(cmd));
4028         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4029                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4030                                        FW_PORT_CMD_PORTID_V(port));
4031         cmd.action_to_len16 =
4032                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4033                                                  ? FW_PORT_ACTION_L1_CFG
4034                                                  : FW_PORT_ACTION_L1_CFG32) |
4035                             FW_LEN16(cmd));
4036         if (fw_caps == FW_CAPS16)
4037                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4038         else
4039                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4040         return t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4041 }
4042
4043 /**
4044  *      t4_restart_aneg - restart autonegotiation
4045  *      @adap: the adapter
4046  *      @mbox: mbox to use for the FW command
4047  *      @port: the port id
4048  *
4049  *      Restarts autonegotiation for the selected port.
4050  */
4051 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4052 {
4053         struct fw_port_cmd c;
4054
4055         memset(&c, 0, sizeof(c));
4056         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4057                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4058                                      FW_PORT_CMD_PORTID_V(port));
4059         c.action_to_len16 =
4060                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4061                             FW_LEN16(c));
4062         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4063         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4064 }
4065
4066 typedef void (*int_handler_t)(struct adapter *adap);
4067
4068 struct intr_info {
4069         unsigned int mask;       /* bits to check in interrupt status */
4070         const char *msg;         /* message to print or NULL */
4071         short stat_idx;          /* stat counter to increment or -1 */
4072         unsigned short fatal;    /* whether the condition reported is fatal */
4073         int_handler_t int_handler; /* platform-specific int handler */
4074 };
4075
4076 /**
4077  *      t4_handle_intr_status - table driven interrupt handler
4078  *      @adapter: the adapter that generated the interrupt
4079  *      @reg: the interrupt status register to process
4080  *      @acts: table of interrupt actions
4081  *
4082  *      A table driven interrupt handler that applies a set of masks to an
4083  *      interrupt status word and performs the corresponding actions if the
4084  *      interrupts described by the mask have occurred.  The actions include
4085  *      optionally emitting a warning or alert message.  The table is terminated
4086  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4087  *      conditions.
4088  */
4089 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4090                                  const struct intr_info *acts)
4091 {
4092         int fatal = 0;
4093         unsigned int mask = 0;
4094         unsigned int status = t4_read_reg(adapter, reg);
4095
4096         for ( ; acts->mask; ++acts) {
4097                 if (!(status & acts->mask))
4098                         continue;
4099                 if (acts->fatal) {
4100                         fatal++;
4101                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4102                                   status & acts->mask);
4103                 } else if (acts->msg && printk_ratelimit())
4104                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4105                                  status & acts->mask);
4106                 if (acts->int_handler)
4107                         acts->int_handler(adapter);
4108                 mask |= acts->mask;
4109         }
4110         status &= mask;
4111         if (status)                           /* clear processed interrupts */
4112                 t4_write_reg(adapter, reg, status);
4113         return fatal;
4114 }
4115
4116 /*
4117  * Interrupt handler for the PCIE module.
4118  */
4119 static void pcie_intr_handler(struct adapter *adapter)
4120 {
4121         static const struct intr_info sysbus_intr_info[] = {
4122                 { RNPP_F, "RXNP array parity error", -1, 1 },
4123                 { RPCP_F, "RXPC array parity error", -1, 1 },
4124                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4125                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4126                 { RFTP_F, "RXFT array parity error", -1, 1 },
4127                 { 0 }
4128         };
4129         static const struct intr_info pcie_port_intr_info[] = {
4130                 { TPCP_F, "TXPC array parity error", -1, 1 },
4131                 { TNPP_F, "TXNP array parity error", -1, 1 },
4132                 { TFTP_F, "TXFT array parity error", -1, 1 },
4133                 { TCAP_F, "TXCA array parity error", -1, 1 },
4134                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4135                 { RCAP_F, "RXCA array parity error", -1, 1 },
4136                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4137                 { RDPE_F, "Rx data parity error", -1, 1 },
4138                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4139                 { 0 }
4140         };
4141         static const struct intr_info pcie_intr_info[] = {
4142                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4143                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4144                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4145                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4146                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4147                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4148                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4149                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4150                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4151                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4152                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4153                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4154                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4155                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4156                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4157                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4158                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4159                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4160                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4161                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4162                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4163                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4164                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4165                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4166                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4167                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4168                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4169                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4170                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4171                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4172                   -1, 0 },
4173                 { 0 }
4174         };
4175
4176         static struct intr_info t5_pcie_intr_info[] = {
4177                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4178                   -1, 1 },
4179                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4180                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4181                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4182                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4183                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4184                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4185                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4186                   -1, 1 },
4187                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4188                   -1, 1 },
4189                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4190                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4191                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4192                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4193                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4194                   -1, 1 },
4195                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4196                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4197                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4198                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4199                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4200                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4201                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4202                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4203                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4204                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4205                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4206                   -1, 1 },
4207                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4208                   -1, 1 },
4209                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4210                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4211                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4212                 { READRSPERR_F, "Outbound read error", -1, 0 },
4213                 { 0 }
4214         };
4215
4216         int fat;
4217
4218         if (is_t4(adapter->params.chip))
4219                 fat = t4_handle_intr_status(adapter,
4220                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4221                                 sysbus_intr_info) +
4222                         t4_handle_intr_status(adapter,
4223                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4224                                         pcie_port_intr_info) +
4225                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4226                                               pcie_intr_info);
4227         else
4228                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4229                                             t5_pcie_intr_info);
4230
4231         if (fat)
4232                 t4_fatal_err(adapter);
4233 }
4234
4235 /*
4236  * TP interrupt handler.
4237  */
4238 static void tp_intr_handler(struct adapter *adapter)
4239 {
4240         static const struct intr_info tp_intr_info[] = {
4241                 { 0x3fffffff, "TP parity error", -1, 1 },
4242                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4243                 { 0 }
4244         };
4245
4246         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4247                 t4_fatal_err(adapter);
4248 }
4249
4250 /*
4251  * SGE interrupt handler.
4252  */
4253 static void sge_intr_handler(struct adapter *adapter)
4254 {
4255         u64 v;
4256         u32 err;
4257
4258         static const struct intr_info sge_intr_info[] = {
4259                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4260                   "SGE received CPL exceeding IQE size", -1, 1 },
4261                 { ERR_INVALID_CIDX_INC_F,
4262                   "SGE GTS CIDX increment too large", -1, 0 },
4263                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4264                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4265                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4266                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4267                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4268                   0 },
4269                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4270                   0 },
4271                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4272                   0 },
4273                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4274                   0 },
4275                 { ERR_ING_CTXT_PRIO_F,
4276                   "SGE too many priority ingress contexts", -1, 0 },
4277                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4278                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4279                 { 0 }
4280         };
4281
4282         static struct intr_info t4t5_sge_intr_info[] = {
4283                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4284                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4285                 { ERR_EGR_CTXT_PRIO_F,
4286                   "SGE too many priority egress contexts", -1, 0 },
4287                 { 0 }
4288         };
4289
4290         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4291                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4292         if (v) {
4293                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4294                                 (unsigned long long)v);
4295                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4296                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4297         }
4298
4299         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4300         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4301                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4302                                            t4t5_sge_intr_info);
4303
4304         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4305         if (err & ERROR_QID_VALID_F) {
4306                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4307                         ERROR_QID_G(err));
4308                 if (err & UNCAPTURED_ERROR_F)
4309                         dev_err(adapter->pdev_dev,
4310                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4311                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4312                              UNCAPTURED_ERROR_F);
4313         }
4314
4315         if (v != 0)
4316                 t4_fatal_err(adapter);
4317 }
4318
4319 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4320                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4321 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4322                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4323
4324 /*
4325  * CIM interrupt handler.
4326  */
4327 static void cim_intr_handler(struct adapter *adapter)
4328 {
4329         static const struct intr_info cim_intr_info[] = {
4330                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4331                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4332                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4333                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4334                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4335                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4336                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4337                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4338                 { 0 }
4339         };
4340         static const struct intr_info cim_upintr_info[] = {
4341                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4342                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4343                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4344                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4345                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4346                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4347                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4348                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4349                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4350                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4351                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4352                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4353                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4354                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4355                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4356                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4357                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4358                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4359                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4360                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4361                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4362                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4363                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4364                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4365                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4366                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4367                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4368                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4369                 { 0 }
4370         };
4371
4372         u32 val, fw_err;
4373         int fat;
4374
4375         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4376         if (fw_err & PCIE_FW_ERR_F)
4377                 t4_report_fw_error(adapter);
4378
4379         /* When the Firmware detects an internal error which normally
4380          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4381          * in order to make sure the Host sees the Firmware Crash.  So
4382          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4383          * ignore the Timer0 interrupt.
4384          */
4385
4386         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4387         if (val & TIMER0INT_F)
4388                 if (!(fw_err & PCIE_FW_ERR_F) ||
4389                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4390                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4391                                      TIMER0INT_F);
4392
4393         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4394                                     cim_intr_info) +
4395               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4396                                     cim_upintr_info);
4397         if (fat)
4398                 t4_fatal_err(adapter);
4399 }
4400
4401 /*
4402  * ULP RX interrupt handler.
4403  */
4404 static void ulprx_intr_handler(struct adapter *adapter)
4405 {
4406         static const struct intr_info ulprx_intr_info[] = {
4407                 { 0x1800000, "ULPRX context error", -1, 1 },
4408                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4409                 { 0 }
4410         };
4411
4412         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4413                 t4_fatal_err(adapter);
4414 }
4415
4416 /*
4417  * ULP TX interrupt handler.
4418  */
4419 static void ulptx_intr_handler(struct adapter *adapter)
4420 {
4421         static const struct intr_info ulptx_intr_info[] = {
4422                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4423                   0 },
4424                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4425                   0 },
4426                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4427                   0 },
4428                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4429                   0 },
4430                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4431                 { 0 }
4432         };
4433
4434         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4435                 t4_fatal_err(adapter);
4436 }
4437
4438 /*
4439  * PM TX interrupt handler.
4440  */
4441 static void pmtx_intr_handler(struct adapter *adapter)
4442 {
4443         static const struct intr_info pmtx_intr_info[] = {
4444                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4445                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4446                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4447                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4448                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4449                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4450                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4451                   -1, 1 },
4452                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4453                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4454                 { 0 }
4455         };
4456
4457         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4458                 t4_fatal_err(adapter);
4459 }
4460
4461 /*
4462  * PM RX interrupt handler.
4463  */
4464 static void pmrx_intr_handler(struct adapter *adapter)
4465 {
4466         static const struct intr_info pmrx_intr_info[] = {
4467                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4468                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4469                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4470                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4471                   -1, 1 },
4472                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4473                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4474                 { 0 }
4475         };
4476
4477         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4478                 t4_fatal_err(adapter);
4479 }
4480
4481 /*
4482  * CPL switch interrupt handler.
4483  */
4484 static void cplsw_intr_handler(struct adapter *adapter)
4485 {
4486         static const struct intr_info cplsw_intr_info[] = {
4487                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4488                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4489                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4490                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4491                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4492                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4493                 { 0 }
4494         };
4495
4496         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4497                 t4_fatal_err(adapter);
4498 }
4499
4500 /*
4501  * LE interrupt handler.
4502  */
4503 static void le_intr_handler(struct adapter *adap)
4504 {
4505         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4506         static const struct intr_info le_intr_info[] = {
4507                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4508                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4509                 { PARITYERR_F, "LE parity error", -1, 1 },
4510                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4511                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4512                 { 0 }
4513         };
4514
4515         static struct intr_info t6_le_intr_info[] = {
4516                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4517                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4518                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4519                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4520                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4521                 { 0 }
4522         };
4523
4524         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4525                                   (chip <= CHELSIO_T5) ?
4526                                   le_intr_info : t6_le_intr_info))
4527                 t4_fatal_err(adap);
4528 }
4529
4530 /*
4531  * MPS interrupt handler.
4532  */
4533 static void mps_intr_handler(struct adapter *adapter)
4534 {
4535         static const struct intr_info mps_rx_intr_info[] = {
4536                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4537                 { 0 }
4538         };
4539         static const struct intr_info mps_tx_intr_info[] = {
4540                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4541                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4542                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4543                   -1, 1 },
4544                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4545                   -1, 1 },
4546                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4547                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4548                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4549                 { 0 }
4550         };
4551         static const struct intr_info t6_mps_tx_intr_info[] = {
4552                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4553                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4554                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4555                   -1, 1 },
4556                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4557                   -1, 1 },
4558                 /* MPS Tx Bubble is normal for T6 */
4559                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4560                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4561                 { 0 }
4562         };
4563         static const struct intr_info mps_trc_intr_info[] = {
4564                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4565                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4566                   -1, 1 },
4567                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4568                 { 0 }
4569         };
4570         static const struct intr_info mps_stat_sram_intr_info[] = {
4571                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4572                 { 0 }
4573         };
4574         static const struct intr_info mps_stat_tx_intr_info[] = {
4575                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4576                 { 0 }
4577         };
4578         static const struct intr_info mps_stat_rx_intr_info[] = {
4579                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4580                 { 0 }
4581         };
4582         static const struct intr_info mps_cls_intr_info[] = {
4583                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4584                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4585                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4586                 { 0 }
4587         };
4588
4589         int fat;
4590
4591         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4592                                     mps_rx_intr_info) +
4593               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4594                                     is_t6(adapter->params.chip)
4595                                     ? t6_mps_tx_intr_info
4596                                     : mps_tx_intr_info) +
4597               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4598                                     mps_trc_intr_info) +
4599               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4600                                     mps_stat_sram_intr_info) +
4601               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4602                                     mps_stat_tx_intr_info) +
4603               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4604                                     mps_stat_rx_intr_info) +
4605               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4606                                     mps_cls_intr_info);
4607
4608         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4609         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4610         if (fat)
4611                 t4_fatal_err(adapter);
4612 }
4613
4614 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4615                       ECC_UE_INT_CAUSE_F)
4616
4617 /*
4618  * EDC/MC interrupt handler.
4619  */
4620 static void mem_intr_handler(struct adapter *adapter, int idx)
4621 {
4622         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4623
4624         unsigned int addr, cnt_addr, v;
4625
4626         if (idx <= MEM_EDC1) {
4627                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4628                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4629         } else if (idx == MEM_MC) {
4630                 if (is_t4(adapter->params.chip)) {
4631                         addr = MC_INT_CAUSE_A;
4632                         cnt_addr = MC_ECC_STATUS_A;
4633                 } else {
4634                         addr = MC_P_INT_CAUSE_A;
4635                         cnt_addr = MC_P_ECC_STATUS_A;
4636                 }
4637         } else {
4638                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4639                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4640         }
4641
4642         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4643         if (v & PERR_INT_CAUSE_F)
4644                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4645                           name[idx]);
4646         if (v & ECC_CE_INT_CAUSE_F) {
4647                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4648
4649                 t4_edc_err_read(adapter, idx);
4650
4651                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4652                 if (printk_ratelimit())
4653                         dev_warn(adapter->pdev_dev,
4654                                  "%u %s correctable ECC data error%s\n",
4655                                  cnt, name[idx], cnt > 1 ? "s" : "");
4656         }
4657         if (v & ECC_UE_INT_CAUSE_F)
4658                 dev_alert(adapter->pdev_dev,
4659                           "%s uncorrectable ECC data error\n", name[idx]);
4660
4661         t4_write_reg(adapter, addr, v);
4662         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4663                 t4_fatal_err(adapter);
4664 }
4665
4666 /*
4667  * MA interrupt handler.
4668  */
4669 static void ma_intr_handler(struct adapter *adap)
4670 {
4671         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4672
4673         if (status & MEM_PERR_INT_CAUSE_F) {
4674                 dev_alert(adap->pdev_dev,
4675                           "MA parity error, parity status %#x\n",
4676                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4677                 if (is_t5(adap->params.chip))
4678                         dev_alert(adap->pdev_dev,
4679                                   "MA parity error, parity status %#x\n",
4680                                   t4_read_reg(adap,
4681                                               MA_PARITY_ERROR_STATUS2_A));
4682         }
4683         if (status & MEM_WRAP_INT_CAUSE_F) {
4684                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4685                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4686                           "client %u to address %#x\n",
4687                           MEM_WRAP_CLIENT_NUM_G(v),
4688                           MEM_WRAP_ADDRESS_G(v) << 4);
4689         }
4690         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4691         t4_fatal_err(adap);
4692 }
4693
4694 /*
4695  * SMB interrupt handler.
4696  */
4697 static void smb_intr_handler(struct adapter *adap)
4698 {
4699         static const struct intr_info smb_intr_info[] = {
4700                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4701                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4702                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4703                 { 0 }
4704         };
4705
4706         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4707                 t4_fatal_err(adap);
4708 }
4709
4710 /*
4711  * NC-SI interrupt handler.
4712  */
4713 static void ncsi_intr_handler(struct adapter *adap)
4714 {
4715         static const struct intr_info ncsi_intr_info[] = {
4716                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4717                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4718                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4719                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4720                 { 0 }
4721         };
4722
4723         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4724                 t4_fatal_err(adap);
4725 }
4726
4727 /*
4728  * XGMAC interrupt handler.
4729  */
4730 static void xgmac_intr_handler(struct adapter *adap, int port)
4731 {
4732         u32 v, int_cause_reg;
4733
4734         if (is_t4(adap->params.chip))
4735                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4736         else
4737                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4738
4739         v = t4_read_reg(adap, int_cause_reg);
4740
4741         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4742         if (!v)
4743                 return;
4744
4745         if (v & TXFIFO_PRTY_ERR_F)
4746                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4747                           port);
4748         if (v & RXFIFO_PRTY_ERR_F)
4749                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4750                           port);
4751         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4752         t4_fatal_err(adap);
4753 }
4754
4755 /*
4756  * PL interrupt handler.
4757  */
4758 static void pl_intr_handler(struct adapter *adap)
4759 {
4760         static const struct intr_info pl_intr_info[] = {
4761                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4762                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4763                 { 0 }
4764         };
4765
4766         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4767                 t4_fatal_err(adap);
4768 }
4769
4770 #define PF_INTR_MASK (PFSW_F)
4771 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4772                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4773                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4774
4775 /**
4776  *      t4_slow_intr_handler - control path interrupt handler
4777  *      @adapter: the adapter
4778  *
4779  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4780  *      The designation 'slow' is because it involves register reads, while
4781  *      data interrupts typically don't involve any MMIOs.
4782  */
4783 int t4_slow_intr_handler(struct adapter *adapter)
4784 {
4785         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4786
4787         if (!(cause & GLBL_INTR_MASK))
4788                 return 0;
4789         if (cause & CIM_F)
4790                 cim_intr_handler(adapter);
4791         if (cause & MPS_F)
4792                 mps_intr_handler(adapter);
4793         if (cause & NCSI_F)
4794                 ncsi_intr_handler(adapter);
4795         if (cause & PL_F)
4796                 pl_intr_handler(adapter);
4797         if (cause & SMB_F)
4798                 smb_intr_handler(adapter);
4799         if (cause & XGMAC0_F)
4800                 xgmac_intr_handler(adapter, 0);
4801         if (cause & XGMAC1_F)
4802                 xgmac_intr_handler(adapter, 1);
4803         if (cause & XGMAC_KR0_F)
4804                 xgmac_intr_handler(adapter, 2);
4805         if (cause & XGMAC_KR1_F)
4806                 xgmac_intr_handler(adapter, 3);
4807         if (cause & PCIE_F)
4808                 pcie_intr_handler(adapter);
4809         if (cause & MC_F)
4810                 mem_intr_handler(adapter, MEM_MC);
4811         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4812                 mem_intr_handler(adapter, MEM_MC1);
4813         if (cause & EDC0_F)
4814                 mem_intr_handler(adapter, MEM_EDC0);
4815         if (cause & EDC1_F)
4816                 mem_intr_handler(adapter, MEM_EDC1);
4817         if (cause & LE_F)
4818                 le_intr_handler(adapter);
4819         if (cause & TP_F)
4820                 tp_intr_handler(adapter);
4821         if (cause & MA_F)
4822                 ma_intr_handler(adapter);
4823         if (cause & PM_TX_F)
4824                 pmtx_intr_handler(adapter);
4825         if (cause & PM_RX_F)
4826                 pmrx_intr_handler(adapter);
4827         if (cause & ULP_RX_F)
4828                 ulprx_intr_handler(adapter);
4829         if (cause & CPL_SWITCH_F)
4830                 cplsw_intr_handler(adapter);
4831         if (cause & SGE_F)
4832                 sge_intr_handler(adapter);
4833         if (cause & ULP_TX_F)
4834                 ulptx_intr_handler(adapter);
4835
4836         /* Clear the interrupts just processed for which we are the master. */
4837         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4838         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4839         return 1;
4840 }
4841
4842 /**
4843  *      t4_intr_enable - enable interrupts
4844  *      @adapter: the adapter whose interrupts should be enabled
4845  *
4846  *      Enable PF-specific interrupts for the calling function and the top-level
4847  *      interrupt concentrator for global interrupts.  Interrupts are already
4848  *      enabled at each module, here we just enable the roots of the interrupt
4849  *      hierarchies.
4850  *
4851  *      Note: this function should be called only when the driver manages
4852  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4853  *      function at a time should be doing this.
4854  */
4855 void t4_intr_enable(struct adapter *adapter)
4856 {
4857         u32 val = 0;
4858         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4859         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4860                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4861
4862         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4863                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4864         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4865                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4866                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4867                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4868                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4869                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4870                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4871         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4872         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4873 }
4874
4875 /**
4876  *      t4_intr_disable - disable interrupts
4877  *      @adapter: the adapter whose interrupts should be disabled
4878  *
4879  *      Disable interrupts.  We only disable the top-level interrupt
4880  *      concentrators.  The caller must be a PCI function managing global
4881  *      interrupts.
4882  */
4883 void t4_intr_disable(struct adapter *adapter)
4884 {
4885         u32 whoami, pf;
4886
4887         if (pci_channel_offline(adapter->pdev))
4888                 return;
4889
4890         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4891         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4892                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4893
4894         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4895         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4896 }
4897
4898 /**
4899  *      t4_config_rss_range - configure a portion of the RSS mapping table
4900  *      @adapter: the adapter
4901  *      @mbox: mbox to use for the FW command
4902  *      @viid: virtual interface whose RSS subtable is to be written
4903  *      @start: start entry in the table to write
4904  *      @n: how many table entries to write
4905  *      @rspq: values for the response queue lookup table
4906  *      @nrspq: number of values in @rspq
4907  *
4908  *      Programs the selected part of the VI's RSS mapping table with the
4909  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4910  *      until the full table range is populated.
4911  *
4912  *      The caller must ensure the values in @rspq are in the range allowed for
4913  *      @viid.
4914  */
4915 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4916                         int start, int n, const u16 *rspq, unsigned int nrspq)
4917 {
4918         int ret;
4919         const u16 *rsp = rspq;
4920         const u16 *rsp_end = rspq + nrspq;
4921         struct fw_rss_ind_tbl_cmd cmd;
4922
4923         memset(&cmd, 0, sizeof(cmd));
4924         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4925                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4926                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4927         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4928
4929         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4930         while (n > 0) {
4931                 int nq = min(n, 32);
4932                 __be32 *qp = &cmd.iq0_to_iq2;
4933
4934                 cmd.niqid = cpu_to_be16(nq);
4935                 cmd.startidx = cpu_to_be16(start);
4936
4937                 start += nq;
4938                 n -= nq;
4939
4940                 while (nq > 0) {
4941                         unsigned int v;
4942
4943                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4944                         if (++rsp >= rsp_end)
4945                                 rsp = rspq;
4946                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4947                         if (++rsp >= rsp_end)
4948                                 rsp = rspq;
4949                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4950                         if (++rsp >= rsp_end)
4951                                 rsp = rspq;
4952
4953                         *qp++ = cpu_to_be32(v);
4954                         nq -= 3;
4955                 }
4956
4957                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4958                 if (ret)
4959                         return ret;
4960         }
4961         return 0;
4962 }
4963
4964 /**
4965  *      t4_config_glbl_rss - configure the global RSS mode
4966  *      @adapter: the adapter
4967  *      @mbox: mbox to use for the FW command
4968  *      @mode: global RSS mode
4969  *      @flags: mode-specific flags
4970  *
4971  *      Sets the global RSS mode.
4972  */
4973 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4974                        unsigned int flags)
4975 {
4976         struct fw_rss_glb_config_cmd c;
4977
4978         memset(&c, 0, sizeof(c));
4979         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4980                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4981         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4982         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4983                 c.u.manual.mode_pkd =
4984                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4985         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4986                 c.u.basicvirtual.mode_pkd =
4987                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4988                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4989         } else
4990                 return -EINVAL;
4991         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4992 }
4993
4994 /**
4995  *      t4_config_vi_rss - configure per VI RSS settings
4996  *      @adapter: the adapter
4997  *      @mbox: mbox to use for the FW command
4998  *      @viid: the VI id
4999  *      @flags: RSS flags
5000  *      @defq: id of the default RSS queue for the VI.
5001  *
5002  *      Configures VI-specific RSS properties.
5003  */
5004 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5005                      unsigned int flags, unsigned int defq)
5006 {
5007         struct fw_rss_vi_config_cmd c;
5008
5009         memset(&c, 0, sizeof(c));
5010         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5011                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5012                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5013         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5014         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5015                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5016         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5017 }
5018
5019 /* Read an RSS table row */
5020 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5021 {
5022         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5023         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5024                                    5, 0, val);
5025 }
5026
5027 /**
5028  *      t4_read_rss - read the contents of the RSS mapping table
5029  *      @adapter: the adapter
5030  *      @map: holds the contents of the RSS mapping table
5031  *
5032  *      Reads the contents of the RSS hash->queue mapping table.
5033  */
5034 int t4_read_rss(struct adapter *adapter, u16 *map)
5035 {
5036         u32 val;
5037         int i, ret;
5038
5039         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5040                 ret = rd_rss_row(adapter, i, &val);
5041                 if (ret)
5042                         return ret;
5043                 *map++ = LKPTBLQUEUE0_G(val);
5044                 *map++ = LKPTBLQUEUE1_G(val);
5045         }
5046         return 0;
5047 }
5048
5049 static unsigned int t4_use_ldst(struct adapter *adap)
5050 {
5051         return (adap->flags & FW_OK) || !adap->use_bd;
5052 }
5053
5054 /**
5055  *      t4_fw_tp_pio_rw - Access TP PIO through LDST
5056  *      @adap: the adapter
5057  *      @vals: where the indirect register values are stored/written
5058  *      @nregs: how many indirect registers to read/write
5059  *      @start_idx: index of first indirect register to read/write
5060  *      @rw: Read (1) or Write (0)
5061  *
5062  *      Access TP PIO registers through LDST
5063  */
5064 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
5065                             unsigned int start_index, unsigned int rw)
5066 {
5067         int ret, i;
5068         int cmd = FW_LDST_ADDRSPC_TP_PIO;
5069         struct fw_ldst_cmd c;
5070
5071         for (i = 0 ; i < nregs; i++) {
5072                 memset(&c, 0, sizeof(c));
5073                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5074                                                 FW_CMD_REQUEST_F |
5075                                                 (rw ? FW_CMD_READ_F :
5076                                                       FW_CMD_WRITE_F) |
5077                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5078                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5079
5080                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5081                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5082                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
5083                 if (!ret && rw)
5084                         vals[i] = be32_to_cpu(c.u.addrval.val);
5085         }
5086 }
5087
5088 /**
5089  *      t4_read_rss_key - read the global RSS key
5090  *      @adap: the adapter
5091  *      @key: 10-entry array holding the 320-bit RSS key
5092  *
5093  *      Reads the global 320-bit RSS key.
5094  */
5095 void t4_read_rss_key(struct adapter *adap, u32 *key)
5096 {
5097         if (t4_use_ldst(adap))
5098                 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
5099         else
5100                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
5101                                  TP_RSS_SECRET_KEY0_A);
5102 }
5103
5104 /**
5105  *      t4_write_rss_key - program one of the RSS keys
5106  *      @adap: the adapter
5107  *      @key: 10-entry array holding the 320-bit RSS key
5108  *      @idx: which RSS key to write
5109  *
5110  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5111  *      0..15 the corresponding entry in the RSS key table is written,
5112  *      otherwise the global RSS key is written.
5113  */
5114 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
5115 {
5116         u8 rss_key_addr_cnt = 16;
5117         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5118
5119         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5120          * allows access to key addresses 16-63 by using KeyWrAddrX
5121          * as index[5:4](upper 2) into key table
5122          */
5123         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5124             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5125                 rss_key_addr_cnt = 32;
5126
5127         if (t4_use_ldst(adap))
5128                 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
5129         else
5130                 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
5131                                   TP_RSS_SECRET_KEY0_A);
5132
5133         if (idx >= 0 && idx < rss_key_addr_cnt) {
5134                 if (rss_key_addr_cnt > 16)
5135                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5136                                      KEYWRADDRX_V(idx >> 4) |
5137                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5138                 else
5139                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5140                                      KEYWRADDR_V(idx) | KEYWREN_F);
5141         }
5142 }
5143
5144 /**
5145  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5146  *      @adapter: the adapter
5147  *      @index: the entry in the PF RSS table to read
5148  *      @valp: where to store the returned value
5149  *
5150  *      Reads the PF RSS Configuration Table at the specified index and returns
5151  *      the value found there.
5152  */
5153 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5154                            u32 *valp)
5155 {
5156         if (t4_use_ldst(adapter))
5157                 t4_fw_tp_pio_rw(adapter, valp, 1,
5158                                 TP_RSS_PF0_CONFIG_A + index, 1);
5159         else
5160                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5161                                  valp, 1, TP_RSS_PF0_CONFIG_A + index);
5162 }
5163
5164 /**
5165  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5166  *      @adapter: the adapter
5167  *      @index: the entry in the VF RSS table to read
5168  *      @vfl: where to store the returned VFL
5169  *      @vfh: where to store the returned VFH
5170  *
5171  *      Reads the VF RSS Configuration Table at the specified index and returns
5172  *      the (VFL, VFH) values found there.
5173  */
5174 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5175                            u32 *vfl, u32 *vfh)
5176 {
5177         u32 vrt, mask, data;
5178
5179         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5180                 mask = VFWRADDR_V(VFWRADDR_M);
5181                 data = VFWRADDR_V(index);
5182         } else {
5183                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5184                  data = T6_VFWRADDR_V(index);
5185         }
5186
5187         /* Request that the index'th VF Table values be read into VFL/VFH.
5188          */
5189         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5190         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5191         vrt |= data | VFRDEN_F;
5192         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5193
5194         /* Grab the VFL/VFH values ...
5195          */
5196         if (t4_use_ldst(adapter)) {
5197                 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
5198                 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
5199         } else {
5200                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5201                                  vfl, 1, TP_RSS_VFL_CONFIG_A);
5202                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5203                                  vfh, 1, TP_RSS_VFH_CONFIG_A);
5204         }
5205 }
5206
5207 /**
5208  *      t4_read_rss_pf_map - read PF RSS Map
5209  *      @adapter: the adapter
5210  *
5211  *      Reads the PF RSS Map register and returns its value.
5212  */
5213 u32 t4_read_rss_pf_map(struct adapter *adapter)
5214 {
5215         u32 pfmap;
5216
5217         if (t4_use_ldst(adapter))
5218                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
5219         else
5220                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5221                                  &pfmap, 1, TP_RSS_PF_MAP_A);
5222         return pfmap;
5223 }
5224
5225 /**
5226  *      t4_read_rss_pf_mask - read PF RSS Mask
5227  *      @adapter: the adapter
5228  *
5229  *      Reads the PF RSS Mask register and returns its value.
5230  */
5231 u32 t4_read_rss_pf_mask(struct adapter *adapter)
5232 {
5233         u32 pfmask;
5234
5235         if (t4_use_ldst(adapter))
5236                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
5237         else
5238                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5239                                  &pfmask, 1, TP_RSS_PF_MSK_A);
5240         return pfmask;
5241 }
5242
5243 /**
5244  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5245  *      @adap: the adapter
5246  *      @v4: holds the TCP/IP counter values
5247  *      @v6: holds the TCP/IPv6 counter values
5248  *
5249  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5250  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5251  */
5252 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5253                          struct tp_tcp_stats *v6)
5254 {
5255         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5256
5257 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5258 #define STAT(x)     val[STAT_IDX(x)]
5259 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5260
5261         if (v4) {
5262                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5263                                  ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
5264                 v4->tcp_out_rsts = STAT(OUT_RST);
5265                 v4->tcp_in_segs  = STAT64(IN_SEG);
5266                 v4->tcp_out_segs = STAT64(OUT_SEG);
5267                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5268         }
5269         if (v6) {
5270                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5271                                  ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
5272                 v6->tcp_out_rsts = STAT(OUT_RST);
5273                 v6->tcp_in_segs  = STAT64(IN_SEG);
5274                 v6->tcp_out_segs = STAT64(OUT_SEG);
5275                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5276         }
5277 #undef STAT64
5278 #undef STAT
5279 #undef STAT_IDX
5280 }
5281
5282 /**
5283  *      t4_tp_get_err_stats - read TP's error MIB counters
5284  *      @adap: the adapter
5285  *      @st: holds the counter values
5286  *
5287  *      Returns the values of TP's error counters.
5288  */
5289 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
5290 {
5291         int nchan = adap->params.arch.nchan;
5292
5293         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5294                          st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
5295         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5296                          st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
5297         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5298                          st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
5299         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5300                          st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
5301         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5302                          st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
5303         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5304                          st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
5305         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5306                          st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
5307         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5308                          st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
5309
5310         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5311                          &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
5312 }
5313
5314 /**
5315  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5316  *      @adap: the adapter
5317  *      @st: holds the counter values
5318  *
5319  *      Returns the values of TP's CPL counters.
5320  */
5321 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
5322 {
5323         int nchan = adap->params.arch.nchan;
5324
5325         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
5326                          nchan, TP_MIB_CPL_IN_REQ_0_A);
5327         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
5328                          nchan, TP_MIB_CPL_OUT_RSP_0_A);
5329
5330 }
5331
5332 /**
5333  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5334  *      @adap: the adapter
5335  *      @st: holds the counter values
5336  *
5337  *      Returns the values of TP's RDMA counters.
5338  */
5339 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5340 {
5341         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
5342                          2, TP_MIB_RQE_DFR_PKT_A);
5343 }
5344
5345 /**
5346  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5347  *      @adap: the adapter
5348  *      @idx: the port index
5349  *      @st: holds the counter values
5350  *
5351  *      Returns the values of TP's FCoE counters for the selected port.
5352  */
5353 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5354                        struct tp_fcoe_stats *st)
5355 {
5356         u32 val[2];
5357
5358         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
5359                          1, TP_MIB_FCOE_DDP_0_A + idx);
5360         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
5361                          1, TP_MIB_FCOE_DROP_0_A + idx);
5362         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5363                          2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
5364         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5365 }
5366
5367 /**
5368  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5369  *      @adap: the adapter
5370  *      @st: holds the counter values
5371  *
5372  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5373  */
5374 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5375 {
5376         u32 val[4];
5377
5378         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
5379                          TP_MIB_USM_PKTS_A);
5380         st->frames = val[0];
5381         st->drops = val[1];
5382         st->octets = ((u64)val[2] << 32) | val[3];
5383 }
5384
5385 /**
5386  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5387  *      @adap: the adapter
5388  *      @mtus: where to store the MTU values
5389  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5390  *
5391  *      Reads the HW path MTU table.
5392  */
5393 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5394 {
5395         u32 v;
5396         int i;
5397
5398         for (i = 0; i < NMTUS; ++i) {
5399                 t4_write_reg(adap, TP_MTU_TABLE_A,
5400                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5401                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5402                 mtus[i] = MTUVALUE_G(v);
5403                 if (mtu_log)
5404                         mtu_log[i] = MTUWIDTH_G(v);
5405         }
5406 }
5407
5408 /**
5409  *      t4_read_cong_tbl - reads the congestion control table
5410  *      @adap: the adapter
5411  *      @incr: where to store the alpha values
5412  *
5413  *      Reads the additive increments programmed into the HW congestion
5414  *      control table.
5415  */
5416 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5417 {
5418         unsigned int mtu, w;
5419
5420         for (mtu = 0; mtu < NMTUS; ++mtu)
5421                 for (w = 0; w < NCCTRL_WIN; ++w) {
5422                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5423                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5424                         incr[mtu][w] = (u16)t4_read_reg(adap,
5425                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5426                 }
5427 }
5428
5429 /**
5430  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5431  *      @adap: the adapter
5432  *      @addr: the indirect TP register address
5433  *      @mask: specifies the field within the register to modify
5434  *      @val: new value for the field
5435  *
5436  *      Sets a field of an indirect TP register to the given value.
5437  */
5438 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5439                             unsigned int mask, unsigned int val)
5440 {
5441         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5442         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5443         t4_write_reg(adap, TP_PIO_DATA_A, val);
5444 }
5445
5446 /**
5447  *      init_cong_ctrl - initialize congestion control parameters
5448  *      @a: the alpha values for congestion control
5449  *      @b: the beta values for congestion control
5450  *
5451  *      Initialize the congestion control parameters.
5452  */
5453 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5454 {
5455         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5456         a[9] = 2;
5457         a[10] = 3;
5458         a[11] = 4;
5459         a[12] = 5;
5460         a[13] = 6;
5461         a[14] = 7;
5462         a[15] = 8;
5463         a[16] = 9;
5464         a[17] = 10;
5465         a[18] = 14;
5466         a[19] = 17;
5467         a[20] = 21;
5468         a[21] = 25;
5469         a[22] = 30;
5470         a[23] = 35;
5471         a[24] = 45;
5472         a[25] = 60;
5473         a[26] = 80;
5474         a[27] = 100;
5475         a[28] = 200;
5476         a[29] = 300;
5477         a[30] = 400;
5478         a[31] = 500;
5479
5480         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5481         b[9] = b[10] = 1;
5482         b[11] = b[12] = 2;
5483         b[13] = b[14] = b[15] = b[16] = 3;
5484         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5485         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5486         b[28] = b[29] = 6;
5487         b[30] = b[31] = 7;
5488 }
5489
5490 /* The minimum additive increment value for the congestion control table */
5491 #define CC_MIN_INCR 2U
5492
5493 /**
5494  *      t4_load_mtus - write the MTU and congestion control HW tables
5495  *      @adap: the adapter
5496  *      @mtus: the values for the MTU table
5497  *      @alpha: the values for the congestion control alpha parameter
5498  *      @beta: the values for the congestion control beta parameter
5499  *
5500  *      Write the HW MTU table with the supplied MTUs and the high-speed
5501  *      congestion control table with the supplied alpha, beta, and MTUs.
5502  *      We write the two tables together because the additive increments
5503  *      depend on the MTUs.
5504  */
5505 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5506                   const unsigned short *alpha, const unsigned short *beta)
5507 {
5508         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5509                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5510                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5511                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5512         };
5513
5514         unsigned int i, w;
5515
5516         for (i = 0; i < NMTUS; ++i) {
5517                 unsigned int mtu = mtus[i];
5518                 unsigned int log2 = fls(mtu);
5519
5520                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5521                         log2--;
5522                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5523                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5524
5525                 for (w = 0; w < NCCTRL_WIN; ++w) {
5526                         unsigned int inc;
5527
5528                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5529                                   CC_MIN_INCR);
5530
5531                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5532                                      (w << 16) | (beta[w] << 13) | inc);
5533                 }
5534         }
5535 }
5536
5537 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5538  * clocks.  The formula is
5539  *
5540  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5541  *
5542  * which is equivalent to
5543  *
5544  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5545  */
5546 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5547 {
5548         u64 v = bytes256 * adap->params.vpd.cclk;
5549
5550         return v * 62 + v / 2;
5551 }
5552
5553 /**
5554  *      t4_get_chan_txrate - get the current per channel Tx rates
5555  *      @adap: the adapter
5556  *      @nic_rate: rates for NIC traffic
5557  *      @ofld_rate: rates for offloaded traffic
5558  *
5559  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5560  *      for each channel.
5561  */
5562 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5563 {
5564         u32 v;
5565
5566         v = t4_read_reg(adap, TP_TX_TRATE_A);
5567         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5568         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5569         if (adap->params.arch.nchan == NCHAN) {
5570                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5571                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5572         }
5573
5574         v = t4_read_reg(adap, TP_TX_ORATE_A);
5575         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5576         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5577         if (adap->params.arch.nchan == NCHAN) {
5578                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5579                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5580         }
5581 }
5582
5583 /**
5584  *      t4_set_trace_filter - configure one of the tracing filters
5585  *      @adap: the adapter
5586  *      @tp: the desired trace filter parameters
5587  *      @idx: which filter to configure
5588  *      @enable: whether to enable or disable the filter
5589  *
5590  *      Configures one of the tracing filters available in HW.  If @enable is
5591  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5592  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5593  */
5594 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5595                         int idx, int enable)
5596 {
5597         int i, ofst = idx * 4;
5598         u32 data_reg, mask_reg, cfg;
5599         u32 multitrc = TRCMULTIFILTER_F;
5600
5601         if (!enable) {
5602                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5603                 return 0;
5604         }
5605
5606         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5607         if (cfg & TRCMULTIFILTER_F) {
5608                 /* If multiple tracers are enabled, then maximum
5609                  * capture size is 2.5KB (FIFO size of a single channel)
5610                  * minus 2 flits for CPL_TRACE_PKT header.
5611                  */
5612                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5613                         return -EINVAL;
5614         } else {
5615                 /* If multiple tracers are disabled, to avoid deadlocks
5616                  * maximum packet capture size of 9600 bytes is recommended.
5617                  * Also in this mode, only trace0 can be enabled and running.
5618                  */
5619                 multitrc = 0;
5620                 if (tp->snap_len > 9600 || idx)
5621                         return -EINVAL;
5622         }
5623
5624         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5625             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5626             tp->min_len > TFMINPKTSIZE_M)
5627                 return -EINVAL;
5628
5629         /* stop the tracer we'll be changing */
5630         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5631
5632         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5633         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5634         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5635
5636         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5637                 t4_write_reg(adap, data_reg, tp->data[i]);
5638                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5639         }
5640         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5641                      TFCAPTUREMAX_V(tp->snap_len) |
5642                      TFMINPKTSIZE_V(tp->min_len));
5643         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5644                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5645                      (is_t4(adap->params.chip) ?
5646                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5647                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5648                      T5_TFINVERTMATCH_V(tp->invert)));
5649
5650         return 0;
5651 }
5652
5653 /**
5654  *      t4_get_trace_filter - query one of the tracing filters
5655  *      @adap: the adapter
5656  *      @tp: the current trace filter parameters
5657  *      @idx: which trace filter to query
5658  *      @enabled: non-zero if the filter is enabled
5659  *
5660  *      Returns the current settings of one of the HW tracing filters.
5661  */
5662 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5663                          int *enabled)
5664 {
5665         u32 ctla, ctlb;
5666         int i, ofst = idx * 4;
5667         u32 data_reg, mask_reg;
5668
5669         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5670         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5671
5672         if (is_t4(adap->params.chip)) {
5673                 *enabled = !!(ctla & TFEN_F);
5674                 tp->port =  TFPORT_G(ctla);
5675                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5676         } else {
5677                 *enabled = !!(ctla & T5_TFEN_F);
5678                 tp->port = T5_TFPORT_G(ctla);
5679                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5680         }
5681         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5682         tp->min_len = TFMINPKTSIZE_G(ctlb);
5683         tp->skip_ofst = TFOFFSET_G(ctla);
5684         tp->skip_len = TFLENGTH_G(ctla);
5685
5686         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5687         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5688         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5689
5690         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5691                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5692                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5693         }
5694 }
5695
5696 /**
5697  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5698  *      @adap: the adapter
5699  *      @cnt: where to store the count statistics
5700  *      @cycles: where to store the cycle statistics
5701  *
5702  *      Returns performance statistics from PMTX.
5703  */
5704 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5705 {
5706         int i;
5707         u32 data[2];
5708
5709         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5710                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5711                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5712                 if (is_t4(adap->params.chip)) {
5713                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5714                 } else {
5715                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5716                                          PM_TX_DBG_DATA_A, data, 2,
5717                                          PM_TX_DBG_STAT_MSB_A);
5718                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5719                 }
5720         }
5721 }
5722
5723 /**
5724  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5725  *      @adap: the adapter
5726  *      @cnt: where to store the count statistics
5727  *      @cycles: where to store the cycle statistics
5728  *
5729  *      Returns performance statistics from PMRX.
5730  */
5731 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5732 {
5733         int i;
5734         u32 data[2];
5735
5736         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5737                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5738                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5739                 if (is_t4(adap->params.chip)) {
5740                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5741                 } else {
5742                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5743                                          PM_RX_DBG_DATA_A, data, 2,
5744                                          PM_RX_DBG_STAT_MSB_A);
5745                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5746                 }
5747         }
5748 }
5749
5750 /**
5751  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5752  *      @adap: the adapter
5753  *      @pidx: the port index
5754  *
5755  *      Computes and returns a bitmap indicating which MPS buffer groups are
5756  *      associated with the given Port.  Bit i is set if buffer group i is
5757  *      used by the Port.
5758  */
5759 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5760                                               int pidx)
5761 {
5762         unsigned int chip_version, nports;
5763
5764         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5765         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5766
5767         switch (chip_version) {
5768         case CHELSIO_T4:
5769         case CHELSIO_T5:
5770                 switch (nports) {
5771                 case 1: return 0xf;
5772                 case 2: return 3 << (2 * pidx);
5773                 case 4: return 1 << pidx;
5774                 }
5775                 break;
5776
5777         case CHELSIO_T6:
5778                 switch (nports) {
5779                 case 2: return 1 << (2 * pidx);
5780                 }
5781                 break;
5782         }
5783
5784         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
5785                 chip_version, nports);
5786
5787         return 0;
5788 }
5789
5790 /**
5791  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5792  *      @adapter: the adapter
5793  *      @pidx: the port index
5794  *
5795  *      Returns a bitmap indicating which MPS buffer groups are associated
5796  *      with the given Port.  Bit i is set if buffer group i is used by the
5797  *      Port.
5798  */
5799 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
5800 {
5801         u8 *mps_bg_map;
5802         unsigned int nports;
5803
5804         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5805         if (pidx >= nports) {
5806                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
5807                         pidx, nports);
5808                 return 0;
5809         }
5810
5811         /* If we've already retrieved/computed this, just return the result.
5812          */
5813         mps_bg_map = adapter->params.mps_bg_map;
5814         if (mps_bg_map[pidx])
5815                 return mps_bg_map[pidx];
5816
5817         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
5818          * If we're talking to such Firmware, let it tell us.  If the new
5819          * API isn't supported, revert back to old hardcoded way.  The value
5820          * obtained from Firmware is encoded in below format:
5821          *
5822          * val = (( MPSBGMAP[Port 3] << 24 ) |
5823          *        ( MPSBGMAP[Port 2] << 16 ) |
5824          *        ( MPSBGMAP[Port 1] <<  8 ) |
5825          *        ( MPSBGMAP[Port 0] <<  0 ))
5826          */
5827         if (adapter->flags & FW_OK) {
5828                 u32 param, val;
5829                 int ret;
5830
5831                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5832                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
5833                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
5834                                          0, 1, &param, &val);
5835                 if (!ret) {
5836                         int p;
5837
5838                         /* Store the BG Map for all of the Ports in order to
5839                          * avoid more calls to the Firmware in the future.
5840                          */
5841                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
5842                                 mps_bg_map[p] = val & 0xff;
5843
5844                         return mps_bg_map[pidx];
5845                 }
5846         }
5847
5848         /* Either we're not talking to the Firmware or we're dealing with
5849          * older Firmware which doesn't support the new API to get the MPS
5850          * Buffer Group Map.  Fall back to computing it ourselves.
5851          */
5852         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
5853         return mps_bg_map[pidx];
5854 }
5855
5856 /**
5857  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
5858  *      @adapter: the adapter
5859  *      @pidx: the port index
5860  *
5861  *      Returns a bitmap indicating which TP Ingress Channels are associated
5862  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
5863  *      the Port.
5864  */
5865 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
5866 {
5867         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
5868         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5869
5870         if (pidx >= nports) {
5871                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
5872                          pidx, nports);
5873                 return 0;
5874         }
5875
5876         switch (chip_version) {
5877         case CHELSIO_T4:
5878         case CHELSIO_T5:
5879                 /* Note that this happens to be the same values as the MPS
5880                  * Buffer Group Map for these Chips.  But we replicate the code
5881                  * here because they're really separate concepts.
5882                  */
5883                 switch (nports) {
5884                 case 1: return 0xf;
5885                 case 2: return 3 << (2 * pidx);
5886                 case 4: return 1 << pidx;
5887                 }
5888                 break;
5889
5890         case CHELSIO_T6:
5891                 switch (nports) {
5892                 case 2: return 1 << pidx;
5893                 }
5894                 break;
5895         }
5896
5897         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
5898                 chip_version, nports);
5899         return 0;
5900 }
5901
5902 /**
5903  *      t4_get_port_type_description - return Port Type string description
5904  *      @port_type: firmware Port Type enumeration
5905  */
5906 const char *t4_get_port_type_description(enum fw_port_type port_type)
5907 {
5908         static const char *const port_type_description[] = {
5909                 "Fiber_XFI",
5910                 "Fiber_XAUI",
5911                 "BT_SGMII",
5912                 "BT_XFI",
5913                 "BT_XAUI",
5914                 "KX4",
5915                 "CX4",
5916                 "KX",
5917                 "KR",
5918                 "SFP",
5919                 "BP_AP",
5920                 "BP4_AP",
5921                 "QSFP_10G",
5922                 "QSA",
5923                 "QSFP",
5924                 "BP40_BA",
5925                 "KR4_100G",
5926                 "CR4_QSFP",
5927                 "CR_QSFP",
5928                 "CR2_QSFP",
5929                 "SFP28",
5930                 "KR_SFP28",
5931         };
5932
5933         if (port_type < ARRAY_SIZE(port_type_description))
5934                 return port_type_description[port_type];
5935         return "UNKNOWN";
5936 }
5937
5938 /**
5939  *      t4_get_port_stats_offset - collect port stats relative to a previous
5940  *                                 snapshot
5941  *      @adap: The adapter
5942  *      @idx: The port
5943  *      @stats: Current stats to fill
5944  *      @offset: Previous stats snapshot
5945  */
5946 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5947                               struct port_stats *stats,
5948                               struct port_stats *offset)
5949 {
5950         u64 *s, *o;
5951         int i;
5952
5953         t4_get_port_stats(adap, idx, stats);
5954         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5955                         i < (sizeof(struct port_stats) / sizeof(u64));
5956                         i++, s++, o++)
5957                 *s -= *o;
5958 }
5959
5960 /**
5961  *      t4_get_port_stats - collect port statistics
5962  *      @adap: the adapter
5963  *      @idx: the port index
5964  *      @p: the stats structure to fill
5965  *
5966  *      Collect statistics related to the given port from HW.
5967  */
5968 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5969 {
5970         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5971         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
5972
5973 #define GET_STAT(name) \
5974         t4_read_reg64(adap, \
5975         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5976         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5977 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5978
5979         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
5980         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
5981         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
5982         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
5983         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
5984         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
5985         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
5986         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
5987         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
5988         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
5989         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
5990         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5991         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
5992         p->tx_drop             = GET_STAT(TX_PORT_DROP);
5993         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
5994         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
5995         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
5996         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
5997         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
5998         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
5999         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
6000         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
6001         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
6002
6003         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6004                 if (stat_ctl & COUNTPAUSESTATTX_F)
6005                         p->tx_frames_64 -= p->tx_pause;
6006                 if (stat_ctl & COUNTPAUSEMCTX_F)
6007                         p->tx_mcast_frames -= p->tx_pause;
6008         }
6009         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6010         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6011         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6012         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6013         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6014         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6015         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6016         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6017         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6018         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6019         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6020         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6021         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6022         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6023         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6024         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6025         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6026         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6027         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6028         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6029         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6030         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6031         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6032         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6033         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6034         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6035         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6036
6037         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6038                 if (stat_ctl & COUNTPAUSESTATRX_F)
6039                         p->rx_frames_64 -= p->rx_pause;
6040                 if (stat_ctl & COUNTPAUSEMCRX_F)
6041                         p->rx_mcast_frames -= p->rx_pause;
6042         }
6043
6044         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6045         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6046         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6047         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6048         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6049         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6050         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6051         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6052
6053 #undef GET_STAT
6054 #undef GET_STAT_COM
6055 }
6056
6057 /**
6058  *      t4_get_lb_stats - collect loopback port statistics
6059  *      @adap: the adapter
6060  *      @idx: the loopback port index
6061  *      @p: the stats structure to fill
6062  *
6063  *      Return HW statistics for the given loopback port.
6064  */
6065 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6066 {
6067         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6068
6069 #define GET_STAT(name) \
6070         t4_read_reg64(adap, \
6071         (is_t4(adap->params.chip) ? \
6072         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6073         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6074 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6075
6076         p->octets           = GET_STAT(BYTES);
6077         p->frames           = GET_STAT(FRAMES);
6078         p->bcast_frames     = GET_STAT(BCAST);
6079         p->mcast_frames     = GET_STAT(MCAST);
6080         p->ucast_frames     = GET_STAT(UCAST);
6081         p->error_frames     = GET_STAT(ERROR);
6082
6083         p->frames_64        = GET_STAT(64B);
6084         p->frames_65_127    = GET_STAT(65B_127B);
6085         p->frames_128_255   = GET_STAT(128B_255B);
6086         p->frames_256_511   = GET_STAT(256B_511B);
6087         p->frames_512_1023  = GET_STAT(512B_1023B);
6088         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6089         p->frames_1519_max  = GET_STAT(1519B_MAX);
6090         p->drop             = GET_STAT(DROP_FRAMES);
6091
6092         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6093         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6094         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6095         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6096         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6097         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6098         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6099         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6100
6101 #undef GET_STAT
6102 #undef GET_STAT_COM
6103 }
6104
6105 /*     t4_mk_filtdelwr - create a delete filter WR
6106  *     @ftid: the filter ID
6107  *     @wr: the filter work request to populate
6108  *     @qid: ingress queue to receive the delete notification
6109  *
6110  *     Creates a filter work request to delete the supplied filter.  If @qid is
6111  *     negative the delete notification is suppressed.
6112  */
6113 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6114 {
6115         memset(wr, 0, sizeof(*wr));
6116         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6117         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6118         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6119                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6120         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6121         if (qid >= 0)
6122                 wr->rx_chan_rx_rpl_iq =
6123                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6124 }
6125
6126 #define INIT_CMD(var, cmd, rd_wr) do { \
6127         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6128                                         FW_CMD_REQUEST_F | \
6129                                         FW_CMD_##rd_wr##_F); \
6130         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6131 } while (0)
6132
6133 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6134                           u32 addr, u32 val)
6135 {
6136         u32 ldst_addrspace;
6137         struct fw_ldst_cmd c;
6138
6139         memset(&c, 0, sizeof(c));
6140         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6141         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6142                                         FW_CMD_REQUEST_F |
6143                                         FW_CMD_WRITE_F |
6144                                         ldst_addrspace);
6145         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6146         c.u.addrval.addr = cpu_to_be32(addr);
6147         c.u.addrval.val = cpu_to_be32(val);
6148
6149         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6150 }
6151
6152 /**
6153  *      t4_mdio_rd - read a PHY register through MDIO
6154  *      @adap: the adapter
6155  *      @mbox: mailbox to use for the FW command
6156  *      @phy_addr: the PHY address
6157  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6158  *      @reg: the register to read
6159  *      @valp: where to store the value
6160  *
6161  *      Issues a FW command through the given mailbox to read a PHY register.
6162  */
6163 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6164                unsigned int mmd, unsigned int reg, u16 *valp)
6165 {
6166         int ret;
6167         u32 ldst_addrspace;
6168         struct fw_ldst_cmd c;
6169
6170         memset(&c, 0, sizeof(c));
6171         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6172         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6173                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6174                                         ldst_addrspace);
6175         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6176         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6177                                          FW_LDST_CMD_MMD_V(mmd));
6178         c.u.mdio.raddr = cpu_to_be16(reg);
6179
6180         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6181         if (ret == 0)
6182                 *valp = be16_to_cpu(c.u.mdio.rval);
6183         return ret;
6184 }
6185
6186 /**
6187  *      t4_mdio_wr - write a PHY register through MDIO
6188  *      @adap: the adapter
6189  *      @mbox: mailbox to use for the FW command
6190  *      @phy_addr: the PHY address
6191  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6192  *      @reg: the register to write
6193  *      @valp: value to write
6194  *
6195  *      Issues a FW command through the given mailbox to write a PHY register.
6196  */
6197 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6198                unsigned int mmd, unsigned int reg, u16 val)
6199 {
6200         u32 ldst_addrspace;
6201         struct fw_ldst_cmd c;
6202
6203         memset(&c, 0, sizeof(c));
6204         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6205         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6206                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6207                                         ldst_addrspace);
6208         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6209         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6210                                          FW_LDST_CMD_MMD_V(mmd));
6211         c.u.mdio.raddr = cpu_to_be16(reg);
6212         c.u.mdio.rval = cpu_to_be16(val);
6213
6214         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6215 }
6216
6217 /**
6218  *      t4_sge_decode_idma_state - decode the idma state
6219  *      @adap: the adapter
6220  *      @state: the state idma is stuck in
6221  */
6222 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6223 {
6224         static const char * const t4_decode[] = {
6225                 "IDMA_IDLE",
6226                 "IDMA_PUSH_MORE_CPL_FIFO",
6227                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6228                 "Not used",
6229                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6230                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6231                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6232                 "IDMA_SEND_FIFO_TO_IMSG",
6233                 "IDMA_FL_REQ_DATA_FL_PREP",
6234                 "IDMA_FL_REQ_DATA_FL",
6235                 "IDMA_FL_DROP",
6236                 "IDMA_FL_H_REQ_HEADER_FL",
6237                 "IDMA_FL_H_SEND_PCIEHDR",
6238                 "IDMA_FL_H_PUSH_CPL_FIFO",
6239                 "IDMA_FL_H_SEND_CPL",
6240                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6241                 "IDMA_FL_H_SEND_IP_HDR",
6242                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6243                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6244                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6245                 "IDMA_FL_D_SEND_PCIEHDR",
6246                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6247                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6248                 "IDMA_FL_SEND_PCIEHDR",
6249                 "IDMA_FL_PUSH_CPL_FIFO",
6250                 "IDMA_FL_SEND_CPL",
6251                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6252                 "IDMA_FL_SEND_PAYLOAD",
6253                 "IDMA_FL_REQ_NEXT_DATA_FL",
6254                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6255                 "IDMA_FL_SEND_PADDING",
6256                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6257                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6258                 "IDMA_FL_REQ_DATAFL_DONE",
6259                 "IDMA_FL_REQ_HEADERFL_DONE",
6260         };
6261         static const char * const t5_decode[] = {
6262                 "IDMA_IDLE",
6263                 "IDMA_ALMOST_IDLE",
6264                 "IDMA_PUSH_MORE_CPL_FIFO",
6265                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6266                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6267                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6268                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6269                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6270                 "IDMA_SEND_FIFO_TO_IMSG",
6271                 "IDMA_FL_REQ_DATA_FL",
6272                 "IDMA_FL_DROP",
6273                 "IDMA_FL_DROP_SEND_INC",
6274                 "IDMA_FL_H_REQ_HEADER_FL",
6275                 "IDMA_FL_H_SEND_PCIEHDR",
6276                 "IDMA_FL_H_PUSH_CPL_FIFO",
6277                 "IDMA_FL_H_SEND_CPL",
6278                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6279                 "IDMA_FL_H_SEND_IP_HDR",
6280                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6281                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6282                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6283                 "IDMA_FL_D_SEND_PCIEHDR",
6284                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6285                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6286                 "IDMA_FL_SEND_PCIEHDR",
6287                 "IDMA_FL_PUSH_CPL_FIFO",
6288                 "IDMA_FL_SEND_CPL",
6289                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6290                 "IDMA_FL_SEND_PAYLOAD",
6291                 "IDMA_FL_REQ_NEXT_DATA_FL",
6292                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6293                 "IDMA_FL_SEND_PADDING",
6294                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6295         };
6296         static const char * const t6_decode[] = {
6297                 "IDMA_IDLE",
6298                 "IDMA_PUSH_MORE_CPL_FIFO",
6299                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6300                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6301                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6302                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6303                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6304                 "IDMA_FL_REQ_DATA_FL",
6305                 "IDMA_FL_DROP",
6306                 "IDMA_FL_DROP_SEND_INC",
6307                 "IDMA_FL_H_REQ_HEADER_FL",
6308                 "IDMA_FL_H_SEND_PCIEHDR",
6309                 "IDMA_FL_H_PUSH_CPL_FIFO",
6310                 "IDMA_FL_H_SEND_CPL",
6311                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6312                 "IDMA_FL_H_SEND_IP_HDR",
6313                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6314                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6315                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6316                 "IDMA_FL_D_SEND_PCIEHDR",
6317                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6318                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6319                 "IDMA_FL_SEND_PCIEHDR",
6320                 "IDMA_FL_PUSH_CPL_FIFO",
6321                 "IDMA_FL_SEND_CPL",
6322                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6323                 "IDMA_FL_SEND_PAYLOAD",
6324                 "IDMA_FL_REQ_NEXT_DATA_FL",
6325                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6326                 "IDMA_FL_SEND_PADDING",
6327                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6328         };
6329         static const u32 sge_regs[] = {
6330                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6331                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6332                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6333         };
6334         const char **sge_idma_decode;
6335         int sge_idma_decode_nstates;
6336         int i;
6337         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6338
6339         /* Select the right set of decode strings to dump depending on the
6340          * adapter chip type.
6341          */
6342         switch (chip_version) {
6343         case CHELSIO_T4:
6344                 sge_idma_decode = (const char **)t4_decode;
6345                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6346                 break;
6347
6348         case CHELSIO_T5:
6349                 sge_idma_decode = (const char **)t5_decode;
6350                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6351                 break;
6352
6353         case CHELSIO_T6:
6354                 sge_idma_decode = (const char **)t6_decode;
6355                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6356                 break;
6357
6358         default:
6359                 dev_err(adapter->pdev_dev,
6360                         "Unsupported chip version %d\n", chip_version);
6361                 return;
6362         }
6363
6364         if (is_t4(adapter->params.chip)) {
6365                 sge_idma_decode = (const char **)t4_decode;
6366                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6367         } else {
6368                 sge_idma_decode = (const char **)t5_decode;
6369                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6370         }
6371
6372         if (state < sge_idma_decode_nstates)
6373                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6374         else
6375                 CH_WARN(adapter, "idma state %d unknown\n", state);
6376
6377         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6378                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6379                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6380 }
6381
6382 /**
6383  *      t4_sge_ctxt_flush - flush the SGE context cache
6384  *      @adap: the adapter
6385  *      @mbox: mailbox to use for the FW command
6386  *
6387  *      Issues a FW command through the given mailbox to flush the
6388  *      SGE context cache.
6389  */
6390 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6391 {
6392         int ret;
6393         u32 ldst_addrspace;
6394         struct fw_ldst_cmd c;
6395
6396         memset(&c, 0, sizeof(c));
6397         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
6398         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6399                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6400                                         ldst_addrspace);
6401         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6402         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6403
6404         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6405         return ret;
6406 }
6407
6408 /**
6409  *      t4_fw_hello - establish communication with FW
6410  *      @adap: the adapter
6411  *      @mbox: mailbox to use for the FW command
6412  *      @evt_mbox: mailbox to receive async FW events
6413  *      @master: specifies the caller's willingness to be the device master
6414  *      @state: returns the current device state (if non-NULL)
6415  *
6416  *      Issues a command to establish communication with FW.  Returns either
6417  *      an error (negative integer) or the mailbox of the Master PF.
6418  */
6419 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6420                 enum dev_master master, enum dev_state *state)
6421 {
6422         int ret;
6423         struct fw_hello_cmd c;
6424         u32 v;
6425         unsigned int master_mbox;
6426         int retries = FW_CMD_HELLO_RETRIES;
6427
6428 retry:
6429         memset(&c, 0, sizeof(c));
6430         INIT_CMD(c, HELLO, WRITE);
6431         c.err_to_clearinit = cpu_to_be32(
6432                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6433                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6434                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6435                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6436                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6437                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6438                 FW_HELLO_CMD_CLEARINIT_F);
6439
6440         /*
6441          * Issue the HELLO command to the firmware.  If it's not successful
6442          * but indicates that we got a "busy" or "timeout" condition, retry
6443          * the HELLO until we exhaust our retry limit.  If we do exceed our
6444          * retry limit, check to see if the firmware left us any error
6445          * information and report that if so.
6446          */
6447         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6448         if (ret < 0) {
6449                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6450                         goto retry;
6451                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6452                         t4_report_fw_error(adap);
6453                 return ret;
6454         }
6455
6456         v = be32_to_cpu(c.err_to_clearinit);
6457         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6458         if (state) {
6459                 if (v & FW_HELLO_CMD_ERR_F)
6460                         *state = DEV_STATE_ERR;
6461                 else if (v & FW_HELLO_CMD_INIT_F)
6462                         *state = DEV_STATE_INIT;
6463                 else
6464                         *state = DEV_STATE_UNINIT;
6465         }
6466
6467         /*
6468          * If we're not the Master PF then we need to wait around for the
6469          * Master PF Driver to finish setting up the adapter.
6470          *
6471          * Note that we also do this wait if we're a non-Master-capable PF and
6472          * there is no current Master PF; a Master PF may show up momentarily
6473          * and we wouldn't want to fail pointlessly.  (This can happen when an
6474          * OS loads lots of different drivers rapidly at the same time).  In
6475          * this case, the Master PF returned by the firmware will be
6476          * PCIE_FW_MASTER_M so the test below will work ...
6477          */
6478         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6479             master_mbox != mbox) {
6480                 int waiting = FW_CMD_HELLO_TIMEOUT;
6481
6482                 /*
6483                  * Wait for the firmware to either indicate an error or
6484                  * initialized state.  If we see either of these we bail out
6485                  * and report the issue to the caller.  If we exhaust the
6486                  * "hello timeout" and we haven't exhausted our retries, try
6487                  * again.  Otherwise bail with a timeout error.
6488                  */
6489                 for (;;) {
6490                         u32 pcie_fw;
6491
6492                         msleep(50);
6493                         waiting -= 50;
6494
6495                         /*
6496                          * If neither Error nor Initialialized are indicated
6497                          * by the firmware keep waiting till we exaust our
6498                          * timeout ... and then retry if we haven't exhausted
6499                          * our retries ...
6500                          */
6501                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6502                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6503                                 if (waiting <= 0) {
6504                                         if (retries-- > 0)
6505                                                 goto retry;
6506
6507                                         return -ETIMEDOUT;
6508                                 }
6509                                 continue;
6510                         }
6511
6512                         /*
6513                          * We either have an Error or Initialized condition
6514                          * report errors preferentially.
6515                          */
6516                         if (state) {
6517                                 if (pcie_fw & PCIE_FW_ERR_F)
6518                                         *state = DEV_STATE_ERR;
6519                                 else if (pcie_fw & PCIE_FW_INIT_F)
6520                                         *state = DEV_STATE_INIT;
6521                         }
6522
6523                         /*
6524                          * If we arrived before a Master PF was selected and
6525                          * there's not a valid Master PF, grab its identity
6526                          * for our caller.
6527                          */
6528                         if (master_mbox == PCIE_FW_MASTER_M &&
6529                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6530                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6531                         break;
6532                 }
6533         }
6534
6535         return master_mbox;
6536 }
6537
6538 /**
6539  *      t4_fw_bye - end communication with FW
6540  *      @adap: the adapter
6541  *      @mbox: mailbox to use for the FW command
6542  *
6543  *      Issues a command to terminate communication with FW.
6544  */
6545 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6546 {
6547         struct fw_bye_cmd c;
6548
6549         memset(&c, 0, sizeof(c));
6550         INIT_CMD(c, BYE, WRITE);
6551         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6552 }
6553
6554 /**
6555  *      t4_init_cmd - ask FW to initialize the device
6556  *      @adap: the adapter
6557  *      @mbox: mailbox to use for the FW command
6558  *
6559  *      Issues a command to FW to partially initialize the device.  This
6560  *      performs initialization that generally doesn't depend on user input.
6561  */
6562 int t4_early_init(struct adapter *adap, unsigned int mbox)
6563 {
6564         struct fw_initialize_cmd c;
6565
6566         memset(&c, 0, sizeof(c));
6567         INIT_CMD(c, INITIALIZE, WRITE);
6568         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6569 }
6570
6571 /**
6572  *      t4_fw_reset - issue a reset to FW
6573  *      @adap: the adapter
6574  *      @mbox: mailbox to use for the FW command
6575  *      @reset: specifies the type of reset to perform
6576  *
6577  *      Issues a reset command of the specified type to FW.
6578  */
6579 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6580 {
6581         struct fw_reset_cmd c;
6582
6583         memset(&c, 0, sizeof(c));
6584         INIT_CMD(c, RESET, WRITE);
6585         c.val = cpu_to_be32(reset);
6586         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6587 }
6588
6589 /**
6590  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6591  *      @adap: the adapter
6592  *      @mbox: mailbox to use for the FW RESET command (if desired)
6593  *      @force: force uP into RESET even if FW RESET command fails
6594  *
6595  *      Issues a RESET command to firmware (if desired) with a HALT indication
6596  *      and then puts the microprocessor into RESET state.  The RESET command
6597  *      will only be issued if a legitimate mailbox is provided (mbox <=
6598  *      PCIE_FW_MASTER_M).
6599  *
6600  *      This is generally used in order for the host to safely manipulate the
6601  *      adapter without fear of conflicting with whatever the firmware might
6602  *      be doing.  The only way out of this state is to RESTART the firmware
6603  *      ...
6604  */
6605 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6606 {
6607         int ret = 0;
6608
6609         /*
6610          * If a legitimate mailbox is provided, issue a RESET command
6611          * with a HALT indication.
6612          */
6613         if (mbox <= PCIE_FW_MASTER_M) {
6614                 struct fw_reset_cmd c;
6615
6616                 memset(&c, 0, sizeof(c));
6617                 INIT_CMD(c, RESET, WRITE);
6618                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6619                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6620                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6621         }
6622
6623         /*
6624          * Normally we won't complete the operation if the firmware RESET
6625          * command fails but if our caller insists we'll go ahead and put the
6626          * uP into RESET.  This can be useful if the firmware is hung or even
6627          * missing ...  We'll have to take the risk of putting the uP into
6628          * RESET without the cooperation of firmware in that case.
6629          *
6630          * We also force the firmware's HALT flag to be on in case we bypassed
6631          * the firmware RESET command above or we're dealing with old firmware
6632          * which doesn't have the HALT capability.  This will serve as a flag
6633          * for the incoming firmware to know that it's coming out of a HALT
6634          * rather than a RESET ... if it's new enough to understand that ...
6635          */
6636         if (ret == 0 || force) {
6637                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6638                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6639                                  PCIE_FW_HALT_F);
6640         }
6641
6642         /*
6643          * And we always return the result of the firmware RESET command
6644          * even when we force the uP into RESET ...
6645          */
6646         return ret;
6647 }
6648
6649 /**
6650  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6651  *      @adap: the adapter
6652  *      @reset: if we want to do a RESET to restart things
6653  *
6654  *      Restart firmware previously halted by t4_fw_halt().  On successful
6655  *      return the previous PF Master remains as the new PF Master and there
6656  *      is no need to issue a new HELLO command, etc.
6657  *
6658  *      We do this in two ways:
6659  *
6660  *       1. If we're dealing with newer firmware we'll simply want to take
6661  *          the chip's microprocessor out of RESET.  This will cause the
6662  *          firmware to start up from its start vector.  And then we'll loop
6663  *          until the firmware indicates it's started again (PCIE_FW.HALT
6664  *          reset to 0) or we timeout.
6665  *
6666  *       2. If we're dealing with older firmware then we'll need to RESET
6667  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6668  *          flag and automatically RESET itself on startup.
6669  */
6670 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6671 {
6672         if (reset) {
6673                 /*
6674                  * Since we're directing the RESET instead of the firmware
6675                  * doing it automatically, we need to clear the PCIE_FW.HALT
6676                  * bit.
6677                  */
6678                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6679
6680                 /*
6681                  * If we've been given a valid mailbox, first try to get the
6682                  * firmware to do the RESET.  If that works, great and we can
6683                  * return success.  Otherwise, if we haven't been given a
6684                  * valid mailbox or the RESET command failed, fall back to
6685                  * hitting the chip with a hammer.
6686                  */
6687                 if (mbox <= PCIE_FW_MASTER_M) {
6688                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6689                         msleep(100);
6690                         if (t4_fw_reset(adap, mbox,
6691                                         PIORST_F | PIORSTMODE_F) == 0)
6692                                 return 0;
6693                 }
6694
6695                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6696                 msleep(2000);
6697         } else {
6698                 int ms;
6699
6700                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6701                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6702                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6703                                 return 0;
6704                         msleep(100);
6705                         ms += 100;
6706                 }
6707                 return -ETIMEDOUT;
6708         }
6709         return 0;
6710 }
6711
6712 /**
6713  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6714  *      @adap: the adapter
6715  *      @mbox: mailbox to use for the FW RESET command (if desired)
6716  *      @fw_data: the firmware image to write
6717  *      @size: image size
6718  *      @force: force upgrade even if firmware doesn't cooperate
6719  *
6720  *      Perform all of the steps necessary for upgrading an adapter's
6721  *      firmware image.  Normally this requires the cooperation of the
6722  *      existing firmware in order to halt all existing activities
6723  *      but if an invalid mailbox token is passed in we skip that step
6724  *      (though we'll still put the adapter microprocessor into RESET in
6725  *      that case).
6726  *
6727  *      On successful return the new firmware will have been loaded and
6728  *      the adapter will have been fully RESET losing all previous setup
6729  *      state.  On unsuccessful return the adapter may be completely hosed ...
6730  *      positive errno indicates that the adapter is ~probably~ intact, a
6731  *      negative errno indicates that things are looking bad ...
6732  */
6733 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6734                   const u8 *fw_data, unsigned int size, int force)
6735 {
6736         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6737         int reset, ret;
6738
6739         if (!t4_fw_matches_chip(adap, fw_hdr))
6740                 return -EINVAL;
6741
6742         /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6743          * wont be sent when we are flashing FW.
6744          */
6745         adap->flags &= ~FW_OK;
6746
6747         ret = t4_fw_halt(adap, mbox, force);
6748         if (ret < 0 && !force)
6749                 goto out;
6750
6751         ret = t4_load_fw(adap, fw_data, size);
6752         if (ret < 0)
6753                 goto out;
6754
6755         /*
6756          * If there was a Firmware Configuration File stored in FLASH,
6757          * there's a good chance that it won't be compatible with the new
6758          * Firmware.  In order to prevent difficult to diagnose adapter
6759          * initialization issues, we clear out the Firmware Configuration File
6760          * portion of the FLASH .  The user will need to re-FLASH a new
6761          * Firmware Configuration File which is compatible with the new
6762          * Firmware if that's desired.
6763          */
6764         (void)t4_load_cfg(adap, NULL, 0);
6765
6766         /*
6767          * Older versions of the firmware don't understand the new
6768          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6769          * restart.  So for newly loaded older firmware we'll have to do the
6770          * RESET for it so it starts up on a clean slate.  We can tell if
6771          * the newly loaded firmware will handle this right by checking
6772          * its header flags to see if it advertises the capability.
6773          */
6774         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6775         ret = t4_fw_restart(adap, mbox, reset);
6776
6777         /* Grab potentially new Firmware Device Log parameters so we can see
6778          * how healthy the new Firmware is.  It's okay to contact the new
6779          * Firmware for these parameters even though, as far as it's
6780          * concerned, we've never said "HELLO" to it ...
6781          */
6782         (void)t4_init_devlog_params(adap);
6783 out:
6784         adap->flags |= FW_OK;
6785         return ret;
6786 }
6787
6788 /**
6789  *      t4_fl_pkt_align - return the fl packet alignment
6790  *      @adap: the adapter
6791  *
6792  *      T4 has a single field to specify the packing and padding boundary.
6793  *      T5 onwards has separate fields for this and hence the alignment for
6794  *      next packet offset is maximum of these two.
6795  *
6796  */
6797 int t4_fl_pkt_align(struct adapter *adap)
6798 {
6799         u32 sge_control, sge_control2;
6800         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6801
6802         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6803
6804         /* T4 uses a single control field to specify both the PCIe Padding and
6805          * Packing Boundary.  T5 introduced the ability to specify these
6806          * separately.  The actual Ingress Packet Data alignment boundary
6807          * within Packed Buffer Mode is the maximum of these two
6808          * specifications.  (Note that it makes no real practical sense to
6809          * have the Pading Boudary be larger than the Packing Boundary but you
6810          * could set the chip up that way and, in fact, legacy T4 code would
6811          * end doing this because it would initialize the Padding Boundary and
6812          * leave the Packing Boundary initialized to 0 (16 bytes).)
6813          * Padding Boundary values in T6 starts from 8B,
6814          * where as it is 32B for T4 and T5.
6815          */
6816         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6817                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6818         else
6819                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6820
6821         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6822
6823         fl_align = ingpadboundary;
6824         if (!is_t4(adap->params.chip)) {
6825                 /* T5 has a weird interpretation of one of the PCIe Packing
6826                  * Boundary values.  No idea why ...
6827                  */
6828                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6829                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6830                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6831                         ingpackboundary = 16;
6832                 else
6833                         ingpackboundary = 1 << (ingpackboundary +
6834                                                 INGPACKBOUNDARY_SHIFT_X);
6835
6836                 fl_align = max(ingpadboundary, ingpackboundary);
6837         }
6838         return fl_align;
6839 }
6840
6841 /**
6842  *      t4_fixup_host_params - fix up host-dependent parameters
6843  *      @adap: the adapter
6844  *      @page_size: the host's Base Page Size
6845  *      @cache_line_size: the host's Cache Line Size
6846  *
6847  *      Various registers in T4 contain values which are dependent on the
6848  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6849  *      those registers with the appropriate values as passed in ...
6850  */
6851 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6852                          unsigned int cache_line_size)
6853 {
6854         unsigned int page_shift = fls(page_size) - 1;
6855         unsigned int sge_hps = page_shift - 10;
6856         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6857         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6858         unsigned int fl_align_log = fls(fl_align) - 1;
6859
6860         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6861                      HOSTPAGESIZEPF0_V(sge_hps) |
6862                      HOSTPAGESIZEPF1_V(sge_hps) |
6863                      HOSTPAGESIZEPF2_V(sge_hps) |
6864                      HOSTPAGESIZEPF3_V(sge_hps) |
6865                      HOSTPAGESIZEPF4_V(sge_hps) |
6866                      HOSTPAGESIZEPF5_V(sge_hps) |
6867                      HOSTPAGESIZEPF6_V(sge_hps) |
6868                      HOSTPAGESIZEPF7_V(sge_hps));
6869
6870         if (is_t4(adap->params.chip)) {
6871                 t4_set_reg_field(adap, SGE_CONTROL_A,
6872                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6873                                  EGRSTATUSPAGESIZE_F,
6874                                  INGPADBOUNDARY_V(fl_align_log -
6875                                                   INGPADBOUNDARY_SHIFT_X) |
6876                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6877         } else {
6878                 unsigned int pack_align;
6879                 unsigned int ingpad, ingpack;
6880                 unsigned int pcie_cap;
6881
6882                 /* T5 introduced the separation of the Free List Padding and
6883                  * Packing Boundaries.  Thus, we can select a smaller Padding
6884                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
6885                  * Bandwidth, and use a Packing Boundary which is large enough
6886                  * to avoid false sharing between CPUs, etc.
6887                  *
6888                  * For the PCI Link, the smaller the Padding Boundary the
6889                  * better.  For the Memory Controller, a smaller Padding
6890                  * Boundary is better until we cross under the Memory Line
6891                  * Size (the minimum unit of transfer to/from Memory).  If we
6892                  * have a Padding Boundary which is smaller than the Memory
6893                  * Line Size, that'll involve a Read-Modify-Write cycle on the
6894                  * Memory Controller which is never good.
6895                  */
6896
6897                 /* We want the Packing Boundary to be based on the Cache Line
6898                  * Size in order to help avoid False Sharing performance
6899                  * issues between CPUs, etc.  We also want the Packing
6900                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
6901                  * get best performance when the Packing Boundary is a
6902                  * multiple of the Maximum Payload Size.
6903                  */
6904                 pack_align = fl_align;
6905                 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
6906                 if (pcie_cap) {
6907                         unsigned int mps, mps_log;
6908                         u16 devctl;
6909
6910                         /* The PCIe Device Control Maximum Payload Size field
6911                          * [bits 7:5] encodes sizes as powers of 2 starting at
6912                          * 128 bytes.
6913                          */
6914                         pci_read_config_word(adap->pdev,
6915                                              pcie_cap + PCI_EXP_DEVCTL,
6916                                              &devctl);
6917                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
6918                         mps = 1 << mps_log;
6919                         if (mps > pack_align)
6920                                 pack_align = mps;
6921                 }
6922
6923                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
6924                  * value for the Packing Boundary.  This corresponds to 16
6925                  * bytes instead of the expected 32 bytes.  So if we want 32
6926                  * bytes, the best we can really do is 64 bytes ...
6927                  */
6928                 if (pack_align <= 16) {
6929                         ingpack = INGPACKBOUNDARY_16B_X;
6930                         fl_align = 16;
6931                 } else if (pack_align == 32) {
6932                         ingpack = INGPACKBOUNDARY_64B_X;
6933                         fl_align = 64;
6934                 } else {
6935                         unsigned int pack_align_log = fls(pack_align) - 1;
6936
6937                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
6938                         fl_align = pack_align;
6939                 }
6940
6941                 /* Use the smallest Ingress Padding which isn't smaller than
6942                  * the Memory Controller Read/Write Size.  We'll take that as
6943                  * being 8 bytes since we don't know of any system with a
6944                  * wider Memory Controller Bus Width.
6945                  */
6946                 if (is_t5(adap->params.chip))
6947                         ingpad = INGPADBOUNDARY_32B_X;
6948                 else
6949                         ingpad = T6_INGPADBOUNDARY_8B_X;
6950
6951                 t4_set_reg_field(adap, SGE_CONTROL_A,
6952                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6953                                  EGRSTATUSPAGESIZE_F,
6954                                  INGPADBOUNDARY_V(ingpad) |
6955                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6956                 t4_set_reg_field(adap, SGE_CONTROL2_A,
6957                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6958                                  INGPACKBOUNDARY_V(ingpack));
6959         }
6960         /*
6961          * Adjust various SGE Free List Host Buffer Sizes.
6962          *
6963          * This is something of a crock since we're using fixed indices into
6964          * the array which are also known by the sge.c code and the T4
6965          * Firmware Configuration File.  We need to come up with a much better
6966          * approach to managing this array.  For now, the first four entries
6967          * are:
6968          *
6969          *   0: Host Page Size
6970          *   1: 64KB
6971          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6972          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6973          *
6974          * For the single-MTU buffers in unpacked mode we need to include
6975          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6976          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6977          * Padding boundary.  All of these are accommodated in the Factory
6978          * Default Firmware Configuration File but we need to adjust it for
6979          * this host's cache line size.
6980          */
6981         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6982         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6983                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6984                      & ~(fl_align-1));
6985         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6986                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6987                      & ~(fl_align-1));
6988
6989         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6990
6991         return 0;
6992 }
6993
6994 /**
6995  *      t4_fw_initialize - ask FW to initialize the device
6996  *      @adap: the adapter
6997  *      @mbox: mailbox to use for the FW command
6998  *
6999  *      Issues a command to FW to partially initialize the device.  This
7000  *      performs initialization that generally doesn't depend on user input.
7001  */
7002 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7003 {
7004         struct fw_initialize_cmd c;
7005
7006         memset(&c, 0, sizeof(c));
7007         INIT_CMD(c, INITIALIZE, WRITE);
7008         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7009 }
7010
7011 /**
7012  *      t4_query_params_rw - query FW or device parameters
7013  *      @adap: the adapter
7014  *      @mbox: mailbox to use for the FW command
7015  *      @pf: the PF
7016  *      @vf: the VF
7017  *      @nparams: the number of parameters
7018  *      @params: the parameter names
7019  *      @val: the parameter values
7020  *      @rw: Write and read flag
7021  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7022  *
7023  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7024  *      queried at once.
7025  */
7026 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7027                        unsigned int vf, unsigned int nparams, const u32 *params,
7028                        u32 *val, int rw, bool sleep_ok)
7029 {
7030         int i, ret;
7031         struct fw_params_cmd c;
7032         __be32 *p = &c.param[0].mnem;
7033
7034         if (nparams > 7)
7035                 return -EINVAL;
7036
7037         memset(&c, 0, sizeof(c));
7038         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7039                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7040                                   FW_PARAMS_CMD_PFN_V(pf) |
7041                                   FW_PARAMS_CMD_VFN_V(vf));
7042         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7043
7044         for (i = 0; i < nparams; i++) {
7045                 *p++ = cpu_to_be32(*params++);
7046                 if (rw)
7047                         *p = cpu_to_be32(*(val + i));
7048                 p++;
7049         }
7050
7051         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7052         if (ret == 0)
7053                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7054                         *val++ = be32_to_cpu(*p);
7055         return ret;
7056 }
7057
7058 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7059                     unsigned int vf, unsigned int nparams, const u32 *params,
7060                     u32 *val)
7061 {
7062         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7063                                   true);
7064 }
7065
7066 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7067                        unsigned int vf, unsigned int nparams, const u32 *params,
7068                        u32 *val)
7069 {
7070         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7071                                   false);
7072 }
7073
7074 /**
7075  *      t4_set_params_timeout - sets FW or device parameters
7076  *      @adap: the adapter
7077  *      @mbox: mailbox to use for the FW command
7078  *      @pf: the PF
7079  *      @vf: the VF
7080  *      @nparams: the number of parameters
7081  *      @params: the parameter names
7082  *      @val: the parameter values
7083  *      @timeout: the timeout time
7084  *
7085  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7086  *      specified at once.
7087  */
7088 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7089                           unsigned int pf, unsigned int vf,
7090                           unsigned int nparams, const u32 *params,
7091                           const u32 *val, int timeout)
7092 {
7093         struct fw_params_cmd c;
7094         __be32 *p = &c.param[0].mnem;
7095
7096         if (nparams > 7)
7097                 return -EINVAL;
7098
7099         memset(&c, 0, sizeof(c));
7100         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7101                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7102                                   FW_PARAMS_CMD_PFN_V(pf) |
7103                                   FW_PARAMS_CMD_VFN_V(vf));
7104         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7105
7106         while (nparams--) {
7107                 *p++ = cpu_to_be32(*params++);
7108                 *p++ = cpu_to_be32(*val++);
7109         }
7110
7111         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7112 }
7113
7114 /**
7115  *      t4_set_params - sets FW or device parameters
7116  *      @adap: the adapter
7117  *      @mbox: mailbox to use for the FW command
7118  *      @pf: the PF
7119  *      @vf: the VF
7120  *      @nparams: the number of parameters
7121  *      @params: the parameter names
7122  *      @val: the parameter values
7123  *
7124  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7125  *      specified at once.
7126  */
7127 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7128                   unsigned int vf, unsigned int nparams, const u32 *params,
7129                   const u32 *val)
7130 {
7131         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7132                                      FW_CMD_MAX_TIMEOUT);
7133 }
7134
7135 /**
7136  *      t4_cfg_pfvf - configure PF/VF resource limits
7137  *      @adap: the adapter
7138  *      @mbox: mailbox to use for the FW command
7139  *      @pf: the PF being configured
7140  *      @vf: the VF being configured
7141  *      @txq: the max number of egress queues
7142  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7143  *      @rxqi: the max number of interrupt-capable ingress queues
7144  *      @rxq: the max number of interruptless ingress queues
7145  *      @tc: the PCI traffic class
7146  *      @vi: the max number of virtual interfaces
7147  *      @cmask: the channel access rights mask for the PF/VF
7148  *      @pmask: the port access rights mask for the PF/VF
7149  *      @nexact: the maximum number of exact MPS filters
7150  *      @rcaps: read capabilities
7151  *      @wxcaps: write/execute capabilities
7152  *
7153  *      Configures resource limits and capabilities for a physical or virtual
7154  *      function.
7155  */
7156 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7157                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7158                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7159                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7160                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7161 {
7162         struct fw_pfvf_cmd c;
7163
7164         memset(&c, 0, sizeof(c));
7165         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7166                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7167                                   FW_PFVF_CMD_VFN_V(vf));
7168         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7169         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7170                                      FW_PFVF_CMD_NIQ_V(rxq));
7171         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7172                                     FW_PFVF_CMD_PMASK_V(pmask) |
7173                                     FW_PFVF_CMD_NEQ_V(txq));
7174         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7175                                       FW_PFVF_CMD_NVI_V(vi) |
7176                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7177         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7178                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7179                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7180         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7181 }
7182
7183 /**
7184  *      t4_alloc_vi - allocate a virtual interface
7185  *      @adap: the adapter
7186  *      @mbox: mailbox to use for the FW command
7187  *      @port: physical port associated with the VI
7188  *      @pf: the PF owning the VI
7189  *      @vf: the VF owning the VI
7190  *      @nmac: number of MAC addresses needed (1 to 5)
7191  *      @mac: the MAC addresses of the VI
7192  *      @rss_size: size of RSS table slice associated with this VI
7193  *
7194  *      Allocates a virtual interface for the given physical port.  If @mac is
7195  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7196  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7197  *      stored consecutively so the space needed is @nmac * 6 bytes.
7198  *      Returns a negative error number or the non-negative VI id.
7199  */
7200 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7201                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7202                 unsigned int *rss_size)
7203 {
7204         int ret;
7205         struct fw_vi_cmd c;
7206
7207         memset(&c, 0, sizeof(c));
7208         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7209                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7210                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7211         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7212         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7213         c.nmac = nmac - 1;
7214
7215         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7216         if (ret)
7217                 return ret;
7218
7219         if (mac) {
7220                 memcpy(mac, c.mac, sizeof(c.mac));
7221                 switch (nmac) {
7222                 case 5:
7223                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7224                 case 4:
7225                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7226                 case 3:
7227                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7228                 case 2:
7229                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7230                 }
7231         }
7232         if (rss_size)
7233                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7234         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7235 }
7236
7237 /**
7238  *      t4_free_vi - free a virtual interface
7239  *      @adap: the adapter
7240  *      @mbox: mailbox to use for the FW command
7241  *      @pf: the PF owning the VI
7242  *      @vf: the VF owning the VI
7243  *      @viid: virtual interface identifiler
7244  *
7245  *      Free a previously allocated virtual interface.
7246  */
7247 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7248                unsigned int vf, unsigned int viid)
7249 {
7250         struct fw_vi_cmd c;
7251
7252         memset(&c, 0, sizeof(c));
7253         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7254                                   FW_CMD_REQUEST_F |
7255                                   FW_CMD_EXEC_F |
7256                                   FW_VI_CMD_PFN_V(pf) |
7257                                   FW_VI_CMD_VFN_V(vf));
7258         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7259         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7260
7261         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7262 }
7263
7264 /**
7265  *      t4_set_rxmode - set Rx properties of a virtual interface
7266  *      @adap: the adapter
7267  *      @mbox: mailbox to use for the FW command
7268  *      @viid: the VI id
7269  *      @mtu: the new MTU or -1
7270  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7271  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7272  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7273  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7274  *      @sleep_ok: if true we may sleep while awaiting command completion
7275  *
7276  *      Sets Rx properties of a virtual interface.
7277  */
7278 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7279                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7280                   bool sleep_ok)
7281 {
7282         struct fw_vi_rxmode_cmd c;
7283
7284         /* convert to FW values */
7285         if (mtu < 0)
7286                 mtu = FW_RXMODE_MTU_NO_CHG;
7287         if (promisc < 0)
7288                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7289         if (all_multi < 0)
7290                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7291         if (bcast < 0)
7292                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7293         if (vlanex < 0)
7294                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7295
7296         memset(&c, 0, sizeof(c));
7297         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7298                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7299                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7300         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7301         c.mtu_to_vlanexen =
7302                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7303                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7304                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7305                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7306                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7307         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7308 }
7309
7310 /**
7311  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7312  *      @adap: the adapter
7313  *      @mbox: mailbox to use for the FW command
7314  *      @viid: the VI id
7315  *      @free: if true any existing filters for this VI id are first removed
7316  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7317  *      @addr: the MAC address(es)
7318  *      @idx: where to store the index of each allocated filter
7319  *      @hash: pointer to hash address filter bitmap
7320  *      @sleep_ok: call is allowed to sleep
7321  *
7322  *      Allocates an exact-match filter for each of the supplied addresses and
7323  *      sets it to the corresponding address.  If @idx is not %NULL it should
7324  *      have at least @naddr entries, each of which will be set to the index of
7325  *      the filter allocated for the corresponding MAC address.  If a filter
7326  *      could not be allocated for an address its index is set to 0xffff.
7327  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7328  *      are hashed and update the hash filter bitmap pointed at by @hash.
7329  *
7330  *      Returns a negative error number or the number of filters allocated.
7331  */
7332 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7333                       unsigned int viid, bool free, unsigned int naddr,
7334                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7335 {
7336         int offset, ret = 0;
7337         struct fw_vi_mac_cmd c;
7338         unsigned int nfilters = 0;
7339         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7340         unsigned int rem = naddr;
7341
7342         if (naddr > max_naddr)
7343                 return -EINVAL;
7344
7345         for (offset = 0; offset < naddr ; /**/) {
7346                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7347                                          rem : ARRAY_SIZE(c.u.exact));
7348                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7349                                                      u.exact[fw_naddr]), 16);
7350                 struct fw_vi_mac_exact *p;
7351                 int i;
7352
7353                 memset(&c, 0, sizeof(c));
7354                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7355                                            FW_CMD_REQUEST_F |
7356                                            FW_CMD_WRITE_F |
7357                                            FW_CMD_EXEC_V(free) |
7358                                            FW_VI_MAC_CMD_VIID_V(viid));
7359                 c.freemacs_to_len16 =
7360                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7361                                     FW_CMD_LEN16_V(len16));
7362
7363                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7364                         p->valid_to_idx =
7365                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7366                                             FW_VI_MAC_CMD_IDX_V(
7367                                                     FW_VI_MAC_ADD_MAC));
7368                         memcpy(p->macaddr, addr[offset + i],
7369                                sizeof(p->macaddr));
7370                 }
7371
7372                 /* It's okay if we run out of space in our MAC address arena.
7373                  * Some of the addresses we submit may get stored so we need
7374                  * to run through the reply to see what the results were ...
7375                  */
7376                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7377                 if (ret && ret != -FW_ENOMEM)
7378                         break;
7379
7380                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7381                         u16 index = FW_VI_MAC_CMD_IDX_G(
7382                                         be16_to_cpu(p->valid_to_idx));
7383
7384                         if (idx)
7385                                 idx[offset + i] = (index >= max_naddr ?
7386                                                    0xffff : index);
7387                         if (index < max_naddr)
7388                                 nfilters++;
7389                         else if (hash)
7390                                 *hash |= (1ULL <<
7391                                           hash_mac_addr(addr[offset + i]));
7392                 }
7393
7394                 free = false;
7395                 offset += fw_naddr;
7396                 rem -= fw_naddr;
7397         }
7398
7399         if (ret == 0 || ret == -FW_ENOMEM)
7400                 ret = nfilters;
7401         return ret;
7402 }
7403
7404 /**
7405  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
7406  *      @adap: the adapter
7407  *      @mbox: mailbox to use for the FW command
7408  *      @viid: the VI id
7409  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7410  *      @addr: the MAC address(es)
7411  *      @sleep_ok: call is allowed to sleep
7412  *
7413  *      Frees the exact-match filter for each of the supplied addresses
7414  *
7415  *      Returns a negative error number or the number of filters freed.
7416  */
7417 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7418                      unsigned int viid, unsigned int naddr,
7419                      const u8 **addr, bool sleep_ok)
7420 {
7421         int offset, ret = 0;
7422         struct fw_vi_mac_cmd c;
7423         unsigned int nfilters = 0;
7424         unsigned int max_naddr = is_t4(adap->params.chip) ?
7425                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
7426                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7427         unsigned int rem = naddr;
7428
7429         if (naddr > max_naddr)
7430                 return -EINVAL;
7431
7432         for (offset = 0; offset < (int)naddr ; /**/) {
7433                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7434                                          ? rem
7435                                          : ARRAY_SIZE(c.u.exact));
7436                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7437                                                      u.exact[fw_naddr]), 16);
7438                 struct fw_vi_mac_exact *p;
7439                 int i;
7440
7441                 memset(&c, 0, sizeof(c));
7442                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7443                                      FW_CMD_REQUEST_F |
7444                                      FW_CMD_WRITE_F |
7445                                      FW_CMD_EXEC_V(0) |
7446                                      FW_VI_MAC_CMD_VIID_V(viid));
7447                 c.freemacs_to_len16 =
7448                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7449                                             FW_CMD_LEN16_V(len16));
7450
7451                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7452                         p->valid_to_idx = cpu_to_be16(
7453                                 FW_VI_MAC_CMD_VALID_F |
7454                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7455                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7456                 }
7457
7458                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7459                 if (ret)
7460                         break;
7461
7462                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7463                         u16 index = FW_VI_MAC_CMD_IDX_G(
7464                                                 be16_to_cpu(p->valid_to_idx));
7465
7466                         if (index < max_naddr)
7467                                 nfilters++;
7468                 }
7469
7470                 offset += fw_naddr;
7471                 rem -= fw_naddr;
7472         }
7473
7474         if (ret == 0)
7475                 ret = nfilters;
7476         return ret;
7477 }
7478
7479 /**
7480  *      t4_change_mac - modifies the exact-match filter for a MAC address
7481  *      @adap: the adapter
7482  *      @mbox: mailbox to use for the FW command
7483  *      @viid: the VI id
7484  *      @idx: index of existing filter for old value of MAC address, or -1
7485  *      @addr: the new MAC address value
7486  *      @persist: whether a new MAC allocation should be persistent
7487  *      @add_smt: if true also add the address to the HW SMT
7488  *
7489  *      Modifies an exact-match filter and sets it to the new MAC address.
7490  *      Note that in general it is not possible to modify the value of a given
7491  *      filter so the generic way to modify an address filter is to free the one
7492  *      being used by the old address value and allocate a new filter for the
7493  *      new address value.  @idx can be -1 if the address is a new addition.
7494  *
7495  *      Returns a negative error number or the index of the filter with the new
7496  *      MAC value.
7497  */
7498 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7499                   int idx, const u8 *addr, bool persist, bool add_smt)
7500 {
7501         int ret, mode;
7502         struct fw_vi_mac_cmd c;
7503         struct fw_vi_mac_exact *p = c.u.exact;
7504         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7505
7506         if (idx < 0)                             /* new allocation */
7507                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7508         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7509
7510         memset(&c, 0, sizeof(c));
7511         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7512                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7513                                    FW_VI_MAC_CMD_VIID_V(viid));
7514         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7515         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7516                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7517                                       FW_VI_MAC_CMD_IDX_V(idx));
7518         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7519
7520         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7521         if (ret == 0) {
7522                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7523                 if (ret >= max_mac_addr)
7524                         ret = -ENOMEM;
7525         }
7526         return ret;
7527 }
7528
7529 /**
7530  *      t4_set_addr_hash - program the MAC inexact-match hash filter
7531  *      @adap: the adapter
7532  *      @mbox: mailbox to use for the FW command
7533  *      @viid: the VI id
7534  *      @ucast: whether the hash filter should also match unicast addresses
7535  *      @vec: the value to be written to the hash filter
7536  *      @sleep_ok: call is allowed to sleep
7537  *
7538  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
7539  */
7540 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7541                      bool ucast, u64 vec, bool sleep_ok)
7542 {
7543         struct fw_vi_mac_cmd c;
7544
7545         memset(&c, 0, sizeof(c));
7546         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7547                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7548                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7549         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7550                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7551                                           FW_CMD_LEN16_V(1));
7552         c.u.hash.hashvec = cpu_to_be64(vec);
7553         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7554 }
7555
7556 /**
7557  *      t4_enable_vi_params - enable/disable a virtual interface
7558  *      @adap: the adapter
7559  *      @mbox: mailbox to use for the FW command
7560  *      @viid: the VI id
7561  *      @rx_en: 1=enable Rx, 0=disable Rx
7562  *      @tx_en: 1=enable Tx, 0=disable Tx
7563  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7564  *
7565  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7566  *      only makes sense when enabling a Virtual Interface ...
7567  */
7568 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7569                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7570 {
7571         struct fw_vi_enable_cmd c;
7572
7573         memset(&c, 0, sizeof(c));
7574         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7575                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7576                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7577         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7578                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7579                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7580                                      FW_LEN16(c));
7581         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7582 }
7583
7584 /**
7585  *      t4_enable_vi - enable/disable a virtual interface
7586  *      @adap: the adapter
7587  *      @mbox: mailbox to use for the FW command
7588  *      @viid: the VI id
7589  *      @rx_en: 1=enable Rx, 0=disable Rx
7590  *      @tx_en: 1=enable Tx, 0=disable Tx
7591  *
7592  *      Enables/disables a virtual interface.
7593  */
7594 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7595                  bool rx_en, bool tx_en)
7596 {
7597         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7598 }
7599
7600 /**
7601  *      t4_identify_port - identify a VI's port by blinking its LED
7602  *      @adap: the adapter
7603  *      @mbox: mailbox to use for the FW command
7604  *      @viid: the VI id
7605  *      @nblinks: how many times to blink LED at 2.5 Hz
7606  *
7607  *      Identifies a VI's port by blinking its LED.
7608  */
7609 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7610                      unsigned int nblinks)
7611 {
7612         struct fw_vi_enable_cmd c;
7613
7614         memset(&c, 0, sizeof(c));
7615         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7616                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7617                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7618         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7619         c.blinkdur = cpu_to_be16(nblinks);
7620         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7621 }
7622
7623 /**
7624  *      t4_iq_stop - stop an ingress queue and its FLs
7625  *      @adap: the adapter
7626  *      @mbox: mailbox to use for the FW command
7627  *      @pf: the PF owning the queues
7628  *      @vf: the VF owning the queues
7629  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7630  *      @iqid: ingress queue id
7631  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7632  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7633  *
7634  *      Stops an ingress queue and its associated FLs, if any.  This causes
7635  *      any current or future data/messages destined for these queues to be
7636  *      tossed.
7637  */
7638 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7639                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7640                unsigned int fl0id, unsigned int fl1id)
7641 {
7642         struct fw_iq_cmd c;
7643
7644         memset(&c, 0, sizeof(c));
7645         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7646                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7647                                   FW_IQ_CMD_VFN_V(vf));
7648         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7649         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7650         c.iqid = cpu_to_be16(iqid);
7651         c.fl0id = cpu_to_be16(fl0id);
7652         c.fl1id = cpu_to_be16(fl1id);
7653         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7654 }
7655
7656 /**
7657  *      t4_iq_free - free an ingress queue and its FLs
7658  *      @adap: the adapter
7659  *      @mbox: mailbox to use for the FW command
7660  *      @pf: the PF owning the queues
7661  *      @vf: the VF owning the queues
7662  *      @iqtype: the ingress queue type
7663  *      @iqid: ingress queue id
7664  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7665  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7666  *
7667  *      Frees an ingress queue and its associated FLs, if any.
7668  */
7669 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7670                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7671                unsigned int fl0id, unsigned int fl1id)
7672 {
7673         struct fw_iq_cmd c;
7674
7675         memset(&c, 0, sizeof(c));
7676         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7677                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7678                                   FW_IQ_CMD_VFN_V(vf));
7679         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7680         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7681         c.iqid = cpu_to_be16(iqid);
7682         c.fl0id = cpu_to_be16(fl0id);
7683         c.fl1id = cpu_to_be16(fl1id);
7684         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7685 }
7686
7687 /**
7688  *      t4_eth_eq_free - free an Ethernet egress queue
7689  *      @adap: the adapter
7690  *      @mbox: mailbox to use for the FW command
7691  *      @pf: the PF owning the queue
7692  *      @vf: the VF owning the queue
7693  *      @eqid: egress queue id
7694  *
7695  *      Frees an Ethernet egress queue.
7696  */
7697 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7698                    unsigned int vf, unsigned int eqid)
7699 {
7700         struct fw_eq_eth_cmd c;
7701
7702         memset(&c, 0, sizeof(c));
7703         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7704                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7705                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7706                                   FW_EQ_ETH_CMD_VFN_V(vf));
7707         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7708         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7709         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7710 }
7711
7712 /**
7713  *      t4_ctrl_eq_free - free a control egress queue
7714  *      @adap: the adapter
7715  *      @mbox: mailbox to use for the FW command
7716  *      @pf: the PF owning the queue
7717  *      @vf: the VF owning the queue
7718  *      @eqid: egress queue id
7719  *
7720  *      Frees a control egress queue.
7721  */
7722 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7723                     unsigned int vf, unsigned int eqid)
7724 {
7725         struct fw_eq_ctrl_cmd c;
7726
7727         memset(&c, 0, sizeof(c));
7728         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7729                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7730                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7731                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7732         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7733         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7734         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7735 }
7736
7737 /**
7738  *      t4_ofld_eq_free - free an offload egress queue
7739  *      @adap: the adapter
7740  *      @mbox: mailbox to use for the FW command
7741  *      @pf: the PF owning the queue
7742  *      @vf: the VF owning the queue
7743  *      @eqid: egress queue id
7744  *
7745  *      Frees a control egress queue.
7746  */
7747 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7748                     unsigned int vf, unsigned int eqid)
7749 {
7750         struct fw_eq_ofld_cmd c;
7751
7752         memset(&c, 0, sizeof(c));
7753         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7754                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7755                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7756                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7757         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7758         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7759         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7760 }
7761
7762 /**
7763  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7764  *      @adap: the adapter
7765  *      @link_down_rc: Link Down Reason Code
7766  *
7767  *      Returns a string representation of the Link Down Reason Code.
7768  */
7769 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7770 {
7771         static const char * const reason[] = {
7772                 "Link Down",
7773                 "Remote Fault",
7774                 "Auto-negotiation Failure",
7775                 "Reserved",
7776                 "Insufficient Airflow",
7777                 "Unable To Determine Reason",
7778                 "No RX Signal Detected",
7779                 "Reserved",
7780         };
7781
7782         if (link_down_rc >= ARRAY_SIZE(reason))
7783                 return "Bad Reason Code";
7784
7785         return reason[link_down_rc];
7786 }
7787
7788 /**
7789  * Return the highest speed set in the port capabilities, in Mb/s.
7790  */
7791 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
7792 {
7793         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
7794                 do { \
7795                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7796                                 return __speed; \
7797                 } while (0)
7798
7799         TEST_SPEED_RETURN(400G, 400000);
7800         TEST_SPEED_RETURN(200G, 200000);
7801         TEST_SPEED_RETURN(100G, 100000);
7802         TEST_SPEED_RETURN(50G,   50000);
7803         TEST_SPEED_RETURN(40G,   40000);
7804         TEST_SPEED_RETURN(25G,   25000);
7805         TEST_SPEED_RETURN(10G,   10000);
7806         TEST_SPEED_RETURN(1G,     1000);
7807         TEST_SPEED_RETURN(100M,    100);
7808
7809         #undef TEST_SPEED_RETURN
7810
7811         return 0;
7812 }
7813
7814 /**
7815  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
7816  *      @acaps: advertised Port Capabilities
7817  *
7818  *      Get the highest speed for the port from the advertised Port
7819  *      Capabilities.  It will be either the highest speed from the list of
7820  *      speeds or whatever user has set using ethtool.
7821  */
7822 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
7823 {
7824         #define TEST_SPEED_RETURN(__caps_speed) \
7825                 do { \
7826                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7827                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
7828                 } while (0)
7829
7830         TEST_SPEED_RETURN(400G);
7831         TEST_SPEED_RETURN(200G);
7832         TEST_SPEED_RETURN(100G);
7833         TEST_SPEED_RETURN(50G);
7834         TEST_SPEED_RETURN(40G);
7835         TEST_SPEED_RETURN(25G);
7836         TEST_SPEED_RETURN(10G);
7837         TEST_SPEED_RETURN(1G);
7838         TEST_SPEED_RETURN(100M);
7839
7840         #undef TEST_SPEED_RETURN
7841
7842         return 0;
7843 }
7844
7845 /**
7846  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
7847  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
7848  *
7849  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
7850  *      32-bit Port Capabilities value.
7851  */
7852 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
7853 {
7854         fw_port_cap32_t linkattr = 0;
7855
7856         /* Unfortunately the format of the Link Status in the old
7857          * 16-bit Port Information message isn't the same as the
7858          * 16-bit Port Capabilities bitfield used everywhere else ...
7859          */
7860         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
7861                 linkattr |= FW_PORT_CAP32_FC_RX;
7862         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
7863                 linkattr |= FW_PORT_CAP32_FC_TX;
7864         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7865                 linkattr |= FW_PORT_CAP32_SPEED_100M;
7866         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7867                 linkattr |= FW_PORT_CAP32_SPEED_1G;
7868         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7869                 linkattr |= FW_PORT_CAP32_SPEED_10G;
7870         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7871                 linkattr |= FW_PORT_CAP32_SPEED_25G;
7872         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7873                 linkattr |= FW_PORT_CAP32_SPEED_40G;
7874         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7875                 linkattr |= FW_PORT_CAP32_SPEED_100G;
7876
7877         return linkattr;
7878 }
7879
7880 /**
7881  *      t4_handle_get_port_info - process a FW reply message
7882  *      @pi: the port info
7883  *      @rpl: start of the FW message
7884  *
7885  *      Processes a GET_PORT_INFO FW reply message.
7886  */
7887 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7888 {
7889         const struct fw_port_cmd *cmd = (const void *)rpl;
7890         int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
7891         struct adapter *adapter = pi->adapter;
7892         struct link_config *lc = &pi->link_cfg;
7893         int link_ok, linkdnrc;
7894         enum fw_port_type port_type;
7895         enum fw_port_module_type mod_type;
7896         unsigned int speed, fc, fec;
7897         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
7898
7899         /* Extract the various fields from the Port Information message.
7900          */
7901         switch (action) {
7902         case FW_PORT_ACTION_GET_PORT_INFO: {
7903                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
7904
7905                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
7906                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
7907                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
7908                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
7909                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
7910                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
7911                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
7912                 linkattr = lstatus_to_fwcap(lstatus);
7913                 break;
7914         }
7915
7916         case FW_PORT_ACTION_GET_PORT_INFO32: {
7917                 u32 lstatus32;
7918
7919                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
7920                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
7921                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
7922                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
7923                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
7924                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
7925                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
7926                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
7927                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
7928                 break;
7929         }
7930
7931         default:
7932                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
7933                         be32_to_cpu(cmd->action_to_len16));
7934                 return;
7935         }
7936
7937         fec = fwcap_to_cc_fec(acaps);
7938         fc = fwcap_to_cc_pause(linkattr);
7939         speed = fwcap_to_speed(linkattr);
7940
7941         if (mod_type != pi->mod_type) {
7942                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
7943                  * various fundamental Port Capabilities which used to be
7944                  * immutable can now change radically.  We can now have
7945                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
7946                  * all change based on what Transceiver Module is inserted.
7947                  * So we need to record the Physical "Port" Capabilities on
7948                  * every Transceiver Module change.
7949                  */
7950                 lc->pcaps = pcaps;
7951
7952                 /* When a new Transceiver Module is inserted, the Firmware
7953                  * will examine its i2c EPROM to determine its type and
7954                  * general operating parameters including things like Forward
7955                  * Error Control, etc.  Various IEEE 802.3 standards dictate
7956                  * how to interpret these i2c values to determine default
7957                  * "sutomatic" settings.  We record these for future use when
7958                  * the user explicitly requests these standards-based values.
7959                  */
7960                 lc->def_acaps = acaps;
7961
7962                 /* Some versions of the early T6 Firmware "cheated" when
7963                  * handling different Transceiver Modules by changing the
7964                  * underlaying Port Type reported to the Host Drivers.  As
7965                  * such we need to capture whatever Port Type the Firmware
7966                  * sends us and record it in case it's different from what we
7967                  * were told earlier.  Unfortunately, since Firmware is
7968                  * forever, we'll need to keep this code here forever, but in
7969                  * later T6 Firmware it should just be an assignment of the
7970                  * same value already recorded.
7971                  */
7972                 pi->port_type = port_type;
7973
7974                 pi->mod_type = mod_type;
7975                 t4_os_portmod_changed(adapter, pi->port_id);
7976         }
7977
7978         if (link_ok != lc->link_ok || speed != lc->speed ||
7979             fc != lc->fc || fec != lc->fec) {   /* something changed */
7980                 if (!link_ok && lc->link_ok) {
7981                         lc->link_down_rc = linkdnrc;
7982                         dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
7983                                  pi->tx_chan, t4_link_down_rc_str(linkdnrc));
7984                 }
7985                 lc->link_ok = link_ok;
7986                 lc->speed = speed;
7987                 lc->fc = fc;
7988                 lc->fec = fec;
7989
7990                 lc->lpacaps = lpacaps;
7991                 lc->acaps = acaps & ADVERT_MASK;
7992
7993                 if (lc->acaps & FW_PORT_CAP32_ANEG) {
7994                         lc->autoneg = AUTONEG_ENABLE;
7995                 } else {
7996                         /* When Autoneg is disabled, user needs to set
7997                          * single speed.
7998                          * Similar to cxgb4_ethtool.c: set_link_ksettings
7999                          */
8000                         lc->acaps = 0;
8001                         lc->speed_caps = fwcap_to_fwspeed(acaps);
8002                         lc->autoneg = AUTONEG_DISABLE;
8003                 }
8004
8005                 t4_os_link_changed(adapter, pi->port_id, link_ok);
8006         }
8007 }
8008
8009 /**
8010  *      t4_update_port_info - retrieve and update port information if changed
8011  *      @pi: the port_info
8012  *
8013  *      We issue a Get Port Information Command to the Firmware and, if
8014  *      successful, we check to see if anything is different from what we
8015  *      last recorded and update things accordingly.
8016  */
8017 int t4_update_port_info(struct port_info *pi)
8018 {
8019         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8020         struct fw_port_cmd port_cmd;
8021         int ret;
8022
8023         memset(&port_cmd, 0, sizeof(port_cmd));
8024         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8025                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8026                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8027         port_cmd.action_to_len16 = cpu_to_be32(
8028                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8029                                      ? FW_PORT_ACTION_GET_PORT_INFO
8030                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8031                 FW_LEN16(port_cmd));
8032         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8033                          &port_cmd, sizeof(port_cmd), &port_cmd);
8034         if (ret)
8035                 return ret;
8036
8037         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8038         return 0;
8039 }
8040
8041 /**
8042  *      t4_get_link_params - retrieve basic link parameters for given port
8043  *      @pi: the port
8044  *      @link_okp: value return pointer for link up/down
8045  *      @speedp: value return pointer for speed (Mb/s)
8046  *      @mtup: value return pointer for mtu
8047  *
8048  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8049  *      and MTU for a specified port.  A negative error is returned on
8050  *      failure; 0 on success.
8051  */
8052 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8053                        unsigned int *speedp, unsigned int *mtup)
8054 {
8055         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8056         struct fw_port_cmd port_cmd;
8057         unsigned int action, link_ok, speed, mtu;
8058         fw_port_cap32_t linkattr;
8059         int ret;
8060
8061         memset(&port_cmd, 0, sizeof(port_cmd));
8062         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8063                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8064                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8065         action = (fw_caps == FW_CAPS16
8066                   ? FW_PORT_ACTION_GET_PORT_INFO
8067                   : FW_PORT_ACTION_GET_PORT_INFO32);
8068         port_cmd.action_to_len16 = cpu_to_be32(
8069                 FW_PORT_CMD_ACTION_V(action) |
8070                 FW_LEN16(port_cmd));
8071         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8072                          &port_cmd, sizeof(port_cmd), &port_cmd);
8073         if (ret)
8074                 return ret;
8075
8076         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8077                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8078
8079                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8080                 linkattr = lstatus_to_fwcap(lstatus);
8081                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8082         } else {
8083                 u32 lstatus32 =
8084                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8085
8086                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8087                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8088                 mtu = FW_PORT_CMD_MTU32_G(
8089                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8090         }
8091         speed = fwcap_to_speed(linkattr);
8092
8093         *link_okp = link_ok;
8094         *speedp = fwcap_to_speed(linkattr);
8095         *mtup = mtu;
8096
8097         return 0;
8098 }
8099
8100 /**
8101  *      t4_handle_fw_rpl - process a FW reply message
8102  *      @adap: the adapter
8103  *      @rpl: start of the FW message
8104  *
8105  *      Processes a FW message, such as link state change messages.
8106  */
8107 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8108 {
8109         u8 opcode = *(const u8 *)rpl;
8110
8111         /* This might be a port command ... this simplifies the following
8112          * conditionals ...  We can get away with pre-dereferencing
8113          * action_to_len16 because it's in the first 16 bytes and all messages
8114          * will be at least that long.
8115          */
8116         const struct fw_port_cmd *p = (const void *)rpl;
8117         unsigned int action =
8118                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8119
8120         if (opcode == FW_PORT_CMD &&
8121             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8122              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8123                 int i;
8124                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8125                 struct port_info *pi = NULL;
8126
8127                 for_each_port(adap, i) {
8128                         pi = adap2pinfo(adap, i);
8129                         if (pi->tx_chan == chan)
8130                                 break;
8131                 }
8132
8133                 t4_handle_get_port_info(pi, rpl);
8134         } else {
8135                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8136                          opcode);
8137                 return -EINVAL;
8138         }
8139         return 0;
8140 }
8141
8142 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8143 {
8144         u16 val;
8145
8146         if (pci_is_pcie(adapter->pdev)) {
8147                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8148                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8149                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8150         }
8151 }
8152
8153 /**
8154  *      init_link_config - initialize a link's SW state
8155  *      @lc: pointer to structure holding the link state
8156  *      @pcaps: link Port Capabilities
8157  *      @acaps: link current Advertised Port Capabilities
8158  *
8159  *      Initializes the SW state maintained for each link, including the link's
8160  *      capabilities and default speed/flow-control/autonegotiation settings.
8161  */
8162 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8163                              fw_port_cap32_t acaps)
8164 {
8165         lc->pcaps = pcaps;
8166         lc->def_acaps = acaps;
8167         lc->lpacaps = 0;
8168         lc->speed_caps = 0;
8169         lc->speed = 0;
8170         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8171
8172         /* For Forward Error Control, we default to whatever the Firmware
8173          * tells us the Link is currently advertising.
8174          */
8175         lc->requested_fec = FEC_AUTO;
8176         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8177
8178         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8179                 lc->acaps = lc->pcaps & ADVERT_MASK;
8180                 lc->autoneg = AUTONEG_ENABLE;
8181                 lc->requested_fc |= PAUSE_AUTONEG;
8182         } else {
8183                 lc->acaps = 0;
8184                 lc->autoneg = AUTONEG_DISABLE;
8185         }
8186 }
8187
8188 #define CIM_PF_NOACCESS 0xeeeeeeee
8189
8190 int t4_wait_dev_ready(void __iomem *regs)
8191 {
8192         u32 whoami;
8193
8194         whoami = readl(regs + PL_WHOAMI_A);
8195         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8196                 return 0;
8197
8198         msleep(500);
8199         whoami = readl(regs + PL_WHOAMI_A);
8200         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8201 }
8202
8203 struct flash_desc {
8204         u32 vendor_and_model_id;
8205         u32 size_mb;
8206 };
8207
8208 static int t4_get_flash_params(struct adapter *adap)
8209 {
8210         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8211          * to the preexisting code.  All flash parts have 64KB sectors.
8212          */
8213         static struct flash_desc supported_flash[] = {
8214                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8215         };
8216
8217         unsigned int part, manufacturer;
8218         unsigned int density, size;
8219         u32 flashid = 0;
8220         int ret;
8221
8222         /* Issue a Read ID Command to the Flash part.  We decode supported
8223          * Flash parts and their sizes from this.  There's a newer Query
8224          * Command which can retrieve detailed geometry information but many
8225          * Flash parts don't support it.
8226          */
8227
8228         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8229         if (!ret)
8230                 ret = sf1_read(adap, 3, 0, 1, &flashid);
8231         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8232         if (ret)
8233                 return ret;
8234
8235         /* Check to see if it's one of our non-standard supported Flash parts.
8236          */
8237         for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8238                 if (supported_flash[part].vendor_and_model_id == flashid) {
8239                         adap->params.sf_size = supported_flash[part].size_mb;
8240                         adap->params.sf_nsec =
8241                                 adap->params.sf_size / SF_SEC_SIZE;
8242                         goto found;
8243                 }
8244
8245         /* Decode Flash part size.  The code below looks repetative with
8246          * common encodings, but that's not guaranteed in the JEDEC
8247          * specification for the Read JADEC ID command.  The only thing that
8248          * we're guaranteed by the JADEC specification is where the
8249          * Manufacturer ID is in the returned result.  After that each
8250          * Manufacturer ~could~ encode things completely differently.
8251          * Note, all Flash parts must have 64KB sectors.
8252          */
8253         manufacturer = flashid & 0xff;
8254         switch (manufacturer) {
8255         case 0x20: { /* Micron/Numonix */
8256                 /* This Density -> Size decoding table is taken from Micron
8257                  * Data Sheets.
8258                  */
8259                 density = (flashid >> 16) & 0xff;
8260                 switch (density) {
8261                 case 0x14: /* 1MB */
8262                         size = 1 << 20;
8263                         break;
8264                 case 0x15: /* 2MB */
8265                         size = 1 << 21;
8266                         break;
8267                 case 0x16: /* 4MB */
8268                         size = 1 << 22;
8269                         break;
8270                 case 0x17: /* 8MB */
8271                         size = 1 << 23;
8272                         break;
8273                 case 0x18: /* 16MB */
8274                         size = 1 << 24;
8275                         break;
8276                 case 0x19: /* 32MB */
8277                         size = 1 << 25;
8278                         break;
8279                 case 0x20: /* 64MB */
8280                         size = 1 << 26;
8281                         break;
8282                 case 0x21: /* 128MB */
8283                         size = 1 << 27;
8284                         break;
8285                 case 0x22: /* 256MB */
8286                         size = 1 << 28;
8287                         break;
8288
8289                 default:
8290                         dev_err(adap->pdev_dev, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
8291                                 flashid, density);
8292                 return -EINVAL;
8293                 }
8294                 break;
8295         }
8296         case 0xc2: { /* Macronix */
8297                 /* This Density -> Size decoding table is taken from Macronix
8298                  * Data Sheets.
8299                  */
8300                 density = (flashid >> 16) & 0xff;
8301                 switch (density) {
8302                 case 0x17: /* 8MB */
8303                         size = 1 << 23;
8304                         break;
8305                 case 0x18: /* 16MB */
8306                         size = 1 << 24;
8307                         break;
8308                 default:
8309                         dev_err(adap->pdev_dev, "Macronix Flash Part has bad size, ID = %#x, Density code = %#x\n",
8310                                 flashid, density);
8311                 return -EINVAL;
8312                 }
8313         }
8314         case 0xef: { /* Winbond */
8315                 /* This Density -> Size decoding table is taken from Winbond
8316                  * Data Sheets.
8317                  */
8318                 density = (flashid >> 16) & 0xff;
8319                 switch (density) {
8320                 case 0x17: /* 8MB */
8321                         size = 1 << 23;
8322                         break;
8323                 case 0x18: /* 16MB */
8324                         size = 1 << 24;
8325                         break;
8326                 default:
8327                         dev_err(adap->pdev_dev, "Winbond Flash Part has bad size, ID = %#x, Density code = %#x\n",
8328                                 flashid, density);
8329                 return -EINVAL;
8330                 }
8331                 break;
8332         }
8333         default:
8334                 dev_err(adap->pdev_dev, "Unsupported Flash Part, ID = %#x\n",
8335                         flashid);
8336                 return -EINVAL;
8337         }
8338
8339         /* Store decoded Flash size and fall through into vetting code. */
8340         adap->params.sf_size = size;
8341         adap->params.sf_nsec = size / SF_SEC_SIZE;
8342
8343 found:
8344         if (adap->params.sf_size < FLASH_MIN_SIZE)
8345                 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8346                          flashid, adap->params.sf_size, FLASH_MIN_SIZE);
8347         return 0;
8348 }
8349
8350 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
8351 {
8352         u16 val;
8353         u32 pcie_cap;
8354
8355         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
8356         if (pcie_cap) {
8357                 pci_read_config_word(adapter->pdev,
8358                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
8359                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
8360                 val |= range;
8361                 pci_write_config_word(adapter->pdev,
8362                                       pcie_cap + PCI_EXP_DEVCTL2, val);
8363         }
8364 }
8365
8366 /**
8367  *      t4_prep_adapter - prepare SW and HW for operation
8368  *      @adapter: the adapter
8369  *      @reset: if true perform a HW reset
8370  *
8371  *      Initialize adapter SW state for the various HW modules, set initial
8372  *      values for some adapter tunables, take PHYs out of reset, and
8373  *      initialize the MDIO interface.
8374  */
8375 int t4_prep_adapter(struct adapter *adapter)
8376 {
8377         int ret, ver;
8378         uint16_t device_id;
8379         u32 pl_rev;
8380
8381         get_pci_mode(adapter, &adapter->params.pci);
8382         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8383
8384         ret = t4_get_flash_params(adapter);
8385         if (ret < 0) {
8386                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8387                 return ret;
8388         }
8389
8390         /* Retrieve adapter's device ID
8391          */
8392         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8393         ver = device_id >> 12;
8394         adapter->params.chip = 0;
8395         switch (ver) {
8396         case CHELSIO_T4:
8397                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8398                 adapter->params.arch.sge_fl_db = DBPRIO_F;
8399                 adapter->params.arch.mps_tcam_size =
8400                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
8401                 adapter->params.arch.mps_rplc_size = 128;
8402                 adapter->params.arch.nchan = NCHAN;
8403                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8404                 adapter->params.arch.vfcount = 128;
8405                 /* Congestion map is for 4 channels so that
8406                  * MPS can have 4 priority per port.
8407                  */
8408                 adapter->params.arch.cng_ch_bits_log = 2;
8409                 break;
8410         case CHELSIO_T5:
8411                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8412                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8413                 adapter->params.arch.mps_tcam_size =
8414                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8415                 adapter->params.arch.mps_rplc_size = 128;
8416                 adapter->params.arch.nchan = NCHAN;
8417                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8418                 adapter->params.arch.vfcount = 128;
8419                 adapter->params.arch.cng_ch_bits_log = 2;
8420                 break;
8421         case CHELSIO_T6:
8422                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8423                 adapter->params.arch.sge_fl_db = 0;
8424                 adapter->params.arch.mps_tcam_size =
8425                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8426                 adapter->params.arch.mps_rplc_size = 256;
8427                 adapter->params.arch.nchan = 2;
8428                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8429                 adapter->params.arch.vfcount = 256;
8430                 /* Congestion map will be for 2 channels so that
8431                  * MPS can have 8 priority per port.
8432                  */
8433                 adapter->params.arch.cng_ch_bits_log = 3;
8434                 break;
8435         default:
8436                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8437                         device_id);
8438                 return -EINVAL;
8439         }
8440
8441         adapter->params.cim_la_size = CIMLA_SIZE;
8442         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8443
8444         /*
8445          * Default port for debugging in case we can't reach FW.
8446          */
8447         adapter->params.nports = 1;
8448         adapter->params.portvec = 1;
8449         adapter->params.vpd.cclk = 50000;
8450
8451         /* Set pci completion timeout value to 4 seconds. */
8452         set_pcie_completion_timeout(adapter, 0xd);
8453         return 0;
8454 }
8455
8456 /**
8457  *      t4_shutdown_adapter - shut down adapter, host & wire
8458  *      @adapter: the adapter
8459  *
8460  *      Perform an emergency shutdown of the adapter and stop it from
8461  *      continuing any further communication on the ports or DMA to the
8462  *      host.  This is typically used when the adapter and/or firmware
8463  *      have crashed and we want to prevent any further accidental
8464  *      communication with the rest of the world.  This will also force
8465  *      the port Link Status to go down -- if register writes work --
8466  *      which should help our peers figure out that we're down.
8467  */
8468 int t4_shutdown_adapter(struct adapter *adapter)
8469 {
8470         int port;
8471
8472         t4_intr_disable(adapter);
8473         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
8474         for_each_port(adapter, port) {
8475                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
8476                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
8477                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
8478
8479                 t4_write_reg(adapter, a_port_cfg,
8480                              t4_read_reg(adapter, a_port_cfg)
8481                              & ~SIGNAL_DET_V(1));
8482         }
8483         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
8484
8485         return 0;
8486 }
8487
8488 /**
8489  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8490  *      @adapter: the adapter
8491  *      @qid: the Queue ID
8492  *      @qtype: the Ingress or Egress type for @qid
8493  *      @user: true if this request is for a user mode queue
8494  *      @pbar2_qoffset: BAR2 Queue Offset
8495  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8496  *
8497  *      Returns the BAR2 SGE Queue Registers information associated with the
8498  *      indicated Absolute Queue ID.  These are passed back in return value
8499  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8500  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8501  *
8502  *      This may return an error which indicates that BAR2 SGE Queue
8503  *      registers aren't available.  If an error is not returned, then the
8504  *      following values are returned:
8505  *
8506  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8507  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8508  *
8509  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8510  *      require the "Inferred Queue ID" ability may be used.  E.g. the
8511  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8512  *      then these "Inferred Queue ID" register may not be used.
8513  */
8514 int t4_bar2_sge_qregs(struct adapter *adapter,
8515                       unsigned int qid,
8516                       enum t4_bar2_qtype qtype,
8517                       int user,
8518                       u64 *pbar2_qoffset,
8519                       unsigned int *pbar2_qid)
8520 {
8521         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
8522         u64 bar2_page_offset, bar2_qoffset;
8523         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
8524
8525         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
8526         if (!user && is_t4(adapter->params.chip))
8527                 return -EINVAL;
8528
8529         /* Get our SGE Page Size parameters.
8530          */
8531         page_shift = adapter->params.sge.hps + 10;
8532         page_size = 1 << page_shift;
8533
8534         /* Get the right Queues per Page parameters for our Queue.
8535          */
8536         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
8537                      ? adapter->params.sge.eq_qpp
8538                      : adapter->params.sge.iq_qpp);
8539         qpp_mask = (1 << qpp_shift) - 1;
8540
8541         /*  Calculate the basics of the BAR2 SGE Queue register area:
8542          *  o The BAR2 page the Queue registers will be in.
8543          *  o The BAR2 Queue ID.
8544          *  o The BAR2 Queue ID Offset into the BAR2 page.
8545          */
8546         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
8547         bar2_qid = qid & qpp_mask;
8548         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
8549
8550         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
8551          * hardware will infer the Absolute Queue ID simply from the writes to
8552          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
8553          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
8554          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
8555          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
8556          * from the BAR2 Page and BAR2 Queue ID.
8557          *
8558          * One important censequence of this is that some BAR2 SGE registers
8559          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
8560          * there.  But other registers synthesize the SGE Queue ID purely
8561          * from the writes to the registers -- the Write Combined Doorbell
8562          * Buffer is a good example.  These BAR2 SGE Registers are only
8563          * available for those BAR2 SGE Register areas where the SGE Absolute
8564          * Queue ID can be inferred from simple writes.
8565          */
8566         bar2_qoffset = bar2_page_offset;
8567         bar2_qinferred = (bar2_qid_offset < page_size);
8568         if (bar2_qinferred) {
8569                 bar2_qoffset += bar2_qid_offset;
8570                 bar2_qid = 0;
8571         }
8572
8573         *pbar2_qoffset = bar2_qoffset;
8574         *pbar2_qid = bar2_qid;
8575         return 0;
8576 }
8577
8578 /**
8579  *      t4_init_devlog_params - initialize adapter->params.devlog
8580  *      @adap: the adapter
8581  *
8582  *      Initialize various fields of the adapter's Firmware Device Log
8583  *      Parameters structure.
8584  */
8585 int t4_init_devlog_params(struct adapter *adap)
8586 {
8587         struct devlog_params *dparams = &adap->params.devlog;
8588         u32 pf_dparams;
8589         unsigned int devlog_meminfo;
8590         struct fw_devlog_cmd devlog_cmd;
8591         int ret;
8592
8593         /* If we're dealing with newer firmware, the Device Log Paramerters
8594          * are stored in a designated register which allows us to access the
8595          * Device Log even if we can't talk to the firmware.
8596          */
8597         pf_dparams =
8598                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
8599         if (pf_dparams) {
8600                 unsigned int nentries, nentries128;
8601
8602                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
8603                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
8604
8605                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
8606                 nentries = (nentries128 + 1) * 128;
8607                 dparams->size = nentries * sizeof(struct fw_devlog_e);
8608
8609                 return 0;
8610         }
8611
8612         /* Otherwise, ask the firmware for it's Device Log Parameters.
8613          */
8614         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
8615         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
8616                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
8617         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
8618         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
8619                          &devlog_cmd);
8620         if (ret)
8621                 return ret;
8622
8623         devlog_meminfo =
8624                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
8625         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
8626         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
8627         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
8628
8629         return 0;
8630 }
8631
8632 /**
8633  *      t4_init_sge_params - initialize adap->params.sge
8634  *      @adapter: the adapter
8635  *
8636  *      Initialize various fields of the adapter's SGE Parameters structure.
8637  */
8638 int t4_init_sge_params(struct adapter *adapter)
8639 {
8640         struct sge_params *sge_params = &adapter->params.sge;
8641         u32 hps, qpp;
8642         unsigned int s_hps, s_qpp;
8643
8644         /* Extract the SGE Page Size for our PF.
8645          */
8646         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
8647         s_hps = (HOSTPAGESIZEPF0_S +
8648                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
8649         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
8650
8651         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
8652          */
8653         s_qpp = (QUEUESPERPAGEPF0_S +
8654                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
8655         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
8656         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8657         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
8658         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8659
8660         return 0;
8661 }
8662
8663 /**
8664  *      t4_init_tp_params - initialize adap->params.tp
8665  *      @adap: the adapter
8666  *
8667  *      Initialize various fields of the adapter's TP Parameters structure.
8668  */
8669 int t4_init_tp_params(struct adapter *adap)
8670 {
8671         int chan;
8672         u32 v;
8673
8674         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
8675         adap->params.tp.tre = TIMERRESOLUTION_G(v);
8676         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
8677
8678         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8679         for (chan = 0; chan < NCHAN; chan++)
8680                 adap->params.tp.tx_modq[chan] = chan;
8681
8682         /* Cache the adapter's Compressed Filter Mode and global Incress
8683          * Configuration.
8684          */
8685         if (t4_use_ldst(adap)) {
8686                 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
8687                                 TP_VLAN_PRI_MAP_A, 1);
8688                 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
8689                                 TP_INGRESS_CONFIG_A, 1);
8690         } else {
8691                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
8692                                  &adap->params.tp.vlan_pri_map, 1,
8693                                  TP_VLAN_PRI_MAP_A);
8694                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
8695                                  &adap->params.tp.ingress_config, 1,
8696                                  TP_INGRESS_CONFIG_A);
8697         }
8698         /* For T6, cache the adapter's compressed error vector
8699          * and passing outer header info for encapsulated packets.
8700          */
8701         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
8702                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
8703                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
8704         }
8705
8706         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
8707          * shift positions of several elements of the Compressed Filter Tuple
8708          * for this adapter which we need frequently ...
8709          */
8710         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
8711         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
8712         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
8713         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
8714                                                                PROTOCOL_F);
8715
8716         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8717          * represents the presence of an Outer VLAN instead of a VNIC ID.
8718          */
8719         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
8720                 adap->params.tp.vnic_shift = -1;
8721
8722         return 0;
8723 }
8724
8725 /**
8726  *      t4_filter_field_shift - calculate filter field shift
8727  *      @adap: the adapter
8728  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8729  *
8730  *      Return the shift position of a filter field within the Compressed
8731  *      Filter Tuple.  The filter field is specified via its selection bit
8732  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8733  */
8734 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8735 {
8736         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8737         unsigned int sel;
8738         int field_shift;
8739
8740         if ((filter_mode & filter_sel) == 0)
8741                 return -1;
8742
8743         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8744                 switch (filter_mode & sel) {
8745                 case FCOE_F:
8746                         field_shift += FT_FCOE_W;
8747                         break;
8748                 case PORT_F:
8749                         field_shift += FT_PORT_W;
8750                         break;
8751                 case VNIC_ID_F:
8752                         field_shift += FT_VNIC_ID_W;
8753                         break;
8754                 case VLAN_F:
8755                         field_shift += FT_VLAN_W;
8756                         break;
8757                 case TOS_F:
8758                         field_shift += FT_TOS_W;
8759                         break;
8760                 case PROTOCOL_F:
8761                         field_shift += FT_PROTOCOL_W;
8762                         break;
8763                 case ETHERTYPE_F:
8764                         field_shift += FT_ETHERTYPE_W;
8765                         break;
8766                 case MACMATCH_F:
8767                         field_shift += FT_MACMATCH_W;
8768                         break;
8769                 case MPSHITTYPE_F:
8770                         field_shift += FT_MPSHITTYPE_W;
8771                         break;
8772                 case FRAGMENTATION_F:
8773                         field_shift += FT_FRAGMENTATION_W;
8774                         break;
8775                 }
8776         }
8777         return field_shift;
8778 }
8779
8780 int t4_init_rss_mode(struct adapter *adap, int mbox)
8781 {
8782         int i, ret;
8783         struct fw_rss_vi_config_cmd rvc;
8784
8785         memset(&rvc, 0, sizeof(rvc));
8786
8787         for_each_port(adap, i) {
8788                 struct port_info *p = adap2pinfo(adap, i);
8789
8790                 rvc.op_to_viid =
8791                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
8792                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
8793                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
8794                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
8795                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
8796                 if (ret)
8797                         return ret;
8798                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
8799         }
8800         return 0;
8801 }
8802
8803 /**
8804  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
8805  *      @pi: the port_info
8806  *      @mbox: mailbox to use for the FW command
8807  *      @port: physical port associated with the VI
8808  *      @pf: the PF owning the VI
8809  *      @vf: the VF owning the VI
8810  *      @mac: the MAC address of the VI
8811  *
8812  *      Allocates a virtual interface for the given physical port.  If @mac is
8813  *      not %NULL it contains the MAC address of the VI as assigned by FW.
8814  *      @mac should be large enough to hold an Ethernet address.
8815  *      Returns < 0 on error.
8816  */
8817 int t4_init_portinfo(struct port_info *pi, int mbox,
8818                      int port, int pf, int vf, u8 mac[])
8819 {
8820         struct adapter *adapter = pi->adapter;
8821         unsigned int fw_caps = adapter->params.fw_caps_support;
8822         struct fw_port_cmd cmd;
8823         unsigned int rss_size;
8824         enum fw_port_type port_type;
8825         int mdio_addr;
8826         fw_port_cap32_t pcaps, acaps;
8827         int ret;
8828
8829         /* If we haven't yet determined whether we're talking to Firmware
8830          * which knows the new 32-bit Port Capabilities, it's time to find
8831          * out now.  This will also tell new Firmware to send us Port Status
8832          * Updates using the new 32-bit Port Capabilities version of the
8833          * Port Information message.
8834          */
8835         if (fw_caps == FW_CAPS_UNKNOWN) {
8836                 u32 param, val;
8837
8838                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
8839                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
8840                 val = 1;
8841                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
8842                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
8843                 adapter->params.fw_caps_support = fw_caps;
8844         }
8845
8846         memset(&cmd, 0, sizeof(cmd));
8847         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8848                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
8849                                        FW_PORT_CMD_PORTID_V(port));
8850         cmd.action_to_len16 = cpu_to_be32(
8851                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8852                                      ? FW_PORT_ACTION_GET_PORT_INFO
8853                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8854                 FW_LEN16(cmd));
8855         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
8856         if (ret)
8857                 return ret;
8858
8859         /* Extract the various fields from the Port Information message.
8860          */
8861         if (fw_caps == FW_CAPS16) {
8862                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
8863
8864                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8865                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
8866                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
8867                              : -1);
8868                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
8869                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
8870         } else {
8871                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
8872
8873                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8874                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
8875                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
8876                              : -1);
8877                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
8878                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
8879         }
8880
8881         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
8882         if (ret < 0)
8883                 return ret;
8884
8885         pi->viid = ret;
8886         pi->tx_chan = port;
8887         pi->lport = port;
8888         pi->rss_size = rss_size;
8889
8890         pi->port_type = port_type;
8891         pi->mdio_addr = mdio_addr;
8892         pi->mod_type = FW_PORT_MOD_TYPE_NA;
8893
8894         init_link_config(&pi->link_cfg, pcaps, acaps);
8895         return 0;
8896 }
8897
8898 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
8899 {
8900         u8 addr[6];
8901         int ret, i, j = 0;
8902
8903         for_each_port(adap, i) {
8904                 struct port_info *pi = adap2pinfo(adap, i);
8905
8906                 while ((adap->params.portvec & (1 << j)) == 0)
8907                         j++;
8908
8909                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
8910                 if (ret)
8911                         return ret;
8912
8913                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
8914                 j++;
8915         }
8916         return 0;
8917 }
8918
8919 /**
8920  *      t4_read_cimq_cfg - read CIM queue configuration
8921  *      @adap: the adapter
8922  *      @base: holds the queue base addresses in bytes
8923  *      @size: holds the queue sizes in bytes
8924  *      @thres: holds the queue full thresholds in bytes
8925  *
8926  *      Returns the current configuration of the CIM queues, starting with
8927  *      the IBQs, then the OBQs.
8928  */
8929 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8930 {
8931         unsigned int i, v;
8932         int cim_num_obq = is_t4(adap->params.chip) ?
8933                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8934
8935         for (i = 0; i < CIM_NUM_IBQ; i++) {
8936                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
8937                              QUENUMSELECT_V(i));
8938                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8939                 /* value is in 256-byte units */
8940                 *base++ = CIMQBASE_G(v) * 256;
8941                 *size++ = CIMQSIZE_G(v) * 256;
8942                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
8943         }
8944         for (i = 0; i < cim_num_obq; i++) {
8945                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8946                              QUENUMSELECT_V(i));
8947                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8948                 /* value is in 256-byte units */
8949                 *base++ = CIMQBASE_G(v) * 256;
8950                 *size++ = CIMQSIZE_G(v) * 256;
8951         }
8952 }
8953
8954 /**
8955  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
8956  *      @adap: the adapter
8957  *      @qid: the queue index
8958  *      @data: where to store the queue contents
8959  *      @n: capacity of @data in 32-bit words
8960  *
8961  *      Reads the contents of the selected CIM queue starting at address 0 up
8962  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8963  *      error and the number of 32-bit words actually read on success.
8964  */
8965 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8966 {
8967         int i, err, attempts;
8968         unsigned int addr;
8969         const unsigned int nwords = CIM_IBQ_SIZE * 4;
8970
8971         if (qid > 5 || (n & 3))
8972                 return -EINVAL;
8973
8974         addr = qid * nwords;
8975         if (n > nwords)
8976                 n = nwords;
8977
8978         /* It might take 3-10ms before the IBQ debug read access is allowed.
8979          * Wait for 1 Sec with a delay of 1 usec.
8980          */
8981         attempts = 1000000;
8982
8983         for (i = 0; i < n; i++, addr++) {
8984                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
8985                              IBQDBGEN_F);
8986                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
8987                                       attempts, 1);
8988                 if (err)
8989                         return err;
8990                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
8991         }
8992         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
8993         return i;
8994 }
8995
8996 /**
8997  *      t4_read_cim_obq - read the contents of a CIM outbound queue
8998  *      @adap: the adapter
8999  *      @qid: the queue index
9000  *      @data: where to store the queue contents
9001  *      @n: capacity of @data in 32-bit words
9002  *
9003  *      Reads the contents of the selected CIM queue starting at address 0 up
9004  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9005  *      error and the number of 32-bit words actually read on success.
9006  */
9007 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9008 {
9009         int i, err;
9010         unsigned int addr, v, nwords;
9011         int cim_num_obq = is_t4(adap->params.chip) ?
9012                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9013
9014         if ((qid > (cim_num_obq - 1)) || (n & 3))
9015                 return -EINVAL;
9016
9017         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9018                      QUENUMSELECT_V(qid));
9019         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9020
9021         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
9022         nwords = CIMQSIZE_G(v) * 64;  /* same */
9023         if (n > nwords)
9024                 n = nwords;
9025
9026         for (i = 0; i < n; i++, addr++) {
9027                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9028                              OBQDBGEN_F);
9029                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9030                                       2, 1);
9031                 if (err)
9032                         return err;
9033                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9034         }
9035         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9036         return i;
9037 }
9038
9039 /**
9040  *      t4_cim_read - read a block from CIM internal address space
9041  *      @adap: the adapter
9042  *      @addr: the start address within the CIM address space
9043  *      @n: number of words to read
9044  *      @valp: where to store the result
9045  *
9046  *      Reads a block of 4-byte words from the CIM intenal address space.
9047  */
9048 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9049                 unsigned int *valp)
9050 {
9051         int ret = 0;
9052
9053         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9054                 return -EBUSY;
9055
9056         for ( ; !ret && n--; addr += 4) {
9057                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9058                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9059                                       0, 5, 2);
9060                 if (!ret)
9061                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9062         }
9063         return ret;
9064 }
9065
9066 /**
9067  *      t4_cim_write - write a block into CIM internal address space
9068  *      @adap: the adapter
9069  *      @addr: the start address within the CIM address space
9070  *      @n: number of words to write
9071  *      @valp: set of values to write
9072  *
9073  *      Writes a block of 4-byte words into the CIM intenal address space.
9074  */
9075 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9076                  const unsigned int *valp)
9077 {
9078         int ret = 0;
9079
9080         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9081                 return -EBUSY;
9082
9083         for ( ; !ret && n--; addr += 4) {
9084                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9085                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9086                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9087                                       0, 5, 2);
9088         }
9089         return ret;
9090 }
9091
9092 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9093                          unsigned int val)
9094 {
9095         return t4_cim_write(adap, addr, 1, &val);
9096 }
9097
9098 /**
9099  *      t4_cim_read_la - read CIM LA capture buffer
9100  *      @adap: the adapter
9101  *      @la_buf: where to store the LA data
9102  *      @wrptr: the HW write pointer within the capture buffer
9103  *
9104  *      Reads the contents of the CIM LA buffer with the most recent entry at
9105  *      the end of the returned data and with the entry at @wrptr first.
9106  *      We try to leave the LA in the running state we find it in.
9107  */
9108 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9109 {
9110         int i, ret;
9111         unsigned int cfg, val, idx;
9112
9113         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9114         if (ret)
9115                 return ret;
9116
9117         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9118                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9119                 if (ret)
9120                         return ret;
9121         }
9122
9123         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9124         if (ret)
9125                 goto restart;
9126
9127         idx = UPDBGLAWRPTR_G(val);
9128         if (wrptr)
9129                 *wrptr = idx;
9130
9131         for (i = 0; i < adap->params.cim_la_size; i++) {
9132                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9133                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9134                 if (ret)
9135                         break;
9136                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9137                 if (ret)
9138                         break;
9139                 if (val & UPDBGLARDEN_F) {
9140                         ret = -ETIMEDOUT;
9141                         break;
9142                 }
9143                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9144                 if (ret)
9145                         break;
9146
9147                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9148                  * identify the 32-bit portion of the full 312-bit data
9149                  */
9150                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9151                         idx = (idx & 0xff0) + 0x10;
9152                 else
9153                         idx++;
9154                 /* address can't exceed 0xfff */
9155                 idx &= UPDBGLARDPTR_M;
9156         }
9157 restart:
9158         if (cfg & UPDBGLAEN_F) {
9159                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9160                                       cfg & ~UPDBGLARDEN_F);
9161                 if (!ret)
9162                         ret = r;
9163         }
9164         return ret;
9165 }
9166
9167 /**
9168  *      t4_tp_read_la - read TP LA capture buffer
9169  *      @adap: the adapter
9170  *      @la_buf: where to store the LA data
9171  *      @wrptr: the HW write pointer within the capture buffer
9172  *
9173  *      Reads the contents of the TP LA buffer with the most recent entry at
9174  *      the end of the returned data and with the entry at @wrptr first.
9175  *      We leave the LA in the running state we find it in.
9176  */
9177 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9178 {
9179         bool last_incomplete;
9180         unsigned int i, cfg, val, idx;
9181
9182         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9183         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
9184                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9185                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9186
9187         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9188         idx = DBGLAWPTR_G(val);
9189         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9190         if (last_incomplete)
9191                 idx = (idx + 1) & DBGLARPTR_M;
9192         if (wrptr)
9193                 *wrptr = idx;
9194
9195         val &= 0xffff;
9196         val &= ~DBGLARPTR_V(DBGLARPTR_M);
9197         val |= adap->params.tp.la_mask;
9198
9199         for (i = 0; i < TPLA_SIZE; i++) {
9200                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9201                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9202                 idx = (idx + 1) & DBGLARPTR_M;
9203         }
9204
9205         /* Wipe out last entry if it isn't valid */
9206         if (last_incomplete)
9207                 la_buf[TPLA_SIZE - 1] = ~0ULL;
9208
9209         if (cfg & DBGLAENABLE_F)                    /* restore running state */
9210                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9211                              cfg | adap->params.tp.la_mask);
9212 }
9213
9214 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9215  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
9216  * state for more than the Warning Threshold then we'll issue a warning about
9217  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
9218  * appears to be hung every Warning Repeat second till the situation clears.
9219  * If the situation clears, we'll note that as well.
9220  */
9221 #define SGE_IDMA_WARN_THRESH 1
9222 #define SGE_IDMA_WARN_REPEAT 300
9223
9224 /**
9225  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9226  *      @adapter: the adapter
9227  *      @idma: the adapter IDMA Monitor state
9228  *
9229  *      Initialize the state of an SGE Ingress DMA Monitor.
9230  */
9231 void t4_idma_monitor_init(struct adapter *adapter,
9232                           struct sge_idma_monitor_state *idma)
9233 {
9234         /* Initialize the state variables for detecting an SGE Ingress DMA
9235          * hang.  The SGE has internal counters which count up on each clock
9236          * tick whenever the SGE finds its Ingress DMA State Engines in the
9237          * same state they were on the previous clock tick.  The clock used is
9238          * the Core Clock so we have a limit on the maximum "time" they can
9239          * record; typically a very small number of seconds.  For instance,
9240          * with a 600MHz Core Clock, we can only count up to a bit more than
9241          * 7s.  So we'll synthesize a larger counter in order to not run the
9242          * risk of having the "timers" overflow and give us the flexibility to
9243          * maintain a Hung SGE State Machine of our own which operates across
9244          * a longer time frame.
9245          */
9246         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9247         idma->idma_stalled[0] = 0;
9248         idma->idma_stalled[1] = 0;
9249 }
9250
9251 /**
9252  *      t4_idma_monitor - monitor SGE Ingress DMA state
9253  *      @adapter: the adapter
9254  *      @idma: the adapter IDMA Monitor state
9255  *      @hz: number of ticks/second
9256  *      @ticks: number of ticks since the last IDMA Monitor call
9257  */
9258 void t4_idma_monitor(struct adapter *adapter,
9259                      struct sge_idma_monitor_state *idma,
9260                      int hz, int ticks)
9261 {
9262         int i, idma_same_state_cnt[2];
9263
9264          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
9265           * are counters inside the SGE which count up on each clock when the
9266           * SGE finds its Ingress DMA State Engines in the same states they
9267           * were in the previous clock.  The counters will peg out at
9268           * 0xffffffff without wrapping around so once they pass the 1s
9269           * threshold they'll stay above that till the IDMA state changes.
9270           */
9271         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9272         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9273         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9274
9275         for (i = 0; i < 2; i++) {
9276                 u32 debug0, debug11;
9277
9278                 /* If the Ingress DMA Same State Counter ("timer") is less
9279                  * than 1s, then we can reset our synthesized Stall Timer and
9280                  * continue.  If we have previously emitted warnings about a
9281                  * potential stalled Ingress Queue, issue a note indicating
9282                  * that the Ingress Queue has resumed forward progress.
9283                  */
9284                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9285                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9286                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9287                                          "resumed after %d seconds\n",
9288                                          i, idma->idma_qid[i],
9289                                          idma->idma_stalled[i] / hz);
9290                         idma->idma_stalled[i] = 0;
9291                         continue;
9292                 }
9293
9294                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9295                  * domain.  The first time we get here it'll be because we
9296                  * passed the 1s Threshold; each additional time it'll be
9297                  * because the RX Timer Callback is being fired on its regular
9298                  * schedule.
9299                  *
9300                  * If the stall is below our Potential Hung Ingress Queue
9301                  * Warning Threshold, continue.
9302                  */
9303                 if (idma->idma_stalled[i] == 0) {
9304                         idma->idma_stalled[i] = hz;
9305                         idma->idma_warn[i] = 0;
9306                 } else {
9307                         idma->idma_stalled[i] += ticks;
9308                         idma->idma_warn[i] -= ticks;
9309                 }
9310
9311                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9312                         continue;
9313
9314                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9315                  */
9316                 if (idma->idma_warn[i] > 0)
9317                         continue;
9318                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9319
9320                 /* Read and save the SGE IDMA State and Queue ID information.
9321                  * We do this every time in case it changes across time ...
9322                  * can't be too careful ...
9323                  */
9324                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9325                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9326                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9327
9328                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9329                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9330                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9331
9332                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9333                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9334                          i, idma->idma_qid[i], idma->idma_state[i],
9335                          idma->idma_stalled[i] / hz,
9336                          debug0, debug11);
9337                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9338         }
9339 }
9340
9341 /**
9342  *      t4_load_cfg - download config file
9343  *      @adap: the adapter
9344  *      @cfg_data: the cfg text file to write
9345  *      @size: text file size
9346  *
9347  *      Write the supplied config text file to the card's serial flash.
9348  */
9349 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9350 {
9351         int ret, i, n, cfg_addr;
9352         unsigned int addr;
9353         unsigned int flash_cfg_start_sec;
9354         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9355
9356         cfg_addr = t4_flash_cfg_addr(adap);
9357         if (cfg_addr < 0)
9358                 return cfg_addr;
9359
9360         addr = cfg_addr;
9361         flash_cfg_start_sec = addr / SF_SEC_SIZE;
9362
9363         if (size > FLASH_CFG_MAX_SIZE) {
9364                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9365                         FLASH_CFG_MAX_SIZE);
9366                 return -EFBIG;
9367         }
9368
9369         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
9370                          sf_sec_size);
9371         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9372                                      flash_cfg_start_sec + i - 1);
9373         /* If size == 0 then we're simply erasing the FLASH sectors associated
9374          * with the on-adapter Firmware Configuration File.
9375          */
9376         if (ret || size == 0)
9377                 goto out;
9378
9379         /* this will write to the flash up to SF_PAGE_SIZE at a time */
9380         for (i = 0; i < size; i += SF_PAGE_SIZE) {
9381                 if ((size - i) <  SF_PAGE_SIZE)
9382                         n = size - i;
9383                 else
9384                         n = SF_PAGE_SIZE;
9385                 ret = t4_write_flash(adap, addr, n, cfg_data);
9386                 if (ret)
9387                         goto out;
9388
9389                 addr += SF_PAGE_SIZE;
9390                 cfg_data += SF_PAGE_SIZE;
9391         }
9392
9393 out:
9394         if (ret)
9395                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9396                         (size == 0 ? "clear" : "download"), ret);
9397         return ret;
9398 }
9399
9400 /**
9401  *      t4_set_vf_mac - Set MAC address for the specified VF
9402  *      @adapter: The adapter
9403  *      @vf: one of the VFs instantiated by the specified PF
9404  *      @naddr: the number of MAC addresses
9405  *      @addr: the MAC address(es) to be set to the specified VF
9406  */
9407 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9408                       unsigned int naddr, u8 *addr)
9409 {
9410         struct fw_acl_mac_cmd cmd;
9411
9412         memset(&cmd, 0, sizeof(cmd));
9413         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9414                                     FW_CMD_REQUEST_F |
9415                                     FW_CMD_WRITE_F |
9416                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9417                                     FW_ACL_MAC_CMD_VFN_V(vf));
9418
9419         /* Note: Do not enable the ACL */
9420         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9421         cmd.nmac = naddr;
9422
9423         switch (adapter->pf) {
9424         case 3:
9425                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9426                 break;
9427         case 2:
9428                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9429                 break;
9430         case 1:
9431                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9432                 break;
9433         case 0:
9434                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9435                 break;
9436         }
9437
9438         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9439 }
9440
9441 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9442                     int rateunit, int ratemode, int channel, int class,
9443                     int minrate, int maxrate, int weight, int pktsize)
9444 {
9445         struct fw_sched_cmd cmd;
9446
9447         memset(&cmd, 0, sizeof(cmd));
9448         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
9449                                       FW_CMD_REQUEST_F |
9450                                       FW_CMD_WRITE_F);
9451         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9452
9453         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9454         cmd.u.params.type = type;
9455         cmd.u.params.level = level;
9456         cmd.u.params.mode = mode;
9457         cmd.u.params.ch = channel;
9458         cmd.u.params.cl = class;
9459         cmd.u.params.unit = rateunit;
9460         cmd.u.params.rate = ratemode;
9461         cmd.u.params.min = cpu_to_be32(minrate);
9462         cmd.u.params.max = cpu_to_be32(maxrate);
9463         cmd.u.params.weight = cpu_to_be16(weight);
9464         cmd.u.params.pktsize = cpu_to_be16(pktsize);
9465
9466         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
9467                                NULL, 1);
9468 }