2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
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10 * OpenIB.org BSD license below:
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20 * - Redistributions in binary form must reproduce the above
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23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F) {
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 adap->flags &= ~CXGB4_FW_OK;
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
211 for ( ; nflit; nflit--, mbox_addr += 8)
212 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
216 * Handle a FW assertion reported in a mailbox.
218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
220 struct fw_debug_cmd asrt;
222 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
223 dev_alert(adap->pdev_dev,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
226 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
237 static void t4_record_mbox(struct adapter *adapter,
238 const __be64 *cmd, unsigned int size,
239 int access, int execute)
241 struct mbox_cmd_log *log = adapter->mbox_log;
242 struct mbox_cmd *entry;
245 entry = mbox_cmd_log_entry(log, log->cursor++);
246 if (log->cursor == log->size)
249 for (i = 0; i < size / 8; i++)
250 entry->cmd[i] = be64_to_cpu(cmd[i]);
251 while (i < MBOX_LEN / 8)
253 entry->timestamp = jiffies;
254 entry->seqno = log->seqno++;
255 entry->access = access;
256 entry->execute = execute;
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
283 int size, void *rpl, bool sleep_ok, int timeout)
285 static const int delay[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
289 struct mbox_list entry;
294 int i, ms, delay_idx, ret;
295 const __be64 *p = cmd;
296 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
297 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
298 __be64 cmd_rpl[MBOX_LEN / 8];
301 if ((size & 15) || size > MBOX_LEN)
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
308 if (adap->pdev->error_state != pci_channel_io_normal)
311 /* If we have a negative timeout, that implies that we can't sleep. */
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
322 spin_lock_bh(&adap->mbox_lock);
323 list_add_tail(&entry.list, &adap->mlist.list);
324 spin_unlock_bh(&adap->mbox_lock);
329 for (i = 0; ; i += ms) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rarely
333 * contend on access to the mailbox ...
335 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
336 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
337 spin_lock_bh(&adap->mbox_lock);
338 list_del(&entry.list);
339 spin_unlock_bh(&adap->mbox_lock);
340 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
341 t4_record_mbox(adap, cmd, size, access, ret);
345 /* If we're at the head, break out and start the mailbox
348 if (list_first_entry(&adap->mlist.list, struct mbox_list,
352 /* Delay for a bit before checking again ... */
354 ms = delay[delay_idx]; /* last element may repeat */
355 if (delay_idx < ARRAY_SIZE(delay) - 1)
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
368 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
369 if (v != MBOX_OWNER_DRV) {
370 spin_lock_bh(&adap->mbox_lock);
371 list_del(&entry.list);
372 spin_unlock_bh(&adap->mbox_lock);
373 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
374 t4_record_mbox(adap, cmd, size, access, ret);
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap, cmd, size, access, 0);
380 for (i = 0; i < size; i += 8)
381 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
383 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
384 t4_read_reg(adap, ctl_reg); /* flush write */
390 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
394 ms = delay[delay_idx]; /* last element may repeat */
395 if (delay_idx < ARRAY_SIZE(delay) - 1)
401 v = t4_read_reg(adap, ctl_reg);
402 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
403 if (!(v & MBMSGVALID_F)) {
404 t4_write_reg(adap, ctl_reg, 0);
408 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
409 res = be64_to_cpu(cmd_rpl[0]);
411 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
412 fw_asrt(adap, data_reg);
413 res = FW_CMD_RETVAL_V(EIO);
415 memcpy(rpl, cmd_rpl, size);
418 t4_write_reg(adap, ctl_reg, 0);
421 t4_record_mbox(adap, cmd_rpl,
422 MBOX_LEN, access, execute);
423 spin_lock_bh(&adap->mbox_lock);
424 list_del(&entry.list);
425 spin_unlock_bh(&adap->mbox_lock);
426 return -FW_CMD_RETVAL_G((int)res);
430 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
431 t4_record_mbox(adap, cmd, size, access, ret);
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
433 *(const u8 *)cmd, mbox);
434 t4_report_fw_error(adap);
435 spin_lock_bh(&adap->mbox_lock);
436 list_del(&entry.list);
437 spin_unlock_bh(&adap->mbox_lock);
442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
443 void *rpl, bool sleep_ok)
445 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
449 static int t4_edc_err_read(struct adapter *adap, int idx)
451 u32 edc_ecc_err_addr_reg;
454 if (is_t4(adap->params.chip)) {
455 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
458 if (idx != 0 && idx != 1) {
459 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
463 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
464 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx, edc_ecc_err_addr_reg,
469 t4_read_reg(adap, edc_ecc_err_addr_reg));
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 (unsigned long long)t4_read_reg64(adap, rdata_reg),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
480 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
481 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
495 * Get the configured memory window's relative offset, base, and size.
497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
498 u32 *mem_base, u32 *mem_aperture)
500 u32 edc_size, mc_size, mem_reg;
502 /* Offset into the region of memory which is being accessed
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
509 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
510 if (mtype == MEM_HMA) {
511 *mem_off = 2 * (edc_size * 1024 * 1024);
512 } else if (mtype != MEM_MC1) {
513 *mem_off = (mtype * (edc_size * 1024 * 1024));
515 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
516 MA_EXT_MEMORY0_BAR_A));
517 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
528 mem_reg = t4_read_reg(adap,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg == 0xffffffff)
535 *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
536 *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
537 if (is_t4(adap->params.chip))
538 *mem_base -= adap->t4_bar0;
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
549 * Move memory window to specified address.
551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
564 * t4_memory_rw_residual - Read/Write residual data.
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
583 if (dir == T4_MEMORY_READ) {
584 last.word = le32_to_cpu((__force __le32)
585 t4_read_reg(adap, addr));
586 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
587 bp[i] = last.byte[i];
590 for (i = off; i < 4; i++)
592 t4_write_reg(adap, addr,
593 (__force u32)cpu_to_le32(last.word));
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boundaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
615 u32 len, void *hbuf, int dir)
617 u32 pos, offset, resid, memoffset;
618 u32 win_pf, mem_aperture, mem_base;
622 /* Argument sanity checks ...
624 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
636 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr = addr + memoffset;
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
649 pos = addr & ~(mem_aperture - 1);
652 /* Set up initial PCI-E Memory Window to cover the start of our
655 t4_memory_update_win(adap, win, pos | win_pf);
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
660 * A note on Endianness issues:
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
670 * Then a read of the adapter memory via the PCI-E Memory Window
675 * [ b3 | b2 | b1 | b0 ]
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
680 * ( ..., b0, b1, b2, b3, ... )
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
685 * ( ..., b3, b2, b1, b0, ... )
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
692 if (dir == T4_MEMORY_READ)
693 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
696 t4_write_reg(adap, mem_base + offset,
697 (__force u32)cpu_to_le32(*buf++));
698 offset += sizeof(__be32);
699 len -= sizeof(__be32);
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
707 if (offset == mem_aperture) {
710 t4_memory_update_win(adap, win, pos | win_pf);
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
720 t4_memory_rw_residual(adap, resid, mem_base + offset,
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
733 u32 val, ldst_addrspace;
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
738 struct fw_ldst_cmd ldst_cmd;
741 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
742 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
743 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
747 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
748 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd.u.pcie.ctrl_to_fn =
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
751 ldst_cmd.u.pcie.r = reg;
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
759 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
764 t4_hw_pci_read_cfg4(adap, reg, &val);
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
777 if (is_t4(adap->params.chip)) {
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
789 bar0 = t4_read_pcie_cfg4(adap, pci_base);
791 adap->t4_bar0 = bar0;
793 ret = bar0 + memwin_base;
795 /* For T5, only relative offset inside the PCIe BAR is passed */
801 /* Get the default utility window (win0) used by everyone */
802 u32 t4_get_util_window(struct adapter *adap)
804 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
805 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
816 memwin_base | BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
826 * Returns the size of the chip's BAR0 register space.
828 unsigned int t4_get_regs_len(struct adapter *adapter)
830 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
832 switch (chip_version) {
834 return T4_REGMAP_SIZE;
838 return T5_REGMAP_SIZE;
841 dev_err(adapter->pdev_dev,
842 "Unsupported chip version %d\n", chip_version);
847 * t4_get_regs - read chip registers into provided buffer
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
858 static const unsigned int t4_reg_ranges[] = {
1317 static const unsigned int t5_reg_ranges[] = {
2081 static const unsigned int t6_reg_ranges[] = {
2639 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2640 const unsigned int *reg_ranges;
2641 int reg_ranges_size, range;
2642 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2644 /* Select the right set of register ranges to dump depending on the
2645 * adapter chip type.
2647 switch (chip_version) {
2649 reg_ranges = t4_reg_ranges;
2650 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2654 reg_ranges = t5_reg_ranges;
2655 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2659 reg_ranges = t6_reg_ranges;
2660 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2664 dev_err(adap->pdev_dev,
2665 "Unsupported chip version %d\n", chip_version);
2669 /* Clear the register buffer and insert the appropriate register
2670 * values selected by the above register ranges.
2672 memset(buf, 0, buf_size);
2673 for (range = 0; range < reg_ranges_size; range += 2) {
2674 unsigned int reg = reg_ranges[range];
2675 unsigned int last_reg = reg_ranges[range + 1];
2676 u32 *bufp = (u32 *)((char *)buf + reg);
2678 /* Iterate across the register range filling in the register
2679 * buffer but don't write past the end of the register buffer.
2681 while (reg <= last_reg && bufp < buf_end) {
2682 *bufp++ = t4_read_reg(adap, reg);
2688 #define EEPROM_STAT_ADDR 0x7bfc
2689 #define VPD_BASE 0x400
2690 #define VPD_BASE_OLD 0
2691 #define VPD_LEN 1024
2692 #define CHELSIO_VPD_UNIQUE_ID 0x82
2695 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2696 * @phys_addr: the physical EEPROM address
2697 * @fn: the PCI function number
2698 * @sz: size of function-specific area
2700 * Translate a physical EEPROM address to virtual. The first 1K is
2701 * accessed through virtual addresses starting at 31K, the rest is
2702 * accessed through virtual addresses starting at 0.
2704 * The mapping is as follows:
2705 * [0..1K) -> [31K..32K)
2706 * [1K..1K+A) -> [31K-A..31K)
2707 * [1K+A..ES) -> [0..ES-A-1K)
2709 * where A = @fn * @sz, and ES = EEPROM size.
2711 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2714 if (phys_addr < 1024)
2715 return phys_addr + (31 << 10);
2716 if (phys_addr < 1024 + fn)
2717 return 31744 - fn + phys_addr - 1024;
2718 if (phys_addr < EEPROMSIZE)
2719 return phys_addr - 1024 - fn;
2724 * t4_seeprom_wp - enable/disable EEPROM write protection
2725 * @adapter: the adapter
2726 * @enable: whether to enable or disable write protection
2728 * Enables or disables write protection on the serial EEPROM.
2730 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2732 unsigned int v = enable ? 0xc : 0;
2733 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2734 return ret < 0 ? ret : 0;
2738 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2739 * @adapter: adapter to read
2740 * @p: where to store the parameters
2742 * Reads card parameters stored in VPD EEPROM.
2744 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2746 int i, ret = 0, addr;
2749 unsigned int vpdr_len, kw_offset, id_len;
2751 vpd = vmalloc(VPD_LEN);
2755 /* Card information normally starts at VPD_BASE but early cards had
2758 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2762 /* The VPD shall have a unique identifier specified by the PCI SIG.
2763 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2764 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2765 * is expected to automatically put this entry at the
2766 * beginning of the VPD.
2768 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2770 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2774 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2775 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2780 id_len = pci_vpd_lrdt_size(vpd);
2781 if (id_len > ID_LEN)
2784 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2786 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2791 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2792 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2793 if (vpdr_len + kw_offset > VPD_LEN) {
2794 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2799 #define FIND_VPD_KW(var, name) do { \
2800 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2802 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2806 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2809 FIND_VPD_KW(i, "RV");
2810 for (csum = 0; i >= 0; i--)
2814 dev_err(adapter->pdev_dev,
2815 "corrupted VPD EEPROM, actual csum %u\n", csum);
2820 FIND_VPD_KW(ec, "EC");
2821 FIND_VPD_KW(sn, "SN");
2822 FIND_VPD_KW(pn, "PN");
2823 FIND_VPD_KW(na, "NA");
2826 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2828 memcpy(p->ec, vpd + ec, EC_LEN);
2830 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2831 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2833 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2834 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2836 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2837 strim((char *)p->na);
2841 return ret < 0 ? ret : 0;
2845 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2846 * @adapter: adapter to read
2847 * @p: where to store the parameters
2849 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2850 * Clock. This can only be called after a connection to the firmware
2853 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2855 u32 cclk_param, cclk_val;
2858 /* Grab the raw VPD parameters.
2860 ret = t4_get_raw_vpd_params(adapter, p);
2864 /* Ask firmware for the Core Clock since it knows how to translate the
2865 * Reference Clock ('V2') VPD field into a Core Clock value ...
2867 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2868 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2869 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2870 1, &cclk_param, &cclk_val);
2880 * t4_get_pfres - retrieve VF resource limits
2881 * @adapter: the adapter
2883 * Retrieves configured resource limits and capabilities for a physical
2884 * function. The results are stored in @adapter->pfres.
2886 int t4_get_pfres(struct adapter *adapter)
2888 struct pf_resources *pfres = &adapter->params.pfres;
2889 struct fw_pfvf_cmd cmd, rpl;
2893 /* Execute PFVF Read command to get VF resource limits; bail out early
2894 * with error on command failure.
2896 memset(&cmd, 0, sizeof(cmd));
2897 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2900 FW_PFVF_CMD_PFN_V(adapter->pf) |
2901 FW_PFVF_CMD_VFN_V(0));
2902 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2903 v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2904 if (v != FW_SUCCESS)
2907 /* Extract PF resource limits and return success.
2909 word = be32_to_cpu(rpl.niqflint_niq);
2910 pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2911 pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2913 word = be32_to_cpu(rpl.type_to_neq);
2914 pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2915 pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2917 word = be32_to_cpu(rpl.tc_to_nexactf);
2918 pfres->tc = FW_PFVF_CMD_TC_G(word);
2919 pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2920 pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2922 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2923 pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2924 pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2925 pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2930 /* serial flash and firmware constants */
2932 SF_ATTEMPTS = 10, /* max retries for SF operations */
2934 /* flash command opcodes */
2935 SF_PROG_PAGE = 2, /* program page */
2936 SF_WR_DISABLE = 4, /* disable writes */
2937 SF_RD_STATUS = 5, /* read status register */
2938 SF_WR_ENABLE = 6, /* enable writes */
2939 SF_RD_DATA_FAST = 0xb, /* read flash */
2940 SF_RD_ID = 0x9f, /* read ID */
2941 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2945 * sf1_read - read data from the serial flash
2946 * @adapter: the adapter
2947 * @byte_cnt: number of bytes to read
2948 * @cont: whether another operation will be chained
2949 * @lock: whether to lock SF for PL access only
2950 * @valp: where to store the read data
2952 * Reads up to 4 bytes of data from the serial flash. The location of
2953 * the read needs to be specified prior to calling this by issuing the
2954 * appropriate commands to the serial flash.
2956 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2957 int lock, u32 *valp)
2961 if (!byte_cnt || byte_cnt > 4)
2963 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2965 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2966 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2967 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2969 *valp = t4_read_reg(adapter, SF_DATA_A);
2974 * sf1_write - write data to the serial flash
2975 * @adapter: the adapter
2976 * @byte_cnt: number of bytes to write
2977 * @cont: whether another operation will be chained
2978 * @lock: whether to lock SF for PL access only
2979 * @val: value to write
2981 * Writes up to 4 bytes of data to the serial flash. The location of
2982 * the write needs to be specified prior to calling this by issuing the
2983 * appropriate commands to the serial flash.
2985 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2988 if (!byte_cnt || byte_cnt > 4)
2990 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2992 t4_write_reg(adapter, SF_DATA_A, val);
2993 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2994 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2995 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2999 * flash_wait_op - wait for a flash operation to complete
3000 * @adapter: the adapter
3001 * @attempts: max number of polls of the status register
3002 * @delay: delay between polls in ms
3004 * Wait for a flash operation to complete by polling the status register.
3006 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3012 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3013 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3017 if (--attempts == 0)
3025 * t4_read_flash - read words from serial flash
3026 * @adapter: the adapter
3027 * @addr: the start address for the read
3028 * @nwords: how many 32-bit words to read
3029 * @data: where to store the read data
3030 * @byte_oriented: whether to store data as bytes or as words
3032 * Read the specified number of 32-bit words from the serial flash.
3033 * If @byte_oriented is set the read data is stored as a byte array
3034 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3035 * natural endianness.
3037 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3038 unsigned int nwords, u32 *data, int byte_oriented)
3042 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3045 addr = swab32(addr) | SF_RD_DATA_FAST;
3047 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3048 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3051 for ( ; nwords; nwords--, data++) {
3052 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3054 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3058 *data = (__force __u32)(cpu_to_be32(*data));
3064 * t4_write_flash - write up to a page of data to the serial flash
3065 * @adapter: the adapter
3066 * @addr: the start address to write
3067 * @n: length of data to write in bytes
3068 * @data: the data to write
3070 * Writes up to a page of data (256 bytes) to the serial flash starting
3071 * at the given address. All the data must be written to the same page.
3073 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3074 unsigned int n, const u8 *data)
3078 unsigned int i, c, left, val, offset = addr & 0xff;
3080 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3083 val = swab32(addr) | SF_PROG_PAGE;
3085 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3086 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3089 for (left = n; left; left -= c) {
3091 for (val = 0, i = 0; i < c; ++i)
3092 val = (val << 8) + *data++;
3094 ret = sf1_write(adapter, c, c != left, 1, val);
3098 ret = flash_wait_op(adapter, 8, 1);
3102 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3104 /* Read the page to verify the write succeeded */
3105 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3109 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3110 dev_err(adapter->pdev_dev,
3111 "failed to correctly write the flash page at %#x\n",
3118 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3123 * t4_get_fw_version - read the firmware version
3124 * @adapter: the adapter
3125 * @vers: where to place the version
3127 * Reads the FW version from flash.
3129 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3131 return t4_read_flash(adapter, FLASH_FW_START +
3132 offsetof(struct fw_hdr, fw_ver), 1,
3137 * t4_get_bs_version - read the firmware bootstrap version
3138 * @adapter: the adapter
3139 * @vers: where to place the version
3141 * Reads the FW Bootstrap version from flash.
3143 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3145 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3146 offsetof(struct fw_hdr, fw_ver), 1,
3151 * t4_get_tp_version - read the TP microcode version
3152 * @adapter: the adapter
3153 * @vers: where to place the version
3155 * Reads the TP microcode version from flash.
3157 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3159 return t4_read_flash(adapter, FLASH_FW_START +
3160 offsetof(struct fw_hdr, tp_microcode_ver),
3165 * t4_get_exprom_version - return the Expansion ROM version (if any)
3166 * @adapter: the adapter
3167 * @vers: where to place the version
3169 * Reads the Expansion ROM header from FLASH and returns the version
3170 * number (if present) through the @vers return value pointer. We return
3171 * this in the Firmware Version Format since it's convenient. Return
3172 * 0 on success, -ENOENT if no Expansion ROM is present.
3174 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3176 struct exprom_header {
3177 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3178 unsigned char hdr_ver[4]; /* Expansion ROM version */
3180 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3184 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3185 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3190 hdr = (struct exprom_header *)exprom_header_buf;
3191 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3194 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3195 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3196 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3197 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3202 * t4_get_vpd_version - return the VPD version
3203 * @adapter: the adapter
3204 * @vers: where to place the version
3206 * Reads the VPD via the Firmware interface (thus this can only be called
3207 * once we're ready to issue Firmware commands). The format of the
3208 * VPD version is adapter specific. Returns 0 on success, an error on
3211 * Note that early versions of the Firmware didn't include the ability
3212 * to retrieve the VPD version, so we zero-out the return-value parameter
3213 * in that case to avoid leaving it with garbage in it.
3215 * Also note that the Firmware will return its cached copy of the VPD
3216 * Revision ID, not the actual Revision ID as written in the Serial
3217 * EEPROM. This is only an issue if a new VPD has been written and the
3218 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3219 * to defer calling this routine till after a FW_RESET_CMD has been issued
3220 * if the Host Driver will be performing a full adapter initialization.
3222 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3227 vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3228 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3229 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3230 1, &vpdrev_param, vers);
3237 * t4_get_scfg_version - return the Serial Configuration version
3238 * @adapter: the adapter
3239 * @vers: where to place the version
3241 * Reads the Serial Configuration Version via the Firmware interface
3242 * (thus this can only be called once we're ready to issue Firmware
3243 * commands). The format of the Serial Configuration version is
3244 * adapter specific. Returns 0 on success, an error on failure.
3246 * Note that early versions of the Firmware didn't include the ability
3247 * to retrieve the Serial Configuration version, so we zero-out the
3248 * return-value parameter in that case to avoid leaving it with
3251 * Also note that the Firmware will return its cached copy of the Serial
3252 * Initialization Revision ID, not the actual Revision ID as written in
3253 * the Serial EEPROM. This is only an issue if a new VPD has been written
3254 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3255 * it's best to defer calling this routine till after a FW_RESET_CMD has
3256 * been issued if the Host Driver will be performing a full adapter
3259 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3264 scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3265 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3266 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3267 1, &scfgrev_param, vers);
3274 * t4_get_version_info - extract various chip/firmware version information
3275 * @adapter: the adapter
3277 * Reads various chip/firmware version numbers and stores them into the
3278 * adapter Adapter Parameters structure. If any of the efforts fails
3279 * the first failure will be returned, but all of the version numbers
3282 int t4_get_version_info(struct adapter *adapter)
3286 #define FIRST_RET(__getvinfo) \
3288 int __ret = __getvinfo; \
3289 if (__ret && !ret) \
3293 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3294 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3295 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3296 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3297 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3298 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3305 * t4_dump_version_info - dump all of the adapter configuration IDs
3306 * @adapter: the adapter
3308 * Dumps all of the various bits of adapter configuration version/revision
3309 * IDs information. This is typically called at some point after
3310 * t4_get_version_info() has been called.
3312 void t4_dump_version_info(struct adapter *adapter)
3314 /* Device information */
3315 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3316 adapter->params.vpd.id,
3317 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3318 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3319 adapter->params.vpd.sn, adapter->params.vpd.pn);
3321 /* Firmware Version */
3322 if (!adapter->params.fw_vers)
3323 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3325 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3326 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3327 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3328 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3329 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3331 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3332 * Firmware, so dev_info() is more appropriate here.)
3334 if (!adapter->params.bs_vers)
3335 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3337 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3338 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3339 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3340 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3341 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3343 /* TP Microcode Version */
3344 if (!adapter->params.tp_vers)
3345 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3347 dev_info(adapter->pdev_dev,
3348 "TP Microcode version: %u.%u.%u.%u\n",
3349 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3350 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3351 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3352 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3354 /* Expansion ROM version */
3355 if (!adapter->params.er_vers)
3356 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3358 dev_info(adapter->pdev_dev,
3359 "Expansion ROM version: %u.%u.%u.%u\n",
3360 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3361 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3362 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3363 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3365 /* Serial Configuration version */
3366 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3367 adapter->params.scfg_vers);
3370 dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3371 adapter->params.vpd_vers);
3375 * t4_check_fw_version - check if the FW is supported with this driver
3376 * @adap: the adapter
3378 * Checks if an adapter's FW is compatible with the driver. Returns 0
3379 * if there's exact match, a negative error if the version could not be
3380 * read or there's a major version mismatch
3382 int t4_check_fw_version(struct adapter *adap)
3384 int i, ret, major, minor, micro;
3385 int exp_major, exp_minor, exp_micro;
3386 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3388 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3389 /* Try multiple times before returning error */
3390 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3391 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3396 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3397 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3398 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3400 switch (chip_version) {
3402 exp_major = T4FW_MIN_VERSION_MAJOR;
3403 exp_minor = T4FW_MIN_VERSION_MINOR;
3404 exp_micro = T4FW_MIN_VERSION_MICRO;
3407 exp_major = T5FW_MIN_VERSION_MAJOR;
3408 exp_minor = T5FW_MIN_VERSION_MINOR;
3409 exp_micro = T5FW_MIN_VERSION_MICRO;
3412 exp_major = T6FW_MIN_VERSION_MAJOR;
3413 exp_minor = T6FW_MIN_VERSION_MINOR;
3414 exp_micro = T6FW_MIN_VERSION_MICRO;
3417 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3422 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3423 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3424 dev_err(adap->pdev_dev,
3425 "Card has firmware version %u.%u.%u, minimum "
3426 "supported firmware is %u.%u.%u.\n", major, minor,
3427 micro, exp_major, exp_minor, exp_micro);
3433 /* Is the given firmware API compatible with the one the driver was compiled
3436 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3439 /* short circuit if it's the exact same firmware version */
3440 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3443 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3444 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3445 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3452 /* The firmware in the filesystem is usable, but should it be installed?
3453 * This routine explains itself in detail if it indicates the filesystem
3454 * firmware should be installed.
3456 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3461 if (!card_fw_usable) {
3462 reason = "incompatible or unusable";
3467 reason = "older than the version supported with this driver";
3474 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3475 "installing firmware %u.%u.%u.%u on card.\n",
3476 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3477 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3478 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3479 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3484 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3485 const u8 *fw_data, unsigned int fw_size,
3486 struct fw_hdr *card_fw, enum dev_state state,
3489 int ret, card_fw_usable, fs_fw_usable;
3490 const struct fw_hdr *fs_fw;
3491 const struct fw_hdr *drv_fw;
3493 drv_fw = &fw_info->fw_hdr;
3495 /* Read the header of the firmware on the card */
3496 ret = -t4_read_flash(adap, FLASH_FW_START,
3497 sizeof(*card_fw) / sizeof(uint32_t),
3498 (uint32_t *)card_fw, 1);
3500 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3502 dev_err(adap->pdev_dev,
3503 "Unable to read card's firmware header: %d\n", ret);
3507 if (fw_data != NULL) {
3508 fs_fw = (const void *)fw_data;
3509 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3515 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3516 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3517 /* Common case: the firmware on the card is an exact match and
3518 * the filesystem one is an exact match too, or the filesystem
3519 * one is absent/incompatible.
3521 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3522 should_install_fs_fw(adap, card_fw_usable,
3523 be32_to_cpu(fs_fw->fw_ver),
3524 be32_to_cpu(card_fw->fw_ver))) {
3525 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3528 dev_err(adap->pdev_dev,
3529 "failed to install firmware: %d\n", ret);
3533 /* Installed successfully, update the cached header too. */
3536 *reset = 0; /* already reset as part of load_fw */
3539 if (!card_fw_usable) {
3542 d = be32_to_cpu(drv_fw->fw_ver);
3543 c = be32_to_cpu(card_fw->fw_ver);
3544 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3546 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3548 "driver compiled with %d.%d.%d.%d, "
3549 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3551 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3552 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3553 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3554 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3555 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3556 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3561 /* We're using whatever's on the card and it's known to be good. */
3562 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3563 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3570 * t4_flash_erase_sectors - erase a range of flash sectors
3571 * @adapter: the adapter
3572 * @start: the first sector to erase
3573 * @end: the last sector to erase
3575 * Erases the sectors in the given inclusive range.
3577 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3581 if (end >= adapter->params.sf_nsec)
3584 while (start <= end) {
3585 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3586 (ret = sf1_write(adapter, 4, 0, 1,
3587 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3588 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3589 dev_err(adapter->pdev_dev,
3590 "erase of flash sector %d failed, error %d\n",
3596 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3601 * t4_flash_cfg_addr - return the address of the flash configuration file
3602 * @adapter: the adapter
3604 * Return the address within the flash where the Firmware Configuration
3607 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3609 if (adapter->params.sf_size == 0x100000)
3610 return FLASH_FPGA_CFG_START;
3612 return FLASH_CFG_START;
3615 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3616 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3617 * and emit an error message for mismatched firmware to save our caller the
3620 static bool t4_fw_matches_chip(const struct adapter *adap,
3621 const struct fw_hdr *hdr)
3623 /* The expression below will return FALSE for any unsupported adapter
3624 * which will keep us "honest" in the future ...
3626 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3627 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3628 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3631 dev_err(adap->pdev_dev,
3632 "FW image (%d) is not suitable for this adapter (%d)\n",
3633 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3638 * t4_load_fw - download firmware
3639 * @adap: the adapter
3640 * @fw_data: the firmware image to write
3643 * Write the supplied firmware image to the card's serial flash.
3645 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3650 u8 first_page[SF_PAGE_SIZE];
3651 const __be32 *p = (const __be32 *)fw_data;
3652 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3653 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3654 unsigned int fw_start_sec = FLASH_FW_START_SEC;
3655 unsigned int fw_size = FLASH_FW_MAX_SIZE;
3656 unsigned int fw_start = FLASH_FW_START;
3659 dev_err(adap->pdev_dev, "FW image has no data\n");
3663 dev_err(adap->pdev_dev,
3664 "FW image size not multiple of 512 bytes\n");
3667 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3668 dev_err(adap->pdev_dev,
3669 "FW image size differs from size in FW header\n");
3672 if (size > fw_size) {
3673 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3677 if (!t4_fw_matches_chip(adap, hdr))
3680 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3681 csum += be32_to_cpu(p[i]);
3683 if (csum != 0xffffffff) {
3684 dev_err(adap->pdev_dev,
3685 "corrupted firmware image, checksum %#x\n", csum);
3689 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3690 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3695 * We write the correct version at the end so the driver can see a bad
3696 * version if the FW write fails. Start by writing a copy of the
3697 * first page with a bad version.
3699 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3700 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3701 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page);
3706 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3707 addr += SF_PAGE_SIZE;
3708 fw_data += SF_PAGE_SIZE;
3709 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3714 ret = t4_write_flash(adap,
3715 fw_start + offsetof(struct fw_hdr, fw_ver),
3716 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3719 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3722 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3727 * t4_phy_fw_ver - return current PHY firmware version
3728 * @adap: the adapter
3729 * @phy_fw_ver: return value buffer for PHY firmware version
3731 * Returns the current version of external PHY firmware on the
3734 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3739 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3740 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3741 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3742 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3743 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3752 * t4_load_phy_fw - download port PHY firmware
3753 * @adap: the adapter
3754 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3755 * @win_lock: the lock to use to guard the memory copy
3756 * @phy_fw_version: function to check PHY firmware versions
3757 * @phy_fw_data: the PHY firmware image to write
3758 * @phy_fw_size: image size
3760 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3761 * @phy_fw_version is supplied, then it will be used to determine if
3762 * it's necessary to perform the transfer by comparing the version
3763 * of any existing adapter PHY firmware with that of the passed in
3764 * PHY firmware image. If @win_lock is non-NULL then it will be used
3765 * around the call to t4_memory_rw() which transfers the PHY firmware
3768 * A negative error number will be returned if an error occurs. If
3769 * version number support is available and there's no need to upgrade
3770 * the firmware, 0 will be returned. If firmware is successfully
3771 * transferred to the adapter, 1 will be returned.
3773 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3774 * a result, a RESET of the adapter would cause that RAM to lose its
3775 * contents. Thus, loading PHY firmware on such adapters must happen
3776 * after any FW_RESET_CMDs ...
3778 int t4_load_phy_fw(struct adapter *adap,
3779 int win, spinlock_t *win_lock,
3780 int (*phy_fw_version)(const u8 *, size_t),
3781 const u8 *phy_fw_data, size_t phy_fw_size)
3783 unsigned long mtype = 0, maddr = 0;
3785 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3788 /* If we have version number support, then check to see if the adapter
3789 * already has up-to-date PHY firmware loaded.
3791 if (phy_fw_version) {
3792 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3793 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3797 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3798 CH_WARN(adap, "PHY Firmware already up-to-date, "
3799 "version %#x\n", cur_phy_fw_ver);
3804 /* Ask the firmware where it wants us to copy the PHY firmware image.
3805 * The size of the file requires a special version of the READ command
3806 * which will pass the file size via the values field in PARAMS_CMD and
3807 * retrieve the return value from firmware and place it in the same
3810 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3811 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3812 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3813 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3815 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3816 ¶m, &val, 1, true);
3820 maddr = (val & 0xff) << 16;
3822 /* Copy the supplied PHY Firmware image to the adapter memory location
3823 * allocated by the adapter firmware.
3826 spin_lock_bh(win_lock);
3827 ret = t4_memory_rw(adap, win, mtype, maddr,
3828 phy_fw_size, (__be32 *)phy_fw_data,
3831 spin_unlock_bh(win_lock);
3835 /* Tell the firmware that the PHY firmware image has been written to
3836 * RAM and it can now start copying it over to the PHYs. The chip
3837 * firmware will RESET the affected PHYs as part of this operation
3838 * leaving them running the new PHY firmware image.
3840 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3841 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3842 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3843 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3844 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3845 ¶m, &val, 30000);
3847 /* If we have version number support, then check to see that the new
3848 * firmware got loaded properly.
3850 if (phy_fw_version) {
3851 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3855 if (cur_phy_fw_ver != new_phy_fw_vers) {
3856 CH_WARN(adap, "PHY Firmware did not update: "
3857 "version on adapter %#x, "
3858 "version flashed %#x\n",
3859 cur_phy_fw_ver, new_phy_fw_vers);
3868 * t4_fwcache - firmware cache operation
3869 * @adap: the adapter
3870 * @op : the operation (flush or flush and invalidate)
3872 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3874 struct fw_params_cmd c;
3876 memset(&c, 0, sizeof(c));
3878 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3879 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3880 FW_PARAMS_CMD_PFN_V(adap->pf) |
3881 FW_PARAMS_CMD_VFN_V(0));
3882 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3884 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3885 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3886 c.param[0].val = cpu_to_be32(op);
3888 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3891 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3892 unsigned int *pif_req_wrptr,
3893 unsigned int *pif_rsp_wrptr)
3896 u32 cfg, val, req, rsp;
3898 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3899 if (cfg & LADBGEN_F)
3900 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3902 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3903 req = POLADBGWRPTR_G(val);
3904 rsp = PILADBGWRPTR_G(val);
3906 *pif_req_wrptr = req;
3908 *pif_rsp_wrptr = rsp;
3910 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3911 for (j = 0; j < 6; j++) {
3912 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3913 PILADBGRDPTR_V(rsp));
3914 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3915 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3919 req = (req + 2) & POLADBGRDPTR_M;
3920 rsp = (rsp + 2) & PILADBGRDPTR_M;
3922 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3925 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3930 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3931 if (cfg & LADBGEN_F)
3932 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3934 for (i = 0; i < CIM_MALA_SIZE; i++) {
3935 for (j = 0; j < 5; j++) {
3937 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3938 PILADBGRDPTR_V(idx));
3939 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3940 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3943 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3946 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3950 for (i = 0; i < 8; i++) {
3951 u32 *p = la_buf + i;
3953 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3954 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3955 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3956 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3957 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3961 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3962 * Capabilities which we control with separate controls -- see, for instance,
3963 * Pause Frames and Forward Error Correction. In order to determine what the
3964 * full set of Advertised Port Capabilities are, the base Advertised Port
3965 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3966 * Port Capabilities associated with those other controls. See
3967 * t4_link_acaps() for how this is done.
3969 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3973 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3974 * @caps16: a 16-bit Port Capabilities value
3976 * Returns the equivalent 32-bit Port Capabilities value.
3978 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3980 fw_port_cap32_t caps32 = 0;
3982 #define CAP16_TO_CAP32(__cap) \
3984 if (caps16 & FW_PORT_CAP_##__cap) \
3985 caps32 |= FW_PORT_CAP32_##__cap; \
3988 CAP16_TO_CAP32(SPEED_100M);
3989 CAP16_TO_CAP32(SPEED_1G);
3990 CAP16_TO_CAP32(SPEED_25G);
3991 CAP16_TO_CAP32(SPEED_10G);
3992 CAP16_TO_CAP32(SPEED_40G);
3993 CAP16_TO_CAP32(SPEED_100G);
3994 CAP16_TO_CAP32(FC_RX);
3995 CAP16_TO_CAP32(FC_TX);
3996 CAP16_TO_CAP32(ANEG);
3997 CAP16_TO_CAP32(FORCE_PAUSE);
3998 CAP16_TO_CAP32(MDIAUTO);
3999 CAP16_TO_CAP32(MDISTRAIGHT);
4000 CAP16_TO_CAP32(FEC_RS);
4001 CAP16_TO_CAP32(FEC_BASER_RS);
4002 CAP16_TO_CAP32(802_3_PAUSE);
4003 CAP16_TO_CAP32(802_3_ASM_DIR);
4005 #undef CAP16_TO_CAP32
4011 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4012 * @caps32: a 32-bit Port Capabilities value
4014 * Returns the equivalent 16-bit Port Capabilities value. Note that
4015 * not all 32-bit Port Capabilities can be represented in the 16-bit
4016 * Port Capabilities and some fields/values may not make it.
4018 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4020 fw_port_cap16_t caps16 = 0;
4022 #define CAP32_TO_CAP16(__cap) \
4024 if (caps32 & FW_PORT_CAP32_##__cap) \
4025 caps16 |= FW_PORT_CAP_##__cap; \
4028 CAP32_TO_CAP16(SPEED_100M);
4029 CAP32_TO_CAP16(SPEED_1G);
4030 CAP32_TO_CAP16(SPEED_10G);
4031 CAP32_TO_CAP16(SPEED_25G);
4032 CAP32_TO_CAP16(SPEED_40G);
4033 CAP32_TO_CAP16(SPEED_100G);
4034 CAP32_TO_CAP16(FC_RX);
4035 CAP32_TO_CAP16(FC_TX);
4036 CAP32_TO_CAP16(802_3_PAUSE);
4037 CAP32_TO_CAP16(802_3_ASM_DIR);
4038 CAP32_TO_CAP16(ANEG);
4039 CAP32_TO_CAP16(FORCE_PAUSE);
4040 CAP32_TO_CAP16(MDIAUTO);
4041 CAP32_TO_CAP16(MDISTRAIGHT);
4042 CAP32_TO_CAP16(FEC_RS);
4043 CAP32_TO_CAP16(FEC_BASER_RS);
4045 #undef CAP32_TO_CAP16
4050 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4051 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4053 enum cc_pause cc_pause = 0;
4055 if (fw_pause & FW_PORT_CAP32_FC_RX)
4056 cc_pause |= PAUSE_RX;
4057 if (fw_pause & FW_PORT_CAP32_FC_TX)
4058 cc_pause |= PAUSE_TX;
4063 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4064 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4066 /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4069 fw_port_cap32_t fw_pause = 0;
4071 if (cc_pause & PAUSE_RX)
4072 fw_pause |= FW_PORT_CAP32_FC_RX;
4073 if (cc_pause & PAUSE_TX)
4074 fw_pause |= FW_PORT_CAP32_FC_TX;
4075 if (!(cc_pause & PAUSE_AUTONEG))
4076 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4078 /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4079 * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4080 * Note that these bits are ignored in L1 Configure commands.
4082 if (cc_pause & PAUSE_RX) {
4083 if (cc_pause & PAUSE_TX)
4084 fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4086 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4087 FW_PORT_CAP32_802_3_PAUSE;
4088 } else if (cc_pause & PAUSE_TX) {
4089 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4095 /* Translate Firmware Forward Error Correction specification to Common Code */
4096 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4098 enum cc_fec cc_fec = 0;
4100 if (fw_fec & FW_PORT_CAP32_FEC_RS)
4102 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4103 cc_fec |= FEC_BASER_RS;
4108 /* Translate Common Code Forward Error Correction specification to Firmware */
4109 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4111 fw_port_cap32_t fw_fec = 0;
4113 if (cc_fec & FEC_RS)
4114 fw_fec |= FW_PORT_CAP32_FEC_RS;
4115 if (cc_fec & FEC_BASER_RS)
4116 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4122 * t4_link_acaps - compute Link Advertised Port Capabilities
4123 * @adapter: the adapter
4124 * @port: the Port ID
4125 * @lc: the Port's Link Configuration
4127 * Synthesize the Advertised Port Capabilities we'll be using based on
4128 * the base Advertised Port Capabilities (which have been filtered by
4129 * ADVERT_MASK) plus the individual controls for things like Pause
4130 * Frames, Forward Error Correction, MDI, etc.
4132 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4133 struct link_config *lc)
4135 fw_port_cap32_t fw_fc, fw_fec, acaps;
4136 unsigned int fw_mdi;
4139 fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4141 /* Convert driver coding of Pause Frame Flow Control settings into the
4144 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4146 /* Convert Common Code Forward Error Control settings into the
4147 * Firmware's API. If the current Requested FEC has "Automatic"
4148 * (IEEE 802.3) specified, then we use whatever the Firmware
4149 * sent us as part of its IEEE 802.3-based interpretation of
4150 * the Transceiver Module EPROM FEC parameters. Otherwise we
4151 * use whatever is in the current Requested FEC settings.
4153 if (lc->requested_fec & FEC_AUTO)
4154 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4156 cc_fec = lc->requested_fec;
4157 fw_fec = cc_to_fwcap_fec(cc_fec);
4159 /* Figure out what our Requested Port Capabilities are going to be.
4160 * Note parallel structure in t4_handle_get_port_info() and
4161 * init_link_config().
4163 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4164 acaps = lc->acaps | fw_fc | fw_fec;
4165 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4167 } else if (lc->autoneg == AUTONEG_DISABLE) {
4168 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4169 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4172 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4175 /* Some Requested Port Capabilities are trivially wrong if they exceed
4176 * the Physical Port Capabilities. We can check that here and provide
4177 * moderately useful feedback in the system log.
4179 * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4180 * we need to exclude this from this check in order to maintain
4183 if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4184 dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4193 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4194 * @adapter: the adapter
4195 * @mbox: the Firmware Mailbox to use
4196 * @port: the Port ID
4197 * @lc: the Port's Link Configuration
4198 * @sleep_ok: if true we may sleep while awaiting command completion
4199 * @timeout: time to wait for command to finish before timing out
4200 * (negative implies @sleep_ok=false)
4202 * Set up a port's MAC and PHY according to a desired link configuration.
4203 * - If the PHY can auto-negotiate first decide what to advertise, then
4204 * enable/disable auto-negotiation as desired, and reset.
4205 * - If the PHY does not auto-negotiate just reset it.
4206 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4207 * otherwise do it later based on the outcome of auto-negotiation.
4209 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4210 unsigned int port, struct link_config *lc,
4211 u8 sleep_ok, int timeout)
4213 unsigned int fw_caps = adapter->params.fw_caps_support;
4214 struct fw_port_cmd cmd;
4215 fw_port_cap32_t rcap;
4218 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4219 lc->autoneg == AUTONEG_ENABLE) {
4223 /* Compute our Requested Port Capabilities and send that on to the
4226 rcap = t4_link_acaps(adapter, port, lc);
4227 memset(&cmd, 0, sizeof(cmd));
4228 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4229 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4230 FW_PORT_CMD_PORTID_V(port));
4231 cmd.action_to_len16 =
4232 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4233 ? FW_PORT_ACTION_L1_CFG
4234 : FW_PORT_ACTION_L1_CFG32) |
4236 if (fw_caps == FW_CAPS16)
4237 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4239 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4241 ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4244 /* Unfortunately, even if the Requested Port Capabilities "fit" within
4245 * the Physical Port Capabilities, some combinations of features may
4246 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
4247 * Error Correction. So if the Firmware rejects the L1 Configure
4248 * request, flag that here.
4251 dev_err(adapter->pdev_dev,
4252 "Requested Port Capabilities %#x rejected, error %d\n",
4260 * t4_restart_aneg - restart autonegotiation
4261 * @adap: the adapter
4262 * @mbox: mbox to use for the FW command
4263 * @port: the port id
4265 * Restarts autonegotiation for the selected port.
4267 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4269 unsigned int fw_caps = adap->params.fw_caps_support;
4270 struct fw_port_cmd c;
4272 memset(&c, 0, sizeof(c));
4273 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4274 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4275 FW_PORT_CMD_PORTID_V(port));
4277 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4278 ? FW_PORT_ACTION_L1_CFG
4279 : FW_PORT_ACTION_L1_CFG32) |
4281 if (fw_caps == FW_CAPS16)
4282 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4284 c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4285 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4288 typedef void (*int_handler_t)(struct adapter *adap);
4291 unsigned int mask; /* bits to check in interrupt status */
4292 const char *msg; /* message to print or NULL */
4293 short stat_idx; /* stat counter to increment or -1 */
4294 unsigned short fatal; /* whether the condition reported is fatal */
4295 int_handler_t int_handler; /* platform-specific int handler */
4299 * t4_handle_intr_status - table driven interrupt handler
4300 * @adapter: the adapter that generated the interrupt
4301 * @reg: the interrupt status register to process
4302 * @acts: table of interrupt actions
4304 * A table driven interrupt handler that applies a set of masks to an
4305 * interrupt status word and performs the corresponding actions if the
4306 * interrupts described by the mask have occurred. The actions include
4307 * optionally emitting a warning or alert message. The table is terminated
4308 * by an entry specifying mask 0. Returns the number of fatal interrupt
4311 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4312 const struct intr_info *acts)
4315 unsigned int mask = 0;
4316 unsigned int status = t4_read_reg(adapter, reg);
4318 for ( ; acts->mask; ++acts) {
4319 if (!(status & acts->mask))
4323 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4324 status & acts->mask);
4325 } else if (acts->msg && printk_ratelimit())
4326 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4327 status & acts->mask);
4328 if (acts->int_handler)
4329 acts->int_handler(adapter);
4333 if (status) /* clear processed interrupts */
4334 t4_write_reg(adapter, reg, status);
4339 * Interrupt handler for the PCIE module.
4341 static void pcie_intr_handler(struct adapter *adapter)
4343 static const struct intr_info sysbus_intr_info[] = {
4344 { RNPP_F, "RXNP array parity error", -1, 1 },
4345 { RPCP_F, "RXPC array parity error", -1, 1 },
4346 { RCIP_F, "RXCIF array parity error", -1, 1 },
4347 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4348 { RFTP_F, "RXFT array parity error", -1, 1 },
4351 static const struct intr_info pcie_port_intr_info[] = {
4352 { TPCP_F, "TXPC array parity error", -1, 1 },
4353 { TNPP_F, "TXNP array parity error", -1, 1 },
4354 { TFTP_F, "TXFT array parity error", -1, 1 },
4355 { TCAP_F, "TXCA array parity error", -1, 1 },
4356 { TCIP_F, "TXCIF array parity error", -1, 1 },
4357 { RCAP_F, "RXCA array parity error", -1, 1 },
4358 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4359 { RDPE_F, "Rx data parity error", -1, 1 },
4360 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4363 static const struct intr_info pcie_intr_info[] = {
4364 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4365 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4366 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4367 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4368 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4369 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4370 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4371 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4372 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4373 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4374 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4375 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4376 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4377 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4378 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4379 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4380 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4381 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4382 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4383 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4384 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4385 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4386 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4387 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4388 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4389 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4390 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4391 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4392 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4393 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4398 static struct intr_info t5_pcie_intr_info[] = {
4399 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4401 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4402 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4403 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4404 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4405 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4406 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4407 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4409 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4411 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4412 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4413 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4414 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4415 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4417 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4418 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4419 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4420 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4421 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4422 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4423 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4424 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4425 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4426 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4427 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4429 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4431 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4432 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4433 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4434 { READRSPERR_F, "Outbound read error", -1, 0 },
4440 if (is_t4(adapter->params.chip))
4441 fat = t4_handle_intr_status(adapter,
4442 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4444 t4_handle_intr_status(adapter,
4445 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4446 pcie_port_intr_info) +
4447 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4450 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4454 t4_fatal_err(adapter);
4458 * TP interrupt handler.
4460 static void tp_intr_handler(struct adapter *adapter)
4462 static const struct intr_info tp_intr_info[] = {
4463 { 0x3fffffff, "TP parity error", -1, 1 },
4464 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4468 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4469 t4_fatal_err(adapter);
4473 * SGE interrupt handler.
4475 static void sge_intr_handler(struct adapter *adapter)
4480 static const struct intr_info sge_intr_info[] = {
4481 { ERR_CPL_EXCEED_IQE_SIZE_F,
4482 "SGE received CPL exceeding IQE size", -1, 1 },
4483 { ERR_INVALID_CIDX_INC_F,
4484 "SGE GTS CIDX increment too large", -1, 0 },
4485 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4486 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4487 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4488 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4489 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4491 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4493 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4495 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4497 { ERR_ING_CTXT_PRIO_F,
4498 "SGE too many priority ingress contexts", -1, 0 },
4499 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4500 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4504 static struct intr_info t4t5_sge_intr_info[] = {
4505 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4506 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4507 { ERR_EGR_CTXT_PRIO_F,
4508 "SGE too many priority egress contexts", -1, 0 },
4512 perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4515 dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
4519 perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4522 dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
4526 if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
4527 perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4528 /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4529 perr &= ~ERR_T_RXCRC_F;
4532 dev_alert(adapter->pdev_dev,
4533 "SGE Cause5 Parity Error %#x\n", perr);
4537 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4538 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4539 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4540 t4t5_sge_intr_info);
4542 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4543 if (err & ERROR_QID_VALID_F) {
4544 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4546 if (err & UNCAPTURED_ERROR_F)
4547 dev_err(adapter->pdev_dev,
4548 "SGE UNCAPTURED_ERROR set (clearing)\n");
4549 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4550 UNCAPTURED_ERROR_F);
4554 t4_fatal_err(adapter);
4557 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4558 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4559 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4560 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4563 * CIM interrupt handler.
4565 static void cim_intr_handler(struct adapter *adapter)
4567 static const struct intr_info cim_intr_info[] = {
4568 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4569 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4570 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4571 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4572 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4573 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4574 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4575 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4578 static const struct intr_info cim_upintr_info[] = {
4579 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4580 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4581 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4582 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4583 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4584 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4585 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4586 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4587 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4588 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4589 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4590 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4591 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4592 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4593 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4594 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4595 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4596 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4597 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4598 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4599 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4600 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4601 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4602 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4603 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4604 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4605 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4606 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4613 fw_err = t4_read_reg(adapter, PCIE_FW_A);
4614 if (fw_err & PCIE_FW_ERR_F)
4615 t4_report_fw_error(adapter);
4617 /* When the Firmware detects an internal error which normally
4618 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4619 * in order to make sure the Host sees the Firmware Crash. So
4620 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4621 * ignore the Timer0 interrupt.
4624 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4625 if (val & TIMER0INT_F)
4626 if (!(fw_err & PCIE_FW_ERR_F) ||
4627 (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4628 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4631 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4633 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4636 t4_fatal_err(adapter);
4640 * ULP RX interrupt handler.
4642 static void ulprx_intr_handler(struct adapter *adapter)
4644 static const struct intr_info ulprx_intr_info[] = {
4645 { 0x1800000, "ULPRX context error", -1, 1 },
4646 { 0x7fffff, "ULPRX parity error", -1, 1 },
4650 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4651 t4_fatal_err(adapter);
4655 * ULP TX interrupt handler.
4657 static void ulptx_intr_handler(struct adapter *adapter)
4659 static const struct intr_info ulptx_intr_info[] = {
4660 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4662 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4664 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4666 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4668 { 0xfffffff, "ULPTX parity error", -1, 1 },
4672 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4673 t4_fatal_err(adapter);
4677 * PM TX interrupt handler.
4679 static void pmtx_intr_handler(struct adapter *adapter)
4681 static const struct intr_info pmtx_intr_info[] = {
4682 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4683 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4684 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4685 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4686 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4687 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4688 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4690 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4691 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4695 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4696 t4_fatal_err(adapter);
4700 * PM RX interrupt handler.
4702 static void pmrx_intr_handler(struct adapter *adapter)
4704 static const struct intr_info pmrx_intr_info[] = {
4705 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4706 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4707 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4708 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4710 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4711 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4715 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4716 t4_fatal_err(adapter);
4720 * CPL switch interrupt handler.
4722 static void cplsw_intr_handler(struct adapter *adapter)
4724 static const struct intr_info cplsw_intr_info[] = {
4725 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4726 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4727 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4728 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4729 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4730 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4734 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4735 t4_fatal_err(adapter);
4739 * LE interrupt handler.
4741 static void le_intr_handler(struct adapter *adap)
4743 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4744 static const struct intr_info le_intr_info[] = {
4745 { LIPMISS_F, "LE LIP miss", -1, 0 },
4746 { LIP0_F, "LE 0 LIP error", -1, 0 },
4747 { PARITYERR_F, "LE parity error", -1, 1 },
4748 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4749 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4753 static struct intr_info t6_le_intr_info[] = {
4754 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4755 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4756 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4757 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4758 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4762 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4763 (chip <= CHELSIO_T5) ?
4764 le_intr_info : t6_le_intr_info))
4769 * MPS interrupt handler.
4771 static void mps_intr_handler(struct adapter *adapter)
4773 static const struct intr_info mps_rx_intr_info[] = {
4774 { 0xffffff, "MPS Rx parity error", -1, 1 },
4777 static const struct intr_info mps_tx_intr_info[] = {
4778 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4779 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4780 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4782 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4784 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4785 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4786 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4789 static const struct intr_info t6_mps_tx_intr_info[] = {
4790 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4791 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4792 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4794 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4796 /* MPS Tx Bubble is normal for T6 */
4797 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4798 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4801 static const struct intr_info mps_trc_intr_info[] = {
4802 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4803 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4805 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4808 static const struct intr_info mps_stat_sram_intr_info[] = {
4809 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4812 static const struct intr_info mps_stat_tx_intr_info[] = {
4813 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4816 static const struct intr_info mps_stat_rx_intr_info[] = {
4817 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4820 static const struct intr_info mps_cls_intr_info[] = {
4821 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4822 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4823 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4829 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4831 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4832 is_t6(adapter->params.chip)
4833 ? t6_mps_tx_intr_info
4834 : mps_tx_intr_info) +
4835 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4836 mps_trc_intr_info) +
4837 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4838 mps_stat_sram_intr_info) +
4839 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4840 mps_stat_tx_intr_info) +
4841 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4842 mps_stat_rx_intr_info) +
4843 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4846 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4847 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4849 t4_fatal_err(adapter);
4852 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4856 * EDC/MC interrupt handler.
4858 static void mem_intr_handler(struct adapter *adapter, int idx)
4860 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4862 unsigned int addr, cnt_addr, v;
4864 if (idx <= MEM_EDC1) {
4865 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4866 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4867 } else if (idx == MEM_MC) {
4868 if (is_t4(adapter->params.chip)) {
4869 addr = MC_INT_CAUSE_A;
4870 cnt_addr = MC_ECC_STATUS_A;
4872 addr = MC_P_INT_CAUSE_A;
4873 cnt_addr = MC_P_ECC_STATUS_A;
4876 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4877 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4880 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4881 if (v & PERR_INT_CAUSE_F)
4882 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4884 if (v & ECC_CE_INT_CAUSE_F) {
4885 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4887 t4_edc_err_read(adapter, idx);
4889 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4890 if (printk_ratelimit())
4891 dev_warn(adapter->pdev_dev,
4892 "%u %s correctable ECC data error%s\n",
4893 cnt, name[idx], cnt > 1 ? "s" : "");
4895 if (v & ECC_UE_INT_CAUSE_F)
4896 dev_alert(adapter->pdev_dev,
4897 "%s uncorrectable ECC data error\n", name[idx]);
4899 t4_write_reg(adapter, addr, v);
4900 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4901 t4_fatal_err(adapter);
4905 * MA interrupt handler.
4907 static void ma_intr_handler(struct adapter *adap)
4909 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4911 if (status & MEM_PERR_INT_CAUSE_F) {
4912 dev_alert(adap->pdev_dev,
4913 "MA parity error, parity status %#x\n",
4914 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4915 if (is_t5(adap->params.chip))
4916 dev_alert(adap->pdev_dev,
4917 "MA parity error, parity status %#x\n",
4919 MA_PARITY_ERROR_STATUS2_A));
4921 if (status & MEM_WRAP_INT_CAUSE_F) {
4922 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4923 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4924 "client %u to address %#x\n",
4925 MEM_WRAP_CLIENT_NUM_G(v),
4926 MEM_WRAP_ADDRESS_G(v) << 4);
4928 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4933 * SMB interrupt handler.
4935 static void smb_intr_handler(struct adapter *adap)
4937 static const struct intr_info smb_intr_info[] = {
4938 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4939 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4940 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4944 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4949 * NC-SI interrupt handler.
4951 static void ncsi_intr_handler(struct adapter *adap)
4953 static const struct intr_info ncsi_intr_info[] = {
4954 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4955 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4956 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4957 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4961 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4966 * XGMAC interrupt handler.
4968 static void xgmac_intr_handler(struct adapter *adap, int port)
4970 u32 v, int_cause_reg;
4972 if (is_t4(adap->params.chip))
4973 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4975 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4977 v = t4_read_reg(adap, int_cause_reg);
4979 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4983 if (v & TXFIFO_PRTY_ERR_F)
4984 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4986 if (v & RXFIFO_PRTY_ERR_F)
4987 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4989 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4994 * PL interrupt handler.
4996 static void pl_intr_handler(struct adapter *adap)
4998 static const struct intr_info pl_intr_info[] = {
4999 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
5000 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
5004 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
5008 #define PF_INTR_MASK (PFSW_F)
5009 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5010 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5011 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5014 * t4_slow_intr_handler - control path interrupt handler
5015 * @adapter: the adapter
5017 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5018 * The designation 'slow' is because it involves register reads, while
5019 * data interrupts typically don't involve any MMIOs.
5021 int t4_slow_intr_handler(struct adapter *adapter)
5023 /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5024 * set when the corresponding PL_INT_ENABLE bit isn't set. It's
5025 * easiest just to mask that case here.
5027 u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5028 u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5029 u32 cause = raw_cause & enable;
5031 if (!(cause & GLBL_INTR_MASK))
5034 cim_intr_handler(adapter);
5036 mps_intr_handler(adapter);
5038 ncsi_intr_handler(adapter);
5040 pl_intr_handler(adapter);
5042 smb_intr_handler(adapter);
5043 if (cause & XGMAC0_F)
5044 xgmac_intr_handler(adapter, 0);
5045 if (cause & XGMAC1_F)
5046 xgmac_intr_handler(adapter, 1);
5047 if (cause & XGMAC_KR0_F)
5048 xgmac_intr_handler(adapter, 2);
5049 if (cause & XGMAC_KR1_F)
5050 xgmac_intr_handler(adapter, 3);
5052 pcie_intr_handler(adapter);
5054 mem_intr_handler(adapter, MEM_MC);
5055 if (is_t5(adapter->params.chip) && (cause & MC1_F))
5056 mem_intr_handler(adapter, MEM_MC1);
5058 mem_intr_handler(adapter, MEM_EDC0);
5060 mem_intr_handler(adapter, MEM_EDC1);
5062 le_intr_handler(adapter);
5064 tp_intr_handler(adapter);
5066 ma_intr_handler(adapter);
5067 if (cause & PM_TX_F)
5068 pmtx_intr_handler(adapter);
5069 if (cause & PM_RX_F)
5070 pmrx_intr_handler(adapter);
5071 if (cause & ULP_RX_F)
5072 ulprx_intr_handler(adapter);
5073 if (cause & CPL_SWITCH_F)
5074 cplsw_intr_handler(adapter);
5076 sge_intr_handler(adapter);
5077 if (cause & ULP_TX_F)
5078 ulptx_intr_handler(adapter);
5080 /* Clear the interrupts just processed for which we are the master. */
5081 t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
5082 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5087 * t4_intr_enable - enable interrupts
5088 * @adapter: the adapter whose interrupts should be enabled
5090 * Enable PF-specific interrupts for the calling function and the top-level
5091 * interrupt concentrator for global interrupts. Interrupts are already
5092 * enabled at each module, here we just enable the roots of the interrupt
5095 * Note: this function should be called only when the driver manages
5096 * non PF-specific interrupts from the various HW modules. Only one PCI
5097 * function at a time should be doing this.
5099 void t4_intr_enable(struct adapter *adapter)
5102 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5103 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5104 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5106 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5107 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5108 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5109 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5110 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5111 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5112 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5113 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5114 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5115 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5116 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5120 * t4_intr_disable - disable interrupts
5121 * @adapter: the adapter whose interrupts should be disabled
5123 * Disable interrupts. We only disable the top-level interrupt
5124 * concentrators. The caller must be a PCI function managing global
5127 void t4_intr_disable(struct adapter *adapter)
5131 if (pci_channel_offline(adapter->pdev))
5134 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5135 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5136 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5138 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5139 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5142 unsigned int t4_chip_rss_size(struct adapter *adap)
5144 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5145 return RSS_NENTRIES;
5147 return T6_RSS_NENTRIES;
5151 * t4_config_rss_range - configure a portion of the RSS mapping table
5152 * @adapter: the adapter
5153 * @mbox: mbox to use for the FW command
5154 * @viid: virtual interface whose RSS subtable is to be written
5155 * @start: start entry in the table to write
5156 * @n: how many table entries to write
5157 * @rspq: values for the response queue lookup table
5158 * @nrspq: number of values in @rspq
5160 * Programs the selected part of the VI's RSS mapping table with the
5161 * provided values. If @nrspq < @n the supplied values are used repeatedly
5162 * until the full table range is populated.
5164 * The caller must ensure the values in @rspq are in the range allowed for
5167 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5168 int start, int n, const u16 *rspq, unsigned int nrspq)
5171 const u16 *rsp = rspq;
5172 const u16 *rsp_end = rspq + nrspq;
5173 struct fw_rss_ind_tbl_cmd cmd;
5175 memset(&cmd, 0, sizeof(cmd));
5176 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5177 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5178 FW_RSS_IND_TBL_CMD_VIID_V(viid));
5179 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5181 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5183 int nq = min(n, 32);
5184 __be32 *qp = &cmd.iq0_to_iq2;
5186 cmd.niqid = cpu_to_be16(nq);
5187 cmd.startidx = cpu_to_be16(start);
5195 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5196 if (++rsp >= rsp_end)
5198 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5199 if (++rsp >= rsp_end)
5201 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5202 if (++rsp >= rsp_end)
5205 *qp++ = cpu_to_be32(v);
5209 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5217 * t4_config_glbl_rss - configure the global RSS mode
5218 * @adapter: the adapter
5219 * @mbox: mbox to use for the FW command
5220 * @mode: global RSS mode
5221 * @flags: mode-specific flags
5223 * Sets the global RSS mode.
5225 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5228 struct fw_rss_glb_config_cmd c;
5230 memset(&c, 0, sizeof(c));
5231 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5232 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5233 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5234 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5235 c.u.manual.mode_pkd =
5236 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5237 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5238 c.u.basicvirtual.mode_pkd =
5239 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5240 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5243 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5247 * t4_config_vi_rss - configure per VI RSS settings
5248 * @adapter: the adapter
5249 * @mbox: mbox to use for the FW command
5252 * @defq: id of the default RSS queue for the VI.
5254 * Configures VI-specific RSS properties.
5256 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5257 unsigned int flags, unsigned int defq)
5259 struct fw_rss_vi_config_cmd c;
5261 memset(&c, 0, sizeof(c));
5262 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5263 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5264 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5265 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5266 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5267 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5268 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5271 /* Read an RSS table row */
5272 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5274 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5275 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5280 * t4_read_rss - read the contents of the RSS mapping table
5281 * @adapter: the adapter
5282 * @map: holds the contents of the RSS mapping table
5284 * Reads the contents of the RSS hash->queue mapping table.
5286 int t4_read_rss(struct adapter *adapter, u16 *map)
5288 int i, ret, nentries;
5291 nentries = t4_chip_rss_size(adapter);
5292 for (i = 0; i < nentries / 2; ++i) {
5293 ret = rd_rss_row(adapter, i, &val);
5296 *map++ = LKPTBLQUEUE0_G(val);
5297 *map++ = LKPTBLQUEUE1_G(val);
5302 static unsigned int t4_use_ldst(struct adapter *adap)
5304 return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5308 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5309 * @adap: the adapter
5310 * @cmd: TP fw ldst address space type
5311 * @vals: where the indirect register values are stored/written
5312 * @nregs: how many indirect registers to read/write
5313 * @start_idx: index of first indirect register to read/write
5314 * @rw: Read (1) or Write (0)
5315 * @sleep_ok: if true we may sleep while awaiting command completion
5317 * Access TP indirect registers through LDST
5319 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5320 unsigned int nregs, unsigned int start_index,
5321 unsigned int rw, bool sleep_ok)
5325 struct fw_ldst_cmd c;
5327 for (i = 0; i < nregs; i++) {
5328 memset(&c, 0, sizeof(c));
5329 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5331 (rw ? FW_CMD_READ_F :
5333 FW_LDST_CMD_ADDRSPACE_V(cmd));
5334 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5336 c.u.addrval.addr = cpu_to_be32(start_index + i);
5337 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5338 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5344 vals[i] = be32_to_cpu(c.u.addrval.val);
5350 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5351 * @adap: the adapter
5352 * @reg_addr: Address Register
5353 * @reg_data: Data register
5354 * @buff: where the indirect register values are stored/written
5355 * @nregs: how many indirect registers to read/write
5356 * @start_index: index of first indirect register to read/write
5357 * @rw: READ(1) or WRITE(0)
5358 * @sleep_ok: if true we may sleep while awaiting command completion
5360 * Read/Write TP indirect registers through LDST if possible.
5361 * Else, use backdoor access
5363 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5364 u32 *buff, u32 nregs, u32 start_index, int rw,
5372 cmd = FW_LDST_ADDRSPC_TP_PIO;
5374 case TP_TM_PIO_ADDR_A:
5375 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5377 case TP_MIB_INDEX_A:
5378 cmd = FW_LDST_ADDRSPC_TP_MIB;
5381 goto indirect_access;
5384 if (t4_use_ldst(adap))
5385 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5392 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5395 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5401 * t4_tp_pio_read - Read TP PIO registers
5402 * @adap: the adapter
5403 * @buff: where the indirect register values are written
5404 * @nregs: how many indirect registers to read
5405 * @start_index: index of first indirect register to read
5406 * @sleep_ok: if true we may sleep while awaiting command completion
5408 * Read TP PIO Registers
5410 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5411 u32 start_index, bool sleep_ok)
5413 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5414 start_index, 1, sleep_ok);
5418 * t4_tp_pio_write - Write TP PIO registers
5419 * @adap: the adapter
5420 * @buff: where the indirect register values are stored
5421 * @nregs: how many indirect registers to write
5422 * @start_index: index of first indirect register to write
5423 * @sleep_ok: if true we may sleep while awaiting command completion
5425 * Write TP PIO Registers
5427 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5428 u32 start_index, bool sleep_ok)
5430 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5431 start_index, 0, sleep_ok);
5435 * t4_tp_tm_pio_read - Read TP TM PIO registers
5436 * @adap: the adapter
5437 * @buff: where the indirect register values are written
5438 * @nregs: how many indirect registers to read
5439 * @start_index: index of first indirect register to read
5440 * @sleep_ok: if true we may sleep while awaiting command completion
5442 * Read TP TM PIO Registers
5444 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5445 u32 start_index, bool sleep_ok)
5447 t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5448 nregs, start_index, 1, sleep_ok);
5452 * t4_tp_mib_read - Read TP MIB registers
5453 * @adap: the adapter
5454 * @buff: where the indirect register values are written
5455 * @nregs: how many indirect registers to read
5456 * @start_index: index of first indirect register to read
5457 * @sleep_ok: if true we may sleep while awaiting command completion
5459 * Read TP MIB Registers
5461 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5464 t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5465 start_index, 1, sleep_ok);
5469 * t4_read_rss_key - read the global RSS key
5470 * @adap: the adapter
5471 * @key: 10-entry array holding the 320-bit RSS key
5472 * @sleep_ok: if true we may sleep while awaiting command completion
5474 * Reads the global 320-bit RSS key.
5476 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5478 t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5482 * t4_write_rss_key - program one of the RSS keys
5483 * @adap: the adapter
5484 * @key: 10-entry array holding the 320-bit RSS key
5485 * @idx: which RSS key to write
5486 * @sleep_ok: if true we may sleep while awaiting command completion
5488 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5489 * 0..15 the corresponding entry in the RSS key table is written,
5490 * otherwise the global RSS key is written.
5492 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5495 u8 rss_key_addr_cnt = 16;
5496 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5498 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5499 * allows access to key addresses 16-63 by using KeyWrAddrX
5500 * as index[5:4](upper 2) into key table
5502 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5503 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5504 rss_key_addr_cnt = 32;
5506 t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5508 if (idx >= 0 && idx < rss_key_addr_cnt) {
5509 if (rss_key_addr_cnt > 16)
5510 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5511 KEYWRADDRX_V(idx >> 4) |
5512 T6_VFWRADDR_V(idx) | KEYWREN_F);
5514 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5515 KEYWRADDR_V(idx) | KEYWREN_F);
5520 * t4_read_rss_pf_config - read PF RSS Configuration Table
5521 * @adapter: the adapter
5522 * @index: the entry in the PF RSS table to read
5523 * @valp: where to store the returned value
5524 * @sleep_ok: if true we may sleep while awaiting command completion
5526 * Reads the PF RSS Configuration Table at the specified index and returns
5527 * the value found there.
5529 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5530 u32 *valp, bool sleep_ok)
5532 t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5536 * t4_read_rss_vf_config - read VF RSS Configuration Table
5537 * @adapter: the adapter
5538 * @index: the entry in the VF RSS table to read
5539 * @vfl: where to store the returned VFL
5540 * @vfh: where to store the returned VFH
5541 * @sleep_ok: if true we may sleep while awaiting command completion
5543 * Reads the VF RSS Configuration Table at the specified index and returns
5544 * the (VFL, VFH) values found there.
5546 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5547 u32 *vfl, u32 *vfh, bool sleep_ok)
5549 u32 vrt, mask, data;
5551 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5552 mask = VFWRADDR_V(VFWRADDR_M);
5553 data = VFWRADDR_V(index);
5555 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
5556 data = T6_VFWRADDR_V(index);
5559 /* Request that the index'th VF Table values be read into VFL/VFH.
5561 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5562 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5563 vrt |= data | VFRDEN_F;
5564 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5566 /* Grab the VFL/VFH values ...
5568 t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5569 t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5573 * t4_read_rss_pf_map - read PF RSS Map
5574 * @adapter: the adapter
5575 * @sleep_ok: if true we may sleep while awaiting command completion
5577 * Reads the PF RSS Map register and returns its value.
5579 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5583 t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5588 * t4_read_rss_pf_mask - read PF RSS Mask
5589 * @adapter: the adapter
5590 * @sleep_ok: if true we may sleep while awaiting command completion
5592 * Reads the PF RSS Mask register and returns its value.
5594 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5598 t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5603 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5604 * @adap: the adapter
5605 * @v4: holds the TCP/IP counter values
5606 * @v6: holds the TCP/IPv6 counter values
5607 * @sleep_ok: if true we may sleep while awaiting command completion
5609 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5610 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5612 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5613 struct tp_tcp_stats *v6, bool sleep_ok)
5615 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5617 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5618 #define STAT(x) val[STAT_IDX(x)]
5619 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5622 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5623 TP_MIB_TCP_OUT_RST_A, sleep_ok);
5624 v4->tcp_out_rsts = STAT(OUT_RST);
5625 v4->tcp_in_segs = STAT64(IN_SEG);
5626 v4->tcp_out_segs = STAT64(OUT_SEG);
5627 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5630 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5631 TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5632 v6->tcp_out_rsts = STAT(OUT_RST);
5633 v6->tcp_in_segs = STAT64(IN_SEG);
5634 v6->tcp_out_segs = STAT64(OUT_SEG);
5635 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5643 * t4_tp_get_err_stats - read TP's error MIB counters
5644 * @adap: the adapter
5645 * @st: holds the counter values
5646 * @sleep_ok: if true we may sleep while awaiting command completion
5648 * Returns the values of TP's error counters.
5650 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5653 int nchan = adap->params.arch.nchan;
5655 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5657 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5659 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5661 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5662 TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5663 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5664 TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5665 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5667 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5668 TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5669 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5670 TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5671 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5676 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5677 * @adap: the adapter
5678 * @st: holds the counter values
5679 * @sleep_ok: if true we may sleep while awaiting command completion
5681 * Returns the values of TP's CPL counters.
5683 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5686 int nchan = adap->params.arch.nchan;
5688 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5690 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5694 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5695 * @adap: the adapter
5696 * @st: holds the counter values
5697 * @sleep_ok: if true we may sleep while awaiting command completion
5699 * Returns the values of TP's RDMA counters.
5701 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5704 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5709 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5710 * @adap: the adapter
5711 * @idx: the port index
5712 * @st: holds the counter values
5713 * @sleep_ok: if true we may sleep while awaiting command completion
5715 * Returns the values of TP's FCoE counters for the selected port.
5717 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5718 struct tp_fcoe_stats *st, bool sleep_ok)
5722 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5725 t4_tp_mib_read(adap, &st->frames_drop, 1,
5726 TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5728 t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5731 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5735 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5736 * @adap: the adapter
5737 * @st: holds the counter values
5738 * @sleep_ok: if true we may sleep while awaiting command completion
5740 * Returns the values of TP's counters for non-TCP directly-placed packets.
5742 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5747 t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5748 st->frames = val[0];
5750 st->octets = ((u64)val[2] << 32) | val[3];
5754 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5755 * @adap: the adapter
5756 * @mtus: where to store the MTU values
5757 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5759 * Reads the HW path MTU table.
5761 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5766 for (i = 0; i < NMTUS; ++i) {
5767 t4_write_reg(adap, TP_MTU_TABLE_A,
5768 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5769 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5770 mtus[i] = MTUVALUE_G(v);
5772 mtu_log[i] = MTUWIDTH_G(v);
5777 * t4_read_cong_tbl - reads the congestion control table
5778 * @adap: the adapter
5779 * @incr: where to store the alpha values
5781 * Reads the additive increments programmed into the HW congestion
5784 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5786 unsigned int mtu, w;
5788 for (mtu = 0; mtu < NMTUS; ++mtu)
5789 for (w = 0; w < NCCTRL_WIN; ++w) {
5790 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5791 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5792 incr[mtu][w] = (u16)t4_read_reg(adap,
5793 TP_CCTRL_TABLE_A) & 0x1fff;
5798 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5799 * @adap: the adapter
5800 * @addr: the indirect TP register address
5801 * @mask: specifies the field within the register to modify
5802 * @val: new value for the field
5804 * Sets a field of an indirect TP register to the given value.
5806 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5807 unsigned int mask, unsigned int val)
5809 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5810 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5811 t4_write_reg(adap, TP_PIO_DATA_A, val);
5815 * init_cong_ctrl - initialize congestion control parameters
5816 * @a: the alpha values for congestion control
5817 * @b: the beta values for congestion control
5819 * Initialize the congestion control parameters.
5821 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5823 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5848 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5851 b[13] = b[14] = b[15] = b[16] = 3;
5852 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5853 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5858 /* The minimum additive increment value for the congestion control table */
5859 #define CC_MIN_INCR 2U
5862 * t4_load_mtus - write the MTU and congestion control HW tables
5863 * @adap: the adapter
5864 * @mtus: the values for the MTU table
5865 * @alpha: the values for the congestion control alpha parameter
5866 * @beta: the values for the congestion control beta parameter
5868 * Write the HW MTU table with the supplied MTUs and the high-speed
5869 * congestion control table with the supplied alpha, beta, and MTUs.
5870 * We write the two tables together because the additive increments
5871 * depend on the MTUs.
5873 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5874 const unsigned short *alpha, const unsigned short *beta)
5876 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5877 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5878 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5879 28672, 40960, 57344, 81920, 114688, 163840, 229376
5884 for (i = 0; i < NMTUS; ++i) {
5885 unsigned int mtu = mtus[i];
5886 unsigned int log2 = fls(mtu);
5888 if (!(mtu & ((1 << log2) >> 2))) /* round */
5890 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5891 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5893 for (w = 0; w < NCCTRL_WIN; ++w) {
5896 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5899 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5900 (w << 16) | (beta[w] << 13) | inc);
5905 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5906 * clocks. The formula is
5908 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5910 * which is equivalent to
5912 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5914 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5916 u64 v = bytes256 * adap->params.vpd.cclk;
5918 return v * 62 + v / 2;
5922 * t4_get_chan_txrate - get the current per channel Tx rates
5923 * @adap: the adapter
5924 * @nic_rate: rates for NIC traffic
5925 * @ofld_rate: rates for offloaded traffic
5927 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5930 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5934 v = t4_read_reg(adap, TP_TX_TRATE_A);
5935 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5936 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5937 if (adap->params.arch.nchan == NCHAN) {
5938 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5939 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5942 v = t4_read_reg(adap, TP_TX_ORATE_A);
5943 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5944 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5945 if (adap->params.arch.nchan == NCHAN) {
5946 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5947 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5952 * t4_set_trace_filter - configure one of the tracing filters
5953 * @adap: the adapter
5954 * @tp: the desired trace filter parameters
5955 * @idx: which filter to configure
5956 * @enable: whether to enable or disable the filter
5958 * Configures one of the tracing filters available in HW. If @enable is
5959 * %0 @tp is not examined and may be %NULL. The user is responsible to
5960 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5962 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5963 int idx, int enable)
5965 int i, ofst = idx * 4;
5966 u32 data_reg, mask_reg, cfg;
5969 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5973 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5974 if (cfg & TRCMULTIFILTER_F) {
5975 /* If multiple tracers are enabled, then maximum
5976 * capture size is 2.5KB (FIFO size of a single channel)
5977 * minus 2 flits for CPL_TRACE_PKT header.
5979 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5982 /* If multiple tracers are disabled, to avoid deadlocks
5983 * maximum packet capture size of 9600 bytes is recommended.
5984 * Also in this mode, only trace0 can be enabled and running.
5986 if (tp->snap_len > 9600 || idx)
5990 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5991 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5992 tp->min_len > TFMINPKTSIZE_M)
5995 /* stop the tracer we'll be changing */
5996 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5998 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5999 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
6000 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
6002 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6003 t4_write_reg(adap, data_reg, tp->data[i]);
6004 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6006 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
6007 TFCAPTUREMAX_V(tp->snap_len) |
6008 TFMINPKTSIZE_V(tp->min_len));
6009 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
6010 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
6011 (is_t4(adap->params.chip) ?
6012 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
6013 T5_TFPORT_V(tp->port) | T5_TFEN_F |
6014 T5_TFINVERTMATCH_V(tp->invert)));
6020 * t4_get_trace_filter - query one of the tracing filters
6021 * @adap: the adapter
6022 * @tp: the current trace filter parameters
6023 * @idx: which trace filter to query
6024 * @enabled: non-zero if the filter is enabled
6026 * Returns the current settings of one of the HW tracing filters.
6028 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6032 int i, ofst = idx * 4;
6033 u32 data_reg, mask_reg;
6035 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6036 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6038 if (is_t4(adap->params.chip)) {
6039 *enabled = !!(ctla & TFEN_F);
6040 tp->port = TFPORT_G(ctla);
6041 tp->invert = !!(ctla & TFINVERTMATCH_F);
6043 *enabled = !!(ctla & T5_TFEN_F);
6044 tp->port = T5_TFPORT_G(ctla);
6045 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
6047 tp->snap_len = TFCAPTUREMAX_G(ctlb);
6048 tp->min_len = TFMINPKTSIZE_G(ctlb);
6049 tp->skip_ofst = TFOFFSET_G(ctla);
6050 tp->skip_len = TFLENGTH_G(ctla);
6052 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
6053 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
6054 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
6056 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6057 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6058 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6063 * t4_pmtx_get_stats - returns the HW stats from PMTX
6064 * @adap: the adapter
6065 * @cnt: where to store the count statistics
6066 * @cycles: where to store the cycle statistics
6068 * Returns performance statistics from PMTX.
6070 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6075 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6076 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6077 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6078 if (is_t4(adap->params.chip)) {
6079 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6081 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6082 PM_TX_DBG_DATA_A, data, 2,
6083 PM_TX_DBG_STAT_MSB_A);
6084 cycles[i] = (((u64)data[0] << 32) | data[1]);
6090 * t4_pmrx_get_stats - returns the HW stats from PMRX
6091 * @adap: the adapter
6092 * @cnt: where to store the count statistics
6093 * @cycles: where to store the cycle statistics
6095 * Returns performance statistics from PMRX.
6097 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6102 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6103 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6104 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6105 if (is_t4(adap->params.chip)) {
6106 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6108 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6109 PM_RX_DBG_DATA_A, data, 2,
6110 PM_RX_DBG_STAT_MSB_A);
6111 cycles[i] = (((u64)data[0] << 32) | data[1]);
6117 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6118 * @adap: the adapter
6119 * @pidx: the port index
6121 * Computes and returns a bitmap indicating which MPS buffer groups are
6122 * associated with the given Port. Bit i is set if buffer group i is
6125 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6128 unsigned int chip_version, nports;
6130 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6131 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6133 switch (chip_version) {
6138 case 2: return 3 << (2 * pidx);
6139 case 4: return 1 << pidx;
6145 case 2: return 1 << (2 * pidx);
6150 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6151 chip_version, nports);
6157 * t4_get_mps_bg_map - return the buffer groups associated with a port
6158 * @adapter: the adapter
6159 * @pidx: the port index
6161 * Returns a bitmap indicating which MPS buffer groups are associated
6162 * with the given Port. Bit i is set if buffer group i is used by the
6165 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6168 unsigned int nports;
6170 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6171 if (pidx >= nports) {
6172 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6177 /* If we've already retrieved/computed this, just return the result.
6179 mps_bg_map = adapter->params.mps_bg_map;
6180 if (mps_bg_map[pidx])
6181 return mps_bg_map[pidx];
6183 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6184 * If we're talking to such Firmware, let it tell us. If the new
6185 * API isn't supported, revert back to old hardcoded way. The value
6186 * obtained from Firmware is encoded in below format:
6188 * val = (( MPSBGMAP[Port 3] << 24 ) |
6189 * ( MPSBGMAP[Port 2] << 16 ) |
6190 * ( MPSBGMAP[Port 1] << 8 ) |
6191 * ( MPSBGMAP[Port 0] << 0 ))
6193 if (adapter->flags & CXGB4_FW_OK) {
6197 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6198 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6199 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6200 0, 1, ¶m, &val);
6204 /* Store the BG Map for all of the Ports in order to
6205 * avoid more calls to the Firmware in the future.
6207 for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6208 mps_bg_map[p] = val & 0xff;
6210 return mps_bg_map[pidx];
6214 /* Either we're not talking to the Firmware or we're dealing with
6215 * older Firmware which doesn't support the new API to get the MPS
6216 * Buffer Group Map. Fall back to computing it ourselves.
6218 mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6219 return mps_bg_map[pidx];
6223 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6224 * @adapter: the adapter
6225 * @pidx: the port index
6227 static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
6229 unsigned int nports;
6233 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6234 if (pidx >= nports) {
6235 CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
6240 /* FW version >= 1.16.44.0 can determine E2C channel map using
6241 * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6243 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6244 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
6245 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6246 0, 1, ¶m, &val);
6248 return (val >> (8 * pidx)) & 0xff;
6254 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6255 * @adapter: the adapter
6256 * @pidx: the port index
6258 * Returns a bitmap indicating which TP Ingress Channels are associated
6259 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6262 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6264 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6265 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6267 if (pidx >= nports) {
6268 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6273 switch (chip_version) {
6276 /* Note that this happens to be the same values as the MPS
6277 * Buffer Group Map for these Chips. But we replicate the code
6278 * here because they're really separate concepts.
6282 case 2: return 3 << (2 * pidx);
6283 case 4: return 1 << pidx;
6290 case 2: return 1 << pidx;
6295 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6296 chip_version, nports);
6301 * t4_get_port_type_description - return Port Type string description
6302 * @port_type: firmware Port Type enumeration
6304 const char *t4_get_port_type_description(enum fw_port_type port_type)
6306 static const char *const port_type_description[] = {
6332 if (port_type < ARRAY_SIZE(port_type_description))
6333 return port_type_description[port_type];
6338 * t4_get_port_stats_offset - collect port stats relative to a previous
6340 * @adap: The adapter
6342 * @stats: Current stats to fill
6343 * @offset: Previous stats snapshot
6345 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6346 struct port_stats *stats,
6347 struct port_stats *offset)
6352 t4_get_port_stats(adap, idx, stats);
6353 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6354 i < (sizeof(struct port_stats) / sizeof(u64));
6360 * t4_get_port_stats - collect port statistics
6361 * @adap: the adapter
6362 * @idx: the port index
6363 * @p: the stats structure to fill
6365 * Collect statistics related to the given port from HW.
6367 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6369 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6370 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6372 #define GET_STAT(name) \
6373 t4_read_reg64(adap, \
6374 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6375 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6376 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6378 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6379 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6380 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6381 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6382 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6383 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6384 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6385 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6386 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6387 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6388 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6389 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6390 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6391 p->tx_drop = GET_STAT(TX_PORT_DROP);
6392 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6393 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6394 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6395 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6396 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6397 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6398 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6399 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6400 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6402 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6403 if (stat_ctl & COUNTPAUSESTATTX_F)
6404 p->tx_frames_64 -= p->tx_pause;
6405 if (stat_ctl & COUNTPAUSEMCTX_F)
6406 p->tx_mcast_frames -= p->tx_pause;
6408 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6409 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6410 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6411 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6412 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6413 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6414 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6415 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6416 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6417 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6418 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6419 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6420 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6421 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6422 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6423 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6424 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6425 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6426 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6427 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6428 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6429 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6430 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6431 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6432 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6433 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6434 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6436 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6437 if (stat_ctl & COUNTPAUSESTATRX_F)
6438 p->rx_frames_64 -= p->rx_pause;
6439 if (stat_ctl & COUNTPAUSEMCRX_F)
6440 p->rx_mcast_frames -= p->rx_pause;
6443 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6444 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6445 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6446 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6447 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6448 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6449 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6450 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6457 * t4_get_lb_stats - collect loopback port statistics
6458 * @adap: the adapter
6459 * @idx: the loopback port index
6460 * @p: the stats structure to fill
6462 * Return HW statistics for the given loopback port.
6464 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6466 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6468 #define GET_STAT(name) \
6469 t4_read_reg64(adap, \
6470 (is_t4(adap->params.chip) ? \
6471 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6472 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6473 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6475 p->octets = GET_STAT(BYTES);
6476 p->frames = GET_STAT(FRAMES);
6477 p->bcast_frames = GET_STAT(BCAST);
6478 p->mcast_frames = GET_STAT(MCAST);
6479 p->ucast_frames = GET_STAT(UCAST);
6480 p->error_frames = GET_STAT(ERROR);
6482 p->frames_64 = GET_STAT(64B);
6483 p->frames_65_127 = GET_STAT(65B_127B);
6484 p->frames_128_255 = GET_STAT(128B_255B);
6485 p->frames_256_511 = GET_STAT(256B_511B);
6486 p->frames_512_1023 = GET_STAT(512B_1023B);
6487 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6488 p->frames_1519_max = GET_STAT(1519B_MAX);
6489 p->drop = GET_STAT(DROP_FRAMES);
6491 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6492 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6493 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6494 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6495 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6496 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6497 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6498 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6504 /* t4_mk_filtdelwr - create a delete filter WR
6505 * @ftid: the filter ID
6506 * @wr: the filter work request to populate
6507 * @qid: ingress queue to receive the delete notification
6509 * Creates a filter work request to delete the supplied filter. If @qid is
6510 * negative the delete notification is suppressed.
6512 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6514 memset(wr, 0, sizeof(*wr));
6515 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6516 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6517 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6518 FW_FILTER_WR_NOREPLY_V(qid < 0));
6519 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6521 wr->rx_chan_rx_rpl_iq =
6522 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6525 #define INIT_CMD(var, cmd, rd_wr) do { \
6526 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6527 FW_CMD_REQUEST_F | \
6528 FW_CMD_##rd_wr##_F); \
6529 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6532 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6536 struct fw_ldst_cmd c;
6538 memset(&c, 0, sizeof(c));
6539 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6540 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6544 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6545 c.u.addrval.addr = cpu_to_be32(addr);
6546 c.u.addrval.val = cpu_to_be32(val);
6548 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6552 * t4_mdio_rd - read a PHY register through MDIO
6553 * @adap: the adapter
6554 * @mbox: mailbox to use for the FW command
6555 * @phy_addr: the PHY address
6556 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6557 * @reg: the register to read
6558 * @valp: where to store the value
6560 * Issues a FW command through the given mailbox to read a PHY register.
6562 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6563 unsigned int mmd, unsigned int reg, u16 *valp)
6567 struct fw_ldst_cmd c;
6569 memset(&c, 0, sizeof(c));
6570 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6571 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6572 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6574 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6575 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6576 FW_LDST_CMD_MMD_V(mmd));
6577 c.u.mdio.raddr = cpu_to_be16(reg);
6579 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6581 *valp = be16_to_cpu(c.u.mdio.rval);
6586 * t4_mdio_wr - write a PHY register through MDIO
6587 * @adap: the adapter
6588 * @mbox: mailbox to use for the FW command
6589 * @phy_addr: the PHY address
6590 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6591 * @reg: the register to write
6592 * @valp: value to write
6594 * Issues a FW command through the given mailbox to write a PHY register.
6596 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6597 unsigned int mmd, unsigned int reg, u16 val)
6600 struct fw_ldst_cmd c;
6602 memset(&c, 0, sizeof(c));
6603 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6604 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6605 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6607 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6608 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6609 FW_LDST_CMD_MMD_V(mmd));
6610 c.u.mdio.raddr = cpu_to_be16(reg);
6611 c.u.mdio.rval = cpu_to_be16(val);
6613 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6617 * t4_sge_decode_idma_state - decode the idma state
6618 * @adap: the adapter
6619 * @state: the state idma is stuck in
6621 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6623 static const char * const t4_decode[] = {
6625 "IDMA_PUSH_MORE_CPL_FIFO",
6626 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6628 "IDMA_PHYSADDR_SEND_PCIEHDR",
6629 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6630 "IDMA_PHYSADDR_SEND_PAYLOAD",
6631 "IDMA_SEND_FIFO_TO_IMSG",
6632 "IDMA_FL_REQ_DATA_FL_PREP",
6633 "IDMA_FL_REQ_DATA_FL",
6635 "IDMA_FL_H_REQ_HEADER_FL",
6636 "IDMA_FL_H_SEND_PCIEHDR",
6637 "IDMA_FL_H_PUSH_CPL_FIFO",
6638 "IDMA_FL_H_SEND_CPL",
6639 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6640 "IDMA_FL_H_SEND_IP_HDR",
6641 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6642 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6643 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6644 "IDMA_FL_D_SEND_PCIEHDR",
6645 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6646 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6647 "IDMA_FL_SEND_PCIEHDR",
6648 "IDMA_FL_PUSH_CPL_FIFO",
6650 "IDMA_FL_SEND_PAYLOAD_FIRST",
6651 "IDMA_FL_SEND_PAYLOAD",
6652 "IDMA_FL_REQ_NEXT_DATA_FL",
6653 "IDMA_FL_SEND_NEXT_PCIEHDR",
6654 "IDMA_FL_SEND_PADDING",
6655 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6656 "IDMA_FL_SEND_FIFO_TO_IMSG",
6657 "IDMA_FL_REQ_DATAFL_DONE",
6658 "IDMA_FL_REQ_HEADERFL_DONE",
6660 static const char * const t5_decode[] = {
6663 "IDMA_PUSH_MORE_CPL_FIFO",
6664 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6665 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6666 "IDMA_PHYSADDR_SEND_PCIEHDR",
6667 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6668 "IDMA_PHYSADDR_SEND_PAYLOAD",
6669 "IDMA_SEND_FIFO_TO_IMSG",
6670 "IDMA_FL_REQ_DATA_FL",
6672 "IDMA_FL_DROP_SEND_INC",
6673 "IDMA_FL_H_REQ_HEADER_FL",
6674 "IDMA_FL_H_SEND_PCIEHDR",
6675 "IDMA_FL_H_PUSH_CPL_FIFO",
6676 "IDMA_FL_H_SEND_CPL",
6677 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6678 "IDMA_FL_H_SEND_IP_HDR",
6679 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6680 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6681 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6682 "IDMA_FL_D_SEND_PCIEHDR",
6683 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6684 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6685 "IDMA_FL_SEND_PCIEHDR",
6686 "IDMA_FL_PUSH_CPL_FIFO",
6688 "IDMA_FL_SEND_PAYLOAD_FIRST",
6689 "IDMA_FL_SEND_PAYLOAD",
6690 "IDMA_FL_REQ_NEXT_DATA_FL",
6691 "IDMA_FL_SEND_NEXT_PCIEHDR",
6692 "IDMA_FL_SEND_PADDING",
6693 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6695 static const char * const t6_decode[] = {
6697 "IDMA_PUSH_MORE_CPL_FIFO",
6698 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6699 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6700 "IDMA_PHYSADDR_SEND_PCIEHDR",
6701 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6702 "IDMA_PHYSADDR_SEND_PAYLOAD",
6703 "IDMA_FL_REQ_DATA_FL",
6705 "IDMA_FL_DROP_SEND_INC",
6706 "IDMA_FL_H_REQ_HEADER_FL",
6707 "IDMA_FL_H_SEND_PCIEHDR",
6708 "IDMA_FL_H_PUSH_CPL_FIFO",
6709 "IDMA_FL_H_SEND_CPL",
6710 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6711 "IDMA_FL_H_SEND_IP_HDR",
6712 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6713 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6714 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6715 "IDMA_FL_D_SEND_PCIEHDR",
6716 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6717 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6718 "IDMA_FL_SEND_PCIEHDR",
6719 "IDMA_FL_PUSH_CPL_FIFO",
6721 "IDMA_FL_SEND_PAYLOAD_FIRST",
6722 "IDMA_FL_SEND_PAYLOAD",
6723 "IDMA_FL_REQ_NEXT_DATA_FL",
6724 "IDMA_FL_SEND_NEXT_PCIEHDR",
6725 "IDMA_FL_SEND_PADDING",
6726 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6728 static const u32 sge_regs[] = {
6729 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6730 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6731 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6733 const char **sge_idma_decode;
6734 int sge_idma_decode_nstates;
6736 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6738 /* Select the right set of decode strings to dump depending on the
6739 * adapter chip type.
6741 switch (chip_version) {
6743 sge_idma_decode = (const char **)t4_decode;
6744 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6748 sge_idma_decode = (const char **)t5_decode;
6749 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6753 sge_idma_decode = (const char **)t6_decode;
6754 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6758 dev_err(adapter->pdev_dev,
6759 "Unsupported chip version %d\n", chip_version);
6763 if (is_t4(adapter->params.chip)) {
6764 sge_idma_decode = (const char **)t4_decode;
6765 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6767 sge_idma_decode = (const char **)t5_decode;
6768 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6771 if (state < sge_idma_decode_nstates)
6772 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6774 CH_WARN(adapter, "idma state %d unknown\n", state);
6776 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6777 CH_WARN(adapter, "SGE register %#x value %#x\n",
6778 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6782 * t4_sge_ctxt_flush - flush the SGE context cache
6783 * @adap: the adapter
6784 * @mbox: mailbox to use for the FW command
6785 * @ctx_type: Egress or Ingress
6787 * Issues a FW command through the given mailbox to flush the
6788 * SGE context cache.
6790 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6794 struct fw_ldst_cmd c;
6796 memset(&c, 0, sizeof(c));
6797 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6798 FW_LDST_ADDRSPC_SGE_EGRC :
6799 FW_LDST_ADDRSPC_SGE_INGC);
6800 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6801 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6803 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6804 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6806 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6811 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6812 * @adap - the adapter
6813 * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6814 * @dbqtimers: SGE Doorbell Queue Timer table
6816 * Reads the SGE Doorbell Queue Timer values into the provided table.
6817 * Returns 0 on success (Firmware and Hardware support this feature),
6818 * an error on failure.
6820 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6823 int ret, dbqtimerix;
6827 while (dbqtimerix < ndbqtimers) {
6829 u32 params[7], vals[7];
6831 nparams = ndbqtimers - dbqtimerix;
6832 if (nparams > ARRAY_SIZE(params))
6833 nparams = ARRAY_SIZE(params);
6835 for (param = 0; param < nparams; param++)
6837 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6838 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
6839 FW_PARAMS_PARAM_Y_V(dbqtimerix + param));
6840 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6841 nparams, params, vals);
6845 for (param = 0; param < nparams; param++)
6846 dbqtimers[dbqtimerix++] = vals[param];
6852 * t4_fw_hello - establish communication with FW
6853 * @adap: the adapter
6854 * @mbox: mailbox to use for the FW command
6855 * @evt_mbox: mailbox to receive async FW events
6856 * @master: specifies the caller's willingness to be the device master
6857 * @state: returns the current device state (if non-NULL)
6859 * Issues a command to establish communication with FW. Returns either
6860 * an error (negative integer) or the mailbox of the Master PF.
6862 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6863 enum dev_master master, enum dev_state *state)
6866 struct fw_hello_cmd c;
6868 unsigned int master_mbox;
6869 int retries = FW_CMD_HELLO_RETRIES;
6872 memset(&c, 0, sizeof(c));
6873 INIT_CMD(c, HELLO, WRITE);
6874 c.err_to_clearinit = cpu_to_be32(
6875 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6876 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6877 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6878 mbox : FW_HELLO_CMD_MBMASTER_M) |
6879 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6880 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6881 FW_HELLO_CMD_CLEARINIT_F);
6884 * Issue the HELLO command to the firmware. If it's not successful
6885 * but indicates that we got a "busy" or "timeout" condition, retry
6886 * the HELLO until we exhaust our retry limit. If we do exceed our
6887 * retry limit, check to see if the firmware left us any error
6888 * information and report that if so.
6890 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6892 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6894 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6895 t4_report_fw_error(adap);
6899 v = be32_to_cpu(c.err_to_clearinit);
6900 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6902 if (v & FW_HELLO_CMD_ERR_F)
6903 *state = DEV_STATE_ERR;
6904 else if (v & FW_HELLO_CMD_INIT_F)
6905 *state = DEV_STATE_INIT;
6907 *state = DEV_STATE_UNINIT;
6911 * If we're not the Master PF then we need to wait around for the
6912 * Master PF Driver to finish setting up the adapter.
6914 * Note that we also do this wait if we're a non-Master-capable PF and
6915 * there is no current Master PF; a Master PF may show up momentarily
6916 * and we wouldn't want to fail pointlessly. (This can happen when an
6917 * OS loads lots of different drivers rapidly at the same time). In
6918 * this case, the Master PF returned by the firmware will be
6919 * PCIE_FW_MASTER_M so the test below will work ...
6921 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6922 master_mbox != mbox) {
6923 int waiting = FW_CMD_HELLO_TIMEOUT;
6926 * Wait for the firmware to either indicate an error or
6927 * initialized state. If we see either of these we bail out
6928 * and report the issue to the caller. If we exhaust the
6929 * "hello timeout" and we haven't exhausted our retries, try
6930 * again. Otherwise bail with a timeout error.
6939 * If neither Error nor Initialized are indicated
6940 * by the firmware keep waiting till we exhaust our
6941 * timeout ... and then retry if we haven't exhausted
6944 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6945 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6956 * We either have an Error or Initialized condition
6957 * report errors preferentially.
6960 if (pcie_fw & PCIE_FW_ERR_F)
6961 *state = DEV_STATE_ERR;
6962 else if (pcie_fw & PCIE_FW_INIT_F)
6963 *state = DEV_STATE_INIT;
6967 * If we arrived before a Master PF was selected and
6968 * there's not a valid Master PF, grab its identity
6971 if (master_mbox == PCIE_FW_MASTER_M &&
6972 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6973 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6982 * t4_fw_bye - end communication with FW
6983 * @adap: the adapter
6984 * @mbox: mailbox to use for the FW command
6986 * Issues a command to terminate communication with FW.
6988 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6990 struct fw_bye_cmd c;
6992 memset(&c, 0, sizeof(c));
6993 INIT_CMD(c, BYE, WRITE);
6994 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6998 * t4_init_cmd - ask FW to initialize the device
6999 * @adap: the adapter
7000 * @mbox: mailbox to use for the FW command
7002 * Issues a command to FW to partially initialize the device. This
7003 * performs initialization that generally doesn't depend on user input.
7005 int t4_early_init(struct adapter *adap, unsigned int mbox)
7007 struct fw_initialize_cmd c;
7009 memset(&c, 0, sizeof(c));
7010 INIT_CMD(c, INITIALIZE, WRITE);
7011 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7015 * t4_fw_reset - issue a reset to FW
7016 * @adap: the adapter
7017 * @mbox: mailbox to use for the FW command
7018 * @reset: specifies the type of reset to perform
7020 * Issues a reset command of the specified type to FW.
7022 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7024 struct fw_reset_cmd c;
7026 memset(&c, 0, sizeof(c));
7027 INIT_CMD(c, RESET, WRITE);
7028 c.val = cpu_to_be32(reset);
7029 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7033 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7034 * @adap: the adapter
7035 * @mbox: mailbox to use for the FW RESET command (if desired)
7036 * @force: force uP into RESET even if FW RESET command fails
7038 * Issues a RESET command to firmware (if desired) with a HALT indication
7039 * and then puts the microprocessor into RESET state. The RESET command
7040 * will only be issued if a legitimate mailbox is provided (mbox <=
7041 * PCIE_FW_MASTER_M).
7043 * This is generally used in order for the host to safely manipulate the
7044 * adapter without fear of conflicting with whatever the firmware might
7045 * be doing. The only way out of this state is to RESTART the firmware
7048 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7053 * If a legitimate mailbox is provided, issue a RESET command
7054 * with a HALT indication.
7056 if (mbox <= PCIE_FW_MASTER_M) {
7057 struct fw_reset_cmd c;
7059 memset(&c, 0, sizeof(c));
7060 INIT_CMD(c, RESET, WRITE);
7061 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
7062 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
7063 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7067 * Normally we won't complete the operation if the firmware RESET
7068 * command fails but if our caller insists we'll go ahead and put the
7069 * uP into RESET. This can be useful if the firmware is hung or even
7070 * missing ... We'll have to take the risk of putting the uP into
7071 * RESET without the cooperation of firmware in that case.
7073 * We also force the firmware's HALT flag to be on in case we bypassed
7074 * the firmware RESET command above or we're dealing with old firmware
7075 * which doesn't have the HALT capability. This will serve as a flag
7076 * for the incoming firmware to know that it's coming out of a HALT
7077 * rather than a RESET ... if it's new enough to understand that ...
7079 if (ret == 0 || force) {
7080 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7081 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7086 * And we always return the result of the firmware RESET command
7087 * even when we force the uP into RESET ...
7093 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7094 * @adap: the adapter
7095 * @reset: if we want to do a RESET to restart things
7097 * Restart firmware previously halted by t4_fw_halt(). On successful
7098 * return the previous PF Master remains as the new PF Master and there
7099 * is no need to issue a new HELLO command, etc.
7101 * We do this in two ways:
7103 * 1. If we're dealing with newer firmware we'll simply want to take
7104 * the chip's microprocessor out of RESET. This will cause the
7105 * firmware to start up from its start vector. And then we'll loop
7106 * until the firmware indicates it's started again (PCIE_FW.HALT
7107 * reset to 0) or we timeout.
7109 * 2. If we're dealing with older firmware then we'll need to RESET
7110 * the chip since older firmware won't recognize the PCIE_FW.HALT
7111 * flag and automatically RESET itself on startup.
7113 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7117 * Since we're directing the RESET instead of the firmware
7118 * doing it automatically, we need to clear the PCIE_FW.HALT
7121 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7124 * If we've been given a valid mailbox, first try to get the
7125 * firmware to do the RESET. If that works, great and we can
7126 * return success. Otherwise, if we haven't been given a
7127 * valid mailbox or the RESET command failed, fall back to
7128 * hitting the chip with a hammer.
7130 if (mbox <= PCIE_FW_MASTER_M) {
7131 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7133 if (t4_fw_reset(adap, mbox,
7134 PIORST_F | PIORSTMODE_F) == 0)
7138 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7143 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7144 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7145 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7156 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7157 * @adap: the adapter
7158 * @mbox: mailbox to use for the FW RESET command (if desired)
7159 * @fw_data: the firmware image to write
7161 * @force: force upgrade even if firmware doesn't cooperate
7163 * Perform all of the steps necessary for upgrading an adapter's
7164 * firmware image. Normally this requires the cooperation of the
7165 * existing firmware in order to halt all existing activities
7166 * but if an invalid mailbox token is passed in we skip that step
7167 * (though we'll still put the adapter microprocessor into RESET in
7170 * On successful return the new firmware will have been loaded and
7171 * the adapter will have been fully RESET losing all previous setup
7172 * state. On unsuccessful return the adapter may be completely hosed ...
7173 * positive errno indicates that the adapter is ~probably~ intact, a
7174 * negative errno indicates that things are looking bad ...
7176 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7177 const u8 *fw_data, unsigned int size, int force)
7179 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7182 if (!t4_fw_matches_chip(adap, fw_hdr))
7185 /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7186 * set wont be sent when we are flashing FW.
7188 adap->flags &= ~CXGB4_FW_OK;
7190 ret = t4_fw_halt(adap, mbox, force);
7191 if (ret < 0 && !force)
7194 ret = t4_load_fw(adap, fw_data, size);
7199 * If there was a Firmware Configuration File stored in FLASH,
7200 * there's a good chance that it won't be compatible with the new
7201 * Firmware. In order to prevent difficult to diagnose adapter
7202 * initialization issues, we clear out the Firmware Configuration File
7203 * portion of the FLASH . The user will need to re-FLASH a new
7204 * Firmware Configuration File which is compatible with the new
7205 * Firmware if that's desired.
7207 (void)t4_load_cfg(adap, NULL, 0);
7210 * Older versions of the firmware don't understand the new
7211 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7212 * restart. So for newly loaded older firmware we'll have to do the
7213 * RESET for it so it starts up on a clean slate. We can tell if
7214 * the newly loaded firmware will handle this right by checking
7215 * its header flags to see if it advertises the capability.
7217 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7218 ret = t4_fw_restart(adap, mbox, reset);
7220 /* Grab potentially new Firmware Device Log parameters so we can see
7221 * how healthy the new Firmware is. It's okay to contact the new
7222 * Firmware for these parameters even though, as far as it's
7223 * concerned, we've never said "HELLO" to it ...
7225 (void)t4_init_devlog_params(adap);
7227 adap->flags |= CXGB4_FW_OK;
7232 * t4_fl_pkt_align - return the fl packet alignment
7233 * @adap: the adapter
7235 * T4 has a single field to specify the packing and padding boundary.
7236 * T5 onwards has separate fields for this and hence the alignment for
7237 * next packet offset is maximum of these two.
7240 int t4_fl_pkt_align(struct adapter *adap)
7242 u32 sge_control, sge_control2;
7243 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7245 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7247 /* T4 uses a single control field to specify both the PCIe Padding and
7248 * Packing Boundary. T5 introduced the ability to specify these
7249 * separately. The actual Ingress Packet Data alignment boundary
7250 * within Packed Buffer Mode is the maximum of these two
7251 * specifications. (Note that it makes no real practical sense to
7252 * have the Padding Boundary be larger than the Packing Boundary but you
7253 * could set the chip up that way and, in fact, legacy T4 code would
7254 * end doing this because it would initialize the Padding Boundary and
7255 * leave the Packing Boundary initialized to 0 (16 bytes).)
7256 * Padding Boundary values in T6 starts from 8B,
7257 * where as it is 32B for T4 and T5.
7259 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7260 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7262 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7264 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7266 fl_align = ingpadboundary;
7267 if (!is_t4(adap->params.chip)) {
7268 /* T5 has a weird interpretation of one of the PCIe Packing
7269 * Boundary values. No idea why ...
7271 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7272 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7273 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7274 ingpackboundary = 16;
7276 ingpackboundary = 1 << (ingpackboundary +
7277 INGPACKBOUNDARY_SHIFT_X);
7279 fl_align = max(ingpadboundary, ingpackboundary);
7285 * t4_fixup_host_params - fix up host-dependent parameters
7286 * @adap: the adapter
7287 * @page_size: the host's Base Page Size
7288 * @cache_line_size: the host's Cache Line Size
7290 * Various registers in T4 contain values which are dependent on the
7291 * host's Base Page and Cache Line Sizes. This function will fix all of
7292 * those registers with the appropriate values as passed in ...
7294 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7295 unsigned int cache_line_size)
7297 unsigned int page_shift = fls(page_size) - 1;
7298 unsigned int sge_hps = page_shift - 10;
7299 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7300 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7301 unsigned int fl_align_log = fls(fl_align) - 1;
7303 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7304 HOSTPAGESIZEPF0_V(sge_hps) |
7305 HOSTPAGESIZEPF1_V(sge_hps) |
7306 HOSTPAGESIZEPF2_V(sge_hps) |
7307 HOSTPAGESIZEPF3_V(sge_hps) |
7308 HOSTPAGESIZEPF4_V(sge_hps) |
7309 HOSTPAGESIZEPF5_V(sge_hps) |
7310 HOSTPAGESIZEPF6_V(sge_hps) |
7311 HOSTPAGESIZEPF7_V(sge_hps));
7313 if (is_t4(adap->params.chip)) {
7314 t4_set_reg_field(adap, SGE_CONTROL_A,
7315 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7316 EGRSTATUSPAGESIZE_F,
7317 INGPADBOUNDARY_V(fl_align_log -
7318 INGPADBOUNDARY_SHIFT_X) |
7319 EGRSTATUSPAGESIZE_V(stat_len != 64));
7321 unsigned int pack_align;
7322 unsigned int ingpad, ingpack;
7324 /* T5 introduced the separation of the Free List Padding and
7325 * Packing Boundaries. Thus, we can select a smaller Padding
7326 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7327 * Bandwidth, and use a Packing Boundary which is large enough
7328 * to avoid false sharing between CPUs, etc.
7330 * For the PCI Link, the smaller the Padding Boundary the
7331 * better. For the Memory Controller, a smaller Padding
7332 * Boundary is better until we cross under the Memory Line
7333 * Size (the minimum unit of transfer to/from Memory). If we
7334 * have a Padding Boundary which is smaller than the Memory
7335 * Line Size, that'll involve a Read-Modify-Write cycle on the
7336 * Memory Controller which is never good.
7339 /* We want the Packing Boundary to be based on the Cache Line
7340 * Size in order to help avoid False Sharing performance
7341 * issues between CPUs, etc. We also want the Packing
7342 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7343 * get best performance when the Packing Boundary is a
7344 * multiple of the Maximum Payload Size.
7346 pack_align = fl_align;
7347 if (pci_is_pcie(adap->pdev)) {
7348 unsigned int mps, mps_log;
7351 /* The PCIe Device Control Maximum Payload Size field
7352 * [bits 7:5] encodes sizes as powers of 2 starting at
7355 pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7357 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7359 if (mps > pack_align)
7363 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7364 * value for the Packing Boundary. This corresponds to 16
7365 * bytes instead of the expected 32 bytes. So if we want 32
7366 * bytes, the best we can really do is 64 bytes ...
7368 if (pack_align <= 16) {
7369 ingpack = INGPACKBOUNDARY_16B_X;
7371 } else if (pack_align == 32) {
7372 ingpack = INGPACKBOUNDARY_64B_X;
7375 unsigned int pack_align_log = fls(pack_align) - 1;
7377 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7378 fl_align = pack_align;
7381 /* Use the smallest Ingress Padding which isn't smaller than
7382 * the Memory Controller Read/Write Size. We'll take that as
7383 * being 8 bytes since we don't know of any system with a
7384 * wider Memory Controller Bus Width.
7386 if (is_t5(adap->params.chip))
7387 ingpad = INGPADBOUNDARY_32B_X;
7389 ingpad = T6_INGPADBOUNDARY_8B_X;
7391 t4_set_reg_field(adap, SGE_CONTROL_A,
7392 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7393 EGRSTATUSPAGESIZE_F,
7394 INGPADBOUNDARY_V(ingpad) |
7395 EGRSTATUSPAGESIZE_V(stat_len != 64));
7396 t4_set_reg_field(adap, SGE_CONTROL2_A,
7397 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7398 INGPACKBOUNDARY_V(ingpack));
7401 * Adjust various SGE Free List Host Buffer Sizes.
7403 * This is something of a crock since we're using fixed indices into
7404 * the array which are also known by the sge.c code and the T4
7405 * Firmware Configuration File. We need to come up with a much better
7406 * approach to managing this array. For now, the first four entries
7411 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7412 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7414 * For the single-MTU buffers in unpacked mode we need to include
7415 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7416 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7417 * Padding boundary. All of these are accommodated in the Factory
7418 * Default Firmware Configuration File but we need to adjust it for
7419 * this host's cache line size.
7421 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7422 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7423 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7425 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7426 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7429 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7435 * t4_fw_initialize - ask FW to initialize the device
7436 * @adap: the adapter
7437 * @mbox: mailbox to use for the FW command
7439 * Issues a command to FW to partially initialize the device. This
7440 * performs initialization that generally doesn't depend on user input.
7442 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7444 struct fw_initialize_cmd c;
7446 memset(&c, 0, sizeof(c));
7447 INIT_CMD(c, INITIALIZE, WRITE);
7448 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7452 * t4_query_params_rw - query FW or device parameters
7453 * @adap: the adapter
7454 * @mbox: mailbox to use for the FW command
7457 * @nparams: the number of parameters
7458 * @params: the parameter names
7459 * @val: the parameter values
7460 * @rw: Write and read flag
7461 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7463 * Reads the value of FW or device parameters. Up to 7 parameters can be
7466 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7467 unsigned int vf, unsigned int nparams, const u32 *params,
7468 u32 *val, int rw, bool sleep_ok)
7471 struct fw_params_cmd c;
7472 __be32 *p = &c.param[0].mnem;
7477 memset(&c, 0, sizeof(c));
7478 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7479 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7480 FW_PARAMS_CMD_PFN_V(pf) |
7481 FW_PARAMS_CMD_VFN_V(vf));
7482 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7484 for (i = 0; i < nparams; i++) {
7485 *p++ = cpu_to_be32(*params++);
7487 *p = cpu_to_be32(*(val + i));
7491 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7493 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7494 *val++ = be32_to_cpu(*p);
7498 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7499 unsigned int vf, unsigned int nparams, const u32 *params,
7502 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7506 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7507 unsigned int vf, unsigned int nparams, const u32 *params,
7510 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7515 * t4_set_params_timeout - sets FW or device parameters
7516 * @adap: the adapter
7517 * @mbox: mailbox to use for the FW command
7520 * @nparams: the number of parameters
7521 * @params: the parameter names
7522 * @val: the parameter values
7523 * @timeout: the timeout time
7525 * Sets the value of FW or device parameters. Up to 7 parameters can be
7526 * specified at once.
7528 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7529 unsigned int pf, unsigned int vf,
7530 unsigned int nparams, const u32 *params,
7531 const u32 *val, int timeout)
7533 struct fw_params_cmd c;
7534 __be32 *p = &c.param[0].mnem;
7539 memset(&c, 0, sizeof(c));
7540 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7541 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7542 FW_PARAMS_CMD_PFN_V(pf) |
7543 FW_PARAMS_CMD_VFN_V(vf));
7544 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7547 *p++ = cpu_to_be32(*params++);
7548 *p++ = cpu_to_be32(*val++);
7551 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7555 * t4_set_params - sets FW or device parameters
7556 * @adap: the adapter
7557 * @mbox: mailbox to use for the FW command
7560 * @nparams: the number of parameters
7561 * @params: the parameter names
7562 * @val: the parameter values
7564 * Sets the value of FW or device parameters. Up to 7 parameters can be
7565 * specified at once.
7567 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7568 unsigned int vf, unsigned int nparams, const u32 *params,
7571 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7572 FW_CMD_MAX_TIMEOUT);
7576 * t4_cfg_pfvf - configure PF/VF resource limits
7577 * @adap: the adapter
7578 * @mbox: mailbox to use for the FW command
7579 * @pf: the PF being configured
7580 * @vf: the VF being configured
7581 * @txq: the max number of egress queues
7582 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7583 * @rxqi: the max number of interrupt-capable ingress queues
7584 * @rxq: the max number of interruptless ingress queues
7585 * @tc: the PCI traffic class
7586 * @vi: the max number of virtual interfaces
7587 * @cmask: the channel access rights mask for the PF/VF
7588 * @pmask: the port access rights mask for the PF/VF
7589 * @nexact: the maximum number of exact MPS filters
7590 * @rcaps: read capabilities
7591 * @wxcaps: write/execute capabilities
7593 * Configures resource limits and capabilities for a physical or virtual
7596 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7597 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7598 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7599 unsigned int vi, unsigned int cmask, unsigned int pmask,
7600 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7602 struct fw_pfvf_cmd c;
7604 memset(&c, 0, sizeof(c));
7605 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7606 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7607 FW_PFVF_CMD_VFN_V(vf));
7608 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7609 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7610 FW_PFVF_CMD_NIQ_V(rxq));
7611 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7612 FW_PFVF_CMD_PMASK_V(pmask) |
7613 FW_PFVF_CMD_NEQ_V(txq));
7614 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7615 FW_PFVF_CMD_NVI_V(vi) |
7616 FW_PFVF_CMD_NEXACTF_V(nexact));
7617 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7618 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7619 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7620 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7624 * t4_alloc_vi - allocate a virtual interface
7625 * @adap: the adapter
7626 * @mbox: mailbox to use for the FW command
7627 * @port: physical port associated with the VI
7628 * @pf: the PF owning the VI
7629 * @vf: the VF owning the VI
7630 * @nmac: number of MAC addresses needed (1 to 5)
7631 * @mac: the MAC addresses of the VI
7632 * @rss_size: size of RSS table slice associated with this VI
7634 * Allocates a virtual interface for the given physical port. If @mac is
7635 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7636 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7637 * stored consecutively so the space needed is @nmac * 6 bytes.
7638 * Returns a negative error number or the non-negative VI id.
7640 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7641 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7642 unsigned int *rss_size, u8 *vivld, u8 *vin)
7647 memset(&c, 0, sizeof(c));
7648 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7649 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7650 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7651 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7652 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7655 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7660 memcpy(mac, c.mac, sizeof(c.mac));
7663 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7666 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7669 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7672 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7676 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7679 *vivld = FW_VI_CMD_VFVLD_G(be32_to_cpu(c.alloc_to_len16));
7682 *vin = FW_VI_CMD_VIN_G(be32_to_cpu(c.alloc_to_len16));
7684 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7688 * t4_free_vi - free a virtual interface
7689 * @adap: the adapter
7690 * @mbox: mailbox to use for the FW command
7691 * @pf: the PF owning the VI
7692 * @vf: the VF owning the VI
7693 * @viid: virtual interface identifiler
7695 * Free a previously allocated virtual interface.
7697 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7698 unsigned int vf, unsigned int viid)
7702 memset(&c, 0, sizeof(c));
7703 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7706 FW_VI_CMD_PFN_V(pf) |
7707 FW_VI_CMD_VFN_V(vf));
7708 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7709 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7711 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7715 * t4_set_rxmode - set Rx properties of a virtual interface
7716 * @adap: the adapter
7717 * @mbox: mailbox to use for the FW command
7719 * @mtu: the new MTU or -1
7720 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7721 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7722 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7723 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7724 * @sleep_ok: if true we may sleep while awaiting command completion
7726 * Sets Rx properties of a virtual interface.
7728 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7729 int mtu, int promisc, int all_multi, int bcast, int vlanex,
7732 struct fw_vi_rxmode_cmd c;
7734 /* convert to FW values */
7736 mtu = FW_RXMODE_MTU_NO_CHG;
7738 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7740 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7742 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7744 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7746 memset(&c, 0, sizeof(c));
7747 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7748 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7749 FW_VI_RXMODE_CMD_VIID_V(viid));
7750 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7752 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7753 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7754 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7755 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7756 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7757 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7761 * t4_free_encap_mac_filt - frees MPS entry at given index
7762 * @adap: the adapter
7764 * @idx: index of MPS entry to be freed
7765 * @sleep_ok: call is allowed to sleep
7767 * Frees the MPS entry at supplied index
7769 * Returns a negative error number or zero on success
7771 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7772 int idx, bool sleep_ok)
7774 struct fw_vi_mac_exact *p;
7775 u8 addr[] = {0, 0, 0, 0, 0, 0};
7776 struct fw_vi_mac_cmd c;
7780 memset(&c, 0, sizeof(c));
7781 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7782 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7784 FW_VI_MAC_CMD_VIID_V(viid));
7785 exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7786 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7790 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7791 FW_VI_MAC_CMD_IDX_V(idx));
7792 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7793 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7798 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7799 * @adap: the adapter
7801 * @addr: the MAC address
7803 * @idx: index of the entry in mps tcam
7804 * @lookup_type: MAC address for inner (1) or outer (0) header
7805 * @port_id: the port index
7806 * @sleep_ok: call is allowed to sleep
7808 * Removes the mac entry at the specified index using raw mac interface.
7810 * Returns a negative error number on failure.
7812 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7813 const u8 *addr, const u8 *mask, unsigned int idx,
7814 u8 lookup_type, u8 port_id, bool sleep_ok)
7816 struct fw_vi_mac_cmd c;
7817 struct fw_vi_mac_raw *p = &c.u.raw;
7820 memset(&c, 0, sizeof(c));
7821 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7822 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7824 FW_VI_MAC_CMD_VIID_V(viid));
7825 val = FW_CMD_LEN16_V(1) |
7826 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7827 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7828 FW_CMD_LEN16_V(val));
7830 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7831 FW_VI_MAC_ID_BASED_FREE);
7833 /* Lookup Type. Outer header: 0, Inner header: 1 */
7834 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7835 DATAPORTNUM_V(port_id));
7836 /* Lookup mask and port mask */
7837 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7838 DATAPORTNUM_V(DATAPORTNUM_M));
7840 /* Copy the address and the mask */
7841 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7842 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7844 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7848 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7849 * @adap: the adapter
7851 * @mac: the MAC address
7853 * @vni: the VNI id for the tunnel protocol
7854 * @vni_mask: mask for the VNI id
7855 * @dip_hit: to enable DIP match for the MPS entry
7856 * @lookup_type: MAC address for inner (1) or outer (0) header
7857 * @sleep_ok: call is allowed to sleep
7859 * Allocates an MPS entry with specified MAC address and VNI value.
7861 * Returns a negative error number or the allocated index for this mac.
7863 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7864 const u8 *addr, const u8 *mask, unsigned int vni,
7865 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7868 struct fw_vi_mac_cmd c;
7869 struct fw_vi_mac_vni *p = c.u.exact_vni;
7873 memset(&c, 0, sizeof(c));
7874 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7875 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7876 FW_VI_MAC_CMD_VIID_V(viid));
7877 val = FW_CMD_LEN16_V(1) |
7878 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7879 c.freemacs_to_len16 = cpu_to_be32(val);
7880 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7881 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7882 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7883 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7885 p->lookup_type_to_vni =
7886 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7887 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7888 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7889 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7890 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7892 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7897 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7898 * @adap: the adapter
7900 * @mac: the MAC address
7902 * @idx: index at which to add this entry
7903 * @port_id: the port index
7904 * @lookup_type: MAC address for inner (1) or outer (0) header
7905 * @sleep_ok: call is allowed to sleep
7907 * Adds the mac entry at the specified index using raw mac interface.
7909 * Returns a negative error number or the allocated index for this mac.
7911 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7912 const u8 *addr, const u8 *mask, unsigned int idx,
7913 u8 lookup_type, u8 port_id, bool sleep_ok)
7916 struct fw_vi_mac_cmd c;
7917 struct fw_vi_mac_raw *p = &c.u.raw;
7920 memset(&c, 0, sizeof(c));
7921 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7922 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7923 FW_VI_MAC_CMD_VIID_V(viid));
7924 val = FW_CMD_LEN16_V(1) |
7925 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7926 c.freemacs_to_len16 = cpu_to_be32(val);
7928 /* Specify that this is an inner mac address */
7929 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7931 /* Lookup Type. Outer header: 0, Inner header: 1 */
7932 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7933 DATAPORTNUM_V(port_id));
7934 /* Lookup mask and port mask */
7935 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7936 DATAPORTNUM_V(DATAPORTNUM_M));
7938 /* Copy the address and the mask */
7939 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7940 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7942 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7944 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7953 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7954 * @adap: the adapter
7955 * @mbox: mailbox to use for the FW command
7957 * @free: if true any existing filters for this VI id are first removed
7958 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7959 * @addr: the MAC address(es)
7960 * @idx: where to store the index of each allocated filter
7961 * @hash: pointer to hash address filter bitmap
7962 * @sleep_ok: call is allowed to sleep
7964 * Allocates an exact-match filter for each of the supplied addresses and
7965 * sets it to the corresponding address. If @idx is not %NULL it should
7966 * have at least @naddr entries, each of which will be set to the index of
7967 * the filter allocated for the corresponding MAC address. If a filter
7968 * could not be allocated for an address its index is set to 0xffff.
7969 * If @hash is not %NULL addresses that fail to allocate an exact filter
7970 * are hashed and update the hash filter bitmap pointed at by @hash.
7972 * Returns a negative error number or the number of filters allocated.
7974 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7975 unsigned int viid, bool free, unsigned int naddr,
7976 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7978 int offset, ret = 0;
7979 struct fw_vi_mac_cmd c;
7980 unsigned int nfilters = 0;
7981 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7982 unsigned int rem = naddr;
7984 if (naddr > max_naddr)
7987 for (offset = 0; offset < naddr ; /**/) {
7988 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7989 rem : ARRAY_SIZE(c.u.exact));
7990 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7991 u.exact[fw_naddr]), 16);
7992 struct fw_vi_mac_exact *p;
7995 memset(&c, 0, sizeof(c));
7996 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7999 FW_CMD_EXEC_V(free) |
8000 FW_VI_MAC_CMD_VIID_V(viid));
8001 c.freemacs_to_len16 =
8002 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
8003 FW_CMD_LEN16_V(len16));
8005 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8007 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8008 FW_VI_MAC_CMD_IDX_V(
8009 FW_VI_MAC_ADD_MAC));
8010 memcpy(p->macaddr, addr[offset + i],
8011 sizeof(p->macaddr));
8014 /* It's okay if we run out of space in our MAC address arena.
8015 * Some of the addresses we submit may get stored so we need
8016 * to run through the reply to see what the results were ...
8018 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8019 if (ret && ret != -FW_ENOMEM)
8022 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8023 u16 index = FW_VI_MAC_CMD_IDX_G(
8024 be16_to_cpu(p->valid_to_idx));
8027 idx[offset + i] = (index >= max_naddr ?
8029 if (index < max_naddr)
8033 hash_mac_addr(addr[offset + i]));
8041 if (ret == 0 || ret == -FW_ENOMEM)
8047 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8048 * @adap: the adapter
8049 * @mbox: mailbox to use for the FW command
8051 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8052 * @addr: the MAC address(es)
8053 * @sleep_ok: call is allowed to sleep
8055 * Frees the exact-match filter for each of the supplied addresses
8057 * Returns a negative error number or the number of filters freed.
8059 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8060 unsigned int viid, unsigned int naddr,
8061 const u8 **addr, bool sleep_ok)
8063 int offset, ret = 0;
8064 struct fw_vi_mac_cmd c;
8065 unsigned int nfilters = 0;
8066 unsigned int max_naddr = is_t4(adap->params.chip) ?
8067 NUM_MPS_CLS_SRAM_L_INSTANCES :
8068 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8069 unsigned int rem = naddr;
8071 if (naddr > max_naddr)
8074 for (offset = 0; offset < (int)naddr ; /**/) {
8075 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8077 : ARRAY_SIZE(c.u.exact));
8078 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8079 u.exact[fw_naddr]), 16);
8080 struct fw_vi_mac_exact *p;
8083 memset(&c, 0, sizeof(c));
8084 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8088 FW_VI_MAC_CMD_VIID_V(viid));
8089 c.freemacs_to_len16 =
8090 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8091 FW_CMD_LEN16_V(len16));
8093 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8094 p->valid_to_idx = cpu_to_be16(
8095 FW_VI_MAC_CMD_VALID_F |
8096 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
8097 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8100 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8104 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8105 u16 index = FW_VI_MAC_CMD_IDX_G(
8106 be16_to_cpu(p->valid_to_idx));
8108 if (index < max_naddr)
8122 * t4_change_mac - modifies the exact-match filter for a MAC address
8123 * @adap: the adapter
8124 * @mbox: mailbox to use for the FW command
8126 * @idx: index of existing filter for old value of MAC address, or -1
8127 * @addr: the new MAC address value
8128 * @persist: whether a new MAC allocation should be persistent
8129 * @add_smt: if true also add the address to the HW SMT
8131 * Modifies an exact-match filter and sets it to the new MAC address.
8132 * Note that in general it is not possible to modify the value of a given
8133 * filter so the generic way to modify an address filter is to free the one
8134 * being used by the old address value and allocate a new filter for the
8135 * new address value. @idx can be -1 if the address is a new addition.
8137 * Returns a negative error number or the index of the filter with the new
8140 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8141 int idx, const u8 *addr, bool persist, u8 *smt_idx)
8144 struct fw_vi_mac_cmd c;
8145 struct fw_vi_mac_exact *p = c.u.exact;
8146 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8148 if (idx < 0) /* new allocation */
8149 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8150 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8152 memset(&c, 0, sizeof(c));
8153 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8154 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8155 FW_VI_MAC_CMD_VIID_V(viid));
8156 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
8157 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8158 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
8159 FW_VI_MAC_CMD_IDX_V(idx));
8160 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8162 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8164 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8165 if (ret >= max_mac_addr)
8168 if (adap->params.viid_smt_extn_support) {
8169 *smt_idx = FW_VI_MAC_CMD_SMTID_G
8170 (be32_to_cpu(c.op_to_viid));
8172 /* In T4/T5, SMT contains 256 SMAC entries
8173 * organized in 128 rows of 2 entries each.
8174 * In T6, SMT contains 256 SMAC entries in
8177 if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8179 *smt_idx = (viid & FW_VIID_VIN_M) << 1;
8181 *smt_idx = (viid & FW_VIID_VIN_M);
8189 * t4_set_addr_hash - program the MAC inexact-match hash filter
8190 * @adap: the adapter
8191 * @mbox: mailbox to use for the FW command
8193 * @ucast: whether the hash filter should also match unicast addresses
8194 * @vec: the value to be written to the hash filter
8195 * @sleep_ok: call is allowed to sleep
8197 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8199 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8200 bool ucast, u64 vec, bool sleep_ok)
8202 struct fw_vi_mac_cmd c;
8204 memset(&c, 0, sizeof(c));
8205 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8206 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8207 FW_VI_ENABLE_CMD_VIID_V(viid));
8208 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8209 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8211 c.u.hash.hashvec = cpu_to_be64(vec);
8212 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8216 * t4_enable_vi_params - enable/disable a virtual interface
8217 * @adap: the adapter
8218 * @mbox: mailbox to use for the FW command
8220 * @rx_en: 1=enable Rx, 0=disable Rx
8221 * @tx_en: 1=enable Tx, 0=disable Tx
8222 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8224 * Enables/disables a virtual interface. Note that setting DCB Enable
8225 * only makes sense when enabling a Virtual Interface ...
8227 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8228 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8230 struct fw_vi_enable_cmd c;
8232 memset(&c, 0, sizeof(c));
8233 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8234 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8235 FW_VI_ENABLE_CMD_VIID_V(viid));
8236 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8237 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8238 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8240 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8244 * t4_enable_vi - enable/disable a virtual interface
8245 * @adap: the adapter
8246 * @mbox: mailbox to use for the FW command
8248 * @rx_en: 1=enable Rx, 0=disable Rx
8249 * @tx_en: 1=enable Tx, 0=disable Tx
8251 * Enables/disables a virtual interface.
8253 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8254 bool rx_en, bool tx_en)
8256 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8260 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8261 * @adap: the adapter
8262 * @mbox: mailbox to use for the FW command
8263 * @pi: the Port Information structure
8264 * @rx_en: 1=enable Rx, 0=disable Rx
8265 * @tx_en: 1=enable Tx, 0=disable Tx
8266 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8268 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8269 * Enable only makes sense when enabling a Virtual Interface ...
8270 * If the Virtual Interface enable/disable operation is successful,
8271 * we notify the OS-specific code of a potential Link Status change
8272 * via the OS Contract API t4_os_link_changed().
8274 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8275 struct port_info *pi,
8276 bool rx_en, bool tx_en, bool dcb_en)
8278 int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8279 rx_en, tx_en, dcb_en);
8282 t4_os_link_changed(adap, pi->port_id,
8283 rx_en && tx_en && pi->link_cfg.link_ok);
8288 * t4_identify_port - identify a VI's port by blinking its LED
8289 * @adap: the adapter
8290 * @mbox: mailbox to use for the FW command
8292 * @nblinks: how many times to blink LED at 2.5 Hz
8294 * Identifies a VI's port by blinking its LED.
8296 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8297 unsigned int nblinks)
8299 struct fw_vi_enable_cmd c;
8301 memset(&c, 0, sizeof(c));
8302 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8303 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8304 FW_VI_ENABLE_CMD_VIID_V(viid));
8305 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8306 c.blinkdur = cpu_to_be16(nblinks);
8307 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8311 * t4_iq_stop - stop an ingress queue and its FLs
8312 * @adap: the adapter
8313 * @mbox: mailbox to use for the FW command
8314 * @pf: the PF owning the queues
8315 * @vf: the VF owning the queues
8316 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8317 * @iqid: ingress queue id
8318 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8319 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8321 * Stops an ingress queue and its associated FLs, if any. This causes
8322 * any current or future data/messages destined for these queues to be
8325 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8326 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8327 unsigned int fl0id, unsigned int fl1id)
8331 memset(&c, 0, sizeof(c));
8332 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8333 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8334 FW_IQ_CMD_VFN_V(vf));
8335 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8336 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8337 c.iqid = cpu_to_be16(iqid);
8338 c.fl0id = cpu_to_be16(fl0id);
8339 c.fl1id = cpu_to_be16(fl1id);
8340 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8344 * t4_iq_free - free an ingress queue and its FLs
8345 * @adap: the adapter
8346 * @mbox: mailbox to use for the FW command
8347 * @pf: the PF owning the queues
8348 * @vf: the VF owning the queues
8349 * @iqtype: the ingress queue type
8350 * @iqid: ingress queue id
8351 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8352 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8354 * Frees an ingress queue and its associated FLs, if any.
8356 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8357 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8358 unsigned int fl0id, unsigned int fl1id)
8362 memset(&c, 0, sizeof(c));
8363 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8364 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8365 FW_IQ_CMD_VFN_V(vf));
8366 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8367 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8368 c.iqid = cpu_to_be16(iqid);
8369 c.fl0id = cpu_to_be16(fl0id);
8370 c.fl1id = cpu_to_be16(fl1id);
8371 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8375 * t4_eth_eq_free - free an Ethernet egress queue
8376 * @adap: the adapter
8377 * @mbox: mailbox to use for the FW command
8378 * @pf: the PF owning the queue
8379 * @vf: the VF owning the queue
8380 * @eqid: egress queue id
8382 * Frees an Ethernet egress queue.
8384 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8385 unsigned int vf, unsigned int eqid)
8387 struct fw_eq_eth_cmd c;
8389 memset(&c, 0, sizeof(c));
8390 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8391 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8392 FW_EQ_ETH_CMD_PFN_V(pf) |
8393 FW_EQ_ETH_CMD_VFN_V(vf));
8394 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8395 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8396 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8400 * t4_ctrl_eq_free - free a control egress queue
8401 * @adap: the adapter
8402 * @mbox: mailbox to use for the FW command
8403 * @pf: the PF owning the queue
8404 * @vf: the VF owning the queue
8405 * @eqid: egress queue id
8407 * Frees a control egress queue.
8409 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8410 unsigned int vf, unsigned int eqid)
8412 struct fw_eq_ctrl_cmd c;
8414 memset(&c, 0, sizeof(c));
8415 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8416 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8417 FW_EQ_CTRL_CMD_PFN_V(pf) |
8418 FW_EQ_CTRL_CMD_VFN_V(vf));
8419 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8420 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8421 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8425 * t4_ofld_eq_free - free an offload egress queue
8426 * @adap: the adapter
8427 * @mbox: mailbox to use for the FW command
8428 * @pf: the PF owning the queue
8429 * @vf: the VF owning the queue
8430 * @eqid: egress queue id
8432 * Frees a control egress queue.
8434 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8435 unsigned int vf, unsigned int eqid)
8437 struct fw_eq_ofld_cmd c;
8439 memset(&c, 0, sizeof(c));
8440 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8441 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8442 FW_EQ_OFLD_CMD_PFN_V(pf) |
8443 FW_EQ_OFLD_CMD_VFN_V(vf));
8444 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8445 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8446 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8450 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8451 * @adap: the adapter
8452 * @link_down_rc: Link Down Reason Code
8454 * Returns a string representation of the Link Down Reason Code.
8456 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8458 static const char * const reason[] = {
8461 "Auto-negotiation Failure",
8463 "Insufficient Airflow",
8464 "Unable To Determine Reason",
8465 "No RX Signal Detected",
8469 if (link_down_rc >= ARRAY_SIZE(reason))
8470 return "Bad Reason Code";
8472 return reason[link_down_rc];
8476 * Return the highest speed set in the port capabilities, in Mb/s.
8478 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8480 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8482 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8486 TEST_SPEED_RETURN(400G, 400000);
8487 TEST_SPEED_RETURN(200G, 200000);
8488 TEST_SPEED_RETURN(100G, 100000);
8489 TEST_SPEED_RETURN(50G, 50000);
8490 TEST_SPEED_RETURN(40G, 40000);
8491 TEST_SPEED_RETURN(25G, 25000);
8492 TEST_SPEED_RETURN(10G, 10000);
8493 TEST_SPEED_RETURN(1G, 1000);
8494 TEST_SPEED_RETURN(100M, 100);
8496 #undef TEST_SPEED_RETURN
8502 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8503 * @acaps: advertised Port Capabilities
8505 * Get the highest speed for the port from the advertised Port
8506 * Capabilities. It will be either the highest speed from the list of
8507 * speeds or whatever user has set using ethtool.
8509 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8511 #define TEST_SPEED_RETURN(__caps_speed) \
8513 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8514 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8517 TEST_SPEED_RETURN(400G);
8518 TEST_SPEED_RETURN(200G);
8519 TEST_SPEED_RETURN(100G);
8520 TEST_SPEED_RETURN(50G);
8521 TEST_SPEED_RETURN(40G);
8522 TEST_SPEED_RETURN(25G);
8523 TEST_SPEED_RETURN(10G);
8524 TEST_SPEED_RETURN(1G);
8525 TEST_SPEED_RETURN(100M);
8527 #undef TEST_SPEED_RETURN
8533 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8534 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8536 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8537 * 32-bit Port Capabilities value.
8539 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8541 fw_port_cap32_t linkattr = 0;
8543 /* Unfortunately the format of the Link Status in the old
8544 * 16-bit Port Information message isn't the same as the
8545 * 16-bit Port Capabilities bitfield used everywhere else ...
8547 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8548 linkattr |= FW_PORT_CAP32_FC_RX;
8549 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8550 linkattr |= FW_PORT_CAP32_FC_TX;
8551 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8552 linkattr |= FW_PORT_CAP32_SPEED_100M;
8553 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8554 linkattr |= FW_PORT_CAP32_SPEED_1G;
8555 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8556 linkattr |= FW_PORT_CAP32_SPEED_10G;
8557 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8558 linkattr |= FW_PORT_CAP32_SPEED_25G;
8559 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8560 linkattr |= FW_PORT_CAP32_SPEED_40G;
8561 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8562 linkattr |= FW_PORT_CAP32_SPEED_100G;
8568 * t4_handle_get_port_info - process a FW reply message
8569 * @pi: the port info
8570 * @rpl: start of the FW message
8572 * Processes a GET_PORT_INFO FW reply message.
8574 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8576 const struct fw_port_cmd *cmd = (const void *)rpl;
8577 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8578 struct link_config *lc = &pi->link_cfg;
8579 struct adapter *adapter = pi->adapter;
8580 unsigned int speed, fc, fec, adv_fc;
8581 enum fw_port_module_type mod_type;
8582 int action, link_ok, linkdnrc;
8583 enum fw_port_type port_type;
8585 /* Extract the various fields from the Port Information message.
8587 action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8589 case FW_PORT_ACTION_GET_PORT_INFO: {
8590 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8592 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8593 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8594 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8595 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8596 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8597 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8598 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8599 linkattr = lstatus_to_fwcap(lstatus);
8603 case FW_PORT_ACTION_GET_PORT_INFO32: {
8606 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8607 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8608 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8609 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8610 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8611 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8612 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8613 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8614 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8619 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8620 be32_to_cpu(cmd->action_to_len16));
8624 fec = fwcap_to_cc_fec(acaps);
8625 adv_fc = fwcap_to_cc_pause(acaps);
8626 fc = fwcap_to_cc_pause(linkattr);
8627 speed = fwcap_to_speed(linkattr);
8629 /* Reset state for communicating new Transceiver Module status and
8630 * whether the OS-dependent layer wants us to redo the current
8631 * "sticky" L1 Configure Link Parameters.
8633 lc->new_module = false;
8634 lc->redo_l1cfg = false;
8636 if (mod_type != pi->mod_type) {
8637 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8638 * various fundamental Port Capabilities which used to be
8639 * immutable can now change radically. We can now have
8640 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8641 * all change based on what Transceiver Module is inserted.
8642 * So we need to record the Physical "Port" Capabilities on
8643 * every Transceiver Module change.
8647 /* When a new Transceiver Module is inserted, the Firmware
8648 * will examine its i2c EPROM to determine its type and
8649 * general operating parameters including things like Forward
8650 * Error Control, etc. Various IEEE 802.3 standards dictate
8651 * how to interpret these i2c values to determine default
8652 * "sutomatic" settings. We record these for future use when
8653 * the user explicitly requests these standards-based values.
8655 lc->def_acaps = acaps;
8657 /* Some versions of the early T6 Firmware "cheated" when
8658 * handling different Transceiver Modules by changing the
8659 * underlaying Port Type reported to the Host Drivers. As
8660 * such we need to capture whatever Port Type the Firmware
8661 * sends us and record it in case it's different from what we
8662 * were told earlier. Unfortunately, since Firmware is
8663 * forever, we'll need to keep this code here forever, but in
8664 * later T6 Firmware it should just be an assignment of the
8665 * same value already recorded.
8667 pi->port_type = port_type;
8669 /* Record new Module Type information.
8671 pi->mod_type = mod_type;
8673 /* Let the OS-dependent layer know if we have a new
8674 * Transceiver Module inserted.
8676 lc->new_module = t4_is_inserted_mod_type(mod_type);
8678 t4_os_portmod_changed(adapter, pi->port_id);
8681 if (link_ok != lc->link_ok || speed != lc->speed ||
8682 fc != lc->fc || adv_fc != lc->advertised_fc ||
8684 /* something changed */
8685 if (!link_ok && lc->link_ok) {
8686 lc->link_down_rc = linkdnrc;
8687 dev_warn_ratelimited(adapter->pdev_dev,
8688 "Port %d link down, reason: %s\n",
8690 t4_link_down_rc_str(linkdnrc));
8692 lc->link_ok = link_ok;
8694 lc->advertised_fc = adv_fc;
8698 lc->lpacaps = lpacaps;
8699 lc->acaps = acaps & ADVERT_MASK;
8701 /* If we're not physically capable of Auto-Negotiation, note
8702 * this as Auto-Negotiation disabled. Otherwise, we track
8703 * what Auto-Negotiation settings we have. Note parallel
8704 * structure in t4_link_l1cfg_core() and init_link_config().
8706 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8707 lc->autoneg = AUTONEG_DISABLE;
8708 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8709 lc->autoneg = AUTONEG_ENABLE;
8711 /* When Autoneg is disabled, user needs to set
8713 * Similar to cxgb4_ethtool.c: set_link_ksettings
8716 lc->speed_caps = fwcap_to_fwspeed(acaps);
8717 lc->autoneg = AUTONEG_DISABLE;
8720 t4_os_link_changed(adapter, pi->port_id, link_ok);
8723 /* If we have a new Transceiver Module and the OS-dependent code has
8724 * told us that it wants us to redo whatever "sticky" L1 Configuration
8725 * Link Parameters are set, do that now.
8727 if (lc->new_module && lc->redo_l1cfg) {
8728 struct link_config old_lc;
8731 /* Save the current L1 Configuration and restore it if an
8732 * error occurs. We probably should fix the l1_cfg*()
8733 * routines not to change the link_config when an error
8737 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8740 dev_warn(adapter->pdev_dev,
8741 "Attempt to update new Transceiver Module settings failed\n");
8744 lc->new_module = false;
8745 lc->redo_l1cfg = false;
8749 * t4_update_port_info - retrieve and update port information if changed
8750 * @pi: the port_info
8752 * We issue a Get Port Information Command to the Firmware and, if
8753 * successful, we check to see if anything is different from what we
8754 * last recorded and update things accordingly.
8756 int t4_update_port_info(struct port_info *pi)
8758 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8759 struct fw_port_cmd port_cmd;
8762 memset(&port_cmd, 0, sizeof(port_cmd));
8763 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8764 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8765 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8766 port_cmd.action_to_len16 = cpu_to_be32(
8767 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8768 ? FW_PORT_ACTION_GET_PORT_INFO
8769 : FW_PORT_ACTION_GET_PORT_INFO32) |
8770 FW_LEN16(port_cmd));
8771 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8772 &port_cmd, sizeof(port_cmd), &port_cmd);
8776 t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8781 * t4_get_link_params - retrieve basic link parameters for given port
8783 * @link_okp: value return pointer for link up/down
8784 * @speedp: value return pointer for speed (Mb/s)
8785 * @mtup: value return pointer for mtu
8787 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8788 * and MTU for a specified port. A negative error is returned on
8789 * failure; 0 on success.
8791 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8792 unsigned int *speedp, unsigned int *mtup)
8794 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8795 unsigned int action, link_ok, mtu;
8796 struct fw_port_cmd port_cmd;
8797 fw_port_cap32_t linkattr;
8800 memset(&port_cmd, 0, sizeof(port_cmd));
8801 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8802 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8803 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8804 action = (fw_caps == FW_CAPS16
8805 ? FW_PORT_ACTION_GET_PORT_INFO
8806 : FW_PORT_ACTION_GET_PORT_INFO32);
8807 port_cmd.action_to_len16 = cpu_to_be32(
8808 FW_PORT_CMD_ACTION_V(action) |
8809 FW_LEN16(port_cmd));
8810 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8811 &port_cmd, sizeof(port_cmd), &port_cmd);
8815 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8816 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8818 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8819 linkattr = lstatus_to_fwcap(lstatus);
8820 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8823 be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8825 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8826 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8827 mtu = FW_PORT_CMD_MTU32_G(
8828 be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8832 *link_okp = link_ok;
8834 *speedp = fwcap_to_speed(linkattr);
8842 * t4_handle_fw_rpl - process a FW reply message
8843 * @adap: the adapter
8844 * @rpl: start of the FW message
8846 * Processes a FW message, such as link state change messages.
8848 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8850 u8 opcode = *(const u8 *)rpl;
8852 /* This might be a port command ... this simplifies the following
8853 * conditionals ... We can get away with pre-dereferencing
8854 * action_to_len16 because it's in the first 16 bytes and all messages
8855 * will be at least that long.
8857 const struct fw_port_cmd *p = (const void *)rpl;
8858 unsigned int action =
8859 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8861 if (opcode == FW_PORT_CMD &&
8862 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8863 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8865 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8866 struct port_info *pi = NULL;
8868 for_each_port(adap, i) {
8869 pi = adap2pinfo(adap, i);
8870 if (pi->tx_chan == chan)
8874 t4_handle_get_port_info(pi, rpl);
8876 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8883 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8887 if (pci_is_pcie(adapter->pdev)) {
8888 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8889 p->speed = val & PCI_EXP_LNKSTA_CLS;
8890 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8895 * init_link_config - initialize a link's SW state
8896 * @lc: pointer to structure holding the link state
8897 * @pcaps: link Port Capabilities
8898 * @acaps: link current Advertised Port Capabilities
8900 * Initializes the SW state maintained for each link, including the link's
8901 * capabilities and default speed/flow-control/autonegotiation settings.
8903 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8904 fw_port_cap32_t acaps)
8907 lc->def_acaps = acaps;
8911 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8913 /* For Forward Error Control, we default to whatever the Firmware
8914 * tells us the Link is currently advertising.
8916 lc->requested_fec = FEC_AUTO;
8917 lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8919 /* If the Port is capable of Auto-Negtotiation, initialize it as
8920 * "enabled" and copy over all of the Physical Port Capabilities
8921 * to the Advertised Port Capabilities. Otherwise mark it as
8922 * Auto-Negotiate disabled and select the highest supported speed
8923 * for the link. Note parallel structure in t4_link_l1cfg_core()
8924 * and t4_handle_get_port_info().
8926 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8927 lc->acaps = lc->pcaps & ADVERT_MASK;
8928 lc->autoneg = AUTONEG_ENABLE;
8929 lc->requested_fc |= PAUSE_AUTONEG;
8932 lc->autoneg = AUTONEG_DISABLE;
8933 lc->speed_caps = fwcap_to_fwspeed(acaps);
8937 #define CIM_PF_NOACCESS 0xeeeeeeee
8939 int t4_wait_dev_ready(void __iomem *regs)
8943 whoami = readl(regs + PL_WHOAMI_A);
8944 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8948 whoami = readl(regs + PL_WHOAMI_A);
8949 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8953 u32 vendor_and_model_id;
8957 static int t4_get_flash_params(struct adapter *adap)
8959 /* Table for non-Numonix supported flash parts. Numonix parts are left
8960 * to the preexisting code. All flash parts have 64KB sectors.
8962 static struct flash_desc supported_flash[] = {
8963 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8966 unsigned int part, manufacturer;
8967 unsigned int density, size = 0;
8971 /* Issue a Read ID Command to the Flash part. We decode supported
8972 * Flash parts and their sizes from this. There's a newer Query
8973 * Command which can retrieve detailed geometry information but many
8974 * Flash parts don't support it.
8977 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8979 ret = sf1_read(adap, 3, 0, 1, &flashid);
8980 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
8984 /* Check to see if it's one of our non-standard supported Flash parts.
8986 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8987 if (supported_flash[part].vendor_and_model_id == flashid) {
8988 adap->params.sf_size = supported_flash[part].size_mb;
8989 adap->params.sf_nsec =
8990 adap->params.sf_size / SF_SEC_SIZE;
8994 /* Decode Flash part size. The code below looks repetitive with
8995 * common encodings, but that's not guaranteed in the JEDEC
8996 * specification for the Read JEDEC ID command. The only thing that
8997 * we're guaranteed by the JEDEC specification is where the
8998 * Manufacturer ID is in the returned result. After that each
8999 * Manufacturer ~could~ encode things completely differently.
9000 * Note, all Flash parts must have 64KB sectors.
9002 manufacturer = flashid & 0xff;
9003 switch (manufacturer) {
9004 case 0x20: { /* Micron/Numonix */
9005 /* This Density -> Size decoding table is taken from Micron
9008 density = (flashid >> 16) & 0xff;
9010 case 0x14: /* 1MB */
9013 case 0x15: /* 2MB */
9016 case 0x16: /* 4MB */
9019 case 0x17: /* 8MB */
9022 case 0x18: /* 16MB */
9025 case 0x19: /* 32MB */
9028 case 0x20: /* 64MB */
9031 case 0x21: /* 128MB */
9034 case 0x22: /* 256MB */
9040 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9041 /* This Density -> Size decoding table is taken from ISSI
9044 density = (flashid >> 16) & 0xff;
9046 case 0x16: /* 32 MB */
9049 case 0x17: /* 64MB */
9055 case 0xc2: { /* Macronix */
9056 /* This Density -> Size decoding table is taken from Macronix
9059 density = (flashid >> 16) & 0xff;
9061 case 0x17: /* 8MB */
9064 case 0x18: /* 16MB */
9070 case 0xef: { /* Winbond */
9071 /* This Density -> Size decoding table is taken from Winbond
9074 density = (flashid >> 16) & 0xff;
9076 case 0x17: /* 8MB */
9079 case 0x18: /* 16MB */
9087 /* If we didn't recognize the FLASH part, that's no real issue: the
9088 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9089 * use a FLASH part which is at least 4MB in size and has 64KB
9090 * sectors. The unrecognized FLASH part is likely to be much larger
9091 * than 4MB, but that's all we really need.
9094 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9099 /* Store decoded Flash size and fall through into vetting code. */
9100 adap->params.sf_size = size;
9101 adap->params.sf_nsec = size / SF_SEC_SIZE;
9104 if (adap->params.sf_size < FLASH_MIN_SIZE)
9105 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9106 flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9111 * t4_prep_adapter - prepare SW and HW for operation
9112 * @adapter: the adapter
9113 * @reset: if true perform a HW reset
9115 * Initialize adapter SW state for the various HW modules, set initial
9116 * values for some adapter tunables, take PHYs out of reset, and
9117 * initialize the MDIO interface.
9119 int t4_prep_adapter(struct adapter *adapter)
9125 get_pci_mode(adapter, &adapter->params.pci);
9126 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9128 ret = t4_get_flash_params(adapter);
9130 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
9134 /* Retrieve adapter's device ID
9136 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
9137 ver = device_id >> 12;
9138 adapter->params.chip = 0;
9141 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
9142 adapter->params.arch.sge_fl_db = DBPRIO_F;
9143 adapter->params.arch.mps_tcam_size =
9144 NUM_MPS_CLS_SRAM_L_INSTANCES;
9145 adapter->params.arch.mps_rplc_size = 128;
9146 adapter->params.arch.nchan = NCHAN;
9147 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9148 adapter->params.arch.vfcount = 128;
9149 /* Congestion map is for 4 channels so that
9150 * MPS can have 4 priority per port.
9152 adapter->params.arch.cng_ch_bits_log = 2;
9155 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
9156 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
9157 adapter->params.arch.mps_tcam_size =
9158 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9159 adapter->params.arch.mps_rplc_size = 128;
9160 adapter->params.arch.nchan = NCHAN;
9161 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9162 adapter->params.arch.vfcount = 128;
9163 adapter->params.arch.cng_ch_bits_log = 2;
9166 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
9167 adapter->params.arch.sge_fl_db = 0;
9168 adapter->params.arch.mps_tcam_size =
9169 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9170 adapter->params.arch.mps_rplc_size = 256;
9171 adapter->params.arch.nchan = 2;
9172 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
9173 adapter->params.arch.vfcount = 256;
9174 /* Congestion map will be for 2 channels so that
9175 * MPS can have 8 priority per port.
9177 adapter->params.arch.cng_ch_bits_log = 3;
9180 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
9185 adapter->params.cim_la_size = CIMLA_SIZE;
9186 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9189 * Default port for debugging in case we can't reach FW.
9191 adapter->params.nports = 1;
9192 adapter->params.portvec = 1;
9193 adapter->params.vpd.cclk = 50000;
9195 /* Set PCIe completion timeout to 4 seconds. */
9196 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
9197 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
9202 * t4_shutdown_adapter - shut down adapter, host & wire
9203 * @adapter: the adapter
9205 * Perform an emergency shutdown of the adapter and stop it from
9206 * continuing any further communication on the ports or DMA to the
9207 * host. This is typically used when the adapter and/or firmware
9208 * have crashed and we want to prevent any further accidental
9209 * communication with the rest of the world. This will also force
9210 * the port Link Status to go down -- if register writes work --
9211 * which should help our peers figure out that we're down.
9213 int t4_shutdown_adapter(struct adapter *adapter)
9217 t4_intr_disable(adapter);
9218 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9219 for_each_port(adapter, port) {
9220 u32 a_port_cfg = is_t4(adapter->params.chip) ?
9221 PORT_REG(port, XGMAC_PORT_CFG_A) :
9222 T5_PORT_REG(port, MAC_PORT_CFG_A);
9224 t4_write_reg(adapter, a_port_cfg,
9225 t4_read_reg(adapter, a_port_cfg)
9226 & ~SIGNAL_DET_V(1));
9228 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9234 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9235 * @adapter: the adapter
9236 * @qid: the Queue ID
9237 * @qtype: the Ingress or Egress type for @qid
9238 * @user: true if this request is for a user mode queue
9239 * @pbar2_qoffset: BAR2 Queue Offset
9240 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9242 * Returns the BAR2 SGE Queue Registers information associated with the
9243 * indicated Absolute Queue ID. These are passed back in return value
9244 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9245 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9247 * This may return an error which indicates that BAR2 SGE Queue
9248 * registers aren't available. If an error is not returned, then the
9249 * following values are returned:
9251 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9252 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9254 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9255 * require the "Inferred Queue ID" ability may be used. E.g. the
9256 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9257 * then these "Inferred Queue ID" register may not be used.
9259 int t4_bar2_sge_qregs(struct adapter *adapter,
9261 enum t4_bar2_qtype qtype,
9264 unsigned int *pbar2_qid)
9266 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9267 u64 bar2_page_offset, bar2_qoffset;
9268 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9270 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9271 if (!user && is_t4(adapter->params.chip))
9274 /* Get our SGE Page Size parameters.
9276 page_shift = adapter->params.sge.hps + 10;
9277 page_size = 1 << page_shift;
9279 /* Get the right Queues per Page parameters for our Queue.
9281 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9282 ? adapter->params.sge.eq_qpp
9283 : adapter->params.sge.iq_qpp);
9284 qpp_mask = (1 << qpp_shift) - 1;
9286 /* Calculate the basics of the BAR2 SGE Queue register area:
9287 * o The BAR2 page the Queue registers will be in.
9288 * o The BAR2 Queue ID.
9289 * o The BAR2 Queue ID Offset into the BAR2 page.
9291 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9292 bar2_qid = qid & qpp_mask;
9293 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9295 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9296 * hardware will infer the Absolute Queue ID simply from the writes to
9297 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9298 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9299 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9300 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9301 * from the BAR2 Page and BAR2 Queue ID.
9303 * One important censequence of this is that some BAR2 SGE registers
9304 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9305 * there. But other registers synthesize the SGE Queue ID purely
9306 * from the writes to the registers -- the Write Combined Doorbell
9307 * Buffer is a good example. These BAR2 SGE Registers are only
9308 * available for those BAR2 SGE Register areas where the SGE Absolute
9309 * Queue ID can be inferred from simple writes.
9311 bar2_qoffset = bar2_page_offset;
9312 bar2_qinferred = (bar2_qid_offset < page_size);
9313 if (bar2_qinferred) {
9314 bar2_qoffset += bar2_qid_offset;
9318 *pbar2_qoffset = bar2_qoffset;
9319 *pbar2_qid = bar2_qid;
9324 * t4_init_devlog_params - initialize adapter->params.devlog
9325 * @adap: the adapter
9327 * Initialize various fields of the adapter's Firmware Device Log
9328 * Parameters structure.
9330 int t4_init_devlog_params(struct adapter *adap)
9332 struct devlog_params *dparams = &adap->params.devlog;
9334 unsigned int devlog_meminfo;
9335 struct fw_devlog_cmd devlog_cmd;
9338 /* If we're dealing with newer firmware, the Device Log Parameters
9339 * are stored in a designated register which allows us to access the
9340 * Device Log even if we can't talk to the firmware.
9343 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9345 unsigned int nentries, nentries128;
9347 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9348 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9350 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9351 nentries = (nentries128 + 1) * 128;
9352 dparams->size = nentries * sizeof(struct fw_devlog_e);
9357 /* Otherwise, ask the firmware for it's Device Log Parameters.
9359 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9360 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9361 FW_CMD_REQUEST_F | FW_CMD_READ_F);
9362 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9363 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9369 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9370 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9371 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9372 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9378 * t4_init_sge_params - initialize adap->params.sge
9379 * @adapter: the adapter
9381 * Initialize various fields of the adapter's SGE Parameters structure.
9383 int t4_init_sge_params(struct adapter *adapter)
9385 struct sge_params *sge_params = &adapter->params.sge;
9387 unsigned int s_hps, s_qpp;
9389 /* Extract the SGE Page Size for our PF.
9391 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9392 s_hps = (HOSTPAGESIZEPF0_S +
9393 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9394 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9396 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9398 s_qpp = (QUEUESPERPAGEPF0_S +
9399 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9400 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9401 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9402 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9403 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9409 * t4_init_tp_params - initialize adap->params.tp
9410 * @adap: the adapter
9411 * @sleep_ok: if true we may sleep while awaiting command completion
9413 * Initialize various fields of the adapter's TP Parameters structure.
9415 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9421 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9422 adap->params.tp.tre = TIMERRESOLUTION_G(v);
9423 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9425 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9426 for (chan = 0; chan < NCHAN; chan++)
9427 adap->params.tp.tx_modq[chan] = chan;
9429 /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9432 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
9433 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER) |
9434 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK));
9436 /* Read current value */
9437 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9440 dev_info(adap->pdev_dev,
9441 "Current filter mode/mask 0x%x:0x%x\n",
9442 FW_PARAMS_PARAM_FILTER_MODE_G(val),
9443 FW_PARAMS_PARAM_FILTER_MASK_G(val));
9444 adap->params.tp.vlan_pri_map =
9445 FW_PARAMS_PARAM_FILTER_MODE_G(val);
9446 adap->params.tp.filter_mask =
9447 FW_PARAMS_PARAM_FILTER_MASK_G(val);
9449 dev_info(adap->pdev_dev,
9450 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9452 /* Incase of older-fw (which doesn't expose the api
9453 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9454 * the fw api) combination, fall-back to older method of reading
9455 * the filter mode from indirect-register
9457 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9458 TP_VLAN_PRI_MAP_A, sleep_ok);
9460 /* With the older-fw and newer-driver combination we might run
9461 * into an issue when user wants to use hash filter region but
9462 * the filter_mask is zero, in this case filter_mask validation
9463 * is tough. To avoid that we set the filter_mask same as filter
9464 * mode, which will behave exactly as the older way of ignoring
9465 * the filter mask validation.
9467 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9470 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9471 TP_INGRESS_CONFIG_A, sleep_ok);
9473 /* For T6, cache the adapter's compressed error vector
9474 * and passing outer header info for encapsulated packets.
9476 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9477 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9478 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9481 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9482 * shift positions of several elements of the Compressed Filter Tuple
9483 * for this adapter which we need frequently ...
9485 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9486 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9487 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9488 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9489 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9490 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9492 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9494 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9496 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9498 adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9501 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9502 * represents the presence of an Outer VLAN instead of a VNIC ID.
9504 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9505 adap->params.tp.vnic_shift = -1;
9507 v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9508 adap->params.tp.hash_filter_mask = v;
9509 v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9510 adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9515 * t4_filter_field_shift - calculate filter field shift
9516 * @adap: the adapter
9517 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9519 * Return the shift position of a filter field within the Compressed
9520 * Filter Tuple. The filter field is specified via its selection bit
9521 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9523 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9525 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9529 if ((filter_mode & filter_sel) == 0)
9532 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9533 switch (filter_mode & sel) {
9535 field_shift += FT_FCOE_W;
9538 field_shift += FT_PORT_W;
9541 field_shift += FT_VNIC_ID_W;
9544 field_shift += FT_VLAN_W;
9547 field_shift += FT_TOS_W;
9550 field_shift += FT_PROTOCOL_W;
9553 field_shift += FT_ETHERTYPE_W;
9556 field_shift += FT_MACMATCH_W;
9559 field_shift += FT_MPSHITTYPE_W;
9561 case FRAGMENTATION_F:
9562 field_shift += FT_FRAGMENTATION_W;
9569 int t4_init_rss_mode(struct adapter *adap, int mbox)
9572 struct fw_rss_vi_config_cmd rvc;
9574 memset(&rvc, 0, sizeof(rvc));
9576 for_each_port(adap, i) {
9577 struct port_info *p = adap2pinfo(adap, i);
9580 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9581 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9582 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9583 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9584 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9587 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9593 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9594 * @pi: the port_info
9595 * @mbox: mailbox to use for the FW command
9596 * @port: physical port associated with the VI
9597 * @pf: the PF owning the VI
9598 * @vf: the VF owning the VI
9599 * @mac: the MAC address of the VI
9601 * Allocates a virtual interface for the given physical port. If @mac is
9602 * not %NULL it contains the MAC address of the VI as assigned by FW.
9603 * @mac should be large enough to hold an Ethernet address.
9604 * Returns < 0 on error.
9606 int t4_init_portinfo(struct port_info *pi, int mbox,
9607 int port, int pf, int vf, u8 mac[])
9609 struct adapter *adapter = pi->adapter;
9610 unsigned int fw_caps = adapter->params.fw_caps_support;
9611 struct fw_port_cmd cmd;
9612 unsigned int rss_size;
9613 enum fw_port_type port_type;
9615 fw_port_cap32_t pcaps, acaps;
9616 u8 vivld = 0, vin = 0;
9619 /* If we haven't yet determined whether we're talking to Firmware
9620 * which knows the new 32-bit Port Capabilities, it's time to find
9621 * out now. This will also tell new Firmware to send us Port Status
9622 * Updates using the new 32-bit Port Capabilities version of the
9623 * Port Information message.
9625 if (fw_caps == FW_CAPS_UNKNOWN) {
9628 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9629 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9631 ret = t4_set_params(adapter, mbox, pf, vf, 1, ¶m, &val);
9632 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9633 adapter->params.fw_caps_support = fw_caps;
9636 memset(&cmd, 0, sizeof(cmd));
9637 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9638 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9639 FW_PORT_CMD_PORTID_V(port));
9640 cmd.action_to_len16 = cpu_to_be32(
9641 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9642 ? FW_PORT_ACTION_GET_PORT_INFO
9643 : FW_PORT_ACTION_GET_PORT_INFO32) |
9645 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9649 /* Extract the various fields from the Port Information message.
9651 if (fw_caps == FW_CAPS16) {
9652 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9654 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9655 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9656 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9658 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9659 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9661 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9663 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9664 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9665 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9667 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9668 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9671 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size,
9679 pi->rss_size = rss_size;
9680 pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
9682 /* If fw supports returning the VIN as part of FW_VI_CMD,
9683 * save the returned values.
9685 if (adapter->params.viid_smt_extn_support) {
9689 /* Retrieve the values from VIID */
9690 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
9691 pi->vin = FW_VIID_VIN_G(pi->viid);
9694 pi->port_type = port_type;
9695 pi->mdio_addr = mdio_addr;
9696 pi->mod_type = FW_PORT_MOD_TYPE_NA;
9698 init_link_config(&pi->link_cfg, pcaps, acaps);
9702 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9707 for_each_port(adap, i) {
9708 struct port_info *pi = adap2pinfo(adap, i);
9710 while ((adap->params.portvec & (1 << j)) == 0)
9713 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9717 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9724 * t4_read_cimq_cfg - read CIM queue configuration
9725 * @adap: the adapter
9726 * @base: holds the queue base addresses in bytes
9727 * @size: holds the queue sizes in bytes
9728 * @thres: holds the queue full thresholds in bytes
9730 * Returns the current configuration of the CIM queues, starting with
9731 * the IBQs, then the OBQs.
9733 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9736 int cim_num_obq = is_t4(adap->params.chip) ?
9737 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9739 for (i = 0; i < CIM_NUM_IBQ; i++) {
9740 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9742 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9743 /* value is in 256-byte units */
9744 *base++ = CIMQBASE_G(v) * 256;
9745 *size++ = CIMQSIZE_G(v) * 256;
9746 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9748 for (i = 0; i < cim_num_obq; i++) {
9749 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9751 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9752 /* value is in 256-byte units */
9753 *base++ = CIMQBASE_G(v) * 256;
9754 *size++ = CIMQSIZE_G(v) * 256;
9759 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9760 * @adap: the adapter
9761 * @qid: the queue index
9762 * @data: where to store the queue contents
9763 * @n: capacity of @data in 32-bit words
9765 * Reads the contents of the selected CIM queue starting at address 0 up
9766 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9767 * error and the number of 32-bit words actually read on success.
9769 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9771 int i, err, attempts;
9773 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9775 if (qid > 5 || (n & 3))
9778 addr = qid * nwords;
9782 /* It might take 3-10ms before the IBQ debug read access is allowed.
9783 * Wait for 1 Sec with a delay of 1 usec.
9787 for (i = 0; i < n; i++, addr++) {
9788 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9790 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9794 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9796 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9801 * t4_read_cim_obq - read the contents of a CIM outbound queue
9802 * @adap: the adapter
9803 * @qid: the queue index
9804 * @data: where to store the queue contents
9805 * @n: capacity of @data in 32-bit words
9807 * Reads the contents of the selected CIM queue starting at address 0 up
9808 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9809 * error and the number of 32-bit words actually read on success.
9811 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9814 unsigned int addr, v, nwords;
9815 int cim_num_obq = is_t4(adap->params.chip) ?
9816 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9818 if ((qid > (cim_num_obq - 1)) || (n & 3))
9821 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9822 QUENUMSELECT_V(qid));
9823 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9825 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
9826 nwords = CIMQSIZE_G(v) * 64; /* same */
9830 for (i = 0; i < n; i++, addr++) {
9831 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9833 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9837 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9839 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9844 * t4_cim_read - read a block from CIM internal address space
9845 * @adap: the adapter
9846 * @addr: the start address within the CIM address space
9847 * @n: number of words to read
9848 * @valp: where to store the result
9850 * Reads a block of 4-byte words from the CIM intenal address space.
9852 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9857 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9860 for ( ; !ret && n--; addr += 4) {
9861 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9862 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9865 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9871 * t4_cim_write - write a block into CIM internal address space
9872 * @adap: the adapter
9873 * @addr: the start address within the CIM address space
9874 * @n: number of words to write
9875 * @valp: set of values to write
9877 * Writes a block of 4-byte words into the CIM intenal address space.
9879 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9880 const unsigned int *valp)
9884 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9887 for ( ; !ret && n--; addr += 4) {
9888 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9889 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9890 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9896 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9899 return t4_cim_write(adap, addr, 1, &val);
9903 * t4_cim_read_la - read CIM LA capture buffer
9904 * @adap: the adapter
9905 * @la_buf: where to store the LA data
9906 * @wrptr: the HW write pointer within the capture buffer
9908 * Reads the contents of the CIM LA buffer with the most recent entry at
9909 * the end of the returned data and with the entry at @wrptr first.
9910 * We try to leave the LA in the running state we find it in.
9912 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9915 unsigned int cfg, val, idx;
9917 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9921 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
9922 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9927 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9931 idx = UPDBGLAWRPTR_G(val);
9935 for (i = 0; i < adap->params.cim_la_size; i++) {
9936 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9937 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9940 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9943 if (val & UPDBGLARDEN_F) {
9947 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9951 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9952 * identify the 32-bit portion of the full 312-bit data
9954 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9955 idx = (idx & 0xff0) + 0x10;
9958 /* address can't exceed 0xfff */
9959 idx &= UPDBGLARDPTR_M;
9962 if (cfg & UPDBGLAEN_F) {
9963 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9964 cfg & ~UPDBGLARDEN_F);
9972 * t4_tp_read_la - read TP LA capture buffer
9973 * @adap: the adapter
9974 * @la_buf: where to store the LA data
9975 * @wrptr: the HW write pointer within the capture buffer
9977 * Reads the contents of the TP LA buffer with the most recent entry at
9978 * the end of the returned data and with the entry at @wrptr first.
9979 * We leave the LA in the running state we find it in.
9981 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9983 bool last_incomplete;
9984 unsigned int i, cfg, val, idx;
9986 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9987 if (cfg & DBGLAENABLE_F) /* freeze LA */
9988 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9989 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9991 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9992 idx = DBGLAWPTR_G(val);
9993 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9994 if (last_incomplete)
9995 idx = (idx + 1) & DBGLARPTR_M;
10000 val &= ~DBGLARPTR_V(DBGLARPTR_M);
10001 val |= adap->params.tp.la_mask;
10003 for (i = 0; i < TPLA_SIZE; i++) {
10004 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
10005 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
10006 idx = (idx + 1) & DBGLARPTR_M;
10009 /* Wipe out last entry if it isn't valid */
10010 if (last_incomplete)
10011 la_buf[TPLA_SIZE - 1] = ~0ULL;
10013 if (cfg & DBGLAENABLE_F) /* restore running state */
10014 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10015 cfg | adap->params.tp.la_mask);
10018 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10019 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10020 * state for more than the Warning Threshold then we'll issue a warning about
10021 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10022 * appears to be hung every Warning Repeat second till the situation clears.
10023 * If the situation clears, we'll note that as well.
10025 #define SGE_IDMA_WARN_THRESH 1
10026 #define SGE_IDMA_WARN_REPEAT 300
10029 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10030 * @adapter: the adapter
10031 * @idma: the adapter IDMA Monitor state
10033 * Initialize the state of an SGE Ingress DMA Monitor.
10035 void t4_idma_monitor_init(struct adapter *adapter,
10036 struct sge_idma_monitor_state *idma)
10038 /* Initialize the state variables for detecting an SGE Ingress DMA
10039 * hang. The SGE has internal counters which count up on each clock
10040 * tick whenever the SGE finds its Ingress DMA State Engines in the
10041 * same state they were on the previous clock tick. The clock used is
10042 * the Core Clock so we have a limit on the maximum "time" they can
10043 * record; typically a very small number of seconds. For instance,
10044 * with a 600MHz Core Clock, we can only count up to a bit more than
10045 * 7s. So we'll synthesize a larger counter in order to not run the
10046 * risk of having the "timers" overflow and give us the flexibility to
10047 * maintain a Hung SGE State Machine of our own which operates across
10048 * a longer time frame.
10050 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10051 idma->idma_stalled[0] = 0;
10052 idma->idma_stalled[1] = 0;
10056 * t4_idma_monitor - monitor SGE Ingress DMA state
10057 * @adapter: the adapter
10058 * @idma: the adapter IDMA Monitor state
10059 * @hz: number of ticks/second
10060 * @ticks: number of ticks since the last IDMA Monitor call
10062 void t4_idma_monitor(struct adapter *adapter,
10063 struct sge_idma_monitor_state *idma,
10066 int i, idma_same_state_cnt[2];
10068 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10069 * are counters inside the SGE which count up on each clock when the
10070 * SGE finds its Ingress DMA State Engines in the same states they
10071 * were in the previous clock. The counters will peg out at
10072 * 0xffffffff without wrapping around so once they pass the 1s
10073 * threshold they'll stay above that till the IDMA state changes.
10075 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
10076 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10077 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10079 for (i = 0; i < 2; i++) {
10080 u32 debug0, debug11;
10082 /* If the Ingress DMA Same State Counter ("timer") is less
10083 * than 1s, then we can reset our synthesized Stall Timer and
10084 * continue. If we have previously emitted warnings about a
10085 * potential stalled Ingress Queue, issue a note indicating
10086 * that the Ingress Queue has resumed forward progress.
10088 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10089 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
10090 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
10091 "resumed after %d seconds\n",
10092 i, idma->idma_qid[i],
10093 idma->idma_stalled[i] / hz);
10094 idma->idma_stalled[i] = 0;
10098 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10099 * domain. The first time we get here it'll be because we
10100 * passed the 1s Threshold; each additional time it'll be
10101 * because the RX Timer Callback is being fired on its regular
10104 * If the stall is below our Potential Hung Ingress Queue
10105 * Warning Threshold, continue.
10107 if (idma->idma_stalled[i] == 0) {
10108 idma->idma_stalled[i] = hz;
10109 idma->idma_warn[i] = 0;
10111 idma->idma_stalled[i] += ticks;
10112 idma->idma_warn[i] -= ticks;
10115 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
10118 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10120 if (idma->idma_warn[i] > 0)
10122 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
10124 /* Read and save the SGE IDMA State and Queue ID information.
10125 * We do this every time in case it changes across time ...
10126 * can't be too careful ...
10128 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
10129 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10130 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10132 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
10133 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10134 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10136 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
10137 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10138 i, idma->idma_qid[i], idma->idma_state[i],
10139 idma->idma_stalled[i] / hz,
10141 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10146 * t4_load_cfg - download config file
10147 * @adap: the adapter
10148 * @cfg_data: the cfg text file to write
10149 * @size: text file size
10151 * Write the supplied config text file to the card's serial flash.
10153 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10155 int ret, i, n, cfg_addr;
10157 unsigned int flash_cfg_start_sec;
10158 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10160 cfg_addr = t4_flash_cfg_addr(adap);
10165 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10167 if (size > FLASH_CFG_MAX_SIZE) {
10168 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10169 FLASH_CFG_MAX_SIZE);
10173 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
10175 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10176 flash_cfg_start_sec + i - 1);
10177 /* If size == 0 then we're simply erasing the FLASH sectors associated
10178 * with the on-adapter Firmware Configuration File.
10180 if (ret || size == 0)
10183 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10184 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10185 if ((size - i) < SF_PAGE_SIZE)
10189 ret = t4_write_flash(adap, addr, n, cfg_data);
10193 addr += SF_PAGE_SIZE;
10194 cfg_data += SF_PAGE_SIZE;
10199 dev_err(adap->pdev_dev, "config file %s failed %d\n",
10200 (size == 0 ? "clear" : "download"), ret);
10205 * t4_set_vf_mac - Set MAC address for the specified VF
10206 * @adapter: The adapter
10207 * @vf: one of the VFs instantiated by the specified PF
10208 * @naddr: the number of MAC addresses
10209 * @addr: the MAC address(es) to be set to the specified VF
10211 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
10212 unsigned int naddr, u8 *addr)
10214 struct fw_acl_mac_cmd cmd;
10216 memset(&cmd, 0, sizeof(cmd));
10217 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
10220 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
10221 FW_ACL_MAC_CMD_VFN_V(vf));
10223 /* Note: Do not enable the ACL */
10224 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10227 switch (adapter->pf) {
10229 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10232 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10235 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10238 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10242 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10246 * t4_read_pace_tbl - read the pace table
10247 * @adap: the adapter
10248 * @pace_vals: holds the returned values
10250 * Returns the values of TP's pace table in microseconds.
10252 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10256 for (i = 0; i < NTX_SCHED; i++) {
10257 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10258 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10259 pace_vals[i] = dack_ticks_to_usec(adap, v);
10264 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10265 * @adap: the adapter
10266 * @sched: the scheduler index
10267 * @kbps: the byte rate in Kbps
10268 * @ipg: the interpacket delay in tenths of nanoseconds
10269 * @sleep_ok: if true we may sleep while awaiting command completion
10271 * Return the current configuration of a HW Tx scheduler.
10273 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10274 unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10276 unsigned int v, addr, bpt, cpt;
10279 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10280 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10283 bpt = (v >> 8) & 0xff;
10286 *kbps = 0; /* scheduler disabled */
10288 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10289 *kbps = (v * bpt) / 125;
10293 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10294 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10298 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10302 /* t4_sge_ctxt_rd - read an SGE context through FW
10303 * @adap: the adapter
10304 * @mbox: mailbox to use for the FW command
10305 * @cid: the context id
10306 * @ctype: the context type
10307 * @data: where to store the context data
10309 * Issues a FW command through the given mailbox to read an SGE context.
10311 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10312 enum ctxt_type ctype, u32 *data)
10314 struct fw_ldst_cmd c;
10317 if (ctype == CTXT_FLM)
10318 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10320 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10322 memset(&c, 0, sizeof(c));
10323 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10324 FW_CMD_REQUEST_F | FW_CMD_READ_F |
10325 FW_LDST_CMD_ADDRSPACE_V(ret));
10326 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10327 c.u.idctxt.physid = cpu_to_be32(cid);
10329 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10331 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10332 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10333 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10334 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10335 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10336 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10342 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10343 * @adap: the adapter
10344 * @cid: the context id
10345 * @ctype: the context type
10346 * @data: where to store the context data
10348 * Reads an SGE context directly, bypassing FW. This is only for
10349 * debugging when FW is unavailable.
10351 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10352 enum ctxt_type ctype, u32 *data)
10356 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10357 ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10359 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10360 *data++ = t4_read_reg(adap, i);
10364 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
10365 int rateunit, int ratemode, int channel, int class,
10366 int minrate, int maxrate, int weight, int pktsize)
10368 struct fw_sched_cmd cmd;
10370 memset(&cmd, 0, sizeof(cmd));
10371 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10374 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10376 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10377 cmd.u.params.type = type;
10378 cmd.u.params.level = level;
10379 cmd.u.params.mode = mode;
10380 cmd.u.params.ch = channel;
10381 cmd.u.params.cl = class;
10382 cmd.u.params.unit = rateunit;
10383 cmd.u.params.rate = ratemode;
10384 cmd.u.params.min = cpu_to_be32(minrate);
10385 cmd.u.params.max = cpu_to_be32(maxrate);
10386 cmd.u.params.weight = cpu_to_be16(weight);
10387 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10389 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10394 * t4_i2c_rd - read I2C data from adapter
10395 * @adap: the adapter
10396 * @port: Port number if per-port device; <0 if not
10397 * @devid: per-port device ID or absolute device ID
10398 * @offset: byte offset into device I2C space
10399 * @len: byte length of I2C space data
10400 * @buf: buffer in which to return I2C data
10402 * Reads the I2C data from the indicated device and location.
10404 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10405 unsigned int devid, unsigned int offset,
10406 unsigned int len, u8 *buf)
10408 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10409 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10412 if (len > I2C_PAGE_SIZE)
10415 /* Dont allow reads that spans multiple pages */
10416 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10419 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10420 ldst_cmd.op_to_addrspace =
10421 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10424 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10425 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10426 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10427 ldst_cmd.u.i2c.did = devid;
10430 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10432 ldst_cmd.u.i2c.boffset = offset;
10433 ldst_cmd.u.i2c.blen = i2c_len;
10435 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10440 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10450 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10451 * @adapter: the adapter
10452 * @mbox: mailbox to use for the FW command
10453 * @vf: one of the VFs instantiated by the specified PF
10454 * @vlan: The vlanid to be set
10456 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10459 struct fw_acl_vlan_cmd vlan_cmd;
10460 unsigned int enable;
10462 enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10463 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10464 vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10468 FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10469 FW_ACL_VLAN_CMD_VFN_V(vf));
10470 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10471 /* Drop all packets that donot match vlan id */
10472 vlan_cmd.dropnovlan_fm = (enable
10473 ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F |
10474 FW_ACL_VLAN_CMD_FM_F) : 0);
10476 vlan_cmd.nvlan = 1;
10477 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10480 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
projects / linux-2.6-microblaze.git / blob