drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 /**
 228  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 229  *      @adapter: the adapter
 230  *      @cmd: the Firmware Mailbox Command or Reply
 231  *      @size: command length in bytes
 232  *      @access: the time (ms) needed to access the Firmware Mailbox
 233  *      @execute: the time (ms) the command spent being executed
 234  */
 235 static void t4_record_mbox(struct adapter *adapter,
 236                            const __be64 *cmd, unsigned int size,
 237                            int access, int execute)
 238 {
 239         struct mbox_cmd_log *log = adapter->mbox_log;
 240         struct mbox_cmd *entry;
 241         int i;
 242
 243         entry = mbox_cmd_log_entry(log, log->cursor++);
 244         if (log->cursor == log->size)
 245                 log->cursor = 0;
 246
 247         for (i = 0; i < size / 8; i++)
 248                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 249         while (i < MBOX_LEN / 8)
 250                 entry->cmd[i++] = 0;
 251         entry->timestamp = jiffies;
 252         entry->seqno = log->seqno++;
 253         entry->access = access;
 254         entry->execute = execute;
 255 }
 256
 257 /**
 258  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 259  *      @adap: the adapter
 260  *      @mbox: index of the mailbox to use
 261  *      @cmd: the command to write
 262  *      @size: command length in bytes
 263  *      @rpl: where to optionally store the reply
 264  *      @sleep_ok: if true we may sleep while awaiting command completion
 265  *      @timeout: time to wait for command to finish before timing out
 266  *
 267  *      Sends the given command to FW through the selected mailbox and waits
 268  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 269  *      store the FW's reply to the command.  The command and its optional
 270  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 271  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 272  *      the response.  If sleeping is allowed we use progressive backoff
 273  *      otherwise we spin.
 274  *
 275  *      The return value is 0 on success or a negative errno on failure.  A
 276  *      failure can happen either because we are not able to execute the
 277  *      command or FW executes it but signals an error.  In the latter case
 278  *      the return value is the error code indicated by FW (negated).
 279  */
 280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 281                             int size, void *rpl, bool sleep_ok, int timeout)
 282 {
 283         static const int delay[] = {
 284                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 285         };
 286
 287         struct mbox_list entry;
 288         u16 access = 0;
 289         u16 execute = 0;
 290         u32 v;
 291         u64 res;
 292         int i, ms, delay_idx, ret;
 293         const __be64 *p = cmd;
 294         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 295         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 296         __be64 cmd_rpl[MBOX_LEN / 8];
 297         u32 pcie_fw;
 298
 299         if ((size & 15) || size > MBOX_LEN)
 300                 return -EINVAL;
 301
 302         /*
 303          * If the device is off-line, as in EEH, commands will time out.
 304          * Fail them early so we don't waste time waiting.
 305          */
 306         if (adap->pdev->error_state != pci_channel_io_normal)
 307                 return -EIO;
 308
 309         /* If we have a negative timeout, that implies that we can't sleep. */
 310         if (timeout < 0) {
 311                 sleep_ok = false;
 312                 timeout = -timeout;
 313         }
 314
 315         /* Queue ourselves onto the mailbox access list.  When our entry is at
 316          * the front of the list, we have rights to access the mailbox.  So we
 317          * wait [for a while] till we're at the front [or bail out with an
 318          * EBUSY] ...
 319          */
 320         spin_lock(&adap->mbox_lock);
 321         list_add_tail(&entry.list, &adap->mlist.list);
 322         spin_unlock(&adap->mbox_lock);
 323
 324         delay_idx = 0;
 325         ms = delay[0];
 326
 327         for (i = 0; ; i += ms) {
 328                 /* If we've waited too long, return a busy indication.  This
 329                  * really ought to be based on our initial position in the
 330                  * mailbox access list but this is a start.  We very rearely
 331                  * contend on access to the mailbox ...
 332                  */
 333                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 334                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 335                         spin_lock(&adap->mbox_lock);
 336                         list_del(&entry.list);
 337                         spin_unlock(&adap->mbox_lock);
 338                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 339                         t4_record_mbox(adap, cmd, size, access, ret);
 340                         return ret;
 341                 }
 342
 343                 /* If we're at the head, break out and start the mailbox
 344                  * protocol.
 345                  */
 346                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 347                                      list) == &entry)
 348                         break;
 349
 350                 /* Delay for a bit before checking again ... */
 351                 if (sleep_ok) {
 352                         ms = delay[delay_idx];  /* last element may repeat */
 353                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 354                                 delay_idx++;
 355                         msleep(ms);
 356                 } else {
 357                         mdelay(ms);
 358                 }
 359         }
 360
 361         /* Loop trying to get ownership of the mailbox.  Return an error
 362          * if we can't gain ownership.
 363          */
 364         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 365         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 366                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         if (v != MBOX_OWNER_DRV) {
 368                 spin_lock(&adap->mbox_lock);
 369                 list_del(&entry.list);
 370                 spin_unlock(&adap->mbox_lock);
 371                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 372                 t4_record_mbox(adap, cmd, size, access, ret);
 373                 return ret;
 374         }
 375
 376         /* Copy in the new mailbox command and send it on its way ... */
 377         t4_record_mbox(adap, cmd, size, access, 0);
 378         for (i = 0; i < size; i += 8)
 379                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 380
 381         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 382         t4_read_reg(adap, ctl_reg);          /* flush write */
 383
 384         delay_idx = 0;
 385         ms = delay[0];
 386
 387         for (i = 0;
 388              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 389              i < timeout;
 390              i += ms) {
 391                 if (sleep_ok) {
 392                         ms = delay[delay_idx];  /* last element may repeat */
 393                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 394                                 delay_idx++;
 395                         msleep(ms);
 396                 } else
 397                         mdelay(ms);
 398
 399                 v = t4_read_reg(adap, ctl_reg);
 400                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 401                         if (!(v & MBMSGVALID_F)) {
 402                                 t4_write_reg(adap, ctl_reg, 0);
 403                                 continue;
 404                         }
 405
 406                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 407                         res = be64_to_cpu(cmd_rpl[0]);
 408
 409                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 410                                 fw_asrt(adap, data_reg);
 411                                 res = FW_CMD_RETVAL_V(EIO);
 412                         } else if (rpl) {
 413                                 memcpy(rpl, cmd_rpl, size);
 414                         }
 415
 416                         t4_write_reg(adap, ctl_reg, 0);
 417
 418                         execute = i + ms;
 419                         t4_record_mbox(adap, cmd_rpl,
 420                                        MBOX_LEN, access, execute);
 421                         spin_lock(&adap->mbox_lock);
 422                         list_del(&entry.list);
 423                         spin_unlock(&adap->mbox_lock);
 424                         return -FW_CMD_RETVAL_G((int)res);
 425                 }
 426         }
 427
 428         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 429         t4_record_mbox(adap, cmd, size, access, ret);
 430         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 431                 *(const u8 *)cmd, mbox);
 432         t4_report_fw_error(adap);
 433         spin_lock(&adap->mbox_lock);
 434         list_del(&entry.list);
 435         spin_unlock(&adap->mbox_lock);
 436         t4_fatal_err(adap);
 437         return ret;
 438 }
 439
 440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 441                     void *rpl, bool sleep_ok)
 442 {
 443         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 444                                        FW_CMD_MAX_TIMEOUT);
 445 }
 446
 447 static int t4_edc_err_read(struct adapter *adap, int idx)
 448 {
 449         u32 edc_ecc_err_addr_reg;
 450         u32 rdata_reg;
 451
 452         if (is_t4(adap->params.chip)) {
 453                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 454                 return 0;
 455         }
 456         if (idx != 0 && idx != 1) {
 457                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 458                 return 0;
 459         }
 460
 461         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 462         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 463
 464         CH_WARN(adap,
 465                 "edc%d err addr 0x%x: 0x%x.\n",
 466                 idx, edc_ecc_err_addr_reg,
 467                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 468         CH_WARN(adap,
 469                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 470                 rdata_reg,
 471                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 472                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 480
 481         return 0;
 482 }
 483
 484 /**
 485  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 486  *      @adap: the adapter
 487  *      @win: PCI-E Memory Window to use
 488  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 489  *      @addr: address within indicated memory type
 490  *      @len: amount of memory to transfer
 491  *      @hbuf: host memory buffer
 492  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 493  *
 494  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 495  *      firmware memory address and host buffer must be aligned on 32-bit
 496  *      boudaries; the length may be arbitrary.  The memory is transferred as
 497  *      a raw byte sequence from/to the firmware's memory.  If this memory
 498  *      contains data structures which contain multi-byte integers, it's the
 499  *      caller's responsibility to perform appropriate byte order conversions.
 500  */
 501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 502                  u32 len, void *hbuf, int dir)
 503 {
 504         u32 pos, offset, resid, memoffset;
 505         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 506         u32 *buf;
 507
 508         /* Argument sanity checks ...
 509          */
 510         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 511                 return -EINVAL;
 512         buf = (u32 *)hbuf;
 513
 514         /* It's convenient to be able to handle lengths which aren't a
 515          * multiple of 32-bits because we often end up transferring files to
 516          * the firmware.  So we'll handle that by normalizing the length here
 517          * and then handling any residual transfer at the end.
 518          */
 519         resid = len & 0x3;
 520         len -= resid;
 521
 522         /* Offset into the region of memory which is being accessed
 523          * MEM_EDC0 = 0
 524          * MEM_EDC1 = 1
 525          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 526          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 527          * MEM_HMA  = 4
 528          */
 529         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 530         if (mtype == MEM_HMA) {
 531                 memoffset = 2 * (edc_size * 1024 * 1024);
 532         } else if (mtype != MEM_MC1) {
 533                 memoffset = (mtype * (edc_size * 1024 * 1024));
 534         } else {
 535                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 536                                                       MA_EXT_MEMORY0_BAR_A));
 537                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 538         }
 539
 540         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 541         addr = addr + memoffset;
 542
 543         /* Each PCI-E Memory Window is programmed with a window size -- or
 544          * "aperture" -- which controls the granularity of its mapping onto
 545          * adapter memory.  We need to grab that aperture in order to know
 546          * how to use the specified window.  The window is also programmed
 547          * with the base address of the Memory Window in BAR0's address
 548          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 549          * the address is relative to BAR0.
 550          */
 551         mem_reg = t4_read_reg(adap,
 552                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 553                                                   win));
 554         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 555         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 556         if (is_t4(adap->params.chip))
 557                 mem_base -= adap->t4_bar0;
 558         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 559
 560         /* Calculate our initial PCI-E Memory Window Position and Offset into
 561          * that Window.
 562          */
 563         pos = addr & ~(mem_aperture-1);
 564         offset = addr - pos;
 565
 566         /* Set up initial PCI-E Memory Window to cover the start of our
 567          * transfer.  (Read it back to ensure that changes propagate before we
 568          * attempt to use the new value.)
 569          */
 570         t4_write_reg(adap,
 571                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 572                      pos | win_pf);
 573         t4_read_reg(adap,
 574                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 575
 576         /* Transfer data to/from the adapter as long as there's an integral
 577          * number of 32-bit transfers to complete.
 578          *
 579          * A note on Endianness issues:
 580          *
 581          * The "register" reads and writes below from/to the PCI-E Memory
 582          * Window invoke the standard adapter Big-Endian to PCI-E Link
 583          * Little-Endian "swizzel."  As a result, if we have the following
 584          * data in adapter memory:
 585          *
 586          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 587          *     Address:      i+0  i+1  i+2  i+3
 588          *
 589          * Then a read of the adapter memory via the PCI-E Memory Window
 590          * will yield:
 591          *
 592          *     x = readl(i)
 593          *         31                  0
 594          *         [ b3 | b2 | b1 | b0 ]
 595          *
 596          * If this value is stored into local memory on a Little-Endian system
 597          * it will show up correctly in local memory as:
 598          *
 599          *     ( ..., b0, b1, b2, b3, ... )
 600          *
 601          * But on a Big-Endian system, the store will show up in memory
 602          * incorrectly swizzled as:
 603          *
 604          *     ( ..., b3, b2, b1, b0, ... )
 605          *
 606          * So we need to account for this in the reads and writes to the
 607          * PCI-E Memory Window below by undoing the register read/write
 608          * swizzels.
 609          */
 610         while (len > 0) {
 611                 if (dir == T4_MEMORY_READ)
 612                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 613                                                 mem_base + offset));
 614                 else
 615                         t4_write_reg(adap, mem_base + offset,
 616                                      (__force u32)cpu_to_le32(*buf++));
 617                 offset += sizeof(__be32);
 618                 len -= sizeof(__be32);
 619
 620                 /* If we've reached the end of our current window aperture,
 621                  * move the PCI-E Memory Window on to the next.  Note that
 622                  * doing this here after "len" may be 0 allows us to set up
 623                  * the PCI-E Memory Window for a possible final residual
 624                  * transfer below ...
 625                  */
 626                 if (offset == mem_aperture) {
 627                         pos += mem_aperture;
 628                         offset = 0;
 629                         t4_write_reg(adap,
 630                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 631                                                     win), pos | win_pf);
 632                         t4_read_reg(adap,
 633                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 634                                                     win));
 635                 }
 636         }
 637
 638         /* If the original transfer had a length which wasn't a multiple of
 639          * 32-bits, now's where we need to finish off the transfer of the
 640          * residual amount.  The PCI-E Memory Window has already been moved
 641          * above (if necessary) to cover this final transfer.
 642          */
 643         if (resid) {
 644                 union {
 645                         u32 word;
 646                         char byte[4];
 647                 } last;
 648                 unsigned char *bp;
 649                 int i;
 650
 651                 if (dir == T4_MEMORY_READ) {
 652                         last.word = le32_to_cpu(
 653                                         (__force __le32)t4_read_reg(adap,
 654                                                 mem_base + offset));
 655                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 656                                 bp[i] = last.byte[i];
 657                 } else {
 658                         last.word = *buf;
 659                         for (i = resid; i < 4; i++)
 660                                 last.byte[i] = 0;
 661                         t4_write_reg(adap, mem_base + offset,
 662                                      (__force u32)cpu_to_le32(last.word));
 663                 }
 664         }
 665
 666         return 0;
 667 }
 668
 669 /* Return the specified PCI-E Configuration Space register from our Physical
 670  * Function.  We try first via a Firmware LDST Command since we prefer to let
 671  * the firmware own all of these registers, but if that fails we go for it
 672  * directly ourselves.
 673  */
 674 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 675 {
 676         u32 val, ldst_addrspace;
 677
 678         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 679          * retrieve the specified PCI-E Configuration Space register.
 680          */
 681         struct fw_ldst_cmd ldst_cmd;
 682         int ret;
 683
 684         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 685         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 686         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 687                                                FW_CMD_REQUEST_F |
 688                                                FW_CMD_READ_F |
 689                                                ldst_addrspace);
 690         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 691         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 692         ldst_cmd.u.pcie.ctrl_to_fn =
 693                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 694         ldst_cmd.u.pcie.r = reg;
 695
 696         /* If the LDST Command succeeds, return the result, otherwise
 697          * fall through to reading it directly ourselves ...
 698          */
 699         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 700                          &ldst_cmd);
 701         if (ret == 0)
 702                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 703         else
 704                 /* Read the desired Configuration Space register via the PCI-E
 705                  * Backdoor mechanism.
 706                  */
 707                 t4_hw_pci_read_cfg4(adap, reg, &val);
 708         return val;
 709 }
 710
 711 /* Get the window based on base passed to it.
 712  * Window aperture is currently unhandled, but there is no use case for it
 713  * right now
 714  */
 715 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 716                          u32 memwin_base)
 717 {
 718         u32 ret;
 719
 720         if (is_t4(adap->params.chip)) {
 721                 u32 bar0;
 722
 723                 /* Truncation intentional: we only read the bottom 32-bits of
 724                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 725                  * mechanism to read BAR0 instead of using
 726                  * pci_resource_start() because we could be operating from
 727                  * within a Virtual Machine which is trapping our accesses to
 728                  * our Configuration Space and we need to set up the PCI-E
 729                  * Memory Window decoders with the actual addresses which will
 730                  * be coming across the PCI-E link.
 731                  */
 732                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 733                 bar0 &= pci_mask;
 734                 adap->t4_bar0 = bar0;
 735
 736                 ret = bar0 + memwin_base;
 737         } else {
 738                 /* For T5, only relative offset inside the PCIe BAR is passed */
 739                 ret = memwin_base;
 740         }
 741         return ret;
 742 }
 743
 744 /* Get the default utility window (win0) used by everyone */
 745 u32 t4_get_util_window(struct adapter *adap)
 746 {
 747         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 748                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 749 }
 750
 751 /* Set up memory window for accessing adapter memory ranges.  (Read
 752  * back MA register to ensure that changes propagate before we attempt
 753  * to use the new values.)
 754  */
 755 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 756 {
 757         t4_write_reg(adap,
 758                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 759                      memwin_base | BIR_V(0) |
 760                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 761         t4_read_reg(adap,
 762                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 763 }
 764
 765 /**
 766  *      t4_get_regs_len - return the size of the chips register set
 767  *      @adapter: the adapter
 768  *
 769  *      Returns the size of the chip's BAR0 register space.
 770  */
 771 unsigned int t4_get_regs_len(struct adapter *adapter)
 772 {
 773         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 774
 775         switch (chip_version) {
 776         case CHELSIO_T4:
 777                 return T4_REGMAP_SIZE;
 778
 779         case CHELSIO_T5:
 780         case CHELSIO_T6:
 781                 return T5_REGMAP_SIZE;
 782         }
 783
 784         dev_err(adapter->pdev_dev,
 785                 "Unsupported chip version %d\n", chip_version);
 786         return 0;
 787 }
 788
 789 /**
 790  *      t4_get_regs - read chip registers into provided buffer
 791  *      @adap: the adapter
 792  *      @buf: register buffer
 793  *      @buf_size: size (in bytes) of register buffer
 794  *
 795  *      If the provided register buffer isn't large enough for the chip's
 796  *      full register range, the register dump will be truncated to the
 797  *      register buffer's size.
 798  */
 799 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 800 {
 801         static const unsigned int t4_reg_ranges[] = {
 802                 0x1008, 0x1108,
 803                 0x1180, 0x1184,
 804                 0x1190, 0x1194,
 805                 0x11a0, 0x11a4,
 806                 0x11b0, 0x11b4,
 807                 0x11fc, 0x123c,
 808                 0x1300, 0x173c,
 809                 0x1800, 0x18fc,
 810                 0x3000, 0x30d8,
 811                 0x30e0, 0x30e4,
 812                 0x30ec, 0x5910,
 813                 0x5920, 0x5924,
 814                 0x5960, 0x5960,
 815                 0x5968, 0x5968,
 816                 0x5970, 0x5970,
 817                 0x5978, 0x5978,
 818                 0x5980, 0x5980,
 819                 0x5988, 0x5988,
 820                 0x5990, 0x5990,
 821                 0x5998, 0x5998,
 822                 0x59a0, 0x59d4,
 823                 0x5a00, 0x5ae0,
 824                 0x5ae8, 0x5ae8,
 825                 0x5af0, 0x5af0,
 826                 0x5af8, 0x5af8,
 827                 0x6000, 0x6098,
 828                 0x6100, 0x6150,
 829                 0x6200, 0x6208,
 830                 0x6240, 0x6248,
 831                 0x6280, 0x62b0,
 832                 0x62c0, 0x6338,
 833                 0x6370, 0x638c,
 834                 0x6400, 0x643c,
 835                 0x6500, 0x6524,
 836                 0x6a00, 0x6a04,
 837                 0x6a14, 0x6a38,
 838                 0x6a60, 0x6a70,
 839                 0x6a78, 0x6a78,
 840                 0x6b00, 0x6b0c,
 841                 0x6b1c, 0x6b84,
 842                 0x6bf0, 0x6bf8,
 843                 0x6c00, 0x6c0c,
 844                 0x6c1c, 0x6c84,
 845                 0x6cf0, 0x6cf8,
 846                 0x6d00, 0x6d0c,
 847                 0x6d1c, 0x6d84,
 848                 0x6df0, 0x6df8,
 849                 0x6e00, 0x6e0c,
 850                 0x6e1c, 0x6e84,
 851                 0x6ef0, 0x6ef8,
 852                 0x6f00, 0x6f0c,
 853                 0x6f1c, 0x6f84,
 854                 0x6ff0, 0x6ff8,
 855                 0x7000, 0x700c,
 856                 0x701c, 0x7084,
 857                 0x70f0, 0x70f8,
 858                 0x7100, 0x710c,
 859                 0x711c, 0x7184,
 860                 0x71f0, 0x71f8,
 861                 0x7200, 0x720c,
 862                 0x721c, 0x7284,
 863                 0x72f0, 0x72f8,
 864                 0x7300, 0x730c,
 865                 0x731c, 0x7384,
 866                 0x73f0, 0x73f8,
 867                 0x7400, 0x7450,
 868                 0x7500, 0x7530,
 869                 0x7600, 0x760c,
 870                 0x7614, 0x761c,
 871                 0x7680, 0x76cc,
 872                 0x7700, 0x7798,
 873                 0x77c0, 0x77fc,
 874                 0x7900, 0x79fc,
 875                 0x7b00, 0x7b58,
 876                 0x7b60, 0x7b84,
 877                 0x7b8c, 0x7c38,
 878                 0x7d00, 0x7d38,
 879                 0x7d40, 0x7d80,
 880                 0x7d8c, 0x7ddc,
 881                 0x7de4, 0x7e04,
 882                 0x7e10, 0x7e1c,
 883                 0x7e24, 0x7e38,
 884                 0x7e40, 0x7e44,
 885                 0x7e4c, 0x7e78,
 886                 0x7e80, 0x7ea4,
 887                 0x7eac, 0x7edc,
 888                 0x7ee8, 0x7efc,
 889                 0x8dc0, 0x8e04,
 890                 0x8e10, 0x8e1c,
 891                 0x8e30, 0x8e78,
 892                 0x8ea0, 0x8eb8,
 893                 0x8ec0, 0x8f6c,
 894                 0x8fc0, 0x9008,
 895                 0x9010, 0x9058,
 896                 0x9060, 0x9060,
 897                 0x9068, 0x9074,
 898                 0x90fc, 0x90fc,
 899                 0x9400, 0x9408,
 900                 0x9410, 0x9458,
 901                 0x9600, 0x9600,
 902                 0x9608, 0x9638,
 903                 0x9640, 0x96bc,
 904                 0x9800, 0x9808,
 905                 0x9820, 0x983c,
 906                 0x9850, 0x9864,
 907                 0x9c00, 0x9c6c,
 908                 0x9c80, 0x9cec,
 909                 0x9d00, 0x9d6c,
 910                 0x9d80, 0x9dec,
 911                 0x9e00, 0x9e6c,
 912                 0x9e80, 0x9eec,
 913                 0x9f00, 0x9f6c,
 914                 0x9f80, 0x9fec,
 915                 0xd004, 0xd004,
 916                 0xd010, 0xd03c,
 917                 0xdfc0, 0xdfe0,
 918                 0xe000, 0xea7c,
 919                 0xf000, 0x11110,
 920                 0x11118, 0x11190,
 921                 0x19040, 0x1906c,
 922                 0x19078, 0x19080,
 923                 0x1908c, 0x190e4,
 924                 0x190f0, 0x190f8,
 925                 0x19100, 0x19110,
 926                 0x19120, 0x19124,
 927                 0x19150, 0x19194,
 928                 0x1919c, 0x191b0,
 929                 0x191d0, 0x191e8,
 930                 0x19238, 0x1924c,
 931                 0x193f8, 0x1943c,
 932                 0x1944c, 0x19474,
 933                 0x19490, 0x194e0,
 934                 0x194f0, 0x194f8,
 935                 0x19800, 0x19c08,
 936                 0x19c10, 0x19c90,
 937                 0x19ca0, 0x19ce4,
 938                 0x19cf0, 0x19d40,
 939                 0x19d50, 0x19d94,
 940                 0x19da0, 0x19de8,
 941                 0x19df0, 0x19e40,
 942                 0x19e50, 0x19e90,
 943                 0x19ea0, 0x19f4c,
 944                 0x1a000, 0x1a004,
 945                 0x1a010, 0x1a06c,
 946                 0x1a0b0, 0x1a0e4,
 947                 0x1a0ec, 0x1a0f4,
 948                 0x1a100, 0x1a108,
 949                 0x1a114, 0x1a120,
 950                 0x1a128, 0x1a130,
 951                 0x1a138, 0x1a138,
 952                 0x1a190, 0x1a1c4,
 953                 0x1a1fc, 0x1a1fc,
 954                 0x1e040, 0x1e04c,
 955                 0x1e284, 0x1e28c,
 956                 0x1e2c0, 0x1e2c0,
 957                 0x1e2e0, 0x1e2e0,
 958                 0x1e300, 0x1e384,
 959                 0x1e3c0, 0x1e3c8,
 960                 0x1e440, 0x1e44c,
 961                 0x1e684, 0x1e68c,
 962                 0x1e6c0, 0x1e6c0,
 963                 0x1e6e0, 0x1e6e0,
 964                 0x1e700, 0x1e784,
 965                 0x1e7c0, 0x1e7c8,
 966                 0x1e840, 0x1e84c,
 967                 0x1ea84, 0x1ea8c,
 968                 0x1eac0, 0x1eac0,
 969                 0x1eae0, 0x1eae0,
 970                 0x1eb00, 0x1eb84,
 971                 0x1ebc0, 0x1ebc8,
 972                 0x1ec40, 0x1ec4c,
 973                 0x1ee84, 0x1ee8c,
 974                 0x1eec0, 0x1eec0,
 975                 0x1eee0, 0x1eee0,
 976                 0x1ef00, 0x1ef84,
 977                 0x1efc0, 0x1efc8,
 978                 0x1f040, 0x1f04c,
 979                 0x1f284, 0x1f28c,
 980                 0x1f2c0, 0x1f2c0,
 981                 0x1f2e0, 0x1f2e0,
 982                 0x1f300, 0x1f384,
 983                 0x1f3c0, 0x1f3c8,
 984                 0x1f440, 0x1f44c,
 985                 0x1f684, 0x1f68c,
 986                 0x1f6c0, 0x1f6c0,
 987                 0x1f6e0, 0x1f6e0,
 988                 0x1f700, 0x1f784,
 989                 0x1f7c0, 0x1f7c8,
 990                 0x1f840, 0x1f84c,
 991                 0x1fa84, 0x1fa8c,
 992                 0x1fac0, 0x1fac0,
 993                 0x1fae0, 0x1fae0,
 994                 0x1fb00, 0x1fb84,
 995                 0x1fbc0, 0x1fbc8,
 996                 0x1fc40, 0x1fc4c,
 997                 0x1fe84, 0x1fe8c,
 998                 0x1fec0, 0x1fec0,
 999                 0x1fee0, 0x1fee0,
1000                 0x1ff00, 0x1ff84,
1001                 0x1ffc0, 0x1ffc8,
1002                 0x20000, 0x2002c,
1003                 0x20100, 0x2013c,
1004                 0x20190, 0x201a0,
1005                 0x201a8, 0x201b8,
1006                 0x201c4, 0x201c8,
1007                 0x20200, 0x20318,
1008                 0x20400, 0x204b4,
1009                 0x204c0, 0x20528,
1010                 0x20540, 0x20614,
1011                 0x21000, 0x21040,
1012                 0x2104c, 0x21060,
1013                 0x210c0, 0x210ec,
1014                 0x21200, 0x21268,
1015                 0x21270, 0x21284,
1016                 0x212fc, 0x21388,
1017                 0x21400, 0x21404,
1018                 0x21500, 0x21500,
1019                 0x21510, 0x21518,
1020                 0x2152c, 0x21530,
1021                 0x2153c, 0x2153c,
1022                 0x21550, 0x21554,
1023                 0x21600, 0x21600,
1024                 0x21608, 0x2161c,
1025                 0x21624, 0x21628,
1026                 0x21630, 0x21634,
1027                 0x2163c, 0x2163c,
1028                 0x21700, 0x2171c,
1029                 0x21780, 0x2178c,
1030                 0x21800, 0x21818,
1031                 0x21820, 0x21828,
1032                 0x21830, 0x21848,
1033                 0x21850, 0x21854,
1034                 0x21860, 0x21868,
1035                 0x21870, 0x21870,
1036                 0x21878, 0x21898,
1037                 0x218a0, 0x218a8,
1038                 0x218b0, 0x218c8,
1039                 0x218d0, 0x218d4,
1040                 0x218e0, 0x218e8,
1041                 0x218f0, 0x218f0,
1042                 0x218f8, 0x21a18,
1043                 0x21a20, 0x21a28,
1044                 0x21a30, 0x21a48,
1045                 0x21a50, 0x21a54,
1046                 0x21a60, 0x21a68,
1047                 0x21a70, 0x21a70,
1048                 0x21a78, 0x21a98,
1049                 0x21aa0, 0x21aa8,
1050                 0x21ab0, 0x21ac8,
1051                 0x21ad0, 0x21ad4,
1052                 0x21ae0, 0x21ae8,
1053                 0x21af0, 0x21af0,
1054                 0x21af8, 0x21c18,
1055                 0x21c20, 0x21c20,
1056                 0x21c28, 0x21c30,
1057                 0x21c38, 0x21c38,
1058                 0x21c80, 0x21c98,
1059                 0x21ca0, 0x21ca8,
1060                 0x21cb0, 0x21cc8,
1061                 0x21cd0, 0x21cd4,
1062                 0x21ce0, 0x21ce8,
1063                 0x21cf0, 0x21cf0,
1064                 0x21cf8, 0x21d7c,
1065                 0x21e00, 0x21e04,
1066                 0x22000, 0x2202c,
1067                 0x22100, 0x2213c,
1068                 0x22190, 0x221a0,
1069                 0x221a8, 0x221b8,
1070                 0x221c4, 0x221c8,
1071                 0x22200, 0x22318,
1072                 0x22400, 0x224b4,
1073                 0x224c0, 0x22528,
1074                 0x22540, 0x22614,
1075                 0x23000, 0x23040,
1076                 0x2304c, 0x23060,
1077                 0x230c0, 0x230ec,
1078                 0x23200, 0x23268,
1079                 0x23270, 0x23284,
1080                 0x232fc, 0x23388,
1081                 0x23400, 0x23404,
1082                 0x23500, 0x23500,
1083                 0x23510, 0x23518,
1084                 0x2352c, 0x23530,
1085                 0x2353c, 0x2353c,
1086                 0x23550, 0x23554,
1087                 0x23600, 0x23600,
1088                 0x23608, 0x2361c,
1089                 0x23624, 0x23628,
1090                 0x23630, 0x23634,
1091                 0x2363c, 0x2363c,
1092                 0x23700, 0x2371c,
1093                 0x23780, 0x2378c,
1094                 0x23800, 0x23818,
1095                 0x23820, 0x23828,
1096                 0x23830, 0x23848,
1097                 0x23850, 0x23854,
1098                 0x23860, 0x23868,
1099                 0x23870, 0x23870,
1100                 0x23878, 0x23898,
1101                 0x238a0, 0x238a8,
1102                 0x238b0, 0x238c8,
1103                 0x238d0, 0x238d4,
1104                 0x238e0, 0x238e8,
1105                 0x238f0, 0x238f0,
1106                 0x238f8, 0x23a18,
1107                 0x23a20, 0x23a28,
1108                 0x23a30, 0x23a48,
1109                 0x23a50, 0x23a54,
1110                 0x23a60, 0x23a68,
1111                 0x23a70, 0x23a70,
1112                 0x23a78, 0x23a98,
1113                 0x23aa0, 0x23aa8,
1114                 0x23ab0, 0x23ac8,
1115                 0x23ad0, 0x23ad4,
1116                 0x23ae0, 0x23ae8,
1117                 0x23af0, 0x23af0,
1118                 0x23af8, 0x23c18,
1119                 0x23c20, 0x23c20,
1120                 0x23c28, 0x23c30,
1121                 0x23c38, 0x23c38,
1122                 0x23c80, 0x23c98,
1123                 0x23ca0, 0x23ca8,
1124                 0x23cb0, 0x23cc8,
1125                 0x23cd0, 0x23cd4,
1126                 0x23ce0, 0x23ce8,
1127                 0x23cf0, 0x23cf0,
1128                 0x23cf8, 0x23d7c,
1129                 0x23e00, 0x23e04,
1130                 0x24000, 0x2402c,
1131                 0x24100, 0x2413c,
1132                 0x24190, 0x241a0,
1133                 0x241a8, 0x241b8,
1134                 0x241c4, 0x241c8,
1135                 0x24200, 0x24318,
1136                 0x24400, 0x244b4,
1137                 0x244c0, 0x24528,
1138                 0x24540, 0x24614,
1139                 0x25000, 0x25040,
1140                 0x2504c, 0x25060,
1141                 0x250c0, 0x250ec,
1142                 0x25200, 0x25268,
1143                 0x25270, 0x25284,
1144                 0x252fc, 0x25388,
1145                 0x25400, 0x25404,
1146                 0x25500, 0x25500,
1147                 0x25510, 0x25518,
1148                 0x2552c, 0x25530,
1149                 0x2553c, 0x2553c,
1150                 0x25550, 0x25554,
1151                 0x25600, 0x25600,
1152                 0x25608, 0x2561c,
1153                 0x25624, 0x25628,
1154                 0x25630, 0x25634,
1155                 0x2563c, 0x2563c,
1156                 0x25700, 0x2571c,
1157                 0x25780, 0x2578c,
1158                 0x25800, 0x25818,
1159                 0x25820, 0x25828,
1160                 0x25830, 0x25848,
1161                 0x25850, 0x25854,
1162                 0x25860, 0x25868,
1163                 0x25870, 0x25870,
1164                 0x25878, 0x25898,
1165                 0x258a0, 0x258a8,
1166                 0x258b0, 0x258c8,
1167                 0x258d0, 0x258d4,
1168                 0x258e0, 0x258e8,
1169                 0x258f0, 0x258f0,
1170                 0x258f8, 0x25a18,
1171                 0x25a20, 0x25a28,
1172                 0x25a30, 0x25a48,
1173                 0x25a50, 0x25a54,
1174                 0x25a60, 0x25a68,
1175                 0x25a70, 0x25a70,
1176                 0x25a78, 0x25a98,
1177                 0x25aa0, 0x25aa8,
1178                 0x25ab0, 0x25ac8,
1179                 0x25ad0, 0x25ad4,
1180                 0x25ae0, 0x25ae8,
1181                 0x25af0, 0x25af0,
1182                 0x25af8, 0x25c18,
1183                 0x25c20, 0x25c20,
1184                 0x25c28, 0x25c30,
1185                 0x25c38, 0x25c38,
1186                 0x25c80, 0x25c98,
1187                 0x25ca0, 0x25ca8,
1188                 0x25cb0, 0x25cc8,
1189                 0x25cd0, 0x25cd4,
1190                 0x25ce0, 0x25ce8,
1191                 0x25cf0, 0x25cf0,
1192                 0x25cf8, 0x25d7c,
1193                 0x25e00, 0x25e04,
1194                 0x26000, 0x2602c,
1195                 0x26100, 0x2613c,
1196                 0x26190, 0x261a0,
1197                 0x261a8, 0x261b8,
1198                 0x261c4, 0x261c8,
1199                 0x26200, 0x26318,
1200                 0x26400, 0x264b4,
1201                 0x264c0, 0x26528,
1202                 0x26540, 0x26614,
1203                 0x27000, 0x27040,
1204                 0x2704c, 0x27060,
1205                 0x270c0, 0x270ec,
1206                 0x27200, 0x27268,
1207                 0x27270, 0x27284,
1208                 0x272fc, 0x27388,
1209                 0x27400, 0x27404,
1210                 0x27500, 0x27500,
1211                 0x27510, 0x27518,
1212                 0x2752c, 0x27530,
1213                 0x2753c, 0x2753c,
1214                 0x27550, 0x27554,
1215                 0x27600, 0x27600,
1216                 0x27608, 0x2761c,
1217                 0x27624, 0x27628,
1218                 0x27630, 0x27634,
1219                 0x2763c, 0x2763c,
1220                 0x27700, 0x2771c,
1221                 0x27780, 0x2778c,
1222                 0x27800, 0x27818,
1223                 0x27820, 0x27828,
1224                 0x27830, 0x27848,
1225                 0x27850, 0x27854,
1226                 0x27860, 0x27868,
1227                 0x27870, 0x27870,
1228                 0x27878, 0x27898,
1229                 0x278a0, 0x278a8,
1230                 0x278b0, 0x278c8,
1231                 0x278d0, 0x278d4,
1232                 0x278e0, 0x278e8,
1233                 0x278f0, 0x278f0,
1234                 0x278f8, 0x27a18,
1235                 0x27a20, 0x27a28,
1236                 0x27a30, 0x27a48,
1237                 0x27a50, 0x27a54,
1238                 0x27a60, 0x27a68,
1239                 0x27a70, 0x27a70,
1240                 0x27a78, 0x27a98,
1241                 0x27aa0, 0x27aa8,
1242                 0x27ab0, 0x27ac8,
1243                 0x27ad0, 0x27ad4,
1244                 0x27ae0, 0x27ae8,
1245                 0x27af0, 0x27af0,
1246                 0x27af8, 0x27c18,
1247                 0x27c20, 0x27c20,
1248                 0x27c28, 0x27c30,
1249                 0x27c38, 0x27c38,
1250                 0x27c80, 0x27c98,
1251                 0x27ca0, 0x27ca8,
1252                 0x27cb0, 0x27cc8,
1253                 0x27cd0, 0x27cd4,
1254                 0x27ce0, 0x27ce8,
1255                 0x27cf0, 0x27cf0,
1256                 0x27cf8, 0x27d7c,
1257                 0x27e00, 0x27e04,
1258         };
1259
1260         static const unsigned int t5_reg_ranges[] = {
1261                 0x1008, 0x10c0,
1262                 0x10cc, 0x10f8,
1263                 0x1100, 0x1100,
1264                 0x110c, 0x1148,
1265                 0x1180, 0x1184,
1266                 0x1190, 0x1194,
1267                 0x11a0, 0x11a4,
1268                 0x11b0, 0x11b4,
1269                 0x11fc, 0x123c,
1270                 0x1280, 0x173c,
1271                 0x1800, 0x18fc,
1272                 0x3000, 0x3028,
1273                 0x3060, 0x30b0,
1274                 0x30b8, 0x30d8,
1275                 0x30e0, 0x30fc,
1276                 0x3140, 0x357c,
1277                 0x35a8, 0x35cc,
1278                 0x35ec, 0x35ec,
1279                 0x3600, 0x5624,
1280                 0x56cc, 0x56ec,
1281                 0x56f4, 0x5720,
1282                 0x5728, 0x575c,
1283                 0x580c, 0x5814,
1284                 0x5890, 0x589c,
1285                 0x58a4, 0x58ac,
1286                 0x58b8, 0x58bc,
1287                 0x5940, 0x59c8,
1288                 0x59d0, 0x59dc,
1289                 0x59fc, 0x5a18,
1290                 0x5a60, 0x5a70,
1291                 0x5a80, 0x5a9c,
1292                 0x5b94, 0x5bfc,
1293                 0x6000, 0x6020,
1294                 0x6028, 0x6040,
1295                 0x6058, 0x609c,
1296                 0x60a8, 0x614c,
1297                 0x7700, 0x7798,
1298                 0x77c0, 0x78fc,
1299                 0x7b00, 0x7b58,
1300                 0x7b60, 0x7b84,
1301                 0x7b8c, 0x7c54,
1302                 0x7d00, 0x7d38,
1303                 0x7d40, 0x7d80,
1304                 0x7d8c, 0x7ddc,
1305                 0x7de4, 0x7e04,
1306                 0x7e10, 0x7e1c,
1307                 0x7e24, 0x7e38,
1308                 0x7e40, 0x7e44,
1309                 0x7e4c, 0x7e78,
1310                 0x7e80, 0x7edc,
1311                 0x7ee8, 0x7efc,
1312                 0x8dc0, 0x8de0,
1313                 0x8df8, 0x8e04,
1314                 0x8e10, 0x8e84,
1315                 0x8ea0, 0x8f84,
1316                 0x8fc0, 0x9058,
1317                 0x9060, 0x9060,
1318                 0x9068, 0x90f8,
1319                 0x9400, 0x9408,
1320                 0x9410, 0x9470,
1321                 0x9600, 0x9600,
1322                 0x9608, 0x9638,
1323                 0x9640, 0x96f4,
1324                 0x9800, 0x9808,
1325                 0x9820, 0x983c,
1326                 0x9850, 0x9864,
1327                 0x9c00, 0x9c6c,
1328                 0x9c80, 0x9cec,
1329                 0x9d00, 0x9d6c,
1330                 0x9d80, 0x9dec,
1331                 0x9e00, 0x9e6c,
1332                 0x9e80, 0x9eec,
1333                 0x9f00, 0x9f6c,
1334                 0x9f80, 0xa020,
1335                 0xd004, 0xd004,
1336                 0xd010, 0xd03c,
1337                 0xdfc0, 0xdfe0,
1338                 0xe000, 0x1106c,
1339                 0x11074, 0x11088,
1340                 0x1109c, 0x1117c,
1341                 0x11190, 0x11204,
1342                 0x19040, 0x1906c,
1343                 0x19078, 0x19080,
1344                 0x1908c, 0x190e8,
1345                 0x190f0, 0x190f8,
1346                 0x19100, 0x19110,
1347                 0x19120, 0x19124,
1348                 0x19150, 0x19194,
1349                 0x1919c, 0x191b0,
1350                 0x191d0, 0x191e8,
1351                 0x19238, 0x19290,
1352                 0x193f8, 0x19428,
1353                 0x19430, 0x19444,
1354                 0x1944c, 0x1946c,
1355                 0x19474, 0x19474,
1356                 0x19490, 0x194cc,
1357                 0x194f0, 0x194f8,
1358                 0x19c00, 0x19c08,
1359                 0x19c10, 0x19c60,
1360                 0x19c94, 0x19ce4,
1361                 0x19cf0, 0x19d40,
1362                 0x19d50, 0x19d94,
1363                 0x19da0, 0x19de8,
1364                 0x19df0, 0x19e10,
1365                 0x19e50, 0x19e90,
1366                 0x19ea0, 0x19f24,
1367                 0x19f34, 0x19f34,
1368                 0x19f40, 0x19f50,
1369                 0x19f90, 0x19fb4,
1370                 0x19fc4, 0x19fe4,
1371                 0x1a000, 0x1a004,
1372                 0x1a010, 0x1a06c,
1373                 0x1a0b0, 0x1a0e4,
1374                 0x1a0ec, 0x1a0f8,
1375                 0x1a100, 0x1a108,
1376                 0x1a114, 0x1a120,
1377                 0x1a128, 0x1a130,
1378                 0x1a138, 0x1a138,
1379                 0x1a190, 0x1a1c4,
1380                 0x1a1fc, 0x1a1fc,
1381                 0x1e008, 0x1e00c,
1382                 0x1e040, 0x1e044,
1383                 0x1e04c, 0x1e04c,
1384                 0x1e284, 0x1e290,
1385                 0x1e2c0, 0x1e2c0,
1386                 0x1e2e0, 0x1e2e0,
1387                 0x1e300, 0x1e384,
1388                 0x1e3c0, 0x1e3c8,
1389                 0x1e408, 0x1e40c,
1390                 0x1e440, 0x1e444,
1391                 0x1e44c, 0x1e44c,
1392                 0x1e684, 0x1e690,
1393                 0x1e6c0, 0x1e6c0,
1394                 0x1e6e0, 0x1e6e0,
1395                 0x1e700, 0x1e784,
1396                 0x1e7c0, 0x1e7c8,
1397                 0x1e808, 0x1e80c,
1398                 0x1e840, 0x1e844,
1399                 0x1e84c, 0x1e84c,
1400                 0x1ea84, 0x1ea90,
1401                 0x1eac0, 0x1eac0,
1402                 0x1eae0, 0x1eae0,
1403                 0x1eb00, 0x1eb84,
1404                 0x1ebc0, 0x1ebc8,
1405                 0x1ec08, 0x1ec0c,
1406                 0x1ec40, 0x1ec44,
1407                 0x1ec4c, 0x1ec4c,
1408                 0x1ee84, 0x1ee90,
1409                 0x1eec0, 0x1eec0,
1410                 0x1eee0, 0x1eee0,
1411                 0x1ef00, 0x1ef84,
1412                 0x1efc0, 0x1efc8,
1413                 0x1f008, 0x1f00c,
1414                 0x1f040, 0x1f044,
1415                 0x1f04c, 0x1f04c,
1416                 0x1f284, 0x1f290,
1417                 0x1f2c0, 0x1f2c0,
1418                 0x1f2e0, 0x1f2e0,
1419                 0x1f300, 0x1f384,
1420                 0x1f3c0, 0x1f3c8,
1421                 0x1f408, 0x1f40c,
1422                 0x1f440, 0x1f444,
1423                 0x1f44c, 0x1f44c,
1424                 0x1f684, 0x1f690,
1425                 0x1f6c0, 0x1f6c0,
1426                 0x1f6e0, 0x1f6e0,
1427                 0x1f700, 0x1f784,
1428                 0x1f7c0, 0x1f7c8,
1429                 0x1f808, 0x1f80c,
1430                 0x1f840, 0x1f844,
1431                 0x1f84c, 0x1f84c,
1432                 0x1fa84, 0x1fa90,
1433                 0x1fac0, 0x1fac0,
1434                 0x1fae0, 0x1fae0,
1435                 0x1fb00, 0x1fb84,
1436                 0x1fbc0, 0x1fbc8,
1437                 0x1fc08, 0x1fc0c,
1438                 0x1fc40, 0x1fc44,
1439                 0x1fc4c, 0x1fc4c,
1440                 0x1fe84, 0x1fe90,
1441                 0x1fec0, 0x1fec0,
1442                 0x1fee0, 0x1fee0,
1443                 0x1ff00, 0x1ff84,
1444                 0x1ffc0, 0x1ffc8,
1445                 0x30000, 0x30030,
1446                 0x30100, 0x30144,
1447                 0x30190, 0x301a0,
1448                 0x301a8, 0x301b8,
1449                 0x301c4, 0x301c8,
1450                 0x301d0, 0x301d0,
1451                 0x30200, 0x30318,
1452                 0x30400, 0x304b4,
1453                 0x304c0, 0x3052c,
1454                 0x30540, 0x3061c,
1455                 0x30800, 0x30828,
1456                 0x30834, 0x30834,
1457                 0x308c0, 0x30908,
1458                 0x30910, 0x309ac,
1459                 0x30a00, 0x30a14,
1460                 0x30a1c, 0x30a2c,
1461                 0x30a44, 0x30a50,
1462                 0x30a74, 0x30a74,
1463                 0x30a7c, 0x30afc,
1464                 0x30b08, 0x30c24,
1465                 0x30d00, 0x30d00,
1466                 0x30d08, 0x30d14,
1467                 0x30d1c, 0x30d20,
1468                 0x30d3c, 0x30d3c,
1469                 0x30d48, 0x30d50,
1470                 0x31200, 0x3120c,
1471                 0x31220, 0x31220,
1472                 0x31240, 0x31240,
1473                 0x31600, 0x3160c,
1474                 0x31a00, 0x31a1c,
1475                 0x31e00, 0x31e20,
1476                 0x31e38, 0x31e3c,
1477                 0x31e80, 0x31e80,
1478                 0x31e88, 0x31ea8,
1479                 0x31eb0, 0x31eb4,
1480                 0x31ec8, 0x31ed4,
1481                 0x31fb8, 0x32004,
1482                 0x32200, 0x32200,
1483                 0x32208, 0x32240,
1484                 0x32248, 0x32280,
1485                 0x32288, 0x322c0,
1486                 0x322c8, 0x322fc,
1487                 0x32600, 0x32630,
1488                 0x32a00, 0x32abc,
1489                 0x32b00, 0x32b10,
1490                 0x32b20, 0x32b30,
1491                 0x32b40, 0x32b50,
1492                 0x32b60, 0x32b70,
1493                 0x33000, 0x33028,
1494                 0x33030, 0x33048,
1495                 0x33060, 0x33068,
1496                 0x33070, 0x3309c,
1497                 0x330f0, 0x33128,
1498                 0x33130, 0x33148,
1499                 0x33160, 0x33168,
1500                 0x33170, 0x3319c,
1501                 0x331f0, 0x33238,
1502                 0x33240, 0x33240,
1503                 0x33248, 0x33250,
1504                 0x3325c, 0x33264,
1505                 0x33270, 0x332b8,
1506                 0x332c0, 0x332e4,
1507                 0x332f8, 0x33338,
1508                 0x33340, 0x33340,
1509                 0x33348, 0x33350,
1510                 0x3335c, 0x33364,
1511                 0x33370, 0x333b8,
1512                 0x333c0, 0x333e4,
1513                 0x333f8, 0x33428,
1514                 0x33430, 0x33448,
1515                 0x33460, 0x33468,
1516                 0x33470, 0x3349c,
1517                 0x334f0, 0x33528,
1518                 0x33530, 0x33548,
1519                 0x33560, 0x33568,
1520                 0x33570, 0x3359c,
1521                 0x335f0, 0x33638,
1522                 0x33640, 0x33640,
1523                 0x33648, 0x33650,
1524                 0x3365c, 0x33664,
1525                 0x33670, 0x336b8,
1526                 0x336c0, 0x336e4,
1527                 0x336f8, 0x33738,
1528                 0x33740, 0x33740,
1529                 0x33748, 0x33750,
1530                 0x3375c, 0x33764,
1531                 0x33770, 0x337b8,
1532                 0x337c0, 0x337e4,
1533                 0x337f8, 0x337fc,
1534                 0x33814, 0x33814,
1535                 0x3382c, 0x3382c,
1536                 0x33880, 0x3388c,
1537                 0x338e8, 0x338ec,
1538                 0x33900, 0x33928,
1539                 0x33930, 0x33948,
1540                 0x33960, 0x33968,
1541                 0x33970, 0x3399c,
1542                 0x339f0, 0x33a38,
1543                 0x33a40, 0x33a40,
1544                 0x33a48, 0x33a50,
1545                 0x33a5c, 0x33a64,
1546                 0x33a70, 0x33ab8,
1547                 0x33ac0, 0x33ae4,
1548                 0x33af8, 0x33b10,
1549                 0x33b28, 0x33b28,
1550                 0x33b3c, 0x33b50,
1551                 0x33bf0, 0x33c10,
1552                 0x33c28, 0x33c28,
1553                 0x33c3c, 0x33c50,
1554                 0x33cf0, 0x33cfc,
1555                 0x34000, 0x34030,
1556                 0x34100, 0x34144,
1557                 0x34190, 0x341a0,
1558                 0x341a8, 0x341b8,
1559                 0x341c4, 0x341c8,
1560                 0x341d0, 0x341d0,
1561                 0x34200, 0x34318,
1562                 0x34400, 0x344b4,
1563                 0x344c0, 0x3452c,
1564                 0x34540, 0x3461c,
1565                 0x34800, 0x34828,
1566                 0x34834, 0x34834,
1567                 0x348c0, 0x34908,
1568                 0x34910, 0x349ac,
1569                 0x34a00, 0x34a14,
1570                 0x34a1c, 0x34a2c,
1571                 0x34a44, 0x34a50,
1572                 0x34a74, 0x34a74,
1573                 0x34a7c, 0x34afc,
1574                 0x34b08, 0x34c24,
1575                 0x34d00, 0x34d00,
1576                 0x34d08, 0x34d14,
1577                 0x34d1c, 0x34d20,
1578                 0x34d3c, 0x34d3c,
1579                 0x34d48, 0x34d50,
1580                 0x35200, 0x3520c,
1581                 0x35220, 0x35220,
1582                 0x35240, 0x35240,
1583                 0x35600, 0x3560c,
1584                 0x35a00, 0x35a1c,
1585                 0x35e00, 0x35e20,
1586                 0x35e38, 0x35e3c,
1587                 0x35e80, 0x35e80,
1588                 0x35e88, 0x35ea8,
1589                 0x35eb0, 0x35eb4,
1590                 0x35ec8, 0x35ed4,
1591                 0x35fb8, 0x36004,
1592                 0x36200, 0x36200,
1593                 0x36208, 0x36240,
1594                 0x36248, 0x36280,
1595                 0x36288, 0x362c0,
1596                 0x362c8, 0x362fc,
1597                 0x36600, 0x36630,
1598                 0x36a00, 0x36abc,
1599                 0x36b00, 0x36b10,
1600                 0x36b20, 0x36b30,
1601                 0x36b40, 0x36b50,
1602                 0x36b60, 0x36b70,
1603                 0x37000, 0x37028,
1604                 0x37030, 0x37048,
1605                 0x37060, 0x37068,
1606                 0x37070, 0x3709c,
1607                 0x370f0, 0x37128,
1608                 0x37130, 0x37148,
1609                 0x37160, 0x37168,
1610                 0x37170, 0x3719c,
1611                 0x371f0, 0x37238,
1612                 0x37240, 0x37240,
1613                 0x37248, 0x37250,
1614                 0x3725c, 0x37264,
1615                 0x37270, 0x372b8,
1616                 0x372c0, 0x372e4,
1617                 0x372f8, 0x37338,
1618                 0x37340, 0x37340,
1619                 0x37348, 0x37350,
1620                 0x3735c, 0x37364,
1621                 0x37370, 0x373b8,
1622                 0x373c0, 0x373e4,
1623                 0x373f8, 0x37428,
1624                 0x37430, 0x37448,
1625                 0x37460, 0x37468,
1626                 0x37470, 0x3749c,
1627                 0x374f0, 0x37528,
1628                 0x37530, 0x37548,
1629                 0x37560, 0x37568,
1630                 0x37570, 0x3759c,
1631                 0x375f0, 0x37638,
1632                 0x37640, 0x37640,
1633                 0x37648, 0x37650,
1634                 0x3765c, 0x37664,
1635                 0x37670, 0x376b8,
1636                 0x376c0, 0x376e4,
1637                 0x376f8, 0x37738,
1638                 0x37740, 0x37740,
1639                 0x37748, 0x37750,
1640                 0x3775c, 0x37764,
1641                 0x37770, 0x377b8,
1642                 0x377c0, 0x377e4,
1643                 0x377f8, 0x377fc,
1644                 0x37814, 0x37814,
1645                 0x3782c, 0x3782c,
1646                 0x37880, 0x3788c,
1647                 0x378e8, 0x378ec,
1648                 0x37900, 0x37928,
1649                 0x37930, 0x37948,
1650                 0x37960, 0x37968,
1651                 0x37970, 0x3799c,
1652                 0x379f0, 0x37a38,
1653                 0x37a40, 0x37a40,
1654                 0x37a48, 0x37a50,
1655                 0x37a5c, 0x37a64,
1656                 0x37a70, 0x37ab8,
1657                 0x37ac0, 0x37ae4,
1658                 0x37af8, 0x37b10,
1659                 0x37b28, 0x37b28,
1660                 0x37b3c, 0x37b50,
1661                 0x37bf0, 0x37c10,
1662                 0x37c28, 0x37c28,
1663                 0x37c3c, 0x37c50,
1664                 0x37cf0, 0x37cfc,
1665                 0x38000, 0x38030,
1666                 0x38100, 0x38144,
1667                 0x38190, 0x381a0,
1668                 0x381a8, 0x381b8,
1669                 0x381c4, 0x381c8,
1670                 0x381d0, 0x381d0,
1671                 0x38200, 0x38318,
1672                 0x38400, 0x384b4,
1673                 0x384c0, 0x3852c,
1674                 0x38540, 0x3861c,
1675                 0x38800, 0x38828,
1676                 0x38834, 0x38834,
1677                 0x388c0, 0x38908,
1678                 0x38910, 0x389ac,
1679                 0x38a00, 0x38a14,
1680                 0x38a1c, 0x38a2c,
1681                 0x38a44, 0x38a50,
1682                 0x38a74, 0x38a74,
1683                 0x38a7c, 0x38afc,
1684                 0x38b08, 0x38c24,
1685                 0x38d00, 0x38d00,
1686                 0x38d08, 0x38d14,
1687                 0x38d1c, 0x38d20,
1688                 0x38d3c, 0x38d3c,
1689                 0x38d48, 0x38d50,
1690                 0x39200, 0x3920c,
1691                 0x39220, 0x39220,
1692                 0x39240, 0x39240,
1693                 0x39600, 0x3960c,
1694                 0x39a00, 0x39a1c,
1695                 0x39e00, 0x39e20,
1696                 0x39e38, 0x39e3c,
1697                 0x39e80, 0x39e80,
1698                 0x39e88, 0x39ea8,
1699                 0x39eb0, 0x39eb4,
1700                 0x39ec8, 0x39ed4,
1701                 0x39fb8, 0x3a004,
1702                 0x3a200, 0x3a200,
1703                 0x3a208, 0x3a240,
1704                 0x3a248, 0x3a280,
1705                 0x3a288, 0x3a2c0,
1706                 0x3a2c8, 0x3a2fc,
1707                 0x3a600, 0x3a630,
1708                 0x3aa00, 0x3aabc,
1709                 0x3ab00, 0x3ab10,
1710                 0x3ab20, 0x3ab30,
1711                 0x3ab40, 0x3ab50,
1712                 0x3ab60, 0x3ab70,
1713                 0x3b000, 0x3b028,
1714                 0x3b030, 0x3b048,
1715                 0x3b060, 0x3b068,
1716                 0x3b070, 0x3b09c,
1717                 0x3b0f0, 0x3b128,
1718                 0x3b130, 0x3b148,
1719                 0x3b160, 0x3b168,
1720                 0x3b170, 0x3b19c,
1721                 0x3b1f0, 0x3b238,
1722                 0x3b240, 0x3b240,
1723                 0x3b248, 0x3b250,
1724                 0x3b25c, 0x3b264,
1725                 0x3b270, 0x3b2b8,
1726                 0x3b2c0, 0x3b2e4,
1727                 0x3b2f8, 0x3b338,
1728                 0x3b340, 0x3b340,
1729                 0x3b348, 0x3b350,
1730                 0x3b35c, 0x3b364,
1731                 0x3b370, 0x3b3b8,
1732                 0x3b3c0, 0x3b3e4,
1733                 0x3b3f8, 0x3b428,
1734                 0x3b430, 0x3b448,
1735                 0x3b460, 0x3b468,
1736                 0x3b470, 0x3b49c,
1737                 0x3b4f0, 0x3b528,
1738                 0x3b530, 0x3b548,
1739                 0x3b560, 0x3b568,
1740                 0x3b570, 0x3b59c,
1741                 0x3b5f0, 0x3b638,
1742                 0x3b640, 0x3b640,
1743                 0x3b648, 0x3b650,
1744                 0x3b65c, 0x3b664,
1745                 0x3b670, 0x3b6b8,
1746                 0x3b6c0, 0x3b6e4,
1747                 0x3b6f8, 0x3b738,
1748                 0x3b740, 0x3b740,
1749                 0x3b748, 0x3b750,
1750                 0x3b75c, 0x3b764,
1751                 0x3b770, 0x3b7b8,
1752                 0x3b7c0, 0x3b7e4,
1753                 0x3b7f8, 0x3b7fc,
1754                 0x3b814, 0x3b814,
1755                 0x3b82c, 0x3b82c,
1756                 0x3b880, 0x3b88c,
1757                 0x3b8e8, 0x3b8ec,
1758                 0x3b900, 0x3b928,
1759                 0x3b930, 0x3b948,
1760                 0x3b960, 0x3b968,
1761                 0x3b970, 0x3b99c,
1762                 0x3b9f0, 0x3ba38,
1763                 0x3ba40, 0x3ba40,
1764                 0x3ba48, 0x3ba50,
1765                 0x3ba5c, 0x3ba64,
1766                 0x3ba70, 0x3bab8,
1767                 0x3bac0, 0x3bae4,
1768                 0x3baf8, 0x3bb10,
1769                 0x3bb28, 0x3bb28,
1770                 0x3bb3c, 0x3bb50,
1771                 0x3bbf0, 0x3bc10,
1772                 0x3bc28, 0x3bc28,
1773                 0x3bc3c, 0x3bc50,
1774                 0x3bcf0, 0x3bcfc,
1775                 0x3c000, 0x3c030,
1776                 0x3c100, 0x3c144,
1777                 0x3c190, 0x3c1a0,
1778                 0x3c1a8, 0x3c1b8,
1779                 0x3c1c4, 0x3c1c8,
1780                 0x3c1d0, 0x3c1d0,
1781                 0x3c200, 0x3c318,
1782                 0x3c400, 0x3c4b4,
1783                 0x3c4c0, 0x3c52c,
1784                 0x3c540, 0x3c61c,
1785                 0x3c800, 0x3c828,
1786                 0x3c834, 0x3c834,
1787                 0x3c8c0, 0x3c908,
1788                 0x3c910, 0x3c9ac,
1789                 0x3ca00, 0x3ca14,
1790                 0x3ca1c, 0x3ca2c,
1791                 0x3ca44, 0x3ca50,
1792                 0x3ca74, 0x3ca74,
1793                 0x3ca7c, 0x3cafc,
1794                 0x3cb08, 0x3cc24,
1795                 0x3cd00, 0x3cd00,
1796                 0x3cd08, 0x3cd14,
1797                 0x3cd1c, 0x3cd20,
1798                 0x3cd3c, 0x3cd3c,
1799                 0x3cd48, 0x3cd50,
1800                 0x3d200, 0x3d20c,
1801                 0x3d220, 0x3d220,
1802                 0x3d240, 0x3d240,
1803                 0x3d600, 0x3d60c,
1804                 0x3da00, 0x3da1c,
1805                 0x3de00, 0x3de20,
1806                 0x3de38, 0x3de3c,
1807                 0x3de80, 0x3de80,
1808                 0x3de88, 0x3dea8,
1809                 0x3deb0, 0x3deb4,
1810                 0x3dec8, 0x3ded4,
1811                 0x3dfb8, 0x3e004,
1812                 0x3e200, 0x3e200,
1813                 0x3e208, 0x3e240,
1814                 0x3e248, 0x3e280,
1815                 0x3e288, 0x3e2c0,
1816                 0x3e2c8, 0x3e2fc,
1817                 0x3e600, 0x3e630,
1818                 0x3ea00, 0x3eabc,
1819                 0x3eb00, 0x3eb10,
1820                 0x3eb20, 0x3eb30,
1821                 0x3eb40, 0x3eb50,
1822                 0x3eb60, 0x3eb70,
1823                 0x3f000, 0x3f028,
1824                 0x3f030, 0x3f048,
1825                 0x3f060, 0x3f068,
1826                 0x3f070, 0x3f09c,
1827                 0x3f0f0, 0x3f128,
1828                 0x3f130, 0x3f148,
1829                 0x3f160, 0x3f168,
1830                 0x3f170, 0x3f19c,
1831                 0x3f1f0, 0x3f238,
1832                 0x3f240, 0x3f240,
1833                 0x3f248, 0x3f250,
1834                 0x3f25c, 0x3f264,
1835                 0x3f270, 0x3f2b8,
1836                 0x3f2c0, 0x3f2e4,
1837                 0x3f2f8, 0x3f338,
1838                 0x3f340, 0x3f340,
1839                 0x3f348, 0x3f350,
1840                 0x3f35c, 0x3f364,
1841                 0x3f370, 0x3f3b8,
1842                 0x3f3c0, 0x3f3e4,
1843                 0x3f3f8, 0x3f428,
1844                 0x3f430, 0x3f448,
1845                 0x3f460, 0x3f468,
1846                 0x3f470, 0x3f49c,
1847                 0x3f4f0, 0x3f528,
1848                 0x3f530, 0x3f548,
1849                 0x3f560, 0x3f568,
1850                 0x3f570, 0x3f59c,
1851                 0x3f5f0, 0x3f638,
1852                 0x3f640, 0x3f640,
1853                 0x3f648, 0x3f650,
1854                 0x3f65c, 0x3f664,
1855                 0x3f670, 0x3f6b8,
1856                 0x3f6c0, 0x3f6e4,
1857                 0x3f6f8, 0x3f738,
1858                 0x3f740, 0x3f740,
1859                 0x3f748, 0x3f750,
1860                 0x3f75c, 0x3f764,
1861                 0x3f770, 0x3f7b8,
1862                 0x3f7c0, 0x3f7e4,
1863                 0x3f7f8, 0x3f7fc,
1864                 0x3f814, 0x3f814,
1865                 0x3f82c, 0x3f82c,
1866                 0x3f880, 0x3f88c,
1867                 0x3f8e8, 0x3f8ec,
1868                 0x3f900, 0x3f928,
1869                 0x3f930, 0x3f948,
1870                 0x3f960, 0x3f968,
1871                 0x3f970, 0x3f99c,
1872                 0x3f9f0, 0x3fa38,
1873                 0x3fa40, 0x3fa40,
1874                 0x3fa48, 0x3fa50,
1875                 0x3fa5c, 0x3fa64,
1876                 0x3fa70, 0x3fab8,
1877                 0x3fac0, 0x3fae4,
1878                 0x3faf8, 0x3fb10,
1879                 0x3fb28, 0x3fb28,
1880                 0x3fb3c, 0x3fb50,
1881                 0x3fbf0, 0x3fc10,
1882                 0x3fc28, 0x3fc28,
1883                 0x3fc3c, 0x3fc50,
1884                 0x3fcf0, 0x3fcfc,
1885                 0x40000, 0x4000c,
1886                 0x40040, 0x40050,
1887                 0x40060, 0x40068,
1888                 0x4007c, 0x4008c,
1889                 0x40094, 0x400b0,
1890                 0x400c0, 0x40144,
1891                 0x40180, 0x4018c,
1892                 0x40200, 0x40254,
1893                 0x40260, 0x40264,
1894                 0x40270, 0x40288,
1895                 0x40290, 0x40298,
1896                 0x402ac, 0x402c8,
1897                 0x402d0, 0x402e0,
1898                 0x402f0, 0x402f0,
1899                 0x40300, 0x4033c,
1900                 0x403f8, 0x403fc,
1901                 0x41304, 0x413c4,
1902                 0x41400, 0x4140c,
1903                 0x41414, 0x4141c,
1904                 0x41480, 0x414d0,
1905                 0x44000, 0x44054,
1906                 0x4405c, 0x44078,
1907                 0x440c0, 0x44174,
1908                 0x44180, 0x441ac,
1909                 0x441b4, 0x441b8,
1910                 0x441c0, 0x44254,
1911                 0x4425c, 0x44278,
1912                 0x442c0, 0x44374,
1913                 0x44380, 0x443ac,
1914                 0x443b4, 0x443b8,
1915                 0x443c0, 0x44454,
1916                 0x4445c, 0x44478,
1917                 0x444c0, 0x44574,
1918                 0x44580, 0x445ac,
1919                 0x445b4, 0x445b8,
1920                 0x445c0, 0x44654,
1921                 0x4465c, 0x44678,
1922                 0x446c0, 0x44774,
1923                 0x44780, 0x447ac,
1924                 0x447b4, 0x447b8,
1925                 0x447c0, 0x44854,
1926                 0x4485c, 0x44878,
1927                 0x448c0, 0x44974,
1928                 0x44980, 0x449ac,
1929                 0x449b4, 0x449b8,
1930                 0x449c0, 0x449fc,
1931                 0x45000, 0x45004,
1932                 0x45010, 0x45030,
1933                 0x45040, 0x45060,
1934                 0x45068, 0x45068,
1935                 0x45080, 0x45084,
1936                 0x450a0, 0x450b0,
1937                 0x45200, 0x45204,
1938                 0x45210, 0x45230,
1939                 0x45240, 0x45260,
1940                 0x45268, 0x45268,
1941                 0x45280, 0x45284,
1942                 0x452a0, 0x452b0,
1943                 0x460c0, 0x460e4,
1944                 0x47000, 0x4703c,
1945                 0x47044, 0x4708c,
1946                 0x47200, 0x47250,
1947                 0x47400, 0x47408,
1948                 0x47414, 0x47420,
1949                 0x47600, 0x47618,
1950                 0x47800, 0x47814,
1951                 0x48000, 0x4800c,
1952                 0x48040, 0x48050,
1953                 0x48060, 0x48068,
1954                 0x4807c, 0x4808c,
1955                 0x48094, 0x480b0,
1956                 0x480c0, 0x48144,
1957                 0x48180, 0x4818c,
1958                 0x48200, 0x48254,
1959                 0x48260, 0x48264,
1960                 0x48270, 0x48288,
1961                 0x48290, 0x48298,
1962                 0x482ac, 0x482c8,
1963                 0x482d0, 0x482e0,
1964                 0x482f0, 0x482f0,
1965                 0x48300, 0x4833c,
1966                 0x483f8, 0x483fc,
1967                 0x49304, 0x493c4,
1968                 0x49400, 0x4940c,
1969                 0x49414, 0x4941c,
1970                 0x49480, 0x494d0,
1971                 0x4c000, 0x4c054,
1972                 0x4c05c, 0x4c078,
1973                 0x4c0c0, 0x4c174,
1974                 0x4c180, 0x4c1ac,
1975                 0x4c1b4, 0x4c1b8,
1976                 0x4c1c0, 0x4c254,
1977                 0x4c25c, 0x4c278,
1978                 0x4c2c0, 0x4c374,
1979                 0x4c380, 0x4c3ac,
1980                 0x4c3b4, 0x4c3b8,
1981                 0x4c3c0, 0x4c454,
1982                 0x4c45c, 0x4c478,
1983                 0x4c4c0, 0x4c574,
1984                 0x4c580, 0x4c5ac,
1985                 0x4c5b4, 0x4c5b8,
1986                 0x4c5c0, 0x4c654,
1987                 0x4c65c, 0x4c678,
1988                 0x4c6c0, 0x4c774,
1989                 0x4c780, 0x4c7ac,
1990                 0x4c7b4, 0x4c7b8,
1991                 0x4c7c0, 0x4c854,
1992                 0x4c85c, 0x4c878,
1993                 0x4c8c0, 0x4c974,
1994                 0x4c980, 0x4c9ac,
1995                 0x4c9b4, 0x4c9b8,
1996                 0x4c9c0, 0x4c9fc,
1997                 0x4d000, 0x4d004,
1998                 0x4d010, 0x4d030,
1999                 0x4d040, 0x4d060,
2000                 0x4d068, 0x4d068,
2001                 0x4d080, 0x4d084,
2002                 0x4d0a0, 0x4d0b0,
2003                 0x4d200, 0x4d204,
2004                 0x4d210, 0x4d230,
2005                 0x4d240, 0x4d260,
2006                 0x4d268, 0x4d268,
2007                 0x4d280, 0x4d284,
2008                 0x4d2a0, 0x4d2b0,
2009                 0x4e0c0, 0x4e0e4,
2010                 0x4f000, 0x4f03c,
2011                 0x4f044, 0x4f08c,
2012                 0x4f200, 0x4f250,
2013                 0x4f400, 0x4f408,
2014                 0x4f414, 0x4f420,
2015                 0x4f600, 0x4f618,
2016                 0x4f800, 0x4f814,
2017                 0x50000, 0x50084,
2018                 0x50090, 0x500cc,
2019                 0x50400, 0x50400,
2020                 0x50800, 0x50884,
2021                 0x50890, 0x508cc,
2022                 0x50c00, 0x50c00,
2023                 0x51000, 0x5101c,
2024                 0x51300, 0x51308,
2025         };
2026
2027         static const unsigned int t6_reg_ranges[] = {
2028                 0x1008, 0x101c,
2029                 0x1024, 0x10a8,
2030                 0x10b4, 0x10f8,
2031                 0x1100, 0x1114,
2032                 0x111c, 0x112c,
2033                 0x1138, 0x113c,
2034                 0x1144, 0x114c,
2035                 0x1180, 0x1184,
2036                 0x1190, 0x1194,
2037                 0x11a0, 0x11a4,
2038                 0x11b0, 0x11b4,
2039                 0x11fc, 0x1274,
2040                 0x1280, 0x133c,
2041                 0x1800, 0x18fc,
2042                 0x3000, 0x302c,
2043                 0x3060, 0x30b0,
2044                 0x30b8, 0x30d8,
2045                 0x30e0, 0x30fc,
2046                 0x3140, 0x357c,
2047                 0x35a8, 0x35cc,
2048                 0x35ec, 0x35ec,
2049                 0x3600, 0x5624,
2050                 0x56cc, 0x56ec,
2051                 0x56f4, 0x5720,
2052                 0x5728, 0x575c,
2053                 0x580c, 0x5814,
2054                 0x5890, 0x589c,
2055                 0x58a4, 0x58ac,
2056                 0x58b8, 0x58bc,
2057                 0x5940, 0x595c,
2058                 0x5980, 0x598c,
2059                 0x59b0, 0x59c8,
2060                 0x59d0, 0x59dc,
2061                 0x59fc, 0x5a18,
2062                 0x5a60, 0x5a6c,
2063                 0x5a80, 0x5a8c,
2064                 0x5a94, 0x5a9c,
2065                 0x5b94, 0x5bfc,
2066                 0x5c10, 0x5e48,
2067                 0x5e50, 0x5e94,
2068                 0x5ea0, 0x5eb0,
2069                 0x5ec0, 0x5ec0,
2070                 0x5ec8, 0x5ed0,
2071                 0x5ee0, 0x5ee0,
2072                 0x5ef0, 0x5ef0,
2073                 0x5f00, 0x5f00,
2074                 0x6000, 0x6020,
2075                 0x6028, 0x6040,
2076                 0x6058, 0x609c,
2077                 0x60a8, 0x619c,
2078                 0x7700, 0x7798,
2079                 0x77c0, 0x7880,
2080                 0x78cc, 0x78fc,
2081                 0x7b00, 0x7b58,
2082                 0x7b60, 0x7b84,
2083                 0x7b8c, 0x7c54,
2084                 0x7d00, 0x7d38,
2085                 0x7d40, 0x7d84,
2086                 0x7d8c, 0x7ddc,
2087                 0x7de4, 0x7e04,
2088                 0x7e10, 0x7e1c,
2089                 0x7e24, 0x7e38,
2090                 0x7e40, 0x7e44,
2091                 0x7e4c, 0x7e78,
2092                 0x7e80, 0x7edc,
2093                 0x7ee8, 0x7efc,
2094                 0x8dc0, 0x8de4,
2095                 0x8df8, 0x8e04,
2096                 0x8e10, 0x8e84,
2097                 0x8ea0, 0x8f88,
2098                 0x8fb8, 0x9058,
2099                 0x9060, 0x9060,
2100                 0x9068, 0x90f8,
2101                 0x9100, 0x9124,
2102                 0x9400, 0x9470,
2103                 0x9600, 0x9600,
2104                 0x9608, 0x9638,
2105                 0x9640, 0x9704,
2106                 0x9710, 0x971c,
2107                 0x9800, 0x9808,
2108                 0x9820, 0x983c,
2109                 0x9850, 0x9864,
2110                 0x9c00, 0x9c6c,
2111                 0x9c80, 0x9cec,
2112                 0x9d00, 0x9d6c,
2113                 0x9d80, 0x9dec,
2114                 0x9e00, 0x9e6c,
2115                 0x9e80, 0x9eec,
2116                 0x9f00, 0x9f6c,
2117                 0x9f80, 0xa020,
2118                 0xd004, 0xd03c,
2119                 0xd100, 0xd118,
2120                 0xd200, 0xd214,
2121                 0xd220, 0xd234,
2122                 0xd240, 0xd254,
2123                 0xd260, 0xd274,
2124                 0xd280, 0xd294,
2125                 0xd2a0, 0xd2b4,
2126                 0xd2c0, 0xd2d4,
2127                 0xd2e0, 0xd2f4,
2128                 0xd300, 0xd31c,
2129                 0xdfc0, 0xdfe0,
2130                 0xe000, 0xf008,
2131                 0xf010, 0xf018,
2132                 0xf020, 0xf028,
2133                 0x11000, 0x11014,
2134                 0x11048, 0x1106c,
2135                 0x11074, 0x11088,
2136                 0x11098, 0x11120,
2137                 0x1112c, 0x1117c,
2138                 0x11190, 0x112e0,
2139                 0x11300, 0x1130c,
2140                 0x12000, 0x1206c,
2141                 0x19040, 0x1906c,
2142                 0x19078, 0x19080,
2143                 0x1908c, 0x190e8,
2144                 0x190f0, 0x190f8,
2145                 0x19100, 0x19110,
2146                 0x19120, 0x19124,
2147                 0x19150, 0x19194,
2148                 0x1919c, 0x191b0,
2149                 0x191d0, 0x191e8,
2150                 0x19238, 0x19290,
2151                 0x192a4, 0x192b0,
2152                 0x192bc, 0x192bc,
2153                 0x19348, 0x1934c,
2154                 0x193f8, 0x19418,
2155                 0x19420, 0x19428,
2156                 0x19430, 0x19444,
2157                 0x1944c, 0x1946c,
2158                 0x19474, 0x19474,
2159                 0x19490, 0x194cc,
2160                 0x194f0, 0x194f8,
2161                 0x19c00, 0x19c48,
2162                 0x19c50, 0x19c80,
2163                 0x19c94, 0x19c98,
2164                 0x19ca0, 0x19cbc,
2165                 0x19ce4, 0x19ce4,
2166                 0x19cf0, 0x19cf8,
2167                 0x19d00, 0x19d28,
2168                 0x19d50, 0x19d78,
2169                 0x19d94, 0x19d98,
2170                 0x19da0, 0x19dc8,
2171                 0x19df0, 0x19e10,
2172                 0x19e50, 0x19e6c,
2173                 0x19ea0, 0x19ebc,
2174                 0x19ec4, 0x19ef4,
2175                 0x19f04, 0x19f2c,
2176                 0x19f34, 0x19f34,
2177                 0x19f40, 0x19f50,
2178                 0x19f90, 0x19fac,
2179                 0x19fc4, 0x19fc8,
2180                 0x19fd0, 0x19fe4,
2181                 0x1a000, 0x1a004,
2182                 0x1a010, 0x1a06c,
2183                 0x1a0b0, 0x1a0e4,
2184                 0x1a0ec, 0x1a0f8,
2185                 0x1a100, 0x1a108,
2186                 0x1a114, 0x1a120,
2187                 0x1a128, 0x1a130,
2188                 0x1a138, 0x1a138,
2189                 0x1a190, 0x1a1c4,
2190                 0x1a1fc, 0x1a1fc,
2191                 0x1e008, 0x1e00c,
2192                 0x1e040, 0x1e044,
2193                 0x1e04c, 0x1e04c,
2194                 0x1e284, 0x1e290,
2195                 0x1e2c0, 0x1e2c0,
2196                 0x1e2e0, 0x1e2e0,
2197                 0x1e300, 0x1e384,
2198                 0x1e3c0, 0x1e3c8,
2199                 0x1e408, 0x1e40c,
2200                 0x1e440, 0x1e444,
2201                 0x1e44c, 0x1e44c,
2202                 0x1e684, 0x1e690,
2203                 0x1e6c0, 0x1e6c0,
2204                 0x1e6e0, 0x1e6e0,
2205                 0x1e700, 0x1e784,
2206                 0x1e7c0, 0x1e7c8,
2207                 0x1e808, 0x1e80c,
2208                 0x1e840, 0x1e844,
2209                 0x1e84c, 0x1e84c,
2210                 0x1ea84, 0x1ea90,
2211                 0x1eac0, 0x1eac0,
2212                 0x1eae0, 0x1eae0,
2213                 0x1eb00, 0x1eb84,
2214                 0x1ebc0, 0x1ebc8,
2215                 0x1ec08, 0x1ec0c,
2216                 0x1ec40, 0x1ec44,
2217                 0x1ec4c, 0x1ec4c,
2218                 0x1ee84, 0x1ee90,
2219                 0x1eec0, 0x1eec0,
2220                 0x1eee0, 0x1eee0,
2221                 0x1ef00, 0x1ef84,
2222                 0x1efc0, 0x1efc8,
2223                 0x1f008, 0x1f00c,
2224                 0x1f040, 0x1f044,
2225                 0x1f04c, 0x1f04c,
2226                 0x1f284, 0x1f290,
2227                 0x1f2c0, 0x1f2c0,
2228                 0x1f2e0, 0x1f2e0,
2229                 0x1f300, 0x1f384,
2230                 0x1f3c0, 0x1f3c8,
2231                 0x1f408, 0x1f40c,
2232                 0x1f440, 0x1f444,
2233                 0x1f44c, 0x1f44c,
2234                 0x1f684, 0x1f690,
2235                 0x1f6c0, 0x1f6c0,
2236                 0x1f6e0, 0x1f6e0,
2237                 0x1f700, 0x1f784,
2238                 0x1f7c0, 0x1f7c8,
2239                 0x1f808, 0x1f80c,
2240                 0x1f840, 0x1f844,
2241                 0x1f84c, 0x1f84c,
2242                 0x1fa84, 0x1fa90,
2243                 0x1fac0, 0x1fac0,
2244                 0x1fae0, 0x1fae0,
2245                 0x1fb00, 0x1fb84,
2246                 0x1fbc0, 0x1fbc8,
2247                 0x1fc08, 0x1fc0c,
2248                 0x1fc40, 0x1fc44,
2249                 0x1fc4c, 0x1fc4c,
2250                 0x1fe84, 0x1fe90,
2251                 0x1fec0, 0x1fec0,
2252                 0x1fee0, 0x1fee0,
2253                 0x1ff00, 0x1ff84,
2254                 0x1ffc0, 0x1ffc8,
2255                 0x30000, 0x30030,
2256                 0x30100, 0x30168,
2257                 0x30190, 0x301a0,
2258                 0x301a8, 0x301b8,
2259                 0x301c4, 0x301c8,
2260                 0x301d0, 0x301d0,
2261                 0x30200, 0x30320,
2262                 0x30400, 0x304b4,
2263                 0x304c0, 0x3052c,
2264                 0x30540, 0x3061c,
2265                 0x30800, 0x308a0,
2266                 0x308c0, 0x30908,
2267                 0x30910, 0x309b8,
2268                 0x30a00, 0x30a04,
2269                 0x30a0c, 0x30a14,
2270                 0x30a1c, 0x30a2c,
2271                 0x30a44, 0x30a50,
2272                 0x30a74, 0x30a74,
2273                 0x30a7c, 0x30afc,
2274                 0x30b08, 0x30c24,
2275                 0x30d00, 0x30d14,
2276                 0x30d1c, 0x30d3c,
2277                 0x30d44, 0x30d4c,
2278                 0x30d54, 0x30d74,
2279                 0x30d7c, 0x30d7c,
2280                 0x30de0, 0x30de0,
2281                 0x30e00, 0x30ed4,
2282                 0x30f00, 0x30fa4,
2283                 0x30fc0, 0x30fc4,
2284                 0x31000, 0x31004,
2285                 0x31080, 0x310fc,
2286                 0x31208, 0x31220,
2287                 0x3123c, 0x31254,
2288                 0x31300, 0x31300,
2289                 0x31308, 0x3131c,
2290                 0x31338, 0x3133c,
2291                 0x31380, 0x31380,
2292                 0x31388, 0x313a8,
2293                 0x313b4, 0x313b4,
2294                 0x31400, 0x31420,
2295                 0x31438, 0x3143c,
2296                 0x31480, 0x31480,
2297                 0x314a8, 0x314a8,
2298                 0x314b0, 0x314b4,
2299                 0x314c8, 0x314d4,
2300                 0x31a40, 0x31a4c,
2301                 0x31af0, 0x31b20,
2302                 0x31b38, 0x31b3c,
2303                 0x31b80, 0x31b80,
2304                 0x31ba8, 0x31ba8,
2305                 0x31bb0, 0x31bb4,
2306                 0x31bc8, 0x31bd4,
2307                 0x32140, 0x3218c,
2308                 0x321f0, 0x321f4,
2309                 0x32200, 0x32200,
2310                 0x32218, 0x32218,
2311                 0x32400, 0x32400,
2312                 0x32408, 0x3241c,
2313                 0x32618, 0x32620,
2314                 0x32664, 0x32664,
2315                 0x326a8, 0x326a8,
2316                 0x326ec, 0x326ec,
2317                 0x32a00, 0x32abc,
2318                 0x32b00, 0x32b18,
2319                 0x32b20, 0x32b38,
2320                 0x32b40, 0x32b58,
2321                 0x32b60, 0x32b78,
2322                 0x32c00, 0x32c00,
2323                 0x32c08, 0x32c3c,
2324                 0x33000, 0x3302c,
2325                 0x33034, 0x33050,
2326                 0x33058, 0x33058,
2327                 0x33060, 0x3308c,
2328                 0x3309c, 0x330ac,
2329                 0x330c0, 0x330c0,
2330                 0x330c8, 0x330d0,
2331                 0x330d8, 0x330e0,
2332                 0x330ec, 0x3312c,
2333                 0x33134, 0x33150,
2334                 0x33158, 0x33158,
2335                 0x33160, 0x3318c,
2336                 0x3319c, 0x331ac,
2337                 0x331c0, 0x331c0,
2338                 0x331c8, 0x331d0,
2339                 0x331d8, 0x331e0,
2340                 0x331ec, 0x33290,
2341                 0x33298, 0x332c4,
2342                 0x332e4, 0x33390,
2343                 0x33398, 0x333c4,
2344                 0x333e4, 0x3342c,
2345                 0x33434, 0x33450,
2346                 0x33458, 0x33458,
2347                 0x33460, 0x3348c,
2348                 0x3349c, 0x334ac,
2349                 0x334c0, 0x334c0,
2350                 0x334c8, 0x334d0,
2351                 0x334d8, 0x334e0,
2352                 0x334ec, 0x3352c,
2353                 0x33534, 0x33550,
2354                 0x33558, 0x33558,
2355                 0x33560, 0x3358c,
2356                 0x3359c, 0x335ac,
2357                 0x335c0, 0x335c0,
2358                 0x335c8, 0x335d0,
2359                 0x335d8, 0x335e0,
2360                 0x335ec, 0x33690,
2361                 0x33698, 0x336c4,
2362                 0x336e4, 0x33790,
2363                 0x33798, 0x337c4,
2364                 0x337e4, 0x337fc,
2365                 0x33814, 0x33814,
2366                 0x33854, 0x33868,
2367                 0x33880, 0x3388c,
2368                 0x338c0, 0x338d0,
2369                 0x338e8, 0x338ec,
2370                 0x33900, 0x3392c,
2371                 0x33934, 0x33950,
2372                 0x33958, 0x33958,
2373                 0x33960, 0x3398c,
2374                 0x3399c, 0x339ac,
2375                 0x339c0, 0x339c0,
2376                 0x339c8, 0x339d0,
2377                 0x339d8, 0x339e0,
2378                 0x339ec, 0x33a90,
2379                 0x33a98, 0x33ac4,
2380                 0x33ae4, 0x33b10,
2381                 0x33b24, 0x33b28,
2382                 0x33b38, 0x33b50,
2383                 0x33bf0, 0x33c10,
2384                 0x33c24, 0x33c28,
2385                 0x33c38, 0x33c50,
2386                 0x33cf0, 0x33cfc,
2387                 0x34000, 0x34030,
2388                 0x34100, 0x34168,
2389                 0x34190, 0x341a0,
2390                 0x341a8, 0x341b8,
2391                 0x341c4, 0x341c8,
2392                 0x341d0, 0x341d0,
2393                 0x34200, 0x34320,
2394                 0x34400, 0x344b4,
2395                 0x344c0, 0x3452c,
2396                 0x34540, 0x3461c,
2397                 0x34800, 0x348a0,
2398                 0x348c0, 0x34908,
2399                 0x34910, 0x349b8,
2400                 0x34a00, 0x34a04,
2401                 0x34a0c, 0x34a14,
2402                 0x34a1c, 0x34a2c,
2403                 0x34a44, 0x34a50,
2404                 0x34a74, 0x34a74,
2405                 0x34a7c, 0x34afc,
2406                 0x34b08, 0x34c24,
2407                 0x34d00, 0x34d14,
2408                 0x34d1c, 0x34d3c,
2409                 0x34d44, 0x34d4c,
2410                 0x34d54, 0x34d74,
2411                 0x34d7c, 0x34d7c,
2412                 0x34de0, 0x34de0,
2413                 0x34e00, 0x34ed4,
2414                 0x34f00, 0x34fa4,
2415                 0x34fc0, 0x34fc4,
2416                 0x35000, 0x35004,
2417                 0x35080, 0x350fc,
2418                 0x35208, 0x35220,
2419                 0x3523c, 0x35254,
2420                 0x35300, 0x35300,
2421                 0x35308, 0x3531c,
2422                 0x35338, 0x3533c,
2423                 0x35380, 0x35380,
2424                 0x35388, 0x353a8,
2425                 0x353b4, 0x353b4,
2426                 0x35400, 0x35420,
2427                 0x35438, 0x3543c,
2428                 0x35480, 0x35480,
2429                 0x354a8, 0x354a8,
2430                 0x354b0, 0x354b4,
2431                 0x354c8, 0x354d4,
2432                 0x35a40, 0x35a4c,
2433                 0x35af0, 0x35b20,
2434                 0x35b38, 0x35b3c,
2435                 0x35b80, 0x35b80,
2436                 0x35ba8, 0x35ba8,
2437                 0x35bb0, 0x35bb4,
2438                 0x35bc8, 0x35bd4,
2439                 0x36140, 0x3618c,
2440                 0x361f0, 0x361f4,
2441                 0x36200, 0x36200,
2442                 0x36218, 0x36218,
2443                 0x36400, 0x36400,
2444                 0x36408, 0x3641c,
2445                 0x36618, 0x36620,
2446                 0x36664, 0x36664,
2447                 0x366a8, 0x366a8,
2448                 0x366ec, 0x366ec,
2449                 0x36a00, 0x36abc,
2450                 0x36b00, 0x36b18,
2451                 0x36b20, 0x36b38,
2452                 0x36b40, 0x36b58,
2453                 0x36b60, 0x36b78,
2454                 0x36c00, 0x36c00,
2455                 0x36c08, 0x36c3c,
2456                 0x37000, 0x3702c,
2457                 0x37034, 0x37050,
2458                 0x37058, 0x37058,
2459                 0x37060, 0x3708c,
2460                 0x3709c, 0x370ac,
2461                 0x370c0, 0x370c0,
2462                 0x370c8, 0x370d0,
2463                 0x370d8, 0x370e0,
2464                 0x370ec, 0x3712c,
2465                 0x37134, 0x37150,
2466                 0x37158, 0x37158,
2467                 0x37160, 0x3718c,
2468                 0x3719c, 0x371ac,
2469                 0x371c0, 0x371c0,
2470                 0x371c8, 0x371d0,
2471                 0x371d8, 0x371e0,
2472                 0x371ec, 0x37290,
2473                 0x37298, 0x372c4,
2474                 0x372e4, 0x37390,
2475                 0x37398, 0x373c4,
2476                 0x373e4, 0x3742c,
2477                 0x37434, 0x37450,
2478                 0x37458, 0x37458,
2479                 0x37460, 0x3748c,
2480                 0x3749c, 0x374ac,
2481                 0x374c0, 0x374c0,
2482                 0x374c8, 0x374d0,
2483                 0x374d8, 0x374e0,
2484                 0x374ec, 0x3752c,
2485                 0x37534, 0x37550,
2486                 0x37558, 0x37558,
2487                 0x37560, 0x3758c,
2488                 0x3759c, 0x375ac,
2489                 0x375c0, 0x375c0,
2490                 0x375c8, 0x375d0,
2491                 0x375d8, 0x375e0,
2492                 0x375ec, 0x37690,
2493                 0x37698, 0x376c4,
2494                 0x376e4, 0x37790,
2495                 0x37798, 0x377c4,
2496                 0x377e4, 0x377fc,
2497                 0x37814, 0x37814,
2498                 0x37854, 0x37868,
2499                 0x37880, 0x3788c,
2500                 0x378c0, 0x378d0,
2501                 0x378e8, 0x378ec,
2502                 0x37900, 0x3792c,
2503                 0x37934, 0x37950,
2504                 0x37958, 0x37958,
2505                 0x37960, 0x3798c,
2506                 0x3799c, 0x379ac,
2507                 0x379c0, 0x379c0,
2508                 0x379c8, 0x379d0,
2509                 0x379d8, 0x379e0,
2510                 0x379ec, 0x37a90,
2511                 0x37a98, 0x37ac4,
2512                 0x37ae4, 0x37b10,
2513                 0x37b24, 0x37b28,
2514                 0x37b38, 0x37b50,
2515                 0x37bf0, 0x37c10,
2516                 0x37c24, 0x37c28,
2517                 0x37c38, 0x37c50,
2518                 0x37cf0, 0x37cfc,
2519                 0x40040, 0x40040,
2520                 0x40080, 0x40084,
2521                 0x40100, 0x40100,
2522                 0x40140, 0x401bc,
2523                 0x40200, 0x40214,
2524                 0x40228, 0x40228,
2525                 0x40240, 0x40258,
2526                 0x40280, 0x40280,
2527                 0x40304, 0x40304,
2528                 0x40330, 0x4033c,
2529                 0x41304, 0x413c8,
2530                 0x413d0, 0x413dc,
2531                 0x413f0, 0x413f0,
2532                 0x41400, 0x4140c,
2533                 0x41414, 0x4141c,
2534                 0x41480, 0x414d0,
2535                 0x44000, 0x4407c,
2536                 0x440c0, 0x441ac,
2537                 0x441b4, 0x4427c,
2538                 0x442c0, 0x443ac,
2539                 0x443b4, 0x4447c,
2540                 0x444c0, 0x445ac,
2541                 0x445b4, 0x4467c,
2542                 0x446c0, 0x447ac,
2543                 0x447b4, 0x4487c,
2544                 0x448c0, 0x449ac,
2545                 0x449b4, 0x44a7c,
2546                 0x44ac0, 0x44bac,
2547                 0x44bb4, 0x44c7c,
2548                 0x44cc0, 0x44dac,
2549                 0x44db4, 0x44e7c,
2550                 0x44ec0, 0x44fac,
2551                 0x44fb4, 0x4507c,
2552                 0x450c0, 0x451ac,
2553                 0x451b4, 0x451fc,
2554                 0x45800, 0x45804,
2555                 0x45810, 0x45830,
2556                 0x45840, 0x45860,
2557                 0x45868, 0x45868,
2558                 0x45880, 0x45884,
2559                 0x458a0, 0x458b0,
2560                 0x45a00, 0x45a04,
2561                 0x45a10, 0x45a30,
2562                 0x45a40, 0x45a60,
2563                 0x45a68, 0x45a68,
2564                 0x45a80, 0x45a84,
2565                 0x45aa0, 0x45ab0,
2566                 0x460c0, 0x460e4,
2567                 0x47000, 0x4703c,
2568                 0x47044, 0x4708c,
2569                 0x47200, 0x47250,
2570                 0x47400, 0x47408,
2571                 0x47414, 0x47420,
2572                 0x47600, 0x47618,
2573                 0x47800, 0x47814,
2574                 0x47820, 0x4782c,
2575                 0x50000, 0x50084,
2576                 0x50090, 0x500cc,
2577                 0x50300, 0x50384,
2578                 0x50400, 0x50400,
2579                 0x50800, 0x50884,
2580                 0x50890, 0x508cc,
2581                 0x50b00, 0x50b84,
2582                 0x50c00, 0x50c00,
2583                 0x51000, 0x51020,
2584                 0x51028, 0x510b0,
2585                 0x51300, 0x51324,
2586         };
2587
2588         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2589         const unsigned int *reg_ranges;
2590         int reg_ranges_size, range;
2591         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2592
2593         /* Select the right set of register ranges to dump depending on the
2594          * adapter chip type.
2595          */
2596         switch (chip_version) {
2597         case CHELSIO_T4:
2598                 reg_ranges = t4_reg_ranges;
2599                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2600                 break;
2601
2602         case CHELSIO_T5:
2603                 reg_ranges = t5_reg_ranges;
2604                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2605                 break;
2606
2607         case CHELSIO_T6:
2608                 reg_ranges = t6_reg_ranges;
2609                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2610                 break;
2611
2612         default:
2613                 dev_err(adap->pdev_dev,
2614                         "Unsupported chip version %d\n", chip_version);
2615                 return;
2616         }
2617
2618         /* Clear the register buffer and insert the appropriate register
2619          * values selected by the above register ranges.
2620          */
2621         memset(buf, 0, buf_size);
2622         for (range = 0; range < reg_ranges_size; range += 2) {
2623                 unsigned int reg = reg_ranges[range];
2624                 unsigned int last_reg = reg_ranges[range + 1];
2625                 u32 *bufp = (u32 *)((char *)buf + reg);
2626
2627                 /* Iterate across the register range filling in the register
2628                  * buffer but don't write past the end of the register buffer.
2629                  */
2630                 while (reg <= last_reg && bufp < buf_end) {
2631                         *bufp++ = t4_read_reg(adap, reg);
2632                         reg += sizeof(u32);
2633                 }
2634         }
2635 }
2636
2637 #define EEPROM_STAT_ADDR   0x7bfc
2638 #define VPD_SIZE           0x800
2639 #define VPD_BASE           0x400
2640 #define VPD_BASE_OLD       0
2641 #define VPD_LEN            1024
2642 #define CHELSIO_VPD_UNIQUE_ID 0x82
2643
2644 /**
2645  * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2646  * @phys_addr: the physical EEPROM address
2647  * @fn: the PCI function number
2648  * @sz: size of function-specific area
2649  *
2650  * Translate a physical EEPROM address to virtual.  The first 1K is
2651  * accessed through virtual addresses starting at 31K, the rest is
2652  * accessed through virtual addresses starting at 0.
2653  *
2654  * The mapping is as follows:
2655  * [0..1K) -> [31K..32K)
2656  * [1K..1K+A) -> [31K-A..31K)
2657  * [1K+A..ES) -> [0..ES-A-1K)
2658  *
2659  * where A = @fn * @sz, and ES = EEPROM size.
2660  */
2661 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2662 {
2663         fn *= sz;
2664         if (phys_addr < 1024)
2665                 return phys_addr + (31 << 10);
2666         if (phys_addr < 1024 + fn)
2667                 return 31744 - fn + phys_addr - 1024;
2668         if (phys_addr < EEPROMSIZE)
2669                 return phys_addr - 1024 - fn;
2670         return -EINVAL;
2671 }
2672
2673 /**
2674  *      t4_seeprom_wp - enable/disable EEPROM write protection
2675  *      @adapter: the adapter
2676  *      @enable: whether to enable or disable write protection
2677  *
2678  *      Enables or disables write protection on the serial EEPROM.
2679  */
2680 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2681 {
2682         unsigned int v = enable ? 0xc : 0;
2683         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2684         return ret < 0 ? ret : 0;
2685 }
2686
2687 /**
2688  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2689  *      @adapter: adapter to read
2690  *      @p: where to store the parameters
2691  *
2692  *      Reads card parameters stored in VPD EEPROM.
2693  */
2694 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2695 {
2696         int i, ret = 0, addr;
2697         int ec, sn, pn, na;
2698         u8 *vpd, csum;
2699         unsigned int vpdr_len, kw_offset, id_len;
2700
2701         vpd = vmalloc(VPD_LEN);
2702         if (!vpd)
2703                 return -ENOMEM;
2704
2705         /* We have two VPD data structures stored in the adapter VPD area.
2706          * By default, Linux calculates the size of the VPD area by traversing
2707          * the first VPD area at offset 0x0, so we need to tell the OS what
2708          * our real VPD size is.
2709          */
2710         ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2711         if (ret < 0)
2712                 goto out;
2713
2714         /* Card information normally starts at VPD_BASE but early cards had
2715          * it at 0.
2716          */
2717         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2718         if (ret < 0)
2719                 goto out;
2720
2721         /* The VPD shall have a unique identifier specified by the PCI SIG.
2722          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2723          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2724          * is expected to automatically put this entry at the
2725          * beginning of the VPD.
2726          */
2727         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2728
2729         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2730         if (ret < 0)
2731                 goto out;
2732
2733         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2734                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2735                 ret = -EINVAL;
2736                 goto out;
2737         }
2738
2739         id_len = pci_vpd_lrdt_size(vpd);
2740         if (id_len > ID_LEN)
2741                 id_len = ID_LEN;
2742
2743         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2744         if (i < 0) {
2745                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2746                 ret = -EINVAL;
2747                 goto out;
2748         }
2749
2750         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2751         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2752         if (vpdr_len + kw_offset > VPD_LEN) {
2753                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2754                 ret = -EINVAL;
2755                 goto out;
2756         }
2757
2758 #define FIND_VPD_KW(var, name) do { \
2759         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2760         if (var < 0) { \
2761                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2762                 ret = -EINVAL; \
2763                 goto out; \
2764         } \
2765         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2766 } while (0)
2767
2768         FIND_VPD_KW(i, "RV");
2769         for (csum = 0; i >= 0; i--)
2770                 csum += vpd[i];
2771
2772         if (csum) {
2773                 dev_err(adapter->pdev_dev,
2774                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2775                 ret = -EINVAL;
2776                 goto out;
2777         }
2778
2779         FIND_VPD_KW(ec, "EC");
2780         FIND_VPD_KW(sn, "SN");
2781         FIND_VPD_KW(pn, "PN");
2782         FIND_VPD_KW(na, "NA");
2783 #undef FIND_VPD_KW
2784
2785         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2786         strim(p->id);
2787         memcpy(p->ec, vpd + ec, EC_LEN);
2788         strim(p->ec);
2789         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2790         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2791         strim(p->sn);
2792         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2793         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2794         strim(p->pn);
2795         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2796         strim((char *)p->na);
2797
2798 out:
2799         vfree(vpd);
2800         return ret < 0 ? ret : 0;
2801 }
2802
2803 /**
2804  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2805  *      @adapter: adapter to read
2806  *      @p: where to store the parameters
2807  *
2808  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2809  *      Clock.  This can only be called after a connection to the firmware
2810  *      is established.
2811  */
2812 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2813 {
2814         u32 cclk_param, cclk_val;
2815         int ret;
2816
2817         /* Grab the raw VPD parameters.
2818          */
2819         ret = t4_get_raw_vpd_params(adapter, p);
2820         if (ret)
2821                 return ret;
2822
2823         /* Ask firmware for the Core Clock since it knows how to translate the
2824          * Reference Clock ('V2') VPD field into a Core Clock value ...
2825          */
2826         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2827                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2828         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2829                               1, &cclk_param, &cclk_val);
2830
2831         if (ret)
2832                 return ret;
2833         p->cclk = cclk_val;
2834
2835         return 0;
2836 }
2837
2838 /* serial flash and firmware constants */
2839 enum {
2840         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2841
2842         /* flash command opcodes */
2843         SF_PROG_PAGE    = 2,          /* program page */
2844         SF_WR_DISABLE   = 4,          /* disable writes */
2845         SF_RD_STATUS    = 5,          /* read status register */
2846         SF_WR_ENABLE    = 6,          /* enable writes */
2847         SF_RD_DATA_FAST = 0xb,        /* read flash */
2848         SF_RD_ID        = 0x9f,       /* read ID */
2849         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2850
2851         FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2852 };
2853
2854 /**
2855  *      sf1_read - read data from the serial flash
2856  *      @adapter: the adapter
2857  *      @byte_cnt: number of bytes to read
2858  *      @cont: whether another operation will be chained
2859  *      @lock: whether to lock SF for PL access only
2860  *      @valp: where to store the read data
2861  *
2862  *      Reads up to 4 bytes of data from the serial flash.  The location of
2863  *      the read needs to be specified prior to calling this by issuing the
2864  *      appropriate commands to the serial flash.
2865  */
2866 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2867                     int lock, u32 *valp)
2868 {
2869         int ret;
2870
2871         if (!byte_cnt || byte_cnt > 4)
2872                 return -EINVAL;
2873         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2874                 return -EBUSY;
2875         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2876                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2877         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2878         if (!ret)
2879                 *valp = t4_read_reg(adapter, SF_DATA_A);
2880         return ret;
2881 }
2882
2883 /**
2884  *      sf1_write - write data to the serial flash
2885  *      @adapter: the adapter
2886  *      @byte_cnt: number of bytes to write
2887  *      @cont: whether another operation will be chained
2888  *      @lock: whether to lock SF for PL access only
2889  *      @val: value to write
2890  *
2891  *      Writes up to 4 bytes of data to the serial flash.  The location of
2892  *      the write needs to be specified prior to calling this by issuing the
2893  *      appropriate commands to the serial flash.
2894  */
2895 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2896                      int lock, u32 val)
2897 {
2898         if (!byte_cnt || byte_cnt > 4)
2899                 return -EINVAL;
2900         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2901                 return -EBUSY;
2902         t4_write_reg(adapter, SF_DATA_A, val);
2903         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2904                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2905         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2906 }
2907
2908 /**
2909  *      flash_wait_op - wait for a flash operation to complete
2910  *      @adapter: the adapter
2911  *      @attempts: max number of polls of the status register
2912  *      @delay: delay between polls in ms
2913  *
2914  *      Wait for a flash operation to complete by polling the status register.
2915  */
2916 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2917 {
2918         int ret;
2919         u32 status;
2920
2921         while (1) {
2922                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2923                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2924                         return ret;
2925                 if (!(status & 1))
2926                         return 0;
2927                 if (--attempts == 0)
2928                         return -EAGAIN;
2929                 if (delay)
2930                         msleep(delay);
2931         }
2932 }
2933
2934 /**
2935  *      t4_read_flash - read words from serial flash
2936  *      @adapter: the adapter
2937  *      @addr: the start address for the read
2938  *      @nwords: how many 32-bit words to read
2939  *      @data: where to store the read data
2940  *      @byte_oriented: whether to store data as bytes or as words
2941  *
2942  *      Read the specified number of 32-bit words from the serial flash.
2943  *      If @byte_oriented is set the read data is stored as a byte array
2944  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2945  *      natural endianness.
2946  */
2947 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2948                   unsigned int nwords, u32 *data, int byte_oriented)
2949 {
2950         int ret;
2951
2952         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2953                 return -EINVAL;
2954
2955         addr = swab32(addr) | SF_RD_DATA_FAST;
2956
2957         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2958             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2959                 return ret;
2960
2961         for ( ; nwords; nwords--, data++) {
2962                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2963                 if (nwords == 1)
2964                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2965                 if (ret)
2966                         return ret;
2967                 if (byte_oriented)
2968                         *data = (__force __u32)(cpu_to_be32(*data));
2969         }
2970         return 0;
2971 }
2972
2973 /**
2974  *      t4_write_flash - write up to a page of data to the serial flash
2975  *      @adapter: the adapter
2976  *      @addr: the start address to write
2977  *      @n: length of data to write in bytes
2978  *      @data: the data to write
2979  *
2980  *      Writes up to a page of data (256 bytes) to the serial flash starting
2981  *      at the given address.  All the data must be written to the same page.
2982  */
2983 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2984                           unsigned int n, const u8 *data)
2985 {
2986         int ret;
2987         u32 buf[64];
2988         unsigned int i, c, left, val, offset = addr & 0xff;
2989
2990         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2991                 return -EINVAL;
2992
2993         val = swab32(addr) | SF_PROG_PAGE;
2994
2995         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2996             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2997                 goto unlock;
2998
2999         for (left = n; left; left -= c) {
3000                 c = min(left, 4U);
3001                 for (val = 0, i = 0; i < c; ++i)
3002                         val = (val << 8) + *data++;
3003
3004                 ret = sf1_write(adapter, c, c != left, 1, val);
3005                 if (ret)
3006                         goto unlock;
3007         }
3008         ret = flash_wait_op(adapter, 8, 1);
3009         if (ret)
3010                 goto unlock;
3011
3012         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3013
3014         /* Read the page to verify the write succeeded */
3015         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3016         if (ret)
3017                 return ret;
3018
3019         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3020                 dev_err(adapter->pdev_dev,
3021                         "failed to correctly write the flash page at %#x\n",
3022                         addr);
3023                 return -EIO;
3024         }
3025         return 0;
3026
3027 unlock:
3028         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3029         return ret;
3030 }
3031
3032 /**
3033  *      t4_get_fw_version - read the firmware version
3034  *      @adapter: the adapter
3035  *      @vers: where to place the version
3036  *
3037  *      Reads the FW version from flash.
3038  */
3039 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3040 {
3041         return t4_read_flash(adapter, FLASH_FW_START +
3042                              offsetof(struct fw_hdr, fw_ver), 1,
3043                              vers, 0);
3044 }
3045
3046 /**
3047  *      t4_get_bs_version - read the firmware bootstrap version
3048  *      @adapter: the adapter
3049  *      @vers: where to place the version
3050  *
3051  *      Reads the FW Bootstrap version from flash.
3052  */
3053 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3054 {
3055         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3056                              offsetof(struct fw_hdr, fw_ver), 1,
3057                              vers, 0);
3058 }
3059
3060 /**
3061  *      t4_get_tp_version - read the TP microcode version
3062  *      @adapter: the adapter
3063  *      @vers: where to place the version
3064  *
3065  *      Reads the TP microcode version from flash.
3066  */
3067 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3068 {
3069         return t4_read_flash(adapter, FLASH_FW_START +
3070                              offsetof(struct fw_hdr, tp_microcode_ver),
3071                              1, vers, 0);
3072 }
3073
3074 /**
3075  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3076  *      @adapter: the adapter
3077  *      @vers: where to place the version
3078  *
3079  *      Reads the Expansion ROM header from FLASH and returns the version
3080  *      number (if present) through the @vers return value pointer.  We return
3081  *      this in the Firmware Version Format since it's convenient.  Return
3082  *      0 on success, -ENOENT if no Expansion ROM is present.
3083  */
3084 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3085 {
3086         struct exprom_header {
3087                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3088                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3089         } *hdr;
3090         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3091                                            sizeof(u32))];
3092         int ret;
3093
3094         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3095                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3096                             0);
3097         if (ret)
3098                 return ret;
3099
3100         hdr = (struct exprom_header *)exprom_header_buf;
3101         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3102                 return -ENOENT;
3103
3104         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3105                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3106                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3107                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3108         return 0;
3109 }
3110
3111 /**
3112  *      t4_get_vpd_version - return the VPD version
3113  *      @adapter: the adapter
3114  *      @vers: where to place the version
3115  *
3116  *      Reads the VPD via the Firmware interface (thus this can only be called
3117  *      once we're ready to issue Firmware commands).  The format of the
3118  *      VPD version is adapter specific.  Returns 0 on success, an error on
3119  *      failure.
3120  *
3121  *      Note that early versions of the Firmware didn't include the ability
3122  *      to retrieve the VPD version, so we zero-out the return-value parameter
3123  *      in that case to avoid leaving it with garbage in it.
3124  *
3125  *      Also note that the Firmware will return its cached copy of the VPD
3126  *      Revision ID, not the actual Revision ID as written in the Serial
3127  *      EEPROM.  This is only an issue if a new VPD has been written and the
3128  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3129  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3130  *      if the Host Driver will be performing a full adapter initialization.
3131  */
3132 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3133 {
3134         u32 vpdrev_param;
3135         int ret;
3136
3137         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3138                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3139         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3140                               1, &vpdrev_param, vers);
3141         if (ret)
3142                 *vers = 0;
3143         return ret;
3144 }
3145
3146 /**
3147  *      t4_get_scfg_version - return the Serial Configuration version
3148  *      @adapter: the adapter
3149  *      @vers: where to place the version
3150  *
3151  *      Reads the Serial Configuration Version via the Firmware interface
3152  *      (thus this can only be called once we're ready to issue Firmware
3153  *      commands).  The format of the Serial Configuration version is
3154  *      adapter specific.  Returns 0 on success, an error on failure.
3155  *
3156  *      Note that early versions of the Firmware didn't include the ability
3157  *      to retrieve the Serial Configuration version, so we zero-out the
3158  *      return-value parameter in that case to avoid leaving it with
3159  *      garbage in it.
3160  *
3161  *      Also note that the Firmware will return its cached copy of the Serial
3162  *      Initialization Revision ID, not the actual Revision ID as written in
3163  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3164  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3165  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3166  *      been issued if the Host Driver will be performing a full adapter
3167  *      initialization.
3168  */
3169 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3170 {
3171         u32 scfgrev_param;
3172         int ret;
3173
3174         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3175                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3176         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3177                               1, &scfgrev_param, vers);
3178         if (ret)
3179                 *vers = 0;
3180         return ret;
3181 }
3182
3183 /**
3184  *      t4_get_version_info - extract various chip/firmware version information
3185  *      @adapter: the adapter
3186  *
3187  *      Reads various chip/firmware version numbers and stores them into the
3188  *      adapter Adapter Parameters structure.  If any of the efforts fails
3189  *      the first failure will be returned, but all of the version numbers
3190  *      will be read.
3191  */
3192 int t4_get_version_info(struct adapter *adapter)
3193 {
3194         int ret = 0;
3195
3196         #define FIRST_RET(__getvinfo) \
3197         do { \
3198                 int __ret = __getvinfo; \
3199                 if (__ret && !ret) \
3200                         ret = __ret; \
3201         } while (0)
3202
3203         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3204         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3205         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3206         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3207         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3208         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3209
3210         #undef FIRST_RET
3211         return ret;
3212 }
3213
3214 /**
3215  *      t4_dump_version_info - dump all of the adapter configuration IDs
3216  *      @adapter: the adapter
3217  *
3218  *      Dumps all of the various bits of adapter configuration version/revision
3219  *      IDs information.  This is typically called at some point after
3220  *      t4_get_version_info() has been called.
3221  */
3222 void t4_dump_version_info(struct adapter *adapter)
3223 {
3224         /* Device information */
3225         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3226                  adapter->params.vpd.id,
3227                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3228         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3229                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3230
3231         /* Firmware Version */
3232         if (!adapter->params.fw_vers)
3233                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3234         else
3235                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3236                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3237                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3238                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3239                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3240
3241         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3242          * Firmware, so dev_info() is more appropriate here.)
3243          */
3244         if (!adapter->params.bs_vers)
3245                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3246         else
3247                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3248                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3249                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3250                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3251                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3252
3253         /* TP Microcode Version */
3254         if (!adapter->params.tp_vers)
3255                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3256         else
3257                 dev_info(adapter->pdev_dev,
3258                          "TP Microcode version: %u.%u.%u.%u\n",
3259                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3260                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3261                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3262                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3263
3264         /* Expansion ROM version */
3265         if (!adapter->params.er_vers)
3266                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3267         else
3268                 dev_info(adapter->pdev_dev,
3269                          "Expansion ROM version: %u.%u.%u.%u\n",
3270                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3271                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3272                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3273                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3274
3275         /* Serial Configuration version */
3276         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3277                  adapter->params.scfg_vers);
3278
3279         /* VPD Version */
3280         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3281                  adapter->params.vpd_vers);
3282 }
3283
3284 /**
3285  *      t4_check_fw_version - check if the FW is supported with this driver
3286  *      @adap: the adapter
3287  *
3288  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3289  *      if there's exact match, a negative error if the version could not be
3290  *      read or there's a major version mismatch
3291  */
3292 int t4_check_fw_version(struct adapter *adap)
3293 {
3294         int i, ret, major, minor, micro;
3295         int exp_major, exp_minor, exp_micro;
3296         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3297
3298         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3299         /* Try multiple times before returning error */
3300         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3301                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3302
3303         if (ret)
3304                 return ret;
3305
3306         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3307         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3308         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3309
3310         switch (chip_version) {
3311         case CHELSIO_T4:
3312                 exp_major = T4FW_MIN_VERSION_MAJOR;
3313                 exp_minor = T4FW_MIN_VERSION_MINOR;
3314                 exp_micro = T4FW_MIN_VERSION_MICRO;
3315                 break;
3316         case CHELSIO_T5:
3317                 exp_major = T5FW_MIN_VERSION_MAJOR;
3318                 exp_minor = T5FW_MIN_VERSION_MINOR;
3319                 exp_micro = T5FW_MIN_VERSION_MICRO;
3320                 break;
3321         case CHELSIO_T6:
3322                 exp_major = T6FW_MIN_VERSION_MAJOR;
3323                 exp_minor = T6FW_MIN_VERSION_MINOR;
3324                 exp_micro = T6FW_MIN_VERSION_MICRO;
3325                 break;
3326         default:
3327                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3328                         adap->chip);
3329                 return -EINVAL;
3330         }
3331
3332         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3333             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3334                 dev_err(adap->pdev_dev,
3335                         "Card has firmware version %u.%u.%u, minimum "
3336                         "supported firmware is %u.%u.%u.\n", major, minor,
3337                         micro, exp_major, exp_minor, exp_micro);
3338                 return -EFAULT;
3339         }
3340         return 0;
3341 }
3342
3343 /* Is the given firmware API compatible with the one the driver was compiled
3344  * with?
3345  */
3346 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3347 {
3348
3349         /* short circuit if it's the exact same firmware version */
3350         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3351                 return 1;
3352
3353 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3354         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3355             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3356                 return 1;
3357 #undef SAME_INTF
3358
3359         return 0;
3360 }
3361
3362 /* The firmware in the filesystem is usable, but should it be installed?
3363  * This routine explains itself in detail if it indicates the filesystem
3364  * firmware should be installed.
3365  */
3366 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3367                                 int k, int c)
3368 {
3369         const char *reason;
3370
3371         if (!card_fw_usable) {
3372                 reason = "incompatible or unusable";
3373                 goto install;
3374         }
3375
3376         if (k > c) {
3377                 reason = "older than the version supported with this driver";
3378                 goto install;
3379         }
3380
3381         return 0;
3382
3383 install:
3384         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3385                 "installing firmware %u.%u.%u.%u on card.\n",
3386                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3387                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3388                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3389                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3390
3391         return 1;
3392 }
3393
3394 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3395                const u8 *fw_data, unsigned int fw_size,
3396                struct fw_hdr *card_fw, enum dev_state state,
3397                int *reset)
3398 {
3399         int ret, card_fw_usable, fs_fw_usable;
3400         const struct fw_hdr *fs_fw;
3401         const struct fw_hdr *drv_fw;
3402
3403         drv_fw = &fw_info->fw_hdr;
3404
3405         /* Read the header of the firmware on the card */
3406         ret = -t4_read_flash(adap, FLASH_FW_START,
3407                             sizeof(*card_fw) / sizeof(uint32_t),
3408                             (uint32_t *)card_fw, 1);
3409         if (ret == 0) {
3410                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3411         } else {
3412                 dev_err(adap->pdev_dev,
3413                         "Unable to read card's firmware header: %d\n", ret);
3414                 card_fw_usable = 0;
3415         }
3416
3417         if (fw_data != NULL) {
3418                 fs_fw = (const void *)fw_data;
3419                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3420         } else {
3421                 fs_fw = NULL;
3422                 fs_fw_usable = 0;
3423         }
3424
3425         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3426             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3427                 /* Common case: the firmware on the card is an exact match and
3428                  * the filesystem one is an exact match too, or the filesystem
3429                  * one is absent/incompatible.
3430                  */
3431         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3432                    should_install_fs_fw(adap, card_fw_usable,
3433                                         be32_to_cpu(fs_fw->fw_ver),
3434                                         be32_to_cpu(card_fw->fw_ver))) {
3435                 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3436                                      fw_size, 0);
3437                 if (ret != 0) {
3438                         dev_err(adap->pdev_dev,
3439                                 "failed to install firmware: %d\n", ret);
3440                         goto bye;
3441                 }
3442
3443                 /* Installed successfully, update the cached header too. */
3444                 *card_fw = *fs_fw;
3445                 card_fw_usable = 1;
3446                 *reset = 0;     /* already reset as part of load_fw */
3447         }
3448
3449         if (!card_fw_usable) {
3450                 uint32_t d, c, k;
3451
3452                 d = be32_to_cpu(drv_fw->fw_ver);
3453                 c = be32_to_cpu(card_fw->fw_ver);
3454                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3455
3456                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3457                         "chip state %d, "
3458                         "driver compiled with %d.%d.%d.%d, "
3459                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3460                         state,
3461                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3462                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3463                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3464                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3465                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3466                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3467                 ret = EINVAL;
3468                 goto bye;
3469         }
3470
3471         /* We're using whatever's on the card and it's known to be good. */
3472         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3473         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3474
3475 bye:
3476         return ret;
3477 }
3478
3479 /**
3480  *      t4_flash_erase_sectors - erase a range of flash sectors
3481  *      @adapter: the adapter
3482  *      @start: the first sector to erase
3483  *      @end: the last sector to erase
3484  *
3485  *      Erases the sectors in the given inclusive range.
3486  */
3487 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3488 {
3489         int ret = 0;
3490
3491         if (end >= adapter->params.sf_nsec)
3492                 return -EINVAL;
3493
3494         while (start <= end) {
3495                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3496                     (ret = sf1_write(adapter, 4, 0, 1,
3497                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3498                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3499                         dev_err(adapter->pdev_dev,
3500                                 "erase of flash sector %d failed, error %d\n",
3501                                 start, ret);
3502                         break;
3503                 }
3504                 start++;
3505         }
3506         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3507         return ret;
3508 }
3509
3510 /**
3511  *      t4_flash_cfg_addr - return the address of the flash configuration file
3512  *      @adapter: the adapter
3513  *
3514  *      Return the address within the flash where the Firmware Configuration
3515  *      File is stored.
3516  */
3517 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3518 {
3519         if (adapter->params.sf_size == 0x100000)
3520                 return FLASH_FPGA_CFG_START;
3521         else
3522                 return FLASH_CFG_START;
3523 }
3524
3525 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3526  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3527  * and emit an error message for mismatched firmware to save our caller the
3528  * effort ...
3529  */
3530 static bool t4_fw_matches_chip(const struct adapter *adap,
3531                                const struct fw_hdr *hdr)
3532 {
3533         /* The expression below will return FALSE for any unsupported adapter
3534          * which will keep us "honest" in the future ...
3535          */
3536         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3537             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3538             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3539                 return true;
3540
3541         dev_err(adap->pdev_dev,
3542                 "FW image (%d) is not suitable for this adapter (%d)\n",
3543                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3544         return false;
3545 }
3546
3547 /**
3548  *      t4_load_fw - download firmware
3549  *      @adap: the adapter
3550  *      @fw_data: the firmware image to write
3551  *      @size: image size
3552  *
3553  *      Write the supplied firmware image to the card's serial flash.
3554  */
3555 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3556 {
3557         u32 csum;
3558         int ret, addr;
3559         unsigned int i;
3560         u8 first_page[SF_PAGE_SIZE];
3561         const __be32 *p = (const __be32 *)fw_data;
3562         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3563         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3564         unsigned int fw_img_start = adap->params.sf_fw_start;
3565         unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3566
3567         if (!size) {
3568                 dev_err(adap->pdev_dev, "FW image has no data\n");
3569                 return -EINVAL;
3570         }
3571         if (size & 511) {
3572                 dev_err(adap->pdev_dev,
3573                         "FW image size not multiple of 512 bytes\n");
3574                 return -EINVAL;
3575         }
3576         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3577                 dev_err(adap->pdev_dev,
3578                         "FW image size differs from size in FW header\n");
3579                 return -EINVAL;
3580         }
3581         if (size > FW_MAX_SIZE) {
3582                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3583                         FW_MAX_SIZE);
3584                 return -EFBIG;
3585         }
3586         if (!t4_fw_matches_chip(adap, hdr))
3587                 return -EINVAL;
3588
3589         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3590                 csum += be32_to_cpu(p[i]);
3591
3592         if (csum != 0xffffffff) {
3593                 dev_err(adap->pdev_dev,
3594                         "corrupted firmware image, checksum %#x\n", csum);
3595                 return -EINVAL;
3596         }
3597
3598         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3599         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3600         if (ret)
3601                 goto out;
3602
3603         /*
3604          * We write the correct version at the end so the driver can see a bad
3605          * version if the FW write fails.  Start by writing a copy of the
3606          * first page with a bad version.
3607          */
3608         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3609         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3610         ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3611         if (ret)
3612                 goto out;
3613
3614         addr = fw_img_start;
3615         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3616                 addr += SF_PAGE_SIZE;
3617                 fw_data += SF_PAGE_SIZE;
3618                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3619                 if (ret)
3620                         goto out;
3621         }
3622
3623         ret = t4_write_flash(adap,
3624                              fw_img_start + offsetof(struct fw_hdr, fw_ver),
3625                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3626 out:
3627         if (ret)
3628                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3629                         ret);
3630         else
3631                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3632         return ret;
3633 }
3634
3635 /**
3636  *      t4_phy_fw_ver - return current PHY firmware version
3637  *      @adap: the adapter
3638  *      @phy_fw_ver: return value buffer for PHY firmware version
3639  *
3640  *      Returns the current version of external PHY firmware on the
3641  *      adapter.
3642  */
3643 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3644 {
3645         u32 param, val;
3646         int ret;
3647
3648         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3649                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3650                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3651                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3652         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3653                               &param, &val);
3654         if (ret < 0)
3655                 return ret;
3656         *phy_fw_ver = val;
3657         return 0;
3658 }
3659
3660 /**
3661  *      t4_load_phy_fw - download port PHY firmware
3662  *      @adap: the adapter
3663  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3664  *      @win_lock: the lock to use to guard the memory copy
3665  *      @phy_fw_version: function to check PHY firmware versions
3666  *      @phy_fw_data: the PHY firmware image to write
3667  *      @phy_fw_size: image size
3668  *
3669  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3670  *      @phy_fw_version is supplied, then it will be used to determine if
3671  *      it's necessary to perform the transfer by comparing the version
3672  *      of any existing adapter PHY firmware with that of the passed in
3673  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3674  *      around the call to t4_memory_rw() which transfers the PHY firmware
3675  *      to the adapter.
3676  *
3677  *      A negative error number will be returned if an error occurs.  If
3678  *      version number support is available and there's no need to upgrade
3679  *      the firmware, 0 will be returned.  If firmware is successfully
3680  *      transferred to the adapter, 1 will be retured.
3681  *
3682  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3683  *      a result, a RESET of the adapter would cause that RAM to lose its
3684  *      contents.  Thus, loading PHY firmware on such adapters must happen
3685  *      after any FW_RESET_CMDs ...
3686  */
3687 int t4_load_phy_fw(struct adapter *adap,
3688                    int win, spinlock_t *win_lock,
3689                    int (*phy_fw_version)(const u8 *, size_t),
3690                    const u8 *phy_fw_data, size_t phy_fw_size)
3691 {
3692         unsigned long mtype = 0, maddr = 0;
3693         u32 param, val;
3694         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3695         int ret;
3696
3697         /* If we have version number support, then check to see if the adapter
3698          * already has up-to-date PHY firmware loaded.
3699          */
3700          if (phy_fw_version) {
3701                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3702                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3703                 if (ret < 0)
3704                         return ret;
3705
3706                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3707                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3708                                 "version %#x\n", cur_phy_fw_ver);
3709                         return 0;
3710                 }
3711         }
3712
3713         /* Ask the firmware where it wants us to copy the PHY firmware image.
3714          * The size of the file requires a special version of the READ coommand
3715          * which will pass the file size via the values field in PARAMS_CMD and
3716          * retrieve the return value from firmware and place it in the same
3717          * buffer values
3718          */
3719         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3720                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3721                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3722                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3723         val = phy_fw_size;
3724         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3725                                  &param, &val, 1, true);
3726         if (ret < 0)
3727                 return ret;
3728         mtype = val >> 8;
3729         maddr = (val & 0xff) << 16;
3730
3731         /* Copy the supplied PHY Firmware image to the adapter memory location
3732          * allocated by the adapter firmware.
3733          */
3734         if (win_lock)
3735                 spin_lock_bh(win_lock);
3736         ret = t4_memory_rw(adap, win, mtype, maddr,
3737                            phy_fw_size, (__be32 *)phy_fw_data,
3738                            T4_MEMORY_WRITE);
3739         if (win_lock)
3740                 spin_unlock_bh(win_lock);
3741         if (ret)
3742                 return ret;
3743
3744         /* Tell the firmware that the PHY firmware image has been written to
3745          * RAM and it can now start copying it over to the PHYs.  The chip
3746          * firmware will RESET the affected PHYs as part of this operation
3747          * leaving them running the new PHY firmware image.
3748          */
3749         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3750                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3751                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3752                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3753         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3754                                     &param, &val, 30000);
3755
3756         /* If we have version number support, then check to see that the new
3757          * firmware got loaded properly.
3758          */
3759         if (phy_fw_version) {
3760                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3761                 if (ret < 0)
3762                         return ret;
3763
3764                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3765                         CH_WARN(adap, "PHY Firmware did not update: "
3766                                 "version on adapter %#x, "
3767                                 "version flashed %#x\n",
3768                                 cur_phy_fw_ver, new_phy_fw_vers);
3769                         return -ENXIO;
3770                 }
3771         }
3772
3773         return 1;
3774 }
3775
3776 /**
3777  *      t4_fwcache - firmware cache operation
3778  *      @adap: the adapter
3779  *      @op  : the operation (flush or flush and invalidate)
3780  */
3781 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3782 {
3783         struct fw_params_cmd c;
3784
3785         memset(&c, 0, sizeof(c));
3786         c.op_to_vfn =
3787                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3788                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3789                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3790                             FW_PARAMS_CMD_VFN_V(0));
3791         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3792         c.param[0].mnem =
3793                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3794                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3795         c.param[0].val = (__force __be32)op;
3796
3797         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3798 }
3799
3800 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3801                         unsigned int *pif_req_wrptr,
3802                         unsigned int *pif_rsp_wrptr)
3803 {
3804         int i, j;
3805         u32 cfg, val, req, rsp;
3806
3807         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3808         if (cfg & LADBGEN_F)
3809                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3810
3811         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3812         req = POLADBGWRPTR_G(val);
3813         rsp = PILADBGWRPTR_G(val);
3814         if (pif_req_wrptr)
3815                 *pif_req_wrptr = req;
3816         if (pif_rsp_wrptr)
3817                 *pif_rsp_wrptr = rsp;
3818
3819         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3820                 for (j = 0; j < 6; j++) {
3821                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3822                                      PILADBGRDPTR_V(rsp));
3823                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3824                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3825                         req++;
3826                         rsp++;
3827                 }
3828                 req = (req + 2) & POLADBGRDPTR_M;
3829                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3830         }
3831         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3832 }
3833
3834 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3835 {
3836         u32 cfg;
3837         int i, j, idx;
3838
3839         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3840         if (cfg & LADBGEN_F)
3841                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3842
3843         for (i = 0; i < CIM_MALA_SIZE; i++) {
3844                 for (j = 0; j < 5; j++) {
3845                         idx = 8 * i + j;
3846                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3847                                      PILADBGRDPTR_V(idx));
3848                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3849                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3850                 }
3851         }
3852         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3853 }
3854
3855 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3856 {
3857         unsigned int i, j;
3858
3859         for (i = 0; i < 8; i++) {
3860                 u32 *p = la_buf + i;
3861
3862                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3863                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3864                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3865                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3866                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3867         }
3868 }
3869
3870 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3871                      FW_PORT_CAP32_ANEG)
3872
3873 /**
3874  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3875  *      @caps16: a 16-bit Port Capabilities value
3876  *
3877  *      Returns the equivalent 32-bit Port Capabilities value.
3878  */
3879 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3880 {
3881         fw_port_cap32_t caps32 = 0;
3882
3883         #define CAP16_TO_CAP32(__cap) \
3884                 do { \
3885                         if (caps16 & FW_PORT_CAP_##__cap) \
3886                                 caps32 |= FW_PORT_CAP32_##__cap; \
3887                 } while (0)
3888
3889         CAP16_TO_CAP32(SPEED_100M);
3890         CAP16_TO_CAP32(SPEED_1G);
3891         CAP16_TO_CAP32(SPEED_25G);
3892         CAP16_TO_CAP32(SPEED_10G);
3893         CAP16_TO_CAP32(SPEED_40G);
3894         CAP16_TO_CAP32(SPEED_100G);
3895         CAP16_TO_CAP32(FC_RX);
3896         CAP16_TO_CAP32(FC_TX);
3897         CAP16_TO_CAP32(ANEG);
3898         CAP16_TO_CAP32(MDIX);
3899         CAP16_TO_CAP32(MDIAUTO);
3900         CAP16_TO_CAP32(FEC_RS);
3901         CAP16_TO_CAP32(FEC_BASER_RS);
3902         CAP16_TO_CAP32(802_3_PAUSE);
3903         CAP16_TO_CAP32(802_3_ASM_DIR);
3904
3905         #undef CAP16_TO_CAP32
3906
3907         return caps32;
3908 }
3909
3910 /**
3911  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3912  *      @caps32: a 32-bit Port Capabilities value
3913  *
3914  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
3915  *      not all 32-bit Port Capabilities can be represented in the 16-bit
3916  *      Port Capabilities and some fields/values may not make it.
3917  */
3918 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3919 {
3920         fw_port_cap16_t caps16 = 0;
3921
3922         #define CAP32_TO_CAP16(__cap) \
3923                 do { \
3924                         if (caps32 & FW_PORT_CAP32_##__cap) \
3925                                 caps16 |= FW_PORT_CAP_##__cap; \
3926                 } while (0)
3927
3928         CAP32_TO_CAP16(SPEED_100M);
3929         CAP32_TO_CAP16(SPEED_1G);
3930         CAP32_TO_CAP16(SPEED_10G);
3931         CAP32_TO_CAP16(SPEED_25G);
3932         CAP32_TO_CAP16(SPEED_40G);
3933         CAP32_TO_CAP16(SPEED_100G);
3934         CAP32_TO_CAP16(FC_RX);
3935         CAP32_TO_CAP16(FC_TX);
3936         CAP32_TO_CAP16(802_3_PAUSE);
3937         CAP32_TO_CAP16(802_3_ASM_DIR);
3938         CAP32_TO_CAP16(ANEG);
3939         CAP32_TO_CAP16(MDIX);
3940         CAP32_TO_CAP16(MDIAUTO);
3941         CAP32_TO_CAP16(FEC_RS);
3942         CAP32_TO_CAP16(FEC_BASER_RS);
3943
3944         #undef CAP32_TO_CAP16
3945
3946         return caps16;
3947 }
3948
3949 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3950 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
3951 {
3952         enum cc_pause cc_pause = 0;
3953
3954         if (fw_pause & FW_PORT_CAP32_FC_RX)
3955                 cc_pause |= PAUSE_RX;
3956         if (fw_pause & FW_PORT_CAP32_FC_TX)
3957                 cc_pause |= PAUSE_TX;
3958
3959         return cc_pause;
3960 }
3961
3962 /* Translate Common Code Pause specification into Firmware Port Capabilities */
3963 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
3964 {
3965         fw_port_cap32_t fw_pause = 0;
3966
3967         if (cc_pause & PAUSE_RX)
3968                 fw_pause |= FW_PORT_CAP32_FC_RX;
3969         if (cc_pause & PAUSE_TX)
3970                 fw_pause |= FW_PORT_CAP32_FC_TX;
3971
3972         return fw_pause;
3973 }
3974
3975 /* Translate Firmware Forward Error Correction specification to Common Code */
3976 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
3977 {
3978         enum cc_fec cc_fec = 0;
3979
3980         if (fw_fec & FW_PORT_CAP32_FEC_RS)
3981                 cc_fec |= FEC_RS;
3982         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
3983                 cc_fec |= FEC_BASER_RS;
3984
3985         return cc_fec;
3986 }
3987
3988 /* Translate Common Code Forward Error Correction specification to Firmware */
3989 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
3990 {
3991         fw_port_cap32_t fw_fec = 0;
3992
3993         if (cc_fec & FEC_RS)
3994                 fw_fec |= FW_PORT_CAP32_FEC_RS;
3995         if (cc_fec & FEC_BASER_RS)
3996                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
3997
3998         return fw_fec;
3999 }
4000
4001 /**
4002  *      t4_link_l1cfg - apply link configuration to MAC/PHY
4003  *      @adapter: the adapter
4004  *      @mbox: the Firmware Mailbox to use
4005  *      @port: the Port ID
4006  *      @lc: the Port's Link Configuration
4007  *
4008  *      Set up a port's MAC and PHY according to a desired link configuration.
4009  *      - If the PHY can auto-negotiate first decide what to advertise, then
4010  *        enable/disable auto-negotiation as desired, and reset.
4011  *      - If the PHY does not auto-negotiate just reset it.
4012  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4013  *        otherwise do it later based on the outcome of auto-negotiation.
4014  */
4015 int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
4016                   unsigned int port, struct link_config *lc)
4017 {
4018         unsigned int fw_caps = adapter->params.fw_caps_support;
4019         struct fw_port_cmd cmd;
4020         unsigned int fw_mdi = FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO);
4021         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
4022
4023         lc->link_ok = 0;
4024
4025         /* Convert driver coding of Pause Frame Flow Control settings into the
4026          * Firmware's API.
4027          */
4028         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4029
4030         /* Convert Common Code Forward Error Control settings into the
4031          * Firmware's API.  If the current Requested FEC has "Automatic"
4032          * (IEEE 802.3) specified, then we use whatever the Firmware
4033          * sent us as part of it's IEEE 802.3-based interpratation of
4034          * the Transceiver Module EPROM FEC parameters.  Otherwise we
4035          * use whatever is in the current Requested FEC settings.
4036          */
4037         if (lc->requested_fec & FEC_AUTO)
4038                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4039         else
4040                 cc_fec = lc->requested_fec;
4041         fw_fec = cc_to_fwcap_fec(cc_fec);
4042
4043         /* Figure out what our Requested Port Capabilities are going to be.
4044          */
4045         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4046                 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
4047                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4048                 lc->fec = cc_fec;
4049         } else if (lc->autoneg == AUTONEG_DISABLE) {
4050                 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4051                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4052                 lc->fec = cc_fec;
4053         } else {
4054                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4055         }
4056
4057         /* And send that on to the Firmware ...
4058          */
4059         memset(&cmd, 0, sizeof(cmd));
4060         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4061                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4062                                        FW_PORT_CMD_PORTID_V(port));
4063         cmd.action_to_len16 =
4064                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4065                                                  ? FW_PORT_ACTION_L1_CFG
4066                                                  : FW_PORT_ACTION_L1_CFG32) |
4067                             FW_LEN16(cmd));
4068         if (fw_caps == FW_CAPS16)
4069                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4070         else
4071                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4072         return t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4073 }
4074
4075 /**
4076  *      t4_restart_aneg - restart autonegotiation
4077  *      @adap: the adapter
4078  *      @mbox: mbox to use for the FW command
4079  *      @port: the port id
4080  *
4081  *      Restarts autonegotiation for the selected port.
4082  */
4083 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4084 {
4085         struct fw_port_cmd c;
4086
4087         memset(&c, 0, sizeof(c));
4088         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4089                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4090                                      FW_PORT_CMD_PORTID_V(port));
4091         c.action_to_len16 =
4092                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4093                             FW_LEN16(c));
4094         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4095         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4096 }
4097
4098 typedef void (*int_handler_t)(struct adapter *adap);
4099
4100 struct intr_info {
4101         unsigned int mask;       /* bits to check in interrupt status */
4102         const char *msg;         /* message to print or NULL */
4103         short stat_idx;          /* stat counter to increment or -1 */
4104         unsigned short fatal;    /* whether the condition reported is fatal */
4105         int_handler_t int_handler; /* platform-specific int handler */
4106 };
4107
4108 /**
4109  *      t4_handle_intr_status - table driven interrupt handler
4110  *      @adapter: the adapter that generated the interrupt
4111  *      @reg: the interrupt status register to process
4112  *      @acts: table of interrupt actions
4113  *
4114  *      A table driven interrupt handler that applies a set of masks to an
4115  *      interrupt status word and performs the corresponding actions if the
4116  *      interrupts described by the mask have occurred.  The actions include
4117  *      optionally emitting a warning or alert message.  The table is terminated
4118  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4119  *      conditions.
4120  */
4121 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4122                                  const struct intr_info *acts)
4123 {
4124         int fatal = 0;
4125         unsigned int mask = 0;
4126         unsigned int status = t4_read_reg(adapter, reg);
4127
4128         for ( ; acts->mask; ++acts) {
4129                 if (!(status & acts->mask))
4130                         continue;
4131                 if (acts->fatal) {
4132                         fatal++;
4133                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4134                                   status & acts->mask);
4135                 } else if (acts->msg && printk_ratelimit())
4136                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4137                                  status & acts->mask);
4138                 if (acts->int_handler)
4139                         acts->int_handler(adapter);
4140                 mask |= acts->mask;
4141         }
4142         status &= mask;
4143         if (status)                           /* clear processed interrupts */
4144                 t4_write_reg(adapter, reg, status);
4145         return fatal;
4146 }
4147
4148 /*
4149  * Interrupt handler for the PCIE module.
4150  */
4151 static void pcie_intr_handler(struct adapter *adapter)
4152 {
4153         static const struct intr_info sysbus_intr_info[] = {
4154                 { RNPP_F, "RXNP array parity error", -1, 1 },
4155                 { RPCP_F, "RXPC array parity error", -1, 1 },
4156                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4157                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4158                 { RFTP_F, "RXFT array parity error", -1, 1 },
4159                 { 0 }
4160         };
4161         static const struct intr_info pcie_port_intr_info[] = {
4162                 { TPCP_F, "TXPC array parity error", -1, 1 },
4163                 { TNPP_F, "TXNP array parity error", -1, 1 },
4164                 { TFTP_F, "TXFT array parity error", -1, 1 },
4165                 { TCAP_F, "TXCA array parity error", -1, 1 },
4166                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4167                 { RCAP_F, "RXCA array parity error", -1, 1 },
4168                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4169                 { RDPE_F, "Rx data parity error", -1, 1 },
4170                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4171                 { 0 }
4172         };
4173         static const struct intr_info pcie_intr_info[] = {
4174                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4175                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4176                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4177                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4178                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4179                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4180                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4181                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4182                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4183                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4184                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4185                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4186                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4187                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4188                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4189                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4190                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4191                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4192                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4193                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4194                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4195                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4196                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4197                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4198                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4199                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4200                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4201                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4202                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4203                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4204                   -1, 0 },
4205                 { 0 }
4206         };
4207
4208         static struct intr_info t5_pcie_intr_info[] = {
4209                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4210                   -1, 1 },
4211                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4212                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4213                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4214                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4215                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4216                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4217                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4218                   -1, 1 },
4219                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4220                   -1, 1 },
4221                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4222                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4223                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4224                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4225                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4226                   -1, 1 },
4227                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4228                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4229                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4230                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4231                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4232                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4233                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4234                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4235                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4236                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4237                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4238                   -1, 1 },
4239                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4240                   -1, 1 },
4241                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4242                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4243                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4244                 { READRSPERR_F, "Outbound read error", -1, 0 },
4245                 { 0 }
4246         };
4247
4248         int fat;
4249
4250         if (is_t4(adapter->params.chip))
4251                 fat = t4_handle_intr_status(adapter,
4252                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4253                                 sysbus_intr_info) +
4254                         t4_handle_intr_status(adapter,
4255                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4256                                         pcie_port_intr_info) +
4257                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4258                                               pcie_intr_info);
4259         else
4260                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4261                                             t5_pcie_intr_info);
4262
4263         if (fat)
4264                 t4_fatal_err(adapter);
4265 }
4266
4267 /*
4268  * TP interrupt handler.
4269  */
4270 static void tp_intr_handler(struct adapter *adapter)
4271 {
4272         static const struct intr_info tp_intr_info[] = {
4273                 { 0x3fffffff, "TP parity error", -1, 1 },
4274                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4275                 { 0 }
4276         };
4277
4278         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4279                 t4_fatal_err(adapter);
4280 }
4281
4282 /*
4283  * SGE interrupt handler.
4284  */
4285 static void sge_intr_handler(struct adapter *adapter)
4286 {
4287         u64 v;
4288         u32 err;
4289
4290         static const struct intr_info sge_intr_info[] = {
4291                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4292                   "SGE received CPL exceeding IQE size", -1, 1 },
4293                 { ERR_INVALID_CIDX_INC_F,
4294                   "SGE GTS CIDX increment too large", -1, 0 },
4295                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4296                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4297                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4298                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4299                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4300                   0 },
4301                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4302                   0 },
4303                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4304                   0 },
4305                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4306                   0 },
4307                 { ERR_ING_CTXT_PRIO_F,
4308                   "SGE too many priority ingress contexts", -1, 0 },
4309                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4310                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4311                 { 0 }
4312         };
4313
4314         static struct intr_info t4t5_sge_intr_info[] = {
4315                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4316                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4317                 { ERR_EGR_CTXT_PRIO_F,
4318                   "SGE too many priority egress contexts", -1, 0 },
4319                 { 0 }
4320         };
4321
4322         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4323                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4324         if (v) {
4325                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4326                                 (unsigned long long)v);
4327                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4328                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4329         }
4330
4331         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4332         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4333                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4334                                            t4t5_sge_intr_info);
4335
4336         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4337         if (err & ERROR_QID_VALID_F) {
4338                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4339                         ERROR_QID_G(err));
4340                 if (err & UNCAPTURED_ERROR_F)
4341                         dev_err(adapter->pdev_dev,
4342                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4343                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4344                              UNCAPTURED_ERROR_F);
4345         }
4346
4347         if (v != 0)
4348                 t4_fatal_err(adapter);
4349 }
4350
4351 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4352                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4353 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4354                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4355
4356 /*
4357  * CIM interrupt handler.
4358  */
4359 static void cim_intr_handler(struct adapter *adapter)
4360 {
4361         static const struct intr_info cim_intr_info[] = {
4362                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4363                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4364                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4365                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4366                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4367                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4368                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4369                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4370                 { 0 }
4371         };
4372         static const struct intr_info cim_upintr_info[] = {
4373                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4374                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4375                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4376                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4377                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4378                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4379                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4380                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4381                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4382                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4383                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4384                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4385                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4386                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4387                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4388                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4389                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4390                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4391                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4392                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4393                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4394                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4395                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4396                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4397                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4398                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4399                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4400                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4401                 { 0 }
4402         };
4403
4404         u32 val, fw_err;
4405         int fat;
4406
4407         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4408         if (fw_err & PCIE_FW_ERR_F)
4409                 t4_report_fw_error(adapter);
4410
4411         /* When the Firmware detects an internal error which normally
4412          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4413          * in order to make sure the Host sees the Firmware Crash.  So
4414          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4415          * ignore the Timer0 interrupt.
4416          */
4417
4418         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4419         if (val & TIMER0INT_F)
4420                 if (!(fw_err & PCIE_FW_ERR_F) ||
4421                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4422                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4423                                      TIMER0INT_F);
4424
4425         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4426                                     cim_intr_info) +
4427               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4428                                     cim_upintr_info);
4429         if (fat)
4430                 t4_fatal_err(adapter);
4431 }
4432
4433 /*
4434  * ULP RX interrupt handler.
4435  */
4436 static void ulprx_intr_handler(struct adapter *adapter)
4437 {
4438         static const struct intr_info ulprx_intr_info[] = {
4439                 { 0x1800000, "ULPRX context error", -1, 1 },
4440                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4441                 { 0 }
4442         };
4443
4444         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4445                 t4_fatal_err(adapter);
4446 }
4447
4448 /*
4449  * ULP TX interrupt handler.
4450  */
4451 static void ulptx_intr_handler(struct adapter *adapter)
4452 {
4453         static const struct intr_info ulptx_intr_info[] = {
4454                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4455                   0 },
4456                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4457                   0 },
4458                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4459                   0 },
4460                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4461                   0 },
4462                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4463                 { 0 }
4464         };
4465
4466         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4467                 t4_fatal_err(adapter);
4468 }
4469
4470 /*
4471  * PM TX interrupt handler.
4472  */
4473 static void pmtx_intr_handler(struct adapter *adapter)
4474 {
4475         static const struct intr_info pmtx_intr_info[] = {
4476                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4477                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4478                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4479                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4480                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4481                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4482                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4483                   -1, 1 },
4484                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4485                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4486                 { 0 }
4487         };
4488
4489         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4490                 t4_fatal_err(adapter);
4491 }
4492
4493 /*
4494  * PM RX interrupt handler.
4495  */
4496 static void pmrx_intr_handler(struct adapter *adapter)
4497 {
4498         static const struct intr_info pmrx_intr_info[] = {
4499                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4500                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4501                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4502                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4503                   -1, 1 },
4504                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4505                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4506                 { 0 }
4507         };
4508
4509         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4510                 t4_fatal_err(adapter);
4511 }
4512
4513 /*
4514  * CPL switch interrupt handler.
4515  */
4516 static void cplsw_intr_handler(struct adapter *adapter)
4517 {
4518         static const struct intr_info cplsw_intr_info[] = {
4519                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4520                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4521                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4522                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4523                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4524                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4525                 { 0 }
4526         };
4527
4528         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4529                 t4_fatal_err(adapter);
4530 }
4531
4532 /*
4533  * LE interrupt handler.
4534  */
4535 static void le_intr_handler(struct adapter *adap)
4536 {
4537         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4538         static const struct intr_info le_intr_info[] = {
4539                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4540                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4541                 { PARITYERR_F, "LE parity error", -1, 1 },
4542                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4543                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4544                 { 0 }
4545         };
4546
4547         static struct intr_info t6_le_intr_info[] = {
4548                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4549                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4550                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4551                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4552                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4553                 { 0 }
4554         };
4555
4556         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4557                                   (chip <= CHELSIO_T5) ?
4558                                   le_intr_info : t6_le_intr_info))
4559                 t4_fatal_err(adap);
4560 }
4561
4562 /*
4563  * MPS interrupt handler.
4564  */
4565 static void mps_intr_handler(struct adapter *adapter)
4566 {
4567         static const struct intr_info mps_rx_intr_info[] = {
4568                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4569                 { 0 }
4570         };
4571         static const struct intr_info mps_tx_intr_info[] = {
4572                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4573                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4574                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4575                   -1, 1 },
4576                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4577                   -1, 1 },
4578                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4579                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4580                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4581                 { 0 }
4582         };
4583         static const struct intr_info t6_mps_tx_intr_info[] = {
4584                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4585                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4586                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4587                   -1, 1 },
4588                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4589                   -1, 1 },
4590                 /* MPS Tx Bubble is normal for T6 */
4591                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4592                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4593                 { 0 }
4594         };
4595         static const struct intr_info mps_trc_intr_info[] = {
4596                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4597                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4598                   -1, 1 },
4599                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4600                 { 0 }
4601         };
4602         static const struct intr_info mps_stat_sram_intr_info[] = {
4603                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4604                 { 0 }
4605         };
4606         static const struct intr_info mps_stat_tx_intr_info[] = {
4607                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4608                 { 0 }
4609         };
4610         static const struct intr_info mps_stat_rx_intr_info[] = {
4611                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4612                 { 0 }
4613         };
4614         static const struct intr_info mps_cls_intr_info[] = {
4615                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4616                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4617                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4618                 { 0 }
4619         };
4620
4621         int fat;
4622
4623         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4624                                     mps_rx_intr_info) +
4625               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4626                                     is_t6(adapter->params.chip)
4627                                     ? t6_mps_tx_intr_info
4628                                     : mps_tx_intr_info) +
4629               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4630                                     mps_trc_intr_info) +
4631               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4632                                     mps_stat_sram_intr_info) +
4633               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4634                                     mps_stat_tx_intr_info) +
4635               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4636                                     mps_stat_rx_intr_info) +
4637               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4638                                     mps_cls_intr_info);
4639
4640         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4641         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4642         if (fat)
4643                 t4_fatal_err(adapter);
4644 }
4645
4646 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4647                       ECC_UE_INT_CAUSE_F)
4648
4649 /*
4650  * EDC/MC interrupt handler.
4651  */
4652 static void mem_intr_handler(struct adapter *adapter, int idx)
4653 {
4654         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4655
4656         unsigned int addr, cnt_addr, v;
4657
4658         if (idx <= MEM_EDC1) {
4659                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4660                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4661         } else if (idx == MEM_MC) {
4662                 if (is_t4(adapter->params.chip)) {
4663                         addr = MC_INT_CAUSE_A;
4664                         cnt_addr = MC_ECC_STATUS_A;
4665                 } else {
4666                         addr = MC_P_INT_CAUSE_A;
4667                         cnt_addr = MC_P_ECC_STATUS_A;
4668                 }
4669         } else {
4670                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4671                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4672         }
4673
4674         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4675         if (v & PERR_INT_CAUSE_F)
4676                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4677                           name[idx]);
4678         if (v & ECC_CE_INT_CAUSE_F) {
4679                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4680
4681                 t4_edc_err_read(adapter, idx);
4682
4683                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4684                 if (printk_ratelimit())
4685                         dev_warn(adapter->pdev_dev,
4686                                  "%u %s correctable ECC data error%s\n",
4687                                  cnt, name[idx], cnt > 1 ? "s" : "");
4688         }
4689         if (v & ECC_UE_INT_CAUSE_F)
4690                 dev_alert(adapter->pdev_dev,
4691                           "%s uncorrectable ECC data error\n", name[idx]);
4692
4693         t4_write_reg(adapter, addr, v);
4694         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4695                 t4_fatal_err(adapter);
4696 }
4697
4698 /*
4699  * MA interrupt handler.
4700  */
4701 static void ma_intr_handler(struct adapter *adap)
4702 {
4703         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4704
4705         if (status & MEM_PERR_INT_CAUSE_F) {
4706                 dev_alert(adap->pdev_dev,
4707                           "MA parity error, parity status %#x\n",
4708                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4709                 if (is_t5(adap->params.chip))
4710                         dev_alert(adap->pdev_dev,
4711                                   "MA parity error, parity status %#x\n",
4712                                   t4_read_reg(adap,
4713                                               MA_PARITY_ERROR_STATUS2_A));
4714         }
4715         if (status & MEM_WRAP_INT_CAUSE_F) {
4716                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4717                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4718                           "client %u to address %#x\n",
4719                           MEM_WRAP_CLIENT_NUM_G(v),
4720                           MEM_WRAP_ADDRESS_G(v) << 4);
4721         }
4722         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4723         t4_fatal_err(adap);
4724 }
4725
4726 /*
4727  * SMB interrupt handler.
4728  */
4729 static void smb_intr_handler(struct adapter *adap)
4730 {
4731         static const struct intr_info smb_intr_info[] = {
4732                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4733                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4734                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4735                 { 0 }
4736         };
4737
4738         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4739                 t4_fatal_err(adap);
4740 }
4741
4742 /*
4743  * NC-SI interrupt handler.
4744  */
4745 static void ncsi_intr_handler(struct adapter *adap)
4746 {
4747         static const struct intr_info ncsi_intr_info[] = {
4748                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4749                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4750                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4751                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4752                 { 0 }
4753         };
4754
4755         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4756                 t4_fatal_err(adap);
4757 }
4758
4759 /*
4760  * XGMAC interrupt handler.
4761  */
4762 static void xgmac_intr_handler(struct adapter *adap, int port)
4763 {
4764         u32 v, int_cause_reg;
4765
4766         if (is_t4(adap->params.chip))
4767                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4768         else
4769                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4770
4771         v = t4_read_reg(adap, int_cause_reg);
4772
4773         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4774         if (!v)
4775                 return;
4776
4777         if (v & TXFIFO_PRTY_ERR_F)
4778                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4779                           port);
4780         if (v & RXFIFO_PRTY_ERR_F)
4781                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4782                           port);
4783         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4784         t4_fatal_err(adap);
4785 }
4786
4787 /*
4788  * PL interrupt handler.
4789  */
4790 static void pl_intr_handler(struct adapter *adap)
4791 {
4792         static const struct intr_info pl_intr_info[] = {
4793                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4794                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4795                 { 0 }
4796         };
4797
4798         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4799                 t4_fatal_err(adap);
4800 }
4801
4802 #define PF_INTR_MASK (PFSW_F)
4803 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4804                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4805                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4806
4807 /**
4808  *      t4_slow_intr_handler - control path interrupt handler
4809  *      @adapter: the adapter
4810  *
4811  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4812  *      The designation 'slow' is because it involves register reads, while
4813  *      data interrupts typically don't involve any MMIOs.
4814  */
4815 int t4_slow_intr_handler(struct adapter *adapter)
4816 {
4817         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4818
4819         if (!(cause & GLBL_INTR_MASK))
4820                 return 0;
4821         if (cause & CIM_F)
4822                 cim_intr_handler(adapter);
4823         if (cause & MPS_F)
4824                 mps_intr_handler(adapter);
4825         if (cause & NCSI_F)
4826                 ncsi_intr_handler(adapter);
4827         if (cause & PL_F)
4828                 pl_intr_handler(adapter);
4829         if (cause & SMB_F)
4830                 smb_intr_handler(adapter);
4831         if (cause & XGMAC0_F)
4832                 xgmac_intr_handler(adapter, 0);
4833         if (cause & XGMAC1_F)
4834                 xgmac_intr_handler(adapter, 1);
4835         if (cause & XGMAC_KR0_F)
4836                 xgmac_intr_handler(adapter, 2);
4837         if (cause & XGMAC_KR1_F)
4838                 xgmac_intr_handler(adapter, 3);
4839         if (cause & PCIE_F)
4840                 pcie_intr_handler(adapter);
4841         if (cause & MC_F)
4842                 mem_intr_handler(adapter, MEM_MC);
4843         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4844                 mem_intr_handler(adapter, MEM_MC1);
4845         if (cause & EDC0_F)
4846                 mem_intr_handler(adapter, MEM_EDC0);
4847         if (cause & EDC1_F)
4848                 mem_intr_handler(adapter, MEM_EDC1);
4849         if (cause & LE_F)
4850                 le_intr_handler(adapter);
4851         if (cause & TP_F)
4852                 tp_intr_handler(adapter);
4853         if (cause & MA_F)
4854                 ma_intr_handler(adapter);
4855         if (cause & PM_TX_F)
4856                 pmtx_intr_handler(adapter);
4857         if (cause & PM_RX_F)
4858                 pmrx_intr_handler(adapter);
4859         if (cause & ULP_RX_F)
4860                 ulprx_intr_handler(adapter);
4861         if (cause & CPL_SWITCH_F)
4862                 cplsw_intr_handler(adapter);
4863         if (cause & SGE_F)
4864                 sge_intr_handler(adapter);
4865         if (cause & ULP_TX_F)
4866                 ulptx_intr_handler(adapter);
4867
4868         /* Clear the interrupts just processed for which we are the master. */
4869         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4870         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4871         return 1;
4872 }
4873
4874 /**
4875  *      t4_intr_enable - enable interrupts
4876  *      @adapter: the adapter whose interrupts should be enabled
4877  *
4878  *      Enable PF-specific interrupts for the calling function and the top-level
4879  *      interrupt concentrator for global interrupts.  Interrupts are already
4880  *      enabled at each module, here we just enable the roots of the interrupt
4881  *      hierarchies.
4882  *
4883  *      Note: this function should be called only when the driver manages
4884  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4885  *      function at a time should be doing this.
4886  */
4887 void t4_intr_enable(struct adapter *adapter)
4888 {
4889         u32 val = 0;
4890         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4891         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4892                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4893
4894         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4895                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4896         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4897                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4898                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4899                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4900                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4901                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4902                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4903         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4904         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4905 }
4906
4907 /**
4908  *      t4_intr_disable - disable interrupts
4909  *      @adapter: the adapter whose interrupts should be disabled
4910  *
4911  *      Disable interrupts.  We only disable the top-level interrupt
4912  *      concentrators.  The caller must be a PCI function managing global
4913  *      interrupts.
4914  */
4915 void t4_intr_disable(struct adapter *adapter)
4916 {
4917         u32 whoami, pf;
4918
4919         if (pci_channel_offline(adapter->pdev))
4920                 return;
4921
4922         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4923         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4924                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4925
4926         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4927         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4928 }
4929
4930 /**
4931  *      t4_config_rss_range - configure a portion of the RSS mapping table
4932  *      @adapter: the adapter
4933  *      @mbox: mbox to use for the FW command
4934  *      @viid: virtual interface whose RSS subtable is to be written
4935  *      @start: start entry in the table to write
4936  *      @n: how many table entries to write
4937  *      @rspq: values for the response queue lookup table
4938  *      @nrspq: number of values in @rspq
4939  *
4940  *      Programs the selected part of the VI's RSS mapping table with the
4941  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4942  *      until the full table range is populated.
4943  *
4944  *      The caller must ensure the values in @rspq are in the range allowed for
4945  *      @viid.
4946  */
4947 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4948                         int start, int n, const u16 *rspq, unsigned int nrspq)
4949 {
4950         int ret;
4951         const u16 *rsp = rspq;
4952         const u16 *rsp_end = rspq + nrspq;
4953         struct fw_rss_ind_tbl_cmd cmd;
4954
4955         memset(&cmd, 0, sizeof(cmd));
4956         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4957                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4958                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4959         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4960
4961         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4962         while (n > 0) {
4963                 int nq = min(n, 32);
4964                 __be32 *qp = &cmd.iq0_to_iq2;
4965
4966                 cmd.niqid = cpu_to_be16(nq);
4967                 cmd.startidx = cpu_to_be16(start);
4968
4969                 start += nq;
4970                 n -= nq;
4971
4972                 while (nq > 0) {
4973                         unsigned int v;
4974
4975                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4976                         if (++rsp >= rsp_end)
4977                                 rsp = rspq;
4978                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4979                         if (++rsp >= rsp_end)
4980                                 rsp = rspq;
4981                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4982                         if (++rsp >= rsp_end)
4983                                 rsp = rspq;
4984
4985                         *qp++ = cpu_to_be32(v);
4986                         nq -= 3;
4987                 }
4988
4989                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4990                 if (ret)
4991                         return ret;
4992         }
4993         return 0;
4994 }
4995
4996 /**
4997  *      t4_config_glbl_rss - configure the global RSS mode
4998  *      @adapter: the adapter
4999  *      @mbox: mbox to use for the FW command
5000  *      @mode: global RSS mode
5001  *      @flags: mode-specific flags
5002  *
5003  *      Sets the global RSS mode.
5004  */
5005 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5006                        unsigned int flags)
5007 {
5008         struct fw_rss_glb_config_cmd c;
5009
5010         memset(&c, 0, sizeof(c));
5011         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5012                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5013         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5014         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5015                 c.u.manual.mode_pkd =
5016                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5017         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5018                 c.u.basicvirtual.mode_pkd =
5019                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5020                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5021         } else
5022                 return -EINVAL;
5023         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5024 }
5025
5026 /**
5027  *      t4_config_vi_rss - configure per VI RSS settings
5028  *      @adapter: the adapter
5029  *      @mbox: mbox to use for the FW command
5030  *      @viid: the VI id
5031  *      @flags: RSS flags
5032  *      @defq: id of the default RSS queue for the VI.
5033  *
5034  *      Configures VI-specific RSS properties.
5035  */
5036 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5037                      unsigned int flags, unsigned int defq)
5038 {
5039         struct fw_rss_vi_config_cmd c;
5040
5041         memset(&c, 0, sizeof(c));
5042         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5043                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5044                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5045         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5046         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5047                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5048         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5049 }
5050
5051 /* Read an RSS table row */
5052 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5053 {
5054         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5055         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5056                                    5, 0, val);
5057 }
5058
5059 /**
5060  *      t4_read_rss - read the contents of the RSS mapping table
5061  *      @adapter: the adapter
5062  *      @map: holds the contents of the RSS mapping table
5063  *
5064  *      Reads the contents of the RSS hash->queue mapping table.
5065  */
5066 int t4_read_rss(struct adapter *adapter, u16 *map)
5067 {
5068         u32 val;
5069         int i, ret;
5070
5071         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5072                 ret = rd_rss_row(adapter, i, &val);
5073                 if (ret)
5074                         return ret;
5075                 *map++ = LKPTBLQUEUE0_G(val);
5076                 *map++ = LKPTBLQUEUE1_G(val);
5077         }
5078         return 0;
5079 }
5080
5081 static unsigned int t4_use_ldst(struct adapter *adap)
5082 {
5083         return (adap->flags & FW_OK) || !adap->use_bd;
5084 }
5085
5086 /**
5087  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5088  * @adap: the adapter
5089  * @cmd: TP fw ldst address space type
5090  * @vals: where the indirect register values are stored/written
5091  * @nregs: how many indirect registers to read/write
5092  * @start_idx: index of first indirect register to read/write
5093  * @rw: Read (1) or Write (0)
5094  * @sleep_ok: if true we may sleep while awaiting command completion
5095  *
5096  * Access TP indirect registers through LDST
5097  */
5098 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5099                             unsigned int nregs, unsigned int start_index,
5100                             unsigned int rw, bool sleep_ok)
5101 {
5102         int ret = 0;
5103         unsigned int i;
5104         struct fw_ldst_cmd c;
5105
5106         for (i = 0; i < nregs; i++) {
5107                 memset(&c, 0, sizeof(c));
5108                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5109                                                 FW_CMD_REQUEST_F |
5110                                                 (rw ? FW_CMD_READ_F :
5111                                                       FW_CMD_WRITE_F) |
5112                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5113                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5114
5115                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5116                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5117                 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5118                                       sleep_ok);
5119                 if (ret)
5120                         return ret;
5121
5122                 if (rw)
5123                         vals[i] = be32_to_cpu(c.u.addrval.val);
5124         }
5125         return 0;
5126 }
5127
5128 /**
5129  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5130  * @adap: the adapter
5131  * @reg_addr: Address Register
5132  * @reg_data: Data register
5133  * @buff: where the indirect register values are stored/written
5134  * @nregs: how many indirect registers to read/write
5135  * @start_index: index of first indirect register to read/write
5136  * @rw: READ(1) or WRITE(0)
5137  * @sleep_ok: if true we may sleep while awaiting command completion
5138  *
5139  * Read/Write TP indirect registers through LDST if possible.
5140  * Else, use backdoor access
5141  **/
5142 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5143                               u32 *buff, u32 nregs, u32 start_index, int rw,
5144                               bool sleep_ok)
5145 {
5146         int rc = -EINVAL;
5147         int cmd;
5148
5149         switch (reg_addr) {
5150         case TP_PIO_ADDR_A:
5151                 cmd = FW_LDST_ADDRSPC_TP_PIO;
5152                 break;
5153         case TP_TM_PIO_ADDR_A:
5154                 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5155                 break;
5156         case TP_MIB_INDEX_A:
5157                 cmd = FW_LDST_ADDRSPC_TP_MIB;
5158                 break;
5159         default:
5160                 goto indirect_access;
5161         }
5162
5163         if (t4_use_ldst(adap))
5164                 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5165                                       sleep_ok);
5166
5167 indirect_access:
5168
5169         if (rc) {
5170                 if (rw)
5171                         t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5172                                          start_index);
5173                 else
5174                         t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5175                                           start_index);
5176         }
5177 }
5178
5179 /**
5180  * t4_tp_pio_read - Read TP PIO registers
5181  * @adap: the adapter
5182  * @buff: where the indirect register values are written
5183  * @nregs: how many indirect registers to read
5184  * @start_index: index of first indirect register to read
5185  * @sleep_ok: if true we may sleep while awaiting command completion
5186  *
5187  * Read TP PIO Registers
5188  **/
5189 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5190                     u32 start_index, bool sleep_ok)
5191 {
5192         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5193                           start_index, 1, sleep_ok);
5194 }
5195
5196 /**
5197  * t4_tp_pio_write - Write TP PIO registers
5198  * @adap: the adapter
5199  * @buff: where the indirect register values are stored
5200  * @nregs: how many indirect registers to write
5201  * @start_index: index of first indirect register to write
5202  * @sleep_ok: if true we may sleep while awaiting command completion
5203  *
5204  * Write TP PIO Registers
5205  **/
5206 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5207                             u32 start_index, bool sleep_ok)
5208 {
5209         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5210                           start_index, 0, sleep_ok);
5211 }
5212
5213 /**
5214  * t4_tp_tm_pio_read - Read TP TM PIO registers
5215  * @adap: the adapter
5216  * @buff: where the indirect register values are written
5217  * @nregs: how many indirect registers to read
5218  * @start_index: index of first indirect register to read
5219  * @sleep_ok: if true we may sleep while awaiting command completion
5220  *
5221  * Read TP TM PIO Registers
5222  **/
5223 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5224                        u32 start_index, bool sleep_ok)
5225 {
5226         t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5227                           nregs, start_index, 1, sleep_ok);
5228 }
5229
5230 /**
5231  * t4_tp_mib_read - Read TP MIB registers
5232  * @adap: the adapter
5233  * @buff: where the indirect register values are written
5234  * @nregs: how many indirect registers to read
5235  * @start_index: index of first indirect register to read
5236  * @sleep_ok: if true we may sleep while awaiting command completion
5237  *
5238  * Read TP MIB Registers
5239  **/
5240 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5241                     bool sleep_ok)
5242 {
5243         t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5244                           start_index, 1, sleep_ok);
5245 }
5246
5247 /**
5248  *      t4_read_rss_key - read the global RSS key
5249  *      @adap: the adapter
5250  *      @key: 10-entry array holding the 320-bit RSS key
5251  *      @sleep_ok: if true we may sleep while awaiting command completion
5252  *
5253  *      Reads the global 320-bit RSS key.
5254  */
5255 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5256 {
5257         t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5258 }
5259
5260 /**
5261  *      t4_write_rss_key - program one of the RSS keys
5262  *      @adap: the adapter
5263  *      @key: 10-entry array holding the 320-bit RSS key
5264  *      @idx: which RSS key to write
5265  *      @sleep_ok: if true we may sleep while awaiting command completion
5266  *
5267  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5268  *      0..15 the corresponding entry in the RSS key table is written,
5269  *      otherwise the global RSS key is written.
5270  */
5271 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5272                       bool sleep_ok)
5273 {
5274         u8 rss_key_addr_cnt = 16;
5275         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5276
5277         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5278          * allows access to key addresses 16-63 by using KeyWrAddrX
5279          * as index[5:4](upper 2) into key table
5280          */
5281         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5282             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5283                 rss_key_addr_cnt = 32;
5284
5285         t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5286
5287         if (idx >= 0 && idx < rss_key_addr_cnt) {
5288                 if (rss_key_addr_cnt > 16)
5289                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5290                                      KEYWRADDRX_V(idx >> 4) |
5291                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5292                 else
5293                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5294                                      KEYWRADDR_V(idx) | KEYWREN_F);
5295         }
5296 }
5297
5298 /**
5299  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5300  *      @adapter: the adapter
5301  *      @index: the entry in the PF RSS table to read
5302  *      @valp: where to store the returned value
5303  *      @sleep_ok: if true we may sleep while awaiting command completion
5304  *
5305  *      Reads the PF RSS Configuration Table at the specified index and returns
5306  *      the value found there.
5307  */
5308 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5309                            u32 *valp, bool sleep_ok)
5310 {
5311         t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5312 }
5313
5314 /**
5315  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5316  *      @adapter: the adapter
5317  *      @index: the entry in the VF RSS table to read
5318  *      @vfl: where to store the returned VFL
5319  *      @vfh: where to store the returned VFH
5320  *      @sleep_ok: if true we may sleep while awaiting command completion
5321  *
5322  *      Reads the VF RSS Configuration Table at the specified index and returns
5323  *      the (VFL, VFH) values found there.
5324  */
5325 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5326                            u32 *vfl, u32 *vfh, bool sleep_ok)
5327 {
5328         u32 vrt, mask, data;
5329
5330         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5331                 mask = VFWRADDR_V(VFWRADDR_M);
5332                 data = VFWRADDR_V(index);
5333         } else {
5334                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5335                  data = T6_VFWRADDR_V(index);
5336         }
5337
5338         /* Request that the index'th VF Table values be read into VFL/VFH.
5339          */
5340         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5341         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5342         vrt |= data | VFRDEN_F;
5343         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5344
5345         /* Grab the VFL/VFH values ...
5346          */
5347         t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5348         t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5349 }
5350
5351 /**
5352  *      t4_read_rss_pf_map - read PF RSS Map
5353  *      @adapter: the adapter
5354  *      @sleep_ok: if true we may sleep while awaiting command completion
5355  *
5356  *      Reads the PF RSS Map register and returns its value.
5357  */
5358 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5359 {
5360         u32 pfmap;
5361
5362         t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5363         return pfmap;
5364 }
5365
5366 /**
5367  *      t4_read_rss_pf_mask - read PF RSS Mask
5368  *      @adapter: the adapter
5369  *      @sleep_ok: if true we may sleep while awaiting command completion
5370  *
5371  *      Reads the PF RSS Mask register and returns its value.
5372  */
5373 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5374 {
5375         u32 pfmask;
5376
5377         t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5378         return pfmask;
5379 }
5380
5381 /**
5382  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5383  *      @adap: the adapter
5384  *      @v4: holds the TCP/IP counter values
5385  *      @v6: holds the TCP/IPv6 counter values
5386  *      @sleep_ok: if true we may sleep while awaiting command completion
5387  *
5388  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5389  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5390  */
5391 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5392                          struct tp_tcp_stats *v6, bool sleep_ok)
5393 {
5394         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5395
5396 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5397 #define STAT(x)     val[STAT_IDX(x)]
5398 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5399
5400         if (v4) {
5401                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5402                                TP_MIB_TCP_OUT_RST_A, sleep_ok);
5403                 v4->tcp_out_rsts = STAT(OUT_RST);
5404                 v4->tcp_in_segs  = STAT64(IN_SEG);
5405                 v4->tcp_out_segs = STAT64(OUT_SEG);
5406                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5407         }
5408         if (v6) {
5409                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5410                                TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5411                 v6->tcp_out_rsts = STAT(OUT_RST);
5412                 v6->tcp_in_segs  = STAT64(IN_SEG);
5413                 v6->tcp_out_segs = STAT64(OUT_SEG);
5414                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5415         }
5416 #undef STAT64
5417 #undef STAT
5418 #undef STAT_IDX
5419 }
5420
5421 /**
5422  *      t4_tp_get_err_stats - read TP's error MIB counters
5423  *      @adap: the adapter
5424  *      @st: holds the counter values
5425  *      @sleep_ok: if true we may sleep while awaiting command completion
5426  *
5427  *      Returns the values of TP's error counters.
5428  */
5429 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5430                          bool sleep_ok)
5431 {
5432         int nchan = adap->params.arch.nchan;
5433
5434         t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5435                        sleep_ok);
5436         t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5437                        sleep_ok);
5438         t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5439                        sleep_ok);
5440         t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5441                        TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5442         t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5443                        TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5444         t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5445                        sleep_ok);
5446         t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5447                        TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5448         t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5449                        TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5450         t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5451                        sleep_ok);
5452 }
5453
5454 /**
5455  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5456  *      @adap: the adapter
5457  *      @st: holds the counter values
5458  *      @sleep_ok: if true we may sleep while awaiting command completion
5459  *
5460  *      Returns the values of TP's CPL counters.
5461  */
5462 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5463                          bool sleep_ok)
5464 {
5465         int nchan = adap->params.arch.nchan;
5466
5467         t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5468
5469         t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5470 }
5471
5472 /**
5473  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5474  *      @adap: the adapter
5475  *      @st: holds the counter values
5476  *      @sleep_ok: if true we may sleep while awaiting command completion
5477  *
5478  *      Returns the values of TP's RDMA counters.
5479  */
5480 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5481                           bool sleep_ok)
5482 {
5483         t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5484                        sleep_ok);
5485 }
5486
5487 /**
5488  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5489  *      @adap: the adapter
5490  *      @idx: the port index
5491  *      @st: holds the counter values
5492  *      @sleep_ok: if true we may sleep while awaiting command completion
5493  *
5494  *      Returns the values of TP's FCoE counters for the selected port.
5495  */
5496 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5497                        struct tp_fcoe_stats *st, bool sleep_ok)
5498 {
5499         u32 val[2];
5500
5501         t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5502                        sleep_ok);
5503
5504         t4_tp_mib_read(adap, &st->frames_drop, 1,
5505                        TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5506
5507         t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5508                        sleep_ok);
5509
5510         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5511 }
5512
5513 /**
5514  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5515  *      @adap: the adapter
5516  *      @st: holds the counter values
5517  *      @sleep_ok: if true we may sleep while awaiting command completion
5518  *
5519  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5520  */
5521 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5522                       bool sleep_ok)
5523 {
5524         u32 val[4];
5525
5526         t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5527         st->frames = val[0];
5528         st->drops = val[1];
5529         st->octets = ((u64)val[2] << 32) | val[3];
5530 }
5531
5532 /**
5533  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5534  *      @adap: the adapter
5535  *      @mtus: where to store the MTU values
5536  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5537  *
5538  *      Reads the HW path MTU table.
5539  */
5540 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5541 {
5542         u32 v;
5543         int i;
5544
5545         for (i = 0; i < NMTUS; ++i) {
5546                 t4_write_reg(adap, TP_MTU_TABLE_A,
5547                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5548                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5549                 mtus[i] = MTUVALUE_G(v);
5550                 if (mtu_log)
5551                         mtu_log[i] = MTUWIDTH_G(v);
5552         }
5553 }
5554
5555 /**
5556  *      t4_read_cong_tbl - reads the congestion control table
5557  *      @adap: the adapter
5558  *      @incr: where to store the alpha values
5559  *
5560  *      Reads the additive increments programmed into the HW congestion
5561  *      control table.
5562  */
5563 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5564 {
5565         unsigned int mtu, w;
5566
5567         for (mtu = 0; mtu < NMTUS; ++mtu)
5568                 for (w = 0; w < NCCTRL_WIN; ++w) {
5569                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5570                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5571                         incr[mtu][w] = (u16)t4_read_reg(adap,
5572                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5573                 }
5574 }
5575
5576 /**
5577  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5578  *      @adap: the adapter
5579  *      @addr: the indirect TP register address
5580  *      @mask: specifies the field within the register to modify
5581  *      @val: new value for the field
5582  *
5583  *      Sets a field of an indirect TP register to the given value.
5584  */
5585 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5586                             unsigned int mask, unsigned int val)
5587 {
5588         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5589         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5590         t4_write_reg(adap, TP_PIO_DATA_A, val);
5591 }
5592
5593 /**
5594  *      init_cong_ctrl - initialize congestion control parameters
5595  *      @a: the alpha values for congestion control
5596  *      @b: the beta values for congestion control
5597  *
5598  *      Initialize the congestion control parameters.
5599  */
5600 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5601 {
5602         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5603         a[9] = 2;
5604         a[10] = 3;
5605         a[11] = 4;
5606         a[12] = 5;
5607         a[13] = 6;
5608         a[14] = 7;
5609         a[15] = 8;
5610         a[16] = 9;
5611         a[17] = 10;
5612         a[18] = 14;
5613         a[19] = 17;
5614         a[20] = 21;
5615         a[21] = 25;
5616         a[22] = 30;
5617         a[23] = 35;
5618         a[24] = 45;
5619         a[25] = 60;
5620         a[26] = 80;
5621         a[27] = 100;
5622         a[28] = 200;
5623         a[29] = 300;
5624         a[30] = 400;
5625         a[31] = 500;
5626
5627         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5628         b[9] = b[10] = 1;
5629         b[11] = b[12] = 2;
5630         b[13] = b[14] = b[15] = b[16] = 3;
5631         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5632         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5633         b[28] = b[29] = 6;
5634         b[30] = b[31] = 7;
5635 }
5636
5637 /* The minimum additive increment value for the congestion control table */
5638 #define CC_MIN_INCR 2U
5639
5640 /**
5641  *      t4_load_mtus - write the MTU and congestion control HW tables
5642  *      @adap: the adapter
5643  *      @mtus: the values for the MTU table
5644  *      @alpha: the values for the congestion control alpha parameter
5645  *      @beta: the values for the congestion control beta parameter
5646  *
5647  *      Write the HW MTU table with the supplied MTUs and the high-speed
5648  *      congestion control table with the supplied alpha, beta, and MTUs.
5649  *      We write the two tables together because the additive increments
5650  *      depend on the MTUs.
5651  */
5652 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5653                   const unsigned short *alpha, const unsigned short *beta)
5654 {
5655         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5656                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5657                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5658                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5659         };
5660
5661         unsigned int i, w;
5662
5663         for (i = 0; i < NMTUS; ++i) {
5664                 unsigned int mtu = mtus[i];
5665                 unsigned int log2 = fls(mtu);
5666
5667                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5668                         log2--;
5669                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5670                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5671
5672                 for (w = 0; w < NCCTRL_WIN; ++w) {
5673                         unsigned int inc;
5674
5675                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5676                                   CC_MIN_INCR);
5677
5678                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5679                                      (w << 16) | (beta[w] << 13) | inc);
5680                 }
5681         }
5682 }
5683
5684 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5685  * clocks.  The formula is
5686  *
5687  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5688  *
5689  * which is equivalent to
5690  *
5691  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5692  */
5693 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5694 {
5695         u64 v = bytes256 * adap->params.vpd.cclk;
5696
5697         return v * 62 + v / 2;
5698 }
5699
5700 /**
5701  *      t4_get_chan_txrate - get the current per channel Tx rates
5702  *      @adap: the adapter
5703  *      @nic_rate: rates for NIC traffic
5704  *      @ofld_rate: rates for offloaded traffic
5705  *
5706  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5707  *      for each channel.
5708  */
5709 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5710 {
5711         u32 v;
5712
5713         v = t4_read_reg(adap, TP_TX_TRATE_A);
5714         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5715         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5716         if (adap->params.arch.nchan == NCHAN) {
5717                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5718                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5719         }
5720
5721         v = t4_read_reg(adap, TP_TX_ORATE_A);
5722         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5723         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5724         if (adap->params.arch.nchan == NCHAN) {
5725                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5726                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5727         }
5728 }
5729
5730 /**
5731  *      t4_set_trace_filter - configure one of the tracing filters
5732  *      @adap: the adapter
5733  *      @tp: the desired trace filter parameters
5734  *      @idx: which filter to configure
5735  *      @enable: whether to enable or disable the filter
5736  *
5737  *      Configures one of the tracing filters available in HW.  If @enable is
5738  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5739  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5740  */
5741 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5742                         int idx, int enable)
5743 {
5744         int i, ofst = idx * 4;
5745         u32 data_reg, mask_reg, cfg;
5746         u32 multitrc = TRCMULTIFILTER_F;
5747
5748         if (!enable) {
5749                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5750                 return 0;
5751         }
5752
5753         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5754         if (cfg & TRCMULTIFILTER_F) {
5755                 /* If multiple tracers are enabled, then maximum
5756                  * capture size is 2.5KB (FIFO size of a single channel)
5757                  * minus 2 flits for CPL_TRACE_PKT header.
5758                  */
5759                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5760                         return -EINVAL;
5761         } else {
5762                 /* If multiple tracers are disabled, to avoid deadlocks
5763                  * maximum packet capture size of 9600 bytes is recommended.
5764                  * Also in this mode, only trace0 can be enabled and running.
5765                  */
5766                 multitrc = 0;
5767                 if (tp->snap_len > 9600 || idx)
5768                         return -EINVAL;
5769         }
5770
5771         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5772             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5773             tp->min_len > TFMINPKTSIZE_M)
5774                 return -EINVAL;
5775
5776         /* stop the tracer we'll be changing */
5777         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5778
5779         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5780         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5781         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5782
5783         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5784                 t4_write_reg(adap, data_reg, tp->data[i]);
5785                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5786         }
5787         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5788                      TFCAPTUREMAX_V(tp->snap_len) |
5789                      TFMINPKTSIZE_V(tp->min_len));
5790         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5791                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5792                      (is_t4(adap->params.chip) ?
5793                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5794                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5795                      T5_TFINVERTMATCH_V(tp->invert)));
5796
5797         return 0;
5798 }
5799
5800 /**
5801  *      t4_get_trace_filter - query one of the tracing filters
5802  *      @adap: the adapter
5803  *      @tp: the current trace filter parameters
5804  *      @idx: which trace filter to query
5805  *      @enabled: non-zero if the filter is enabled
5806  *
5807  *      Returns the current settings of one of the HW tracing filters.
5808  */
5809 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5810                          int *enabled)
5811 {
5812         u32 ctla, ctlb;
5813         int i, ofst = idx * 4;
5814         u32 data_reg, mask_reg;
5815
5816         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5817         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5818
5819         if (is_t4(adap->params.chip)) {
5820                 *enabled = !!(ctla & TFEN_F);
5821                 tp->port =  TFPORT_G(ctla);
5822                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5823         } else {
5824                 *enabled = !!(ctla & T5_TFEN_F);
5825                 tp->port = T5_TFPORT_G(ctla);
5826                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5827         }
5828         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5829         tp->min_len = TFMINPKTSIZE_G(ctlb);
5830         tp->skip_ofst = TFOFFSET_G(ctla);
5831         tp->skip_len = TFLENGTH_G(ctla);
5832
5833         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5834         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5835         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5836
5837         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5838                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5839                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5840         }
5841 }
5842
5843 /**
5844  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5845  *      @adap: the adapter
5846  *      @cnt: where to store the count statistics
5847  *      @cycles: where to store the cycle statistics
5848  *
5849  *      Returns performance statistics from PMTX.
5850  */
5851 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5852 {
5853         int i;
5854         u32 data[2];
5855
5856         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5857                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5858                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5859                 if (is_t4(adap->params.chip)) {
5860                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5861                 } else {
5862                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5863                                          PM_TX_DBG_DATA_A, data, 2,
5864                                          PM_TX_DBG_STAT_MSB_A);
5865                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5866                 }
5867         }
5868 }
5869
5870 /**
5871  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5872  *      @adap: the adapter
5873  *      @cnt: where to store the count statistics
5874  *      @cycles: where to store the cycle statistics
5875  *
5876  *      Returns performance statistics from PMRX.
5877  */
5878 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5879 {
5880         int i;
5881         u32 data[2];
5882
5883         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5884                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5885                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5886                 if (is_t4(adap->params.chip)) {
5887                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5888                 } else {
5889                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5890                                          PM_RX_DBG_DATA_A, data, 2,
5891                                          PM_RX_DBG_STAT_MSB_A);
5892                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5893                 }
5894         }
5895 }
5896
5897 /**
5898  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5899  *      @adap: the adapter
5900  *      @pidx: the port index
5901  *
5902  *      Computes and returns a bitmap indicating which MPS buffer groups are
5903  *      associated with the given Port.  Bit i is set if buffer group i is
5904  *      used by the Port.
5905  */
5906 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5907                                               int pidx)
5908 {
5909         unsigned int chip_version, nports;
5910
5911         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5912         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5913
5914         switch (chip_version) {
5915         case CHELSIO_T4:
5916         case CHELSIO_T5:
5917                 switch (nports) {
5918                 case 1: return 0xf;
5919                 case 2: return 3 << (2 * pidx);
5920                 case 4: return 1 << pidx;
5921                 }
5922                 break;
5923
5924         case CHELSIO_T6:
5925                 switch (nports) {
5926                 case 2: return 1 << (2 * pidx);
5927                 }
5928                 break;
5929         }
5930
5931         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
5932                 chip_version, nports);
5933
5934         return 0;
5935 }
5936
5937 /**
5938  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5939  *      @adapter: the adapter
5940  *      @pidx: the port index
5941  *
5942  *      Returns a bitmap indicating which MPS buffer groups are associated
5943  *      with the given Port.  Bit i is set if buffer group i is used by the
5944  *      Port.
5945  */
5946 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
5947 {
5948         u8 *mps_bg_map;
5949         unsigned int nports;
5950
5951         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5952         if (pidx >= nports) {
5953                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
5954                         pidx, nports);
5955                 return 0;
5956         }
5957
5958         /* If we've already retrieved/computed this, just return the result.
5959          */
5960         mps_bg_map = adapter->params.mps_bg_map;
5961         if (mps_bg_map[pidx])
5962                 return mps_bg_map[pidx];
5963
5964         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
5965          * If we're talking to such Firmware, let it tell us.  If the new
5966          * API isn't supported, revert back to old hardcoded way.  The value
5967          * obtained from Firmware is encoded in below format:
5968          *
5969          * val = (( MPSBGMAP[Port 3] << 24 ) |
5970          *        ( MPSBGMAP[Port 2] << 16 ) |
5971          *        ( MPSBGMAP[Port 1] <<  8 ) |
5972          *        ( MPSBGMAP[Port 0] <<  0 ))
5973          */
5974         if (adapter->flags & FW_OK) {
5975                 u32 param, val;
5976                 int ret;
5977
5978                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5979                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
5980                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
5981                                          0, 1, &param, &val);
5982                 if (!ret) {
5983                         int p;
5984
5985                         /* Store the BG Map for all of the Ports in order to
5986                          * avoid more calls to the Firmware in the future.
5987                          */
5988                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
5989                                 mps_bg_map[p] = val & 0xff;
5990
5991                         return mps_bg_map[pidx];
5992                 }
5993         }
5994
5995         /* Either we're not talking to the Firmware or we're dealing with
5996          * older Firmware which doesn't support the new API to get the MPS
5997          * Buffer Group Map.  Fall back to computing it ourselves.
5998          */
5999         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6000         return mps_bg_map[pidx];
6001 }
6002
6003 /**
6004  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
6005  *      @adapter: the adapter
6006  *      @pidx: the port index
6007  *
6008  *      Returns a bitmap indicating which TP Ingress Channels are associated
6009  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
6010  *      the Port.
6011  */
6012 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6013 {
6014         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6015         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6016
6017         if (pidx >= nports) {
6018                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6019                          pidx, nports);
6020                 return 0;
6021         }
6022
6023         switch (chip_version) {
6024         case CHELSIO_T4:
6025         case CHELSIO_T5:
6026                 /* Note that this happens to be the same values as the MPS
6027                  * Buffer Group Map for these Chips.  But we replicate the code
6028                  * here because they're really separate concepts.
6029                  */
6030                 switch (nports) {
6031                 case 1: return 0xf;
6032                 case 2: return 3 << (2 * pidx);
6033                 case 4: return 1 << pidx;
6034                 }
6035                 break;
6036
6037         case CHELSIO_T6:
6038                 switch (nports) {
6039                 case 2: return 1 << pidx;
6040                 }
6041                 break;
6042         }
6043
6044         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6045                 chip_version, nports);
6046         return 0;
6047 }
6048
6049 /**
6050  *      t4_get_port_type_description - return Port Type string description
6051  *      @port_type: firmware Port Type enumeration
6052  */
6053 const char *t4_get_port_type_description(enum fw_port_type port_type)
6054 {
6055         static const char *const port_type_description[] = {
6056                 "Fiber_XFI",
6057                 "Fiber_XAUI",
6058                 "BT_SGMII",
6059                 "BT_XFI",
6060                 "BT_XAUI",
6061                 "KX4",
6062                 "CX4",
6063                 "KX",
6064                 "KR",
6065                 "SFP",
6066                 "BP_AP",
6067                 "BP4_AP",
6068                 "QSFP_10G",
6069                 "QSA",
6070                 "QSFP",
6071                 "BP40_BA",
6072                 "KR4_100G",
6073                 "CR4_QSFP",
6074                 "CR_QSFP",
6075                 "CR2_QSFP",
6076                 "SFP28",
6077                 "KR_SFP28",
6078         };
6079
6080         if (port_type < ARRAY_SIZE(port_type_description))
6081                 return port_type_description[port_type];
6082         return "UNKNOWN";
6083 }
6084
6085 /**
6086  *      t4_get_port_stats_offset - collect port stats relative to a previous
6087  *                                 snapshot
6088  *      @adap: The adapter
6089  *      @idx: The port
6090  *      @stats: Current stats to fill
6091  *      @offset: Previous stats snapshot
6092  */
6093 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6094                               struct port_stats *stats,
6095                               struct port_stats *offset)
6096 {
6097         u64 *s, *o;
6098         int i;
6099
6100         t4_get_port_stats(adap, idx, stats);
6101         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6102                         i < (sizeof(struct port_stats) / sizeof(u64));
6103                         i++, s++, o++)
6104                 *s -= *o;
6105 }
6106
6107 /**
6108  *      t4_get_port_stats - collect port statistics
6109  *      @adap: the adapter
6110  *      @idx: the port index
6111  *      @p: the stats structure to fill
6112  *
6113  *      Collect statistics related to the given port from HW.
6114  */
6115 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6116 {
6117         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6118         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6119
6120 #define GET_STAT(name) \
6121         t4_read_reg64(adap, \
6122         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6123         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6124 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6125
6126         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
6127         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
6128         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
6129         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
6130         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
6131         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
6132         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
6133         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
6134         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
6135         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
6136         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
6137         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6138         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
6139         p->tx_drop             = GET_STAT(TX_PORT_DROP);
6140         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
6141         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
6142         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
6143         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
6144         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
6145         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
6146         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
6147         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
6148         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
6149
6150         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6151                 if (stat_ctl & COUNTPAUSESTATTX_F)
6152                         p->tx_frames_64 -= p->tx_pause;
6153                 if (stat_ctl & COUNTPAUSEMCTX_F)
6154                         p->tx_mcast_frames -= p->tx_pause;
6155         }
6156         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6157         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6158         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6159         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6160         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6161         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6162         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6163         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6164         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6165         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6166         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6167         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6168         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6169         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6170         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6171         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6172         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6173         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6174         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6175         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6176         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6177         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6178         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6179         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6180         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6181         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6182         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6183
6184         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6185                 if (stat_ctl & COUNTPAUSESTATRX_F)
6186                         p->rx_frames_64 -= p->rx_pause;
6187                 if (stat_ctl & COUNTPAUSEMCRX_F)
6188                         p->rx_mcast_frames -= p->rx_pause;
6189         }
6190
6191         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6192         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6193         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6194         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6195         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6196         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6197         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6198         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6199
6200 #undef GET_STAT
6201 #undef GET_STAT_COM
6202 }
6203
6204 /**
6205  *      t4_get_lb_stats - collect loopback port statistics
6206  *      @adap: the adapter
6207  *      @idx: the loopback port index
6208  *      @p: the stats structure to fill
6209  *
6210  *      Return HW statistics for the given loopback port.
6211  */
6212 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6213 {
6214         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6215
6216 #define GET_STAT(name) \
6217         t4_read_reg64(adap, \
6218         (is_t4(adap->params.chip) ? \
6219         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6220         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6221 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6222
6223         p->octets           = GET_STAT(BYTES);
6224         p->frames           = GET_STAT(FRAMES);
6225         p->bcast_frames     = GET_STAT(BCAST);
6226         p->mcast_frames     = GET_STAT(MCAST);
6227         p->ucast_frames     = GET_STAT(UCAST);
6228         p->error_frames     = GET_STAT(ERROR);
6229
6230         p->frames_64        = GET_STAT(64B);
6231         p->frames_65_127    = GET_STAT(65B_127B);
6232         p->frames_128_255   = GET_STAT(128B_255B);
6233         p->frames_256_511   = GET_STAT(256B_511B);
6234         p->frames_512_1023  = GET_STAT(512B_1023B);
6235         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6236         p->frames_1519_max  = GET_STAT(1519B_MAX);
6237         p->drop             = GET_STAT(DROP_FRAMES);
6238
6239         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6240         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6241         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6242         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6243         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6244         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6245         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6246         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6247
6248 #undef GET_STAT
6249 #undef GET_STAT_COM
6250 }
6251
6252 /*     t4_mk_filtdelwr - create a delete filter WR
6253  *     @ftid: the filter ID
6254  *     @wr: the filter work request to populate
6255  *     @qid: ingress queue to receive the delete notification
6256  *
6257  *     Creates a filter work request to delete the supplied filter.  If @qid is
6258  *     negative the delete notification is suppressed.
6259  */
6260 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6261 {
6262         memset(wr, 0, sizeof(*wr));
6263         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6264         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6265         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6266                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6267         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6268         if (qid >= 0)
6269                 wr->rx_chan_rx_rpl_iq =
6270                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6271 }
6272
6273 #define INIT_CMD(var, cmd, rd_wr) do { \
6274         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6275                                         FW_CMD_REQUEST_F | \
6276                                         FW_CMD_##rd_wr##_F); \
6277         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6278 } while (0)
6279
6280 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6281                           u32 addr, u32 val)
6282 {
6283         u32 ldst_addrspace;
6284         struct fw_ldst_cmd c;
6285
6286         memset(&c, 0, sizeof(c));
6287         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6288         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6289                                         FW_CMD_REQUEST_F |
6290                                         FW_CMD_WRITE_F |
6291                                         ldst_addrspace);
6292         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6293         c.u.addrval.addr = cpu_to_be32(addr);
6294         c.u.addrval.val = cpu_to_be32(val);
6295
6296         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6297 }
6298
6299 /**
6300  *      t4_mdio_rd - read a PHY register through MDIO
6301  *      @adap: the adapter
6302  *      @mbox: mailbox to use for the FW command
6303  *      @phy_addr: the PHY address
6304  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6305  *      @reg: the register to read
6306  *      @valp: where to store the value
6307  *
6308  *      Issues a FW command through the given mailbox to read a PHY register.
6309  */
6310 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6311                unsigned int mmd, unsigned int reg, u16 *valp)
6312 {
6313         int ret;
6314         u32 ldst_addrspace;
6315         struct fw_ldst_cmd c;
6316
6317         memset(&c, 0, sizeof(c));
6318         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6319         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6320                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6321                                         ldst_addrspace);
6322         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6323         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6324                                          FW_LDST_CMD_MMD_V(mmd));
6325         c.u.mdio.raddr = cpu_to_be16(reg);
6326
6327         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6328         if (ret == 0)
6329                 *valp = be16_to_cpu(c.u.mdio.rval);
6330         return ret;
6331 }
6332
6333 /**
6334  *      t4_mdio_wr - write a PHY register through MDIO
6335  *      @adap: the adapter
6336  *      @mbox: mailbox to use for the FW command
6337  *      @phy_addr: the PHY address
6338  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6339  *      @reg: the register to write
6340  *      @valp: value to write
6341  *
6342  *      Issues a FW command through the given mailbox to write a PHY register.
6343  */
6344 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6345                unsigned int mmd, unsigned int reg, u16 val)
6346 {
6347         u32 ldst_addrspace;
6348         struct fw_ldst_cmd c;
6349
6350         memset(&c, 0, sizeof(c));
6351         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6352         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6353                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6354                                         ldst_addrspace);
6355         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6356         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6357                                          FW_LDST_CMD_MMD_V(mmd));
6358         c.u.mdio.raddr = cpu_to_be16(reg);
6359         c.u.mdio.rval = cpu_to_be16(val);
6360
6361         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6362 }
6363
6364 /**
6365  *      t4_sge_decode_idma_state - decode the idma state
6366  *      @adap: the adapter
6367  *      @state: the state idma is stuck in
6368  */
6369 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6370 {
6371         static const char * const t4_decode[] = {
6372                 "IDMA_IDLE",
6373                 "IDMA_PUSH_MORE_CPL_FIFO",
6374                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6375                 "Not used",
6376                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6377                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6378                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6379                 "IDMA_SEND_FIFO_TO_IMSG",
6380                 "IDMA_FL_REQ_DATA_FL_PREP",
6381                 "IDMA_FL_REQ_DATA_FL",
6382                 "IDMA_FL_DROP",
6383                 "IDMA_FL_H_REQ_HEADER_FL",
6384                 "IDMA_FL_H_SEND_PCIEHDR",
6385                 "IDMA_FL_H_PUSH_CPL_FIFO",
6386                 "IDMA_FL_H_SEND_CPL",
6387                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6388                 "IDMA_FL_H_SEND_IP_HDR",
6389                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6390                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6391                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6392                 "IDMA_FL_D_SEND_PCIEHDR",
6393                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6394                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6395                 "IDMA_FL_SEND_PCIEHDR",
6396                 "IDMA_FL_PUSH_CPL_FIFO",
6397                 "IDMA_FL_SEND_CPL",
6398                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6399                 "IDMA_FL_SEND_PAYLOAD",
6400                 "IDMA_FL_REQ_NEXT_DATA_FL",
6401                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6402                 "IDMA_FL_SEND_PADDING",
6403                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6404                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6405                 "IDMA_FL_REQ_DATAFL_DONE",
6406                 "IDMA_FL_REQ_HEADERFL_DONE",
6407         };
6408         static const char * const t5_decode[] = {
6409                 "IDMA_IDLE",
6410                 "IDMA_ALMOST_IDLE",
6411                 "IDMA_PUSH_MORE_CPL_FIFO",
6412                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6413                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6414                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6415                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6416                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6417                 "IDMA_SEND_FIFO_TO_IMSG",
6418                 "IDMA_FL_REQ_DATA_FL",
6419                 "IDMA_FL_DROP",
6420                 "IDMA_FL_DROP_SEND_INC",
6421                 "IDMA_FL_H_REQ_HEADER_FL",
6422                 "IDMA_FL_H_SEND_PCIEHDR",
6423                 "IDMA_FL_H_PUSH_CPL_FIFO",
6424                 "IDMA_FL_H_SEND_CPL",
6425                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6426                 "IDMA_FL_H_SEND_IP_HDR",
6427                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6428                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6429                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6430                 "IDMA_FL_D_SEND_PCIEHDR",
6431                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6432                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6433                 "IDMA_FL_SEND_PCIEHDR",
6434                 "IDMA_FL_PUSH_CPL_FIFO",
6435                 "IDMA_FL_SEND_CPL",
6436                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6437                 "IDMA_FL_SEND_PAYLOAD",
6438                 "IDMA_FL_REQ_NEXT_DATA_FL",
6439                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6440                 "IDMA_FL_SEND_PADDING",
6441                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6442         };
6443         static const char * const t6_decode[] = {
6444                 "IDMA_IDLE",
6445                 "IDMA_PUSH_MORE_CPL_FIFO",
6446                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6447                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6448                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6449                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6450                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6451                 "IDMA_FL_REQ_DATA_FL",
6452                 "IDMA_FL_DROP",
6453                 "IDMA_FL_DROP_SEND_INC",
6454                 "IDMA_FL_H_REQ_HEADER_FL",
6455                 "IDMA_FL_H_SEND_PCIEHDR",
6456                 "IDMA_FL_H_PUSH_CPL_FIFO",
6457                 "IDMA_FL_H_SEND_CPL",
6458                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6459                 "IDMA_FL_H_SEND_IP_HDR",
6460                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6461                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6462                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6463                 "IDMA_FL_D_SEND_PCIEHDR",
6464                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6465                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6466                 "IDMA_FL_SEND_PCIEHDR",
6467                 "IDMA_FL_PUSH_CPL_FIFO",
6468                 "IDMA_FL_SEND_CPL",
6469                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6470                 "IDMA_FL_SEND_PAYLOAD",
6471                 "IDMA_FL_REQ_NEXT_DATA_FL",
6472                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6473                 "IDMA_FL_SEND_PADDING",
6474                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6475         };
6476         static const u32 sge_regs[] = {
6477                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6478                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6479                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6480         };
6481         const char **sge_idma_decode;
6482         int sge_idma_decode_nstates;
6483         int i;
6484         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6485
6486         /* Select the right set of decode strings to dump depending on the
6487          * adapter chip type.
6488          */
6489         switch (chip_version) {
6490         case CHELSIO_T4:
6491                 sge_idma_decode = (const char **)t4_decode;
6492                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6493                 break;
6494
6495         case CHELSIO_T5:
6496                 sge_idma_decode = (const char **)t5_decode;
6497                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6498                 break;
6499
6500         case CHELSIO_T6:
6501                 sge_idma_decode = (const char **)t6_decode;
6502                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6503                 break;
6504
6505         default:
6506                 dev_err(adapter->pdev_dev,
6507                         "Unsupported chip version %d\n", chip_version);
6508                 return;
6509         }
6510
6511         if (is_t4(adapter->params.chip)) {
6512                 sge_idma_decode = (const char **)t4_decode;
6513                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6514         } else {
6515                 sge_idma_decode = (const char **)t5_decode;
6516                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6517         }
6518
6519         if (state < sge_idma_decode_nstates)
6520                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6521         else
6522                 CH_WARN(adapter, "idma state %d unknown\n", state);
6523
6524         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6525                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6526                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6527 }
6528
6529 /**
6530  *      t4_sge_ctxt_flush - flush the SGE context cache
6531  *      @adap: the adapter
6532  *      @mbox: mailbox to use for the FW command
6533  *      @ctx_type: Egress or Ingress
6534  *
6535  *      Issues a FW command through the given mailbox to flush the
6536  *      SGE context cache.
6537  */
6538 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6539 {
6540         int ret;
6541         u32 ldst_addrspace;
6542         struct fw_ldst_cmd c;
6543
6544         memset(&c, 0, sizeof(c));
6545         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6546                                                  FW_LDST_ADDRSPC_SGE_EGRC :
6547                                                  FW_LDST_ADDRSPC_SGE_INGC);
6548         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6549                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6550                                         ldst_addrspace);
6551         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6552         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6553
6554         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6555         return ret;
6556 }
6557
6558 /**
6559  *      t4_fw_hello - establish communication with FW
6560  *      @adap: the adapter
6561  *      @mbox: mailbox to use for the FW command
6562  *      @evt_mbox: mailbox to receive async FW events
6563  *      @master: specifies the caller's willingness to be the device master
6564  *      @state: returns the current device state (if non-NULL)
6565  *
6566  *      Issues a command to establish communication with FW.  Returns either
6567  *      an error (negative integer) or the mailbox of the Master PF.
6568  */
6569 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6570                 enum dev_master master, enum dev_state *state)
6571 {
6572         int ret;
6573         struct fw_hello_cmd c;
6574         u32 v;
6575         unsigned int master_mbox;
6576         int retries = FW_CMD_HELLO_RETRIES;
6577
6578 retry:
6579         memset(&c, 0, sizeof(c));
6580         INIT_CMD(c, HELLO, WRITE);
6581         c.err_to_clearinit = cpu_to_be32(
6582                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6583                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6584                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6585                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6586                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6587                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6588                 FW_HELLO_CMD_CLEARINIT_F);
6589
6590         /*
6591          * Issue the HELLO command to the firmware.  If it's not successful
6592          * but indicates that we got a "busy" or "timeout" condition, retry
6593          * the HELLO until we exhaust our retry limit.  If we do exceed our
6594          * retry limit, check to see if the firmware left us any error
6595          * information and report that if so.
6596          */
6597         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6598         if (ret < 0) {
6599                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6600                         goto retry;
6601                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6602                         t4_report_fw_error(adap);
6603                 return ret;
6604         }
6605
6606         v = be32_to_cpu(c.err_to_clearinit);
6607         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6608         if (state) {
6609                 if (v & FW_HELLO_CMD_ERR_F)
6610                         *state = DEV_STATE_ERR;
6611                 else if (v & FW_HELLO_CMD_INIT_F)
6612                         *state = DEV_STATE_INIT;
6613                 else
6614                         *state = DEV_STATE_UNINIT;
6615         }
6616
6617         /*
6618          * If we're not the Master PF then we need to wait around for the
6619          * Master PF Driver to finish setting up the adapter.
6620          *
6621          * Note that we also do this wait if we're a non-Master-capable PF and
6622          * there is no current Master PF; a Master PF may show up momentarily
6623          * and we wouldn't want to fail pointlessly.  (This can happen when an
6624          * OS loads lots of different drivers rapidly at the same time).  In
6625          * this case, the Master PF returned by the firmware will be
6626          * PCIE_FW_MASTER_M so the test below will work ...
6627          */
6628         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6629             master_mbox != mbox) {
6630                 int waiting = FW_CMD_HELLO_TIMEOUT;
6631
6632                 /*
6633                  * Wait for the firmware to either indicate an error or
6634                  * initialized state.  If we see either of these we bail out
6635                  * and report the issue to the caller.  If we exhaust the
6636                  * "hello timeout" and we haven't exhausted our retries, try
6637                  * again.  Otherwise bail with a timeout error.
6638                  */
6639                 for (;;) {
6640                         u32 pcie_fw;
6641
6642                         msleep(50);
6643                         waiting -= 50;
6644
6645                         /*
6646                          * If neither Error nor Initialialized are indicated
6647                          * by the firmware keep waiting till we exaust our
6648                          * timeout ... and then retry if we haven't exhausted
6649                          * our retries ...
6650                          */
6651                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6652                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6653                                 if (waiting <= 0) {
6654                                         if (retries-- > 0)
6655                                                 goto retry;
6656
6657                                         return -ETIMEDOUT;
6658                                 }
6659                                 continue;
6660                         }
6661
6662                         /*
6663                          * We either have an Error or Initialized condition
6664                          * report errors preferentially.
6665                          */
6666                         if (state) {
6667                                 if (pcie_fw & PCIE_FW_ERR_F)
6668                                         *state = DEV_STATE_ERR;
6669                                 else if (pcie_fw & PCIE_FW_INIT_F)
6670                                         *state = DEV_STATE_INIT;
6671                         }
6672
6673                         /*
6674                          * If we arrived before a Master PF was selected and
6675                          * there's not a valid Master PF, grab its identity
6676                          * for our caller.
6677                          */
6678                         if (master_mbox == PCIE_FW_MASTER_M &&
6679                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6680                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6681                         break;
6682                 }
6683         }
6684
6685         return master_mbox;
6686 }
6687
6688 /**
6689  *      t4_fw_bye - end communication with FW
6690  *      @adap: the adapter
6691  *      @mbox: mailbox to use for the FW command
6692  *
6693  *      Issues a command to terminate communication with FW.
6694  */
6695 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6696 {
6697         struct fw_bye_cmd c;
6698
6699         memset(&c, 0, sizeof(c));
6700         INIT_CMD(c, BYE, WRITE);
6701         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6702 }
6703
6704 /**
6705  *      t4_init_cmd - ask FW to initialize the device
6706  *      @adap: the adapter
6707  *      @mbox: mailbox to use for the FW command
6708  *
6709  *      Issues a command to FW to partially initialize the device.  This
6710  *      performs initialization that generally doesn't depend on user input.
6711  */
6712 int t4_early_init(struct adapter *adap, unsigned int mbox)
6713 {
6714         struct fw_initialize_cmd c;
6715
6716         memset(&c, 0, sizeof(c));
6717         INIT_CMD(c, INITIALIZE, WRITE);
6718         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6719 }
6720
6721 /**
6722  *      t4_fw_reset - issue a reset to FW
6723  *      @adap: the adapter
6724  *      @mbox: mailbox to use for the FW command
6725  *      @reset: specifies the type of reset to perform
6726  *
6727  *      Issues a reset command of the specified type to FW.
6728  */
6729 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6730 {
6731         struct fw_reset_cmd c;
6732
6733         memset(&c, 0, sizeof(c));
6734         INIT_CMD(c, RESET, WRITE);
6735         c.val = cpu_to_be32(reset);
6736         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6737 }
6738
6739 /**
6740  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6741  *      @adap: the adapter
6742  *      @mbox: mailbox to use for the FW RESET command (if desired)
6743  *      @force: force uP into RESET even if FW RESET command fails
6744  *
6745  *      Issues a RESET command to firmware (if desired) with a HALT indication
6746  *      and then puts the microprocessor into RESET state.  The RESET command
6747  *      will only be issued if a legitimate mailbox is provided (mbox <=
6748  *      PCIE_FW_MASTER_M).
6749  *
6750  *      This is generally used in order for the host to safely manipulate the
6751  *      adapter without fear of conflicting with whatever the firmware might
6752  *      be doing.  The only way out of this state is to RESTART the firmware
6753  *      ...
6754  */
6755 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6756 {
6757         int ret = 0;
6758
6759         /*
6760          * If a legitimate mailbox is provided, issue a RESET command
6761          * with a HALT indication.
6762          */
6763         if (mbox <= PCIE_FW_MASTER_M) {
6764                 struct fw_reset_cmd c;
6765
6766                 memset(&c, 0, sizeof(c));
6767                 INIT_CMD(c, RESET, WRITE);
6768                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6769                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6770                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6771         }
6772
6773         /*
6774          * Normally we won't complete the operation if the firmware RESET
6775          * command fails but if our caller insists we'll go ahead and put the
6776          * uP into RESET.  This can be useful if the firmware is hung or even
6777          * missing ...  We'll have to take the risk of putting the uP into
6778          * RESET without the cooperation of firmware in that case.
6779          *
6780          * We also force the firmware's HALT flag to be on in case we bypassed
6781          * the firmware RESET command above or we're dealing with old firmware
6782          * which doesn't have the HALT capability.  This will serve as a flag
6783          * for the incoming firmware to know that it's coming out of a HALT
6784          * rather than a RESET ... if it's new enough to understand that ...
6785          */
6786         if (ret == 0 || force) {
6787                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6788                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6789                                  PCIE_FW_HALT_F);
6790         }
6791
6792         /*
6793          * And we always return the result of the firmware RESET command
6794          * even when we force the uP into RESET ...
6795          */
6796         return ret;
6797 }
6798
6799 /**
6800  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6801  *      @adap: the adapter
6802  *      @reset: if we want to do a RESET to restart things
6803  *
6804  *      Restart firmware previously halted by t4_fw_halt().  On successful
6805  *      return the previous PF Master remains as the new PF Master and there
6806  *      is no need to issue a new HELLO command, etc.
6807  *
6808  *      We do this in two ways:
6809  *
6810  *       1. If we're dealing with newer firmware we'll simply want to take
6811  *          the chip's microprocessor out of RESET.  This will cause the
6812  *          firmware to start up from its start vector.  And then we'll loop
6813  *          until the firmware indicates it's started again (PCIE_FW.HALT
6814  *          reset to 0) or we timeout.
6815  *
6816  *       2. If we're dealing with older firmware then we'll need to RESET
6817  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6818  *          flag and automatically RESET itself on startup.
6819  */
6820 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6821 {
6822         if (reset) {
6823                 /*
6824                  * Since we're directing the RESET instead of the firmware
6825                  * doing it automatically, we need to clear the PCIE_FW.HALT
6826                  * bit.
6827                  */
6828                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6829
6830                 /*
6831                  * If we've been given a valid mailbox, first try to get the
6832                  * firmware to do the RESET.  If that works, great and we can
6833                  * return success.  Otherwise, if we haven't been given a
6834                  * valid mailbox or the RESET command failed, fall back to
6835                  * hitting the chip with a hammer.
6836                  */
6837                 if (mbox <= PCIE_FW_MASTER_M) {
6838                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6839                         msleep(100);
6840                         if (t4_fw_reset(adap, mbox,
6841                                         PIORST_F | PIORSTMODE_F) == 0)
6842                                 return 0;
6843                 }
6844
6845                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6846                 msleep(2000);
6847         } else {
6848                 int ms;
6849
6850                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6851                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6852                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6853                                 return 0;
6854                         msleep(100);
6855                         ms += 100;
6856                 }
6857                 return -ETIMEDOUT;
6858         }
6859         return 0;
6860 }
6861
6862 /**
6863  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6864  *      @adap: the adapter
6865  *      @mbox: mailbox to use for the FW RESET command (if desired)
6866  *      @fw_data: the firmware image to write
6867  *      @size: image size
6868  *      @force: force upgrade even if firmware doesn't cooperate
6869  *
6870  *      Perform all of the steps necessary for upgrading an adapter's
6871  *      firmware image.  Normally this requires the cooperation of the
6872  *      existing firmware in order to halt all existing activities
6873  *      but if an invalid mailbox token is passed in we skip that step
6874  *      (though we'll still put the adapter microprocessor into RESET in
6875  *      that case).
6876  *
6877  *      On successful return the new firmware will have been loaded and
6878  *      the adapter will have been fully RESET losing all previous setup
6879  *      state.  On unsuccessful return the adapter may be completely hosed ...
6880  *      positive errno indicates that the adapter is ~probably~ intact, a
6881  *      negative errno indicates that things are looking bad ...
6882  */
6883 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6884                   const u8 *fw_data, unsigned int size, int force)
6885 {
6886         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6887         int reset, ret;
6888
6889         if (!t4_fw_matches_chip(adap, fw_hdr))
6890                 return -EINVAL;
6891
6892         /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6893          * wont be sent when we are flashing FW.
6894          */
6895         adap->flags &= ~FW_OK;
6896
6897         ret = t4_fw_halt(adap, mbox, force);
6898         if (ret < 0 && !force)
6899                 goto out;
6900
6901         ret = t4_load_fw(adap, fw_data, size);
6902         if (ret < 0)
6903                 goto out;
6904
6905         /*
6906          * If there was a Firmware Configuration File stored in FLASH,
6907          * there's a good chance that it won't be compatible with the new
6908          * Firmware.  In order to prevent difficult to diagnose adapter
6909          * initialization issues, we clear out the Firmware Configuration File
6910          * portion of the FLASH .  The user will need to re-FLASH a new
6911          * Firmware Configuration File which is compatible with the new
6912          * Firmware if that's desired.
6913          */
6914         (void)t4_load_cfg(adap, NULL, 0);
6915
6916         /*
6917          * Older versions of the firmware don't understand the new
6918          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6919          * restart.  So for newly loaded older firmware we'll have to do the
6920          * RESET for it so it starts up on a clean slate.  We can tell if
6921          * the newly loaded firmware will handle this right by checking
6922          * its header flags to see if it advertises the capability.
6923          */
6924         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6925         ret = t4_fw_restart(adap, mbox, reset);
6926
6927         /* Grab potentially new Firmware Device Log parameters so we can see
6928          * how healthy the new Firmware is.  It's okay to contact the new
6929          * Firmware for these parameters even though, as far as it's
6930          * concerned, we've never said "HELLO" to it ...
6931          */
6932         (void)t4_init_devlog_params(adap);
6933 out:
6934         adap->flags |= FW_OK;
6935         return ret;
6936 }
6937
6938 /**
6939  *      t4_fl_pkt_align - return the fl packet alignment
6940  *      @adap: the adapter
6941  *
6942  *      T4 has a single field to specify the packing and padding boundary.
6943  *      T5 onwards has separate fields for this and hence the alignment for
6944  *      next packet offset is maximum of these two.
6945  *
6946  */
6947 int t4_fl_pkt_align(struct adapter *adap)
6948 {
6949         u32 sge_control, sge_control2;
6950         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6951
6952         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6953
6954         /* T4 uses a single control field to specify both the PCIe Padding and
6955          * Packing Boundary.  T5 introduced the ability to specify these
6956          * separately.  The actual Ingress Packet Data alignment boundary
6957          * within Packed Buffer Mode is the maximum of these two
6958          * specifications.  (Note that it makes no real practical sense to
6959          * have the Pading Boudary be larger than the Packing Boundary but you
6960          * could set the chip up that way and, in fact, legacy T4 code would
6961          * end doing this because it would initialize the Padding Boundary and
6962          * leave the Packing Boundary initialized to 0 (16 bytes).)
6963          * Padding Boundary values in T6 starts from 8B,
6964          * where as it is 32B for T4 and T5.
6965          */
6966         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6967                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6968         else
6969                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6970
6971         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6972
6973         fl_align = ingpadboundary;
6974         if (!is_t4(adap->params.chip)) {
6975                 /* T5 has a weird interpretation of one of the PCIe Packing
6976                  * Boundary values.  No idea why ...
6977                  */
6978                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6979                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6980                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6981                         ingpackboundary = 16;
6982                 else
6983                         ingpackboundary = 1 << (ingpackboundary +
6984                                                 INGPACKBOUNDARY_SHIFT_X);
6985
6986                 fl_align = max(ingpadboundary, ingpackboundary);
6987         }
6988         return fl_align;
6989 }
6990
6991 /**
6992  *      t4_fixup_host_params - fix up host-dependent parameters
6993  *      @adap: the adapter
6994  *      @page_size: the host's Base Page Size
6995  *      @cache_line_size: the host's Cache Line Size
6996  *
6997  *      Various registers in T4 contain values which are dependent on the
6998  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6999  *      those registers with the appropriate values as passed in ...
7000  */
7001 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7002                          unsigned int cache_line_size)
7003 {
7004         unsigned int page_shift = fls(page_size) - 1;
7005         unsigned int sge_hps = page_shift - 10;
7006         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7007         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7008         unsigned int fl_align_log = fls(fl_align) - 1;
7009
7010         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7011                      HOSTPAGESIZEPF0_V(sge_hps) |
7012                      HOSTPAGESIZEPF1_V(sge_hps) |
7013                      HOSTPAGESIZEPF2_V(sge_hps) |
7014                      HOSTPAGESIZEPF3_V(sge_hps) |
7015                      HOSTPAGESIZEPF4_V(sge_hps) |
7016                      HOSTPAGESIZEPF5_V(sge_hps) |
7017                      HOSTPAGESIZEPF6_V(sge_hps) |
7018                      HOSTPAGESIZEPF7_V(sge_hps));
7019
7020         if (is_t4(adap->params.chip)) {
7021                 t4_set_reg_field(adap, SGE_CONTROL_A,
7022                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7023                                  EGRSTATUSPAGESIZE_F,
7024                                  INGPADBOUNDARY_V(fl_align_log -
7025                                                   INGPADBOUNDARY_SHIFT_X) |
7026                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7027         } else {
7028                 unsigned int pack_align;
7029                 unsigned int ingpad, ingpack;
7030                 unsigned int pcie_cap;
7031
7032                 /* T5 introduced the separation of the Free List Padding and
7033                  * Packing Boundaries.  Thus, we can select a smaller Padding
7034                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
7035                  * Bandwidth, and use a Packing Boundary which is large enough
7036                  * to avoid false sharing between CPUs, etc.
7037                  *
7038                  * For the PCI Link, the smaller the Padding Boundary the
7039                  * better.  For the Memory Controller, a smaller Padding
7040                  * Boundary is better until we cross under the Memory Line
7041                  * Size (the minimum unit of transfer to/from Memory).  If we
7042                  * have a Padding Boundary which is smaller than the Memory
7043                  * Line Size, that'll involve a Read-Modify-Write cycle on the
7044                  * Memory Controller which is never good.
7045                  */
7046
7047                 /* We want the Packing Boundary to be based on the Cache Line
7048                  * Size in order to help avoid False Sharing performance
7049                  * issues between CPUs, etc.  We also want the Packing
7050                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
7051                  * get best performance when the Packing Boundary is a
7052                  * multiple of the Maximum Payload Size.
7053                  */
7054                 pack_align = fl_align;
7055                 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
7056                 if (pcie_cap) {
7057                         unsigned int mps, mps_log;
7058                         u16 devctl;
7059
7060                         /* The PCIe Device Control Maximum Payload Size field
7061                          * [bits 7:5] encodes sizes as powers of 2 starting at
7062                          * 128 bytes.
7063                          */
7064                         pci_read_config_word(adap->pdev,
7065                                              pcie_cap + PCI_EXP_DEVCTL,
7066                                              &devctl);
7067                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7068                         mps = 1 << mps_log;
7069                         if (mps > pack_align)
7070                                 pack_align = mps;
7071                 }
7072
7073                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7074                  * value for the Packing Boundary.  This corresponds to 16
7075                  * bytes instead of the expected 32 bytes.  So if we want 32
7076                  * bytes, the best we can really do is 64 bytes ...
7077                  */
7078                 if (pack_align <= 16) {
7079                         ingpack = INGPACKBOUNDARY_16B_X;
7080                         fl_align = 16;
7081                 } else if (pack_align == 32) {
7082                         ingpack = INGPACKBOUNDARY_64B_X;
7083                         fl_align = 64;
7084                 } else {
7085                         unsigned int pack_align_log = fls(pack_align) - 1;
7086
7087                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7088                         fl_align = pack_align;
7089                 }
7090
7091                 /* Use the smallest Ingress Padding which isn't smaller than
7092                  * the Memory Controller Read/Write Size.  We'll take that as
7093                  * being 8 bytes since we don't know of any system with a
7094                  * wider Memory Controller Bus Width.
7095                  */
7096                 if (is_t5(adap->params.chip))
7097                         ingpad = INGPADBOUNDARY_32B_X;
7098                 else
7099                         ingpad = T6_INGPADBOUNDARY_8B_X;
7100
7101                 t4_set_reg_field(adap, SGE_CONTROL_A,
7102                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7103                                  EGRSTATUSPAGESIZE_F,
7104                                  INGPADBOUNDARY_V(ingpad) |
7105                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7106                 t4_set_reg_field(adap, SGE_CONTROL2_A,
7107                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7108                                  INGPACKBOUNDARY_V(ingpack));
7109         }
7110         /*
7111          * Adjust various SGE Free List Host Buffer Sizes.
7112          *
7113          * This is something of a crock since we're using fixed indices into
7114          * the array which are also known by the sge.c code and the T4
7115          * Firmware Configuration File.  We need to come up with a much better
7116          * approach to managing this array.  For now, the first four entries
7117          * are:
7118          *
7119          *   0: Host Page Size
7120          *   1: 64KB
7121          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7122          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7123          *
7124          * For the single-MTU buffers in unpacked mode we need to include
7125          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7126          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7127          * Padding boundary.  All of these are accommodated in the Factory
7128          * Default Firmware Configuration File but we need to adjust it for
7129          * this host's cache line size.
7130          */
7131         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7132         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7133                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7134                      & ~(fl_align-1));
7135         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7136                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7137                      & ~(fl_align-1));
7138
7139         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7140
7141         return 0;
7142 }
7143
7144 /**
7145  *      t4_fw_initialize - ask FW to initialize the device
7146  *      @adap: the adapter
7147  *      @mbox: mailbox to use for the FW command
7148  *
7149  *      Issues a command to FW to partially initialize the device.  This
7150  *      performs initialization that generally doesn't depend on user input.
7151  */
7152 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7153 {
7154         struct fw_initialize_cmd c;
7155
7156         memset(&c, 0, sizeof(c));
7157         INIT_CMD(c, INITIALIZE, WRITE);
7158         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7159 }
7160
7161 /**
7162  *      t4_query_params_rw - query FW or device parameters
7163  *      @adap: the adapter
7164  *      @mbox: mailbox to use for the FW command
7165  *      @pf: the PF
7166  *      @vf: the VF
7167  *      @nparams: the number of parameters
7168  *      @params: the parameter names
7169  *      @val: the parameter values
7170  *      @rw: Write and read flag
7171  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7172  *
7173  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7174  *      queried at once.
7175  */
7176 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7177                        unsigned int vf, unsigned int nparams, const u32 *params,
7178                        u32 *val, int rw, bool sleep_ok)
7179 {
7180         int i, ret;
7181         struct fw_params_cmd c;
7182         __be32 *p = &c.param[0].mnem;
7183
7184         if (nparams > 7)
7185                 return -EINVAL;
7186
7187         memset(&c, 0, sizeof(c));
7188         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7189                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7190                                   FW_PARAMS_CMD_PFN_V(pf) |
7191                                   FW_PARAMS_CMD_VFN_V(vf));
7192         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7193
7194         for (i = 0; i < nparams; i++) {
7195                 *p++ = cpu_to_be32(*params++);
7196                 if (rw)
7197                         *p = cpu_to_be32(*(val + i));
7198                 p++;
7199         }
7200
7201         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7202         if (ret == 0)
7203                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7204                         *val++ = be32_to_cpu(*p);
7205         return ret;
7206 }
7207
7208 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7209                     unsigned int vf, unsigned int nparams, const u32 *params,
7210                     u32 *val)
7211 {
7212         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7213                                   true);
7214 }
7215
7216 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7217                        unsigned int vf, unsigned int nparams, const u32 *params,
7218                        u32 *val)
7219 {
7220         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7221                                   false);
7222 }
7223
7224 /**
7225  *      t4_set_params_timeout - sets FW or device parameters
7226  *      @adap: the adapter
7227  *      @mbox: mailbox to use for the FW command
7228  *      @pf: the PF
7229  *      @vf: the VF
7230  *      @nparams: the number of parameters
7231  *      @params: the parameter names
7232  *      @val: the parameter values
7233  *      @timeout: the timeout time
7234  *
7235  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7236  *      specified at once.
7237  */
7238 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7239                           unsigned int pf, unsigned int vf,
7240                           unsigned int nparams, const u32 *params,
7241                           const u32 *val, int timeout)
7242 {
7243         struct fw_params_cmd c;
7244         __be32 *p = &c.param[0].mnem;
7245
7246         if (nparams > 7)
7247                 return -EINVAL;
7248
7249         memset(&c, 0, sizeof(c));
7250         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7251                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7252                                   FW_PARAMS_CMD_PFN_V(pf) |
7253                                   FW_PARAMS_CMD_VFN_V(vf));
7254         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7255
7256         while (nparams--) {
7257                 *p++ = cpu_to_be32(*params++);
7258                 *p++ = cpu_to_be32(*val++);
7259         }
7260
7261         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7262 }
7263
7264 /**
7265  *      t4_set_params - sets FW or device parameters
7266  *      @adap: the adapter
7267  *      @mbox: mailbox to use for the FW command
7268  *      @pf: the PF
7269  *      @vf: the VF
7270  *      @nparams: the number of parameters
7271  *      @params: the parameter names
7272  *      @val: the parameter values
7273  *
7274  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7275  *      specified at once.
7276  */
7277 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7278                   unsigned int vf, unsigned int nparams, const u32 *params,
7279                   const u32 *val)
7280 {
7281         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7282                                      FW_CMD_MAX_TIMEOUT);
7283 }
7284
7285 /**
7286  *      t4_cfg_pfvf - configure PF/VF resource limits
7287  *      @adap: the adapter
7288  *      @mbox: mailbox to use for the FW command
7289  *      @pf: the PF being configured
7290  *      @vf: the VF being configured
7291  *      @txq: the max number of egress queues
7292  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7293  *      @rxqi: the max number of interrupt-capable ingress queues
7294  *      @rxq: the max number of interruptless ingress queues
7295  *      @tc: the PCI traffic class
7296  *      @vi: the max number of virtual interfaces
7297  *      @cmask: the channel access rights mask for the PF/VF
7298  *      @pmask: the port access rights mask for the PF/VF
7299  *      @nexact: the maximum number of exact MPS filters
7300  *      @rcaps: read capabilities
7301  *      @wxcaps: write/execute capabilities
7302  *
7303  *      Configures resource limits and capabilities for a physical or virtual
7304  *      function.
7305  */
7306 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7307                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7308                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7309                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7310                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7311 {
7312         struct fw_pfvf_cmd c;
7313
7314         memset(&c, 0, sizeof(c));
7315         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7316                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7317                                   FW_PFVF_CMD_VFN_V(vf));
7318         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7319         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7320                                      FW_PFVF_CMD_NIQ_V(rxq));
7321         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7322                                     FW_PFVF_CMD_PMASK_V(pmask) |
7323                                     FW_PFVF_CMD_NEQ_V(txq));
7324         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7325                                       FW_PFVF_CMD_NVI_V(vi) |
7326                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7327         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7328                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7329                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7330         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7331 }
7332
7333 /**
7334  *      t4_alloc_vi - allocate a virtual interface
7335  *      @adap: the adapter
7336  *      @mbox: mailbox to use for the FW command
7337  *      @port: physical port associated with the VI
7338  *      @pf: the PF owning the VI
7339  *      @vf: the VF owning the VI
7340  *      @nmac: number of MAC addresses needed (1 to 5)
7341  *      @mac: the MAC addresses of the VI
7342  *      @rss_size: size of RSS table slice associated with this VI
7343  *
7344  *      Allocates a virtual interface for the given physical port.  If @mac is
7345  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7346  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7347  *      stored consecutively so the space needed is @nmac * 6 bytes.
7348  *      Returns a negative error number or the non-negative VI id.
7349  */
7350 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7351                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7352                 unsigned int *rss_size)
7353 {
7354         int ret;
7355         struct fw_vi_cmd c;
7356
7357         memset(&c, 0, sizeof(c));
7358         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7359                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7360                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7361         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7362         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7363         c.nmac = nmac - 1;
7364
7365         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7366         if (ret)
7367                 return ret;
7368
7369         if (mac) {
7370                 memcpy(mac, c.mac, sizeof(c.mac));
7371                 switch (nmac) {
7372                 case 5:
7373                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7374                 case 4:
7375                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7376                 case 3:
7377                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7378                 case 2:
7379                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7380                 }
7381         }
7382         if (rss_size)
7383                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7384         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7385 }
7386
7387 /**
7388  *      t4_free_vi - free a virtual interface
7389  *      @adap: the adapter
7390  *      @mbox: mailbox to use for the FW command
7391  *      @pf: the PF owning the VI
7392  *      @vf: the VF owning the VI
7393  *      @viid: virtual interface identifiler
7394  *
7395  *      Free a previously allocated virtual interface.
7396  */
7397 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7398                unsigned int vf, unsigned int viid)
7399 {
7400         struct fw_vi_cmd c;
7401
7402         memset(&c, 0, sizeof(c));
7403         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7404                                   FW_CMD_REQUEST_F |
7405                                   FW_CMD_EXEC_F |
7406                                   FW_VI_CMD_PFN_V(pf) |
7407                                   FW_VI_CMD_VFN_V(vf));
7408         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7409         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7410
7411         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7412 }
7413
7414 /**
7415  *      t4_set_rxmode - set Rx properties of a virtual interface
7416  *      @adap: the adapter
7417  *      @mbox: mailbox to use for the FW command
7418  *      @viid: the VI id
7419  *      @mtu: the new MTU or -1
7420  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7421  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7422  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7423  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7424  *      @sleep_ok: if true we may sleep while awaiting command completion
7425  *
7426  *      Sets Rx properties of a virtual interface.
7427  */
7428 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7429                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7430                   bool sleep_ok)
7431 {
7432         struct fw_vi_rxmode_cmd c;
7433
7434         /* convert to FW values */
7435         if (mtu < 0)
7436                 mtu = FW_RXMODE_MTU_NO_CHG;
7437         if (promisc < 0)
7438                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7439         if (all_multi < 0)
7440                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7441         if (bcast < 0)
7442                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7443         if (vlanex < 0)
7444                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7445
7446         memset(&c, 0, sizeof(c));
7447         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7448                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7449                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7450         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7451         c.mtu_to_vlanexen =
7452                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7453                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7454                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7455                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7456                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7457         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7458 }
7459
7460 /**
7461  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7462  *      @adap: the adapter
7463  *      @mbox: mailbox to use for the FW command
7464  *      @viid: the VI id
7465  *      @free: if true any existing filters for this VI id are first removed
7466  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7467  *      @addr: the MAC address(es)
7468  *      @idx: where to store the index of each allocated filter
7469  *      @hash: pointer to hash address filter bitmap
7470  *      @sleep_ok: call is allowed to sleep
7471  *
7472  *      Allocates an exact-match filter for each of the supplied addresses and
7473  *      sets it to the corresponding address.  If @idx is not %NULL it should
7474  *      have at least @naddr entries, each of which will be set to the index of
7475  *      the filter allocated for the corresponding MAC address.  If a filter
7476  *      could not be allocated for an address its index is set to 0xffff.
7477  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7478  *      are hashed and update the hash filter bitmap pointed at by @hash.
7479  *
7480  *      Returns a negative error number or the number of filters allocated.
7481  */
7482 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7483                       unsigned int viid, bool free, unsigned int naddr,
7484                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7485 {
7486         int offset, ret = 0;
7487         struct fw_vi_mac_cmd c;
7488         unsigned int nfilters = 0;
7489         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7490         unsigned int rem = naddr;
7491
7492         if (naddr > max_naddr)
7493                 return -EINVAL;
7494
7495         for (offset = 0; offset < naddr ; /**/) {
7496                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7497                                          rem : ARRAY_SIZE(c.u.exact));
7498                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7499                                                      u.exact[fw_naddr]), 16);
7500                 struct fw_vi_mac_exact *p;
7501                 int i;
7502
7503                 memset(&c, 0, sizeof(c));
7504                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7505                                            FW_CMD_REQUEST_F |
7506                                            FW_CMD_WRITE_F |
7507                                            FW_CMD_EXEC_V(free) |
7508                                            FW_VI_MAC_CMD_VIID_V(viid));
7509                 c.freemacs_to_len16 =
7510                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7511                                     FW_CMD_LEN16_V(len16));
7512
7513                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7514                         p->valid_to_idx =
7515                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7516                                             FW_VI_MAC_CMD_IDX_V(
7517                                                     FW_VI_MAC_ADD_MAC));
7518                         memcpy(p->macaddr, addr[offset + i],
7519                                sizeof(p->macaddr));
7520                 }
7521
7522                 /* It's okay if we run out of space in our MAC address arena.
7523                  * Some of the addresses we submit may get stored so we need
7524                  * to run through the reply to see what the results were ...
7525                  */
7526                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7527                 if (ret && ret != -FW_ENOMEM)
7528                         break;
7529
7530                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7531                         u16 index = FW_VI_MAC_CMD_IDX_G(
7532                                         be16_to_cpu(p->valid_to_idx));
7533
7534                         if (idx)
7535                                 idx[offset + i] = (index >= max_naddr ?
7536                                                    0xffff : index);
7537                         if (index < max_naddr)
7538                                 nfilters++;
7539                         else if (hash)
7540                                 *hash |= (1ULL <<
7541                                           hash_mac_addr(addr[offset + i]));
7542                 }
7543
7544                 free = false;
7545                 offset += fw_naddr;
7546                 rem -= fw_naddr;
7547         }
7548
7549         if (ret == 0 || ret == -FW_ENOMEM)
7550                 ret = nfilters;
7551         return ret;
7552 }
7553
7554 /**
7555  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
7556  *      @adap: the adapter
7557  *      @mbox: mailbox to use for the FW command
7558  *      @viid: the VI id
7559  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7560  *      @addr: the MAC address(es)
7561  *      @sleep_ok: call is allowed to sleep
7562  *
7563  *      Frees the exact-match filter for each of the supplied addresses
7564  *
7565  *      Returns a negative error number or the number of filters freed.
7566  */
7567 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7568                      unsigned int viid, unsigned int naddr,
7569                      const u8 **addr, bool sleep_ok)
7570 {
7571         int offset, ret = 0;
7572         struct fw_vi_mac_cmd c;
7573         unsigned int nfilters = 0;
7574         unsigned int max_naddr = is_t4(adap->params.chip) ?
7575                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
7576                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7577         unsigned int rem = naddr;
7578
7579         if (naddr > max_naddr)
7580                 return -EINVAL;
7581
7582         for (offset = 0; offset < (int)naddr ; /**/) {
7583                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7584                                          ? rem
7585                                          : ARRAY_SIZE(c.u.exact));
7586                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7587                                                      u.exact[fw_naddr]), 16);
7588                 struct fw_vi_mac_exact *p;
7589                 int i;
7590
7591                 memset(&c, 0, sizeof(c));
7592                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7593                                      FW_CMD_REQUEST_F |
7594                                      FW_CMD_WRITE_F |
7595                                      FW_CMD_EXEC_V(0) |
7596                                      FW_VI_MAC_CMD_VIID_V(viid));
7597                 c.freemacs_to_len16 =
7598                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7599                                             FW_CMD_LEN16_V(len16));
7600
7601                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7602                         p->valid_to_idx = cpu_to_be16(
7603                                 FW_VI_MAC_CMD_VALID_F |
7604                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7605                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7606                 }
7607
7608                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7609                 if (ret)
7610                         break;
7611
7612                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7613                         u16 index = FW_VI_MAC_CMD_IDX_G(
7614                                                 be16_to_cpu(p->valid_to_idx));
7615
7616                         if (index < max_naddr)
7617                                 nfilters++;
7618                 }
7619
7620                 offset += fw_naddr;
7621                 rem -= fw_naddr;
7622         }
7623
7624         if (ret == 0)
7625                 ret = nfilters;
7626         return ret;
7627 }
7628
7629 /**
7630  *      t4_change_mac - modifies the exact-match filter for a MAC address
7631  *      @adap: the adapter
7632  *      @mbox: mailbox to use for the FW command
7633  *      @viid: the VI id
7634  *      @idx: index of existing filter for old value of MAC address, or -1
7635  *      @addr: the new MAC address value
7636  *      @persist: whether a new MAC allocation should be persistent
7637  *      @add_smt: if true also add the address to the HW SMT
7638  *
7639  *      Modifies an exact-match filter and sets it to the new MAC address.
7640  *      Note that in general it is not possible to modify the value of a given
7641  *      filter so the generic way to modify an address filter is to free the one
7642  *      being used by the old address value and allocate a new filter for the
7643  *      new address value.  @idx can be -1 if the address is a new addition.
7644  *
7645  *      Returns a negative error number or the index of the filter with the new
7646  *      MAC value.
7647  */
7648 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7649                   int idx, const u8 *addr, bool persist, bool add_smt)
7650 {
7651         int ret, mode;
7652         struct fw_vi_mac_cmd c;
7653         struct fw_vi_mac_exact *p = c.u.exact;
7654         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7655
7656         if (idx < 0)                             /* new allocation */
7657                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7658         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7659
7660         memset(&c, 0, sizeof(c));
7661         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7662                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7663                                    FW_VI_MAC_CMD_VIID_V(viid));
7664         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7665         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7666                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7667                                       FW_VI_MAC_CMD_IDX_V(idx));
7668         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7669
7670         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7671         if (ret == 0) {
7672                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7673                 if (ret >= max_mac_addr)
7674                         ret = -ENOMEM;
7675         }
7676         return ret;
7677 }
7678
7679 /**
7680  *      t4_set_addr_hash - program the MAC inexact-match hash filter
7681  *      @adap: the adapter
7682  *      @mbox: mailbox to use for the FW command
7683  *      @viid: the VI id
7684  *      @ucast: whether the hash filter should also match unicast addresses
7685  *      @vec: the value to be written to the hash filter
7686  *      @sleep_ok: call is allowed to sleep
7687  *
7688  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
7689  */
7690 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7691                      bool ucast, u64 vec, bool sleep_ok)
7692 {
7693         struct fw_vi_mac_cmd c;
7694
7695         memset(&c, 0, sizeof(c));
7696         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7697                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7698                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7699         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7700                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7701                                           FW_CMD_LEN16_V(1));
7702         c.u.hash.hashvec = cpu_to_be64(vec);
7703         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7704 }
7705
7706 /**
7707  *      t4_enable_vi_params - enable/disable a virtual interface
7708  *      @adap: the adapter
7709  *      @mbox: mailbox to use for the FW command
7710  *      @viid: the VI id
7711  *      @rx_en: 1=enable Rx, 0=disable Rx
7712  *      @tx_en: 1=enable Tx, 0=disable Tx
7713  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7714  *
7715  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7716  *      only makes sense when enabling a Virtual Interface ...
7717  */
7718 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7719                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7720 {
7721         struct fw_vi_enable_cmd c;
7722
7723         memset(&c, 0, sizeof(c));
7724         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7725                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7726                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7727         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7728                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7729                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7730                                      FW_LEN16(c));
7731         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7732 }
7733
7734 /**
7735  *      t4_enable_vi - enable/disable a virtual interface
7736  *      @adap: the adapter
7737  *      @mbox: mailbox to use for the FW command
7738  *      @viid: the VI id
7739  *      @rx_en: 1=enable Rx, 0=disable Rx
7740  *      @tx_en: 1=enable Tx, 0=disable Tx
7741  *
7742  *      Enables/disables a virtual interface.
7743  */
7744 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7745                  bool rx_en, bool tx_en)
7746 {
7747         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7748 }
7749
7750 /**
7751  *      t4_identify_port - identify a VI's port by blinking its LED
7752  *      @adap: the adapter
7753  *      @mbox: mailbox to use for the FW command
7754  *      @viid: the VI id
7755  *      @nblinks: how many times to blink LED at 2.5 Hz
7756  *
7757  *      Identifies a VI's port by blinking its LED.
7758  */
7759 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7760                      unsigned int nblinks)
7761 {
7762         struct fw_vi_enable_cmd c;
7763
7764         memset(&c, 0, sizeof(c));
7765         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7766                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7767                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7768         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7769         c.blinkdur = cpu_to_be16(nblinks);
7770         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7771 }
7772
7773 /**
7774  *      t4_iq_stop - stop an ingress queue and its FLs
7775  *      @adap: the adapter
7776  *      @mbox: mailbox to use for the FW command
7777  *      @pf: the PF owning the queues
7778  *      @vf: the VF owning the queues
7779  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7780  *      @iqid: ingress queue id
7781  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7782  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7783  *
7784  *      Stops an ingress queue and its associated FLs, if any.  This causes
7785  *      any current or future data/messages destined for these queues to be
7786  *      tossed.
7787  */
7788 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7789                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7790                unsigned int fl0id, unsigned int fl1id)
7791 {
7792         struct fw_iq_cmd c;
7793
7794         memset(&c, 0, sizeof(c));
7795         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7796                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7797                                   FW_IQ_CMD_VFN_V(vf));
7798         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7799         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7800         c.iqid = cpu_to_be16(iqid);
7801         c.fl0id = cpu_to_be16(fl0id);
7802         c.fl1id = cpu_to_be16(fl1id);
7803         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7804 }
7805
7806 /**
7807  *      t4_iq_free - free an ingress queue and its FLs
7808  *      @adap: the adapter
7809  *      @mbox: mailbox to use for the FW command
7810  *      @pf: the PF owning the queues
7811  *      @vf: the VF owning the queues
7812  *      @iqtype: the ingress queue type
7813  *      @iqid: ingress queue id
7814  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7815  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7816  *
7817  *      Frees an ingress queue and its associated FLs, if any.
7818  */
7819 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7820                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7821                unsigned int fl0id, unsigned int fl1id)
7822 {
7823         struct fw_iq_cmd c;
7824
7825         memset(&c, 0, sizeof(c));
7826         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7827                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7828                                   FW_IQ_CMD_VFN_V(vf));
7829         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7830         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7831         c.iqid = cpu_to_be16(iqid);
7832         c.fl0id = cpu_to_be16(fl0id);
7833         c.fl1id = cpu_to_be16(fl1id);
7834         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7835 }
7836
7837 /**
7838  *      t4_eth_eq_free - free an Ethernet egress queue
7839  *      @adap: the adapter
7840  *      @mbox: mailbox to use for the FW command
7841  *      @pf: the PF owning the queue
7842  *      @vf: the VF owning the queue
7843  *      @eqid: egress queue id
7844  *
7845  *      Frees an Ethernet egress queue.
7846  */
7847 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7848                    unsigned int vf, unsigned int eqid)
7849 {
7850         struct fw_eq_eth_cmd c;
7851
7852         memset(&c, 0, sizeof(c));
7853         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7854                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7855                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7856                                   FW_EQ_ETH_CMD_VFN_V(vf));
7857         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7858         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7859         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7860 }
7861
7862 /**
7863  *      t4_ctrl_eq_free - free a control egress queue
7864  *      @adap: the adapter
7865  *      @mbox: mailbox to use for the FW command
7866  *      @pf: the PF owning the queue
7867  *      @vf: the VF owning the queue
7868  *      @eqid: egress queue id
7869  *
7870  *      Frees a control egress queue.
7871  */
7872 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7873                     unsigned int vf, unsigned int eqid)
7874 {
7875         struct fw_eq_ctrl_cmd c;
7876
7877         memset(&c, 0, sizeof(c));
7878         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7879                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7880                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7881                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7882         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7883         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7884         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7885 }
7886
7887 /**
7888  *      t4_ofld_eq_free - free an offload egress queue
7889  *      @adap: the adapter
7890  *      @mbox: mailbox to use for the FW command
7891  *      @pf: the PF owning the queue
7892  *      @vf: the VF owning the queue
7893  *      @eqid: egress queue id
7894  *
7895  *      Frees a control egress queue.
7896  */
7897 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7898                     unsigned int vf, unsigned int eqid)
7899 {
7900         struct fw_eq_ofld_cmd c;
7901
7902         memset(&c, 0, sizeof(c));
7903         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7904                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7905                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7906                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7907         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7908         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7909         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7910 }
7911
7912 /**
7913  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7914  *      @adap: the adapter
7915  *      @link_down_rc: Link Down Reason Code
7916  *
7917  *      Returns a string representation of the Link Down Reason Code.
7918  */
7919 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7920 {
7921         static const char * const reason[] = {
7922                 "Link Down",
7923                 "Remote Fault",
7924                 "Auto-negotiation Failure",
7925                 "Reserved",
7926                 "Insufficient Airflow",
7927                 "Unable To Determine Reason",
7928                 "No RX Signal Detected",
7929                 "Reserved",
7930         };
7931
7932         if (link_down_rc >= ARRAY_SIZE(reason))
7933                 return "Bad Reason Code";
7934
7935         return reason[link_down_rc];
7936 }
7937
7938 /**
7939  * Return the highest speed set in the port capabilities, in Mb/s.
7940  */
7941 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
7942 {
7943         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
7944                 do { \
7945                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7946                                 return __speed; \
7947                 } while (0)
7948
7949         TEST_SPEED_RETURN(400G, 400000);
7950         TEST_SPEED_RETURN(200G, 200000);
7951         TEST_SPEED_RETURN(100G, 100000);
7952         TEST_SPEED_RETURN(50G,   50000);
7953         TEST_SPEED_RETURN(40G,   40000);
7954         TEST_SPEED_RETURN(25G,   25000);
7955         TEST_SPEED_RETURN(10G,   10000);
7956         TEST_SPEED_RETURN(1G,     1000);
7957         TEST_SPEED_RETURN(100M,    100);
7958
7959         #undef TEST_SPEED_RETURN
7960
7961         return 0;
7962 }
7963
7964 /**
7965  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
7966  *      @acaps: advertised Port Capabilities
7967  *
7968  *      Get the highest speed for the port from the advertised Port
7969  *      Capabilities.  It will be either the highest speed from the list of
7970  *      speeds or whatever user has set using ethtool.
7971  */
7972 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
7973 {
7974         #define TEST_SPEED_RETURN(__caps_speed) \
7975                 do { \
7976                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7977                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
7978                 } while (0)
7979
7980         TEST_SPEED_RETURN(400G);
7981         TEST_SPEED_RETURN(200G);
7982         TEST_SPEED_RETURN(100G);
7983         TEST_SPEED_RETURN(50G);
7984         TEST_SPEED_RETURN(40G);
7985         TEST_SPEED_RETURN(25G);
7986         TEST_SPEED_RETURN(10G);
7987         TEST_SPEED_RETURN(1G);
7988         TEST_SPEED_RETURN(100M);
7989
7990         #undef TEST_SPEED_RETURN
7991
7992         return 0;
7993 }
7994
7995 /**
7996  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
7997  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
7998  *
7999  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8000  *      32-bit Port Capabilities value.
8001  */
8002 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8003 {
8004         fw_port_cap32_t linkattr = 0;
8005
8006         /* Unfortunately the format of the Link Status in the old
8007          * 16-bit Port Information message isn't the same as the
8008          * 16-bit Port Capabilities bitfield used everywhere else ...
8009          */
8010         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8011                 linkattr |= FW_PORT_CAP32_FC_RX;
8012         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8013                 linkattr |= FW_PORT_CAP32_FC_TX;
8014         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8015                 linkattr |= FW_PORT_CAP32_SPEED_100M;
8016         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8017                 linkattr |= FW_PORT_CAP32_SPEED_1G;
8018         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8019                 linkattr |= FW_PORT_CAP32_SPEED_10G;
8020         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8021                 linkattr |= FW_PORT_CAP32_SPEED_25G;
8022         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8023                 linkattr |= FW_PORT_CAP32_SPEED_40G;
8024         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8025                 linkattr |= FW_PORT_CAP32_SPEED_100G;
8026
8027         return linkattr;
8028 }
8029
8030 /**
8031  *      t4_handle_get_port_info - process a FW reply message
8032  *      @pi: the port info
8033  *      @rpl: start of the FW message
8034  *
8035  *      Processes a GET_PORT_INFO FW reply message.
8036  */
8037 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8038 {
8039         const struct fw_port_cmd *cmd = (const void *)rpl;
8040         int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8041         struct adapter *adapter = pi->adapter;
8042         struct link_config *lc = &pi->link_cfg;
8043         int link_ok, linkdnrc;
8044         enum fw_port_type port_type;
8045         enum fw_port_module_type mod_type;
8046         unsigned int speed, fc, fec;
8047         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8048
8049         /* Extract the various fields from the Port Information message.
8050          */
8051         switch (action) {
8052         case FW_PORT_ACTION_GET_PORT_INFO: {
8053                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8054
8055                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8056                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8057                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8058                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8059                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8060                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8061                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8062                 linkattr = lstatus_to_fwcap(lstatus);
8063                 break;
8064         }
8065
8066         case FW_PORT_ACTION_GET_PORT_INFO32: {
8067                 u32 lstatus32;
8068
8069                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8070                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8071                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8072                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8073                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8074                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8075                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8076                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8077                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8078                 break;
8079         }
8080
8081         default:
8082                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8083                         be32_to_cpu(cmd->action_to_len16));
8084                 return;
8085         }
8086
8087         fec = fwcap_to_cc_fec(acaps);
8088         fc = fwcap_to_cc_pause(linkattr);
8089         speed = fwcap_to_speed(linkattr);
8090
8091         if (mod_type != pi->mod_type) {
8092                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8093                  * various fundamental Port Capabilities which used to be
8094                  * immutable can now change radically.  We can now have
8095                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8096                  * all change based on what Transceiver Module is inserted.
8097                  * So we need to record the Physical "Port" Capabilities on
8098                  * every Transceiver Module change.
8099                  */
8100                 lc->pcaps = pcaps;
8101
8102                 /* When a new Transceiver Module is inserted, the Firmware
8103                  * will examine its i2c EPROM to determine its type and
8104                  * general operating parameters including things like Forward
8105                  * Error Control, etc.  Various IEEE 802.3 standards dictate
8106                  * how to interpret these i2c values to determine default
8107                  * "sutomatic" settings.  We record these for future use when
8108                  * the user explicitly requests these standards-based values.
8109                  */
8110                 lc->def_acaps = acaps;
8111
8112                 /* Some versions of the early T6 Firmware "cheated" when
8113                  * handling different Transceiver Modules by changing the
8114                  * underlaying Port Type reported to the Host Drivers.  As
8115                  * such we need to capture whatever Port Type the Firmware
8116                  * sends us and record it in case it's different from what we
8117                  * were told earlier.  Unfortunately, since Firmware is
8118                  * forever, we'll need to keep this code here forever, but in
8119                  * later T6 Firmware it should just be an assignment of the
8120                  * same value already recorded.
8121                  */
8122                 pi->port_type = port_type;
8123
8124                 pi->mod_type = mod_type;
8125                 t4_os_portmod_changed(adapter, pi->port_id);
8126         }
8127
8128         if (link_ok != lc->link_ok || speed != lc->speed ||
8129             fc != lc->fc || fec != lc->fec) {   /* something changed */
8130                 if (!link_ok && lc->link_ok) {
8131                         lc->link_down_rc = linkdnrc;
8132                         dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
8133                                  pi->tx_chan, t4_link_down_rc_str(linkdnrc));
8134                 }
8135                 lc->link_ok = link_ok;
8136                 lc->speed = speed;
8137                 lc->fc = fc;
8138                 lc->fec = fec;
8139
8140                 lc->lpacaps = lpacaps;
8141                 lc->acaps = acaps & ADVERT_MASK;
8142
8143                 if (lc->acaps & FW_PORT_CAP32_ANEG) {
8144                         lc->autoneg = AUTONEG_ENABLE;
8145                 } else {
8146                         /* When Autoneg is disabled, user needs to set
8147                          * single speed.
8148                          * Similar to cxgb4_ethtool.c: set_link_ksettings
8149                          */
8150                         lc->acaps = 0;
8151                         lc->speed_caps = fwcap_to_fwspeed(acaps);
8152                         lc->autoneg = AUTONEG_DISABLE;
8153                 }
8154
8155                 t4_os_link_changed(adapter, pi->port_id, link_ok);
8156         }
8157 }
8158
8159 /**
8160  *      t4_update_port_info - retrieve and update port information if changed
8161  *      @pi: the port_info
8162  *
8163  *      We issue a Get Port Information Command to the Firmware and, if
8164  *      successful, we check to see if anything is different from what we
8165  *      last recorded and update things accordingly.
8166  */
8167 int t4_update_port_info(struct port_info *pi)
8168 {
8169         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8170         struct fw_port_cmd port_cmd;
8171         int ret;
8172
8173         memset(&port_cmd, 0, sizeof(port_cmd));
8174         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8175                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8176                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8177         port_cmd.action_to_len16 = cpu_to_be32(
8178                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8179                                      ? FW_PORT_ACTION_GET_PORT_INFO
8180                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8181                 FW_LEN16(port_cmd));
8182         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8183                          &port_cmd, sizeof(port_cmd), &port_cmd);
8184         if (ret)
8185                 return ret;
8186
8187         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8188         return 0;
8189 }
8190
8191 /**
8192  *      t4_get_link_params - retrieve basic link parameters for given port
8193  *      @pi: the port
8194  *      @link_okp: value return pointer for link up/down
8195  *      @speedp: value return pointer for speed (Mb/s)
8196  *      @mtup: value return pointer for mtu
8197  *
8198  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8199  *      and MTU for a specified port.  A negative error is returned on
8200  *      failure; 0 on success.
8201  */
8202 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8203                        unsigned int *speedp, unsigned int *mtup)
8204 {
8205         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8206         struct fw_port_cmd port_cmd;
8207         unsigned int action, link_ok, speed, mtu;
8208         fw_port_cap32_t linkattr;
8209         int ret;
8210
8211         memset(&port_cmd, 0, sizeof(port_cmd));
8212         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8213                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8214                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8215         action = (fw_caps == FW_CAPS16
8216                   ? FW_PORT_ACTION_GET_PORT_INFO
8217                   : FW_PORT_ACTION_GET_PORT_INFO32);
8218         port_cmd.action_to_len16 = cpu_to_be32(
8219                 FW_PORT_CMD_ACTION_V(action) |
8220                 FW_LEN16(port_cmd));
8221         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8222                          &port_cmd, sizeof(port_cmd), &port_cmd);
8223         if (ret)
8224                 return ret;
8225
8226         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8227                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8228
8229                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8230                 linkattr = lstatus_to_fwcap(lstatus);
8231                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8232         } else {
8233                 u32 lstatus32 =
8234                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8235
8236                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8237                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8238                 mtu = FW_PORT_CMD_MTU32_G(
8239                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8240         }
8241         speed = fwcap_to_speed(linkattr);
8242
8243         *link_okp = link_ok;
8244         *speedp = fwcap_to_speed(linkattr);
8245         *mtup = mtu;
8246
8247         return 0;
8248 }
8249
8250 /**
8251  *      t4_handle_fw_rpl - process a FW reply message
8252  *      @adap: the adapter
8253  *      @rpl: start of the FW message
8254  *
8255  *      Processes a FW message, such as link state change messages.
8256  */
8257 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8258 {
8259         u8 opcode = *(const u8 *)rpl;
8260
8261         /* This might be a port command ... this simplifies the following
8262          * conditionals ...  We can get away with pre-dereferencing
8263          * action_to_len16 because it's in the first 16 bytes and all messages
8264          * will be at least that long.
8265          */
8266         const struct fw_port_cmd *p = (const void *)rpl;
8267         unsigned int action =
8268                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8269
8270         if (opcode == FW_PORT_CMD &&
8271             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8272              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8273                 int i;
8274                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8275                 struct port_info *pi = NULL;
8276
8277                 for_each_port(adap, i) {
8278                         pi = adap2pinfo(adap, i);
8279                         if (pi->tx_chan == chan)
8280                                 break;
8281                 }
8282
8283                 t4_handle_get_port_info(pi, rpl);
8284         } else {
8285                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8286                          opcode);
8287                 return -EINVAL;
8288         }
8289         return 0;
8290 }
8291
8292 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8293 {
8294         u16 val;
8295
8296         if (pci_is_pcie(adapter->pdev)) {
8297                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8298                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8299                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8300         }
8301 }
8302
8303 /**
8304  *      init_link_config - initialize a link's SW state
8305  *      @lc: pointer to structure holding the link state
8306  *      @pcaps: link Port Capabilities
8307  *      @acaps: link current Advertised Port Capabilities
8308  *
8309  *      Initializes the SW state maintained for each link, including the link's
8310  *      capabilities and default speed/flow-control/autonegotiation settings.
8311  */
8312 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8313                              fw_port_cap32_t acaps)
8314 {
8315         lc->pcaps = pcaps;
8316         lc->def_acaps = acaps;
8317         lc->lpacaps = 0;
8318         lc->speed_caps = 0;
8319         lc->speed = 0;
8320         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8321
8322         /* For Forward Error Control, we default to whatever the Firmware
8323          * tells us the Link is currently advertising.
8324          */
8325         lc->requested_fec = FEC_AUTO;
8326         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8327
8328         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8329                 lc->acaps = lc->pcaps & ADVERT_MASK;
8330                 lc->autoneg = AUTONEG_ENABLE;
8331                 lc->requested_fc |= PAUSE_AUTONEG;
8332         } else {
8333                 lc->acaps = 0;
8334                 lc->autoneg = AUTONEG_DISABLE;
8335         }
8336 }
8337
8338 #define CIM_PF_NOACCESS 0xeeeeeeee
8339
8340 int t4_wait_dev_ready(void __iomem *regs)
8341 {
8342         u32 whoami;
8343
8344         whoami = readl(regs + PL_WHOAMI_A);
8345         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8346                 return 0;
8347
8348         msleep(500);
8349         whoami = readl(regs + PL_WHOAMI_A);
8350         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8351 }
8352
8353 struct flash_desc {
8354         u32 vendor_and_model_id;
8355         u32 size_mb;
8356 };
8357
8358 static int t4_get_flash_params(struct adapter *adap)
8359 {
8360         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8361          * to the preexisting code.  All flash parts have 64KB sectors.
8362          */
8363         static struct flash_desc supported_flash[] = {
8364                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8365         };
8366
8367         unsigned int part, manufacturer;
8368         unsigned int density, size;
8369         u32 flashid = 0;
8370         int ret;
8371
8372         /* Issue a Read ID Command to the Flash part.  We decode supported
8373          * Flash parts and their sizes from this.  There's a newer Query
8374          * Command which can retrieve detailed geometry information but many
8375          * Flash parts don't support it.
8376          */
8377
8378         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8379         if (!ret)
8380                 ret = sf1_read(adap, 3, 0, 1, &flashid);
8381         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8382         if (ret)
8383                 return ret;
8384
8385         /* Check to see if it's one of our non-standard supported Flash parts.
8386          */
8387         for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8388                 if (supported_flash[part].vendor_and_model_id == flashid) {
8389                         adap->params.sf_size = supported_flash[part].size_mb;
8390                         adap->params.sf_nsec =
8391                                 adap->params.sf_size / SF_SEC_SIZE;
8392                         goto found;
8393                 }
8394
8395         /* Decode Flash part size.  The code below looks repetative with
8396          * common encodings, but that's not guaranteed in the JEDEC
8397          * specification for the Read JADEC ID command.  The only thing that
8398          * we're guaranteed by the JADEC specification is where the
8399          * Manufacturer ID is in the returned result.  After that each
8400          * Manufacturer ~could~ encode things completely differently.
8401          * Note, all Flash parts must have 64KB sectors.
8402          */
8403         manufacturer = flashid & 0xff;
8404         switch (manufacturer) {
8405         case 0x20: { /* Micron/Numonix */
8406                 /* This Density -> Size decoding table is taken from Micron
8407                  * Data Sheets.
8408                  */
8409                 density = (flashid >> 16) & 0xff;
8410                 switch (density) {
8411                 case 0x14: /* 1MB */
8412                         size = 1 << 20;
8413                         break;
8414                 case 0x15: /* 2MB */
8415                         size = 1 << 21;
8416                         break;
8417                 case 0x16: /* 4MB */
8418                         size = 1 << 22;
8419                         break;
8420                 case 0x17: /* 8MB */
8421                         size = 1 << 23;
8422                         break;
8423                 case 0x18: /* 16MB */
8424                         size = 1 << 24;
8425                         break;
8426                 case 0x19: /* 32MB */
8427                         size = 1 << 25;
8428                         break;
8429                 case 0x20: /* 64MB */
8430                         size = 1 << 26;
8431                         break;
8432                 case 0x21: /* 128MB */
8433                         size = 1 << 27;
8434                         break;
8435                 case 0x22: /* 256MB */
8436                         size = 1 << 28;
8437                         break;
8438
8439                 default:
8440                         dev_err(adap->pdev_dev, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
8441                                 flashid, density);
8442                         return -EINVAL;
8443                 }
8444                 break;
8445         }
8446         case 0xc2: { /* Macronix */
8447                 /* This Density -> Size decoding table is taken from Macronix
8448                  * Data Sheets.
8449                  */
8450                 density = (flashid >> 16) & 0xff;
8451                 switch (density) {
8452                 case 0x17: /* 8MB */
8453                         size = 1 << 23;
8454                         break;
8455                 case 0x18: /* 16MB */
8456                         size = 1 << 24;
8457                         break;
8458                 default:
8459                         dev_err(adap->pdev_dev, "Macronix Flash Part has bad size, ID = %#x, Density code = %#x\n",
8460                                 flashid, density);
8461                         return -EINVAL;
8462                 }
8463                 break;
8464         }
8465         case 0xef: { /* Winbond */
8466                 /* This Density -> Size decoding table is taken from Winbond
8467                  * Data Sheets.
8468                  */
8469                 density = (flashid >> 16) & 0xff;
8470                 switch (density) {
8471                 case 0x17: /* 8MB */
8472                         size = 1 << 23;
8473                         break;
8474                 case 0x18: /* 16MB */
8475                         size = 1 << 24;
8476                         break;
8477                 default:
8478                         dev_err(adap->pdev_dev, "Winbond Flash Part has bad size, ID = %#x, Density code = %#x\n",
8479                                 flashid, density);
8480                         return -EINVAL;
8481                 }
8482                 break;
8483         }
8484         default:
8485                 dev_err(adap->pdev_dev, "Unsupported Flash Part, ID = %#x\n",
8486                         flashid);
8487                 return -EINVAL;
8488         }
8489
8490         /* Store decoded Flash size and fall through into vetting code. */
8491         adap->params.sf_size = size;
8492         adap->params.sf_nsec = size / SF_SEC_SIZE;
8493
8494 found:
8495         if (adap->params.sf_size < FLASH_MIN_SIZE)
8496                 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8497                          flashid, adap->params.sf_size, FLASH_MIN_SIZE);
8498         return 0;
8499 }
8500
8501 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
8502 {
8503         u16 val;
8504         u32 pcie_cap;
8505
8506         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
8507         if (pcie_cap) {
8508                 pci_read_config_word(adapter->pdev,
8509                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
8510                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
8511                 val |= range;
8512                 pci_write_config_word(adapter->pdev,
8513                                       pcie_cap + PCI_EXP_DEVCTL2, val);
8514         }
8515 }
8516
8517 /**
8518  *      t4_prep_adapter - prepare SW and HW for operation
8519  *      @adapter: the adapter
8520  *      @reset: if true perform a HW reset
8521  *
8522  *      Initialize adapter SW state for the various HW modules, set initial
8523  *      values for some adapter tunables, take PHYs out of reset, and
8524  *      initialize the MDIO interface.
8525  */
8526 int t4_prep_adapter(struct adapter *adapter)
8527 {
8528         int ret, ver;
8529         uint16_t device_id;
8530         u32 pl_rev;
8531
8532         get_pci_mode(adapter, &adapter->params.pci);
8533         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8534
8535         ret = t4_get_flash_params(adapter);
8536         if (ret < 0) {
8537                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8538                 return ret;
8539         }
8540
8541         /* Retrieve adapter's device ID
8542          */
8543         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8544         ver = device_id >> 12;
8545         adapter->params.chip = 0;
8546         switch (ver) {
8547         case CHELSIO_T4:
8548                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8549                 adapter->params.arch.sge_fl_db = DBPRIO_F;
8550                 adapter->params.arch.mps_tcam_size =
8551                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
8552                 adapter->params.arch.mps_rplc_size = 128;
8553                 adapter->params.arch.nchan = NCHAN;
8554                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8555                 adapter->params.arch.vfcount = 128;
8556                 /* Congestion map is for 4 channels so that
8557                  * MPS can have 4 priority per port.
8558                  */
8559                 adapter->params.arch.cng_ch_bits_log = 2;
8560                 break;
8561         case CHELSIO_T5:
8562                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8563                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8564                 adapter->params.arch.mps_tcam_size =
8565                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8566                 adapter->params.arch.mps_rplc_size = 128;
8567                 adapter->params.arch.nchan = NCHAN;
8568                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8569                 adapter->params.arch.vfcount = 128;
8570                 adapter->params.arch.cng_ch_bits_log = 2;
8571                 break;
8572         case CHELSIO_T6:
8573                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8574                 adapter->params.arch.sge_fl_db = 0;
8575                 adapter->params.arch.mps_tcam_size =
8576                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8577                 adapter->params.arch.mps_rplc_size = 256;
8578                 adapter->params.arch.nchan = 2;
8579                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8580                 adapter->params.arch.vfcount = 256;
8581                 /* Congestion map will be for 2 channels so that
8582                  * MPS can have 8 priority per port.
8583                  */
8584                 adapter->params.arch.cng_ch_bits_log = 3;
8585                 break;
8586         default:
8587                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8588                         device_id);
8589                 return -EINVAL;
8590         }
8591
8592         adapter->params.cim_la_size = CIMLA_SIZE;
8593         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8594
8595         /*
8596          * Default port for debugging in case we can't reach FW.
8597          */
8598         adapter->params.nports = 1;
8599         adapter->params.portvec = 1;
8600         adapter->params.vpd.cclk = 50000;
8601
8602         /* Set pci completion timeout value to 4 seconds. */
8603         set_pcie_completion_timeout(adapter, 0xd);
8604         return 0;
8605 }
8606
8607 /**
8608  *      t4_shutdown_adapter - shut down adapter, host & wire
8609  *      @adapter: the adapter
8610  *
8611  *      Perform an emergency shutdown of the adapter and stop it from
8612  *      continuing any further communication on the ports or DMA to the
8613  *      host.  This is typically used when the adapter and/or firmware
8614  *      have crashed and we want to prevent any further accidental
8615  *      communication with the rest of the world.  This will also force
8616  *      the port Link Status to go down -- if register writes work --
8617  *      which should help our peers figure out that we're down.
8618  */
8619 int t4_shutdown_adapter(struct adapter *adapter)
8620 {
8621         int port;
8622
8623         t4_intr_disable(adapter);
8624         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
8625         for_each_port(adapter, port) {
8626                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
8627                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
8628                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
8629
8630                 t4_write_reg(adapter, a_port_cfg,
8631                              t4_read_reg(adapter, a_port_cfg)
8632                              & ~SIGNAL_DET_V(1));
8633         }
8634         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
8635
8636         return 0;
8637 }
8638
8639 /**
8640  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8641  *      @adapter: the adapter
8642  *      @qid: the Queue ID
8643  *      @qtype: the Ingress or Egress type for @qid
8644  *      @user: true if this request is for a user mode queue
8645  *      @pbar2_qoffset: BAR2 Queue Offset
8646  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8647  *
8648  *      Returns the BAR2 SGE Queue Registers information associated with the
8649  *      indicated Absolute Queue ID.  These are passed back in return value
8650  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8651  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8652  *
8653  *      This may return an error which indicates that BAR2 SGE Queue
8654  *      registers aren't available.  If an error is not returned, then the
8655  *      following values are returned:
8656  *
8657  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8658  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8659  *
8660  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8661  *      require the "Inferred Queue ID" ability may be used.  E.g. the
8662  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8663  *      then these "Inferred Queue ID" register may not be used.
8664  */
8665 int t4_bar2_sge_qregs(struct adapter *adapter,
8666                       unsigned int qid,
8667                       enum t4_bar2_qtype qtype,
8668                       int user,
8669                       u64 *pbar2_qoffset,
8670                       unsigned int *pbar2_qid)
8671 {
8672         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
8673         u64 bar2_page_offset, bar2_qoffset;
8674         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
8675
8676         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
8677         if (!user && is_t4(adapter->params.chip))
8678                 return -EINVAL;
8679
8680         /* Get our SGE Page Size parameters.
8681          */
8682         page_shift = adapter->params.sge.hps + 10;
8683         page_size = 1 << page_shift;
8684
8685         /* Get the right Queues per Page parameters for our Queue.
8686          */
8687         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
8688                      ? adapter->params.sge.eq_qpp
8689                      : adapter->params.sge.iq_qpp);
8690         qpp_mask = (1 << qpp_shift) - 1;
8691
8692         /*  Calculate the basics of the BAR2 SGE Queue register area:
8693          *  o The BAR2 page the Queue registers will be in.
8694          *  o The BAR2 Queue ID.
8695          *  o The BAR2 Queue ID Offset into the BAR2 page.
8696          */
8697         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
8698         bar2_qid = qid & qpp_mask;
8699         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
8700
8701         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
8702          * hardware will infer the Absolute Queue ID simply from the writes to
8703          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
8704          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
8705          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
8706          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
8707          * from the BAR2 Page and BAR2 Queue ID.
8708          *
8709          * One important censequence of this is that some BAR2 SGE registers
8710          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
8711          * there.  But other registers synthesize the SGE Queue ID purely
8712          * from the writes to the registers -- the Write Combined Doorbell
8713          * Buffer is a good example.  These BAR2 SGE Registers are only
8714          * available for those BAR2 SGE Register areas where the SGE Absolute
8715          * Queue ID can be inferred from simple writes.
8716          */
8717         bar2_qoffset = bar2_page_offset;
8718         bar2_qinferred = (bar2_qid_offset < page_size);
8719         if (bar2_qinferred) {
8720                 bar2_qoffset += bar2_qid_offset;
8721                 bar2_qid = 0;
8722         }
8723
8724         *pbar2_qoffset = bar2_qoffset;
8725         *pbar2_qid = bar2_qid;
8726         return 0;
8727 }
8728
8729 /**
8730  *      t4_init_devlog_params - initialize adapter->params.devlog
8731  *      @adap: the adapter
8732  *
8733  *      Initialize various fields of the adapter's Firmware Device Log
8734  *      Parameters structure.
8735  */
8736 int t4_init_devlog_params(struct adapter *adap)
8737 {
8738         struct devlog_params *dparams = &adap->params.devlog;
8739         u32 pf_dparams;
8740         unsigned int devlog_meminfo;
8741         struct fw_devlog_cmd devlog_cmd;
8742         int ret;
8743
8744         /* If we're dealing with newer firmware, the Device Log Paramerters
8745          * are stored in a designated register which allows us to access the
8746          * Device Log even if we can't talk to the firmware.
8747          */
8748         pf_dparams =
8749                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
8750         if (pf_dparams) {
8751                 unsigned int nentries, nentries128;
8752
8753                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
8754                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
8755
8756                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
8757                 nentries = (nentries128 + 1) * 128;
8758                 dparams->size = nentries * sizeof(struct fw_devlog_e);
8759
8760                 return 0;
8761         }
8762
8763         /* Otherwise, ask the firmware for it's Device Log Parameters.
8764          */
8765         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
8766         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
8767                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
8768         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
8769         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
8770                          &devlog_cmd);
8771         if (ret)
8772                 return ret;
8773
8774         devlog_meminfo =
8775                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
8776         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
8777         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
8778         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
8779
8780         return 0;
8781 }
8782
8783 /**
8784  *      t4_init_sge_params - initialize adap->params.sge
8785  *      @adapter: the adapter
8786  *
8787  *      Initialize various fields of the adapter's SGE Parameters structure.
8788  */
8789 int t4_init_sge_params(struct adapter *adapter)
8790 {
8791         struct sge_params *sge_params = &adapter->params.sge;
8792         u32 hps, qpp;
8793         unsigned int s_hps, s_qpp;
8794
8795         /* Extract the SGE Page Size for our PF.
8796          */
8797         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
8798         s_hps = (HOSTPAGESIZEPF0_S +
8799                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
8800         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
8801
8802         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
8803          */
8804         s_qpp = (QUEUESPERPAGEPF0_S +
8805                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
8806         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
8807         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8808         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
8809         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8810
8811         return 0;
8812 }
8813
8814 /**
8815  *      t4_init_tp_params - initialize adap->params.tp
8816  *      @adap: the adapter
8817  *      @sleep_ok: if true we may sleep while awaiting command completion
8818  *
8819  *      Initialize various fields of the adapter's TP Parameters structure.
8820  */
8821 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
8822 {
8823         int chan;
8824         u32 v;
8825
8826         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
8827         adap->params.tp.tre = TIMERRESOLUTION_G(v);
8828         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
8829
8830         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8831         for (chan = 0; chan < NCHAN; chan++)
8832                 adap->params.tp.tx_modq[chan] = chan;
8833
8834         /* Cache the adapter's Compressed Filter Mode and global Incress
8835          * Configuration.
8836          */
8837         t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
8838                        TP_VLAN_PRI_MAP_A, sleep_ok);
8839         t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
8840                        TP_INGRESS_CONFIG_A, sleep_ok);
8841
8842         /* For T6, cache the adapter's compressed error vector
8843          * and passing outer header info for encapsulated packets.
8844          */
8845         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
8846                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
8847                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
8848         }
8849
8850         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
8851          * shift positions of several elements of the Compressed Filter Tuple
8852          * for this adapter which we need frequently ...
8853          */
8854         adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
8855         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
8856         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
8857         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
8858         adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
8859         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
8860                                                                PROTOCOL_F);
8861         adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
8862                                                                 ETHERTYPE_F);
8863         adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
8864                                                                MACMATCH_F);
8865         adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
8866                                                                 MPSHITTYPE_F);
8867         adap->params.tp.frag_shift = t4_filter_field_shift(adap,
8868                                                            FRAGMENTATION_F);
8869
8870         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8871          * represents the presence of an Outer VLAN instead of a VNIC ID.
8872          */
8873         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
8874                 adap->params.tp.vnic_shift = -1;
8875
8876         v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
8877         adap->params.tp.hash_filter_mask = v;
8878         v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
8879         adap->params.tp.hash_filter_mask |= ((u64)v << 32);
8880         return 0;
8881 }
8882
8883 /**
8884  *      t4_filter_field_shift - calculate filter field shift
8885  *      @adap: the adapter
8886  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8887  *
8888  *      Return the shift position of a filter field within the Compressed
8889  *      Filter Tuple.  The filter field is specified via its selection bit
8890  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8891  */
8892 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8893 {
8894         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8895         unsigned int sel;
8896         int field_shift;
8897
8898         if ((filter_mode & filter_sel) == 0)
8899                 return -1;
8900
8901         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8902                 switch (filter_mode & sel) {
8903                 case FCOE_F:
8904                         field_shift += FT_FCOE_W;
8905                         break;
8906                 case PORT_F:
8907                         field_shift += FT_PORT_W;
8908                         break;
8909                 case VNIC_ID_F:
8910                         field_shift += FT_VNIC_ID_W;
8911                         break;
8912                 case VLAN_F:
8913                         field_shift += FT_VLAN_W;
8914                         break;
8915                 case TOS_F:
8916                         field_shift += FT_TOS_W;
8917                         break;
8918                 case PROTOCOL_F:
8919                         field_shift += FT_PROTOCOL_W;
8920                         break;
8921                 case ETHERTYPE_F:
8922                         field_shift += FT_ETHERTYPE_W;
8923                         break;
8924                 case MACMATCH_F:
8925                         field_shift += FT_MACMATCH_W;
8926                         break;
8927                 case MPSHITTYPE_F:
8928                         field_shift += FT_MPSHITTYPE_W;
8929                         break;
8930                 case FRAGMENTATION_F:
8931                         field_shift += FT_FRAGMENTATION_W;
8932                         break;
8933                 }
8934         }
8935         return field_shift;
8936 }
8937
8938 int t4_init_rss_mode(struct adapter *adap, int mbox)
8939 {
8940         int i, ret;
8941         struct fw_rss_vi_config_cmd rvc;
8942
8943         memset(&rvc, 0, sizeof(rvc));
8944
8945         for_each_port(adap, i) {
8946                 struct port_info *p = adap2pinfo(adap, i);
8947
8948                 rvc.op_to_viid =
8949                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
8950                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
8951                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
8952                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
8953                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
8954                 if (ret)
8955                         return ret;
8956                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
8957         }
8958         return 0;
8959 }
8960
8961 /**
8962  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
8963  *      @pi: the port_info
8964  *      @mbox: mailbox to use for the FW command
8965  *      @port: physical port associated with the VI
8966  *      @pf: the PF owning the VI
8967  *      @vf: the VF owning the VI
8968  *      @mac: the MAC address of the VI
8969  *
8970  *      Allocates a virtual interface for the given physical port.  If @mac is
8971  *      not %NULL it contains the MAC address of the VI as assigned by FW.
8972  *      @mac should be large enough to hold an Ethernet address.
8973  *      Returns < 0 on error.
8974  */
8975 int t4_init_portinfo(struct port_info *pi, int mbox,
8976                      int port, int pf, int vf, u8 mac[])
8977 {
8978         struct adapter *adapter = pi->adapter;
8979         unsigned int fw_caps = adapter->params.fw_caps_support;
8980         struct fw_port_cmd cmd;
8981         unsigned int rss_size;
8982         enum fw_port_type port_type;
8983         int mdio_addr;
8984         fw_port_cap32_t pcaps, acaps;
8985         int ret;
8986
8987         /* If we haven't yet determined whether we're talking to Firmware
8988          * which knows the new 32-bit Port Capabilities, it's time to find
8989          * out now.  This will also tell new Firmware to send us Port Status
8990          * Updates using the new 32-bit Port Capabilities version of the
8991          * Port Information message.
8992          */
8993         if (fw_caps == FW_CAPS_UNKNOWN) {
8994                 u32 param, val;
8995
8996                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
8997                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
8998                 val = 1;
8999                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
9000                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9001                 adapter->params.fw_caps_support = fw_caps;
9002         }
9003
9004         memset(&cmd, 0, sizeof(cmd));
9005         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9006                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
9007                                        FW_PORT_CMD_PORTID_V(port));
9008         cmd.action_to_len16 = cpu_to_be32(
9009                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9010                                      ? FW_PORT_ACTION_GET_PORT_INFO
9011                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
9012                 FW_LEN16(cmd));
9013         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9014         if (ret)
9015                 return ret;
9016
9017         /* Extract the various fields from the Port Information message.
9018          */
9019         if (fw_caps == FW_CAPS16) {
9020                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9021
9022                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9023                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9024                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9025                              : -1);
9026                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9027                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9028         } else {
9029                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9030
9031                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9032                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9033                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9034                              : -1);
9035                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9036                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9037         }
9038
9039         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
9040         if (ret < 0)
9041                 return ret;
9042
9043         pi->viid = ret;
9044         pi->tx_chan = port;
9045         pi->lport = port;
9046         pi->rss_size = rss_size;
9047
9048         pi->port_type = port_type;
9049         pi->mdio_addr = mdio_addr;
9050         pi->mod_type = FW_PORT_MOD_TYPE_NA;
9051
9052         init_link_config(&pi->link_cfg, pcaps, acaps);
9053         return 0;
9054 }
9055
9056 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9057 {
9058         u8 addr[6];
9059         int ret, i, j = 0;
9060
9061         for_each_port(adap, i) {
9062                 struct port_info *pi = adap2pinfo(adap, i);
9063
9064                 while ((adap->params.portvec & (1 << j)) == 0)
9065                         j++;
9066
9067                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9068                 if (ret)
9069                         return ret;
9070
9071                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9072                 j++;
9073         }
9074         return 0;
9075 }
9076
9077 /**
9078  *      t4_read_cimq_cfg - read CIM queue configuration
9079  *      @adap: the adapter
9080  *      @base: holds the queue base addresses in bytes
9081  *      @size: holds the queue sizes in bytes
9082  *      @thres: holds the queue full thresholds in bytes
9083  *
9084  *      Returns the current configuration of the CIM queues, starting with
9085  *      the IBQs, then the OBQs.
9086  */
9087 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9088 {
9089         unsigned int i, v;
9090         int cim_num_obq = is_t4(adap->params.chip) ?
9091                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9092
9093         for (i = 0; i < CIM_NUM_IBQ; i++) {
9094                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9095                              QUENUMSELECT_V(i));
9096                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9097                 /* value is in 256-byte units */
9098                 *base++ = CIMQBASE_G(v) * 256;
9099                 *size++ = CIMQSIZE_G(v) * 256;
9100                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9101         }
9102         for (i = 0; i < cim_num_obq; i++) {
9103                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9104                              QUENUMSELECT_V(i));
9105                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9106                 /* value is in 256-byte units */
9107                 *base++ = CIMQBASE_G(v) * 256;
9108                 *size++ = CIMQSIZE_G(v) * 256;
9109         }
9110 }
9111
9112 /**
9113  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
9114  *      @adap: the adapter
9115  *      @qid: the queue index
9116  *      @data: where to store the queue contents
9117  *      @n: capacity of @data in 32-bit words
9118  *
9119  *      Reads the contents of the selected CIM queue starting at address 0 up
9120  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9121  *      error and the number of 32-bit words actually read on success.
9122  */
9123 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9124 {
9125         int i, err, attempts;
9126         unsigned int addr;
9127         const unsigned int nwords = CIM_IBQ_SIZE * 4;
9128
9129         if (qid > 5 || (n & 3))
9130                 return -EINVAL;
9131
9132         addr = qid * nwords;
9133         if (n > nwords)
9134                 n = nwords;
9135
9136         /* It might take 3-10ms before the IBQ debug read access is allowed.
9137          * Wait for 1 Sec with a delay of 1 usec.
9138          */
9139         attempts = 1000000;
9140
9141         for (i = 0; i < n; i++, addr++) {
9142                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9143                              IBQDBGEN_F);
9144                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9145                                       attempts, 1);
9146                 if (err)
9147                         return err;
9148                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9149         }
9150         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9151         return i;
9152 }
9153
9154 /**
9155  *      t4_read_cim_obq - read the contents of a CIM outbound queue
9156  *      @adap: the adapter
9157  *      @qid: the queue index
9158  *      @data: where to store the queue contents
9159  *      @n: capacity of @data in 32-bit words
9160  *
9161  *      Reads the contents of the selected CIM queue starting at address 0 up
9162  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9163  *      error and the number of 32-bit words actually read on success.
9164  */
9165 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9166 {
9167         int i, err;
9168         unsigned int addr, v, nwords;
9169         int cim_num_obq = is_t4(adap->params.chip) ?
9170                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9171
9172         if ((qid > (cim_num_obq - 1)) || (n & 3))
9173                 return -EINVAL;
9174
9175         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9176                      QUENUMSELECT_V(qid));
9177         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9178
9179         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
9180         nwords = CIMQSIZE_G(v) * 64;  /* same */
9181         if (n > nwords)
9182                 n = nwords;
9183
9184         for (i = 0; i < n; i++, addr++) {
9185                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9186                              OBQDBGEN_F);
9187                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9188                                       2, 1);
9189                 if (err)
9190                         return err;
9191                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9192         }
9193         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9194         return i;
9195 }
9196
9197 /**
9198  *      t4_cim_read - read a block from CIM internal address space
9199  *      @adap: the adapter
9200  *      @addr: the start address within the CIM address space
9201  *      @n: number of words to read
9202  *      @valp: where to store the result
9203  *
9204  *      Reads a block of 4-byte words from the CIM intenal address space.
9205  */
9206 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9207                 unsigned int *valp)
9208 {
9209         int ret = 0;
9210
9211         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9212                 return -EBUSY;
9213
9214         for ( ; !ret && n--; addr += 4) {
9215                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9216                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9217                                       0, 5, 2);
9218                 if (!ret)
9219                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9220         }
9221         return ret;
9222 }
9223
9224 /**
9225  *      t4_cim_write - write a block into CIM internal address space
9226  *      @adap: the adapter
9227  *      @addr: the start address within the CIM address space
9228  *      @n: number of words to write
9229  *      @valp: set of values to write
9230  *
9231  *      Writes a block of 4-byte words into the CIM intenal address space.
9232  */
9233 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9234                  const unsigned int *valp)
9235 {
9236         int ret = 0;
9237
9238         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9239                 return -EBUSY;
9240
9241         for ( ; !ret && n--; addr += 4) {
9242                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9243                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9244                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9245                                       0, 5, 2);
9246         }
9247         return ret;
9248 }
9249
9250 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9251                          unsigned int val)
9252 {
9253         return t4_cim_write(adap, addr, 1, &val);
9254 }
9255
9256 /**
9257  *      t4_cim_read_la - read CIM LA capture buffer
9258  *      @adap: the adapter
9259  *      @la_buf: where to store the LA data
9260  *      @wrptr: the HW write pointer within the capture buffer
9261  *
9262  *      Reads the contents of the CIM LA buffer with the most recent entry at
9263  *      the end of the returned data and with the entry at @wrptr first.
9264  *      We try to leave the LA in the running state we find it in.
9265  */
9266 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9267 {
9268         int i, ret;
9269         unsigned int cfg, val, idx;
9270
9271         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9272         if (ret)
9273                 return ret;
9274
9275         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9276                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9277                 if (ret)
9278                         return ret;
9279         }
9280
9281         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9282         if (ret)
9283                 goto restart;
9284
9285         idx = UPDBGLAWRPTR_G(val);
9286         if (wrptr)
9287                 *wrptr = idx;
9288
9289         for (i = 0; i < adap->params.cim_la_size; i++) {
9290                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9291                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9292                 if (ret)
9293                         break;
9294                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9295                 if (ret)
9296                         break;
9297                 if (val & UPDBGLARDEN_F) {
9298                         ret = -ETIMEDOUT;
9299                         break;
9300                 }
9301                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9302                 if (ret)
9303                         break;
9304
9305                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9306                  * identify the 32-bit portion of the full 312-bit data
9307                  */
9308                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9309                         idx = (idx & 0xff0) + 0x10;
9310                 else
9311                         idx++;
9312                 /* address can't exceed 0xfff */
9313                 idx &= UPDBGLARDPTR_M;
9314         }
9315 restart:
9316         if (cfg & UPDBGLAEN_F) {
9317                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9318                                       cfg & ~UPDBGLARDEN_F);
9319                 if (!ret)
9320                         ret = r;
9321         }
9322         return ret;
9323 }
9324
9325 /**
9326  *      t4_tp_read_la - read TP LA capture buffer
9327  *      @adap: the adapter
9328  *      @la_buf: where to store the LA data
9329  *      @wrptr: the HW write pointer within the capture buffer
9330  *
9331  *      Reads the contents of the TP LA buffer with the most recent entry at
9332  *      the end of the returned data and with the entry at @wrptr first.
9333  *      We leave the LA in the running state we find it in.
9334  */
9335 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9336 {
9337         bool last_incomplete;
9338         unsigned int i, cfg, val, idx;
9339
9340         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9341         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
9342                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9343                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9344
9345         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9346         idx = DBGLAWPTR_G(val);
9347         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9348         if (last_incomplete)
9349                 idx = (idx + 1) & DBGLARPTR_M;
9350         if (wrptr)
9351                 *wrptr = idx;
9352
9353         val &= 0xffff;
9354         val &= ~DBGLARPTR_V(DBGLARPTR_M);
9355         val |= adap->params.tp.la_mask;
9356
9357         for (i = 0; i < TPLA_SIZE; i++) {
9358                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9359                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9360                 idx = (idx + 1) & DBGLARPTR_M;
9361         }
9362
9363         /* Wipe out last entry if it isn't valid */
9364         if (last_incomplete)
9365                 la_buf[TPLA_SIZE - 1] = ~0ULL;
9366
9367         if (cfg & DBGLAENABLE_F)                    /* restore running state */
9368                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9369                              cfg | adap->params.tp.la_mask);
9370 }
9371
9372 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9373  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
9374  * state for more than the Warning Threshold then we'll issue a warning about
9375  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
9376  * appears to be hung every Warning Repeat second till the situation clears.
9377  * If the situation clears, we'll note that as well.
9378  */
9379 #define SGE_IDMA_WARN_THRESH 1
9380 #define SGE_IDMA_WARN_REPEAT 300
9381
9382 /**
9383  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9384  *      @adapter: the adapter
9385  *      @idma: the adapter IDMA Monitor state
9386  *
9387  *      Initialize the state of an SGE Ingress DMA Monitor.
9388  */
9389 void t4_idma_monitor_init(struct adapter *adapter,
9390                           struct sge_idma_monitor_state *idma)
9391 {
9392         /* Initialize the state variables for detecting an SGE Ingress DMA
9393          * hang.  The SGE has internal counters which count up on each clock
9394          * tick whenever the SGE finds its Ingress DMA State Engines in the
9395          * same state they were on the previous clock tick.  The clock used is
9396          * the Core Clock so we have a limit on the maximum "time" they can
9397          * record; typically a very small number of seconds.  For instance,
9398          * with a 600MHz Core Clock, we can only count up to a bit more than
9399          * 7s.  So we'll synthesize a larger counter in order to not run the
9400          * risk of having the "timers" overflow and give us the flexibility to
9401          * maintain a Hung SGE State Machine of our own which operates across
9402          * a longer time frame.
9403          */
9404         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9405         idma->idma_stalled[0] = 0;
9406         idma->idma_stalled[1] = 0;
9407 }
9408
9409 /**
9410  *      t4_idma_monitor - monitor SGE Ingress DMA state
9411  *      @adapter: the adapter
9412  *      @idma: the adapter IDMA Monitor state
9413  *      @hz: number of ticks/second
9414  *      @ticks: number of ticks since the last IDMA Monitor call
9415  */
9416 void t4_idma_monitor(struct adapter *adapter,
9417                      struct sge_idma_monitor_state *idma,
9418                      int hz, int ticks)
9419 {
9420         int i, idma_same_state_cnt[2];
9421
9422          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
9423           * are counters inside the SGE which count up on each clock when the
9424           * SGE finds its Ingress DMA State Engines in the same states they
9425           * were in the previous clock.  The counters will peg out at
9426           * 0xffffffff without wrapping around so once they pass the 1s
9427           * threshold they'll stay above that till the IDMA state changes.
9428           */
9429         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9430         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9431         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9432
9433         for (i = 0; i < 2; i++) {
9434                 u32 debug0, debug11;
9435
9436                 /* If the Ingress DMA Same State Counter ("timer") is less
9437                  * than 1s, then we can reset our synthesized Stall Timer and
9438                  * continue.  If we have previously emitted warnings about a
9439                  * potential stalled Ingress Queue, issue a note indicating
9440                  * that the Ingress Queue has resumed forward progress.
9441                  */
9442                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9443                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9444                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9445                                          "resumed after %d seconds\n",
9446                                          i, idma->idma_qid[i],
9447                                          idma->idma_stalled[i] / hz);
9448                         idma->idma_stalled[i] = 0;
9449                         continue;
9450                 }
9451
9452                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9453                  * domain.  The first time we get here it'll be because we
9454                  * passed the 1s Threshold; each additional time it'll be
9455                  * because the RX Timer Callback is being fired on its regular
9456                  * schedule.
9457                  *
9458                  * If the stall is below our Potential Hung Ingress Queue
9459                  * Warning Threshold, continue.
9460                  */
9461                 if (idma->idma_stalled[i] == 0) {
9462                         idma->idma_stalled[i] = hz;
9463                         idma->idma_warn[i] = 0;
9464                 } else {
9465                         idma->idma_stalled[i] += ticks;
9466                         idma->idma_warn[i] -= ticks;
9467                 }
9468
9469                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9470                         continue;
9471
9472                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9473                  */
9474                 if (idma->idma_warn[i] > 0)
9475                         continue;
9476                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9477
9478                 /* Read and save the SGE IDMA State and Queue ID information.
9479                  * We do this every time in case it changes across time ...
9480                  * can't be too careful ...
9481                  */
9482                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9483                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9484                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9485
9486                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9487                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9488                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9489
9490                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9491                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9492                          i, idma->idma_qid[i], idma->idma_state[i],
9493                          idma->idma_stalled[i] / hz,
9494                          debug0, debug11);
9495                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9496         }
9497 }
9498
9499 /**
9500  *      t4_load_cfg - download config file
9501  *      @adap: the adapter
9502  *      @cfg_data: the cfg text file to write
9503  *      @size: text file size
9504  *
9505  *      Write the supplied config text file to the card's serial flash.
9506  */
9507 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9508 {
9509         int ret, i, n, cfg_addr;
9510         unsigned int addr;
9511         unsigned int flash_cfg_start_sec;
9512         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9513
9514         cfg_addr = t4_flash_cfg_addr(adap);
9515         if (cfg_addr < 0)
9516                 return cfg_addr;
9517
9518         addr = cfg_addr;
9519         flash_cfg_start_sec = addr / SF_SEC_SIZE;
9520
9521         if (size > FLASH_CFG_MAX_SIZE) {
9522                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9523                         FLASH_CFG_MAX_SIZE);
9524                 return -EFBIG;
9525         }
9526
9527         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
9528                          sf_sec_size);
9529         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9530                                      flash_cfg_start_sec + i - 1);
9531         /* If size == 0 then we're simply erasing the FLASH sectors associated
9532          * with the on-adapter Firmware Configuration File.
9533          */
9534         if (ret || size == 0)
9535                 goto out;
9536
9537         /* this will write to the flash up to SF_PAGE_SIZE at a time */
9538         for (i = 0; i < size; i += SF_PAGE_SIZE) {
9539                 if ((size - i) <  SF_PAGE_SIZE)
9540                         n = size - i;
9541                 else
9542                         n = SF_PAGE_SIZE;
9543                 ret = t4_write_flash(adap, addr, n, cfg_data);
9544                 if (ret)
9545                         goto out;
9546
9547                 addr += SF_PAGE_SIZE;
9548                 cfg_data += SF_PAGE_SIZE;
9549         }
9550
9551 out:
9552         if (ret)
9553                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9554                         (size == 0 ? "clear" : "download"), ret);
9555         return ret;
9556 }
9557
9558 /**
9559  *      t4_set_vf_mac - Set MAC address for the specified VF
9560  *      @adapter: The adapter
9561  *      @vf: one of the VFs instantiated by the specified PF
9562  *      @naddr: the number of MAC addresses
9563  *      @addr: the MAC address(es) to be set to the specified VF
9564  */
9565 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9566                       unsigned int naddr, u8 *addr)
9567 {
9568         struct fw_acl_mac_cmd cmd;
9569
9570         memset(&cmd, 0, sizeof(cmd));
9571         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9572                                     FW_CMD_REQUEST_F |
9573                                     FW_CMD_WRITE_F |
9574                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9575                                     FW_ACL_MAC_CMD_VFN_V(vf));
9576
9577         /* Note: Do not enable the ACL */
9578         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9579         cmd.nmac = naddr;
9580
9581         switch (adapter->pf) {
9582         case 3:
9583                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9584                 break;
9585         case 2:
9586                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9587                 break;
9588         case 1:
9589                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9590                 break;
9591         case 0:
9592                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9593                 break;
9594         }
9595
9596         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9597 }
9598
9599 /**
9600  * t4_read_pace_tbl - read the pace table
9601  * @adap: the adapter
9602  * @pace_vals: holds the returned values
9603  *
9604  * Returns the values of TP's pace table in microseconds.
9605  */
9606 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9607 {
9608         unsigned int i, v;
9609
9610         for (i = 0; i < NTX_SCHED; i++) {
9611                 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
9612                 v = t4_read_reg(adap, TP_PACE_TABLE_A);
9613                 pace_vals[i] = dack_ticks_to_usec(adap, v);
9614         }
9615 }
9616
9617 /**
9618  * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9619  * @adap: the adapter
9620  * @sched: the scheduler index
9621  * @kbps: the byte rate in Kbps
9622  * @ipg: the interpacket delay in tenths of nanoseconds
9623  * @sleep_ok: if true we may sleep while awaiting command completion
9624  *
9625  * Return the current configuration of a HW Tx scheduler.
9626  */
9627 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
9628                      unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
9629 {
9630         unsigned int v, addr, bpt, cpt;
9631
9632         if (kbps) {
9633                 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
9634                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9635                 if (sched & 1)
9636                         v >>= 16;
9637                 bpt = (v >> 8) & 0xff;
9638                 cpt = v & 0xff;
9639                 if (!cpt) {
9640                         *kbps = 0;      /* scheduler disabled */
9641                 } else {
9642                         v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
9643                         *kbps = (v * bpt) / 125;
9644                 }
9645         }
9646         if (ipg) {
9647                 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
9648                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9649                 if (sched & 1)
9650                         v >>= 16;
9651                 v &= 0xffff;
9652                 *ipg = (10000 * v) / core_ticks_per_usec(adap);
9653         }
9654 }
9655
9656 /* t4_sge_ctxt_rd - read an SGE context through FW
9657  * @adap: the adapter
9658  * @mbox: mailbox to use for the FW command
9659  * @cid: the context id
9660  * @ctype: the context type
9661  * @data: where to store the context data
9662  *
9663  * Issues a FW command through the given mailbox to read an SGE context.
9664  */
9665 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9666                    enum ctxt_type ctype, u32 *data)
9667 {
9668         struct fw_ldst_cmd c;
9669         int ret;
9670
9671         if (ctype == CTXT_FLM)
9672                 ret = FW_LDST_ADDRSPC_SGE_FLMC;
9673         else
9674                 ret = FW_LDST_ADDRSPC_SGE_CONMC;
9675
9676         memset(&c, 0, sizeof(c));
9677         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
9678                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
9679                                         FW_LDST_CMD_ADDRSPACE_V(ret));
9680         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9681         c.u.idctxt.physid = cpu_to_be32(cid);
9682
9683         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9684         if (ret == 0) {
9685                 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9686                 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9687                 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9688                 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9689                 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9690                 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9691         }
9692         return ret;
9693 }
9694
9695 /**
9696  * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9697  * @adap: the adapter
9698  * @cid: the context id
9699  * @ctype: the context type
9700  * @data: where to store the context data
9701  *
9702  * Reads an SGE context directly, bypassing FW.  This is only for
9703  * debugging when FW is unavailable.
9704  */
9705 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
9706                       enum ctxt_type ctype, u32 *data)
9707 {
9708         int i, ret;
9709
9710         t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
9711         ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
9712         if (!ret)
9713                 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
9714                         *data++ = t4_read_reg(adap, i);
9715         return ret;
9716 }
9717
9718 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9719                     int rateunit, int ratemode, int channel, int class,
9720                     int minrate, int maxrate, int weight, int pktsize)
9721 {
9722         struct fw_sched_cmd cmd;
9723
9724         memset(&cmd, 0, sizeof(cmd));
9725         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
9726                                       FW_CMD_REQUEST_F |
9727                                       FW_CMD_WRITE_F);
9728         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9729
9730         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9731         cmd.u.params.type = type;
9732         cmd.u.params.level = level;
9733         cmd.u.params.mode = mode;
9734         cmd.u.params.ch = channel;
9735         cmd.u.params.cl = class;
9736         cmd.u.params.unit = rateunit;
9737         cmd.u.params.rate = ratemode;
9738         cmd.u.params.min = cpu_to_be32(minrate);
9739         cmd.u.params.max = cpu_to_be32(maxrate);
9740         cmd.u.params.weight = cpu_to_be16(weight);
9741         cmd.u.params.pktsize = cpu_to_be16(pktsize);
9742
9743         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
9744                                NULL, 1);
9745 }