2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/if_vlan.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/jiffies.h>
42 #include <linux/prefetch.h>
43 #include <linux/export.h>
47 #include <net/busy_poll.h>
48 #ifdef CONFIG_CHELSIO_T4_FCOE
49 #include <scsi/fc/fc_fcoe.h>
50 #endif /* CONFIG_CHELSIO_T4_FCOE */
53 #include "t4_values.h"
56 #include "cxgb4_ptp.h"
57 #include "cxgb4_uld.h"
58 #include "cxgb4_tc_mqprio.h"
62 * Rx buffer size. We use largish buffers if possible but settle for single
63 * pages under memory shortage.
66 # define FL_PG_ORDER 0
68 # define FL_PG_ORDER (16 - PAGE_SHIFT)
71 /* RX_PULL_LEN should be <= RX_COPY_THRES */
72 #define RX_COPY_THRES 256
73 #define RX_PULL_LEN 128
76 * Main body length for sk_buffs used for Rx Ethernet packets with fragments.
77 * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room.
79 #define RX_PKT_SKB_LEN 512
82 * Max number of Tx descriptors we clean up at a time. Should be modest as
83 * freeing skbs isn't cheap and it happens while holding locks. We just need
84 * to free packets faster than they arrive, we eventually catch up and keep
85 * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES. It should
86 * also match the CIDX Flush Threshold.
88 #define MAX_TX_RECLAIM 32
91 * Max number of Rx buffers we replenish at a time. Again keep this modest,
92 * allocating buffers isn't cheap either.
94 #define MAX_RX_REFILL 16U
97 * Period of the Rx queue check timer. This timer is infrequent as it has
98 * something to do only when the system experiences severe memory shortage.
100 #define RX_QCHECK_PERIOD (HZ / 2)
103 * Period of the Tx queue check timer.
105 #define TX_QCHECK_PERIOD (HZ / 2)
108 * Max number of Tx descriptors to be reclaimed by the Tx timer.
110 #define MAX_TIMER_TX_RECLAIM 100
113 * Timer index used when backing off due to memory shortage.
115 #define NOMEM_TMR_IDX (SGE_NTIMERS - 1)
118 * Suspension threshold for non-Ethernet Tx queues. We require enough room
119 * for a full sized WR.
121 #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc))
124 * Max Tx descriptor space we allow for an Ethernet packet to be inlined
127 #define MAX_IMM_TX_PKT_LEN 256
130 * Max size of a WR sent through a control Tx queue.
132 #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN
134 struct rx_sw_desc { /* SW state per Rx descriptor */
140 * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb
141 * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs.
142 * We could easily support more but there doesn't seem to be much need for
145 #define FL_MTU_SMALL 1500
146 #define FL_MTU_LARGE 9000
148 static inline unsigned int fl_mtu_bufsize(struct adapter *adapter,
151 struct sge *s = &adapter->sge;
153 return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align);
156 #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL)
157 #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE)
160 * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses
161 * these to specify the buffer size as an index into the SGE Free List Buffer
162 * Size register array. We also use bit 4, when the buffer has been unmapped
163 * for DMA, but this is of course never sent to the hardware and is only used
164 * to prevent double unmappings. All of the above requires that the Free List
165 * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are
166 * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal
167 * Free List Buffer alignment is 32 bytes, this works out for us ...
170 RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */
171 RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */
172 RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */
175 * XXX We shouldn't depend on being able to use these indices.
176 * XXX Especially when some other Master PF has initialized the
177 * XXX adapter or we use the Firmware Configuration File. We
178 * XXX should really search through the Host Buffer Size register
179 * XXX array for the appropriately sized buffer indices.
181 RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */
182 RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */
184 RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */
185 RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */
188 static int timer_pkt_quota[] = {1, 1, 2, 3, 4, 5};
189 #define MIN_NAPI_WORK 1
191 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d)
193 return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS;
196 static inline bool is_buf_mapped(const struct rx_sw_desc *d)
198 return !(d->dma_addr & RX_UNMAPPED_BUF);
202 * txq_avail - return the number of available slots in a Tx queue
205 * Returns the number of descriptors in a Tx queue available to write new
208 static inline unsigned int txq_avail(const struct sge_txq *q)
210 return q->size - 1 - q->in_use;
214 * fl_cap - return the capacity of a free-buffer list
217 * Returns the capacity of a free-buffer list. The capacity is less than
218 * the size because one descriptor needs to be left unpopulated, otherwise
219 * HW will think the FL is empty.
221 static inline unsigned int fl_cap(const struct sge_fl *fl)
223 return fl->size - 8; /* 1 descriptor = 8 buffers */
227 * fl_starving - return whether a Free List is starving.
228 * @adapter: pointer to the adapter
231 * Tests specified Free List to see whether the number of buffers
232 * available to the hardware has falled below our "starvation"
235 static inline bool fl_starving(const struct adapter *adapter,
236 const struct sge_fl *fl)
238 const struct sge *s = &adapter->sge;
240 return fl->avail - fl->pend_cred <= s->fl_starve_thres;
243 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
246 const skb_frag_t *fp, *end;
247 const struct skb_shared_info *si;
249 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
250 if (dma_mapping_error(dev, *addr))
253 si = skb_shinfo(skb);
254 end = &si->frags[si->nr_frags];
256 for (fp = si->frags; fp < end; fp++) {
257 *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp),
259 if (dma_mapping_error(dev, *addr))
265 while (fp-- > si->frags)
266 dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE);
268 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
272 EXPORT_SYMBOL(cxgb4_map_skb);
274 static void unmap_skb(struct device *dev, const struct sk_buff *skb,
275 const dma_addr_t *addr)
277 const skb_frag_t *fp, *end;
278 const struct skb_shared_info *si;
280 dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE);
282 si = skb_shinfo(skb);
283 end = &si->frags[si->nr_frags];
284 for (fp = si->frags; fp < end; fp++)
285 dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE);
288 #ifdef CONFIG_NEED_DMA_MAP_STATE
290 * deferred_unmap_destructor - unmap a packet when it is freed
293 * This is the packet destructor used for Tx packets that need to remain
294 * mapped until they are freed rather than until their Tx descriptors are
297 static void deferred_unmap_destructor(struct sk_buff *skb)
299 unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head);
304 * free_tx_desc - reclaims Tx descriptors and their buffers
306 * @q: the Tx queue to reclaim descriptors from
307 * @n: the number of descriptors to reclaim
308 * @unmap: whether the buffers should be unmapped for DMA
310 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
311 * Tx buffers. Called with the Tx queue lock held.
313 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
314 unsigned int n, bool unmap)
316 unsigned int cidx = q->cidx;
317 struct tx_sw_desc *d;
321 if (d->skb) { /* an SGL is present */
322 if (unmap && d->addr[0]) {
323 unmap_skb(adap->pdev_dev, d->skb, d->addr);
324 memset(d->addr, 0, sizeof(d->addr));
326 dev_consume_skb_any(d->skb);
330 if (++cidx == q->size) {
339 * Return the number of reclaimable descriptors in a Tx queue.
341 static inline int reclaimable(const struct sge_txq *q)
343 int hw_cidx = ntohs(READ_ONCE(q->stat->cidx));
345 return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx;
349 * reclaim_completed_tx - reclaims completed TX Descriptors
351 * @q: the Tx queue to reclaim completed descriptors from
352 * @maxreclaim: the maximum number of TX Descriptors to reclaim or -1
353 * @unmap: whether the buffers should be unmapped for DMA
355 * Reclaims Tx Descriptors that the SGE has indicated it has processed,
356 * and frees the associated buffers if possible. If @max == -1, then
357 * we'll use a defaiult maximum. Called with the TX Queue locked.
359 static inline int reclaim_completed_tx(struct adapter *adap, struct sge_txq *q,
360 int maxreclaim, bool unmap)
362 int reclaim = reclaimable(q);
366 * Limit the amount of clean up work we do at a time to keep
367 * the Tx lock hold time O(1).
370 maxreclaim = MAX_TX_RECLAIM;
371 if (reclaim > maxreclaim)
372 reclaim = maxreclaim;
374 free_tx_desc(adap, q, reclaim, unmap);
375 q->in_use -= reclaim;
382 * cxgb4_reclaim_completed_tx - reclaims completed Tx descriptors
384 * @q: the Tx queue to reclaim completed descriptors from
385 * @unmap: whether the buffers should be unmapped for DMA
387 * Reclaims Tx descriptors that the SGE has indicated it has processed,
388 * and frees the associated buffers if possible. Called with the Tx
391 void cxgb4_reclaim_completed_tx(struct adapter *adap, struct sge_txq *q,
394 (void)reclaim_completed_tx(adap, q, -1, unmap);
396 EXPORT_SYMBOL(cxgb4_reclaim_completed_tx);
398 static inline int get_buf_size(struct adapter *adapter,
399 const struct rx_sw_desc *d)
401 struct sge *s = &adapter->sge;
402 unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE;
405 switch (rx_buf_size_idx) {
406 case RX_SMALL_PG_BUF:
407 buf_size = PAGE_SIZE;
410 case RX_LARGE_PG_BUF:
411 buf_size = PAGE_SIZE << s->fl_pg_order;
414 case RX_SMALL_MTU_BUF:
415 buf_size = FL_MTU_SMALL_BUFSIZE(adapter);
418 case RX_LARGE_MTU_BUF:
419 buf_size = FL_MTU_LARGE_BUFSIZE(adapter);
430 * free_rx_bufs - free the Rx buffers on an SGE free list
432 * @q: the SGE free list to free buffers from
433 * @n: how many buffers to free
435 * Release the next @n buffers on an SGE free-buffer Rx queue. The
436 * buffers must be made inaccessible to HW before calling this function.
438 static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n)
441 struct rx_sw_desc *d = &q->sdesc[q->cidx];
443 if (is_buf_mapped(d))
444 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
445 get_buf_size(adap, d),
449 if (++q->cidx == q->size)
456 * unmap_rx_buf - unmap the current Rx buffer on an SGE free list
458 * @q: the SGE free list
460 * Unmap the current buffer on an SGE free-buffer Rx queue. The
461 * buffer must be made inaccessible to HW before calling this function.
463 * This is similar to @free_rx_bufs above but does not free the buffer.
464 * Do note that the FL still loses any further access to the buffer.
466 static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q)
468 struct rx_sw_desc *d = &q->sdesc[q->cidx];
470 if (is_buf_mapped(d))
471 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
472 get_buf_size(adap, d), PCI_DMA_FROMDEVICE);
474 if (++q->cidx == q->size)
479 static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
481 if (q->pend_cred >= 8) {
482 u32 val = adap->params.arch.sge_fl_db;
484 if (is_t4(adap->params.chip))
485 val |= PIDX_V(q->pend_cred / 8);
487 val |= PIDX_T5_V(q->pend_cred / 8);
489 /* Make sure all memory writes to the Free List queue are
490 * committed before we tell the hardware about them.
494 /* If we don't have access to the new User Doorbell (T5+), use
495 * the old doorbell mechanism; otherwise use the new BAR2
498 if (unlikely(q->bar2_addr == NULL)) {
499 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
500 val | QID_V(q->cntxt_id));
502 writel(val | QID_V(q->bar2_qid),
503 q->bar2_addr + SGE_UDB_KDOORBELL);
505 /* This Write memory Barrier will force the write to
506 * the User Doorbell area to be flushed.
514 static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg,
518 sd->dma_addr = mapping; /* includes size low bits */
522 * refill_fl - refill an SGE Rx buffer ring
524 * @q: the ring to refill
525 * @n: the number of new buffers to allocate
526 * @gfp: the gfp flags for the allocations
528 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
529 * allocated with the supplied gfp flags. The caller must assure that
530 * @n does not exceed the queue's capacity. If afterwards the queue is
531 * found critically low mark it as starving in the bitmap of starving FLs.
533 * Returns the number of buffers allocated.
535 static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n,
538 struct sge *s = &adap->sge;
541 unsigned int cred = q->avail;
542 __be64 *d = &q->desc[q->pidx];
543 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
546 #ifdef CONFIG_DEBUG_FS
547 if (test_bit(q->cntxt_id - adap->sge.egr_start, adap->sge.blocked_fl))
552 node = dev_to_node(adap->pdev_dev);
554 if (s->fl_pg_order == 0)
555 goto alloc_small_pages;
558 * Prefer large buffers
561 pg = alloc_pages_node(node, gfp | __GFP_COMP, s->fl_pg_order);
563 q->large_alloc_failed++;
564 break; /* fall back to single pages */
567 mapping = dma_map_page(adap->pdev_dev, pg, 0,
568 PAGE_SIZE << s->fl_pg_order,
570 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
571 __free_pages(pg, s->fl_pg_order);
573 goto out; /* do not try small pages for this error */
575 mapping |= RX_LARGE_PG_BUF;
576 *d++ = cpu_to_be64(mapping);
578 set_rx_sw_desc(sd, pg, mapping);
582 if (++q->pidx == q->size) {
592 pg = alloc_pages_node(node, gfp, 0);
598 mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE,
600 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
605 *d++ = cpu_to_be64(mapping);
607 set_rx_sw_desc(sd, pg, mapping);
611 if (++q->pidx == q->size) {
618 out: cred = q->avail - cred;
619 q->pend_cred += cred;
622 if (unlikely(fl_starving(adap, q))) {
625 set_bit(q->cntxt_id - adap->sge.egr_start,
626 adap->sge.starving_fl);
632 static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
634 refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail),
639 * alloc_ring - allocate resources for an SGE descriptor ring
640 * @dev: the PCI device's core device
641 * @nelem: the number of descriptors
642 * @elem_size: the size of each descriptor
643 * @sw_size: the size of the SW state associated with each ring element
644 * @phys: the physical address of the allocated ring
645 * @metadata: address of the array holding the SW state for the ring
646 * @stat_size: extra space in HW ring for status information
647 * @node: preferred node for memory allocations
649 * Allocates resources for an SGE descriptor ring, such as Tx queues,
650 * free buffer lists, or response queues. Each SGE ring requires
651 * space for its HW descriptors plus, optionally, space for the SW state
652 * associated with each HW entry (the metadata). The function returns
653 * three values: the virtual address for the HW ring (the return value
654 * of the function), the bus address of the HW ring, and the address
657 static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size,
658 size_t sw_size, dma_addr_t *phys, void *metadata,
659 size_t stat_size, int node)
661 size_t len = nelem * elem_size + stat_size;
663 void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL);
668 s = kcalloc_node(sw_size, nelem, GFP_KERNEL, node);
671 dma_free_coherent(dev, len, p, *phys);
676 *(void **)metadata = s;
681 * sgl_len - calculates the size of an SGL of the given capacity
682 * @n: the number of SGL entries
684 * Calculates the number of flits needed for a scatter/gather list that
685 * can hold the given number of entries.
687 static inline unsigned int sgl_len(unsigned int n)
689 /* A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
690 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
691 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
692 * repeated sequences of { Length[i], Length[i+1], Address[i],
693 * Address[i+1] } (this ensures that all addresses are on 64-bit
694 * boundaries). If N is even, then Length[N+1] should be set to 0 and
695 * Address[N+1] is omitted.
697 * The following calculation incorporates all of the above. It's
698 * somewhat hard to follow but, briefly: the "+2" accounts for the
699 * first two flits which include the DSGL header, Length0 and
700 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
701 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
702 * finally the "+((n-1)&1)" adds the one remaining flit needed if
706 return (3 * n) / 2 + (n & 1) + 2;
710 * flits_to_desc - returns the num of Tx descriptors for the given flits
711 * @n: the number of flits
713 * Returns the number of Tx descriptors needed for the supplied number
716 static inline unsigned int flits_to_desc(unsigned int n)
718 BUG_ON(n > SGE_MAX_WR_LEN / 8);
719 return DIV_ROUND_UP(n, 8);
723 * is_eth_imm - can an Ethernet packet be sent as immediate data?
725 * @chip_ver: chip version
727 * Returns whether an Ethernet packet is small enough to fit as
728 * immediate data. Return value corresponds to headroom required.
730 static inline int is_eth_imm(const struct sk_buff *skb, unsigned int chip_ver)
734 if (skb->encapsulation && skb_shinfo(skb)->gso_size &&
735 chip_ver > CHELSIO_T5) {
736 hdrlen = sizeof(struct cpl_tx_tnl_lso);
737 hdrlen += sizeof(struct cpl_tx_pkt_core);
738 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
741 hdrlen = skb_shinfo(skb)->gso_size ?
742 sizeof(struct cpl_tx_pkt_lso_core) : 0;
743 hdrlen += sizeof(struct cpl_tx_pkt);
745 if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen)
751 * calc_tx_flits - calculate the number of flits for a packet Tx WR
753 * @chip_ver: chip version
755 * Returns the number of flits needed for a Tx WR for the given Ethernet
756 * packet, including the needed WR and CPL headers.
758 static inline unsigned int calc_tx_flits(const struct sk_buff *skb,
759 unsigned int chip_ver)
762 int hdrlen = is_eth_imm(skb, chip_ver);
764 /* If the skb is small enough, we can pump it out as a work request
765 * with only immediate data. In that case we just have to have the
766 * TX Packet header plus the skb data in the Work Request.
770 return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64));
772 /* Otherwise, we're going to have to construct a Scatter gather list
773 * of the skb body and fragments. We also include the flits necessary
774 * for the TX Packet Work Request and CPL. We always have a firmware
775 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
776 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
777 * message or, if we're doing a Large Send Offload, an LSO CPL message
778 * with an embedded TX Packet Write CPL message.
780 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
781 if (skb_shinfo(skb)->gso_size) {
782 if (skb->encapsulation && chip_ver > CHELSIO_T5) {
783 hdrlen = sizeof(struct fw_eth_tx_pkt_wr) +
784 sizeof(struct cpl_tx_tnl_lso);
785 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
788 pkt_hdrlen = eth_get_headlen(skb->dev, skb->data,
790 hdrlen = sizeof(struct fw_eth_tx_eo_wr) +
791 round_up(pkt_hdrlen, 16);
793 hdrlen = sizeof(struct fw_eth_tx_pkt_wr) +
794 sizeof(struct cpl_tx_pkt_lso_core);
797 hdrlen += sizeof(struct cpl_tx_pkt_core);
798 flits += (hdrlen / sizeof(__be64));
800 flits += (sizeof(struct fw_eth_tx_pkt_wr) +
801 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
807 * calc_tx_descs - calculate the number of Tx descriptors for a packet
809 * @chip_ver: chip version
811 * Returns the number of Tx descriptors needed for the given Ethernet
812 * packet, including the needed WR and CPL headers.
814 static inline unsigned int calc_tx_descs(const struct sk_buff *skb,
815 unsigned int chip_ver)
817 return flits_to_desc(calc_tx_flits(skb, chip_ver));
821 * cxgb4_write_sgl - populate a scatter/gather list for a packet
823 * @q: the Tx queue we are writing into
824 * @sgl: starting location for writing the SGL
825 * @end: points right after the end of the SGL
826 * @start: start offset into skb main-body data to include in the SGL
827 * @addr: the list of bus addresses for the SGL elements
829 * Generates a gather list for the buffers that make up a packet.
830 * The caller must provide adequate space for the SGL that will be written.
831 * The SGL includes all of the packet's page fragments and the data in its
832 * main body except for the first @start bytes. @sgl must be 16-byte
833 * aligned and within a Tx descriptor with available space. @end points
834 * right after the end of the SGL but does not account for any potential
835 * wrap around, i.e., @end > @sgl.
837 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
838 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
839 const dma_addr_t *addr)
842 struct ulptx_sge_pair *to;
843 const struct skb_shared_info *si = skb_shinfo(skb);
844 unsigned int nfrags = si->nr_frags;
845 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
847 len = skb_headlen(skb) - start;
849 sgl->len0 = htonl(len);
850 sgl->addr0 = cpu_to_be64(addr[0] + start);
853 sgl->len0 = htonl(skb_frag_size(&si->frags[0]));
854 sgl->addr0 = cpu_to_be64(addr[1]);
857 sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
858 ULPTX_NSGE_V(nfrags));
859 if (likely(--nfrags == 0))
862 * Most of the complexity below deals with the possibility we hit the
863 * end of the queue in the middle of writing the SGL. For this case
864 * only we create the SGL in a temporary buffer and then copy it.
866 to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge;
868 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
869 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
870 to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i]));
871 to->addr[0] = cpu_to_be64(addr[i]);
872 to->addr[1] = cpu_to_be64(addr[++i]);
875 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
876 to->len[1] = cpu_to_be32(0);
877 to->addr[0] = cpu_to_be64(addr[i + 1]);
879 if (unlikely((u8 *)end > (u8 *)q->stat)) {
880 unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1;
883 memcpy(sgl->sge, buf, part0);
884 part1 = (u8 *)end - (u8 *)q->stat;
885 memcpy(q->desc, (u8 *)buf + part0, part1);
886 end = (void *)q->desc + part1;
888 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
891 EXPORT_SYMBOL(cxgb4_write_sgl);
893 /* This function copies 64 byte coalesced work request to
894 * memory mapped BAR2 space. For coalesced WR SGE fetches
895 * data from the FIFO instead of from Host.
897 static void cxgb_pio_copy(u64 __iomem *dst, u64 *src)
910 * cxgb4_ring_tx_db - check and potentially ring a Tx queue's doorbell
913 * @n: number of new descriptors to give to HW
915 * Ring the doorbel for a Tx queue.
917 inline void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
919 /* Make sure that all writes to the TX Descriptors are committed
920 * before we tell the hardware about them.
924 /* If we don't have access to the new User Doorbell (T5+), use the old
925 * doorbell mechanism; otherwise use the new BAR2 mechanism.
927 if (unlikely(q->bar2_addr == NULL)) {
931 /* For T4 we need to participate in the Doorbell Recovery
934 spin_lock_irqsave(&q->db_lock, flags);
936 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
937 QID_V(q->cntxt_id) | val);
940 q->db_pidx = q->pidx;
941 spin_unlock_irqrestore(&q->db_lock, flags);
943 u32 val = PIDX_T5_V(n);
945 /* T4 and later chips share the same PIDX field offset within
946 * the doorbell, but T5 and later shrank the field in order to
947 * gain a bit for Doorbell Priority. The field was absurdly
948 * large in the first place (14 bits) so we just use the T5
949 * and later limits and warn if a Queue ID is too large.
951 WARN_ON(val & DBPRIO_F);
953 /* If we're only writing a single TX Descriptor and we can use
954 * Inferred QID registers, we can use the Write Combining
955 * Gather Buffer; otherwise we use the simple doorbell.
957 if (n == 1 && q->bar2_qid == 0) {
961 u64 *wr = (u64 *)&q->desc[index];
963 cxgb_pio_copy((u64 __iomem *)
964 (q->bar2_addr + SGE_UDB_WCDOORBELL),
967 writel(val | QID_V(q->bar2_qid),
968 q->bar2_addr + SGE_UDB_KDOORBELL);
971 /* This Write Memory Barrier will force the write to the User
972 * Doorbell area to be flushed. This is needed to prevent
973 * writes on different CPUs for the same queue from hitting
974 * the adapter out of order. This is required when some Work
975 * Requests take the Write Combine Gather Buffer path (user
976 * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some
977 * take the traditional path where we simply increment the
978 * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the
979 * hardware DMA read the actual Work Request.
984 EXPORT_SYMBOL(cxgb4_ring_tx_db);
987 * cxgb4_inline_tx_skb - inline a packet's data into Tx descriptors
989 * @q: the Tx queue where the packet will be inlined
990 * @pos: starting position in the Tx queue where to inline the packet
992 * Inline a packet's contents directly into Tx descriptors, starting at
993 * the given position within the Tx DMA ring.
994 * Most of the complexity of this operation is dealing with wrap arounds
995 * in the middle of the packet we want to inline.
997 void cxgb4_inline_tx_skb(const struct sk_buff *skb,
998 const struct sge_txq *q, void *pos)
1000 int left = (void *)q->stat - pos;
1003 if (likely(skb->len <= left)) {
1004 if (likely(!skb->data_len))
1005 skb_copy_from_linear_data(skb, pos, skb->len);
1007 skb_copy_bits(skb, 0, pos, skb->len);
1010 skb_copy_bits(skb, 0, pos, left);
1011 skb_copy_bits(skb, left, q->desc, skb->len - left);
1012 pos = (void *)q->desc + (skb->len - left);
1015 /* 0-pad to multiple of 16 */
1016 p = PTR_ALIGN(pos, 8);
1017 if ((uintptr_t)p & 8)
1020 EXPORT_SYMBOL(cxgb4_inline_tx_skb);
1022 static void *inline_tx_skb_header(const struct sk_buff *skb,
1023 const struct sge_txq *q, void *pos,
1027 int left = (void *)q->stat - pos;
1029 if (likely(length <= left)) {
1030 memcpy(pos, skb->data, length);
1033 memcpy(pos, skb->data, left);
1034 memcpy(q->desc, skb->data + left, length - left);
1035 pos = (void *)q->desc + (length - left);
1037 /* 0-pad to multiple of 16 */
1038 p = PTR_ALIGN(pos, 8);
1039 if ((uintptr_t)p & 8) {
1047 * Figure out what HW csum a packet wants and return the appropriate control
1050 static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb)
1053 bool inner_hdr_csum = false;
1056 if (skb->encapsulation &&
1057 (CHELSIO_CHIP_VERSION(chip) > CHELSIO_T5))
1058 inner_hdr_csum = true;
1060 if (inner_hdr_csum) {
1061 ver = inner_ip_hdr(skb)->version;
1062 proto = (ver == 4) ? inner_ip_hdr(skb)->protocol :
1063 inner_ipv6_hdr(skb)->nexthdr;
1065 ver = ip_hdr(skb)->version;
1066 proto = (ver == 4) ? ip_hdr(skb)->protocol :
1067 ipv6_hdr(skb)->nexthdr;
1071 if (proto == IPPROTO_TCP)
1072 csum_type = TX_CSUM_TCPIP;
1073 else if (proto == IPPROTO_UDP)
1074 csum_type = TX_CSUM_UDPIP;
1077 * unknown protocol, disable HW csum
1078 * and hope a bad packet is detected
1080 return TXPKT_L4CSUM_DIS_F;
1084 * this doesn't work with extension headers
1086 if (proto == IPPROTO_TCP)
1087 csum_type = TX_CSUM_TCPIP6;
1088 else if (proto == IPPROTO_UDP)
1089 csum_type = TX_CSUM_UDPIP6;
1094 if (likely(csum_type >= TX_CSUM_TCPIP)) {
1095 int eth_hdr_len, l4_len;
1098 if (inner_hdr_csum) {
1099 /* This allows checksum offload for all encapsulated
1100 * packets like GRE etc..
1102 l4_len = skb_inner_network_header_len(skb);
1103 eth_hdr_len = skb_inner_network_offset(skb) - ETH_HLEN;
1105 l4_len = skb_network_header_len(skb);
1106 eth_hdr_len = skb_network_offset(skb) - ETH_HLEN;
1108 hdr_len = TXPKT_IPHDR_LEN_V(l4_len);
1110 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1111 hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1113 hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1114 return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len;
1116 int start = skb_transport_offset(skb);
1118 return TXPKT_CSUM_TYPE_V(csum_type) |
1119 TXPKT_CSUM_START_V(start) |
1120 TXPKT_CSUM_LOC_V(start + skb->csum_offset);
1124 static void eth_txq_stop(struct sge_eth_txq *q)
1126 netif_tx_stop_queue(q->txq);
1130 static inline void txq_advance(struct sge_txq *q, unsigned int n)
1134 if (q->pidx >= q->size)
1138 #ifdef CONFIG_CHELSIO_T4_FCOE
1140 cxgb_fcoe_offload(struct sk_buff *skb, struct adapter *adap,
1141 const struct port_info *pi, u64 *cntrl)
1143 const struct cxgb_fcoe *fcoe = &pi->fcoe;
1145 if (!(fcoe->flags & CXGB_FCOE_ENABLED))
1148 if (skb->protocol != htons(ETH_P_FCOE))
1151 skb_reset_mac_header(skb);
1152 skb->mac_len = sizeof(struct ethhdr);
1154 skb_set_network_header(skb, skb->mac_len);
1155 skb_set_transport_header(skb, skb->mac_len + sizeof(struct fcoe_hdr));
1157 if (!cxgb_fcoe_sof_eof_supported(adap, skb))
1160 /* FC CRC offload */
1161 *cntrl = TXPKT_CSUM_TYPE_V(TX_CSUM_FCOE) |
1162 TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F |
1163 TXPKT_CSUM_START_V(CXGB_FCOE_TXPKT_CSUM_START) |
1164 TXPKT_CSUM_END_V(CXGB_FCOE_TXPKT_CSUM_END) |
1165 TXPKT_CSUM_LOC_V(CXGB_FCOE_TXPKT_CSUM_END);
1168 #endif /* CONFIG_CHELSIO_T4_FCOE */
1170 /* Returns tunnel type if hardware supports offloading of the same.
1171 * It is called only for T5 and onwards.
1173 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb)
1176 enum cpl_tx_tnl_lso_type tnl_type = TX_TNL_TYPE_OPAQUE;
1177 struct port_info *pi = netdev_priv(skb->dev);
1178 struct adapter *adapter = pi->adapter;
1180 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1181 skb->inner_protocol != htons(ETH_P_TEB))
1184 switch (vlan_get_protocol(skb)) {
1185 case htons(ETH_P_IP):
1186 l4_hdr = ip_hdr(skb)->protocol;
1188 case htons(ETH_P_IPV6):
1189 l4_hdr = ipv6_hdr(skb)->nexthdr;
1197 if (adapter->vxlan_port == udp_hdr(skb)->dest)
1198 tnl_type = TX_TNL_TYPE_VXLAN;
1199 else if (adapter->geneve_port == udp_hdr(skb)->dest)
1200 tnl_type = TX_TNL_TYPE_GENEVE;
1209 static inline void t6_fill_tnl_lso(struct sk_buff *skb,
1210 struct cpl_tx_tnl_lso *tnl_lso,
1211 enum cpl_tx_tnl_lso_type tnl_type)
1214 int in_eth_xtra_len;
1215 int l3hdr_len = skb_network_header_len(skb);
1216 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1217 const struct skb_shared_info *ssi = skb_shinfo(skb);
1218 bool v6 = (ip_hdr(skb)->version == 6);
1220 val = CPL_TX_TNL_LSO_OPCODE_V(CPL_TX_TNL_LSO) |
1221 CPL_TX_TNL_LSO_FIRST_F |
1222 CPL_TX_TNL_LSO_LAST_F |
1223 (v6 ? CPL_TX_TNL_LSO_IPV6OUT_F : 0) |
1224 CPL_TX_TNL_LSO_ETHHDRLENOUT_V(eth_xtra_len / 4) |
1225 CPL_TX_TNL_LSO_IPHDRLENOUT_V(l3hdr_len / 4) |
1226 (v6 ? 0 : CPL_TX_TNL_LSO_IPHDRCHKOUT_F) |
1227 CPL_TX_TNL_LSO_IPLENSETOUT_F |
1228 (v6 ? 0 : CPL_TX_TNL_LSO_IPIDINCOUT_F);
1229 tnl_lso->op_to_IpIdSplitOut = htonl(val);
1231 tnl_lso->IpIdOffsetOut = 0;
1233 /* Get the tunnel header length */
1234 val = skb_inner_mac_header(skb) - skb_mac_header(skb);
1235 in_eth_xtra_len = skb_inner_network_header(skb) -
1236 skb_inner_mac_header(skb) - ETH_HLEN;
1239 case TX_TNL_TYPE_VXLAN:
1240 case TX_TNL_TYPE_GENEVE:
1241 tnl_lso->UdpLenSetOut_to_TnlHdrLen =
1242 htons(CPL_TX_TNL_LSO_UDPCHKCLROUT_F |
1243 CPL_TX_TNL_LSO_UDPLENSETOUT_F);
1246 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 0;
1250 tnl_lso->UdpLenSetOut_to_TnlHdrLen |=
1251 htons(CPL_TX_TNL_LSO_TNLHDRLEN_V(val) |
1252 CPL_TX_TNL_LSO_TNLTYPE_V(tnl_type));
1256 val = CPL_TX_TNL_LSO_ETHHDRLEN_V(in_eth_xtra_len / 4) |
1257 CPL_TX_TNL_LSO_IPV6_V(inner_ip_hdr(skb)->version == 6) |
1258 CPL_TX_TNL_LSO_IPHDRLEN_V(skb_inner_network_header_len(skb) / 4) |
1259 CPL_TX_TNL_LSO_TCPHDRLEN_V(inner_tcp_hdrlen(skb) / 4);
1260 tnl_lso->Flow_to_TcpHdrLen = htonl(val);
1262 tnl_lso->IpIdOffset = htons(0);
1264 tnl_lso->IpIdSplit_to_Mss = htons(CPL_TX_TNL_LSO_MSS_V(ssi->gso_size));
1265 tnl_lso->TCPSeqOffset = htonl(0);
1266 tnl_lso->EthLenOffset_Size = htonl(CPL_TX_TNL_LSO_SIZE_V(skb->len));
1269 static inline void *write_tso_wr(struct adapter *adap, struct sk_buff *skb,
1270 struct cpl_tx_pkt_lso_core *lso)
1272 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1273 int l3hdr_len = skb_network_header_len(skb);
1274 const struct skb_shared_info *ssi;
1277 ssi = skb_shinfo(skb);
1278 if (ssi->gso_type & SKB_GSO_TCPV6)
1281 lso->lso_ctrl = htonl(LSO_OPCODE_V(CPL_TX_PKT_LSO) |
1282 LSO_FIRST_SLICE_F | LSO_LAST_SLICE_F |
1284 LSO_ETHHDR_LEN_V(eth_xtra_len / 4) |
1285 LSO_IPHDR_LEN_V(l3hdr_len / 4) |
1286 LSO_TCPHDR_LEN_V(tcp_hdr(skb)->doff));
1287 lso->ipid_ofst = htons(0);
1288 lso->mss = htons(ssi->gso_size);
1289 lso->seqno_offset = htonl(0);
1290 if (is_t4(adap->params.chip))
1291 lso->len = htonl(skb->len);
1293 lso->len = htonl(LSO_T5_XFER_SIZE_V(skb->len));
1295 return (void *)(lso + 1);
1299 * t4_sge_eth_txq_egress_update - handle Ethernet TX Queue update
1300 * @adap: the adapter
1301 * @eq: the Ethernet TX Queue
1302 * @maxreclaim: the maximum number of TX Descriptors to reclaim or -1
1304 * We're typically called here to update the state of an Ethernet TX
1305 * Queue with respect to the hardware's progress in consuming the TX
1306 * Work Requests that we've put on that Egress Queue. This happens
1307 * when we get Egress Queue Update messages and also prophylactically
1308 * in regular timer-based Ethernet TX Queue maintenance.
1310 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *eq,
1313 unsigned int reclaimed, hw_cidx;
1314 struct sge_txq *q = &eq->q;
1317 if (!q->in_use || !__netif_tx_trylock(eq->txq))
1320 /* Reclaim pending completed TX Descriptors. */
1321 reclaimed = reclaim_completed_tx(adap, &eq->q, maxreclaim, true);
1323 hw_cidx = ntohs(READ_ONCE(q->stat->cidx));
1324 hw_in_use = q->pidx - hw_cidx;
1326 hw_in_use += q->size;
1328 /* If the TX Queue is currently stopped and there's now more than half
1329 * the queue available, restart it. Otherwise bail out since the rest
1330 * of what we want do here is with the possibility of shipping any
1331 * currently buffered Coalesced TX Work Request.
1333 if (netif_tx_queue_stopped(eq->txq) && hw_in_use < (q->size / 2)) {
1334 netif_tx_wake_queue(eq->txq);
1338 __netif_tx_unlock(eq->txq);
1342 static inline int cxgb4_validate_skb(struct sk_buff *skb,
1343 struct net_device *dev,
1348 /* The chip min packet length is 10 octets but some firmware
1349 * commands have a minimum packet length requirement. So, play
1350 * safe and reject anything shorter than @min_pkt_len.
1352 if (unlikely(skb->len < min_pkt_len))
1355 /* Discard the packet if the length is greater than mtu */
1356 max_pkt_len = ETH_HLEN + dev->mtu;
1358 if (skb_vlan_tagged(skb))
1359 max_pkt_len += VLAN_HLEN;
1361 if (!skb_shinfo(skb)->gso_size && (unlikely(skb->len > max_pkt_len)))
1367 static void *write_eo_udp_wr(struct sk_buff *skb, struct fw_eth_tx_eo_wr *wr,
1370 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
1371 wr->u.udpseg.ethlen = skb_network_offset(skb);
1372 wr->u.udpseg.iplen = cpu_to_be16(skb_network_header_len(skb));
1373 wr->u.udpseg.udplen = sizeof(struct udphdr);
1374 wr->u.udpseg.rtplen = 0;
1375 wr->u.udpseg.r4 = 0;
1376 if (skb_shinfo(skb)->gso_size)
1377 wr->u.udpseg.mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
1379 wr->u.udpseg.mss = cpu_to_be16(skb->len - hdr_len);
1380 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
1381 wr->u.udpseg.plen = cpu_to_be32(skb->len - hdr_len);
1383 return (void *)(wr + 1);
1387 * cxgb4_eth_xmit - add a packet to an Ethernet Tx queue
1389 * @dev: the egress net device
1391 * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled.
1393 static netdev_tx_t cxgb4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1395 enum cpl_tx_tnl_lso_type tnl_type = TX_TNL_TYPE_OPAQUE;
1396 bool ptp_enabled = is_ptp_enabled(skb, dev);
1397 unsigned int last_desc, flits, ndesc;
1398 u32 wr_mid, ctrl0, op, sgl_off = 0;
1399 const struct skb_shared_info *ssi;
1400 int len, qidx, credits, ret, left;
1401 struct tx_sw_desc *sgl_sdesc;
1402 struct fw_eth_tx_eo_wr *eowr;
1403 struct fw_eth_tx_pkt_wr *wr;
1404 struct cpl_tx_pkt_core *cpl;
1405 const struct port_info *pi;
1406 bool immediate = false;
1407 u64 cntrl, *end, *sgl;
1408 struct sge_eth_txq *q;
1409 unsigned int chip_ver;
1410 struct adapter *adap;
1412 ret = cxgb4_validate_skb(skb, dev, ETH_HLEN);
1416 pi = netdev_priv(dev);
1418 ssi = skb_shinfo(skb);
1419 #if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE)
1420 if (xfrm_offload(skb) && !ssi->gso_size)
1421 return adap->uld[CXGB4_ULD_IPSEC].tx_handler(skb, dev);
1422 #endif /* CHELSIO_IPSEC_INLINE */
1424 #if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
1425 if (cxgb4_is_ktls_skb(skb) &&
1426 (skb->len - (skb_transport_offset(skb) + tcp_hdrlen(skb))))
1427 return adap->uld[CXGB4_ULD_KTLS].tx_handler(skb, dev);
1428 #endif /* CHELSIO_TLS_DEVICE */
1430 qidx = skb_get_queue_mapping(skb);
1432 if (!(adap->ptp_tx_skb)) {
1433 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1434 adap->ptp_tx_skb = skb_get(skb);
1438 q = &adap->sge.ptptxq;
1440 q = &adap->sge.ethtxq[qidx + pi->first_qset];
1442 skb_tx_timestamp(skb);
1444 reclaim_completed_tx(adap, &q->q, -1, true);
1445 cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
1447 #ifdef CONFIG_CHELSIO_T4_FCOE
1448 ret = cxgb_fcoe_offload(skb, adap, pi, &cntrl);
1449 if (unlikely(ret == -EOPNOTSUPP))
1451 #endif /* CONFIG_CHELSIO_T4_FCOE */
1453 chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
1454 flits = calc_tx_flits(skb, chip_ver);
1455 ndesc = flits_to_desc(flits);
1456 credits = txq_avail(&q->q) - ndesc;
1458 if (unlikely(credits < 0)) {
1460 dev_err(adap->pdev_dev,
1461 "%s: Tx ring %u full while queue awake!\n",
1463 return NETDEV_TX_BUSY;
1466 if (is_eth_imm(skb, chip_ver))
1469 if (skb->encapsulation && chip_ver > CHELSIO_T5)
1470 tnl_type = cxgb_encap_offload_supported(skb);
1472 last_desc = q->q.pidx + ndesc - 1;
1473 if (last_desc >= q->q.size)
1474 last_desc -= q->q.size;
1475 sgl_sdesc = &q->q.sdesc[last_desc];
1478 unlikely(cxgb4_map_skb(adap->pdev_dev, skb, sgl_sdesc->addr) < 0)) {
1479 memset(sgl_sdesc->addr, 0, sizeof(sgl_sdesc->addr));
1484 wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
1485 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1486 /* After we're done injecting the Work Request for this
1487 * packet, we'll be below our "stop threshold" so stop the TX
1488 * Queue now and schedule a request for an SGE Egress Queue
1489 * Update message. The queue will get started later on when
1490 * the firmware processes this Work Request and sends us an
1491 * Egress Queue Status Update message indicating that space
1495 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
1498 wr = (void *)&q->q.desc[q->q.pidx];
1499 eowr = (void *)&q->q.desc[q->q.pidx];
1500 wr->equiq_to_len16 = htonl(wr_mid);
1501 wr->r3 = cpu_to_be64(0);
1502 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)
1503 end = (u64 *)eowr + flits;
1505 end = (u64 *)wr + flits;
1507 len = immediate ? skb->len : 0;
1508 len += sizeof(*cpl);
1509 if (ssi->gso_size && !(ssi->gso_type & SKB_GSO_UDP_L4)) {
1510 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
1511 struct cpl_tx_tnl_lso *tnl_lso = (void *)(wr + 1);
1514 len += sizeof(*tnl_lso);
1516 len += sizeof(*lso);
1518 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
1519 FW_WR_IMMDLEN_V(len));
1521 struct iphdr *iph = ip_hdr(skb);
1523 t6_fill_tnl_lso(skb, tnl_lso, tnl_type);
1524 cpl = (void *)(tnl_lso + 1);
1525 /* Driver is expected to compute partial checksum that
1526 * does not include the IP Total Length.
1528 if (iph->version == 4) {
1531 iph->check = ~ip_fast_csum((u8 *)iph, iph->ihl);
1533 if (skb->ip_summed == CHECKSUM_PARTIAL)
1534 cntrl = hwcsum(adap->params.chip, skb);
1536 cpl = write_tso_wr(adap, skb, lso);
1537 cntrl = hwcsum(adap->params.chip, skb);
1539 sgl = (u64 *)(cpl + 1); /* sgl start here */
1541 q->tx_cso += ssi->gso_segs;
1542 } else if (ssi->gso_size) {
1546 hdrlen = eth_get_headlen(dev, skb->data, skb_headlen(skb));
1548 wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_EO_WR) |
1549 FW_ETH_TX_EO_WR_IMMDLEN_V(len));
1550 cpl = write_eo_udp_wr(skb, eowr, hdrlen);
1551 cntrl = hwcsum(adap->params.chip, skb);
1553 start = (u64 *)(cpl + 1);
1554 sgl = (u64 *)inline_tx_skb_header(skb, &q->q, (void *)start,
1556 if (unlikely(start > sgl)) {
1557 left = (u8 *)end - (u8 *)q->q.stat;
1558 end = (void *)q->q.desc + left;
1562 q->tx_cso += ssi->gso_segs;
1565 op = FW_PTP_TX_PKT_WR;
1567 op = FW_ETH_TX_PKT_WR;
1568 wr->op_immdlen = htonl(FW_WR_OP_V(op) |
1569 FW_WR_IMMDLEN_V(len));
1570 cpl = (void *)(wr + 1);
1571 sgl = (u64 *)(cpl + 1);
1572 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1573 cntrl = hwcsum(adap->params.chip, skb) |
1579 if (unlikely((u8 *)sgl >= (u8 *)q->q.stat)) {
1580 /* If current position is already at the end of the
1581 * txq, reset the current to point to start of the queue
1582 * and update the end ptr as well.
1584 left = (u8 *)end - (u8 *)q->q.stat;
1585 end = (void *)q->q.desc + left;
1586 sgl = (void *)q->q.desc;
1589 if (skb_vlan_tag_present(skb)) {
1591 cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb));
1592 #ifdef CONFIG_CHELSIO_T4_FCOE
1593 if (skb->protocol == htons(ETH_P_FCOE))
1594 cntrl |= TXPKT_VLAN_V(
1595 ((skb->priority & 0x7) << VLAN_PRIO_SHIFT));
1596 #endif /* CONFIG_CHELSIO_T4_FCOE */
1599 ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) |
1600 TXPKT_PF_V(adap->pf);
1602 ctrl0 |= TXPKT_TSTAMP_F;
1603 #ifdef CONFIG_CHELSIO_T4_DCB
1604 if (is_t4(adap->params.chip))
1605 ctrl0 |= TXPKT_OVLAN_IDX_V(q->dcb_prio);
1607 ctrl0 |= TXPKT_T5_OVLAN_IDX_V(q->dcb_prio);
1609 cpl->ctrl0 = htonl(ctrl0);
1610 cpl->pack = htons(0);
1611 cpl->len = htons(skb->len);
1612 cpl->ctrl1 = cpu_to_be64(cntrl);
1615 cxgb4_inline_tx_skb(skb, &q->q, sgl);
1616 dev_consume_skb_any(skb);
1618 cxgb4_write_sgl(skb, &q->q, (void *)sgl, end, sgl_off,
1621 sgl_sdesc->skb = skb;
1624 txq_advance(&q->q, ndesc);
1626 cxgb4_ring_tx_db(adap, &q->q, ndesc);
1627 return NETDEV_TX_OK;
1630 dev_kfree_skb_any(skb);
1631 return NETDEV_TX_OK;
1636 /* Egress Queue sizes, producer and consumer indices are all in units
1637 * of Egress Context Units bytes. Note that as far as the hardware is
1638 * concerned, the free list is an Egress Queue (the host produces free
1639 * buffers which the hardware consumes) and free list entries are
1640 * 64-bit PCI DMA addresses.
1642 EQ_UNIT = SGE_EQ_IDXSIZE,
1643 FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
1644 TXD_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
1646 T4VF_ETHTXQ_MAX_HDR = (sizeof(struct fw_eth_tx_pkt_vm_wr) +
1647 sizeof(struct cpl_tx_pkt_lso_core) +
1648 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64),
1652 * t4vf_is_eth_imm - can an Ethernet packet be sent as immediate data?
1655 * Returns whether an Ethernet packet is small enough to fit completely as
1658 static inline int t4vf_is_eth_imm(const struct sk_buff *skb)
1660 /* The VF Driver uses the FW_ETH_TX_PKT_VM_WR firmware Work Request
1661 * which does not accommodate immediate data. We could dike out all
1662 * of the support code for immediate data but that would tie our hands
1663 * too much if we ever want to enhace the firmware. It would also
1664 * create more differences between the PF and VF Drivers.
1670 * t4vf_calc_tx_flits - calculate the number of flits for a packet TX WR
1673 * Returns the number of flits needed for a TX Work Request for the
1674 * given Ethernet packet, including the needed WR and CPL headers.
1676 static inline unsigned int t4vf_calc_tx_flits(const struct sk_buff *skb)
1680 /* If the skb is small enough, we can pump it out as a work request
1681 * with only immediate data. In that case we just have to have the
1682 * TX Packet header plus the skb data in the Work Request.
1684 if (t4vf_is_eth_imm(skb))
1685 return DIV_ROUND_UP(skb->len + sizeof(struct cpl_tx_pkt),
1688 /* Otherwise, we're going to have to construct a Scatter gather list
1689 * of the skb body and fragments. We also include the flits necessary
1690 * for the TX Packet Work Request and CPL. We always have a firmware
1691 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
1692 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
1693 * message or, if we're doing a Large Send Offload, an LSO CPL message
1694 * with an embedded TX Packet Write CPL message.
1696 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
1697 if (skb_shinfo(skb)->gso_size)
1698 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
1699 sizeof(struct cpl_tx_pkt_lso_core) +
1700 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
1702 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
1703 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
1708 * cxgb4_vf_eth_xmit - add a packet to an Ethernet TX queue
1710 * @dev: the egress net device
1712 * Add a packet to an SGE Ethernet TX queue. Runs with softirqs disabled.
1714 static netdev_tx_t cxgb4_vf_eth_xmit(struct sk_buff *skb,
1715 struct net_device *dev)
1717 unsigned int last_desc, flits, ndesc;
1718 const struct skb_shared_info *ssi;
1719 struct fw_eth_tx_pkt_vm_wr *wr;
1720 struct tx_sw_desc *sgl_sdesc;
1721 struct cpl_tx_pkt_core *cpl;
1722 const struct port_info *pi;
1723 struct sge_eth_txq *txq;
1724 struct adapter *adapter;
1725 int qidx, credits, ret;
1726 size_t fw_hdr_copy_len;
1730 /* The chip minimum packet length is 10 octets but the firmware
1731 * command that we are using requires that we copy the Ethernet header
1732 * (including the VLAN tag) into the header so we reject anything
1733 * smaller than that ...
1735 fw_hdr_copy_len = sizeof(wr->ethmacdst) + sizeof(wr->ethmacsrc) +
1736 sizeof(wr->ethtype) + sizeof(wr->vlantci);
1737 ret = cxgb4_validate_skb(skb, dev, fw_hdr_copy_len);
1741 /* Figure out which TX Queue we're going to use. */
1742 pi = netdev_priv(dev);
1743 adapter = pi->adapter;
1744 qidx = skb_get_queue_mapping(skb);
1745 WARN_ON(qidx >= pi->nqsets);
1746 txq = &adapter->sge.ethtxq[pi->first_qset + qidx];
1748 /* Take this opportunity to reclaim any TX Descriptors whose DMA
1749 * transfers have completed.
1751 reclaim_completed_tx(adapter, &txq->q, -1, true);
1753 /* Calculate the number of flits and TX Descriptors we're going to
1754 * need along with how many TX Descriptors will be left over after
1755 * we inject our Work Request.
1757 flits = t4vf_calc_tx_flits(skb);
1758 ndesc = flits_to_desc(flits);
1759 credits = txq_avail(&txq->q) - ndesc;
1761 if (unlikely(credits < 0)) {
1762 /* Not enough room for this packet's Work Request. Stop the
1763 * TX Queue and return a "busy" condition. The queue will get
1764 * started later on when the firmware informs us that space
1768 dev_err(adapter->pdev_dev,
1769 "%s: TX ring %u full while queue awake!\n",
1771 return NETDEV_TX_BUSY;
1774 last_desc = txq->q.pidx + ndesc - 1;
1775 if (last_desc >= txq->q.size)
1776 last_desc -= txq->q.size;
1777 sgl_sdesc = &txq->q.sdesc[last_desc];
1779 if (!t4vf_is_eth_imm(skb) &&
1780 unlikely(cxgb4_map_skb(adapter->pdev_dev, skb,
1781 sgl_sdesc->addr) < 0)) {
1782 /* We need to map the skb into PCI DMA space (because it can't
1783 * be in-lined directly into the Work Request) and the mapping
1784 * operation failed. Record the error and drop the packet.
1786 memset(sgl_sdesc->addr, 0, sizeof(sgl_sdesc->addr));
1791 wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
1792 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1793 /* After we're done injecting the Work Request for this
1794 * packet, we'll be below our "stop threshold" so stop the TX
1795 * Queue now and schedule a request for an SGE Egress Queue
1796 * Update message. The queue will get started later on when
1797 * the firmware processes this Work Request and sends us an
1798 * Egress Queue Status Update message indicating that space
1802 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
1805 /* Start filling in our Work Request. Note that we do _not_ handle
1806 * the WR Header wrapping around the TX Descriptor Ring. If our
1807 * maximum header size ever exceeds one TX Descriptor, we'll need to
1808 * do something else here.
1810 WARN_ON(DIV_ROUND_UP(T4VF_ETHTXQ_MAX_HDR, TXD_PER_EQ_UNIT) > 1);
1811 wr = (void *)&txq->q.desc[txq->q.pidx];
1812 wr->equiq_to_len16 = cpu_to_be32(wr_mid);
1813 wr->r3[0] = cpu_to_be32(0);
1814 wr->r3[1] = cpu_to_be32(0);
1815 skb_copy_from_linear_data(skb, (void *)wr->ethmacdst, fw_hdr_copy_len);
1816 end = (u64 *)wr + flits;
1818 /* If this is a Large Send Offload packet we'll put in an LSO CPL
1819 * message with an encapsulated TX Packet CPL message. Otherwise we
1820 * just use a TX Packet CPL message.
1822 ssi = skb_shinfo(skb);
1823 if (ssi->gso_size) {
1824 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
1825 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1826 int l3hdr_len = skb_network_header_len(skb);
1827 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1830 cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_PKT_VM_WR) |
1831 FW_WR_IMMDLEN_V(sizeof(*lso) +
1833 /* Fill in the LSO CPL message. */
1835 cpu_to_be32(LSO_OPCODE_V(CPL_TX_PKT_LSO) |
1839 LSO_ETHHDR_LEN_V(eth_xtra_len / 4) |
1840 LSO_IPHDR_LEN_V(l3hdr_len / 4) |
1841 LSO_TCPHDR_LEN_V(tcp_hdr(skb)->doff));
1842 lso->ipid_ofst = cpu_to_be16(0);
1843 lso->mss = cpu_to_be16(ssi->gso_size);
1844 lso->seqno_offset = cpu_to_be32(0);
1845 if (is_t4(adapter->params.chip))
1846 lso->len = cpu_to_be32(skb->len);
1848 lso->len = cpu_to_be32(LSO_T5_XFER_SIZE_V(skb->len));
1850 /* Set up TX Packet CPL pointer, control word and perform
1853 cpl = (void *)(lso + 1);
1855 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
1856 cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1858 cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1860 cntrl |= TXPKT_CSUM_TYPE_V(v6 ?
1861 TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1862 TXPKT_IPHDR_LEN_V(l3hdr_len);
1864 txq->tx_cso += ssi->gso_segs;
1868 len = (t4vf_is_eth_imm(skb)
1869 ? skb->len + sizeof(*cpl)
1872 cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_PKT_VM_WR) |
1873 FW_WR_IMMDLEN_V(len));
1875 /* Set up TX Packet CPL pointer, control word and perform
1878 cpl = (void *)(wr + 1);
1879 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1880 cntrl = hwcsum(adapter->params.chip, skb) |
1884 cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
1888 /* If there's a VLAN tag present, add that to the list of things to
1889 * do in this Work Request.
1891 if (skb_vlan_tag_present(skb)) {
1893 cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb));
1896 /* Fill in the TX Packet CPL message header. */
1897 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) |
1898 TXPKT_INTF_V(pi->port_id) |
1900 cpl->pack = cpu_to_be16(0);
1901 cpl->len = cpu_to_be16(skb->len);
1902 cpl->ctrl1 = cpu_to_be64(cntrl);
1904 /* Fill in the body of the TX Packet CPL message with either in-lined
1905 * data or a Scatter/Gather List.
1907 if (t4vf_is_eth_imm(skb)) {
1908 /* In-line the packet's data and free the skb since we don't
1909 * need it any longer.
1911 cxgb4_inline_tx_skb(skb, &txq->q, cpl + 1);
1912 dev_consume_skb_any(skb);
1914 /* Write the skb's Scatter/Gather list into the TX Packet CPL
1915 * message and retain a pointer to the skb so we can free it
1916 * later when its DMA completes. (We store the skb pointer
1917 * in the Software Descriptor corresponding to the last TX
1918 * Descriptor used by the Work Request.)
1920 * The retained skb will be freed when the corresponding TX
1921 * Descriptors are reclaimed after their DMAs complete.
1922 * However, this could take quite a while since, in general,
1923 * the hardware is set up to be lazy about sending DMA
1924 * completion notifications to us and we mostly perform TX
1925 * reclaims in the transmit routine.
1927 * This is good for performamce but means that we rely on new
1928 * TX packets arriving to run the destructors of completed
1929 * packets, which open up space in their sockets' send queues.
1930 * Sometimes we do not get such new packets causing TX to
1931 * stall. A single UDP transmitter is a good example of this
1932 * situation. We have a clean up timer that periodically
1933 * reclaims completed packets but it doesn't run often enough
1934 * (nor do we want it to) to prevent lengthy stalls. A
1935 * solution to this problem is to run the destructor early,
1936 * after the packet is queued but before it's DMAd. A con is
1937 * that we lie to socket memory accounting, but the amount of
1938 * extra memory is reasonable (limited by the number of TX
1939 * descriptors), the packets do actually get freed quickly by
1940 * new packets almost always, and for protocols like TCP that
1941 * wait for acks to really free up the data the extra memory
1942 * is even less. On the positive side we run the destructors
1943 * on the sending CPU rather than on a potentially different
1944 * completing CPU, usually a good thing.
1946 * Run the destructor before telling the DMA engine about the
1947 * packet to make sure it doesn't complete and get freed
1950 struct ulptx_sgl *sgl = (struct ulptx_sgl *)(cpl + 1);
1951 struct sge_txq *tq = &txq->q;
1953 /* If the Work Request header was an exact multiple of our TX
1954 * Descriptor length, then it's possible that the starting SGL
1955 * pointer lines up exactly with the end of our TX Descriptor
1956 * ring. If that's the case, wrap around to the beginning
1959 if (unlikely((void *)sgl == (void *)tq->stat)) {
1960 sgl = (void *)tq->desc;
1961 end = (void *)((void *)tq->desc +
1962 ((void *)end - (void *)tq->stat));
1965 cxgb4_write_sgl(skb, tq, sgl, end, 0, sgl_sdesc->addr);
1967 sgl_sdesc->skb = skb;
1970 /* Advance our internal TX Queue state, tell the hardware about
1971 * the new TX descriptors and return success.
1973 txq_advance(&txq->q, ndesc);
1975 cxgb4_ring_tx_db(adapter, &txq->q, ndesc);
1976 return NETDEV_TX_OK;
1979 /* An error of some sort happened. Free the TX skb and tell the
1980 * OS that we've "dealt" with the packet ...
1982 dev_kfree_skb_any(skb);
1983 return NETDEV_TX_OK;
1987 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
1988 * @q: the SGE control Tx queue
1990 * This is a variant of cxgb4_reclaim_completed_tx() that is used
1991 * for Tx queues that send only immediate data (presently just
1992 * the control queues) and thus do not have any sk_buffs to release.
1994 static inline void reclaim_completed_tx_imm(struct sge_txq *q)
1996 int hw_cidx = ntohs(READ_ONCE(q->stat->cidx));
1997 int reclaim = hw_cidx - q->cidx;
2002 q->in_use -= reclaim;
2006 static inline void eosw_txq_advance_index(u32 *idx, u32 n, u32 max)
2016 void cxgb4_eosw_txq_free_desc(struct adapter *adap,
2017 struct sge_eosw_txq *eosw_txq, u32 ndesc)
2019 struct tx_sw_desc *d;
2021 d = &eosw_txq->desc[eosw_txq->last_cidx];
2025 unmap_skb(adap->pdev_dev, d->skb, d->addr);
2026 memset(d->addr, 0, sizeof(d->addr));
2028 dev_consume_skb_any(d->skb);
2031 eosw_txq_advance_index(&eosw_txq->last_cidx, 1,
2033 d = &eosw_txq->desc[eosw_txq->last_cidx];
2037 static inline void eosw_txq_advance(struct sge_eosw_txq *eosw_txq, u32 n)
2039 eosw_txq_advance_index(&eosw_txq->pidx, n, eosw_txq->ndesc);
2040 eosw_txq->inuse += n;
2043 static inline int eosw_txq_enqueue(struct sge_eosw_txq *eosw_txq,
2044 struct sk_buff *skb)
2046 if (eosw_txq->inuse == eosw_txq->ndesc)
2049 eosw_txq->desc[eosw_txq->pidx].skb = skb;
2053 static inline struct sk_buff *eosw_txq_peek(struct sge_eosw_txq *eosw_txq)
2055 return eosw_txq->desc[eosw_txq->last_pidx].skb;
2058 static inline u8 ethofld_calc_tx_flits(struct adapter *adap,
2059 struct sk_buff *skb, u32 hdr_len)
2064 wrlen = sizeof(struct fw_eth_tx_eo_wr) + sizeof(struct cpl_tx_pkt_core);
2065 if (skb_shinfo(skb)->gso_size &&
2066 !(skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4))
2067 wrlen += sizeof(struct cpl_tx_pkt_lso_core);
2069 wrlen += roundup(hdr_len, 16);
2071 /* Packet headers + WR + CPLs */
2072 flits = DIV_ROUND_UP(wrlen, 8);
2074 if (skb_shinfo(skb)->nr_frags > 0) {
2075 if (skb_headlen(skb) - hdr_len)
2076 nsgl = sgl_len(skb_shinfo(skb)->nr_frags + 1);
2078 nsgl = sgl_len(skb_shinfo(skb)->nr_frags);
2079 } else if (skb->len - hdr_len) {
2083 return flits + nsgl;
2086 static void *write_eo_wr(struct adapter *adap, struct sge_eosw_txq *eosw_txq,
2087 struct sk_buff *skb, struct fw_eth_tx_eo_wr *wr,
2088 u32 hdr_len, u32 wrlen)
2090 const struct skb_shared_info *ssi = skb_shinfo(skb);
2091 struct cpl_tx_pkt_core *cpl;
2092 u32 immd_len, wrlen16;
2096 ver = ip_hdr(skb)->version;
2097 proto = (ver == 6) ? ipv6_hdr(skb)->nexthdr : ip_hdr(skb)->protocol;
2099 wrlen16 = DIV_ROUND_UP(wrlen, 16);
2100 immd_len = sizeof(struct cpl_tx_pkt_core);
2101 if (skb_shinfo(skb)->gso_size &&
2102 !(skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4))
2103 immd_len += sizeof(struct cpl_tx_pkt_lso_core);
2104 immd_len += hdr_len;
2106 if (!eosw_txq->ncompl ||
2107 (eosw_txq->last_compl + wrlen16) >=
2108 (adap->params.ofldq_wr_cred / 2)) {
2111 eosw_txq->last_compl = 0;
2114 wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_EO_WR) |
2115 FW_ETH_TX_EO_WR_IMMDLEN_V(immd_len) |
2116 FW_WR_COMPL_V(compl));
2117 wr->equiq_to_len16 = cpu_to_be32(FW_WR_LEN16_V(wrlen16) |
2118 FW_WR_FLOWID_V(eosw_txq->hwtid));
2120 if (proto == IPPROTO_UDP) {
2121 cpl = write_eo_udp_wr(skb, wr, hdr_len);
2123 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
2124 wr->u.tcpseg.ethlen = skb_network_offset(skb);
2125 wr->u.tcpseg.iplen = cpu_to_be16(skb_network_header_len(skb));
2126 wr->u.tcpseg.tcplen = tcp_hdrlen(skb);
2127 wr->u.tcpseg.tsclk_tsoff = 0;
2128 wr->u.tcpseg.r4 = 0;
2129 wr->u.tcpseg.r5 = 0;
2130 wr->u.tcpseg.plen = cpu_to_be32(skb->len - hdr_len);
2132 if (ssi->gso_size) {
2133 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
2135 wr->u.tcpseg.mss = cpu_to_be16(ssi->gso_size);
2136 cpl = write_tso_wr(adap, skb, lso);
2138 wr->u.tcpseg.mss = cpu_to_be16(0xffff);
2139 cpl = (void *)(wr + 1);
2143 eosw_txq->cred -= wrlen16;
2144 eosw_txq->last_compl += wrlen16;
2148 static int ethofld_hard_xmit(struct net_device *dev,
2149 struct sge_eosw_txq *eosw_txq)
2151 struct port_info *pi = netdev2pinfo(dev);
2152 struct adapter *adap = netdev2adap(dev);
2153 u32 wrlen, wrlen16, hdr_len, data_len;
2154 enum sge_eosw_state next_state;
2155 u64 cntrl, *start, *end, *sgl;
2156 struct sge_eohw_txq *eohw_txq;
2157 struct cpl_tx_pkt_core *cpl;
2158 struct fw_eth_tx_eo_wr *wr;
2159 bool skip_eotx_wr = false;
2160 struct tx_sw_desc *d;
2161 struct sk_buff *skb;
2165 eohw_txq = &adap->sge.eohw_txq[eosw_txq->hwqid];
2166 spin_lock(&eohw_txq->lock);
2167 reclaim_completed_tx_imm(&eohw_txq->q);
2169 d = &eosw_txq->desc[eosw_txq->last_pidx];
2171 skb_tx_timestamp(skb);
2173 wr = (struct fw_eth_tx_eo_wr *)&eohw_txq->q.desc[eohw_txq->q.pidx];
2174 if (unlikely(eosw_txq->state != CXGB4_EO_STATE_ACTIVE &&
2175 eosw_txq->last_pidx == eosw_txq->flowc_idx)) {
2178 flits = DIV_ROUND_UP(hdr_len, 8);
2179 if (eosw_txq->state == CXGB4_EO_STATE_FLOWC_OPEN_SEND)
2180 next_state = CXGB4_EO_STATE_FLOWC_OPEN_REPLY;
2182 next_state = CXGB4_EO_STATE_FLOWC_CLOSE_REPLY;
2183 skip_eotx_wr = true;
2185 hdr_len = eth_get_headlen(dev, skb->data, skb_headlen(skb));
2186 data_len = skb->len - hdr_len;
2187 flits = ethofld_calc_tx_flits(adap, skb, hdr_len);
2189 ndesc = flits_to_desc(flits);
2191 wrlen16 = DIV_ROUND_UP(wrlen, 16);
2193 left = txq_avail(&eohw_txq->q) - ndesc;
2195 /* If there are no descriptors left in hardware queues or no
2196 * CPL credits left in software queues, then wait for them
2197 * to come back and retry again. Note that we always request
2198 * for credits update via interrupt for every half credits
2199 * consumed. So, the interrupt will eventually restore the
2200 * credits and invoke the Tx path again.
2202 if (unlikely(left < 0 || wrlen16 > eosw_txq->cred)) {
2207 if (unlikely(skip_eotx_wr)) {
2209 eosw_txq->state = next_state;
2210 eosw_txq->cred -= wrlen16;
2212 eosw_txq->last_compl = 0;
2213 goto write_wr_headers;
2216 cpl = write_eo_wr(adap, eosw_txq, skb, wr, hdr_len, wrlen);
2217 cntrl = hwcsum(adap->params.chip, skb);
2218 if (skb_vlan_tag_present(skb))
2219 cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb));
2221 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) |
2222 TXPKT_INTF_V(pi->tx_chan) |
2223 TXPKT_PF_V(adap->pf));
2225 cpl->len = cpu_to_be16(skb->len);
2226 cpl->ctrl1 = cpu_to_be64(cntrl);
2228 start = (u64 *)(cpl + 1);
2231 sgl = (u64 *)inline_tx_skb_header(skb, &eohw_txq->q, (void *)start,
2234 ret = cxgb4_map_skb(adap->pdev_dev, skb, d->addr);
2235 if (unlikely(ret)) {
2236 memset(d->addr, 0, sizeof(d->addr));
2237 eohw_txq->mapping_err++;
2241 end = (u64 *)wr + flits;
2242 if (unlikely(start > sgl)) {
2243 left = (u8 *)end - (u8 *)eohw_txq->q.stat;
2244 end = (void *)eohw_txq->q.desc + left;
2247 if (unlikely((u8 *)sgl >= (u8 *)eohw_txq->q.stat)) {
2248 /* If current position is already at the end of the
2249 * txq, reset the current to point to start of the queue
2250 * and update the end ptr as well.
2252 left = (u8 *)end - (u8 *)eohw_txq->q.stat;
2254 end = (void *)eohw_txq->q.desc + left;
2255 sgl = (void *)eohw_txq->q.desc;
2258 cxgb4_write_sgl(skb, &eohw_txq->q, (void *)sgl, end, hdr_len,
2262 if (skb_shinfo(skb)->gso_size) {
2263 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)
2267 eohw_txq->tx_cso += skb_shinfo(skb)->gso_segs;
2268 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2272 if (skb_vlan_tag_present(skb))
2273 eohw_txq->vlan_ins++;
2275 txq_advance(&eohw_txq->q, ndesc);
2276 cxgb4_ring_tx_db(adap, &eohw_txq->q, ndesc);
2277 eosw_txq_advance_index(&eosw_txq->last_pidx, 1, eosw_txq->ndesc);
2280 spin_unlock(&eohw_txq->lock);
2284 static void ethofld_xmit(struct net_device *dev, struct sge_eosw_txq *eosw_txq)
2286 struct sk_buff *skb;
2289 switch (eosw_txq->state) {
2290 case CXGB4_EO_STATE_ACTIVE:
2291 case CXGB4_EO_STATE_FLOWC_OPEN_SEND:
2292 case CXGB4_EO_STATE_FLOWC_CLOSE_SEND:
2293 pktcount = eosw_txq->pidx - eosw_txq->last_pidx;
2295 pktcount += eosw_txq->ndesc;
2297 case CXGB4_EO_STATE_FLOWC_OPEN_REPLY:
2298 case CXGB4_EO_STATE_FLOWC_CLOSE_REPLY:
2299 case CXGB4_EO_STATE_CLOSED:
2304 while (pktcount--) {
2305 skb = eosw_txq_peek(eosw_txq);
2307 eosw_txq_advance_index(&eosw_txq->last_pidx, 1,
2312 ret = ethofld_hard_xmit(dev, eosw_txq);
2318 static netdev_tx_t cxgb4_ethofld_xmit(struct sk_buff *skb,
2319 struct net_device *dev)
2321 struct cxgb4_tc_port_mqprio *tc_port_mqprio;
2322 struct port_info *pi = netdev2pinfo(dev);
2323 struct adapter *adap = netdev2adap(dev);
2324 struct sge_eosw_txq *eosw_txq;
2328 ret = cxgb4_validate_skb(skb, dev, ETH_HLEN);
2332 tc_port_mqprio = &adap->tc_mqprio->port_mqprio[pi->port_id];
2333 qid = skb_get_queue_mapping(skb) - pi->nqsets;
2334 eosw_txq = &tc_port_mqprio->eosw_txq[qid];
2335 spin_lock_bh(&eosw_txq->lock);
2336 if (eosw_txq->state != CXGB4_EO_STATE_ACTIVE)
2339 ret = eosw_txq_enqueue(eosw_txq, skb);
2343 /* SKB is queued for processing until credits are available.
2344 * So, call the destructor now and we'll free the skb later
2345 * after it has been successfully transmitted.
2349 eosw_txq_advance(eosw_txq, 1);
2350 ethofld_xmit(dev, eosw_txq);
2351 spin_unlock_bh(&eosw_txq->lock);
2352 return NETDEV_TX_OK;
2355 spin_unlock_bh(&eosw_txq->lock);
2357 dev_kfree_skb_any(skb);
2358 return NETDEV_TX_OK;
2361 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev)
2363 struct port_info *pi = netdev_priv(dev);
2364 u16 qid = skb_get_queue_mapping(skb);
2366 if (unlikely(pi->eth_flags & PRIV_FLAG_PORT_TX_VM))
2367 return cxgb4_vf_eth_xmit(skb, dev);
2369 if (unlikely(qid >= pi->nqsets))
2370 return cxgb4_ethofld_xmit(skb, dev);
2372 if (is_ptp_enabled(skb, dev)) {
2373 struct adapter *adap = netdev2adap(dev);
2376 spin_lock(&adap->ptp_lock);
2377 ret = cxgb4_eth_xmit(skb, dev);
2378 spin_unlock(&adap->ptp_lock);
2382 return cxgb4_eth_xmit(skb, dev);
2385 static void eosw_txq_flush_pending_skbs(struct sge_eosw_txq *eosw_txq)
2387 int pktcount = eosw_txq->pidx - eosw_txq->last_pidx;
2388 int pidx = eosw_txq->pidx;
2389 struct sk_buff *skb;
2395 pktcount += eosw_txq->ndesc;
2397 while (pktcount--) {
2400 pidx += eosw_txq->ndesc;
2402 skb = eosw_txq->desc[pidx].skb;
2404 dev_consume_skb_any(skb);
2405 eosw_txq->desc[pidx].skb = NULL;
2410 eosw_txq->pidx = eosw_txq->last_pidx + 1;
2414 * cxgb4_ethofld_send_flowc - Send ETHOFLD flowc request to bind eotid to tc.
2416 * @eotid: ETHOFLD tid to bind/unbind
2417 * @tc: traffic class. If set to FW_SCHED_CLS_NONE, then unbinds the @eotid
2419 * Send a FLOWC work request to bind an ETHOFLD TID to a traffic class.
2420 * If @tc is set to FW_SCHED_CLS_NONE, then the @eotid is unbound from
2423 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc)
2425 struct port_info *pi = netdev2pinfo(dev);
2426 struct adapter *adap = netdev2adap(dev);
2427 enum sge_eosw_state next_state;
2428 struct sge_eosw_txq *eosw_txq;
2429 u32 len, len16, nparams = 6;
2430 struct fw_flowc_wr *flowc;
2431 struct eotid_entry *entry;
2432 struct sge_ofld_rxq *rxq;
2433 struct sk_buff *skb;
2436 len = struct_size(flowc, mnemval, nparams);
2437 len16 = DIV_ROUND_UP(len, 16);
2439 entry = cxgb4_lookup_eotid(&adap->tids, eotid);
2443 eosw_txq = (struct sge_eosw_txq *)entry->data;
2447 skb = alloc_skb(len, GFP_KERNEL);
2451 spin_lock_bh(&eosw_txq->lock);
2452 if (tc != FW_SCHED_CLS_NONE) {
2453 if (eosw_txq->state != CXGB4_EO_STATE_CLOSED)
2456 next_state = CXGB4_EO_STATE_FLOWC_OPEN_SEND;
2458 if (eosw_txq->state != CXGB4_EO_STATE_ACTIVE)
2461 next_state = CXGB4_EO_STATE_FLOWC_CLOSE_SEND;
2464 flowc = __skb_put(skb, len);
2465 memset(flowc, 0, len);
2467 rxq = &adap->sge.eohw_rxq[eosw_txq->hwqid];
2468 flowc->flowid_len16 = cpu_to_be32(FW_WR_LEN16_V(len16) |
2469 FW_WR_FLOWID_V(eosw_txq->hwtid));
2470 flowc->op_to_nparams = cpu_to_be32(FW_WR_OP_V(FW_FLOWC_WR) |
2471 FW_FLOWC_WR_NPARAMS_V(nparams) |
2473 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
2474 flowc->mnemval[0].val = cpu_to_be32(FW_PFVF_CMD_PFN_V(adap->pf));
2475 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
2476 flowc->mnemval[1].val = cpu_to_be32(pi->tx_chan);
2477 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
2478 flowc->mnemval[2].val = cpu_to_be32(pi->tx_chan);
2479 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
2480 flowc->mnemval[3].val = cpu_to_be32(rxq->rspq.abs_id);
2481 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
2482 flowc->mnemval[4].val = cpu_to_be32(tc);
2483 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_EOSTATE;
2484 flowc->mnemval[5].val = cpu_to_be32(tc == FW_SCHED_CLS_NONE ?
2485 FW_FLOWC_MNEM_EOSTATE_CLOSING :
2486 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
2488 /* Free up any pending skbs to ensure there's room for
2489 * termination FLOWC.
2491 if (tc == FW_SCHED_CLS_NONE)
2492 eosw_txq_flush_pending_skbs(eosw_txq);
2494 ret = eosw_txq_enqueue(eosw_txq, skb);
2496 dev_consume_skb_any(skb);
2500 eosw_txq->state = next_state;
2501 eosw_txq->flowc_idx = eosw_txq->pidx;
2502 eosw_txq_advance(eosw_txq, 1);
2503 ethofld_xmit(dev, eosw_txq);
2506 spin_unlock_bh(&eosw_txq->lock);
2511 * is_imm - check whether a packet can be sent as immediate data
2514 * Returns true if a packet can be sent as a WR with immediate data.
2516 static inline int is_imm(const struct sk_buff *skb)
2518 return skb->len <= MAX_CTRL_WR_LEN;
2522 * ctrlq_check_stop - check if a control queue is full and should stop
2524 * @wr: most recent WR written to the queue
2526 * Check if a control queue has become full and should be stopped.
2527 * We clean up control queue descriptors very lazily, only when we are out.
2528 * If the queue is still full after reclaiming any completed descriptors
2529 * we suspend it and have the last WR wake it up.
2531 static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr)
2533 reclaim_completed_tx_imm(&q->q);
2534 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
2535 wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F);
2541 #define CXGB4_SELFTEST_LB_STR "CHELSIO_SELFTEST"
2543 int cxgb4_selftest_lb_pkt(struct net_device *netdev)
2545 struct port_info *pi = netdev_priv(netdev);
2546 struct adapter *adap = pi->adapter;
2547 struct cxgb4_ethtool_lb_test *lb;
2548 int ret, i = 0, pkt_len, credits;
2549 struct fw_eth_tx_pkt_wr *wr;
2550 struct cpl_tx_pkt_core *cpl;
2551 u32 ctrl0, ndesc, flits;
2552 struct sge_eth_txq *q;
2555 pkt_len = ETH_HLEN + sizeof(CXGB4_SELFTEST_LB_STR);
2557 flits = DIV_ROUND_UP(pkt_len + sizeof(*cpl) + sizeof(*wr),
2559 ndesc = flits_to_desc(flits);
2561 lb = &pi->ethtool_lb;
2564 q = &adap->sge.ethtxq[pi->first_qset];
2565 __netif_tx_lock(q->txq, smp_processor_id());
2567 reclaim_completed_tx(adap, &q->q, -1, true);
2568 credits = txq_avail(&q->q) - ndesc;
2569 if (unlikely(credits < 0)) {
2570 __netif_tx_unlock(q->txq);
2574 wr = (void *)&q->q.desc[q->q.pidx];
2575 memset(wr, 0, sizeof(struct tx_desc));
2577 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
2578 FW_WR_IMMDLEN_V(pkt_len +
2580 wr->equiq_to_len16 = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2)));
2581 wr->r3 = cpu_to_be64(0);
2583 cpl = (void *)(wr + 1);
2584 sgl = (u8 *)(cpl + 1);
2586 ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_PF_V(adap->pf) |
2587 TXPKT_INTF_V(pi->tx_chan + 4);
2589 cpl->ctrl0 = htonl(ctrl0);
2590 cpl->pack = htons(0);
2591 cpl->len = htons(pkt_len);
2592 cpl->ctrl1 = cpu_to_be64(TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F);
2594 eth_broadcast_addr(sgl);
2596 ether_addr_copy(&sgl[i], netdev->dev_addr);
2599 snprintf(&sgl[i], sizeof(CXGB4_SELFTEST_LB_STR), "%s",
2600 CXGB4_SELFTEST_LB_STR);
2602 init_completion(&lb->completion);
2603 txq_advance(&q->q, ndesc);
2604 cxgb4_ring_tx_db(adap, &q->q, ndesc);
2605 __netif_tx_unlock(q->txq);
2607 /* wait for the pkt to return */
2608 ret = wait_for_completion_timeout(&lb->completion, 10 * HZ);
2620 * ctrl_xmit - send a packet through an SGE control Tx queue
2621 * @q: the control queue
2624 * Send a packet through an SGE control Tx queue. Packets sent through
2625 * a control queue must fit entirely as immediate data.
2627 static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb)
2630 struct fw_wr_hdr *wr;
2632 if (unlikely(!is_imm(skb))) {
2635 return NET_XMIT_DROP;
2638 ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc));
2639 spin_lock(&q->sendq.lock);
2641 if (unlikely(q->full)) {
2642 skb->priority = ndesc; /* save for restart */
2643 __skb_queue_tail(&q->sendq, skb);
2644 spin_unlock(&q->sendq.lock);
2648 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
2649 cxgb4_inline_tx_skb(skb, &q->q, wr);
2651 txq_advance(&q->q, ndesc);
2652 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES))
2653 ctrlq_check_stop(q, wr);
2655 cxgb4_ring_tx_db(q->adap, &q->q, ndesc);
2656 spin_unlock(&q->sendq.lock);
2659 return NET_XMIT_SUCCESS;
2663 * restart_ctrlq - restart a suspended control queue
2664 * @t: pointer to the tasklet associated with this handler
2666 * Resumes transmission on a suspended Tx control queue.
2668 static void restart_ctrlq(struct tasklet_struct *t)
2670 struct sk_buff *skb;
2671 unsigned int written = 0;
2672 struct sge_ctrl_txq *q = from_tasklet(q, t, qresume_tsk);
2674 spin_lock(&q->sendq.lock);
2675 reclaim_completed_tx_imm(&q->q);
2676 BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */
2678 while ((skb = __skb_dequeue(&q->sendq)) != NULL) {
2679 struct fw_wr_hdr *wr;
2680 unsigned int ndesc = skb->priority; /* previously saved */
2683 /* Write descriptors and free skbs outside the lock to limit
2684 * wait times. q->full is still set so new skbs will be queued.
2686 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
2687 txq_advance(&q->q, ndesc);
2688 spin_unlock(&q->sendq.lock);
2690 cxgb4_inline_tx_skb(skb, &q->q, wr);
2693 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
2694 unsigned long old = q->q.stops;
2696 ctrlq_check_stop(q, wr);
2697 if (q->q.stops != old) { /* suspended anew */
2698 spin_lock(&q->sendq.lock);
2703 cxgb4_ring_tx_db(q->adap, &q->q, written);
2706 spin_lock(&q->sendq.lock);
2711 cxgb4_ring_tx_db(q->adap, &q->q, written);
2712 spin_unlock(&q->sendq.lock);
2716 * t4_mgmt_tx - send a management message
2717 * @adap: the adapter
2718 * @skb: the packet containing the management message
2720 * Send a management message through control queue 0.
2722 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
2727 ret = ctrl_xmit(&adap->sge.ctrlq[0], skb);
2733 * is_ofld_imm - check whether a packet can be sent as immediate data
2736 * Returns true if a packet can be sent as an offload WR with immediate
2737 * data. We currently use the same limit as for Ethernet packets.
2739 static inline int is_ofld_imm(const struct sk_buff *skb)
2741 struct work_request_hdr *req = (struct work_request_hdr *)skb->data;
2742 unsigned long opcode = FW_WR_OP_G(ntohl(req->wr_hi));
2744 if (opcode == FW_CRYPTO_LOOKASIDE_WR)
2745 return skb->len <= SGE_MAX_WR_LEN;
2747 return skb->len <= MAX_IMM_TX_PKT_LEN;
2751 * calc_tx_flits_ofld - calculate # of flits for an offload packet
2754 * Returns the number of flits needed for the given offload packet.
2755 * These packets are already fully constructed and no additional headers
2758 static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb)
2760 unsigned int flits, cnt;
2762 if (is_ofld_imm(skb))
2763 return DIV_ROUND_UP(skb->len, 8);
2765 flits = skb_transport_offset(skb) / 8U; /* headers */
2766 cnt = skb_shinfo(skb)->nr_frags;
2767 if (skb_tail_pointer(skb) != skb_transport_header(skb))
2769 return flits + sgl_len(cnt);
2773 * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion
2774 * @q: the queue to stop
2776 * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting
2777 * inability to map packets. A periodic timer attempts to restart
2780 static void txq_stop_maperr(struct sge_uld_txq *q)
2784 set_bit(q->q.cntxt_id - q->adap->sge.egr_start,
2785 q->adap->sge.txq_maperr);
2789 * ofldtxq_stop - stop an offload Tx queue that has become full
2790 * @q: the queue to stop
2791 * @wr: the Work Request causing the queue to become full
2793 * Stops an offload Tx queue that has become full and modifies the packet
2794 * being written to request a wakeup.
2796 static void ofldtxq_stop(struct sge_uld_txq *q, struct fw_wr_hdr *wr)
2798 wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F);
2804 * service_ofldq - service/restart a suspended offload queue
2805 * @q: the offload queue
2807 * Services an offload Tx queue by moving packets from its Pending Send
2808 * Queue to the Hardware TX ring. The function starts and ends with the
2809 * Send Queue locked, but drops the lock while putting the skb at the
2810 * head of the Send Queue onto the Hardware TX Ring. Dropping the lock
2811 * allows more skbs to be added to the Send Queue by other threads.
2812 * The packet being processed at the head of the Pending Send Queue is
2813 * left on the queue in case we experience DMA Mapping errors, etc.
2814 * and need to give up and restart later.
2816 * service_ofldq() can be thought of as a task which opportunistically
2817 * uses other threads execution contexts. We use the Offload Queue
2818 * boolean "service_ofldq_running" to make sure that only one instance
2819 * is ever running at a time ...
2821 static void service_ofldq(struct sge_uld_txq *q)
2822 __must_hold(&q->sendq.lock)
2824 u64 *pos, *before, *end;
2826 struct sk_buff *skb;
2827 struct sge_txq *txq;
2829 unsigned int written = 0;
2830 unsigned int flits, ndesc;
2832 /* If another thread is currently in service_ofldq() processing the
2833 * Pending Send Queue then there's nothing to do. Otherwise, flag
2834 * that we're doing the work and continue. Examining/modifying
2835 * the Offload Queue boolean "service_ofldq_running" must be done
2836 * while holding the Pending Send Queue Lock.
2838 if (q->service_ofldq_running)
2840 q->service_ofldq_running = true;
2842 while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) {
2843 /* We drop the lock while we're working with the skb at the
2844 * head of the Pending Send Queue. This allows more skbs to
2845 * be added to the Pending Send Queue while we're working on
2846 * this one. We don't need to lock to guard the TX Ring
2847 * updates because only one thread of execution is ever
2848 * allowed into service_ofldq() at a time.
2850 spin_unlock(&q->sendq.lock);
2852 cxgb4_reclaim_completed_tx(q->adap, &q->q, false);
2854 flits = skb->priority; /* previously saved */
2855 ndesc = flits_to_desc(flits);
2856 credits = txq_avail(&q->q) - ndesc;
2857 BUG_ON(credits < 0);
2858 if (unlikely(credits < TXQ_STOP_THRES))
2859 ofldtxq_stop(q, (struct fw_wr_hdr *)skb->data);
2861 pos = (u64 *)&q->q.desc[q->q.pidx];
2862 if (is_ofld_imm(skb))
2863 cxgb4_inline_tx_skb(skb, &q->q, pos);
2864 else if (cxgb4_map_skb(q->adap->pdev_dev, skb,
2865 (dma_addr_t *)skb->head)) {
2867 spin_lock(&q->sendq.lock);
2870 int last_desc, hdr_len = skb_transport_offset(skb);
2872 /* The WR headers may not fit within one descriptor.
2873 * So we need to deal with wrap-around here.
2875 before = (u64 *)pos;
2876 end = (u64 *)pos + flits;
2878 pos = (void *)inline_tx_skb_header(skb, &q->q,
2881 if (before > (u64 *)pos) {
2882 left = (u8 *)end - (u8 *)txq->stat;
2883 end = (void *)txq->desc + left;
2886 /* If current position is already at the end of the
2887 * ofld queue, reset the current to point to
2888 * start of the queue and update the end ptr as well.
2890 if (pos == (u64 *)txq->stat) {
2891 left = (u8 *)end - (u8 *)txq->stat;
2892 end = (void *)txq->desc + left;
2893 pos = (void *)txq->desc;
2896 cxgb4_write_sgl(skb, &q->q, (void *)pos,
2898 (dma_addr_t *)skb->head);
2899 #ifdef CONFIG_NEED_DMA_MAP_STATE
2900 skb->dev = q->adap->port[0];
2901 skb->destructor = deferred_unmap_destructor;
2903 last_desc = q->q.pidx + ndesc - 1;
2904 if (last_desc >= q->q.size)
2905 last_desc -= q->q.size;
2906 q->q.sdesc[last_desc].skb = skb;
2909 txq_advance(&q->q, ndesc);
2911 if (unlikely(written > 32)) {
2912 cxgb4_ring_tx_db(q->adap, &q->q, written);
2916 /* Reacquire the Pending Send Queue Lock so we can unlink the
2917 * skb we've just successfully transferred to the TX Ring and
2918 * loop for the next skb which may be at the head of the
2919 * Pending Send Queue.
2921 spin_lock(&q->sendq.lock);
2922 __skb_unlink(skb, &q->sendq);
2923 if (is_ofld_imm(skb))
2926 if (likely(written))
2927 cxgb4_ring_tx_db(q->adap, &q->q, written);
2929 /*Indicate that no thread is processing the Pending Send Queue
2932 q->service_ofldq_running = false;
2936 * ofld_xmit - send a packet through an offload queue
2937 * @q: the Tx offload queue
2940 * Send an offload packet through an SGE offload queue.
2942 static int ofld_xmit(struct sge_uld_txq *q, struct sk_buff *skb)
2944 skb->priority = calc_tx_flits_ofld(skb); /* save for restart */
2945 spin_lock(&q->sendq.lock);
2947 /* Queue the new skb onto the Offload Queue's Pending Send Queue. If
2948 * that results in this new skb being the only one on the queue, start
2949 * servicing it. If there are other skbs already on the list, then
2950 * either the queue is currently being processed or it's been stopped
2951 * for some reason and it'll be restarted at a later time. Restart
2952 * paths are triggered by events like experiencing a DMA Mapping Error
2953 * or filling the Hardware TX Ring.
2955 __skb_queue_tail(&q->sendq, skb);
2956 if (q->sendq.qlen == 1)
2959 spin_unlock(&q->sendq.lock);
2960 return NET_XMIT_SUCCESS;
2964 * restart_ofldq - restart a suspended offload queue
2965 * @t: pointer to the tasklet associated with this handler
2967 * Resumes transmission on a suspended Tx offload queue.
2969 static void restart_ofldq(struct tasklet_struct *t)
2971 struct sge_uld_txq *q = from_tasklet(q, t, qresume_tsk);
2973 spin_lock(&q->sendq.lock);
2974 q->full = 0; /* the queue actually is completely empty now */
2976 spin_unlock(&q->sendq.lock);
2980 * skb_txq - return the Tx queue an offload packet should use
2983 * Returns the Tx queue an offload packet should use as indicated by bits
2984 * 1-15 in the packet's queue_mapping.
2986 static inline unsigned int skb_txq(const struct sk_buff *skb)
2988 return skb->queue_mapping >> 1;
2992 * is_ctrl_pkt - return whether an offload packet is a control packet
2995 * Returns whether an offload packet should use an OFLD or a CTRL
2996 * Tx queue as indicated by bit 0 in the packet's queue_mapping.
2998 static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb)
3000 return skb->queue_mapping & 1;
3003 static inline int uld_send(struct adapter *adap, struct sk_buff *skb,
3004 unsigned int tx_uld_type)
3006 struct sge_uld_txq_info *txq_info;
3007 struct sge_uld_txq *txq;
3008 unsigned int idx = skb_txq(skb);
3010 if (unlikely(is_ctrl_pkt(skb))) {
3011 /* Single ctrl queue is a requirement for LE workaround path */
3012 if (adap->tids.nsftids)
3014 return ctrl_xmit(&adap->sge.ctrlq[idx], skb);
3017 txq_info = adap->sge.uld_txq_info[tx_uld_type];
3018 if (unlikely(!txq_info)) {
3021 return NET_XMIT_DROP;
3024 txq = &txq_info->uldtxq[idx];
3025 return ofld_xmit(txq, skb);
3029 * t4_ofld_send - send an offload packet
3030 * @adap: the adapter
3033 * Sends an offload packet. We use the packet queue_mapping to select the
3034 * appropriate Tx queue as follows: bit 0 indicates whether the packet
3035 * should be sent as regular or control, bits 1-15 select the queue.
3037 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb)
3042 ret = uld_send(adap, skb, CXGB4_TX_OFLD);
3048 * cxgb4_ofld_send - send an offload packet
3049 * @dev: the net device
3052 * Sends an offload packet. This is an exported version of @t4_ofld_send,
3053 * intended for ULDs.
3055 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb)
3057 return t4_ofld_send(netdev2adap(dev), skb);
3059 EXPORT_SYMBOL(cxgb4_ofld_send);
3061 static void *inline_tx_header(const void *src,
3062 const struct sge_txq *q,
3063 void *pos, int length)
3065 int left = (void *)q->stat - pos;
3068 if (likely(length <= left)) {
3069 memcpy(pos, src, length);
3072 memcpy(pos, src, left);
3073 memcpy(q->desc, src + left, length - left);
3074 pos = (void *)q->desc + (length - left);
3076 /* 0-pad to multiple of 16 */
3077 p = PTR_ALIGN(pos, 8);
3078 if ((uintptr_t)p & 8) {
3086 * ofld_xmit_direct - copy a WR into offload queue
3087 * @q: the Tx offload queue
3088 * @src: location of WR
3091 * Copy an immediate WR into an uncontended SGE offload queue.
3093 static int ofld_xmit_direct(struct sge_uld_txq *q, const void *src,
3100 /* Use the lower limit as the cut-off */
3101 if (len > MAX_IMM_OFLD_TX_DATA_WR_LEN) {
3103 return NET_XMIT_DROP;
3106 /* Don't return NET_XMIT_CN here as the current
3107 * implementation doesn't queue the request
3108 * using an skb when the following conditions not met
3110 if (!spin_trylock(&q->sendq.lock))
3111 return NET_XMIT_DROP;
3113 if (q->full || !skb_queue_empty(&q->sendq) ||
3114 q->service_ofldq_running) {
3115 spin_unlock(&q->sendq.lock);
3116 return NET_XMIT_DROP;
3118 ndesc = flits_to_desc(DIV_ROUND_UP(len, 8));
3119 credits = txq_avail(&q->q) - ndesc;
3120 pos = (u64 *)&q->q.desc[q->q.pidx];
3122 /* ofldtxq_stop modifies WR header in-situ */
3123 inline_tx_header(src, &q->q, pos, len);
3124 if (unlikely(credits < TXQ_STOP_THRES))
3125 ofldtxq_stop(q, (struct fw_wr_hdr *)pos);
3126 txq_advance(&q->q, ndesc);
3127 cxgb4_ring_tx_db(q->adap, &q->q, ndesc);
3129 spin_unlock(&q->sendq.lock);
3130 return NET_XMIT_SUCCESS;
3133 int cxgb4_immdata_send(struct net_device *dev, unsigned int idx,
3134 const void *src, unsigned int len)
3136 struct sge_uld_txq_info *txq_info;
3137 struct sge_uld_txq *txq;
3138 struct adapter *adap;
3141 adap = netdev2adap(dev);
3144 txq_info = adap->sge.uld_txq_info[CXGB4_TX_OFLD];
3145 if (unlikely(!txq_info)) {
3148 return NET_XMIT_DROP;
3150 txq = &txq_info->uldtxq[idx];
3152 ret = ofld_xmit_direct(txq, src, len);
3154 return net_xmit_eval(ret);
3156 EXPORT_SYMBOL(cxgb4_immdata_send);
3159 * t4_crypto_send - send crypto packet
3160 * @adap: the adapter
3163 * Sends crypto packet. We use the packet queue_mapping to select the
3164 * appropriate Tx queue as follows: bit 0 indicates whether the packet
3165 * should be sent as regular or control, bits 1-15 select the queue.
3167 static int t4_crypto_send(struct adapter *adap, struct sk_buff *skb)
3172 ret = uld_send(adap, skb, CXGB4_TX_CRYPTO);
3178 * cxgb4_crypto_send - send crypto packet
3179 * @dev: the net device
3182 * Sends crypto packet. This is an exported version of @t4_crypto_send,
3183 * intended for ULDs.
3185 int cxgb4_crypto_send(struct net_device *dev, struct sk_buff *skb)
3187 return t4_crypto_send(netdev2adap(dev), skb);
3189 EXPORT_SYMBOL(cxgb4_crypto_send);
3191 static inline void copy_frags(struct sk_buff *skb,
3192 const struct pkt_gl *gl, unsigned int offset)
3196 /* usually there's just one frag */
3197 __skb_fill_page_desc(skb, 0, gl->frags[0].page,
3198 gl->frags[0].offset + offset,
3199 gl->frags[0].size - offset);
3200 skb_shinfo(skb)->nr_frags = gl->nfrags;
3201 for (i = 1; i < gl->nfrags; i++)
3202 __skb_fill_page_desc(skb, i, gl->frags[i].page,
3203 gl->frags[i].offset,
3206 /* get a reference to the last page, we don't own it */
3207 get_page(gl->frags[gl->nfrags - 1].page);
3211 * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list
3212 * @gl: the gather list
3213 * @skb_len: size of sk_buff main body if it carries fragments
3214 * @pull_len: amount of data to move to the sk_buff's main body
3216 * Builds an sk_buff from the given packet gather list. Returns the
3217 * sk_buff or %NULL if sk_buff allocation failed.
3219 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
3220 unsigned int skb_len, unsigned int pull_len)
3222 struct sk_buff *skb;
3225 * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer
3226 * size, which is expected since buffers are at least PAGE_SIZEd.
3227 * In this case packets up to RX_COPY_THRES have only one fragment.
3229 if (gl->tot_len <= RX_COPY_THRES) {
3230 skb = dev_alloc_skb(gl->tot_len);
3233 __skb_put(skb, gl->tot_len);
3234 skb_copy_to_linear_data(skb, gl->va, gl->tot_len);
3236 skb = dev_alloc_skb(skb_len);
3239 __skb_put(skb, pull_len);
3240 skb_copy_to_linear_data(skb, gl->va, pull_len);
3242 copy_frags(skb, gl, pull_len);
3243 skb->len = gl->tot_len;
3244 skb->data_len = skb->len - pull_len;
3245 skb->truesize += skb->data_len;
3249 EXPORT_SYMBOL(cxgb4_pktgl_to_skb);
3252 * t4_pktgl_free - free a packet gather list
3253 * @gl: the gather list
3255 * Releases the pages of a packet gather list. We do not own the last
3256 * page on the list and do not free it.
3258 static void t4_pktgl_free(const struct pkt_gl *gl)
3261 const struct page_frag *p;
3263 for (p = gl->frags, n = gl->nfrags - 1; n--; p++)
3268 * Process an MPS trace packet. Give it an unused protocol number so it won't
3269 * be delivered to anyone and send it to the stack for capture.
3271 static noinline int handle_trace_pkt(struct adapter *adap,
3272 const struct pkt_gl *gl)
3274 struct sk_buff *skb;
3276 skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
3277 if (unlikely(!skb)) {
3282 if (is_t4(adap->params.chip))
3283 __skb_pull(skb, sizeof(struct cpl_trace_pkt));
3285 __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt));
3287 skb_reset_mac_header(skb);
3288 skb->protocol = htons(0xffff);
3289 skb->dev = adap->port[0];
3290 netif_receive_skb(skb);
3295 * cxgb4_sgetim_to_hwtstamp - convert sge time stamp to hw time stamp
3296 * @adap: the adapter
3297 * @hwtstamps: time stamp structure to update
3298 * @sgetstamp: 60bit iqe timestamp
3300 * Every ingress queue entry has the 60-bit timestamp, convert that timestamp
3301 * which is in Core Clock ticks into ktime_t and assign it
3303 static void cxgb4_sgetim_to_hwtstamp(struct adapter *adap,
3304 struct skb_shared_hwtstamps *hwtstamps,
3308 u64 tmp = (sgetstamp * 1000 * 1000 + adap->params.vpd.cclk / 2);
3310 ns = div_u64(tmp, adap->params.vpd.cclk);
3312 memset(hwtstamps, 0, sizeof(*hwtstamps));
3313 hwtstamps->hwtstamp = ns_to_ktime(ns);
3316 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
3317 const struct cpl_rx_pkt *pkt, unsigned long tnl_hdr_len)
3319 struct adapter *adapter = rxq->rspq.adap;
3320 struct sge *s = &adapter->sge;
3321 struct port_info *pi;
3323 struct sk_buff *skb;
3325 skb = napi_get_frags(&rxq->rspq.napi);
3326 if (unlikely(!skb)) {
3328 rxq->stats.rx_drops++;
3332 copy_frags(skb, gl, s->pktshift);
3334 skb->csum_level = 1;
3335 skb->len = gl->tot_len - s->pktshift;
3336 skb->data_len = skb->len;
3337 skb->truesize += skb->data_len;
3338 skb->ip_summed = CHECKSUM_UNNECESSARY;
3339 skb_record_rx_queue(skb, rxq->rspq.idx);
3340 pi = netdev_priv(skb->dev);
3342 cxgb4_sgetim_to_hwtstamp(adapter, skb_hwtstamps(skb),
3344 if (rxq->rspq.netdev->features & NETIF_F_RXHASH)
3345 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
3348 if (unlikely(pkt->vlan_ex)) {
3349 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan));
3350 rxq->stats.vlan_ex++;
3352 ret = napi_gro_frags(&rxq->rspq.napi);
3353 if (ret == GRO_HELD)
3354 rxq->stats.lro_pkts++;
3355 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
3356 rxq->stats.lro_merged++;
3358 rxq->stats.rx_cso++;
3368 * t4_systim_to_hwstamp - read hardware time stamp
3369 * @adapter: the adapter
3372 * Read Time Stamp from MPS packet and insert in skb which
3373 * is forwarded to PTP application
3375 static noinline int t4_systim_to_hwstamp(struct adapter *adapter,
3376 struct sk_buff *skb)
3378 struct skb_shared_hwtstamps *hwtstamps;
3379 struct cpl_rx_mps_pkt *cpl = NULL;
3380 unsigned char *data;
3383 cpl = (struct cpl_rx_mps_pkt *)skb->data;
3384 if (!(CPL_RX_MPS_PKT_TYPE_G(ntohl(cpl->op_to_r1_hi)) &
3385 X_CPL_RX_MPS_PKT_TYPE_PTP))
3386 return RX_PTP_PKT_ERR;
3388 data = skb->data + sizeof(*cpl);
3389 skb_pull(skb, 2 * sizeof(u64) + sizeof(struct cpl_rx_mps_pkt));
3390 offset = ETH_HLEN + IPV4_HLEN(skb->data) + UDP_HLEN;
3391 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(short))
3392 return RX_PTP_PKT_ERR;
3394 hwtstamps = skb_hwtstamps(skb);
3395 memset(hwtstamps, 0, sizeof(*hwtstamps));
3396 hwtstamps->hwtstamp = ns_to_ktime(get_unaligned_be64(data));
3398 return RX_PTP_PKT_SUC;
3402 * t4_rx_hststamp - Recv PTP Event Message
3403 * @adapter: the adapter
3404 * @rsp: the response queue descriptor holding the RX_PKT message
3405 * @rxq: the response queue holding the RX_PKT message
3408 * PTP enabled and MPS packet, read HW timestamp
3410 static int t4_rx_hststamp(struct adapter *adapter, const __be64 *rsp,
3411 struct sge_eth_rxq *rxq, struct sk_buff *skb)
3415 if (unlikely((*(u8 *)rsp == CPL_RX_MPS_PKT) &&
3416 !is_t4(adapter->params.chip))) {
3417 ret = t4_systim_to_hwstamp(adapter, skb);
3418 if (ret == RX_PTP_PKT_ERR) {
3420 rxq->stats.rx_drops++;
3424 return RX_NON_PTP_PKT;
3428 * t4_tx_hststamp - Loopback PTP Transmit Event Message
3429 * @adapter: the adapter
3431 * @dev: the ingress net device
3433 * Read hardware timestamp for the loopback PTP Tx event message
3435 static int t4_tx_hststamp(struct adapter *adapter, struct sk_buff *skb,
3436 struct net_device *dev)
3438 struct port_info *pi = netdev_priv(dev);
3440 if (!is_t4(adapter->params.chip) && adapter->ptp_tx_skb) {
3441 cxgb4_ptp_read_hwstamp(adapter, pi);
3449 * t4_tx_completion_handler - handle CPL_SGE_EGR_UPDATE messages
3450 * @rspq: Ethernet RX Response Queue associated with Ethernet TX Queue
3451 * @rsp: Response Entry pointer into Response Queue
3452 * @gl: Gather List pointer
3454 * For adapters which support the SGE Doorbell Queue Timer facility,
3455 * we configure the Ethernet TX Queues to send CIDX Updates to the
3456 * Associated Ethernet RX Response Queue with CPL_SGE_EGR_UPDATE
3457 * messages. This adds a small load to PCIe Link RX bandwidth and,
3458 * potentially, higher CPU Interrupt load, but allows us to respond
3459 * much more quickly to the CIDX Updates. This is important for
3460 * Upper Layer Software which isn't willing to have a large amount
3461 * of TX Data outstanding before receiving DMA Completions.
3463 static void t4_tx_completion_handler(struct sge_rspq *rspq,
3465 const struct pkt_gl *gl)
3467 u8 opcode = ((const struct rss_header *)rsp)->opcode;
3468 struct port_info *pi = netdev_priv(rspq->netdev);
3469 struct adapter *adapter = rspq->adap;
3470 struct sge *s = &adapter->sge;
3471 struct sge_eth_txq *txq;
3473 /* skip RSS header */
3476 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
3478 if (unlikely(opcode == CPL_FW4_MSG &&
3479 ((const struct cpl_fw4_msg *)rsp)->type ==
3482 opcode = ((const struct rss_header *)rsp)->opcode;
3486 if (unlikely(opcode != CPL_SGE_EGR_UPDATE)) {
3487 pr_info("%s: unexpected FW4/CPL %#x on Rx queue\n",
3492 txq = &s->ethtxq[pi->first_qset + rspq->idx];
3493 t4_sge_eth_txq_egress_update(adapter, txq, -1);
3496 static int cxgb4_validate_lb_pkt(struct port_info *pi, const struct pkt_gl *si)
3498 struct adapter *adap = pi->adapter;
3499 struct cxgb4_ethtool_lb_test *lb;
3500 struct sge *s = &adap->sge;
3501 struct net_device *netdev;
3505 netdev = adap->port[pi->port_id];
3506 lb = &pi->ethtool_lb;
3507 data = si->va + s->pktshift;
3510 if (!ether_addr_equal(data + i, netdev->dev_addr))
3514 if (strcmp(&data[i], CXGB4_SELFTEST_LB_STR))
3517 complete(&lb->completion);
3522 * t4_ethrx_handler - process an ingress ethernet packet
3523 * @q: the response queue that received the packet
3524 * @rsp: the response queue descriptor holding the RX_PKT message
3525 * @si: the gather list of packet fragments
3527 * Process an ingress ethernet packet and deliver it to the stack.
3529 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
3530 const struct pkt_gl *si)
3533 struct sk_buff *skb;
3534 const struct cpl_rx_pkt *pkt;
3535 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
3536 struct adapter *adapter = q->adap;
3537 struct sge *s = &q->adap->sge;
3538 int cpl_trace_pkt = is_t4(q->adap->params.chip) ?
3539 CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
3540 u16 err_vec, tnl_hdr_len = 0;
3541 struct port_info *pi;
3544 pi = netdev_priv(q->netdev);
3545 /* If we're looking at TX Queue CIDX Update, handle that separately
3548 if (unlikely((*(u8 *)rsp == CPL_FW4_MSG) ||
3549 (*(u8 *)rsp == CPL_SGE_EGR_UPDATE))) {
3550 t4_tx_completion_handler(q, rsp, si);
3554 if (unlikely(*(u8 *)rsp == cpl_trace_pkt))
3555 return handle_trace_pkt(q->adap, si);
3557 pkt = (const struct cpl_rx_pkt *)rsp;
3558 /* Compressed error vector is enabled for T6 only */
3559 if (q->adap->params.tp.rx_pkt_encap) {
3560 err_vec = T6_COMPR_RXERR_VEC_G(be16_to_cpu(pkt->err_vec));
3561 tnl_hdr_len = T6_RX_TNLHDR_LEN_G(ntohs(pkt->err_vec));
3563 err_vec = be16_to_cpu(pkt->err_vec);
3566 csum_ok = pkt->csum_calc && !err_vec &&
3567 (q->netdev->features & NETIF_F_RXCSUM);
3570 rxq->stats.bad_rx_pkts++;
3572 if (unlikely(pi->ethtool_lb.loopback && pkt->iff >= NCHAN)) {
3573 ret = cxgb4_validate_lb_pkt(pi, si);
3578 if (((pkt->l2info & htonl(RXF_TCP_F)) ||
3580 (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) {
3581 do_gro(rxq, si, pkt, tnl_hdr_len);
3585 skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN);
3586 if (unlikely(!skb)) {
3588 rxq->stats.rx_drops++;
3592 /* Handle PTP Event Rx packet */
3593 if (unlikely(pi->ptp_enable)) {
3594 ret = t4_rx_hststamp(adapter, rsp, rxq, skb);
3595 if (ret == RX_PTP_PKT_ERR)
3599 __skb_pull(skb, s->pktshift); /* remove ethernet header pad */
3601 /* Handle the PTP Event Tx Loopback packet */
3602 if (unlikely(pi->ptp_enable && !ret &&
3603 (pkt->l2info & htonl(RXF_UDP_F)) &&
3604 cxgb4_ptp_is_ptp_rx(skb))) {
3605 if (!t4_tx_hststamp(adapter, skb, q->netdev))
3609 skb->protocol = eth_type_trans(skb, q->netdev);
3610 skb_record_rx_queue(skb, q->idx);
3611 if (skb->dev->features & NETIF_F_RXHASH)
3612 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
3618 cxgb4_sgetim_to_hwtstamp(q->adap, skb_hwtstamps(skb),
3620 if (csum_ok && (pkt->l2info & htonl(RXF_UDP_F | RXF_TCP_F))) {
3621 if (!pkt->ip_frag) {
3622 skb->ip_summed = CHECKSUM_UNNECESSARY;
3623 rxq->stats.rx_cso++;
3624 } else if (pkt->l2info & htonl(RXF_IP_F)) {
3625 __sum16 c = (__force __sum16)pkt->csum;
3626 skb->csum = csum_unfold(c);
3629 skb->ip_summed = CHECKSUM_UNNECESSARY;
3630 skb->csum_level = 1;
3632 skb->ip_summed = CHECKSUM_COMPLETE;
3634 rxq->stats.rx_cso++;
3637 skb_checksum_none_assert(skb);
3638 #ifdef CONFIG_CHELSIO_T4_FCOE
3639 #define CPL_RX_PKT_FLAGS (RXF_PSH_F | RXF_SYN_F | RXF_UDP_F | \
3640 RXF_TCP_F | RXF_IP_F | RXF_IP6_F | RXF_LRO_F)
3642 if (!(pkt->l2info & cpu_to_be32(CPL_RX_PKT_FLAGS))) {
3643 if ((pkt->l2info & cpu_to_be32(RXF_FCOE_F)) &&
3644 (pi->fcoe.flags & CXGB_FCOE_ENABLED)) {
3645 if (q->adap->params.tp.rx_pkt_encap)
3647 T6_COMPR_RXERR_SUM_F;
3649 csum_ok = err_vec & RXERR_CSUM_F;
3651 skb->ip_summed = CHECKSUM_UNNECESSARY;
3655 #undef CPL_RX_PKT_FLAGS
3656 #endif /* CONFIG_CHELSIO_T4_FCOE */
3659 if (unlikely(pkt->vlan_ex)) {
3660 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan));
3661 rxq->stats.vlan_ex++;
3663 skb_mark_napi_id(skb, &q->napi);
3664 netif_receive_skb(skb);
3669 * restore_rx_bufs - put back a packet's Rx buffers
3670 * @si: the packet gather list
3671 * @q: the SGE free list
3672 * @frags: number of FL buffers to restore
3674 * Puts back on an FL the Rx buffers associated with @si. The buffers
3675 * have already been unmapped and are left unmapped, we mark them so to
3676 * prevent further unmapping attempts.
3678 * This function undoes a series of @unmap_rx_buf calls when we find out
3679 * that the current packet can't be processed right away afterall and we
3680 * need to come back to it later. This is a very rare event and there's
3681 * no effort to make this particularly efficient.
3683 static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q,
3686 struct rx_sw_desc *d;
3690 q->cidx = q->size - 1;
3693 d = &q->sdesc[q->cidx];
3694 d->page = si->frags[frags].page;
3695 d->dma_addr |= RX_UNMAPPED_BUF;
3701 * is_new_response - check if a response is newly written
3702 * @r: the response descriptor
3703 * @q: the response queue
3705 * Returns true if a response descriptor contains a yet unprocessed
3708 static inline bool is_new_response(const struct rsp_ctrl *r,
3709 const struct sge_rspq *q)
3711 return (r->type_gen >> RSPD_GEN_S) == q->gen;
3715 * rspq_next - advance to the next entry in a response queue
3718 * Updates the state of a response queue to advance it to the next entry.
3720 static inline void rspq_next(struct sge_rspq *q)
3722 q->cur_desc = (void *)q->cur_desc + q->iqe_len;
3723 if (unlikely(++q->cidx == q->size)) {
3726 q->cur_desc = q->desc;
3731 * process_responses - process responses from an SGE response queue
3732 * @q: the ingress queue to process
3733 * @budget: how many responses can be processed in this round
3735 * Process responses from an SGE response queue up to the supplied budget.
3736 * Responses include received packets as well as control messages from FW
3739 * Additionally choose the interrupt holdoff time for the next interrupt
3740 * on this queue. If the system is under memory shortage use a fairly
3741 * long delay to help recovery.
3743 static int process_responses(struct sge_rspq *q, int budget)
3746 int budget_left = budget;
3747 const struct rsp_ctrl *rc;
3748 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
3749 struct adapter *adapter = q->adap;
3750 struct sge *s = &adapter->sge;
3752 while (likely(budget_left)) {
3753 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
3754 if (!is_new_response(rc, q)) {
3755 if (q->flush_handler)
3756 q->flush_handler(q);
3761 rsp_type = RSPD_TYPE_G(rc->type_gen);
3762 if (likely(rsp_type == RSPD_TYPE_FLBUF_X)) {
3763 struct page_frag *fp;
3765 const struct rx_sw_desc *rsd;
3766 u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags;
3768 if (len & RSPD_NEWBUF_F) {
3769 if (likely(q->offset > 0)) {
3770 free_rx_bufs(q->adap, &rxq->fl, 1);
3773 len = RSPD_LEN_G(len);
3777 /* gather packet fragments */
3778 for (frags = 0, fp = si.frags; ; frags++, fp++) {
3779 rsd = &rxq->fl.sdesc[rxq->fl.cidx];
3780 bufsz = get_buf_size(adapter, rsd);
3781 fp->page = rsd->page;
3782 fp->offset = q->offset;
3783 fp->size = min(bufsz, len);
3787 unmap_rx_buf(q->adap, &rxq->fl);
3790 si.sgetstamp = SGE_TIMESTAMP_G(
3791 be64_to_cpu(rc->last_flit));
3793 * Last buffer remains mapped so explicitly make it
3794 * coherent for CPU access.
3796 dma_sync_single_for_cpu(q->adap->pdev_dev,
3798 fp->size, DMA_FROM_DEVICE);
3800 si.va = page_address(si.frags[0].page) +
3804 si.nfrags = frags + 1;
3805 ret = q->handler(q, q->cur_desc, &si);
3806 if (likely(ret == 0))
3807 q->offset += ALIGN(fp->size, s->fl_align);
3809 restore_rx_bufs(&si, &rxq->fl, frags);
3810 } else if (likely(rsp_type == RSPD_TYPE_CPL_X)) {
3811 ret = q->handler(q, q->cur_desc, NULL);
3813 ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN);
3816 if (unlikely(ret)) {
3817 /* couldn't process descriptor, back off for recovery */
3818 q->next_intr_params = QINTR_TIMER_IDX_V(NOMEM_TMR_IDX);
3826 if (q->offset >= 0 && fl_cap(&rxq->fl) - rxq->fl.avail >= 16)
3827 __refill_fl(q->adap, &rxq->fl);
3828 return budget - budget_left;
3832 * napi_rx_handler - the NAPI handler for Rx processing
3833 * @napi: the napi instance
3834 * @budget: how many packets we can process in this round
3836 * Handler for new data events when using NAPI. This does not need any
3837 * locking or protection from interrupts as data interrupts are off at
3838 * this point and other adapter interrupts do not interfere (the latter
3839 * in not a concern at all with MSI-X as non-data interrupts then have
3840 * a separate handler).
3842 static int napi_rx_handler(struct napi_struct *napi, int budget)
3844 unsigned int params;
3845 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi);
3849 work_done = process_responses(q, budget);
3850 if (likely(work_done < budget)) {
3853 napi_complete_done(napi, work_done);
3854 timer_index = QINTR_TIMER_IDX_G(q->next_intr_params);
3856 if (q->adaptive_rx) {
3857 if (work_done > max(timer_pkt_quota[timer_index],
3859 timer_index = (timer_index + 1);
3861 timer_index = timer_index - 1;
3863 timer_index = clamp(timer_index, 0, SGE_TIMERREGS - 1);
3864 q->next_intr_params =
3865 QINTR_TIMER_IDX_V(timer_index) |
3867 params = q->next_intr_params;
3869 params = q->next_intr_params;
3870 q->next_intr_params = q->intr_params;
3873 params = QINTR_TIMER_IDX_V(7);
3875 val = CIDXINC_V(work_done) | SEINTARM_V(params);
3877 /* If we don't have access to the new User GTS (T5+), use the old
3878 * doorbell mechanism; otherwise use the new BAR2 mechanism.
3880 if (unlikely(q->bar2_addr == NULL)) {
3881 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
3882 val | INGRESSQID_V((u32)q->cntxt_id));
3884 writel(val | INGRESSQID_V(q->bar2_qid),
3885 q->bar2_addr + SGE_UDB_GTS);
3891 void cxgb4_ethofld_restart(struct tasklet_struct *t)
3893 struct sge_eosw_txq *eosw_txq = from_tasklet(eosw_txq, t,
3897 spin_lock(&eosw_txq->lock);
3898 pktcount = eosw_txq->cidx - eosw_txq->last_cidx;
3900 pktcount += eosw_txq->ndesc;
3903 cxgb4_eosw_txq_free_desc(netdev2adap(eosw_txq->netdev),
3904 eosw_txq, pktcount);
3905 eosw_txq->inuse -= pktcount;
3908 /* There may be some packets waiting for completions. So,
3909 * attempt to send these packets now.
3911 ethofld_xmit(eosw_txq->netdev, eosw_txq);
3912 spin_unlock(&eosw_txq->lock);
3915 /* cxgb4_ethofld_rx_handler - Process ETHOFLD Tx completions
3916 * @q: the response queue that received the packet
3917 * @rsp: the response queue descriptor holding the CPL message
3918 * @si: the gather list of packet fragments
3920 * Process a ETHOFLD Tx completion. Increment the cidx here, but
3921 * free up the descriptors in a tasklet later.
3923 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp,
3924 const struct pkt_gl *si)
3926 u8 opcode = ((const struct rss_header *)rsp)->opcode;
3928 /* skip RSS header */
3931 if (opcode == CPL_FW4_ACK) {
3932 const struct cpl_fw4_ack *cpl;
3933 struct sge_eosw_txq *eosw_txq;
3934 struct eotid_entry *entry;
3935 struct sk_buff *skb;
3940 cpl = (const struct cpl_fw4_ack *)rsp;
3941 eotid = CPL_FW4_ACK_FLOWID_G(ntohl(OPCODE_TID(cpl))) -
3942 q->adap->tids.eotid_base;
3943 entry = cxgb4_lookup_eotid(&q->adap->tids, eotid);
3947 eosw_txq = (struct sge_eosw_txq *)entry->data;
3951 spin_lock(&eosw_txq->lock);
3952 credits = cpl->credits;
3953 while (credits > 0) {
3954 skb = eosw_txq->desc[eosw_txq->cidx].skb;
3958 if (unlikely((eosw_txq->state ==
3959 CXGB4_EO_STATE_FLOWC_OPEN_REPLY ||
3961 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY) &&
3962 eosw_txq->cidx == eosw_txq->flowc_idx)) {
3963 flits = DIV_ROUND_UP(skb->len, 8);
3964 if (eosw_txq->state ==
3965 CXGB4_EO_STATE_FLOWC_OPEN_REPLY)
3966 eosw_txq->state = CXGB4_EO_STATE_ACTIVE;
3968 eosw_txq->state = CXGB4_EO_STATE_CLOSED;
3969 complete(&eosw_txq->completion);
3971 hdr_len = eth_get_headlen(eosw_txq->netdev,
3974 flits = ethofld_calc_tx_flits(q->adap, skb,
3977 eosw_txq_advance_index(&eosw_txq->cidx, 1,
3979 wrlen16 = DIV_ROUND_UP(flits * 8, 16);
3983 eosw_txq->cred += cpl->credits;
3986 spin_unlock(&eosw_txq->lock);
3988 /* Schedule a tasklet to reclaim SKBs and restart ETHOFLD Tx,
3989 * if there were packets waiting for completion.
3991 tasklet_schedule(&eosw_txq->qresume_tsk);
3999 * The MSI-X interrupt handler for an SGE response queue.
4001 irqreturn_t t4_sge_intr_msix(int irq, void *cookie)
4003 struct sge_rspq *q = cookie;
4005 napi_schedule(&q->napi);
4010 * Process the indirect interrupt entries in the interrupt queue and kick off
4011 * NAPI for each queue that has generated an entry.
4013 static unsigned int process_intrq(struct adapter *adap)
4015 unsigned int credits;
4016 const struct rsp_ctrl *rc;
4017 struct sge_rspq *q = &adap->sge.intrq;
4020 spin_lock(&adap->sge.intrq_lock);
4021 for (credits = 0; ; credits++) {
4022 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
4023 if (!is_new_response(rc, q))
4027 if (RSPD_TYPE_G(rc->type_gen) == RSPD_TYPE_INTR_X) {
4028 unsigned int qid = ntohl(rc->pldbuflen_qid);
4030 qid -= adap->sge.ingr_start;
4031 napi_schedule(&adap->sge.ingr_map[qid]->napi);
4037 val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params);
4039 /* If we don't have access to the new User GTS (T5+), use the old
4040 * doorbell mechanism; otherwise use the new BAR2 mechanism.
4042 if (unlikely(q->bar2_addr == NULL)) {
4043 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
4044 val | INGRESSQID_V(q->cntxt_id));
4046 writel(val | INGRESSQID_V(q->bar2_qid),
4047 q->bar2_addr + SGE_UDB_GTS);
4050 spin_unlock(&adap->sge.intrq_lock);
4055 * The MSI interrupt handler, which handles data events from SGE response queues
4056 * as well as error and other async events as they all use the same MSI vector.
4058 static irqreturn_t t4_intr_msi(int irq, void *cookie)
4060 struct adapter *adap = cookie;
4062 if (adap->flags & CXGB4_MASTER_PF)
4063 t4_slow_intr_handler(adap);
4064 process_intrq(adap);
4069 * Interrupt handler for legacy INTx interrupts.
4070 * Handles data events from SGE response queues as well as error and other
4071 * async events as they all use the same interrupt line.
4073 static irqreturn_t t4_intr_intx(int irq, void *cookie)
4075 struct adapter *adap = cookie;
4077 t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
4078 if (((adap->flags & CXGB4_MASTER_PF) && t4_slow_intr_handler(adap)) |
4079 process_intrq(adap))
4081 return IRQ_NONE; /* probably shared interrupt */
4085 * t4_intr_handler - select the top-level interrupt handler
4086 * @adap: the adapter
4088 * Selects the top-level interrupt handler based on the type of interrupts
4089 * (MSI-X, MSI, or INTx).
4091 irq_handler_t t4_intr_handler(struct adapter *adap)
4093 if (adap->flags & CXGB4_USING_MSIX)
4094 return t4_sge_intr_msix;
4095 if (adap->flags & CXGB4_USING_MSI)
4097 return t4_intr_intx;
4100 static void sge_rx_timer_cb(struct timer_list *t)
4104 struct adapter *adap = from_timer(adap, t, sge.rx_timer);
4105 struct sge *s = &adap->sge;
4107 for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++)
4108 for (m = s->starving_fl[i]; m; m &= m - 1) {
4109 struct sge_eth_rxq *rxq;
4110 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
4111 struct sge_fl *fl = s->egr_map[id];
4113 clear_bit(id, s->starving_fl);
4114 smp_mb__after_atomic();
4116 if (fl_starving(adap, fl)) {
4117 rxq = container_of(fl, struct sge_eth_rxq, fl);
4118 if (napi_reschedule(&rxq->rspq.napi))
4121 set_bit(id, s->starving_fl);
4124 /* The remainder of the SGE RX Timer Callback routine is dedicated to
4125 * global Master PF activities like checking for chip ingress stalls,
4128 if (!(adap->flags & CXGB4_MASTER_PF))
4131 t4_idma_monitor(adap, &s->idma_monitor, HZ, RX_QCHECK_PERIOD);
4134 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
4137 static void sge_tx_timer_cb(struct timer_list *t)
4139 struct adapter *adap = from_timer(adap, t, sge.tx_timer);
4140 struct sge *s = &adap->sge;
4141 unsigned long m, period;
4142 unsigned int i, budget;
4144 for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++)
4145 for (m = s->txq_maperr[i]; m; m &= m - 1) {
4146 unsigned long id = __ffs(m) + i * BITS_PER_LONG;
4147 struct sge_uld_txq *txq = s->egr_map[id];
4149 clear_bit(id, s->txq_maperr);
4150 tasklet_schedule(&txq->qresume_tsk);
4153 if (!is_t4(adap->params.chip)) {
4154 struct sge_eth_txq *q = &s->ptptxq;
4157 spin_lock(&adap->ptp_lock);
4158 avail = reclaimable(&q->q);
4161 free_tx_desc(adap, &q->q, avail, false);
4162 q->q.in_use -= avail;
4164 spin_unlock(&adap->ptp_lock);
4167 budget = MAX_TIMER_TX_RECLAIM;
4168 i = s->ethtxq_rover;
4170 budget -= t4_sge_eth_txq_egress_update(adap, &s->ethtxq[i],
4175 if (++i >= s->ethqsets)
4177 } while (i != s->ethtxq_rover);
4178 s->ethtxq_rover = i;
4181 /* If we found too many reclaimable packets schedule a timer
4182 * in the near future to continue where we left off.
4186 /* We reclaimed all reclaimable TX Descriptors, so reschedule
4187 * at the normal period.
4189 period = TX_QCHECK_PERIOD;
4192 mod_timer(&s->tx_timer, jiffies + period);
4196 * bar2_address - return the BAR2 address for an SGE Queue's Registers
4197 * @adapter: the adapter
4198 * @qid: the SGE Queue ID
4199 * @qtype: the SGE Queue Type (Egress or Ingress)
4200 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4202 * Returns the BAR2 address for the SGE Queue Registers associated with
4203 * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also
4204 * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE
4205 * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID"
4206 * Registers are supported (e.g. the Write Combining Doorbell Buffer).
4208 static void __iomem *bar2_address(struct adapter *adapter,
4210 enum t4_bar2_qtype qtype,
4211 unsigned int *pbar2_qid)
4216 ret = t4_bar2_sge_qregs(adapter, qid, qtype, 0,
4217 &bar2_qoffset, pbar2_qid);
4221 return adapter->bar2 + bar2_qoffset;
4224 /* @intr_idx: MSI/MSI-X vector if >=0, -(absolute qid + 1) if < 0
4225 * @cong: < 0 -> no congestion feedback, >= 0 -> congestion channel map
4227 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
4228 struct net_device *dev, int intr_idx,
4229 struct sge_fl *fl, rspq_handler_t hnd,
4230 rspq_flush_handler_t flush_hnd, int cong)
4234 struct sge *s = &adap->sge;
4235 struct port_info *pi = netdev_priv(dev);
4236 int relaxed = !(adap->flags & CXGB4_ROOT_NO_RELAXED_ORDERING);
4238 /* Size needs to be multiple of 16, including status entry. */
4239 iq->size = roundup(iq->size, 16);
4241 iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0,
4242 &iq->phys_addr, NULL, 0,
4243 dev_to_node(adap->pdev_dev));
4247 memset(&c, 0, sizeof(c));
4248 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
4249 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
4250 FW_IQ_CMD_PFN_V(adap->pf) | FW_IQ_CMD_VFN_V(0));
4251 c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F |
4253 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) |
4254 FW_IQ_CMD_IQASYNCH_V(fwevtq) | FW_IQ_CMD_VIID_V(pi->viid) |
4255 FW_IQ_CMD_IQANDST_V(intr_idx < 0) |
4256 FW_IQ_CMD_IQANUD_V(UPDATEDELIVERY_INTERRUPT_X) |
4257 FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx :
4259 c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) |
4260 FW_IQ_CMD_IQGTSMODE_F |
4261 FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) |
4262 FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4));
4263 c.iqsize = htons(iq->size);
4264 c.iqaddr = cpu_to_be64(iq->phys_addr);
4266 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F |
4267 FW_IQ_CMD_IQTYPE_V(cong ? FW_IQ_IQTYPE_NIC
4268 : FW_IQ_IQTYPE_OFLD));
4271 unsigned int chip_ver =
4272 CHELSIO_CHIP_VERSION(adap->params.chip);
4274 /* Allocate the ring for the hardware free list (with space
4275 * for its status page) along with the associated software
4276 * descriptor ring. The free list size needs to be a multiple
4277 * of the Egress Queue Unit and at least 2 Egress Units larger
4278 * than the SGE's Egress Congrestion Threshold
4279 * (fl_starve_thres - 1).
4281 if (fl->size < s->fl_starve_thres - 1 + 2 * 8)
4282 fl->size = s->fl_starve_thres - 1 + 2 * 8;
4283 fl->size = roundup(fl->size, 8);
4284 fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
4285 sizeof(struct rx_sw_desc), &fl->addr,
4286 &fl->sdesc, s->stat_len,
4287 dev_to_node(adap->pdev_dev));
4291 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
4292 c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F |
4293 FW_IQ_CMD_FL0FETCHRO_V(relaxed) |
4294 FW_IQ_CMD_FL0DATARO_V(relaxed) |
4295 FW_IQ_CMD_FL0PADEN_F);
4297 c.iqns_to_fl0congen |=
4298 htonl(FW_IQ_CMD_FL0CNGCHMAP_V(cong) |
4299 FW_IQ_CMD_FL0CONGCIF_F |
4300 FW_IQ_CMD_FL0CONGEN_F);
4301 /* In T6, for egress queue type FL there is internal overhead
4302 * of 16B for header going into FLM module. Hence the maximum
4303 * allowed burst size is 448 bytes. For T4/T5, the hardware
4304 * doesn't coalesce fetch requests if more than 64 bytes of
4305 * Free List pointers are provided, so we use a 128-byte Fetch
4306 * Burst Minimum there (T6 implements coalescing so we can use
4307 * the smaller 64-byte value there).
4309 c.fl0dcaen_to_fl0cidxfthresh =
4310 htons(FW_IQ_CMD_FL0FBMIN_V(chip_ver <= CHELSIO_T5 ?
4311 FETCHBURSTMIN_128B_X :
4312 FETCHBURSTMIN_64B_T6_X) |
4313 FW_IQ_CMD_FL0FBMAX_V((chip_ver <= CHELSIO_T5) ?
4314 FETCHBURSTMAX_512B_X :
4315 FETCHBURSTMAX_256B_X));
4316 c.fl0size = htons(flsz);
4317 c.fl0addr = cpu_to_be64(fl->addr);
4320 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4324 netif_napi_add(dev, &iq->napi, napi_rx_handler, 64);
4325 iq->cur_desc = iq->desc;
4328 iq->next_intr_params = iq->intr_params;
4329 iq->cntxt_id = ntohs(c.iqid);
4330 iq->abs_id = ntohs(c.physiqid);
4331 iq->bar2_addr = bar2_address(adap,
4333 T4_BAR2_QTYPE_INGRESS,
4335 iq->size--; /* subtract status entry */
4338 iq->flush_handler = flush_hnd;
4340 memset(&iq->lro_mgr, 0, sizeof(struct t4_lro_mgr));
4341 skb_queue_head_init(&iq->lro_mgr.lroq);
4343 /* set offset to -1 to distinguish ingress queues without FL */
4344 iq->offset = fl ? 0 : -1;
4346 adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq;
4349 fl->cntxt_id = ntohs(c.fl0id);
4350 fl->avail = fl->pend_cred = 0;
4351 fl->pidx = fl->cidx = 0;
4352 fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0;
4353 adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl;
4355 /* Note, we must initialize the BAR2 Free List User Doorbell
4356 * information before refilling the Free List!
4358 fl->bar2_addr = bar2_address(adap,
4360 T4_BAR2_QTYPE_EGRESS,
4362 refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL);
4365 /* For T5 and later we attempt to set up the Congestion Manager values
4366 * of the new RX Ethernet Queue. This should really be handled by
4367 * firmware because it's more complex than any host driver wants to
4368 * get involved with and it's different per chip and this is almost
4369 * certainly wrong. Firmware would be wrong as well, but it would be
4370 * a lot easier to fix in one place ... For now we do something very
4371 * simple (and hopefully less wrong).
4373 if (!is_t4(adap->params.chip) && cong >= 0) {
4374 u32 param, val, ch_map = 0;
4376 u16 cng_ch_bits_log = adap->params.arch.cng_ch_bits_log;
4378 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
4379 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
4380 FW_PARAMS_PARAM_YZ_V(iq->cntxt_id));
4382 val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X);
4385 CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X);
4386 for (i = 0; i < 4; i++) {
4387 if (cong & (1 << i))
4388 ch_map |= 1 << (i << cng_ch_bits_log);
4390 val |= CONMCTXT_CNGCHMAP_V(ch_map);
4392 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
4395 dev_warn(adap->pdev_dev, "Failed to set Congestion"
4396 " Manager Context for Ingress Queue %d: %d\n",
4397 iq->cntxt_id, -ret);
4406 dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len,
4407 iq->desc, iq->phys_addr);
4410 if (fl && fl->desc) {
4413 dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc),
4414 fl->desc, fl->addr);
4420 static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
4423 q->bar2_addr = bar2_address(adap,
4425 T4_BAR2_QTYPE_EGRESS,
4428 q->cidx = q->pidx = 0;
4429 q->stops = q->restarts = 0;
4430 q->stat = (void *)&q->desc[q->size];
4431 spin_lock_init(&q->db_lock);
4432 adap->sge.egr_map[id - adap->sge.egr_start] = q;
4436 * t4_sge_alloc_eth_txq - allocate an Ethernet TX Queue
4437 * @adap: the adapter
4438 * @txq: the SGE Ethernet TX Queue to initialize
4439 * @dev: the Linux Network Device
4440 * @netdevq: the corresponding Linux TX Queue
4441 * @iqid: the Ingress Queue to which to deliver CIDX Update messages
4442 * @dbqt: whether this TX Queue will use the SGE Doorbell Queue Timers
4444 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
4445 struct net_device *dev, struct netdev_queue *netdevq,
4446 unsigned int iqid, u8 dbqt)
4448 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
4449 struct port_info *pi = netdev_priv(dev);
4450 struct sge *s = &adap->sge;
4451 struct fw_eq_eth_cmd c;
4454 /* Add status entries */
4455 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
4457 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
4458 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
4459 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len,
4460 netdev_queue_numa_node_read(netdevq));
4464 memset(&c, 0, sizeof(c));
4465 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F |
4466 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
4467 FW_EQ_ETH_CMD_PFN_V(adap->pf) |
4468 FW_EQ_ETH_CMD_VFN_V(0));
4469 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F |
4470 FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c));
4472 /* For TX Ethernet Queues using the SGE Doorbell Queue Timer
4473 * mechanism, we use Ingress Queue messages for Hardware Consumer
4474 * Index Updates on the TX Queue. Otherwise we have the Hardware
4475 * write the CIDX Updates into the Status Page at the end of the
4478 c.autoequiqe_to_viid = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE_F |
4479 FW_EQ_ETH_CMD_VIID_V(pi->viid));
4481 c.fetchszm_to_iqid =
4482 htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
4483 FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) |
4484 FW_EQ_ETH_CMD_FETCHRO_F | FW_EQ_ETH_CMD_IQID_V(iqid));
4486 /* Note that the CIDX Flush Threshold should match MAX_TX_RECLAIM. */
4488 htonl(FW_EQ_ETH_CMD_FBMIN_V(chip_ver <= CHELSIO_T5
4489 ? FETCHBURSTMIN_64B_X
4490 : FETCHBURSTMIN_64B_T6_X) |
4491 FW_EQ_ETH_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) |
4492 FW_EQ_ETH_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) |
4493 FW_EQ_ETH_CMD_EQSIZE_V(nentries));
4495 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
4497 /* If we're using the SGE Doorbell Queue Timer mechanism, pass in the
4498 * currently configured Timer Index. THis can be changed later via an
4499 * ethtool -C tx-usecs {Timer Val} command. Note that the SGE
4500 * Doorbell Queue mode is currently automatically enabled in the
4501 * Firmware by setting either AUTOEQUEQE or AUTOEQUIQE ...
4505 cpu_to_be32(FW_EQ_ETH_CMD_TIMEREN_F |
4506 FW_EQ_ETH_CMD_TIMERIX_V(txq->dbqtimerix));
4508 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4510 kfree(txq->q.sdesc);
4511 txq->q.sdesc = NULL;
4512 dma_free_coherent(adap->pdev_dev,
4513 nentries * sizeof(struct tx_desc),
4514 txq->q.desc, txq->q.phys_addr);
4519 txq->q.q_type = CXGB4_TXQ_ETH;
4520 init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd)));
4526 txq->mapping_err = 0;
4532 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
4533 struct net_device *dev, unsigned int iqid,
4534 unsigned int cmplqid)
4536 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
4537 struct port_info *pi = netdev_priv(dev);
4538 struct sge *s = &adap->sge;
4539 struct fw_eq_ctrl_cmd c;
4542 /* Add status entries */
4543 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
4545 txq->q.desc = alloc_ring(adap->pdev_dev, nentries,
4546 sizeof(struct tx_desc), 0, &txq->q.phys_addr,
4547 NULL, 0, dev_to_node(adap->pdev_dev));
4551 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F |
4552 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
4553 FW_EQ_CTRL_CMD_PFN_V(adap->pf) |
4554 FW_EQ_CTRL_CMD_VFN_V(0));
4555 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F |
4556 FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c));
4557 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid));
4558 c.physeqid_pkd = htonl(0);
4559 c.fetchszm_to_iqid =
4560 htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
4561 FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) |
4562 FW_EQ_CTRL_CMD_FETCHRO_F | FW_EQ_CTRL_CMD_IQID_V(iqid));
4564 htonl(FW_EQ_CTRL_CMD_FBMIN_V(chip_ver <= CHELSIO_T5
4565 ? FETCHBURSTMIN_64B_X
4566 : FETCHBURSTMIN_64B_T6_X) |
4567 FW_EQ_CTRL_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) |
4568 FW_EQ_CTRL_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) |
4569 FW_EQ_CTRL_CMD_EQSIZE_V(nentries));
4570 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
4572 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4574 dma_free_coherent(adap->pdev_dev,
4575 nentries * sizeof(struct tx_desc),
4576 txq->q.desc, txq->q.phys_addr);
4581 txq->q.q_type = CXGB4_TXQ_CTRL;
4582 init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid)));
4584 skb_queue_head_init(&txq->sendq);
4585 tasklet_setup(&txq->qresume_tsk, restart_ctrlq);
4590 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
4591 unsigned int cmplqid)
4595 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
4596 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL) |
4597 FW_PARAMS_PARAM_YZ_V(eqid));
4599 return t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
4602 static int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_txq *q,
4603 struct net_device *dev, u32 cmd, u32 iqid)
4605 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
4606 struct port_info *pi = netdev_priv(dev);
4607 struct sge *s = &adap->sge;
4608 struct fw_eq_ofld_cmd c;
4609 u32 fb_min, nentries;
4612 /* Add status entries */
4613 nentries = q->size + s->stat_len / sizeof(struct tx_desc);
4614 q->desc = alloc_ring(adap->pdev_dev, q->size, sizeof(struct tx_desc),
4615 sizeof(struct tx_sw_desc), &q->phys_addr,
4616 &q->sdesc, s->stat_len, NUMA_NO_NODE);
4620 if (chip_ver <= CHELSIO_T5)
4621 fb_min = FETCHBURSTMIN_64B_X;
4623 fb_min = FETCHBURSTMIN_64B_T6_X;
4625 memset(&c, 0, sizeof(c));
4626 c.op_to_vfn = htonl(FW_CMD_OP_V(cmd) | FW_CMD_REQUEST_F |
4627 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
4628 FW_EQ_OFLD_CMD_PFN_V(adap->pf) |
4629 FW_EQ_OFLD_CMD_VFN_V(0));
4630 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F |
4631 FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c));
4632 c.fetchszm_to_iqid =
4633 htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
4634 FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) |
4635 FW_EQ_OFLD_CMD_FETCHRO_F | FW_EQ_OFLD_CMD_IQID_V(iqid));
4637 htonl(FW_EQ_OFLD_CMD_FBMIN_V(fb_min) |
4638 FW_EQ_OFLD_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) |
4639 FW_EQ_OFLD_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) |
4640 FW_EQ_OFLD_CMD_EQSIZE_V(nentries));
4641 c.eqaddr = cpu_to_be64(q->phys_addr);
4643 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4647 dma_free_coherent(adap->pdev_dev,
4648 nentries * sizeof(struct tx_desc),
4649 q->desc, q->phys_addr);
4654 init_txq(adap, q, FW_EQ_OFLD_CMD_EQID_G(ntohl(c.eqid_pkd)));
4658 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
4659 struct net_device *dev, unsigned int iqid,
4660 unsigned int uld_type)
4662 u32 cmd = FW_EQ_OFLD_CMD;
4665 if (unlikely(uld_type == CXGB4_TX_CRYPTO))
4666 cmd = FW_EQ_CTRL_CMD;
4668 ret = t4_sge_alloc_ofld_txq(adap, &txq->q, dev, cmd, iqid);
4672 txq->q.q_type = CXGB4_TXQ_ULD;
4674 skb_queue_head_init(&txq->sendq);
4675 tasklet_setup(&txq->qresume_tsk, restart_ofldq);
4677 txq->mapping_err = 0;
4681 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
4682 struct net_device *dev, u32 iqid)
4686 ret = t4_sge_alloc_ofld_txq(adap, &txq->q, dev, FW_EQ_OFLD_CMD, iqid);
4690 txq->q.q_type = CXGB4_TXQ_ULD;
4691 spin_lock_init(&txq->lock);
4697 txq->mapping_err = 0;
4701 void free_txq(struct adapter *adap, struct sge_txq *q)
4703 struct sge *s = &adap->sge;
4705 dma_free_coherent(adap->pdev_dev,
4706 q->size * sizeof(struct tx_desc) + s->stat_len,
4707 q->desc, q->phys_addr);
4713 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq,
4716 struct sge *s = &adap->sge;
4717 unsigned int fl_id = fl ? fl->cntxt_id : 0xffff;
4719 adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL;
4720 t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
4721 rq->cntxt_id, fl_id, 0xffff);
4722 dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len,
4723 rq->desc, rq->phys_addr);
4724 netif_napi_del(&rq->napi);
4726 rq->cntxt_id = rq->abs_id = 0;
4730 free_rx_bufs(adap, fl, fl->avail);
4731 dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len,
4732 fl->desc, fl->addr);
4741 * t4_free_ofld_rxqs - free a block of consecutive Rx queues
4742 * @adap: the adapter
4743 * @n: number of queues
4744 * @q: pointer to first queue
4746 * Release the resources of a consecutive block of offload Rx queues.
4748 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q)
4750 for ( ; n; n--, q++)
4752 free_rspq_fl(adap, &q->rspq,
4753 q->fl.size ? &q->fl : NULL);
4756 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq)
4759 t4_ofld_eq_free(adap, adap->mbox, adap->pf, 0,
4761 free_tx_desc(adap, &txq->q, txq->q.in_use, false);
4762 kfree(txq->q.sdesc);
4763 free_txq(adap, &txq->q);
4768 * t4_free_sge_resources - free SGE resources
4769 * @adap: the adapter
4771 * Frees resources used by the SGE queue sets.
4773 void t4_free_sge_resources(struct adapter *adap)
4776 struct sge_eth_rxq *eq;
4777 struct sge_eth_txq *etq;
4779 /* stop all Rx queues in order to start them draining */
4780 for (i = 0; i < adap->sge.ethqsets; i++) {
4781 eq = &adap->sge.ethrxq[i];
4783 t4_iq_stop(adap, adap->mbox, adap->pf, 0,
4784 FW_IQ_TYPE_FL_INT_CAP,
4786 eq->fl.size ? eq->fl.cntxt_id : 0xffff,
4790 /* clean up Ethernet Tx/Rx queues */
4791 for (i = 0; i < adap->sge.ethqsets; i++) {
4792 eq = &adap->sge.ethrxq[i];
4794 free_rspq_fl(adap, &eq->rspq,
4795 eq->fl.size ? &eq->fl : NULL);
4797 cxgb4_free_msix_idx_in_bmap(adap, eq->msix->idx);
4801 etq = &adap->sge.ethtxq[i];
4803 t4_eth_eq_free(adap, adap->mbox, adap->pf, 0,
4805 __netif_tx_lock_bh(etq->txq);
4806 free_tx_desc(adap, &etq->q, etq->q.in_use, true);
4807 __netif_tx_unlock_bh(etq->txq);
4808 kfree(etq->q.sdesc);
4809 free_txq(adap, &etq->q);
4813 /* clean up control Tx queues */
4814 for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) {
4815 struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i];
4818 tasklet_kill(&cq->qresume_tsk);
4819 t4_ctrl_eq_free(adap, adap->mbox, adap->pf, 0,
4821 __skb_queue_purge(&cq->sendq);
4822 free_txq(adap, &cq->q);
4826 if (adap->sge.fw_evtq.desc) {
4827 free_rspq_fl(adap, &adap->sge.fw_evtq, NULL);
4828 if (adap->sge.fwevtq_msix_idx >= 0)
4829 cxgb4_free_msix_idx_in_bmap(adap,
4830 adap->sge.fwevtq_msix_idx);
4833 if (adap->sge.nd_msix_idx >= 0)
4834 cxgb4_free_msix_idx_in_bmap(adap, adap->sge.nd_msix_idx);
4836 if (adap->sge.intrq.desc)
4837 free_rspq_fl(adap, &adap->sge.intrq, NULL);
4839 if (!is_t4(adap->params.chip)) {
4840 etq = &adap->sge.ptptxq;
4842 t4_eth_eq_free(adap, adap->mbox, adap->pf, 0,
4844 spin_lock_bh(&adap->ptp_lock);
4845 free_tx_desc(adap, &etq->q, etq->q.in_use, true);
4846 spin_unlock_bh(&adap->ptp_lock);
4847 kfree(etq->q.sdesc);
4848 free_txq(adap, &etq->q);
4852 /* clear the reverse egress queue map */
4853 memset(adap->sge.egr_map, 0,
4854 adap->sge.egr_sz * sizeof(*adap->sge.egr_map));
4857 void t4_sge_start(struct adapter *adap)
4859 adap->sge.ethtxq_rover = 0;
4860 mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
4861 mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
4865 * t4_sge_stop - disable SGE operation
4866 * @adap: the adapter
4868 * Stop tasklets and timers associated with the DMA engine. Note that
4869 * this is effective only if measures have been taken to disable any HW
4870 * events that may restart them.
4872 void t4_sge_stop(struct adapter *adap)
4875 struct sge *s = &adap->sge;
4877 if (s->rx_timer.function)
4878 del_timer_sync(&s->rx_timer);
4879 if (s->tx_timer.function)
4880 del_timer_sync(&s->tx_timer);
4882 if (is_offload(adap)) {
4883 struct sge_uld_txq_info *txq_info;
4885 txq_info = adap->sge.uld_txq_info[CXGB4_TX_OFLD];
4887 struct sge_uld_txq *txq = txq_info->uldtxq;
4889 for_each_ofldtxq(&adap->sge, i) {
4891 tasklet_kill(&txq->qresume_tsk);
4896 if (is_pci_uld(adap)) {
4897 struct sge_uld_txq_info *txq_info;
4899 txq_info = adap->sge.uld_txq_info[CXGB4_TX_CRYPTO];
4901 struct sge_uld_txq *txq = txq_info->uldtxq;
4903 for_each_ofldtxq(&adap->sge, i) {
4905 tasklet_kill(&txq->qresume_tsk);
4910 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) {
4911 struct sge_ctrl_txq *cq = &s->ctrlq[i];
4914 tasklet_kill(&cq->qresume_tsk);
4919 * t4_sge_init_soft - grab core SGE values needed by SGE code
4920 * @adap: the adapter
4922 * We need to grab the SGE operating parameters that we need to have
4923 * in order to do our job and make sure we can live with them.
4926 static int t4_sge_init_soft(struct adapter *adap)
4928 struct sge *s = &adap->sge;
4929 u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu;
4930 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
4931 u32 ingress_rx_threshold;
4934 * Verify that CPL messages are going to the Ingress Queue for
4935 * process_responses() and that only packet data is going to the
4938 if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) !=
4939 RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) {
4940 dev_err(adap->pdev_dev, "bad SGE CPL MODE\n");
4945 * Validate the Host Buffer Register Array indices that we want to
4948 * XXX Note that we should really read through the Host Buffer Size
4949 * XXX register array and find the indices of the Buffer Sizes which
4950 * XXX meet our needs!
4952 #define READ_FL_BUF(x) \
4953 t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32))
4955 fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);
4956 fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);
4957 fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF);
4958 fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF);
4960 /* We only bother using the Large Page logic if the Large Page Buffer
4961 * is larger than our Page Size Buffer.
4963 if (fl_large_pg <= fl_small_pg)
4968 /* The Page Size Buffer must be exactly equal to our Page Size and the
4969 * Large Page Size Buffer should be 0 (per above) or a power of 2.
4971 if (fl_small_pg != PAGE_SIZE ||
4972 (fl_large_pg & (fl_large_pg-1)) != 0) {
4973 dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n",
4974 fl_small_pg, fl_large_pg);
4978 s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT;
4980 if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) ||
4981 fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) {
4982 dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n",
4983 fl_small_mtu, fl_large_mtu);
4988 * Retrieve our RX interrupt holdoff timer values and counter
4989 * threshold values from the SGE parameters.
4991 timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A);
4992 timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A);
4993 timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A);
4994 s->timer_val[0] = core_ticks_to_us(adap,
4995 TIMERVALUE0_G(timer_value_0_and_1));
4996 s->timer_val[1] = core_ticks_to_us(adap,
4997 TIMERVALUE1_G(timer_value_0_and_1));
4998 s->timer_val[2] = core_ticks_to_us(adap,
4999 TIMERVALUE2_G(timer_value_2_and_3));
5000 s->timer_val[3] = core_ticks_to_us(adap,
5001 TIMERVALUE3_G(timer_value_2_and_3));
5002 s->timer_val[4] = core_ticks_to_us(adap,
5003 TIMERVALUE4_G(timer_value_4_and_5));
5004 s->timer_val[5] = core_ticks_to_us(adap,
5005 TIMERVALUE5_G(timer_value_4_and_5));
5007 ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);
5008 s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
5009 s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold);
5010 s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold);
5011 s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold);
5017 * t4_sge_init - initialize SGE
5018 * @adap: the adapter
5020 * Perform low-level SGE code initialization needed every time after a
5023 int t4_sge_init(struct adapter *adap)
5025 struct sge *s = &adap->sge;
5026 u32 sge_control, sge_conm_ctrl;
5027 int ret, egress_threshold;
5030 * Ingress Padding Boundary and Egress Status Page Size are set up by
5031 * t4_fixup_host_params().
5033 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
5034 s->pktshift = PKTSHIFT_G(sge_control);
5035 s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64;
5037 s->fl_align = t4_fl_pkt_align(adap);
5038 ret = t4_sge_init_soft(adap);
5043 * A FL with <= fl_starve_thres buffers is starving and a periodic
5044 * timer will attempt to refill it. This needs to be larger than the
5045 * SGE's Egress Congestion Threshold. If it isn't, then we can get
5046 * stuck waiting for new packets while the SGE is waiting for us to
5047 * give it more Free List entries. (Note that the SGE's Egress
5048 * Congestion Threshold is in units of 2 Free List pointers.) For T4,
5049 * there was only a single field to control this. For T5 there's the
5050 * original field which now only applies to Unpacked Mode Free List
5051 * buffers and a new field which only applies to Packed Mode Free List
5054 sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A);
5055 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
5057 egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl);
5060 egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
5063 egress_threshold = T6_EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
5066 dev_err(adap->pdev_dev, "Unsupported Chip version %d\n",
5067 CHELSIO_CHIP_VERSION(adap->params.chip));
5070 s->fl_starve_thres = 2*egress_threshold + 1;
5072 t4_idma_monitor_init(adap, &s->idma_monitor);
5074 /* Set up timers used for recuring callbacks to process RX and TX
5075 * administrative tasks.
5077 timer_setup(&s->rx_timer, sge_rx_timer_cb, 0);
5078 timer_setup(&s->tx_timer, sge_tx_timer_cb, 0);
5080 spin_lock_init(&s->intrq_lock);