drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <asm/uaccess.h>
  64
  65 #include "cxgb4.h"
  66 #include "t4_regs.h"
  67 #include "t4_msg.h"
  68 #include "t4fw_api.h"
  69 #include "l2t.h"
  70
  71 #define DRV_VERSION "2.0.0-ko"
  72 #define DRV_DESC "Chelsio T4/T5 Network Driver"
  73
  74 /*
  75  * Max interrupt hold-off timer value in us.  Queues fall back to this value
  76  * under extreme memory pressure so it's largish to give the system time to
  77  * recover.
  78  */
  79 #define MAX_SGE_TIMERVAL 200U
  80
  81 enum {
  82         /*
  83          * Physical Function provisioning constants.
  84          */
  85         PFRES_NVI = 4,                  /* # of Virtual Interfaces */
  86         PFRES_NETHCTRL = 128,           /* # of EQs used for ETH or CTRL Qs */
  87         PFRES_NIQFLINT = 128,           /* # of ingress Qs/w Free List(s)/intr
  88                                          */
  89         PFRES_NEQ = 256,                /* # of egress queues */
  90         PFRES_NIQ = 0,                  /* # of ingress queues */
  91         PFRES_TC = 0,                   /* PCI-E traffic class */
  92         PFRES_NEXACTF = 128,            /* # of exact MPS filters */
  93
  94         PFRES_R_CAPS = FW_CMD_CAP_PF,
  95         PFRES_WX_CAPS = FW_CMD_CAP_PF,
  96
  97 #ifdef CONFIG_PCI_IOV
  98         /*
  99          * Virtual Function provisioning constants.  We need two extra Ingress
 100          * Queues with Interrupt capability to serve as the VF's Firmware
 101          * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
 102          * neither will have Free Lists associated with them).  For each
 103          * Ethernet/Control Egress Queue and for each Free List, we need an
 104          * Egress Context.
 105          */
 106         VFRES_NPORTS = 1,               /* # of "ports" per VF */
 107         VFRES_NQSETS = 2,               /* # of "Queue Sets" per VF */
 108
 109         VFRES_NVI = VFRES_NPORTS,       /* # of Virtual Interfaces */
 110         VFRES_NETHCTRL = VFRES_NQSETS,  /* # of EQs used for ETH or CTRL Qs */
 111         VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
 112         VFRES_NEQ = VFRES_NQSETS*2,     /* # of egress queues */
 113         VFRES_NIQ = 0,                  /* # of non-fl/int ingress queues */
 114         VFRES_TC = 0,                   /* PCI-E traffic class */
 115         VFRES_NEXACTF = 16,             /* # of exact MPS filters */
 116
 117         VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
 118         VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
 119 #endif
 120 };
 121
 122 /*
 123  * Provide a Port Access Rights Mask for the specified PF/VF.  This is very
 124  * static and likely not to be useful in the long run.  We really need to
 125  * implement some form of persistent configuration which the firmware
 126  * controls.
 127  */
 128 static unsigned int pfvfres_pmask(struct adapter *adapter,
 129                                   unsigned int pf, unsigned int vf)
 130 {
 131         unsigned int portn, portvec;
 132
 133         /*
 134          * Give PF's access to all of the ports.
 135          */
 136         if (vf == 0)
 137                 return FW_PFVF_CMD_PMASK_MASK;
 138
 139         /*
 140          * For VFs, we'll assign them access to the ports based purely on the
 141          * PF.  We assign active ports in order, wrapping around if there are
 142          * fewer active ports than PFs: e.g. active port[pf % nports].
 143          * Unfortunately the adapter's port_info structs haven't been
 144          * initialized yet so we have to compute this.
 145          */
 146         if (adapter->params.nports == 0)
 147                 return 0;
 148
 149         portn = pf % adapter->params.nports;
 150         portvec = adapter->params.portvec;
 151         for (;;) {
 152                 /*
 153                  * Isolate the lowest set bit in the port vector.  If we're at
 154                  * the port number that we want, return that as the pmask.
 155                  * otherwise mask that bit out of the port vector and
 156                  * decrement our port number ...
 157                  */
 158                 unsigned int pmask = portvec ^ (portvec & (portvec-1));
 159                 if (portn == 0)
 160                         return pmask;
 161                 portn--;
 162                 portvec &= ~pmask;
 163         }
 164         /*NOTREACHED*/
 165 }
 166
 167 enum {
 168         MAX_TXQ_ENTRIES      = 16384,
 169         MAX_CTRL_TXQ_ENTRIES = 1024,
 170         MAX_RSPQ_ENTRIES     = 16384,
 171         MAX_RX_BUFFERS       = 16384,
 172         MIN_TXQ_ENTRIES      = 32,
 173         MIN_CTRL_TXQ_ENTRIES = 32,
 174         MIN_RSPQ_ENTRIES     = 128,
 175         MIN_FL_ENTRIES       = 16
 176 };
 177
 178 /* Host shadow copy of ingress filter entry.  This is in host native format
 179  * and doesn't match the ordering or bit order, etc. of the hardware of the
 180  * firmware command.  The use of bit-field structure elements is purely to
 181  * remind ourselves of the field size limitations and save memory in the case
 182  * where the filter table is large.
 183  */
 184 struct filter_entry {
 185         /* Administrative fields for filter.
 186          */
 187         u32 valid:1;            /* filter allocated and valid */
 188         u32 locked:1;           /* filter is administratively locked */
 189
 190         u32 pending:1;          /* filter action is pending firmware reply */
 191         u32 smtidx:8;           /* Source MAC Table index for smac */
 192         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 193
 194         /* The filter itself.  Most of this is a straight copy of information
 195          * provided by the extended ioctl().  Some fields are translated to
 196          * internal forms -- for instance the Ingress Queue ID passed in from
 197          * the ioctl() is translated into the Absolute Ingress Queue ID.
 198          */
 199         struct ch_filter_specification fs;
 200 };
 201
 202 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
 203                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
 204                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 205
 206 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
 207
 208 static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
 209         CH_DEVICE(0xa000, 0),  /* PE10K */
 210         CH_DEVICE(0x4001, -1),
 211         CH_DEVICE(0x4002, -1),
 212         CH_DEVICE(0x4003, -1),
 213         CH_DEVICE(0x4004, -1),
 214         CH_DEVICE(0x4005, -1),
 215         CH_DEVICE(0x4006, -1),
 216         CH_DEVICE(0x4007, -1),
 217         CH_DEVICE(0x4008, -1),
 218         CH_DEVICE(0x4009, -1),
 219         CH_DEVICE(0x400a, -1),
 220         CH_DEVICE(0x4401, 4),
 221         CH_DEVICE(0x4402, 4),
 222         CH_DEVICE(0x4403, 4),
 223         CH_DEVICE(0x4404, 4),
 224         CH_DEVICE(0x4405, 4),
 225         CH_DEVICE(0x4406, 4),
 226         CH_DEVICE(0x4407, 4),
 227         CH_DEVICE(0x4408, 4),
 228         CH_DEVICE(0x4409, 4),
 229         CH_DEVICE(0x440a, 4),
 230         CH_DEVICE(0x440d, 4),
 231         CH_DEVICE(0x440e, 4),
 232         CH_DEVICE(0x5001, 5),
 233         CH_DEVICE(0x5002, 5),
 234         CH_DEVICE(0x5003, 5),
 235         CH_DEVICE(0x5004, 5),
 236         CH_DEVICE(0x5005, 5),
 237         CH_DEVICE(0x5006, 5),
 238         CH_DEVICE(0x5007, 5),
 239         CH_DEVICE(0x5008, 5),
 240         CH_DEVICE(0x5009, 5),
 241         CH_DEVICE(0x500A, 5),
 242         CH_DEVICE(0x500B, 5),
 243         CH_DEVICE(0x500C, 5),
 244         CH_DEVICE(0x500D, 5),
 245         CH_DEVICE(0x500E, 5),
 246         CH_DEVICE(0x500F, 5),
 247         CH_DEVICE(0x5010, 5),
 248         CH_DEVICE(0x5011, 5),
 249         CH_DEVICE(0x5012, 5),
 250         CH_DEVICE(0x5013, 5),
 251         CH_DEVICE(0x5401, 5),
 252         CH_DEVICE(0x5402, 5),
 253         CH_DEVICE(0x5403, 5),
 254         CH_DEVICE(0x5404, 5),
 255         CH_DEVICE(0x5405, 5),
 256         CH_DEVICE(0x5406, 5),
 257         CH_DEVICE(0x5407, 5),
 258         CH_DEVICE(0x5408, 5),
 259         CH_DEVICE(0x5409, 5),
 260         CH_DEVICE(0x540A, 5),
 261         CH_DEVICE(0x540B, 5),
 262         CH_DEVICE(0x540C, 5),
 263         CH_DEVICE(0x540D, 5),
 264         CH_DEVICE(0x540E, 5),
 265         CH_DEVICE(0x540F, 5),
 266         CH_DEVICE(0x5410, 5),
 267         CH_DEVICE(0x5411, 5),
 268         CH_DEVICE(0x5412, 5),
 269         CH_DEVICE(0x5413, 5),
 270         { 0, }
 271 };
 272
 273 #define FW_FNAME "cxgb4/t4fw.bin"
 274 #define FW5_FNAME "cxgb4/t5fw.bin"
 275 #define FW_CFNAME "cxgb4/t4-config.txt"
 276 #define FW5_CFNAME "cxgb4/t5-config.txt"
 277
 278 MODULE_DESCRIPTION(DRV_DESC);
 279 MODULE_AUTHOR("Chelsio Communications");
 280 MODULE_LICENSE("Dual BSD/GPL");
 281 MODULE_VERSION(DRV_VERSION);
 282 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 283 MODULE_FIRMWARE(FW_FNAME);
 284 MODULE_FIRMWARE(FW5_FNAME);
 285
 286 /*
 287  * Normally we're willing to become the firmware's Master PF but will be happy
 288  * if another PF has already become the Master and initialized the adapter.
 289  * Setting "force_init" will cause this driver to forcibly establish itself as
 290  * the Master PF and initialize the adapter.
 291  */
 292 static uint force_init;
 293
 294 module_param(force_init, uint, 0644);
 295 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
 296
 297 /*
 298  * Normally if the firmware we connect to has Configuration File support, we
 299  * use that and only fall back to the old Driver-based initialization if the
 300  * Configuration File fails for some reason.  If force_old_init is set, then
 301  * we'll always use the old Driver-based initialization sequence.
 302  */
 303 static uint force_old_init;
 304
 305 module_param(force_old_init, uint, 0644);
 306 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
 307
 308 static int dflt_msg_enable = DFLT_MSG_ENABLE;
 309
 310 module_param(dflt_msg_enable, int, 0644);
 311 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
 312
 313 /*
 314  * The driver uses the best interrupt scheme available on a platform in the
 315  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 316  * of these schemes the driver may consider as follows:
 317  *
 318  * msi = 2: choose from among all three options
 319  * msi = 1: only consider MSI and INTx interrupts
 320  * msi = 0: force INTx interrupts
 321  */
 322 static int msi = 2;
 323
 324 module_param(msi, int, 0644);
 325 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 326
 327 /*
 328  * Queue interrupt hold-off timer values.  Queues default to the first of these
 329  * upon creation.
 330  */
 331 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
 332
 333 module_param_array(intr_holdoff, uint, NULL, 0644);
 334 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
 335                  "0..4 in microseconds");
 336
 337 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
 338
 339 module_param_array(intr_cnt, uint, NULL, 0644);
 340 MODULE_PARM_DESC(intr_cnt,
 341                  "thresholds 1..3 for queue interrupt packet counters");
 342
 343 /*
 344  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 345  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 346  * boundaries.  This is a requirement for many architectures which will throw
 347  * a machine check fault if an attempt is made to access one of the 4-byte IP
 348  * header fields on a non-4-byte boundary.  And it's a major performance issue
 349  * even on some architectures which allow it like some implementations of the
 350  * x86 ISA.  However, some architectures don't mind this and for some very
 351  * edge-case performance sensitive applications (like forwarding large volumes
 352  * of small packets), setting this DMA offset to 0 will decrease the number of
 353  * PCI-E Bus transfers enough to measurably affect performance.
 354  */
 355 static int rx_dma_offset = 2;
 356
 357 static bool vf_acls;
 358
 359 #ifdef CONFIG_PCI_IOV
 360 module_param(vf_acls, bool, 0644);
 361 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
 362
 363 /* Configure the number of PCI-E Virtual Function which are to be instantiated
 364  * on SR-IOV Capable Physical Functions.
 365  */
 366 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
 367
 368 module_param_array(num_vf, uint, NULL, 0644);
 369 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
 370 #endif
 371
 372 /*
 373  * The filter TCAM has a fixed portion and a variable portion.  The fixed
 374  * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
 375  * ports.  The variable portion is 36 bits which can include things like Exact
 376  * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
 377  * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
 378  * far exceed the 36-bit budget for this "compressed" header portion of the
 379  * filter.  Thus, we have a scarce resource which must be carefully managed.
 380  *
 381  * By default we set this up to mostly match the set of filter matching
 382  * capabilities of T3 but with accommodations for some of T4's more
 383  * interesting features:
 384  *
 385  *   { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
 386  *     [Inner] VLAN (17), Port (3), FCoE (1) }
 387  */
 388 enum {
 389         TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
 390         TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
 391         TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
 392 };
 393
 394 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
 395
 396 module_param(tp_vlan_pri_map, uint, 0644);
 397 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
 398
 399 static struct dentry *cxgb4_debugfs_root;
 400
 401 static LIST_HEAD(adapter_list);
 402 static DEFINE_MUTEX(uld_mutex);
 403 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
 404 static const char *uld_str[] = { "RDMA", "iSCSI" };
 405
 406 static void link_report(struct net_device *dev)
 407 {
 408         if (!netif_carrier_ok(dev))
 409                 netdev_info(dev, "link down\n");
 410         else {
 411                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 412
 413                 const char *s = "10Mbps";
 414                 const struct port_info *p = netdev_priv(dev);
 415
 416                 switch (p->link_cfg.speed) {
 417                 case SPEED_10000:
 418                         s = "10Gbps";
 419                         break;
 420                 case SPEED_1000:
 421                         s = "1000Mbps";
 422                         break;
 423                 case SPEED_100:
 424                         s = "100Mbps";
 425                         break;
 426                 }
 427
 428                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 429                             fc[p->link_cfg.fc]);
 430         }
 431 }
 432
 433 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 434 {
 435         struct net_device *dev = adapter->port[port_id];
 436
 437         /* Skip changes from disabled ports. */
 438         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 439                 if (link_stat)
 440                         netif_carrier_on(dev);
 441                 else
 442                         netif_carrier_off(dev);
 443
 444                 link_report(dev);
 445         }
 446 }
 447
 448 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 449 {
 450         static const char *mod_str[] = {
 451                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 452         };
 453
 454         const struct net_device *dev = adap->port[port_id];
 455         const struct port_info *pi = netdev_priv(dev);
 456
 457         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 458                 netdev_info(dev, "port module unplugged\n");
 459         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 460                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 461 }
 462
 463 /*
 464  * Configure the exact and hash address filters to handle a port's multicast
 465  * and secondary unicast MAC addresses.
 466  */
 467 static int set_addr_filters(const struct net_device *dev, bool sleep)
 468 {
 469         u64 mhash = 0;
 470         u64 uhash = 0;
 471         bool free = true;
 472         u16 filt_idx[7];
 473         const u8 *addr[7];
 474         int ret, naddr = 0;
 475         const struct netdev_hw_addr *ha;
 476         int uc_cnt = netdev_uc_count(dev);
 477         int mc_cnt = netdev_mc_count(dev);
 478         const struct port_info *pi = netdev_priv(dev);
 479         unsigned int mb = pi->adapter->fn;
 480
 481         /* first do the secondary unicast addresses */
 482         netdev_for_each_uc_addr(ha, dev) {
 483                 addr[naddr++] = ha->addr;
 484                 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 485                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 486                                         naddr, addr, filt_idx, &uhash, sleep);
 487                         if (ret < 0)
 488                                 return ret;
 489
 490                         free = false;
 491                         naddr = 0;
 492                 }
 493         }
 494
 495         /* next set up the multicast addresses */
 496         netdev_for_each_mc_addr(ha, dev) {
 497                 addr[naddr++] = ha->addr;
 498                 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 499                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 500                                         naddr, addr, filt_idx, &mhash, sleep);
 501                         if (ret < 0)
 502                                 return ret;
 503
 504                         free = false;
 505                         naddr = 0;
 506                 }
 507         }
 508
 509         return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
 510                                 uhash | mhash, sleep);
 511 }
 512
 513 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 514 module_param(dbfifo_int_thresh, int, 0644);
 515 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 516
 517 /*
 518  * usecs to sleep while draining the dbfifo
 519  */
 520 static int dbfifo_drain_delay = 1000;
 521 module_param(dbfifo_drain_delay, int, 0644);
 522 MODULE_PARM_DESC(dbfifo_drain_delay,
 523                  "usecs to sleep while draining the dbfifo");
 524
 525 /*
 526  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 527  * If @mtu is -1 it is left unchanged.
 528  */
 529 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 530 {
 531         int ret;
 532         struct port_info *pi = netdev_priv(dev);
 533
 534         ret = set_addr_filters(dev, sleep_ok);
 535         if (ret == 0)
 536                 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
 537                                     (dev->flags & IFF_PROMISC) ? 1 : 0,
 538                                     (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 539                                     sleep_ok);
 540         return ret;
 541 }
 542
 543 static struct workqueue_struct *workq;
 544
 545 /**
 546  *      link_start - enable a port
 547  *      @dev: the port to enable
 548  *
 549  *      Performs the MAC and PHY actions needed to enable a port.
 550  */
 551 static int link_start(struct net_device *dev)
 552 {
 553         int ret;
 554         struct port_info *pi = netdev_priv(dev);
 555         unsigned int mb = pi->adapter->fn;
 556
 557         /*
 558          * We do not set address filters and promiscuity here, the stack does
 559          * that step explicitly.
 560          */
 561         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 562                             !!(dev->features & NETIF_F_HW_VLAN_RX), true);
 563         if (ret == 0) {
 564                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 565                                     pi->xact_addr_filt, dev->dev_addr, true,
 566                                     true);
 567                 if (ret >= 0) {
 568                         pi->xact_addr_filt = ret;
 569                         ret = 0;
 570                 }
 571         }
 572         if (ret == 0)
 573                 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
 574                                     &pi->link_cfg);
 575         if (ret == 0)
 576                 ret = t4_enable_vi(pi->adapter, mb, pi->viid, true, true);
 577         return ret;
 578 }
 579
 580 /* Clear a filter and release any of its resources that we own.  This also
 581  * clears the filter's "pending" status.
 582  */
 583 static void clear_filter(struct adapter *adap, struct filter_entry *f)
 584 {
 585         /* If the new or old filter have loopback rewriteing rules then we'll
 586          * need to free any existing Layer Two Table (L2T) entries of the old
 587          * filter rule.  The firmware will handle freeing up any Source MAC
 588          * Table (SMT) entries used for rewriting Source MAC Addresses in
 589          * loopback rules.
 590          */
 591         if (f->l2t)
 592                 cxgb4_l2t_release(f->l2t);
 593
 594         /* The zeroing of the filter rule below clears the filter valid,
 595          * pending, locked flags, l2t pointer, etc. so it's all we need for
 596          * this operation.
 597          */
 598         memset(f, 0, sizeof(*f));
 599 }
 600
 601 /* Handle a filter write/deletion reply.
 602  */
 603 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
 604 {
 605         unsigned int idx = GET_TID(rpl);
 606         unsigned int nidx = idx - adap->tids.ftid_base;
 607         unsigned int ret;
 608         struct filter_entry *f;
 609
 610         if (idx >= adap->tids.ftid_base && nidx <
 611            (adap->tids.nftids + adap->tids.nsftids)) {
 612                 idx = nidx;
 613                 ret = GET_TCB_COOKIE(rpl->cookie);
 614                 f = &adap->tids.ftid_tab[idx];
 615
 616                 if (ret == FW_FILTER_WR_FLT_DELETED) {
 617                         /* Clear the filter when we get confirmation from the
 618                          * hardware that the filter has been deleted.
 619                          */
 620                         clear_filter(adap, f);
 621                 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
 622                         dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
 623                                 idx);
 624                         clear_filter(adap, f);
 625                 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
 626                         f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
 627                         f->pending = 0;  /* asynchronous setup completed */
 628                         f->valid = 1;
 629                 } else {
 630                         /* Something went wrong.  Issue a warning about the
 631                          * problem and clear everything out.
 632                          */
 633                         dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
 634                                 idx, ret);
 635                         clear_filter(adap, f);
 636                 }
 637         }
 638 }
 639
 640 /* Response queue handler for the FW event queue.
 641  */
 642 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 643                           const struct pkt_gl *gl)
 644 {
 645         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 646
 647         rsp++;                                          /* skip RSS header */
 648         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 649                 const struct cpl_sge_egr_update *p = (void *)rsp;
 650                 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
 651                 struct sge_txq *txq;
 652
 653                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 654                 txq->restarts++;
 655                 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
 656                         struct sge_eth_txq *eq;
 657
 658                         eq = container_of(txq, struct sge_eth_txq, q);
 659                         netif_tx_wake_queue(eq->txq);
 660                 } else {
 661                         struct sge_ofld_txq *oq;
 662
 663                         oq = container_of(txq, struct sge_ofld_txq, q);
 664                         tasklet_schedule(&oq->qresume_tsk);
 665                 }
 666         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 667                 const struct cpl_fw6_msg *p = (void *)rsp;
 668
 669                 if (p->type == 0)
 670                         t4_handle_fw_rpl(q->adap, p->data);
 671         } else if (opcode == CPL_L2T_WRITE_RPL) {
 672                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 673
 674                 do_l2t_write_rpl(q->adap, p);
 675         } else if (opcode == CPL_SET_TCB_RPL) {
 676                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 677
 678                 filter_rpl(q->adap, p);
 679         } else
 680                 dev_err(q->adap->pdev_dev,
 681                         "unexpected CPL %#x on FW event queue\n", opcode);
 682         return 0;
 683 }
 684
 685 /**
 686  *      uldrx_handler - response queue handler for ULD queues
 687  *      @q: the response queue that received the packet
 688  *      @rsp: the response queue descriptor holding the offload message
 689  *      @gl: the gather list of packet fragments
 690  *
 691  *      Deliver an ingress offload packet to a ULD.  All processing is done by
 692  *      the ULD, we just maintain statistics.
 693  */
 694 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
 695                          const struct pkt_gl *gl)
 696 {
 697         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
 698
 699         if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
 700                 rxq->stats.nomem++;
 701                 return -1;
 702         }
 703         if (gl == NULL)
 704                 rxq->stats.imm++;
 705         else if (gl == CXGB4_MSG_AN)
 706                 rxq->stats.an++;
 707         else
 708                 rxq->stats.pkts++;
 709         return 0;
 710 }
 711
 712 static void disable_msi(struct adapter *adapter)
 713 {
 714         if (adapter->flags & USING_MSIX) {
 715                 pci_disable_msix(adapter->pdev);
 716                 adapter->flags &= ~USING_MSIX;
 717         } else if (adapter->flags & USING_MSI) {
 718                 pci_disable_msi(adapter->pdev);
 719                 adapter->flags &= ~USING_MSI;
 720         }
 721 }
 722
 723 /*
 724  * Interrupt handler for non-data events used with MSI-X.
 725  */
 726 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 727 {
 728         struct adapter *adap = cookie;
 729
 730         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
 731         if (v & PFSW) {
 732                 adap->swintr = 1;
 733                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
 734         }
 735         t4_slow_intr_handler(adap);
 736         return IRQ_HANDLED;
 737 }
 738
 739 /*
 740  * Name the MSI-X interrupts.
 741  */
 742 static void name_msix_vecs(struct adapter *adap)
 743 {
 744         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 745
 746         /* non-data interrupts */
 747         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 748
 749         /* FW events */
 750         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 751                  adap->port[0]->name);
 752
 753         /* Ethernet queues */
 754         for_each_port(adap, j) {
 755                 struct net_device *d = adap->port[j];
 756                 const struct port_info *pi = netdev_priv(d);
 757
 758                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 759                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 760                                  d->name, i);
 761         }
 762
 763         /* offload queues */
 764         for_each_ofldrxq(&adap->sge, i)
 765                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
 766                          adap->port[0]->name, i);
 767
 768         for_each_rdmarxq(&adap->sge, i)
 769                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
 770                          adap->port[0]->name, i);
 771 }
 772
 773 static int request_msix_queue_irqs(struct adapter *adap)
 774 {
 775         struct sge *s = &adap->sge;
 776         int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, msi_index = 2;
 777
 778         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 779                           adap->msix_info[1].desc, &s->fw_evtq);
 780         if (err)
 781                 return err;
 782
 783         for_each_ethrxq(s, ethqidx) {
 784                 err = request_irq(adap->msix_info[msi_index].vec,
 785                                   t4_sge_intr_msix, 0,
 786                                   adap->msix_info[msi_index].desc,
 787                                   &s->ethrxq[ethqidx].rspq);
 788                 if (err)
 789                         goto unwind;
 790                 msi_index++;
 791         }
 792         for_each_ofldrxq(s, ofldqidx) {
 793                 err = request_irq(adap->msix_info[msi_index].vec,
 794                                   t4_sge_intr_msix, 0,
 795                                   adap->msix_info[msi_index].desc,
 796                                   &s->ofldrxq[ofldqidx].rspq);
 797                 if (err)
 798                         goto unwind;
 799                 msi_index++;
 800         }
 801         for_each_rdmarxq(s, rdmaqidx) {
 802                 err = request_irq(adap->msix_info[msi_index].vec,
 803                                   t4_sge_intr_msix, 0,
 804                                   adap->msix_info[msi_index].desc,
 805                                   &s->rdmarxq[rdmaqidx].rspq);
 806                 if (err)
 807                         goto unwind;
 808                 msi_index++;
 809         }
 810         return 0;
 811
 812 unwind:
 813         while (--rdmaqidx >= 0)
 814                 free_irq(adap->msix_info[--msi_index].vec,
 815                          &s->rdmarxq[rdmaqidx].rspq);
 816         while (--ofldqidx >= 0)
 817                 free_irq(adap->msix_info[--msi_index].vec,
 818                          &s->ofldrxq[ofldqidx].rspq);
 819         while (--ethqidx >= 0)
 820                 free_irq(adap->msix_info[--msi_index].vec,
 821                          &s->ethrxq[ethqidx].rspq);
 822         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 823         return err;
 824 }
 825
 826 static void free_msix_queue_irqs(struct adapter *adap)
 827 {
 828         int i, msi_index = 2;
 829         struct sge *s = &adap->sge;
 830
 831         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 832         for_each_ethrxq(s, i)
 833                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
 834         for_each_ofldrxq(s, i)
 835                 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
 836         for_each_rdmarxq(s, i)
 837                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
 838 }
 839
 840 /**
 841  *      write_rss - write the RSS table for a given port
 842  *      @pi: the port
 843  *      @queues: array of queue indices for RSS
 844  *
 845  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 846  *      packets to the Rx queues in @queues.
 847  */
 848 static int write_rss(const struct port_info *pi, const u16 *queues)
 849 {
 850         u16 *rss;
 851         int i, err;
 852         const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
 853
 854         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
 855         if (!rss)
 856                 return -ENOMEM;
 857
 858         /* map the queue indices to queue ids */
 859         for (i = 0; i < pi->rss_size; i++, queues++)
 860                 rss[i] = q[*queues].rspq.abs_id;
 861
 862         err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
 863                                   pi->rss_size, rss, pi->rss_size);
 864         kfree(rss);
 865         return err;
 866 }
 867
 868 /**
 869  *      setup_rss - configure RSS
 870  *      @adap: the adapter
 871  *
 872  *      Sets up RSS for each port.
 873  */
 874 static int setup_rss(struct adapter *adap)
 875 {
 876         int i, err;
 877
 878         for_each_port(adap, i) {
 879                 const struct port_info *pi = adap2pinfo(adap, i);
 880
 881                 err = write_rss(pi, pi->rss);
 882                 if (err)
 883                         return err;
 884         }
 885         return 0;
 886 }
 887
 888 /*
 889  * Return the channel of the ingress queue with the given qid.
 890  */
 891 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
 892 {
 893         qid -= p->ingr_start;
 894         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
 895 }
 896
 897 /*
 898  * Wait until all NAPI handlers are descheduled.
 899  */
 900 static void quiesce_rx(struct adapter *adap)
 901 {
 902         int i;
 903
 904         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
 905                 struct sge_rspq *q = adap->sge.ingr_map[i];
 906
 907                 if (q && q->handler)
 908                         napi_disable(&q->napi);
 909         }
 910 }
 911
 912 /*
 913  * Enable NAPI scheduling and interrupt generation for all Rx queues.
 914  */
 915 static void enable_rx(struct adapter *adap)
 916 {
 917         int i;
 918
 919         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
 920                 struct sge_rspq *q = adap->sge.ingr_map[i];
 921
 922                 if (!q)
 923                         continue;
 924                 if (q->handler)
 925                         napi_enable(&q->napi);
 926                 /* 0-increment GTS to start the timer and enable interrupts */
 927                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
 928                              SEINTARM(q->intr_params) |
 929                              INGRESSQID(q->cntxt_id));
 930         }
 931 }
 932
 933 /**
 934  *      setup_sge_queues - configure SGE Tx/Rx/response queues
 935  *      @adap: the adapter
 936  *
 937  *      Determines how many sets of SGE queues to use and initializes them.
 938  *      We support multiple queue sets per port if we have MSI-X, otherwise
 939  *      just one queue set per port.
 940  */
 941 static int setup_sge_queues(struct adapter *adap)
 942 {
 943         int err, msi_idx, i, j;
 944         struct sge *s = &adap->sge;
 945
 946         bitmap_zero(s->starving_fl, MAX_EGRQ);
 947         bitmap_zero(s->txq_maperr, MAX_EGRQ);
 948
 949         if (adap->flags & USING_MSIX)
 950                 msi_idx = 1;         /* vector 0 is for non-queue interrupts */
 951         else {
 952                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
 953                                        NULL, NULL);
 954                 if (err)
 955                         return err;
 956                 msi_idx = -((int)s->intrq.abs_id + 1);
 957         }
 958
 959         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
 960                                msi_idx, NULL, fwevtq_handler);
 961         if (err) {
 962 freeout:        t4_free_sge_resources(adap);
 963                 return err;
 964         }
 965
 966         for_each_port(adap, i) {
 967                 struct net_device *dev = adap->port[i];
 968                 struct port_info *pi = netdev_priv(dev);
 969                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
 970                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
 971
 972                 for (j = 0; j < pi->nqsets; j++, q++) {
 973                         if (msi_idx > 0)
 974                                 msi_idx++;
 975                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
 976                                                msi_idx, &q->fl,
 977                                                t4_ethrx_handler);
 978                         if (err)
 979                                 goto freeout;
 980                         q->rspq.idx = j;
 981                         memset(&q->stats, 0, sizeof(q->stats));
 982                 }
 983                 for (j = 0; j < pi->nqsets; j++, t++) {
 984                         err = t4_sge_alloc_eth_txq(adap, t, dev,
 985                                         netdev_get_tx_queue(dev, j),
 986                                         s->fw_evtq.cntxt_id);
 987                         if (err)
 988                                 goto freeout;
 989                 }
 990         }
 991
 992         j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
 993         for_each_ofldrxq(s, i) {
 994                 struct sge_ofld_rxq *q = &s->ofldrxq[i];
 995                 struct net_device *dev = adap->port[i / j];
 996
 997                 if (msi_idx > 0)
 998                         msi_idx++;
 999                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
1000                                        &q->fl, uldrx_handler);
1001                 if (err)
1002                         goto freeout;
1003                 memset(&q->stats, 0, sizeof(q->stats));
1004                 s->ofld_rxq[i] = q->rspq.abs_id;
1005                 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1006                                             s->fw_evtq.cntxt_id);
1007                 if (err)
1008                         goto freeout;
1009         }
1010
1011         for_each_rdmarxq(s, i) {
1012                 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1013
1014                 if (msi_idx > 0)
1015                         msi_idx++;
1016                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1017                                        msi_idx, &q->fl, uldrx_handler);
1018                 if (err)
1019                         goto freeout;
1020                 memset(&q->stats, 0, sizeof(q->stats));
1021                 s->rdma_rxq[i] = q->rspq.abs_id;
1022         }
1023
1024         for_each_port(adap, i) {
1025                 /*
1026                  * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1027                  * have RDMA queues, and that's the right value.
1028                  */
1029                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1030                                             s->fw_evtq.cntxt_id,
1031                                             s->rdmarxq[i].rspq.cntxt_id);
1032                 if (err)
1033                         goto freeout;
1034         }
1035
1036         t4_write_reg(adap, MPS_TRC_RSS_CONTROL,
1037                      RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1038                      QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1039         return 0;
1040 }
1041
1042 /*
1043  * Returns 0 if new FW was successfully loaded, a positive errno if a load was
1044  * started but failed, and a negative errno if flash load couldn't start.
1045  */
1046 static int upgrade_fw(struct adapter *adap)
1047 {
1048         int ret;
1049         u32 vers, exp_major;
1050         const struct fw_hdr *hdr;
1051         const struct firmware *fw;
1052         struct device *dev = adap->pdev_dev;
1053         char *fw_file_name;
1054
1055         switch (CHELSIO_CHIP_VERSION(adap->chip)) {
1056         case CHELSIO_T4:
1057                 fw_file_name = FW_FNAME;
1058                 exp_major = FW_VERSION_MAJOR;
1059                 break;
1060         case CHELSIO_T5:
1061                 fw_file_name = FW5_FNAME;
1062                 exp_major = FW_VERSION_MAJOR_T5;
1063                 break;
1064         default:
1065                 dev_err(dev, "Unsupported chip type, %x\n", adap->chip);
1066                 return -EINVAL;
1067         }
1068
1069         ret = request_firmware(&fw, fw_file_name, dev);
1070         if (ret < 0) {
1071                 dev_err(dev, "unable to load firmware image %s, error %d\n",
1072                         fw_file_name, ret);
1073                 return ret;
1074         }
1075
1076         hdr = (const struct fw_hdr *)fw->data;
1077         vers = ntohl(hdr->fw_ver);
1078         if (FW_HDR_FW_VER_MAJOR_GET(vers) != exp_major) {
1079                 ret = -EINVAL;              /* wrong major version, won't do */
1080                 goto out;
1081         }
1082
1083         /*
1084          * If the flash FW is unusable or we found something newer, load it.
1085          */
1086         if (FW_HDR_FW_VER_MAJOR_GET(adap->params.fw_vers) != exp_major ||
1087             vers > adap->params.fw_vers) {
1088                 dev_info(dev, "upgrading firmware ...\n");
1089                 ret = t4_fw_upgrade(adap, adap->mbox, fw->data, fw->size,
1090                                     /*force=*/false);
1091                 if (!ret)
1092                         dev_info(dev,
1093                                  "firmware upgraded to version %pI4 from %s\n",
1094                                  &hdr->fw_ver, fw_file_name);
1095                 else
1096                         dev_err(dev, "firmware upgrade failed! err=%d\n", -ret);
1097         } else {
1098                 /*
1099                  * Tell our caller that we didn't upgrade the firmware.
1100                  */
1101                 ret = -EINVAL;
1102         }
1103
1104 out:    release_firmware(fw);
1105         return ret;
1106 }
1107
1108 /*
1109  * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1110  * The allocated memory is cleared.
1111  */
1112 void *t4_alloc_mem(size_t size)
1113 {
1114         void *p = kzalloc(size, GFP_KERNEL);
1115
1116         if (!p)
1117                 p = vzalloc(size);
1118         return p;
1119 }
1120
1121 /*
1122  * Free memory allocated through alloc_mem().
1123  */
1124 static void t4_free_mem(void *addr)
1125 {
1126         if (is_vmalloc_addr(addr))
1127                 vfree(addr);
1128         else
1129                 kfree(addr);
1130 }
1131
1132 /* Send a Work Request to write the filter at a specified index.  We construct
1133  * a Firmware Filter Work Request to have the work done and put the indicated
1134  * filter into "pending" mode which will prevent any further actions against
1135  * it till we get a reply from the firmware on the completion status of the
1136  * request.
1137  */
1138 static int set_filter_wr(struct adapter *adapter, int fidx)
1139 {
1140         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1141         struct sk_buff *skb;
1142         struct fw_filter_wr *fwr;
1143         unsigned int ftid;
1144
1145         /* If the new filter requires loopback Destination MAC and/or VLAN
1146          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1147          * the filter.
1148          */
1149         if (f->fs.newdmac || f->fs.newvlan) {
1150                 /* allocate L2T entry for new filter */
1151                 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1152                 if (f->l2t == NULL)
1153                         return -EAGAIN;
1154                 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1155                                         f->fs.eport, f->fs.dmac)) {
1156                         cxgb4_l2t_release(f->l2t);
1157                         f->l2t = NULL;
1158                         return -ENOMEM;
1159                 }
1160         }
1161
1162         ftid = adapter->tids.ftid_base + fidx;
1163
1164         skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1165         fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1166         memset(fwr, 0, sizeof(*fwr));
1167
1168         /* It would be nice to put most of the following in t4_hw.c but most
1169          * of the work is translating the cxgbtool ch_filter_specification
1170          * into the Work Request and the definition of that structure is
1171          * currently in cxgbtool.h which isn't appropriate to pull into the
1172          * common code.  We may eventually try to come up with a more neutral
1173          * filter specification structure but for now it's easiest to simply
1174          * put this fairly direct code in line ...
1175          */
1176         fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1177         fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1178         fwr->tid_to_iq =
1179                 htonl(V_FW_FILTER_WR_TID(ftid) |
1180                       V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1181                       V_FW_FILTER_WR_NOREPLY(0) |
1182                       V_FW_FILTER_WR_IQ(f->fs.iq));
1183         fwr->del_filter_to_l2tix =
1184                 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1185                       V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1186                       V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1187                       V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1188                       V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1189                       V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1190                       V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1191                       V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1192                       V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1193                                              f->fs.newvlan == VLAN_REWRITE) |
1194                       V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1195                                             f->fs.newvlan == VLAN_REWRITE) |
1196                       V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1197                       V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1198                       V_FW_FILTER_WR_PRIO(f->fs.prio) |
1199                       V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1200         fwr->ethtype = htons(f->fs.val.ethtype);
1201         fwr->ethtypem = htons(f->fs.mask.ethtype);
1202         fwr->frag_to_ovlan_vldm =
1203                 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1204                  V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1205                  V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1206                  V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1207                  V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1208                  V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1209         fwr->smac_sel = 0;
1210         fwr->rx_chan_rx_rpl_iq =
1211                 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1212                       V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1213         fwr->maci_to_matchtypem =
1214                 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1215                       V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1216                       V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1217                       V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1218                       V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1219                       V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1220                       V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1221                       V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1222         fwr->ptcl = f->fs.val.proto;
1223         fwr->ptclm = f->fs.mask.proto;
1224         fwr->ttyp = f->fs.val.tos;
1225         fwr->ttypm = f->fs.mask.tos;
1226         fwr->ivlan = htons(f->fs.val.ivlan);
1227         fwr->ivlanm = htons(f->fs.mask.ivlan);
1228         fwr->ovlan = htons(f->fs.val.ovlan);
1229         fwr->ovlanm = htons(f->fs.mask.ovlan);
1230         memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1231         memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1232         memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1233         memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1234         fwr->lp = htons(f->fs.val.lport);
1235         fwr->lpm = htons(f->fs.mask.lport);
1236         fwr->fp = htons(f->fs.val.fport);
1237         fwr->fpm = htons(f->fs.mask.fport);
1238         if (f->fs.newsmac)
1239                 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1240
1241         /* Mark the filter as "pending" and ship off the Filter Work Request.
1242          * When we get the Work Request Reply we'll clear the pending status.
1243          */
1244         f->pending = 1;
1245         set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1246         t4_ofld_send(adapter, skb);
1247         return 0;
1248 }
1249
1250 /* Delete the filter at a specified index.
1251  */
1252 static int del_filter_wr(struct adapter *adapter, int fidx)
1253 {
1254         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1255         struct sk_buff *skb;
1256         struct fw_filter_wr *fwr;
1257         unsigned int len, ftid;
1258
1259         len = sizeof(*fwr);
1260         ftid = adapter->tids.ftid_base + fidx;
1261
1262         skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1263         fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1264         t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1265
1266         /* Mark the filter as "pending" and ship off the Filter Work Request.
1267          * When we get the Work Request Reply we'll clear the pending status.
1268          */
1269         f->pending = 1;
1270         t4_mgmt_tx(adapter, skb);
1271         return 0;
1272 }
1273
1274 static inline int is_offload(const struct adapter *adap)
1275 {
1276         return adap->params.offload;
1277 }
1278
1279 /*
1280  * Implementation of ethtool operations.
1281  */
1282
1283 static u32 get_msglevel(struct net_device *dev)
1284 {
1285         return netdev2adap(dev)->msg_enable;
1286 }
1287
1288 static void set_msglevel(struct net_device *dev, u32 val)
1289 {
1290         netdev2adap(dev)->msg_enable = val;
1291 }
1292
1293 static char stats_strings[][ETH_GSTRING_LEN] = {
1294         "TxOctetsOK         ",
1295         "TxFramesOK         ",
1296         "TxBroadcastFrames  ",
1297         "TxMulticastFrames  ",
1298         "TxUnicastFrames    ",
1299         "TxErrorFrames      ",
1300
1301         "TxFrames64         ",
1302         "TxFrames65To127    ",
1303         "TxFrames128To255   ",
1304         "TxFrames256To511   ",
1305         "TxFrames512To1023  ",
1306         "TxFrames1024To1518 ",
1307         "TxFrames1519ToMax  ",
1308
1309         "TxFramesDropped    ",
1310         "TxPauseFrames      ",
1311         "TxPPP0Frames       ",
1312         "TxPPP1Frames       ",
1313         "TxPPP2Frames       ",
1314         "TxPPP3Frames       ",
1315         "TxPPP4Frames       ",
1316         "TxPPP5Frames       ",
1317         "TxPPP6Frames       ",
1318         "TxPPP7Frames       ",
1319
1320         "RxOctetsOK         ",
1321         "RxFramesOK         ",
1322         "RxBroadcastFrames  ",
1323         "RxMulticastFrames  ",
1324         "RxUnicastFrames    ",
1325
1326         "RxFramesTooLong    ",
1327         "RxJabberErrors     ",
1328         "RxFCSErrors        ",
1329         "RxLengthErrors     ",
1330         "RxSymbolErrors     ",
1331         "RxRuntFrames       ",
1332
1333         "RxFrames64         ",
1334         "RxFrames65To127    ",
1335         "RxFrames128To255   ",
1336         "RxFrames256To511   ",
1337         "RxFrames512To1023  ",
1338         "RxFrames1024To1518 ",
1339         "RxFrames1519ToMax  ",
1340
1341         "RxPauseFrames      ",
1342         "RxPPP0Frames       ",
1343         "RxPPP1Frames       ",
1344         "RxPPP2Frames       ",
1345         "RxPPP3Frames       ",
1346         "RxPPP4Frames       ",
1347         "RxPPP5Frames       ",
1348         "RxPPP6Frames       ",
1349         "RxPPP7Frames       ",
1350
1351         "RxBG0FramesDropped ",
1352         "RxBG1FramesDropped ",
1353         "RxBG2FramesDropped ",
1354         "RxBG3FramesDropped ",
1355         "RxBG0FramesTrunc   ",
1356         "RxBG1FramesTrunc   ",
1357         "RxBG2FramesTrunc   ",
1358         "RxBG3FramesTrunc   ",
1359
1360         "TSO                ",
1361         "TxCsumOffload      ",
1362         "RxCsumGood         ",
1363         "VLANextractions    ",
1364         "VLANinsertions     ",
1365         "GROpackets         ",
1366         "GROmerged          ",
1367         "WriteCoalSuccess   ",
1368         "WriteCoalFail      ",
1369 };
1370
1371 static int get_sset_count(struct net_device *dev, int sset)
1372 {
1373         switch (sset) {
1374         case ETH_SS_STATS:
1375                 return ARRAY_SIZE(stats_strings);
1376         default:
1377                 return -EOPNOTSUPP;
1378         }
1379 }
1380
1381 #define T4_REGMAP_SIZE (160 * 1024)
1382 #define T5_REGMAP_SIZE (332 * 1024)
1383
1384 static int get_regs_len(struct net_device *dev)
1385 {
1386         struct adapter *adap = netdev2adap(dev);
1387         if (is_t4(adap->chip))
1388                 return T4_REGMAP_SIZE;
1389         else
1390                 return T5_REGMAP_SIZE;
1391 }
1392
1393 static int get_eeprom_len(struct net_device *dev)
1394 {
1395         return EEPROMSIZE;
1396 }
1397
1398 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1399 {
1400         struct adapter *adapter = netdev2adap(dev);
1401
1402         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1403         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1404         strlcpy(info->bus_info, pci_name(adapter->pdev),
1405                 sizeof(info->bus_info));
1406
1407         if (adapter->params.fw_vers)
1408                 snprintf(info->fw_version, sizeof(info->fw_version),
1409                         "%u.%u.%u.%u, TP %u.%u.%u.%u",
1410                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1411                         FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1412                         FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1413                         FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1414                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1415                         FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1416                         FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1417                         FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1418 }
1419
1420 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1421 {
1422         if (stringset == ETH_SS_STATS)
1423                 memcpy(data, stats_strings, sizeof(stats_strings));
1424 }
1425
1426 /*
1427  * port stats maintained per queue of the port.  They should be in the same
1428  * order as in stats_strings above.
1429  */
1430 struct queue_port_stats {
1431         u64 tso;
1432         u64 tx_csum;
1433         u64 rx_csum;
1434         u64 vlan_ex;
1435         u64 vlan_ins;
1436         u64 gro_pkts;
1437         u64 gro_merged;
1438 };
1439
1440 static void collect_sge_port_stats(const struct adapter *adap,
1441                 const struct port_info *p, struct queue_port_stats *s)
1442 {
1443         int i;
1444         const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1445         const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1446
1447         memset(s, 0, sizeof(*s));
1448         for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1449                 s->tso += tx->tso;
1450                 s->tx_csum += tx->tx_cso;
1451                 s->rx_csum += rx->stats.rx_cso;
1452                 s->vlan_ex += rx->stats.vlan_ex;
1453                 s->vlan_ins += tx->vlan_ins;
1454                 s->gro_pkts += rx->stats.lro_pkts;
1455                 s->gro_merged += rx->stats.lro_merged;
1456         }
1457 }
1458
1459 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1460                       u64 *data)
1461 {
1462         struct port_info *pi = netdev_priv(dev);
1463         struct adapter *adapter = pi->adapter;
1464         u32 val1, val2;
1465
1466         t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1467
1468         data += sizeof(struct port_stats) / sizeof(u64);
1469         collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1470         data += sizeof(struct queue_port_stats) / sizeof(u64);
1471         if (!is_t4(adapter->chip)) {
1472                 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1473                 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1474                 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1475                 *data = val1 - val2;
1476                 data++;
1477                 *data = val2;
1478                 data++;
1479         } else {
1480                 memset(data, 0, 2 * sizeof(u64));
1481                 *data += 2;
1482         }
1483 }
1484
1485 /*
1486  * Return a version number to identify the type of adapter.  The scheme is:
1487  * - bits 0..9: chip version
1488  * - bits 10..15: chip revision
1489  * - bits 16..23: register dump version
1490  */
1491 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1492 {
1493         return CHELSIO_CHIP_VERSION(ap->chip) |
1494                 (CHELSIO_CHIP_RELEASE(ap->chip) << 10) | (1 << 16);
1495 }
1496
1497 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1498                            unsigned int end)
1499 {
1500         u32 *p = buf + start;
1501
1502         for ( ; start <= end; start += sizeof(u32))
1503                 *p++ = t4_read_reg(ap, start);
1504 }
1505
1506 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1507                      void *buf)
1508 {
1509         static const unsigned int t4_reg_ranges[] = {
1510                 0x1008, 0x1108,
1511                 0x1180, 0x11b4,
1512                 0x11fc, 0x123c,
1513                 0x1300, 0x173c,
1514                 0x1800, 0x18fc,
1515                 0x3000, 0x30d8,
1516                 0x30e0, 0x5924,
1517                 0x5960, 0x59d4,
1518                 0x5a00, 0x5af8,
1519                 0x6000, 0x6098,
1520                 0x6100, 0x6150,
1521                 0x6200, 0x6208,
1522                 0x6240, 0x6248,
1523                 0x6280, 0x6338,
1524                 0x6370, 0x638c,
1525                 0x6400, 0x643c,
1526                 0x6500, 0x6524,
1527                 0x6a00, 0x6a38,
1528                 0x6a60, 0x6a78,
1529                 0x6b00, 0x6b84,
1530                 0x6bf0, 0x6c84,
1531                 0x6cf0, 0x6d84,
1532                 0x6df0, 0x6e84,
1533                 0x6ef0, 0x6f84,
1534                 0x6ff0, 0x7084,
1535                 0x70f0, 0x7184,
1536                 0x71f0, 0x7284,
1537                 0x72f0, 0x7384,
1538                 0x73f0, 0x7450,
1539                 0x7500, 0x7530,
1540                 0x7600, 0x761c,
1541                 0x7680, 0x76cc,
1542                 0x7700, 0x7798,
1543                 0x77c0, 0x77fc,
1544                 0x7900, 0x79fc,
1545                 0x7b00, 0x7c38,
1546                 0x7d00, 0x7efc,
1547                 0x8dc0, 0x8e1c,
1548                 0x8e30, 0x8e78,
1549                 0x8ea0, 0x8f6c,
1550                 0x8fc0, 0x9074,
1551                 0x90fc, 0x90fc,
1552                 0x9400, 0x9458,
1553                 0x9600, 0x96bc,
1554                 0x9800, 0x9808,
1555                 0x9820, 0x983c,
1556                 0x9850, 0x9864,
1557                 0x9c00, 0x9c6c,
1558                 0x9c80, 0x9cec,
1559                 0x9d00, 0x9d6c,
1560                 0x9d80, 0x9dec,
1561                 0x9e00, 0x9e6c,
1562                 0x9e80, 0x9eec,
1563                 0x9f00, 0x9f6c,
1564                 0x9f80, 0x9fec,
1565                 0xd004, 0xd03c,
1566                 0xdfc0, 0xdfe0,
1567                 0xe000, 0xea7c,
1568                 0xf000, 0x11190,
1569                 0x19040, 0x1906c,
1570                 0x19078, 0x19080,
1571                 0x1908c, 0x19124,
1572                 0x19150, 0x191b0,
1573                 0x191d0, 0x191e8,
1574                 0x19238, 0x1924c,
1575                 0x193f8, 0x19474,
1576                 0x19490, 0x194f8,
1577                 0x19800, 0x19f30,
1578                 0x1a000, 0x1a06c,
1579                 0x1a0b0, 0x1a120,
1580                 0x1a128, 0x1a138,
1581                 0x1a190, 0x1a1c4,
1582                 0x1a1fc, 0x1a1fc,
1583                 0x1e040, 0x1e04c,
1584                 0x1e284, 0x1e28c,
1585                 0x1e2c0, 0x1e2c0,
1586                 0x1e2e0, 0x1e2e0,
1587                 0x1e300, 0x1e384,
1588                 0x1e3c0, 0x1e3c8,
1589                 0x1e440, 0x1e44c,
1590                 0x1e684, 0x1e68c,
1591                 0x1e6c0, 0x1e6c0,
1592                 0x1e6e0, 0x1e6e0,
1593                 0x1e700, 0x1e784,
1594                 0x1e7c0, 0x1e7c8,
1595                 0x1e840, 0x1e84c,
1596                 0x1ea84, 0x1ea8c,
1597                 0x1eac0, 0x1eac0,
1598                 0x1eae0, 0x1eae0,
1599                 0x1eb00, 0x1eb84,
1600                 0x1ebc0, 0x1ebc8,
1601                 0x1ec40, 0x1ec4c,
1602                 0x1ee84, 0x1ee8c,
1603                 0x1eec0, 0x1eec0,
1604                 0x1eee0, 0x1eee0,
1605                 0x1ef00, 0x1ef84,
1606                 0x1efc0, 0x1efc8,
1607                 0x1f040, 0x1f04c,
1608                 0x1f284, 0x1f28c,
1609                 0x1f2c0, 0x1f2c0,
1610                 0x1f2e0, 0x1f2e0,
1611                 0x1f300, 0x1f384,
1612                 0x1f3c0, 0x1f3c8,
1613                 0x1f440, 0x1f44c,
1614                 0x1f684, 0x1f68c,
1615                 0x1f6c0, 0x1f6c0,
1616                 0x1f6e0, 0x1f6e0,
1617                 0x1f700, 0x1f784,
1618                 0x1f7c0, 0x1f7c8,
1619                 0x1f840, 0x1f84c,
1620                 0x1fa84, 0x1fa8c,
1621                 0x1fac0, 0x1fac0,
1622                 0x1fae0, 0x1fae0,
1623                 0x1fb00, 0x1fb84,
1624                 0x1fbc0, 0x1fbc8,
1625                 0x1fc40, 0x1fc4c,
1626                 0x1fe84, 0x1fe8c,
1627                 0x1fec0, 0x1fec0,
1628                 0x1fee0, 0x1fee0,
1629                 0x1ff00, 0x1ff84,
1630                 0x1ffc0, 0x1ffc8,
1631                 0x20000, 0x2002c,
1632                 0x20100, 0x2013c,
1633                 0x20190, 0x201c8,
1634                 0x20200, 0x20318,
1635                 0x20400, 0x20528,
1636                 0x20540, 0x20614,
1637                 0x21000, 0x21040,
1638                 0x2104c, 0x21060,
1639                 0x210c0, 0x210ec,
1640                 0x21200, 0x21268,
1641                 0x21270, 0x21284,
1642                 0x212fc, 0x21388,
1643                 0x21400, 0x21404,
1644                 0x21500, 0x21518,
1645                 0x2152c, 0x2153c,
1646                 0x21550, 0x21554,
1647                 0x21600, 0x21600,
1648                 0x21608, 0x21628,
1649                 0x21630, 0x2163c,
1650                 0x21700, 0x2171c,
1651                 0x21780, 0x2178c,
1652                 0x21800, 0x21c38,
1653                 0x21c80, 0x21d7c,
1654                 0x21e00, 0x21e04,
1655                 0x22000, 0x2202c,
1656                 0x22100, 0x2213c,
1657                 0x22190, 0x221c8,
1658                 0x22200, 0x22318,
1659                 0x22400, 0x22528,
1660                 0x22540, 0x22614,
1661                 0x23000, 0x23040,
1662                 0x2304c, 0x23060,
1663                 0x230c0, 0x230ec,
1664                 0x23200, 0x23268,
1665                 0x23270, 0x23284,
1666                 0x232fc, 0x23388,
1667                 0x23400, 0x23404,
1668                 0x23500, 0x23518,
1669                 0x2352c, 0x2353c,
1670                 0x23550, 0x23554,
1671                 0x23600, 0x23600,
1672                 0x23608, 0x23628,
1673                 0x23630, 0x2363c,
1674                 0x23700, 0x2371c,
1675                 0x23780, 0x2378c,
1676                 0x23800, 0x23c38,
1677                 0x23c80, 0x23d7c,
1678                 0x23e00, 0x23e04,
1679                 0x24000, 0x2402c,
1680                 0x24100, 0x2413c,
1681                 0x24190, 0x241c8,
1682                 0x24200, 0x24318,
1683                 0x24400, 0x24528,
1684                 0x24540, 0x24614,
1685                 0x25000, 0x25040,
1686                 0x2504c, 0x25060,
1687                 0x250c0, 0x250ec,
1688                 0x25200, 0x25268,
1689                 0x25270, 0x25284,
1690                 0x252fc, 0x25388,
1691                 0x25400, 0x25404,
1692                 0x25500, 0x25518,
1693                 0x2552c, 0x2553c,
1694                 0x25550, 0x25554,
1695                 0x25600, 0x25600,
1696                 0x25608, 0x25628,
1697                 0x25630, 0x2563c,
1698                 0x25700, 0x2571c,
1699                 0x25780, 0x2578c,
1700                 0x25800, 0x25c38,
1701                 0x25c80, 0x25d7c,
1702                 0x25e00, 0x25e04,
1703                 0x26000, 0x2602c,
1704                 0x26100, 0x2613c,
1705                 0x26190, 0x261c8,
1706                 0x26200, 0x26318,
1707                 0x26400, 0x26528,
1708                 0x26540, 0x26614,
1709                 0x27000, 0x27040,
1710                 0x2704c, 0x27060,
1711                 0x270c0, 0x270ec,
1712                 0x27200, 0x27268,
1713                 0x27270, 0x27284,
1714                 0x272fc, 0x27388,
1715                 0x27400, 0x27404,
1716                 0x27500, 0x27518,
1717                 0x2752c, 0x2753c,
1718                 0x27550, 0x27554,
1719                 0x27600, 0x27600,
1720                 0x27608, 0x27628,
1721                 0x27630, 0x2763c,
1722                 0x27700, 0x2771c,
1723                 0x27780, 0x2778c,
1724                 0x27800, 0x27c38,
1725                 0x27c80, 0x27d7c,
1726                 0x27e00, 0x27e04
1727         };
1728
1729         static const unsigned int t5_reg_ranges[] = {
1730                 0x1008, 0x1148,
1731                 0x1180, 0x11b4,
1732                 0x11fc, 0x123c,
1733                 0x1280, 0x173c,
1734                 0x1800, 0x18fc,
1735                 0x3000, 0x3028,
1736                 0x3060, 0x30d8,
1737                 0x30e0, 0x30fc,
1738                 0x3140, 0x357c,
1739                 0x35a8, 0x35cc,
1740                 0x35ec, 0x35ec,
1741                 0x3600, 0x5624,
1742                 0x56cc, 0x575c,
1743                 0x580c, 0x5814,
1744                 0x5890, 0x58bc,
1745                 0x5940, 0x59dc,
1746                 0x59fc, 0x5a18,
1747                 0x5a60, 0x5a9c,
1748                 0x5b9c, 0x5bfc,
1749                 0x6000, 0x6040,
1750                 0x6058, 0x614c,
1751                 0x7700, 0x7798,
1752                 0x77c0, 0x78fc,
1753                 0x7b00, 0x7c54,
1754                 0x7d00, 0x7efc,
1755                 0x8dc0, 0x8de0,
1756                 0x8df8, 0x8e84,
1757                 0x8ea0, 0x8f84,
1758                 0x8fc0, 0x90f8,
1759                 0x9400, 0x9470,
1760                 0x9600, 0x96f4,
1761                 0x9800, 0x9808,
1762                 0x9820, 0x983c,
1763                 0x9850, 0x9864,
1764                 0x9c00, 0x9c6c,
1765                 0x9c80, 0x9cec,
1766                 0x9d00, 0x9d6c,
1767                 0x9d80, 0x9dec,
1768                 0x9e00, 0x9e6c,
1769                 0x9e80, 0x9eec,
1770                 0x9f00, 0x9f6c,
1771                 0x9f80, 0xa020,
1772                 0xd004, 0xd03c,
1773                 0xdfc0, 0xdfe0,
1774                 0xe000, 0x11088,
1775                 0x1109c, 0x1117c,
1776                 0x11190, 0x11204,
1777                 0x19040, 0x1906c,
1778                 0x19078, 0x19080,
1779                 0x1908c, 0x19124,
1780                 0x19150, 0x191b0,
1781                 0x191d0, 0x191e8,
1782                 0x19238, 0x19290,
1783                 0x193f8, 0x19474,
1784                 0x19490, 0x194cc,
1785                 0x194f0, 0x194f8,
1786                 0x19c00, 0x19c60,
1787                 0x19c94, 0x19e10,
1788                 0x19e50, 0x19f34,
1789                 0x19f40, 0x19f50,
1790                 0x19f90, 0x19fe4,
1791                 0x1a000, 0x1a06c,
1792                 0x1a0b0, 0x1a120,
1793                 0x1a128, 0x1a138,
1794                 0x1a190, 0x1a1c4,
1795                 0x1a1fc, 0x1a1fc,
1796                 0x1e008, 0x1e00c,
1797                 0x1e040, 0x1e04c,
1798                 0x1e284, 0x1e290,
1799                 0x1e2c0, 0x1e2c0,
1800                 0x1e2e0, 0x1e2e0,
1801                 0x1e300, 0x1e384,
1802                 0x1e3c0, 0x1e3c8,
1803                 0x1e408, 0x1e40c,
1804                 0x1e440, 0x1e44c,
1805                 0x1e684, 0x1e690,
1806                 0x1e6c0, 0x1e6c0,
1807                 0x1e6e0, 0x1e6e0,
1808                 0x1e700, 0x1e784,
1809                 0x1e7c0, 0x1e7c8,
1810                 0x1e808, 0x1e80c,
1811                 0x1e840, 0x1e84c,
1812                 0x1ea84, 0x1ea90,
1813                 0x1eac0, 0x1eac0,
1814                 0x1eae0, 0x1eae0,
1815                 0x1eb00, 0x1eb84,
1816                 0x1ebc0, 0x1ebc8,
1817                 0x1ec08, 0x1ec0c,
1818                 0x1ec40, 0x1ec4c,
1819                 0x1ee84, 0x1ee90,
1820                 0x1eec0, 0x1eec0,
1821                 0x1eee0, 0x1eee0,
1822                 0x1ef00, 0x1ef84,
1823                 0x1efc0, 0x1efc8,
1824                 0x1f008, 0x1f00c,
1825                 0x1f040, 0x1f04c,
1826                 0x1f284, 0x1f290,
1827                 0x1f2c0, 0x1f2c0,
1828                 0x1f2e0, 0x1f2e0,
1829                 0x1f300, 0x1f384,
1830                 0x1f3c0, 0x1f3c8,
1831                 0x1f408, 0x1f40c,
1832                 0x1f440, 0x1f44c,
1833                 0x1f684, 0x1f690,
1834                 0x1f6c0, 0x1f6c0,
1835                 0x1f6e0, 0x1f6e0,
1836                 0x1f700, 0x1f784,
1837                 0x1f7c0, 0x1f7c8,
1838                 0x1f808, 0x1f80c,
1839                 0x1f840, 0x1f84c,
1840                 0x1fa84, 0x1fa90,
1841                 0x1fac0, 0x1fac0,
1842                 0x1fae0, 0x1fae0,
1843                 0x1fb00, 0x1fb84,
1844                 0x1fbc0, 0x1fbc8,
1845                 0x1fc08, 0x1fc0c,
1846                 0x1fc40, 0x1fc4c,
1847                 0x1fe84, 0x1fe90,
1848                 0x1fec0, 0x1fec0,
1849                 0x1fee0, 0x1fee0,
1850                 0x1ff00, 0x1ff84,
1851                 0x1ffc0, 0x1ffc8,
1852                 0x30000, 0x30030,
1853                 0x30100, 0x30144,
1854                 0x30190, 0x301d0,
1855                 0x30200, 0x30318,
1856                 0x30400, 0x3052c,
1857                 0x30540, 0x3061c,
1858                 0x30800, 0x30834,
1859                 0x308c0, 0x30908,
1860                 0x30910, 0x309ac,
1861                 0x30a00, 0x30a04,
1862                 0x30a0c, 0x30a2c,
1863                 0x30a44, 0x30a50,
1864                 0x30a74, 0x30c24,
1865                 0x30d08, 0x30d14,
1866                 0x30d1c, 0x30d20,
1867                 0x30d3c, 0x30d50,
1868                 0x31200, 0x3120c,
1869                 0x31220, 0x31220,
1870                 0x31240, 0x31240,
1871                 0x31600, 0x31600,
1872                 0x31608, 0x3160c,
1873                 0x31a00, 0x31a1c,
1874                 0x31e04, 0x31e20,
1875                 0x31e38, 0x31e3c,
1876                 0x31e80, 0x31e80,
1877                 0x31e88, 0x31ea8,
1878                 0x31eb0, 0x31eb4,
1879                 0x31ec8, 0x31ed4,
1880                 0x31fb8, 0x32004,
1881                 0x32208, 0x3223c,
1882                 0x32600, 0x32630,
1883                 0x32a00, 0x32abc,
1884                 0x32b00, 0x32b70,
1885                 0x33000, 0x33048,
1886                 0x33060, 0x3309c,
1887                 0x330f0, 0x33148,
1888                 0x33160, 0x3319c,
1889                 0x331f0, 0x332e4,
1890                 0x332f8, 0x333e4,
1891                 0x333f8, 0x33448,
1892                 0x33460, 0x3349c,
1893                 0x334f0, 0x33548,
1894                 0x33560, 0x3359c,
1895                 0x335f0, 0x336e4,
1896                 0x336f8, 0x337e4,
1897                 0x337f8, 0x337fc,
1898                 0x33814, 0x33814,
1899                 0x3382c, 0x3382c,
1900                 0x33880, 0x3388c,
1901                 0x338e8, 0x338ec,
1902                 0x33900, 0x33948,
1903                 0x33960, 0x3399c,
1904                 0x339f0, 0x33ae4,
1905                 0x33af8, 0x33b10,
1906                 0x33b28, 0x33b28,
1907                 0x33b3c, 0x33b50,
1908                 0x33bf0, 0x33c10,
1909                 0x33c28, 0x33c28,
1910                 0x33c3c, 0x33c50,
1911                 0x33cf0, 0x33cfc,
1912                 0x34000, 0x34030,
1913                 0x34100, 0x34144,
1914                 0x34190, 0x341d0,
1915                 0x34200, 0x34318,
1916                 0x34400, 0x3452c,
1917                 0x34540, 0x3461c,
1918                 0x34800, 0x34834,
1919                 0x348c0, 0x34908,
1920                 0x34910, 0x349ac,
1921                 0x34a00, 0x34a04,
1922                 0x34a0c, 0x34a2c,
1923                 0x34a44, 0x34a50,
1924                 0x34a74, 0x34c24,
1925                 0x34d08, 0x34d14,
1926                 0x34d1c, 0x34d20,
1927                 0x34d3c, 0x34d50,
1928                 0x35200, 0x3520c,
1929                 0x35220, 0x35220,
1930                 0x35240, 0x35240,
1931                 0x35600, 0x35600,
1932                 0x35608, 0x3560c,
1933                 0x35a00, 0x35a1c,
1934                 0x35e04, 0x35e20,
1935                 0x35e38, 0x35e3c,
1936                 0x35e80, 0x35e80,
1937                 0x35e88, 0x35ea8,
1938                 0x35eb0, 0x35eb4,
1939                 0x35ec8, 0x35ed4,
1940                 0x35fb8, 0x36004,
1941                 0x36208, 0x3623c,
1942                 0x36600, 0x36630,
1943                 0x36a00, 0x36abc,
1944                 0x36b00, 0x36b70,
1945                 0x37000, 0x37048,
1946                 0x37060, 0x3709c,
1947                 0x370f0, 0x37148,
1948                 0x37160, 0x3719c,
1949                 0x371f0, 0x372e4,
1950                 0x372f8, 0x373e4,
1951                 0x373f8, 0x37448,
1952                 0x37460, 0x3749c,
1953                 0x374f0, 0x37548,
1954                 0x37560, 0x3759c,
1955                 0x375f0, 0x376e4,
1956                 0x376f8, 0x377e4,
1957                 0x377f8, 0x377fc,
1958                 0x37814, 0x37814,
1959                 0x3782c, 0x3782c,
1960                 0x37880, 0x3788c,
1961                 0x378e8, 0x378ec,
1962                 0x37900, 0x37948,
1963                 0x37960, 0x3799c,
1964                 0x379f0, 0x37ae4,
1965                 0x37af8, 0x37b10,
1966                 0x37b28, 0x37b28,
1967                 0x37b3c, 0x37b50,
1968                 0x37bf0, 0x37c10,
1969                 0x37c28, 0x37c28,
1970                 0x37c3c, 0x37c50,
1971                 0x37cf0, 0x37cfc,
1972                 0x38000, 0x38030,
1973                 0x38100, 0x38144,
1974                 0x38190, 0x381d0,
1975                 0x38200, 0x38318,
1976                 0x38400, 0x3852c,
1977                 0x38540, 0x3861c,
1978                 0x38800, 0x38834,
1979                 0x388c0, 0x38908,
1980                 0x38910, 0x389ac,
1981                 0x38a00, 0x38a04,
1982                 0x38a0c, 0x38a2c,
1983                 0x38a44, 0x38a50,
1984                 0x38a74, 0x38c24,
1985                 0x38d08, 0x38d14,
1986                 0x38d1c, 0x38d20,
1987                 0x38d3c, 0x38d50,
1988                 0x39200, 0x3920c,
1989                 0x39220, 0x39220,
1990                 0x39240, 0x39240,
1991                 0x39600, 0x39600,
1992                 0x39608, 0x3960c,
1993                 0x39a00, 0x39a1c,
1994                 0x39e04, 0x39e20,
1995                 0x39e38, 0x39e3c,
1996                 0x39e80, 0x39e80,
1997                 0x39e88, 0x39ea8,
1998                 0x39eb0, 0x39eb4,
1999                 0x39ec8, 0x39ed4,
2000                 0x39fb8, 0x3a004,
2001                 0x3a208, 0x3a23c,
2002                 0x3a600, 0x3a630,
2003                 0x3aa00, 0x3aabc,
2004                 0x3ab00, 0x3ab70,
2005                 0x3b000, 0x3b048,
2006                 0x3b060, 0x3b09c,
2007                 0x3b0f0, 0x3b148,
2008                 0x3b160, 0x3b19c,
2009                 0x3b1f0, 0x3b2e4,
2010                 0x3b2f8, 0x3b3e4,
2011                 0x3b3f8, 0x3b448,
2012                 0x3b460, 0x3b49c,
2013                 0x3b4f0, 0x3b548,
2014                 0x3b560, 0x3b59c,
2015                 0x3b5f0, 0x3b6e4,
2016                 0x3b6f8, 0x3b7e4,
2017                 0x3b7f8, 0x3b7fc,
2018                 0x3b814, 0x3b814,
2019                 0x3b82c, 0x3b82c,
2020                 0x3b880, 0x3b88c,
2021                 0x3b8e8, 0x3b8ec,
2022                 0x3b900, 0x3b948,
2023                 0x3b960, 0x3b99c,
2024                 0x3b9f0, 0x3bae4,
2025                 0x3baf8, 0x3bb10,
2026                 0x3bb28, 0x3bb28,
2027                 0x3bb3c, 0x3bb50,
2028                 0x3bbf0, 0x3bc10,
2029                 0x3bc28, 0x3bc28,
2030                 0x3bc3c, 0x3bc50,
2031                 0x3bcf0, 0x3bcfc,
2032                 0x3c000, 0x3c030,
2033                 0x3c100, 0x3c144,
2034                 0x3c190, 0x3c1d0,
2035                 0x3c200, 0x3c318,
2036                 0x3c400, 0x3c52c,
2037                 0x3c540, 0x3c61c,
2038                 0x3c800, 0x3c834,
2039                 0x3c8c0, 0x3c908,
2040                 0x3c910, 0x3c9ac,
2041                 0x3ca00, 0x3ca04,
2042                 0x3ca0c, 0x3ca2c,
2043                 0x3ca44, 0x3ca50,
2044                 0x3ca74, 0x3cc24,
2045                 0x3cd08, 0x3cd14,
2046                 0x3cd1c, 0x3cd20,
2047                 0x3cd3c, 0x3cd50,
2048                 0x3d200, 0x3d20c,
2049                 0x3d220, 0x3d220,
2050                 0x3d240, 0x3d240,
2051                 0x3d600, 0x3d600,
2052                 0x3d608, 0x3d60c,
2053                 0x3da00, 0x3da1c,
2054                 0x3de04, 0x3de20,
2055                 0x3de38, 0x3de3c,
2056                 0x3de80, 0x3de80,
2057                 0x3de88, 0x3dea8,
2058                 0x3deb0, 0x3deb4,
2059                 0x3dec8, 0x3ded4,
2060                 0x3dfb8, 0x3e004,
2061                 0x3e208, 0x3e23c,
2062                 0x3e600, 0x3e630,
2063                 0x3ea00, 0x3eabc,
2064                 0x3eb00, 0x3eb70,
2065                 0x3f000, 0x3f048,
2066                 0x3f060, 0x3f09c,
2067                 0x3f0f0, 0x3f148,
2068                 0x3f160, 0x3f19c,
2069                 0x3f1f0, 0x3f2e4,
2070                 0x3f2f8, 0x3f3e4,
2071                 0x3f3f8, 0x3f448,
2072                 0x3f460, 0x3f49c,
2073                 0x3f4f0, 0x3f548,
2074                 0x3f560, 0x3f59c,
2075                 0x3f5f0, 0x3f6e4,
2076                 0x3f6f8, 0x3f7e4,
2077                 0x3f7f8, 0x3f7fc,
2078                 0x3f814, 0x3f814,
2079                 0x3f82c, 0x3f82c,
2080                 0x3f880, 0x3f88c,
2081                 0x3f8e8, 0x3f8ec,
2082                 0x3f900, 0x3f948,
2083                 0x3f960, 0x3f99c,
2084                 0x3f9f0, 0x3fae4,
2085                 0x3faf8, 0x3fb10,
2086                 0x3fb28, 0x3fb28,
2087                 0x3fb3c, 0x3fb50,
2088                 0x3fbf0, 0x3fc10,
2089                 0x3fc28, 0x3fc28,
2090                 0x3fc3c, 0x3fc50,
2091                 0x3fcf0, 0x3fcfc,
2092                 0x40000, 0x4000c,
2093                 0x40040, 0x40068,
2094                 0x40080, 0x40144,
2095                 0x40180, 0x4018c,
2096                 0x40200, 0x40298,
2097                 0x402ac, 0x4033c,
2098                 0x403f8, 0x403fc,
2099                 0x41300, 0x413c4,
2100                 0x41400, 0x4141c,
2101                 0x41480, 0x414d0,
2102                 0x44000, 0x44078,
2103                 0x440c0, 0x44278,
2104                 0x442c0, 0x44478,
2105                 0x444c0, 0x44678,
2106                 0x446c0, 0x44878,
2107                 0x448c0, 0x449fc,
2108                 0x45000, 0x45068,
2109                 0x45080, 0x45084,
2110                 0x450a0, 0x450b0,
2111                 0x45200, 0x45268,
2112                 0x45280, 0x45284,
2113                 0x452a0, 0x452b0,
2114                 0x460c0, 0x460e4,
2115                 0x47000, 0x4708c,
2116                 0x47200, 0x47250,
2117                 0x47400, 0x47420,
2118                 0x47600, 0x47618,
2119                 0x47800, 0x47814,
2120                 0x48000, 0x4800c,
2121                 0x48040, 0x48068,
2122                 0x48080, 0x48144,
2123                 0x48180, 0x4818c,
2124                 0x48200, 0x48298,
2125                 0x482ac, 0x4833c,
2126                 0x483f8, 0x483fc,
2127                 0x49300, 0x493c4,
2128                 0x49400, 0x4941c,
2129                 0x49480, 0x494d0,
2130                 0x4c000, 0x4c078,
2131                 0x4c0c0, 0x4c278,
2132                 0x4c2c0, 0x4c478,
2133                 0x4c4c0, 0x4c678,
2134                 0x4c6c0, 0x4c878,
2135                 0x4c8c0, 0x4c9fc,
2136                 0x4d000, 0x4d068,
2137                 0x4d080, 0x4d084,
2138                 0x4d0a0, 0x4d0b0,
2139                 0x4d200, 0x4d268,
2140                 0x4d280, 0x4d284,
2141                 0x4d2a0, 0x4d2b0,
2142                 0x4e0c0, 0x4e0e4,
2143                 0x4f000, 0x4f08c,
2144                 0x4f200, 0x4f250,
2145                 0x4f400, 0x4f420,
2146                 0x4f600, 0x4f618,
2147                 0x4f800, 0x4f814,
2148                 0x50000, 0x500cc,
2149                 0x50400, 0x50400,
2150                 0x50800, 0x508cc,
2151                 0x50c00, 0x50c00,
2152                 0x51000, 0x5101c,
2153                 0x51300, 0x51308,
2154         };
2155
2156         int i;
2157         struct adapter *ap = netdev2adap(dev);
2158         static const unsigned int *reg_ranges;
2159         int arr_size = 0, buf_size = 0;
2160
2161         if (is_t4(ap->chip)) {
2162                 reg_ranges = &t4_reg_ranges[0];
2163                 arr_size = ARRAY_SIZE(t4_reg_ranges);
2164                 buf_size = T4_REGMAP_SIZE;
2165         } else {
2166                 reg_ranges = &t5_reg_ranges[0];
2167                 arr_size = ARRAY_SIZE(t5_reg_ranges);
2168                 buf_size = T5_REGMAP_SIZE;
2169         }
2170
2171         regs->version = mk_adap_vers(ap);
2172
2173         memset(buf, 0, buf_size);
2174         for (i = 0; i < arr_size; i += 2)
2175                 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2176 }
2177
2178 static int restart_autoneg(struct net_device *dev)
2179 {
2180         struct port_info *p = netdev_priv(dev);
2181
2182         if (!netif_running(dev))
2183                 return -EAGAIN;
2184         if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2185                 return -EINVAL;
2186         t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
2187         return 0;
2188 }
2189
2190 static int identify_port(struct net_device *dev,
2191                          enum ethtool_phys_id_state state)
2192 {
2193         unsigned int val;
2194         struct adapter *adap = netdev2adap(dev);
2195
2196         if (state == ETHTOOL_ID_ACTIVE)
2197                 val = 0xffff;
2198         else if (state == ETHTOOL_ID_INACTIVE)
2199                 val = 0;
2200         else
2201                 return -EINVAL;
2202
2203         return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
2204 }
2205
2206 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2207 {
2208         unsigned int v = 0;
2209
2210         if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2211             type == FW_PORT_TYPE_BT_XAUI) {
2212                 v |= SUPPORTED_TP;
2213                 if (caps & FW_PORT_CAP_SPEED_100M)
2214                         v |= SUPPORTED_100baseT_Full;
2215                 if (caps & FW_PORT_CAP_SPEED_1G)
2216                         v |= SUPPORTED_1000baseT_Full;
2217                 if (caps & FW_PORT_CAP_SPEED_10G)
2218                         v |= SUPPORTED_10000baseT_Full;
2219         } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2220                 v |= SUPPORTED_Backplane;
2221                 if (caps & FW_PORT_CAP_SPEED_1G)
2222                         v |= SUPPORTED_1000baseKX_Full;
2223                 if (caps & FW_PORT_CAP_SPEED_10G)
2224                         v |= SUPPORTED_10000baseKX4_Full;
2225         } else if (type == FW_PORT_TYPE_KR)
2226                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
2227         else if (type == FW_PORT_TYPE_BP_AP)
2228                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2229                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2230         else if (type == FW_PORT_TYPE_BP4_AP)
2231                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2232                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2233                      SUPPORTED_10000baseKX4_Full;
2234         else if (type == FW_PORT_TYPE_FIBER_XFI ||
2235                  type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
2236                 v |= SUPPORTED_FIBRE;
2237
2238         if (caps & FW_PORT_CAP_ANEG)
2239                 v |= SUPPORTED_Autoneg;
2240         return v;
2241 }
2242
2243 static unsigned int to_fw_linkcaps(unsigned int caps)
2244 {
2245         unsigned int v = 0;
2246
2247         if (caps & ADVERTISED_100baseT_Full)
2248                 v |= FW_PORT_CAP_SPEED_100M;
2249         if (caps & ADVERTISED_1000baseT_Full)
2250                 v |= FW_PORT_CAP_SPEED_1G;
2251         if (caps & ADVERTISED_10000baseT_Full)
2252                 v |= FW_PORT_CAP_SPEED_10G;
2253         return v;
2254 }
2255
2256 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2257 {
2258         const struct port_info *p = netdev_priv(dev);
2259
2260         if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
2261             p->port_type == FW_PORT_TYPE_BT_XFI ||
2262             p->port_type == FW_PORT_TYPE_BT_XAUI)
2263                 cmd->port = PORT_TP;
2264         else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2265                  p->port_type == FW_PORT_TYPE_FIBER_XAUI)
2266                 cmd->port = PORT_FIBRE;
2267         else if (p->port_type == FW_PORT_TYPE_SFP) {
2268                 if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2269                     p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
2270                         cmd->port = PORT_DA;
2271                 else
2272                         cmd->port = PORT_FIBRE;
2273         } else
2274                 cmd->port = PORT_OTHER;
2275
2276         if (p->mdio_addr >= 0) {
2277                 cmd->phy_address = p->mdio_addr;
2278                 cmd->transceiver = XCVR_EXTERNAL;
2279                 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2280                         MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2281         } else {
2282                 cmd->phy_address = 0;  /* not really, but no better option */
2283                 cmd->transceiver = XCVR_INTERNAL;
2284                 cmd->mdio_support = 0;
2285         }
2286
2287         cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2288         cmd->advertising = from_fw_linkcaps(p->port_type,
2289                                             p->link_cfg.advertising);
2290         ethtool_cmd_speed_set(cmd,
2291                               netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
2292         cmd->duplex = DUPLEX_FULL;
2293         cmd->autoneg = p->link_cfg.autoneg;
2294         cmd->maxtxpkt = 0;
2295         cmd->maxrxpkt = 0;
2296         return 0;
2297 }
2298
2299 static unsigned int speed_to_caps(int speed)
2300 {
2301         if (speed == SPEED_100)
2302                 return FW_PORT_CAP_SPEED_100M;
2303         if (speed == SPEED_1000)
2304                 return FW_PORT_CAP_SPEED_1G;
2305         if (speed == SPEED_10000)
2306                 return FW_PORT_CAP_SPEED_10G;
2307         return 0;
2308 }
2309
2310 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2311 {
2312         unsigned int cap;
2313         struct port_info *p = netdev_priv(dev);
2314         struct link_config *lc = &p->link_cfg;
2315         u32 speed = ethtool_cmd_speed(cmd);
2316
2317         if (cmd->duplex != DUPLEX_FULL)     /* only full-duplex supported */
2318                 return -EINVAL;
2319
2320         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2321                 /*
2322                  * PHY offers a single speed.  See if that's what's
2323                  * being requested.
2324                  */
2325                 if (cmd->autoneg == AUTONEG_DISABLE &&
2326                     (lc->supported & speed_to_caps(speed)))
2327                         return 0;
2328                 return -EINVAL;
2329         }
2330
2331         if (cmd->autoneg == AUTONEG_DISABLE) {
2332                 cap = speed_to_caps(speed);
2333
2334                 if (!(lc->supported & cap) || (speed == SPEED_1000) ||
2335                     (speed == SPEED_10000))
2336                         return -EINVAL;
2337                 lc->requested_speed = cap;
2338                 lc->advertising = 0;
2339         } else {
2340                 cap = to_fw_linkcaps(cmd->advertising);
2341                 if (!(lc->supported & cap))
2342                         return -EINVAL;
2343                 lc->requested_speed = 0;
2344                 lc->advertising = cap | FW_PORT_CAP_ANEG;
2345         }
2346         lc->autoneg = cmd->autoneg;
2347
2348         if (netif_running(dev))
2349                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2350                                      lc);
2351         return 0;
2352 }
2353
2354 static void get_pauseparam(struct net_device *dev,
2355                            struct ethtool_pauseparam *epause)
2356 {
2357         struct port_info *p = netdev_priv(dev);
2358
2359         epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2360         epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2361         epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2362 }
2363
2364 static int set_pauseparam(struct net_device *dev,
2365                           struct ethtool_pauseparam *epause)
2366 {
2367         struct port_info *p = netdev_priv(dev);
2368         struct link_config *lc = &p->link_cfg;
2369
2370         if (epause->autoneg == AUTONEG_DISABLE)
2371                 lc->requested_fc = 0;
2372         else if (lc->supported & FW_PORT_CAP_ANEG)
2373                 lc->requested_fc = PAUSE_AUTONEG;
2374         else
2375                 return -EINVAL;
2376
2377         if (epause->rx_pause)
2378                 lc->requested_fc |= PAUSE_RX;
2379         if (epause->tx_pause)
2380                 lc->requested_fc |= PAUSE_TX;
2381         if (netif_running(dev))
2382                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2383                                      lc);
2384         return 0;
2385 }
2386
2387 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2388 {
2389         const struct port_info *pi = netdev_priv(dev);
2390         const struct sge *s = &pi->adapter->sge;
2391
2392         e->rx_max_pending = MAX_RX_BUFFERS;
2393         e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2394         e->rx_jumbo_max_pending = 0;
2395         e->tx_max_pending = MAX_TXQ_ENTRIES;
2396
2397         e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2398         e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2399         e->rx_jumbo_pending = 0;
2400         e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2401 }
2402
2403 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2404 {
2405         int i;
2406         const struct port_info *pi = netdev_priv(dev);
2407         struct adapter *adapter = pi->adapter;
2408         struct sge *s = &adapter->sge;
2409
2410         if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2411             e->tx_pending > MAX_TXQ_ENTRIES ||
2412             e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2413             e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2414             e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2415                 return -EINVAL;
2416
2417         if (adapter->flags & FULL_INIT_DONE)
2418                 return -EBUSY;
2419
2420         for (i = 0; i < pi->nqsets; ++i) {
2421                 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2422                 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2423                 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2424         }
2425         return 0;
2426 }
2427
2428 static int closest_timer(const struct sge *s, int time)
2429 {
2430         int i, delta, match = 0, min_delta = INT_MAX;
2431
2432         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2433                 delta = time - s->timer_val[i];
2434                 if (delta < 0)
2435                         delta = -delta;
2436                 if (delta < min_delta) {
2437                         min_delta = delta;
2438                         match = i;
2439                 }
2440         }
2441         return match;
2442 }
2443
2444 static int closest_thres(const struct sge *s, int thres)
2445 {
2446         int i, delta, match = 0, min_delta = INT_MAX;
2447
2448         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2449                 delta = thres - s->counter_val[i];
2450                 if (delta < 0)
2451                         delta = -delta;
2452                 if (delta < min_delta) {
2453                         min_delta = delta;
2454                         match = i;
2455                 }
2456         }
2457         return match;
2458 }
2459
2460 /*
2461  * Return a queue's interrupt hold-off time in us.  0 means no timer.
2462  */
2463 static unsigned int qtimer_val(const struct adapter *adap,
2464                                const struct sge_rspq *q)
2465 {
2466         unsigned int idx = q->intr_params >> 1;
2467
2468         return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2469 }
2470
2471 /**
2472  *      set_rxq_intr_params - set a queue's interrupt holdoff parameters
2473  *      @adap: the adapter
2474  *      @q: the Rx queue
2475  *      @us: the hold-off time in us, or 0 to disable timer
2476  *      @cnt: the hold-off packet count, or 0 to disable counter
2477  *
2478  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
2479  *      one of the two needs to be enabled for the queue to generate interrupts.
2480  */
2481 static int set_rxq_intr_params(struct adapter *adap, struct sge_rspq *q,
2482                                unsigned int us, unsigned int cnt)
2483 {
2484         if ((us | cnt) == 0)
2485                 cnt = 1;
2486
2487         if (cnt) {
2488                 int err;
2489                 u32 v, new_idx;
2490
2491                 new_idx = closest_thres(&adap->sge, cnt);
2492                 if (q->desc && q->pktcnt_idx != new_idx) {
2493                         /* the queue has already been created, update it */
2494                         v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2495                             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2496                             FW_PARAMS_PARAM_YZ(q->cntxt_id);
2497                         err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2498                                             &new_idx);
2499                         if (err)
2500                                 return err;
2501                 }
2502                 q->pktcnt_idx = new_idx;
2503         }
2504
2505         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2506         q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2507         return 0;
2508 }
2509
2510 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2511 {
2512         const struct port_info *pi = netdev_priv(dev);
2513         struct adapter *adap = pi->adapter;
2514         struct sge_rspq *q;
2515         int i;
2516         int r = 0;
2517
2518         for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) {
2519                 q = &adap->sge.ethrxq[i].rspq;
2520                 r = set_rxq_intr_params(adap, q, c->rx_coalesce_usecs,
2521                         c->rx_max_coalesced_frames);
2522                 if (r) {
2523                         dev_err(&dev->dev, "failed to set coalesce %d\n", r);
2524                         break;
2525                 }
2526         }
2527         return r;
2528 }
2529
2530 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2531 {
2532         const struct port_info *pi = netdev_priv(dev);
2533         const struct adapter *adap = pi->adapter;
2534         const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2535
2536         c->rx_coalesce_usecs = qtimer_val(adap, rq);
2537         c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2538                 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2539         return 0;
2540 }
2541
2542 /**
2543  *      eeprom_ptov - translate a physical EEPROM address to virtual
2544  *      @phys_addr: the physical EEPROM address
2545  *      @fn: the PCI function number
2546  *      @sz: size of function-specific area
2547  *
2548  *      Translate a physical EEPROM address to virtual.  The first 1K is
2549  *      accessed through virtual addresses starting at 31K, the rest is
2550  *      accessed through virtual addresses starting at 0.
2551  *
2552  *      The mapping is as follows:
2553  *      [0..1K) -> [31K..32K)
2554  *      [1K..1K+A) -> [31K-A..31K)
2555  *      [1K+A..ES) -> [0..ES-A-1K)
2556  *
2557  *      where A = @fn * @sz, and ES = EEPROM size.
2558  */
2559 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2560 {
2561         fn *= sz;
2562         if (phys_addr < 1024)
2563                 return phys_addr + (31 << 10);
2564         if (phys_addr < 1024 + fn)
2565                 return 31744 - fn + phys_addr - 1024;
2566         if (phys_addr < EEPROMSIZE)
2567                 return phys_addr - 1024 - fn;
2568         return -EINVAL;
2569 }
2570
2571 /*
2572  * The next two routines implement eeprom read/write from physical addresses.
2573  */
2574 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2575 {
2576         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2577
2578         if (vaddr >= 0)
2579                 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2580         return vaddr < 0 ? vaddr : 0;
2581 }
2582
2583 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2584 {
2585         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2586
2587         if (vaddr >= 0)
2588                 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2589         return vaddr < 0 ? vaddr : 0;
2590 }
2591
2592 #define EEPROM_MAGIC 0x38E2F10C
2593
2594 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2595                       u8 *data)
2596 {
2597         int i, err = 0;
2598         struct adapter *adapter = netdev2adap(dev);
2599
2600         u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2601         if (!buf)
2602                 return -ENOMEM;
2603
2604         e->magic = EEPROM_MAGIC;
2605         for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2606                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2607
2608         if (!err)
2609                 memcpy(data, buf + e->offset, e->len);
2610         kfree(buf);
2611         return err;
2612 }
2613
2614 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2615                       u8 *data)
2616 {
2617         u8 *buf;
2618         int err = 0;
2619         u32 aligned_offset, aligned_len, *p;
2620         struct adapter *adapter = netdev2adap(dev);
2621
2622         if (eeprom->magic != EEPROM_MAGIC)
2623                 return -EINVAL;
2624
2625         aligned_offset = eeprom->offset & ~3;
2626         aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2627
2628         if (adapter->fn > 0) {
2629                 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2630
2631                 if (aligned_offset < start ||
2632                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
2633                         return -EPERM;
2634         }
2635
2636         if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2637                 /*
2638                  * RMW possibly needed for first or last words.
2639                  */
2640                 buf = kmalloc(aligned_len, GFP_KERNEL);
2641                 if (!buf)
2642                         return -ENOMEM;
2643                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2644                 if (!err && aligned_len > 4)
2645                         err = eeprom_rd_phys(adapter,
2646                                              aligned_offset + aligned_len - 4,
2647                                              (u32 *)&buf[aligned_len - 4]);
2648                 if (err)
2649                         goto out;
2650                 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2651         } else
2652                 buf = data;
2653
2654         err = t4_seeprom_wp(adapter, false);
2655         if (err)
2656                 goto out;
2657
2658         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2659                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2660                 aligned_offset += 4;
2661         }
2662
2663         if (!err)
2664                 err = t4_seeprom_wp(adapter, true);
2665 out:
2666         if (buf != data)
2667                 kfree(buf);
2668         return err;
2669 }
2670
2671 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2672 {
2673         int ret;
2674         const struct firmware *fw;
2675         struct adapter *adap = netdev2adap(netdev);
2676
2677         ef->data[sizeof(ef->data) - 1] = '\0';
2678         ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2679         if (ret < 0)
2680                 return ret;
2681
2682         ret = t4_load_fw(adap, fw->data, fw->size);
2683         release_firmware(fw);
2684         if (!ret)
2685                 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
2686         return ret;
2687 }
2688
2689 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2690 #define BCAST_CRC 0xa0ccc1a6
2691
2692 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2693 {
2694         wol->supported = WAKE_BCAST | WAKE_MAGIC;
2695         wol->wolopts = netdev2adap(dev)->wol;
2696         memset(&wol->sopass, 0, sizeof(wol->sopass));
2697 }
2698
2699 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2700 {
2701         int err = 0;
2702         struct port_info *pi = netdev_priv(dev);
2703
2704         if (wol->wolopts & ~WOL_SUPPORTED)
2705                 return -EINVAL;
2706         t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2707                             (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2708         if (wol->wolopts & WAKE_BCAST) {
2709                 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2710                                         ~0ULL, 0, false);
2711                 if (!err)
2712                         err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2713                                                 ~6ULL, ~0ULL, BCAST_CRC, true);
2714         } else
2715                 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2716         return err;
2717 }
2718
2719 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2720 {
2721         const struct port_info *pi = netdev_priv(dev);
2722         netdev_features_t changed = dev->features ^ features;
2723         int err;
2724
2725         if (!(changed & NETIF_F_HW_VLAN_RX))
2726                 return 0;
2727
2728         err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2729                             -1, -1, -1,
2730                             !!(features & NETIF_F_HW_VLAN_RX), true);
2731         if (unlikely(err))
2732                 dev->features = features ^ NETIF_F_HW_VLAN_RX;
2733         return err;
2734 }
2735
2736 static u32 get_rss_table_size(struct net_device *dev)
2737 {
2738         const struct port_info *pi = netdev_priv(dev);
2739
2740         return pi->rss_size;
2741 }
2742
2743 static int get_rss_table(struct net_device *dev, u32 *p)
2744 {
2745         const struct port_info *pi = netdev_priv(dev);
2746         unsigned int n = pi->rss_size;
2747
2748         while (n--)
2749                 p[n] = pi->rss[n];
2750         return 0;
2751 }
2752
2753 static int set_rss_table(struct net_device *dev, const u32 *p)
2754 {
2755         unsigned int i;
2756         struct port_info *pi = netdev_priv(dev);
2757
2758         for (i = 0; i < pi->rss_size; i++)
2759                 pi->rss[i] = p[i];
2760         if (pi->adapter->flags & FULL_INIT_DONE)
2761                 return write_rss(pi, pi->rss);
2762         return 0;
2763 }
2764
2765 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2766                      u32 *rules)
2767 {
2768         const struct port_info *pi = netdev_priv(dev);
2769
2770         switch (info->cmd) {
2771         case ETHTOOL_GRXFH: {
2772                 unsigned int v = pi->rss_mode;
2773
2774                 info->data = 0;
2775                 switch (info->flow_type) {
2776                 case TCP_V4_FLOW:
2777                         if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2778                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2779                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2780                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2781                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2782                         break;
2783                 case UDP_V4_FLOW:
2784                         if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
2785                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
2786                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2787                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2788                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2789                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2790                         break;
2791                 case SCTP_V4_FLOW:
2792                 case AH_ESP_V4_FLOW:
2793                 case IPV4_FLOW:
2794                         if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2795                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2796                         break;
2797                 case TCP_V6_FLOW:
2798                         if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2799                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2800                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2801                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2802                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2803                         break;
2804                 case UDP_V6_FLOW:
2805                         if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
2806                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
2807                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2808                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2809                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2810                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2811                         break;
2812                 case SCTP_V6_FLOW:
2813                 case AH_ESP_V6_FLOW:
2814                 case IPV6_FLOW:
2815                         if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2816                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2817                         break;
2818                 }
2819                 return 0;
2820         }
2821         case ETHTOOL_GRXRINGS:
2822                 info->data = pi->nqsets;
2823                 return 0;
2824         }
2825         return -EOPNOTSUPP;
2826 }
2827
2828 static const struct ethtool_ops cxgb_ethtool_ops = {
2829         .get_settings      = get_settings,
2830         .set_settings      = set_settings,
2831         .get_drvinfo       = get_drvinfo,
2832         .get_msglevel      = get_msglevel,
2833         .set_msglevel      = set_msglevel,
2834         .get_ringparam     = get_sge_param,
2835         .set_ringparam     = set_sge_param,
2836         .get_coalesce      = get_coalesce,
2837         .set_coalesce      = set_coalesce,
2838         .get_eeprom_len    = get_eeprom_len,
2839         .get_eeprom        = get_eeprom,
2840         .set_eeprom        = set_eeprom,
2841         .get_pauseparam    = get_pauseparam,
2842         .set_pauseparam    = set_pauseparam,
2843         .get_link          = ethtool_op_get_link,
2844         .get_strings       = get_strings,
2845         .set_phys_id       = identify_port,
2846         .nway_reset        = restart_autoneg,
2847         .get_sset_count    = get_sset_count,
2848         .get_ethtool_stats = get_stats,
2849         .get_regs_len      = get_regs_len,
2850         .get_regs          = get_regs,
2851         .get_wol           = get_wol,
2852         .set_wol           = set_wol,
2853         .get_rxnfc         = get_rxnfc,
2854         .get_rxfh_indir_size = get_rss_table_size,
2855         .get_rxfh_indir    = get_rss_table,
2856         .set_rxfh_indir    = set_rss_table,
2857         .flash_device      = set_flash,
2858 };
2859
2860 /*
2861  * debugfs support
2862  */
2863 static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
2864                         loff_t *ppos)
2865 {
2866         loff_t pos = *ppos;
2867         loff_t avail = file_inode(file)->i_size;
2868         unsigned int mem = (uintptr_t)file->private_data & 3;
2869         struct adapter *adap = file->private_data - mem;
2870
2871         if (pos < 0)
2872                 return -EINVAL;
2873         if (pos >= avail)
2874                 return 0;
2875         if (count > avail - pos)
2876                 count = avail - pos;
2877
2878         while (count) {
2879                 size_t len;
2880                 int ret, ofst;
2881                 __be32 data[16];
2882
2883                 if ((mem == MEM_MC) || (mem == MEM_MC1))
2884                         ret = t4_mc_read(adap, mem % MEM_MC, pos, data, NULL);
2885                 else
2886                         ret = t4_edc_read(adap, mem, pos, data, NULL);
2887                 if (ret)
2888                         return ret;
2889
2890                 ofst = pos % sizeof(data);
2891                 len = min(count, sizeof(data) - ofst);
2892                 if (copy_to_user(buf, (u8 *)data + ofst, len))
2893                         return -EFAULT;
2894
2895                 buf += len;
2896                 pos += len;
2897                 count -= len;
2898         }
2899         count = pos - *ppos;
2900         *ppos = pos;
2901         return count;
2902 }
2903
2904 static const struct file_operations mem_debugfs_fops = {
2905         .owner   = THIS_MODULE,
2906         .open    = simple_open,
2907         .read    = mem_read,
2908         .llseek  = default_llseek,
2909 };
2910
2911 static void add_debugfs_mem(struct adapter *adap, const char *name,
2912                             unsigned int idx, unsigned int size_mb)
2913 {
2914         struct dentry *de;
2915
2916         de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
2917                                  (void *)adap + idx, &mem_debugfs_fops);
2918         if (de && de->d_inode)
2919                 de->d_inode->i_size = size_mb << 20;
2920 }
2921
2922 static int setup_debugfs(struct adapter *adap)
2923 {
2924         int i;
2925         u32 size;
2926
2927         if (IS_ERR_OR_NULL(adap->debugfs_root))
2928                 return -1;
2929
2930         i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
2931         if (i & EDRAM0_ENABLE) {
2932                 size = t4_read_reg(adap, MA_EDRAM0_BAR);
2933                 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM_SIZE_GET(size));
2934         }
2935         if (i & EDRAM1_ENABLE) {
2936                 size = t4_read_reg(adap, MA_EDRAM1_BAR);
2937                 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM_SIZE_GET(size));
2938         }
2939         if (is_t4(adap->chip)) {
2940                 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
2941                 if (i & EXT_MEM_ENABLE)
2942                         add_debugfs_mem(adap, "mc", MEM_MC,
2943                                         EXT_MEM_SIZE_GET(size));
2944         } else {
2945                 if (i & EXT_MEM_ENABLE) {
2946                         size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
2947                         add_debugfs_mem(adap, "mc0", MEM_MC0,
2948                                         EXT_MEM_SIZE_GET(size));
2949                 }
2950                 if (i & EXT_MEM1_ENABLE) {
2951                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR);
2952                         add_debugfs_mem(adap, "mc1", MEM_MC1,
2953                                         EXT_MEM_SIZE_GET(size));
2954                 }
2955         }
2956         if (adap->l2t)
2957                 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
2958                                     &t4_l2t_fops);
2959         return 0;
2960 }
2961
2962 /*
2963  * upper-layer driver support
2964  */
2965
2966 /*
2967  * Allocate an active-open TID and set it to the supplied value.
2968  */
2969 int cxgb4_alloc_atid(struct tid_info *t, void *data)
2970 {
2971         int atid = -1;
2972
2973         spin_lock_bh(&t->atid_lock);
2974         if (t->afree) {
2975                 union aopen_entry *p = t->afree;
2976
2977                 atid = (p - t->atid_tab) + t->atid_base;
2978                 t->afree = p->next;
2979                 p->data = data;
2980                 t->atids_in_use++;
2981         }
2982         spin_unlock_bh(&t->atid_lock);
2983         return atid;
2984 }
2985 EXPORT_SYMBOL(cxgb4_alloc_atid);
2986
2987 /*
2988  * Release an active-open TID.
2989  */
2990 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
2991 {
2992         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
2993
2994         spin_lock_bh(&t->atid_lock);
2995         p->next = t->afree;
2996         t->afree = p;
2997         t->atids_in_use--;
2998         spin_unlock_bh(&t->atid_lock);
2999 }
3000 EXPORT_SYMBOL(cxgb4_free_atid);
3001
3002 /*
3003  * Allocate a server TID and set it to the supplied value.
3004  */
3005 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3006 {
3007         int stid;
3008
3009         spin_lock_bh(&t->stid_lock);
3010         if (family == PF_INET) {
3011                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3012                 if (stid < t->nstids)
3013                         __set_bit(stid, t->stid_bmap);
3014                 else
3015                         stid = -1;
3016         } else {
3017                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3018                 if (stid < 0)
3019                         stid = -1;
3020         }
3021         if (stid >= 0) {
3022                 t->stid_tab[stid].data = data;
3023                 stid += t->stid_base;
3024                 t->stids_in_use++;
3025         }
3026         spin_unlock_bh(&t->stid_lock);
3027         return stid;
3028 }
3029 EXPORT_SYMBOL(cxgb4_alloc_stid);
3030
3031 /* Allocate a server filter TID and set it to the supplied value.
3032  */
3033 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3034 {
3035         int stid;
3036
3037         spin_lock_bh(&t->stid_lock);
3038         if (family == PF_INET) {
3039                 stid = find_next_zero_bit(t->stid_bmap,
3040                                 t->nstids + t->nsftids, t->nstids);
3041                 if (stid < (t->nstids + t->nsftids))
3042                         __set_bit(stid, t->stid_bmap);
3043                 else
3044                         stid = -1;
3045         } else {
3046                 stid = -1;
3047         }
3048         if (stid >= 0) {
3049                 t->stid_tab[stid].data = data;
3050                 stid += t->stid_base;
3051                 t->stids_in_use++;
3052         }
3053         spin_unlock_bh(&t->stid_lock);
3054         return stid;
3055 }
3056 EXPORT_SYMBOL(cxgb4_alloc_sftid);
3057
3058 /* Release a server TID.
3059  */
3060 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3061 {
3062         stid -= t->stid_base;
3063         spin_lock_bh(&t->stid_lock);
3064         if (family == PF_INET)
3065                 __clear_bit(stid, t->stid_bmap);
3066         else
3067                 bitmap_release_region(t->stid_bmap, stid, 2);
3068         t->stid_tab[stid].data = NULL;
3069         t->stids_in_use--;
3070         spin_unlock_bh(&t->stid_lock);
3071 }
3072 EXPORT_SYMBOL(cxgb4_free_stid);
3073
3074 /*
3075  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
3076  */
3077 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3078                            unsigned int tid)
3079 {
3080         struct cpl_tid_release *req;
3081
3082         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3083         req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3084         INIT_TP_WR(req, tid);
3085         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3086 }
3087
3088 /*
3089  * Queue a TID release request and if necessary schedule a work queue to
3090  * process it.
3091  */
3092 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3093                                     unsigned int tid)
3094 {
3095         void **p = &t->tid_tab[tid];
3096         struct adapter *adap = container_of(t, struct adapter, tids);
3097
3098         spin_lock_bh(&adap->tid_release_lock);
3099         *p = adap->tid_release_head;
3100         /* Low 2 bits encode the Tx channel number */
3101         adap->tid_release_head = (void **)((uintptr_t)p | chan);
3102         if (!adap->tid_release_task_busy) {
3103                 adap->tid_release_task_busy = true;
3104                 queue_work(workq, &adap->tid_release_task);
3105         }
3106         spin_unlock_bh(&adap->tid_release_lock);
3107 }
3108
3109 /*
3110  * Process the list of pending TID release requests.
3111  */
3112 static void process_tid_release_list(struct work_struct *work)
3113 {
3114         struct sk_buff *skb;
3115         struct adapter *adap;
3116
3117         adap = container_of(work, struct adapter, tid_release_task);
3118
3119         spin_lock_bh(&adap->tid_release_lock);
3120         while (adap->tid_release_head) {
3121                 void **p = adap->tid_release_head;
3122                 unsigned int chan = (uintptr_t)p & 3;
3123                 p = (void *)p - chan;
3124
3125                 adap->tid_release_head = *p;
3126                 *p = NULL;
3127                 spin_unlock_bh(&adap->tid_release_lock);
3128
3129                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3130                                          GFP_KERNEL)))
3131                         schedule_timeout_uninterruptible(1);
3132
3133                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3134                 t4_ofld_send(adap, skb);
3135                 spin_lock_bh(&adap->tid_release_lock);
3136         }
3137         adap->tid_release_task_busy = false;
3138         spin_unlock_bh(&adap->tid_release_lock);
3139 }
3140
3141 /*
3142  * Release a TID and inform HW.  If we are unable to allocate the release
3143  * message we defer to a work queue.
3144  */
3145 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3146 {
3147         void *old;
3148         struct sk_buff *skb;
3149         struct adapter *adap = container_of(t, struct adapter, tids);
3150
3151         old = t->tid_tab[tid];
3152         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3153         if (likely(skb)) {
3154                 t->tid_tab[tid] = NULL;
3155                 mk_tid_release(skb, chan, tid);
3156                 t4_ofld_send(adap, skb);
3157         } else
3158                 cxgb4_queue_tid_release(t, chan, tid);
3159         if (old)
3160                 atomic_dec(&t->tids_in_use);
3161 }
3162 EXPORT_SYMBOL(cxgb4_remove_tid);
3163
3164 /*
3165  * Allocate and initialize the TID tables.  Returns 0 on success.
3166  */
3167 static int tid_init(struct tid_info *t)
3168 {
3169         size_t size;
3170         unsigned int stid_bmap_size;
3171         unsigned int natids = t->natids;
3172
3173         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
3174         size = t->ntids * sizeof(*t->tid_tab) +
3175                natids * sizeof(*t->atid_tab) +
3176                t->nstids * sizeof(*t->stid_tab) +
3177                t->nsftids * sizeof(*t->stid_tab) +
3178                stid_bmap_size * sizeof(long) +
3179                t->nftids * sizeof(*t->ftid_tab) +
3180                t->nsftids * sizeof(*t->ftid_tab);
3181
3182         t->tid_tab = t4_alloc_mem(size);
3183         if (!t->tid_tab)
3184                 return -ENOMEM;
3185
3186         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3187         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
3188         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
3189         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
3190         spin_lock_init(&t->stid_lock);
3191         spin_lock_init(&t->atid_lock);
3192
3193         t->stids_in_use = 0;
3194         t->afree = NULL;
3195         t->atids_in_use = 0;
3196         atomic_set(&t->tids_in_use, 0);
3197
3198         /* Setup the free list for atid_tab and clear the stid bitmap. */
3199         if (natids) {
3200                 while (--natids)
3201                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3202                 t->afree = t->atid_tab;
3203         }
3204         bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
3205         return 0;
3206 }
3207
3208 /**
3209  *      cxgb4_create_server - create an IP server
3210  *      @dev: the device
3211  *      @stid: the server TID
3212  *      @sip: local IP address to bind server to
3213  *      @sport: the server's TCP port
3214  *      @queue: queue to direct messages from this server to
3215  *
3216  *      Create an IP server for the given port and address.
3217  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3218  */
3219 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
3220                         __be32 sip, __be16 sport, __be16 vlan,
3221                         unsigned int queue)
3222 {
3223         unsigned int chan;
3224         struct sk_buff *skb;
3225         struct adapter *adap;
3226         struct cpl_pass_open_req *req;
3227
3228         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3229         if (!skb)
3230                 return -ENOMEM;
3231
3232         adap = netdev2adap(dev);
3233         req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3234         INIT_TP_WR(req, 0);
3235         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3236         req->local_port = sport;
3237         req->peer_port = htons(0);
3238         req->local_ip = sip;
3239         req->peer_ip = htonl(0);
3240         chan = rxq_to_chan(&adap->sge, queue);
3241         req->opt0 = cpu_to_be64(TX_CHAN(chan));
3242         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3243                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3244         return t4_mgmt_tx(adap, skb);
3245 }
3246 EXPORT_SYMBOL(cxgb4_create_server);
3247
3248 /**
3249  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3250  *      @mtus: the HW MTU table
3251  *      @mtu: the target MTU
3252  *      @idx: index of selected entry in the MTU table
3253  *
3254  *      Returns the index and the value in the HW MTU table that is closest to
3255  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
3256  *      table, in which case that smallest available value is selected.
3257  */
3258 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3259                             unsigned int *idx)
3260 {
3261         unsigned int i = 0;
3262
3263         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3264                 ++i;
3265         if (idx)
3266                 *idx = i;
3267         return mtus[i];
3268 }
3269 EXPORT_SYMBOL(cxgb4_best_mtu);
3270
3271 /**
3272  *      cxgb4_port_chan - get the HW channel of a port
3273  *      @dev: the net device for the port
3274  *
3275  *      Return the HW Tx channel of the given port.
3276  */
3277 unsigned int cxgb4_port_chan(const struct net_device *dev)
3278 {
3279         return netdev2pinfo(dev)->tx_chan;
3280 }
3281 EXPORT_SYMBOL(cxgb4_port_chan);
3282
3283 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3284 {
3285         struct adapter *adap = netdev2adap(dev);
3286         u32 v1, v2, lp_count, hp_count;
3287
3288         v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3289         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3290         if (is_t4(adap->chip)) {
3291                 lp_count = G_LP_COUNT(v1);
3292                 hp_count = G_HP_COUNT(v1);
3293         } else {
3294                 lp_count = G_LP_COUNT_T5(v1);
3295                 hp_count = G_HP_COUNT_T5(v2);
3296         }
3297         return lpfifo ? lp_count : hp_count;
3298 }
3299 EXPORT_SYMBOL(cxgb4_dbfifo_count);
3300
3301 /**
3302  *      cxgb4_port_viid - get the VI id of a port
3303  *      @dev: the net device for the port
3304  *
3305  *      Return the VI id of the given port.
3306  */
3307 unsigned int cxgb4_port_viid(const struct net_device *dev)
3308 {
3309         return netdev2pinfo(dev)->viid;
3310 }
3311 EXPORT_SYMBOL(cxgb4_port_viid);
3312
3313 /**
3314  *      cxgb4_port_idx - get the index of a port
3315  *      @dev: the net device for the port
3316  *
3317  *      Return the index of the given port.
3318  */
3319 unsigned int cxgb4_port_idx(const struct net_device *dev)
3320 {
3321         return netdev2pinfo(dev)->port_id;
3322 }
3323 EXPORT_SYMBOL(cxgb4_port_idx);
3324
3325 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3326                          struct tp_tcp_stats *v6)
3327 {
3328         struct adapter *adap = pci_get_drvdata(pdev);
3329
3330         spin_lock(&adap->stats_lock);
3331         t4_tp_get_tcp_stats(adap, v4, v6);
3332         spin_unlock(&adap->stats_lock);
3333 }
3334 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3335
3336 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3337                       const unsigned int *pgsz_order)
3338 {
3339         struct adapter *adap = netdev2adap(dev);
3340
3341         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3342         t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3343                      HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3344                      HPZ3(pgsz_order[3]));
3345 }
3346 EXPORT_SYMBOL(cxgb4_iscsi_init);
3347
3348 int cxgb4_flush_eq_cache(struct net_device *dev)
3349 {
3350         struct adapter *adap = netdev2adap(dev);
3351         int ret;
3352
3353         ret = t4_fwaddrspace_write(adap, adap->mbox,
3354                                    0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3355         return ret;
3356 }
3357 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3358
3359 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3360 {
3361         u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3362         __be64 indices;
3363         int ret;
3364
3365         ret = t4_mem_win_read_len(adap, addr, (__be32 *)&indices, 8);
3366         if (!ret) {
3367                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3368                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3369         }
3370         return ret;
3371 }
3372
3373 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3374                         u16 size)
3375 {
3376         struct adapter *adap = netdev2adap(dev);
3377         u16 hw_pidx, hw_cidx;
3378         int ret;
3379
3380         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3381         if (ret)
3382                 goto out;
3383
3384         if (pidx != hw_pidx) {
3385                 u16 delta;
3386
3387                 if (pidx >= hw_pidx)
3388                         delta = pidx - hw_pidx;
3389                 else
3390                         delta = size - hw_pidx + pidx;
3391                 wmb();
3392                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3393                              QID(qid) | PIDX(delta));
3394         }
3395 out:
3396         return ret;
3397 }
3398 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3399
3400 void cxgb4_disable_db_coalescing(struct net_device *dev)
3401 {
3402         struct adapter *adap;
3403
3404         adap = netdev2adap(dev);
3405         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3406                          F_NOCOALESCE);
3407 }
3408 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3409
3410 void cxgb4_enable_db_coalescing(struct net_device *dev)
3411 {
3412         struct adapter *adap;
3413
3414         adap = netdev2adap(dev);
3415         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3416 }
3417 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3418
3419 static struct pci_driver cxgb4_driver;
3420
3421 static void check_neigh_update(struct neighbour *neigh)
3422 {
3423         const struct device *parent;
3424         const struct net_device *netdev = neigh->dev;
3425
3426         if (netdev->priv_flags & IFF_802_1Q_VLAN)
3427                 netdev = vlan_dev_real_dev(netdev);
3428         parent = netdev->dev.parent;
3429         if (parent && parent->driver == &cxgb4_driver.driver)
3430                 t4_l2t_update(dev_get_drvdata(parent), neigh);
3431 }
3432
3433 static int netevent_cb(struct notifier_block *nb, unsigned long event,
3434                        void *data)
3435 {
3436         switch (event) {
3437         case NETEVENT_NEIGH_UPDATE:
3438                 check_neigh_update(data);
3439                 break;
3440         case NETEVENT_REDIRECT:
3441         default:
3442                 break;
3443         }
3444         return 0;
3445 }
3446
3447 static bool netevent_registered;
3448 static struct notifier_block cxgb4_netevent_nb = {
3449         .notifier_call = netevent_cb
3450 };
3451
3452 static void drain_db_fifo(struct adapter *adap, int usecs)
3453 {
3454         u32 v1, v2, lp_count, hp_count;
3455
3456         do {
3457                 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3458                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3459                 if (is_t4(adap->chip)) {
3460                         lp_count = G_LP_COUNT(v1);
3461                         hp_count = G_HP_COUNT(v1);
3462                 } else {
3463                         lp_count = G_LP_COUNT_T5(v1);
3464                         hp_count = G_HP_COUNT_T5(v2);
3465                 }
3466
3467                 if (lp_count == 0 && hp_count == 0)
3468                         break;
3469                 set_current_state(TASK_UNINTERRUPTIBLE);
3470                 schedule_timeout(usecs_to_jiffies(usecs));
3471         } while (1);
3472 }
3473
3474 static void disable_txq_db(struct sge_txq *q)
3475 {
3476         spin_lock_irq(&q->db_lock);
3477         q->db_disabled = 1;
3478         spin_unlock_irq(&q->db_lock);
3479 }
3480
3481 static void enable_txq_db(struct sge_txq *q)
3482 {
3483         spin_lock_irq(&q->db_lock);
3484         q->db_disabled = 0;
3485         spin_unlock_irq(&q->db_lock);
3486 }
3487
3488 static void disable_dbs(struct adapter *adap)
3489 {
3490         int i;
3491
3492         for_each_ethrxq(&adap->sge, i)
3493                 disable_txq_db(&adap->sge.ethtxq[i].q);
3494         for_each_ofldrxq(&adap->sge, i)
3495                 disable_txq_db(&adap->sge.ofldtxq[i].q);
3496         for_each_port(adap, i)
3497                 disable_txq_db(&adap->sge.ctrlq[i].q);
3498 }
3499
3500 static void enable_dbs(struct adapter *adap)
3501 {
3502         int i;
3503
3504         for_each_ethrxq(&adap->sge, i)
3505                 enable_txq_db(&adap->sge.ethtxq[i].q);
3506         for_each_ofldrxq(&adap->sge, i)
3507                 enable_txq_db(&adap->sge.ofldtxq[i].q);
3508         for_each_port(adap, i)
3509                 enable_txq_db(&adap->sge.ctrlq[i].q);
3510 }
3511
3512 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
3513 {
3514         u16 hw_pidx, hw_cidx;
3515         int ret;
3516
3517         spin_lock_bh(&q->db_lock);
3518         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
3519         if (ret)
3520                 goto out;
3521         if (q->db_pidx != hw_pidx) {
3522                 u16 delta;
3523
3524                 if (q->db_pidx >= hw_pidx)
3525                         delta = q->db_pidx - hw_pidx;
3526                 else
3527                         delta = q->size - hw_pidx + q->db_pidx;
3528                 wmb();
3529                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3530                              QID(q->cntxt_id) | PIDX(delta));
3531         }
3532 out:
3533         q->db_disabled = 0;
3534         spin_unlock_bh(&q->db_lock);
3535         if (ret)
3536                 CH_WARN(adap, "DB drop recovery failed.\n");
3537 }
3538 static void recover_all_queues(struct adapter *adap)
3539 {
3540         int i;
3541
3542         for_each_ethrxq(&adap->sge, i)
3543                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
3544         for_each_ofldrxq(&adap->sge, i)
3545                 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
3546         for_each_port(adap, i)
3547                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
3548 }
3549
3550 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
3551 {
3552         mutex_lock(&uld_mutex);
3553         if (adap->uld_handle[CXGB4_ULD_RDMA])
3554                 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
3555                                 cmd);
3556         mutex_unlock(&uld_mutex);
3557 }
3558
3559 static void process_db_full(struct work_struct *work)
3560 {
3561         struct adapter *adap;
3562
3563         adap = container_of(work, struct adapter, db_full_task);
3564
3565         notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
3566         drain_db_fifo(adap, dbfifo_drain_delay);
3567         t4_set_reg_field(adap, SGE_INT_ENABLE3,
3568                          DBFIFO_HP_INT | DBFIFO_LP_INT,
3569                          DBFIFO_HP_INT | DBFIFO_LP_INT);
3570         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3571 }
3572
3573 static void process_db_drop(struct work_struct *work)
3574 {
3575         struct adapter *adap;
3576
3577         adap = container_of(work, struct adapter, db_drop_task);
3578
3579         if (is_t4(adap->chip)) {
3580                 disable_dbs(adap);
3581                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
3582                 drain_db_fifo(adap, 1);
3583                 recover_all_queues(adap);
3584                 enable_dbs(adap);
3585         } else {
3586                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
3587                 u16 qid = (dropped_db >> 15) & 0x1ffff;
3588                 u16 pidx_inc = dropped_db & 0x1fff;
3589                 unsigned int s_qpp;
3590                 unsigned short udb_density;
3591                 unsigned long qpshift;
3592                 int page;
3593                 u32 udb;
3594
3595                 dev_warn(adap->pdev_dev,
3596                          "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
3597                          dropped_db, qid,
3598                          (dropped_db >> 14) & 1,
3599                          (dropped_db >> 13) & 1,
3600                          pidx_inc);
3601
3602                 drain_db_fifo(adap, 1);
3603
3604                 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
3605                 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
3606                                 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
3607                 qpshift = PAGE_SHIFT - ilog2(udb_density);
3608                 udb = qid << qpshift;
3609                 udb &= PAGE_MASK;
3610                 page = udb / PAGE_SIZE;
3611                 udb += (qid - (page * udb_density)) * 128;
3612
3613                 writel(PIDX(pidx_inc),  adap->bar2 + udb + 8);
3614
3615                 /* Re-enable BAR2 WC */
3616                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
3617         }
3618
3619         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
3620 }
3621
3622 void t4_db_full(struct adapter *adap)
3623 {
3624         if (is_t4(adap->chip)) {
3625                 t4_set_reg_field(adap, SGE_INT_ENABLE3,
3626                                  DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
3627                 queue_work(workq, &adap->db_full_task);
3628         }
3629 }
3630
3631 void t4_db_dropped(struct adapter *adap)
3632 {
3633         if (is_t4(adap->chip))
3634                 queue_work(workq, &adap->db_drop_task);
3635 }
3636
3637 static void uld_attach(struct adapter *adap, unsigned int uld)
3638 {
3639         void *handle;
3640         struct cxgb4_lld_info lli;
3641         unsigned short i;
3642
3643         lli.pdev = adap->pdev;
3644         lli.l2t = adap->l2t;
3645         lli.tids = &adap->tids;
3646         lli.ports = adap->port;
3647         lli.vr = &adap->vres;
3648         lli.mtus = adap->params.mtus;
3649         if (uld == CXGB4_ULD_RDMA) {
3650                 lli.rxq_ids = adap->sge.rdma_rxq;
3651                 lli.nrxq = adap->sge.rdmaqs;
3652         } else if (uld == CXGB4_ULD_ISCSI) {
3653                 lli.rxq_ids = adap->sge.ofld_rxq;
3654                 lli.nrxq = adap->sge.ofldqsets;
3655         }
3656         lli.ntxq = adap->sge.ofldqsets;
3657         lli.nchan = adap->params.nports;
3658         lli.nports = adap->params.nports;
3659         lli.wr_cred = adap->params.ofldq_wr_cred;
3660         lli.adapter_type = adap->params.rev;
3661         lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
3662         lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
3663                         t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
3664                         (adap->fn * 4));
3665         lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
3666                         t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
3667                         (adap->fn * 4));
3668         lli.filt_mode = adap->filter_mode;
3669         /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
3670         for (i = 0; i < NCHAN; i++)
3671                 lli.tx_modq[i] = i;
3672         lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
3673         lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
3674         lli.fw_vers = adap->params.fw_vers;
3675         lli.dbfifo_int_thresh = dbfifo_int_thresh;
3676         lli.sge_pktshift = adap->sge.pktshift;
3677         lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
3678
3679         handle = ulds[uld].add(&lli);
3680         if (IS_ERR(handle)) {
3681                 dev_warn(adap->pdev_dev,
3682                          "could not attach to the %s driver, error %ld\n",
3683                          uld_str[uld], PTR_ERR(handle));
3684                 return;
3685         }
3686
3687         adap->uld_handle[uld] = handle;
3688
3689         if (!netevent_registered) {
3690                 register_netevent_notifier(&cxgb4_netevent_nb);
3691                 netevent_registered = true;
3692         }
3693
3694         if (adap->flags & FULL_INIT_DONE)
3695                 ulds[uld].state_change(handle, CXGB4_STATE_UP);
3696 }
3697
3698 static void attach_ulds(struct adapter *adap)
3699 {
3700         unsigned int i;
3701
3702         mutex_lock(&uld_mutex);
3703         list_add_tail(&adap->list_node, &adapter_list);
3704         for (i = 0; i < CXGB4_ULD_MAX; i++)
3705                 if (ulds[i].add)
3706                         uld_attach(adap, i);
3707         mutex_unlock(&uld_mutex);
3708 }
3709
3710 static void detach_ulds(struct adapter *adap)
3711 {
3712         unsigned int i;
3713
3714         mutex_lock(&uld_mutex);
3715         list_del(&adap->list_node);
3716         for (i = 0; i < CXGB4_ULD_MAX; i++)
3717                 if (adap->uld_handle[i]) {
3718                         ulds[i].state_change(adap->uld_handle[i],
3719                                              CXGB4_STATE_DETACH);
3720                         adap->uld_handle[i] = NULL;
3721                 }
3722         if (netevent_registered && list_empty(&adapter_list)) {
3723                 unregister_netevent_notifier(&cxgb4_netevent_nb);
3724                 netevent_registered = false;
3725         }
3726         mutex_unlock(&uld_mutex);
3727 }
3728
3729 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
3730 {
3731         unsigned int i;
3732
3733         mutex_lock(&uld_mutex);
3734         for (i = 0; i < CXGB4_ULD_MAX; i++)
3735                 if (adap->uld_handle[i])
3736                         ulds[i].state_change(adap->uld_handle[i], new_state);
3737         mutex_unlock(&uld_mutex);
3738 }
3739
3740 /**
3741  *      cxgb4_register_uld - register an upper-layer driver
3742  *      @type: the ULD type
3743  *      @p: the ULD methods
3744  *
3745  *      Registers an upper-layer driver with this driver and notifies the ULD
3746  *      about any presently available devices that support its type.  Returns
3747  *      %-EBUSY if a ULD of the same type is already registered.
3748  */
3749 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
3750 {
3751         int ret = 0;
3752         struct adapter *adap;
3753
3754         if (type >= CXGB4_ULD_MAX)
3755                 return -EINVAL;
3756         mutex_lock(&uld_mutex);
3757         if (ulds[type].add) {
3758                 ret = -EBUSY;
3759                 goto out;
3760         }
3761         ulds[type] = *p;
3762         list_for_each_entry(adap, &adapter_list, list_node)
3763                 uld_attach(adap, type);
3764 out:    mutex_unlock(&uld_mutex);
3765         return ret;
3766 }
3767 EXPORT_SYMBOL(cxgb4_register_uld);
3768
3769 /**
3770  *      cxgb4_unregister_uld - unregister an upper-layer driver
3771  *      @type: the ULD type
3772  *
3773  *      Unregisters an existing upper-layer driver.
3774  */
3775 int cxgb4_unregister_uld(enum cxgb4_uld type)
3776 {
3777         struct adapter *adap;
3778
3779         if (type >= CXGB4_ULD_MAX)
3780                 return -EINVAL;
3781         mutex_lock(&uld_mutex);
3782         list_for_each_entry(adap, &adapter_list, list_node)
3783                 adap->uld_handle[type] = NULL;
3784         ulds[type].add = NULL;
3785         mutex_unlock(&uld_mutex);
3786         return 0;
3787 }
3788 EXPORT_SYMBOL(cxgb4_unregister_uld);
3789
3790 /**
3791  *      cxgb_up - enable the adapter
3792  *      @adap: adapter being enabled
3793  *
3794  *      Called when the first port is enabled, this function performs the
3795  *      actions necessary to make an adapter operational, such as completing
3796  *      the initialization of HW modules, and enabling interrupts.
3797  *
3798  *      Must be called with the rtnl lock held.
3799  */
3800 static int cxgb_up(struct adapter *adap)
3801 {
3802         int err;
3803
3804         err = setup_sge_queues(adap);
3805         if (err)
3806                 goto out;
3807         err = setup_rss(adap);
3808         if (err)
3809                 goto freeq;
3810
3811         if (adap->flags & USING_MSIX) {
3812                 name_msix_vecs(adap);
3813                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
3814                                   adap->msix_info[0].desc, adap);
3815                 if (err)
3816                         goto irq_err;
3817
3818                 err = request_msix_queue_irqs(adap);
3819                 if (err) {
3820                         free_irq(adap->msix_info[0].vec, adap);
3821                         goto irq_err;
3822                 }
3823         } else {
3824                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
3825                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
3826                                   adap->port[0]->name, adap);
3827                 if (err)
3828                         goto irq_err;
3829         }
3830         enable_rx(adap);
3831         t4_sge_start(adap);
3832         t4_intr_enable(adap);
3833         adap->flags |= FULL_INIT_DONE;
3834         notify_ulds(adap, CXGB4_STATE_UP);
3835  out:
3836         return err;
3837  irq_err:
3838         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
3839  freeq:
3840         t4_free_sge_resources(adap);
3841         goto out;
3842 }
3843
3844 static void cxgb_down(struct adapter *adapter)
3845 {
3846         t4_intr_disable(adapter);
3847         cancel_work_sync(&adapter->tid_release_task);
3848         cancel_work_sync(&adapter->db_full_task);
3849         cancel_work_sync(&adapter->db_drop_task);
3850         adapter->tid_release_task_busy = false;
3851         adapter->tid_release_head = NULL;
3852
3853         if (adapter->flags & USING_MSIX) {
3854                 free_msix_queue_irqs(adapter);
3855                 free_irq(adapter->msix_info[0].vec, adapter);
3856         } else
3857                 free_irq(adapter->pdev->irq, adapter);
3858         quiesce_rx(adapter);
3859         t4_sge_stop(adapter);
3860         t4_free_sge_resources(adapter);
3861         adapter->flags &= ~FULL_INIT_DONE;
3862 }
3863
3864 /*
3865  * net_device operations
3866  */
3867 static int cxgb_open(struct net_device *dev)
3868 {
3869         int err;
3870         struct port_info *pi = netdev_priv(dev);
3871         struct adapter *adapter = pi->adapter;
3872
3873         netif_carrier_off(dev);
3874
3875         if (!(adapter->flags & FULL_INIT_DONE)) {
3876                 err = cxgb_up(adapter);
3877                 if (err < 0)
3878                         return err;
3879         }
3880
3881         err = link_start(dev);
3882         if (!err)
3883                 netif_tx_start_all_queues(dev);
3884         return err;
3885 }
3886
3887 static int cxgb_close(struct net_device *dev)
3888 {
3889         struct port_info *pi = netdev_priv(dev);
3890         struct adapter *adapter = pi->adapter;
3891
3892         netif_tx_stop_all_queues(dev);
3893         netif_carrier_off(dev);
3894         return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
3895 }
3896
3897 /* Return an error number if the indicated filter isn't writable ...
3898  */
3899 static int writable_filter(struct filter_entry *f)
3900 {
3901         if (f->locked)
3902                 return -EPERM;
3903         if (f->pending)
3904                 return -EBUSY;
3905
3906         return 0;
3907 }
3908
3909 /* Delete the filter at the specified index (if valid).  The checks for all
3910  * the common problems with doing this like the filter being locked, currently
3911  * pending in another operation, etc.
3912  */
3913 static int delete_filter(struct adapter *adapter, unsigned int fidx)
3914 {
3915         struct filter_entry *f;
3916         int ret;
3917
3918         if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
3919                 return -EINVAL;
3920
3921         f = &adapter->tids.ftid_tab[fidx];
3922         ret = writable_filter(f);
3923         if (ret)
3924                 return ret;
3925         if (f->valid)
3926                 return del_filter_wr(adapter, fidx);
3927
3928         return 0;
3929 }
3930
3931 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
3932                 __be32 sip, __be16 sport, __be16 vlan,
3933                 unsigned int queue, unsigned char port, unsigned char mask)
3934 {
3935         int ret;
3936         struct filter_entry *f;
3937         struct adapter *adap;
3938         int i;
3939         u8 *val;
3940
3941         adap = netdev2adap(dev);
3942
3943         /* Adjust stid to correct filter index */
3944         stid -= adap->tids.nstids;
3945         stid += adap->tids.nftids;
3946
3947         /* Check to make sure the filter requested is writable ...
3948          */
3949         f = &adap->tids.ftid_tab[stid];
3950         ret = writable_filter(f);
3951         if (ret)
3952                 return ret;
3953
3954         /* Clear out any old resources being used by the filter before
3955          * we start constructing the new filter.
3956          */
3957         if (f->valid)
3958                 clear_filter(adap, f);
3959
3960         /* Clear out filter specifications */
3961         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
3962         f->fs.val.lport = cpu_to_be16(sport);
3963         f->fs.mask.lport  = ~0;
3964         val = (u8 *)&sip;
3965         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
3966                 for (i = 0; i < 4; i++) {
3967                         f->fs.val.lip[i] = val[i];
3968                         f->fs.mask.lip[i] = ~0;
3969                 }
3970                 if (adap->filter_mode & F_PORT) {
3971                         f->fs.val.iport = port;
3972                         f->fs.mask.iport = mask;
3973                 }
3974         }
3975
3976         f->fs.dirsteer = 1;
3977         f->fs.iq = queue;
3978         /* Mark filter as locked */
3979         f->locked = 1;
3980         f->fs.rpttid = 1;
3981
3982         ret = set_filter_wr(adap, stid);
3983         if (ret) {
3984                 clear_filter(adap, f);
3985                 return ret;
3986         }
3987
3988         return 0;
3989 }
3990 EXPORT_SYMBOL(cxgb4_create_server_filter);
3991
3992 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
3993                 unsigned int queue, bool ipv6)
3994 {
3995         int ret;
3996         struct filter_entry *f;
3997         struct adapter *adap;
3998
3999         adap = netdev2adap(dev);
4000
4001         /* Adjust stid to correct filter index */
4002         stid -= adap->tids.nstids;
4003         stid += adap->tids.nftids;
4004
4005         f = &adap->tids.ftid_tab[stid];
4006         /* Unlock the filter */
4007         f->locked = 0;
4008
4009         ret = delete_filter(adap, stid);
4010         if (ret)
4011                 return ret;
4012
4013         return 0;
4014 }
4015 EXPORT_SYMBOL(cxgb4_remove_server_filter);
4016
4017 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4018                                                 struct rtnl_link_stats64 *ns)
4019 {
4020         struct port_stats stats;
4021         struct port_info *p = netdev_priv(dev);
4022         struct adapter *adapter = p->adapter;
4023
4024         spin_lock(&adapter->stats_lock);
4025         t4_get_port_stats(adapter, p->tx_chan, &stats);
4026         spin_unlock(&adapter->stats_lock);
4027
4028         ns->tx_bytes   = stats.tx_octets;
4029         ns->tx_packets = stats.tx_frames;
4030         ns->rx_bytes   = stats.rx_octets;
4031         ns->rx_packets = stats.rx_frames;
4032         ns->multicast  = stats.rx_mcast_frames;
4033
4034         /* detailed rx_errors */
4035         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4036                                stats.rx_runt;
4037         ns->rx_over_errors   = 0;
4038         ns->rx_crc_errors    = stats.rx_fcs_err;
4039         ns->rx_frame_errors  = stats.rx_symbol_err;
4040         ns->rx_fifo_errors   = stats.rx_ovflow0 + stats.rx_ovflow1 +
4041                                stats.rx_ovflow2 + stats.rx_ovflow3 +
4042                                stats.rx_trunc0 + stats.rx_trunc1 +
4043                                stats.rx_trunc2 + stats.rx_trunc3;
4044         ns->rx_missed_errors = 0;
4045
4046         /* detailed tx_errors */
4047         ns->tx_aborted_errors   = 0;
4048         ns->tx_carrier_errors   = 0;
4049         ns->tx_fifo_errors      = 0;
4050         ns->tx_heartbeat_errors = 0;
4051         ns->tx_window_errors    = 0;
4052
4053         ns->tx_errors = stats.tx_error_frames;
4054         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4055                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4056         return ns;
4057 }
4058
4059 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4060 {
4061         unsigned int mbox;
4062         int ret = 0, prtad, devad;
4063         struct port_info *pi = netdev_priv(dev);
4064         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4065
4066         switch (cmd) {
4067         case SIOCGMIIPHY:
4068                 if (pi->mdio_addr < 0)
4069                         return -EOPNOTSUPP;
4070                 data->phy_id = pi->mdio_addr;
4071                 break;
4072         case SIOCGMIIREG:
4073         case SIOCSMIIREG:
4074                 if (mdio_phy_id_is_c45(data->phy_id)) {
4075                         prtad = mdio_phy_id_prtad(data->phy_id);
4076                         devad = mdio_phy_id_devad(data->phy_id);
4077                 } else if (data->phy_id < 32) {
4078                         prtad = data->phy_id;
4079                         devad = 0;
4080                         data->reg_num &= 0x1f;
4081                 } else
4082                         return -EINVAL;
4083
4084                 mbox = pi->adapter->fn;
4085                 if (cmd == SIOCGMIIREG)
4086                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
4087                                          data->reg_num, &data->val_out);
4088                 else
4089                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
4090                                          data->reg_num, data->val_in);
4091                 break;
4092         default:
4093                 return -EOPNOTSUPP;
4094         }
4095         return ret;
4096 }
4097
4098 static void cxgb_set_rxmode(struct net_device *dev)
4099 {
4100         /* unfortunately we can't return errors to the stack */
4101         set_rxmode(dev, -1, false);
4102 }
4103
4104 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4105 {
4106         int ret;
4107         struct port_info *pi = netdev_priv(dev);
4108
4109         if (new_mtu < 81 || new_mtu > MAX_MTU)         /* accommodate SACK */
4110                 return -EINVAL;
4111         ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4112                             -1, -1, -1, true);
4113         if (!ret)
4114                 dev->mtu = new_mtu;
4115         return ret;
4116 }
4117
4118 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4119 {
4120         int ret;
4121         struct sockaddr *addr = p;
4122         struct port_info *pi = netdev_priv(dev);
4123
4124         if (!is_valid_ether_addr(addr->sa_data))
4125                 return -EADDRNOTAVAIL;
4126
4127         ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4128                             pi->xact_addr_filt, addr->sa_data, true, true);
4129         if (ret < 0)
4130                 return ret;
4131
4132         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4133         pi->xact_addr_filt = ret;
4134         return 0;
4135 }
4136
4137 #ifdef CONFIG_NET_POLL_CONTROLLER
4138 static void cxgb_netpoll(struct net_device *dev)
4139 {
4140         struct port_info *pi = netdev_priv(dev);
4141         struct adapter *adap = pi->adapter;
4142
4143         if (adap->flags & USING_MSIX) {
4144                 int i;
4145                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4146
4147                 for (i = pi->nqsets; i; i--, rx++)
4148                         t4_sge_intr_msix(0, &rx->rspq);
4149         } else
4150                 t4_intr_handler(adap)(0, adap);
4151 }
4152 #endif
4153
4154 static const struct net_device_ops cxgb4_netdev_ops = {
4155         .ndo_open             = cxgb_open,
4156         .ndo_stop             = cxgb_close,
4157         .ndo_start_xmit       = t4_eth_xmit,
4158         .ndo_get_stats64      = cxgb_get_stats,
4159         .ndo_set_rx_mode      = cxgb_set_rxmode,
4160         .ndo_set_mac_address  = cxgb_set_mac_addr,
4161         .ndo_set_features     = cxgb_set_features,
4162         .ndo_validate_addr    = eth_validate_addr,
4163         .ndo_do_ioctl         = cxgb_ioctl,
4164         .ndo_change_mtu       = cxgb_change_mtu,
4165 #ifdef CONFIG_NET_POLL_CONTROLLER
4166         .ndo_poll_controller  = cxgb_netpoll,
4167 #endif
4168 };
4169
4170 void t4_fatal_err(struct adapter *adap)
4171 {
4172         t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4173         t4_intr_disable(adap);
4174         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4175 }
4176
4177 static void setup_memwin(struct adapter *adap)
4178 {
4179         u32 bar0, mem_win0_base, mem_win1_base, mem_win2_base;
4180
4181         bar0 = pci_resource_start(adap->pdev, 0);  /* truncation intentional */
4182         if (is_t4(adap->chip)) {
4183                 mem_win0_base = bar0 + MEMWIN0_BASE;
4184                 mem_win1_base = bar0 + MEMWIN1_BASE;
4185                 mem_win2_base = bar0 + MEMWIN2_BASE;
4186         } else {
4187                 /* For T5, only relative offset inside the PCIe BAR is passed */
4188                 mem_win0_base = MEMWIN0_BASE;
4189                 mem_win1_base = MEMWIN1_BASE_T5;
4190                 mem_win2_base = MEMWIN2_BASE_T5;
4191         }
4192         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
4193                      mem_win0_base | BIR(0) |
4194                      WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4195         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
4196                      mem_win1_base | BIR(0) |
4197                      WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4198         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
4199                      mem_win2_base | BIR(0) |
4200                      WINDOW(ilog2(MEMWIN2_APERTURE) - 10));
4201 }
4202
4203 static void setup_memwin_rdma(struct adapter *adap)
4204 {
4205         if (adap->vres.ocq.size) {
4206                 unsigned int start, sz_kb;
4207
4208                 start = pci_resource_start(adap->pdev, 2) +
4209                         OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
4210                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4211                 t4_write_reg(adap,
4212                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4213                              start | BIR(1) | WINDOW(ilog2(sz_kb)));
4214                 t4_write_reg(adap,
4215                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4216                              adap->vres.ocq.start);
4217                 t4_read_reg(adap,
4218                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4219         }
4220 }
4221
4222 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4223 {
4224         u32 v;
4225         int ret;
4226
4227         /* get device capabilities */
4228         memset(c, 0, sizeof(*c));
4229         c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4230                                FW_CMD_REQUEST | FW_CMD_READ);
4231         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
4232         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
4233         if (ret < 0)
4234                 return ret;
4235
4236         /* select capabilities we'll be using */
4237         if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4238                 if (!vf_acls)
4239                         c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4240                 else
4241                         c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4242         } else if (vf_acls) {
4243                 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
4244                 return ret;
4245         }
4246         c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4247                                FW_CMD_REQUEST | FW_CMD_WRITE);
4248         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
4249         if (ret < 0)
4250                 return ret;
4251
4252         ret = t4_config_glbl_rss(adap, adap->fn,
4253                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4254                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
4255                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
4256         if (ret < 0)
4257                 return ret;
4258
4259         ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
4260                           0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
4261         if (ret < 0)
4262                 return ret;
4263
4264         t4_sge_init(adap);
4265
4266         /* tweak some settings */
4267         t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
4268         t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
4269         t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
4270         v = t4_read_reg(adap, TP_PIO_DATA);
4271         t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
4272
4273         /* first 4 Tx modulation queues point to consecutive Tx channels */
4274         adap->params.tp.tx_modq_map = 0xE4;
4275         t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
4276                      V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
4277
4278         /* associate each Tx modulation queue with consecutive Tx channels */
4279         v = 0x84218421;
4280         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4281                           &v, 1, A_TP_TX_SCHED_HDR);
4282         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4283                           &v, 1, A_TP_TX_SCHED_FIFO);
4284         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4285                           &v, 1, A_TP_TX_SCHED_PCMD);
4286
4287 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
4288         if (is_offload(adap)) {
4289                 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
4290                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4291                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4292                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4293                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4294                 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
4295                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4296                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4297                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4298                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4299         }
4300
4301         /* get basic stuff going */
4302         return t4_early_init(adap, adap->fn);
4303 }
4304
4305 /*
4306  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
4307  */
4308 #define MAX_ATIDS 8192U
4309
4310 /*
4311  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4312  *
4313  * If the firmware we're dealing with has Configuration File support, then
4314  * we use that to perform all configuration
4315  */
4316
4317 /*
4318  * Tweak configuration based on module parameters, etc.  Most of these have
4319  * defaults assigned to them by Firmware Configuration Files (if we're using
4320  * them) but need to be explicitly set if we're using hard-coded
4321  * initialization.  But even in the case of using Firmware Configuration
4322  * Files, we'd like to expose the ability to change these via module
4323  * parameters so these are essentially common tweaks/settings for
4324  * Configuration Files and hard-coded initialization ...
4325  */
4326 static int adap_init0_tweaks(struct adapter *adapter)
4327 {
4328         /*
4329          * Fix up various Host-Dependent Parameters like Page Size, Cache
4330          * Line Size, etc.  The firmware default is for a 4KB Page Size and
4331          * 64B Cache Line Size ...
4332          */
4333         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
4334
4335         /*
4336          * Process module parameters which affect early initialization.
4337          */
4338         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
4339                 dev_err(&adapter->pdev->dev,
4340                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
4341                         rx_dma_offset);
4342                 rx_dma_offset = 2;
4343         }
4344         t4_set_reg_field(adapter, SGE_CONTROL,
4345                          PKTSHIFT_MASK,
4346                          PKTSHIFT(rx_dma_offset));
4347
4348         /*
4349          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
4350          * adds the pseudo header itself.
4351          */
4352         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
4353                                CSUM_HAS_PSEUDO_HDR, 0);
4354
4355         return 0;
4356 }
4357
4358 /*
4359  * Attempt to initialize the adapter via a Firmware Configuration File.
4360  */
4361 static int adap_init0_config(struct adapter *adapter, int reset)
4362 {
4363         struct fw_caps_config_cmd caps_cmd;
4364         const struct firmware *cf;
4365         unsigned long mtype = 0, maddr = 0;
4366         u32 finiver, finicsum, cfcsum;
4367         int ret, using_flash;
4368         char *fw_config_file, fw_config_file_path[256];
4369
4370         /*
4371          * Reset device if necessary.
4372          */
4373         if (reset) {
4374                 ret = t4_fw_reset(adapter, adapter->mbox,
4375                                   PIORSTMODE | PIORST);
4376                 if (ret < 0)
4377                         goto bye;
4378         }
4379
4380         /*
4381          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
4382          * then use that.  Otherwise, use the configuration file stored
4383          * in the adapter flash ...
4384          */
4385         switch (CHELSIO_CHIP_VERSION(adapter->chip)) {
4386         case CHELSIO_T4:
4387                 fw_config_file = FW_CFNAME;
4388                 break;
4389         case CHELSIO_T5:
4390                 fw_config_file = FW5_CFNAME;
4391                 break;
4392         default:
4393                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
4394                        adapter->pdev->device);
4395                 ret = -EINVAL;
4396                 goto bye;
4397         }
4398
4399         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
4400         if (ret < 0) {
4401                 using_flash = 1;
4402                 mtype = FW_MEMTYPE_CF_FLASH;
4403                 maddr = t4_flash_cfg_addr(adapter);
4404         } else {
4405                 u32 params[7], val[7];
4406
4407                 using_flash = 0;
4408                 if (cf->size >= FLASH_CFG_MAX_SIZE)
4409                         ret = -ENOMEM;
4410                 else {
4411                         params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4412                              FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
4413                         ret = t4_query_params(adapter, adapter->mbox,
4414                                               adapter->fn, 0, 1, params, val);
4415                         if (ret == 0) {
4416                                 /*
4417                                  * For t4_memory_write() below addresses and
4418                                  * sizes have to be in terms of multiples of 4
4419                                  * bytes.  So, if the Configuration File isn't
4420                                  * a multiple of 4 bytes in length we'll have
4421                                  * to write that out separately since we can't
4422                                  * guarantee that the bytes following the
4423                                  * residual byte in the buffer returned by
4424                                  * request_firmware() are zeroed out ...
4425                                  */
4426                                 size_t resid = cf->size & 0x3;
4427                                 size_t size = cf->size & ~0x3;
4428                                 __be32 *data = (__be32 *)cf->data;
4429
4430                                 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
4431                                 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
4432
4433                                 ret = t4_memory_write(adapter, mtype, maddr,
4434                                                       size, data);
4435                                 if (ret == 0 && resid != 0) {
4436                                         union {
4437                                                 __be32 word;
4438                                                 char buf[4];
4439                                         } last;
4440                                         int i;
4441
4442                                         last.word = data[size >> 2];
4443                                         for (i = resid; i < 4; i++)
4444                                                 last.buf[i] = 0;
4445                                         ret = t4_memory_write(adapter, mtype,
4446                                                               maddr + size,
4447                                                               4, &last.word);
4448                                 }
4449                         }
4450                 }
4451
4452                 release_firmware(cf);
4453                 if (ret)
4454                         goto bye;
4455         }
4456
4457         /*
4458          * Issue a Capability Configuration command to the firmware to get it
4459          * to parse the Configuration File.  We don't use t4_fw_config_file()
4460          * because we want the ability to modify various features after we've
4461          * processed the configuration file ...
4462          */
4463         memset(&caps_cmd, 0, sizeof(caps_cmd));
4464         caps_cmd.op_to_write =
4465                 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4466                       FW_CMD_REQUEST |
4467                       FW_CMD_READ);
4468         caps_cmd.cfvalid_to_len16 =
4469                 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
4470                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
4471                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
4472                       FW_LEN16(caps_cmd));
4473         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4474                          &caps_cmd);
4475         if (ret < 0)
4476                 goto bye;
4477
4478         finiver = ntohl(caps_cmd.finiver);
4479         finicsum = ntohl(caps_cmd.finicsum);
4480         cfcsum = ntohl(caps_cmd.cfcsum);
4481         if (finicsum != cfcsum)
4482                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4483                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4484                          finicsum, cfcsum);
4485
4486         /*
4487          * And now tell the firmware to use the configuration we just loaded.
4488          */
4489         caps_cmd.op_to_write =
4490                 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4491                       FW_CMD_REQUEST |
4492                       FW_CMD_WRITE);
4493         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4494         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4495                          NULL);
4496         if (ret < 0)
4497                 goto bye;
4498
4499         /*
4500          * Tweak configuration based on system architecture, module
4501          * parameters, etc.
4502          */
4503         ret = adap_init0_tweaks(adapter);
4504         if (ret < 0)
4505                 goto bye;
4506
4507         /*
4508          * And finally tell the firmware to initialize itself using the
4509          * parameters from the Configuration File.
4510          */
4511         ret = t4_fw_initialize(adapter, adapter->mbox);
4512         if (ret < 0)
4513                 goto bye;
4514
4515         sprintf(fw_config_file_path, "/lib/firmware/%s", fw_config_file);
4516         /*
4517          * Return successfully and note that we're operating with parameters
4518          * not supplied by the driver, rather than from hard-wired
4519          * initialization constants burried in the driver.
4520          */
4521         adapter->flags |= USING_SOFT_PARAMS;
4522         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
4523                  "Configuration File %s, version %#x, computed checksum %#x\n",
4524                  (using_flash
4525                   ? "in device FLASH"
4526                   : fw_config_file_path),
4527                  finiver, cfcsum);
4528         return 0;
4529
4530         /*
4531          * Something bad happened.  Return the error ...  (If the "error"
4532          * is that there's no Configuration File on the adapter we don't
4533          * want to issue a warning since this is fairly common.)
4534          */
4535 bye:
4536         if (ret != -ENOENT)
4537                 dev_warn(adapter->pdev_dev, "Configuration file error %d\n",
4538                          -ret);
4539         return ret;
4540 }
4541
4542 /*
4543  * Attempt to initialize the adapter via hard-coded, driver supplied
4544  * parameters ...
4545  */
4546 static int adap_init0_no_config(struct adapter *adapter, int reset)
4547 {
4548         struct sge *s = &adapter->sge;
4549         struct fw_caps_config_cmd caps_cmd;
4550         u32 v;
4551         int i, ret;
4552
4553         /*
4554          * Reset device if necessary
4555          */
4556         if (reset) {
4557                 ret = t4_fw_reset(adapter, adapter->mbox,
4558                                   PIORSTMODE | PIORST);
4559                 if (ret < 0)
4560                         goto bye;
4561         }
4562
4563         /*
4564          * Get device capabilities and select which we'll be using.
4565          */
4566         memset(&caps_cmd, 0, sizeof(caps_cmd));
4567         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4568                                      FW_CMD_REQUEST | FW_CMD_READ);
4569         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4570         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4571                          &caps_cmd);
4572         if (ret < 0)
4573                 goto bye;
4574
4575         if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4576                 if (!vf_acls)
4577                         caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4578                 else
4579                         caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4580         } else if (vf_acls) {
4581                 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
4582                 goto bye;
4583         }
4584         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4585                               FW_CMD_REQUEST | FW_CMD_WRITE);
4586         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4587                          NULL);
4588         if (ret < 0)
4589                 goto bye;
4590
4591         /*
4592          * Tweak configuration based on system architecture, module
4593          * parameters, etc.
4594          */
4595         ret = adap_init0_tweaks(adapter);
4596         if (ret < 0)
4597                 goto bye;
4598
4599         /*
4600          * Select RSS Global Mode we want to use.  We use "Basic Virtual"
4601          * mode which maps each Virtual Interface to its own section of
4602          * the RSS Table and we turn on all map and hash enables ...
4603          */
4604         adapter->flags |= RSS_TNLALLLOOKUP;
4605         ret = t4_config_glbl_rss(adapter, adapter->mbox,
4606                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4607                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
4608                                  FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
4609                                  ((adapter->flags & RSS_TNLALLLOOKUP) ?
4610                                         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
4611         if (ret < 0)
4612                 goto bye;
4613
4614         /*
4615          * Set up our own fundamental resource provisioning ...
4616          */
4617         ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
4618                           PFRES_NEQ, PFRES_NETHCTRL,
4619                           PFRES_NIQFLINT, PFRES_NIQ,
4620                           PFRES_TC, PFRES_NVI,
4621                           FW_PFVF_CMD_CMASK_MASK,
4622                           pfvfres_pmask(adapter, adapter->fn, 0),
4623                           PFRES_NEXACTF,
4624                           PFRES_R_CAPS, PFRES_WX_CAPS);
4625         if (ret < 0)
4626                 goto bye;
4627
4628         /*
4629          * Perform low level SGE initialization.  We need to do this before we
4630          * send the firmware the INITIALIZE command because that will cause
4631          * any other PF Drivers which are waiting for the Master
4632          * Initialization to proceed forward.
4633          */
4634         for (i = 0; i < SGE_NTIMERS - 1; i++)
4635                 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
4636         s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
4637         s->counter_val[0] = 1;
4638         for (i = 1; i < SGE_NCOUNTERS; i++)
4639                 s->counter_val[i] = min(intr_cnt[i - 1],
4640                                         THRESHOLD_0_GET(THRESHOLD_0_MASK));
4641         t4_sge_init(adapter);
4642
4643 #ifdef CONFIG_PCI_IOV
4644         /*
4645          * Provision resource limits for Virtual Functions.  We currently
4646          * grant them all the same static resource limits except for the Port
4647          * Access Rights Mask which we're assigning based on the PF.  All of
4648          * the static provisioning stuff for both the PF and VF really needs
4649          * to be managed in a persistent manner for each device which the
4650          * firmware controls.
4651          */
4652         {
4653                 int pf, vf;
4654
4655                 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
4656                         if (num_vf[pf] <= 0)
4657                                 continue;
4658
4659                         /* VF numbering starts at 1! */
4660                         for (vf = 1; vf <= num_vf[pf]; vf++) {
4661                                 ret = t4_cfg_pfvf(adapter, adapter->mbox,
4662                                                   pf, vf,
4663                                                   VFRES_NEQ, VFRES_NETHCTRL,
4664                                                   VFRES_NIQFLINT, VFRES_NIQ,
4665                                                   VFRES_TC, VFRES_NVI,
4666                                                   FW_PFVF_CMD_CMASK_MASK,
4667                                                   pfvfres_pmask(
4668                                                   adapter, pf, vf),
4669                                                   VFRES_NEXACTF,
4670                                                   VFRES_R_CAPS, VFRES_WX_CAPS);
4671                                 if (ret < 0)
4672                                         dev_warn(adapter->pdev_dev,
4673                                                  "failed to "\
4674                                                  "provision pf/vf=%d/%d; "
4675                                                  "err=%d\n", pf, vf, ret);
4676                         }
4677                 }
4678         }
4679 #endif
4680
4681         /*
4682          * Set up the default filter mode.  Later we'll want to implement this
4683          * via a firmware command, etc. ...  This needs to be done before the
4684          * firmare initialization command ...  If the selected set of fields
4685          * isn't equal to the default value, we'll need to make sure that the
4686          * field selections will fit in the 36-bit budget.
4687          */
4688         if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
4689                 int j, bits = 0;
4690
4691                 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
4692                         switch (tp_vlan_pri_map & (1 << j)) {
4693                         case 0:
4694                                 /* compressed filter field not enabled */
4695                                 break;
4696                         case FCOE_MASK:
4697                                 bits +=  1;
4698                                 break;
4699                         case PORT_MASK:
4700                                 bits +=  3;
4701                                 break;
4702                         case VNIC_ID_MASK:
4703                                 bits += 17;
4704                                 break;
4705                         case VLAN_MASK:
4706                                 bits += 17;
4707                                 break;
4708                         case TOS_MASK:
4709                                 bits +=  8;
4710                                 break;
4711                         case PROTOCOL_MASK:
4712                                 bits +=  8;
4713                                 break;
4714                         case ETHERTYPE_MASK:
4715                                 bits += 16;
4716                                 break;
4717                         case MACMATCH_MASK:
4718                                 bits +=  9;
4719                                 break;
4720                         case MPSHITTYPE_MASK:
4721                                 bits +=  3;
4722                                 break;
4723                         case FRAGMENTATION_MASK:
4724                                 bits +=  1;
4725                                 break;
4726                         }
4727
4728                 if (bits > 36) {
4729                         dev_err(adapter->pdev_dev,
4730                                 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
4731                                 " using %#x\n", tp_vlan_pri_map, bits,
4732                                 TP_VLAN_PRI_MAP_DEFAULT);
4733                         tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
4734                 }
4735         }
4736         v = tp_vlan_pri_map;
4737         t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
4738                           &v, 1, TP_VLAN_PRI_MAP);
4739
4740         /*
4741          * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
4742          * to support any of the compressed filter fields above.  Newer
4743          * versions of the firmware do this automatically but it doesn't hurt
4744          * to set it here.  Meanwhile, we do _not_ need to set Lookup Every
4745          * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
4746          * since the firmware automatically turns this on and off when we have
4747          * a non-zero number of filters active (since it does have a
4748          * performance impact).
4749          */
4750         if (tp_vlan_pri_map)
4751                 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
4752                                  FIVETUPLELOOKUP_MASK,
4753                                  FIVETUPLELOOKUP_MASK);
4754
4755         /*
4756          * Tweak some settings.
4757          */
4758         t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
4759                      RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
4760                      PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
4761                      KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
4762
4763         /*
4764          * Get basic stuff going by issuing the Firmware Initialize command.
4765          * Note that this _must_ be after all PFVF commands ...
4766          */
4767         ret = t4_fw_initialize(adapter, adapter->mbox);
4768         if (ret < 0)
4769                 goto bye;
4770
4771         /*
4772          * Return successfully!
4773          */
4774         dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
4775                  "driver parameters\n");
4776         return 0;
4777
4778         /*
4779          * Something bad happened.  Return the error ...
4780          */
4781 bye:
4782         return ret;
4783 }
4784
4785 /*
4786  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4787  */
4788 static int adap_init0(struct adapter *adap)
4789 {
4790         int ret;
4791         u32 v, port_vec;
4792         enum dev_state state;
4793         u32 params[7], val[7];
4794         struct fw_caps_config_cmd caps_cmd;
4795         int reset = 1, j;
4796
4797         /*
4798          * Contact FW, advertising Master capability (and potentially forcing
4799          * ourselves as the Master PF if our module parameter force_init is
4800          * set).
4801          */
4802         ret = t4_fw_hello(adap, adap->mbox, adap->fn,
4803                           force_init ? MASTER_MUST : MASTER_MAY,
4804                           &state);
4805         if (ret < 0) {
4806                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4807                         ret);
4808                 return ret;
4809         }
4810         if (ret == adap->mbox)
4811                 adap->flags |= MASTER_PF;
4812         if (force_init && state == DEV_STATE_INIT)
4813                 state = DEV_STATE_UNINIT;
4814
4815         /*
4816          * If we're the Master PF Driver and the device is uninitialized,
4817          * then let's consider upgrading the firmware ...  (We always want
4818          * to check the firmware version number in order to A. get it for
4819          * later reporting and B. to warn if the currently loaded firmware
4820          * is excessively mismatched relative to the driver.)
4821          */
4822         ret = t4_check_fw_version(adap);
4823         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
4824                 if (ret == -EINVAL || ret > 0) {
4825                         if (upgrade_fw(adap) >= 0) {
4826                                 /*
4827                                  * Note that the chip was reset as part of the
4828                                  * firmware upgrade so we don't reset it again
4829                                  * below and grab the new firmware version.
4830                                  */
4831                                 reset = 0;
4832                                 ret = t4_check_fw_version(adap);
4833                         }
4834                 }
4835                 if (ret < 0)
4836                         return ret;
4837         }
4838
4839         /*
4840          * Grab VPD parameters.  This should be done after we establish a
4841          * connection to the firmware since some of the VPD parameters
4842          * (notably the Core Clock frequency) are retrieved via requests to
4843          * the firmware.  On the other hand, we need these fairly early on
4844          * so we do this right after getting ahold of the firmware.
4845          */
4846         ret = get_vpd_params(adap, &adap->params.vpd);
4847         if (ret < 0)
4848                 goto bye;
4849
4850         /*
4851          * Find out what ports are available to us.  Note that we need to do
4852          * this before calling adap_init0_no_config() since it needs nports
4853          * and portvec ...
4854          */
4855         v =
4856             FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4857             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
4858         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
4859         if (ret < 0)
4860                 goto bye;
4861
4862         adap->params.nports = hweight32(port_vec);
4863         adap->params.portvec = port_vec;
4864
4865         /*
4866          * If the firmware is initialized already (and we're not forcing a
4867          * master initialization), note that we're living with existing
4868          * adapter parameters.  Otherwise, it's time to try initializing the
4869          * adapter ...
4870          */
4871         if (state == DEV_STATE_INIT) {
4872                 dev_info(adap->pdev_dev, "Coming up as %s: "\
4873                          "Adapter already initialized\n",
4874                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
4875                 adap->flags |= USING_SOFT_PARAMS;
4876         } else {
4877                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4878                          "Initializing adapter\n");
4879
4880                 /*
4881                  * If the firmware doesn't support Configuration
4882                  * Files warn user and exit,
4883                  */
4884                 if (ret < 0)
4885                         dev_warn(adap->pdev_dev, "Firmware doesn't support "
4886                                  "configuration file.\n");
4887                 if (force_old_init)
4888                         ret = adap_init0_no_config(adap, reset);
4889                 else {
4890                         /*
4891                          * Find out whether we're dealing with a version of
4892                          * the firmware which has configuration file support.
4893                          */
4894                         params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4895                                      FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
4896                         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
4897                                               params, val);
4898
4899                         /*
4900                          * If the firmware doesn't support Configuration
4901                          * Files, use the old Driver-based, hard-wired
4902                          * initialization.  Otherwise, try using the
4903                          * Configuration File support and fall back to the
4904                          * Driver-based initialization if there's no
4905                          * Configuration File found.
4906                          */
4907                         if (ret < 0)
4908                                 ret = adap_init0_no_config(adap, reset);
4909                         else {
4910                                 /*
4911                                  * The firmware provides us with a memory
4912                                  * buffer where we can load a Configuration
4913                                  * File from the host if we want to override
4914                                  * the Configuration File in flash.
4915                                  */
4916
4917                                 ret = adap_init0_config(adap, reset);
4918                                 if (ret == -ENOENT) {
4919                                         dev_info(adap->pdev_dev,
4920                                             "No Configuration File present "
4921                                             "on adapter.  Using hard-wired "
4922                                             "configuration parameters.\n");
4923                                         ret = adap_init0_no_config(adap, reset);
4924                                 }
4925                         }
4926                 }
4927                 if (ret < 0) {
4928                         dev_err(adap->pdev_dev,
4929                                 "could not initialize adapter, error %d\n",
4930                                 -ret);
4931                         goto bye;
4932                 }
4933         }
4934
4935         /*
4936          * If we're living with non-hard-coded parameters (either from a
4937          * Firmware Configuration File or values programmed by a different PF
4938          * Driver), give the SGE code a chance to pull in anything that it
4939          * needs ...  Note that this must be called after we retrieve our VPD
4940          * parameters in order to know how to convert core ticks to seconds.
4941          */
4942         if (adap->flags & USING_SOFT_PARAMS) {
4943                 ret = t4_sge_init(adap);
4944                 if (ret < 0)
4945                         goto bye;
4946         }
4947
4948         if (is_bypass_device(adap->pdev->device))
4949                 adap->params.bypass = 1;
4950
4951         /*
4952          * Grab some of our basic fundamental operating parameters.
4953          */
4954 #define FW_PARAM_DEV(param) \
4955         (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
4956         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
4957
4958 #define FW_PARAM_PFVF(param) \
4959         FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
4960         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)|  \
4961         FW_PARAMS_PARAM_Y(0) | \
4962         FW_PARAMS_PARAM_Z(0)
4963
4964         params[0] = FW_PARAM_PFVF(EQ_START);
4965         params[1] = FW_PARAM_PFVF(L2T_START);
4966         params[2] = FW_PARAM_PFVF(L2T_END);
4967         params[3] = FW_PARAM_PFVF(FILTER_START);
4968         params[4] = FW_PARAM_PFVF(FILTER_END);
4969         params[5] = FW_PARAM_PFVF(IQFLINT_START);
4970         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
4971         if (ret < 0)
4972                 goto bye;
4973         adap->sge.egr_start = val[0];
4974         adap->l2t_start = val[1];
4975         adap->l2t_end = val[2];
4976         adap->tids.ftid_base = val[3];
4977         adap->tids.nftids = val[4] - val[3] + 1;
4978         adap->sge.ingr_start = val[5];
4979
4980         /* query params related to active filter region */
4981         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4982         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4983         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
4984         /* If Active filter size is set we enable establishing
4985          * offload connection through firmware work request
4986          */
4987         if ((val[0] != val[1]) && (ret >= 0)) {
4988                 adap->flags |= FW_OFLD_CONN;
4989                 adap->tids.aftid_base = val[0];
4990                 adap->tids.aftid_end = val[1];
4991         }
4992
4993         /*
4994          * Get device capabilities so we can determine what resources we need
4995          * to manage.
4996          */
4997         memset(&caps_cmd, 0, sizeof(caps_cmd));
4998         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4999                                      FW_CMD_REQUEST | FW_CMD_READ);
5000         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5001         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5002                          &caps_cmd);
5003         if (ret < 0)
5004                 goto bye;
5005
5006         if (caps_cmd.ofldcaps) {
5007                 /* query offload-related parameters */
5008                 params[0] = FW_PARAM_DEV(NTID);
5009                 params[1] = FW_PARAM_PFVF(SERVER_START);
5010                 params[2] = FW_PARAM_PFVF(SERVER_END);
5011                 params[3] = FW_PARAM_PFVF(TDDP_START);
5012                 params[4] = FW_PARAM_PFVF(TDDP_END);
5013                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5014                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5015                                       params, val);
5016                 if (ret < 0)
5017                         goto bye;
5018                 adap->tids.ntids = val[0];
5019                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5020                 adap->tids.stid_base = val[1];
5021                 adap->tids.nstids = val[2] - val[1] + 1;
5022                 /*
5023                  * Setup server filter region. Divide the availble filter
5024                  * region into two parts. Regular filters get 1/3rd and server
5025                  * filters get 2/3rd part. This is only enabled if workarond
5026                  * path is enabled.
5027                  * 1. For regular filters.
5028                  * 2. Server filter: This are special filters which are used
5029                  * to redirect SYN packets to offload queue.
5030                  */
5031                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5032                         adap->tids.sftid_base = adap->tids.ftid_base +
5033                                         DIV_ROUND_UP(adap->tids.nftids, 3);
5034                         adap->tids.nsftids = adap->tids.nftids -
5035                                          DIV_ROUND_UP(adap->tids.nftids, 3);
5036                         adap->tids.nftids = adap->tids.sftid_base -
5037                                                 adap->tids.ftid_base;
5038                 }
5039                 adap->vres.ddp.start = val[3];
5040                 adap->vres.ddp.size = val[4] - val[3] + 1;
5041                 adap->params.ofldq_wr_cred = val[5];
5042
5043                 adap->params.offload = 1;
5044         }
5045         if (caps_cmd.rdmacaps) {
5046                 params[0] = FW_PARAM_PFVF(STAG_START);
5047                 params[1] = FW_PARAM_PFVF(STAG_END);
5048                 params[2] = FW_PARAM_PFVF(RQ_START);
5049                 params[3] = FW_PARAM_PFVF(RQ_END);
5050                 params[4] = FW_PARAM_PFVF(PBL_START);
5051                 params[5] = FW_PARAM_PFVF(PBL_END);
5052                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5053                                       params, val);
5054                 if (ret < 0)
5055                         goto bye;
5056                 adap->vres.stag.start = val[0];
5057                 adap->vres.stag.size = val[1] - val[0] + 1;
5058                 adap->vres.rq.start = val[2];
5059                 adap->vres.rq.size = val[3] - val[2] + 1;
5060                 adap->vres.pbl.start = val[4];
5061                 adap->vres.pbl.size = val[5] - val[4] + 1;
5062
5063                 params[0] = FW_PARAM_PFVF(SQRQ_START);
5064                 params[1] = FW_PARAM_PFVF(SQRQ_END);
5065                 params[2] = FW_PARAM_PFVF(CQ_START);
5066                 params[3] = FW_PARAM_PFVF(CQ_END);
5067                 params[4] = FW_PARAM_PFVF(OCQ_START);
5068                 params[5] = FW_PARAM_PFVF(OCQ_END);
5069                 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
5070                 if (ret < 0)
5071                         goto bye;
5072                 adap->vres.qp.start = val[0];
5073                 adap->vres.qp.size = val[1] - val[0] + 1;
5074                 adap->vres.cq.start = val[2];
5075                 adap->vres.cq.size = val[3] - val[2] + 1;
5076                 adap->vres.ocq.start = val[4];
5077                 adap->vres.ocq.size = val[5] - val[4] + 1;
5078         }
5079         if (caps_cmd.iscsicaps) {
5080                 params[0] = FW_PARAM_PFVF(ISCSI_START);
5081                 params[1] = FW_PARAM_PFVF(ISCSI_END);
5082                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5083                                       params, val);
5084                 if (ret < 0)
5085                         goto bye;
5086                 adap->vres.iscsi.start = val[0];
5087                 adap->vres.iscsi.size = val[1] - val[0] + 1;
5088         }
5089 #undef FW_PARAM_PFVF
5090 #undef FW_PARAM_DEV
5091
5092         /*
5093          * These are finalized by FW initialization, load their values now.
5094          */
5095         v = t4_read_reg(adap, TP_TIMER_RESOLUTION);
5096         adap->params.tp.tre = TIMERRESOLUTION_GET(v);
5097         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_GET(v);
5098         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5099         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5100                      adap->params.b_wnd);
5101
5102         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
5103         for (j = 0; j < NCHAN; j++)
5104                 adap->params.tp.tx_modq[j] = j;
5105
5106         t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5107                          &adap->filter_mode, 1,
5108                          TP_VLAN_PRI_MAP);
5109
5110         adap->flags |= FW_OK;
5111         return 0;
5112
5113         /*
5114          * Something bad happened.  If a command timed out or failed with EIO
5115          * FW does not operate within its spec or something catastrophic
5116          * happened to HW/FW, stop issuing commands.
5117          */
5118 bye:
5119         if (ret != -ETIMEDOUT && ret != -EIO)
5120                 t4_fw_bye(adap, adap->mbox);
5121         return ret;
5122 }
5123
5124 /* EEH callbacks */
5125
5126 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5127                                          pci_channel_state_t state)
5128 {
5129         int i;
5130         struct adapter *adap = pci_get_drvdata(pdev);
5131
5132         if (!adap)
5133                 goto out;
5134
5135         rtnl_lock();
5136         adap->flags &= ~FW_OK;
5137         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
5138         for_each_port(adap, i) {
5139                 struct net_device *dev = adap->port[i];
5140
5141                 netif_device_detach(dev);
5142                 netif_carrier_off(dev);
5143         }
5144         if (adap->flags & FULL_INIT_DONE)
5145                 cxgb_down(adap);
5146         rtnl_unlock();
5147         pci_disable_device(pdev);
5148 out:    return state == pci_channel_io_perm_failure ?
5149                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5150 }
5151
5152 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5153 {
5154         int i, ret;
5155         struct fw_caps_config_cmd c;
5156         struct adapter *adap = pci_get_drvdata(pdev);
5157
5158         if (!adap) {
5159                 pci_restore_state(pdev);
5160                 pci_save_state(pdev);
5161                 return PCI_ERS_RESULT_RECOVERED;
5162         }
5163
5164         if (pci_enable_device(pdev)) {
5165                 dev_err(&pdev->dev, "cannot reenable PCI device after reset\n");
5166                 return PCI_ERS_RESULT_DISCONNECT;
5167         }
5168
5169         pci_set_master(pdev);
5170         pci_restore_state(pdev);
5171         pci_save_state(pdev);
5172         pci_cleanup_aer_uncorrect_error_status(pdev);
5173
5174         if (t4_wait_dev_ready(adap) < 0)
5175                 return PCI_ERS_RESULT_DISCONNECT;
5176         if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL))
5177                 return PCI_ERS_RESULT_DISCONNECT;
5178         adap->flags |= FW_OK;
5179         if (adap_init1(adap, &c))
5180                 return PCI_ERS_RESULT_DISCONNECT;
5181
5182         for_each_port(adap, i) {
5183                 struct port_info *p = adap2pinfo(adap, i);
5184
5185                 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
5186                                   NULL, NULL);
5187                 if (ret < 0)
5188                         return PCI_ERS_RESULT_DISCONNECT;
5189                 p->viid = ret;
5190                 p->xact_addr_filt = -1;
5191         }
5192
5193         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5194                      adap->params.b_wnd);
5195         setup_memwin(adap);
5196         if (cxgb_up(adap))
5197                 return PCI_ERS_RESULT_DISCONNECT;
5198         return PCI_ERS_RESULT_RECOVERED;
5199 }
5200
5201 static void eeh_resume(struct pci_dev *pdev)
5202 {
5203         int i;
5204         struct adapter *adap = pci_get_drvdata(pdev);
5205
5206         if (!adap)
5207                 return;
5208
5209         rtnl_lock();
5210         for_each_port(adap, i) {
5211                 struct net_device *dev = adap->port[i];
5212
5213                 if (netif_running(dev)) {
5214                         link_start(dev);
5215                         cxgb_set_rxmode(dev);
5216                 }
5217                 netif_device_attach(dev);
5218         }
5219         rtnl_unlock();
5220 }
5221
5222 static const struct pci_error_handlers cxgb4_eeh = {
5223         .error_detected = eeh_err_detected,
5224         .slot_reset     = eeh_slot_reset,
5225         .resume         = eeh_resume,
5226 };
5227
5228 static inline bool is_10g_port(const struct link_config *lc)
5229 {
5230         return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0;
5231 }
5232
5233 static inline void init_rspq(struct sge_rspq *q, u8 timer_idx, u8 pkt_cnt_idx,
5234                              unsigned int size, unsigned int iqe_size)
5235 {
5236         q->intr_params = QINTR_TIMER_IDX(timer_idx) |
5237                          (pkt_cnt_idx < SGE_NCOUNTERS ? QINTR_CNT_EN : 0);
5238         q->pktcnt_idx = pkt_cnt_idx < SGE_NCOUNTERS ? pkt_cnt_idx : 0;
5239         q->iqe_len = iqe_size;
5240         q->size = size;
5241 }
5242
5243 /*
5244  * Perform default configuration of DMA queues depending on the number and type
5245  * of ports we found and the number of available CPUs.  Most settings can be
5246  * modified by the admin prior to actual use.
5247  */
5248 static void cfg_queues(struct adapter *adap)
5249 {
5250         struct sge *s = &adap->sge;
5251         int i, q10g = 0, n10g = 0, qidx = 0;
5252
5253         for_each_port(adap, i)
5254                 n10g += is_10g_port(&adap2pinfo(adap, i)->link_cfg);
5255
5256         /*
5257          * We default to 1 queue per non-10G port and up to # of cores queues
5258          * per 10G port.
5259          */
5260         if (n10g)
5261                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5262         if (q10g > netif_get_num_default_rss_queues())
5263                 q10g = netif_get_num_default_rss_queues();
5264
5265         for_each_port(adap, i) {
5266                 struct port_info *pi = adap2pinfo(adap, i);
5267
5268                 pi->first_qset = qidx;
5269                 pi->nqsets = is_10g_port(&pi->link_cfg) ? q10g : 1;
5270                 qidx += pi->nqsets;
5271         }
5272
5273         s->ethqsets = qidx;
5274         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
5275
5276         if (is_offload(adap)) {
5277                 /*
5278                  * For offload we use 1 queue/channel if all ports are up to 1G,
5279                  * otherwise we divide all available queues amongst the channels
5280                  * capped by the number of available cores.
5281                  */
5282                 if (n10g) {
5283                         i = min_t(int, ARRAY_SIZE(s->ofldrxq),
5284                                   num_online_cpus());
5285                         s->ofldqsets = roundup(i, adap->params.nports);
5286                 } else
5287                         s->ofldqsets = adap->params.nports;
5288                 /* For RDMA one Rx queue per channel suffices */
5289                 s->rdmaqs = adap->params.nports;
5290         }
5291
5292         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5293                 struct sge_eth_rxq *r = &s->ethrxq[i];
5294
5295                 init_rspq(&r->rspq, 0, 0, 1024, 64);
5296                 r->fl.size = 72;
5297         }
5298
5299         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5300                 s->ethtxq[i].q.size = 1024;
5301
5302         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5303                 s->ctrlq[i].q.size = 512;
5304
5305         for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
5306                 s->ofldtxq[i].q.size = 1024;
5307
5308         for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
5309                 struct sge_ofld_rxq *r = &s->ofldrxq[i];
5310
5311                 init_rspq(&r->rspq, 0, 0, 1024, 64);
5312                 r->rspq.uld = CXGB4_ULD_ISCSI;
5313                 r->fl.size = 72;
5314         }
5315
5316         for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
5317                 struct sge_ofld_rxq *r = &s->rdmarxq[i];
5318
5319                 init_rspq(&r->rspq, 0, 0, 511, 64);
5320                 r->rspq.uld = CXGB4_ULD_RDMA;
5321                 r->fl.size = 72;
5322         }
5323
5324         init_rspq(&s->fw_evtq, 6, 0, 512, 64);
5325         init_rspq(&s->intrq, 6, 0, 2 * MAX_INGQ, 64);
5326 }
5327
5328 /*
5329  * Reduce the number of Ethernet queues across all ports to at most n.
5330  * n provides at least one queue per port.
5331  */
5332 static void reduce_ethqs(struct adapter *adap, int n)
5333 {
5334         int i;
5335         struct port_info *pi;
5336
5337         while (n < adap->sge.ethqsets)
5338                 for_each_port(adap, i) {
5339                         pi = adap2pinfo(adap, i);
5340                         if (pi->nqsets > 1) {
5341                                 pi->nqsets--;
5342                                 adap->sge.ethqsets--;
5343                                 if (adap->sge.ethqsets <= n)
5344                                         break;
5345                         }
5346                 }
5347
5348         n = 0;
5349         for_each_port(adap, i) {
5350                 pi = adap2pinfo(adap, i);
5351                 pi->first_qset = n;
5352                 n += pi->nqsets;
5353         }
5354 }
5355
5356 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5357 #define EXTRA_VECS 2
5358
5359 static int enable_msix(struct adapter *adap)
5360 {
5361         int ofld_need = 0;
5362         int i, err, want, need;
5363         struct sge *s = &adap->sge;
5364         unsigned int nchan = adap->params.nports;
5365         struct msix_entry entries[MAX_INGQ + 1];
5366
5367         for (i = 0; i < ARRAY_SIZE(entries); ++i)
5368                 entries[i].entry = i;
5369
5370         want = s->max_ethqsets + EXTRA_VECS;
5371         if (is_offload(adap)) {
5372                 want += s->rdmaqs + s->ofldqsets;
5373                 /* need nchan for each possible ULD */
5374                 ofld_need = 2 * nchan;
5375         }
5376         need = adap->params.nports + EXTRA_VECS + ofld_need;
5377
5378         while ((err = pci_enable_msix(adap->pdev, entries, want)) >= need)
5379                 want = err;
5380
5381         if (!err) {
5382                 /*
5383                  * Distribute available vectors to the various queue groups.
5384                  * Every group gets its minimum requirement and NIC gets top
5385                  * priority for leftovers.
5386                  */
5387                 i = want - EXTRA_VECS - ofld_need;
5388                 if (i < s->max_ethqsets) {
5389                         s->max_ethqsets = i;
5390                         if (i < s->ethqsets)
5391                                 reduce_ethqs(adap, i);
5392                 }
5393                 if (is_offload(adap)) {
5394                         i = want - EXTRA_VECS - s->max_ethqsets;
5395                         i -= ofld_need - nchan;
5396                         s->ofldqsets = (i / nchan) * nchan;  /* round down */
5397                 }
5398                 for (i = 0; i < want; ++i)
5399                         adap->msix_info[i].vec = entries[i].vector;
5400         } else if (err > 0)
5401                 dev_info(adap->pdev_dev,
5402                          "only %d MSI-X vectors left, not using MSI-X\n", err);
5403         return err;
5404 }
5405
5406 #undef EXTRA_VECS
5407
5408 static int init_rss(struct adapter *adap)
5409 {
5410         unsigned int i, j;
5411
5412         for_each_port(adap, i) {
5413                 struct port_info *pi = adap2pinfo(adap, i);
5414
5415                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5416                 if (!pi->rss)
5417                         return -ENOMEM;
5418                 for (j = 0; j < pi->rss_size; j++)
5419                         pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
5420         }
5421         return 0;
5422 }
5423
5424 static void print_port_info(const struct net_device *dev)
5425 {
5426         static const char *base[] = {
5427                 "R XFI", "R XAUI", "T SGMII", "T XFI", "T XAUI", "KX4", "CX4",
5428                 "KX", "KR", "R SFP+", "KR/KX", "KR/KX/KX4"
5429         };
5430
5431         char buf[80];
5432         char *bufp = buf;
5433         const char *spd = "";
5434         const struct port_info *pi = netdev_priv(dev);
5435         const struct adapter *adap = pi->adapter;
5436
5437         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
5438                 spd = " 2.5 GT/s";
5439         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
5440                 spd = " 5 GT/s";
5441
5442         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
5443                 bufp += sprintf(bufp, "100/");
5444         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
5445                 bufp += sprintf(bufp, "1000/");
5446         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
5447                 bufp += sprintf(bufp, "10G/");
5448         if (bufp != buf)
5449                 --bufp;
5450         sprintf(bufp, "BASE-%s", base[pi->port_type]);
5451
5452         netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
5453                     adap->params.vpd.id,
5454                     CHELSIO_CHIP_RELEASE(adap->params.rev), buf,
5455                     is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
5456                     (adap->flags & USING_MSIX) ? " MSI-X" :
5457                     (adap->flags & USING_MSI) ? " MSI" : "");
5458         netdev_info(dev, "S/N: %s, E/C: %s\n",
5459                     adap->params.vpd.sn, adap->params.vpd.ec);
5460 }
5461
5462 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
5463 {
5464         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
5465 }
5466
5467 /*
5468  * Free the following resources:
5469  * - memory used for tables
5470  * - MSI/MSI-X
5471  * - net devices
5472  * - resources FW is holding for us
5473  */
5474 static void free_some_resources(struct adapter *adapter)
5475 {
5476         unsigned int i;
5477
5478         t4_free_mem(adapter->l2t);
5479         t4_free_mem(adapter->tids.tid_tab);
5480         disable_msi(adapter);
5481
5482         for_each_port(adapter, i)
5483                 if (adapter->port[i]) {
5484                         kfree(adap2pinfo(adapter, i)->rss);
5485                         free_netdev(adapter->port[i]);
5486                 }
5487         if (adapter->flags & FW_OK)
5488                 t4_fw_bye(adapter, adapter->fn);
5489 }
5490
5491 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
5492 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
5493                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
5494 #define SEGMENT_SIZE 128
5495
5496 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5497 {
5498         int func, i, err, s_qpp, qpp, num_seg;
5499         struct port_info *pi;
5500         bool highdma = false;
5501         struct adapter *adapter = NULL;
5502
5503         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
5504
5505         err = pci_request_regions(pdev, KBUILD_MODNAME);
5506         if (err) {
5507                 /* Just info, some other driver may have claimed the device. */
5508                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
5509                 return err;
5510         }
5511
5512         /* We control everything through one PF */
5513         func = PCI_FUNC(pdev->devfn);
5514         if (func != ent->driver_data) {
5515                 pci_save_state(pdev);        /* to restore SR-IOV later */
5516                 goto sriov;
5517         }
5518
5519         err = pci_enable_device(pdev);
5520         if (err) {
5521                 dev_err(&pdev->dev, "cannot enable PCI device\n");
5522                 goto out_release_regions;
5523         }
5524
5525         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5526                 highdma = true;
5527                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5528                 if (err) {
5529                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
5530                                 "coherent allocations\n");
5531                         goto out_disable_device;
5532                 }
5533         } else {
5534                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5535                 if (err) {
5536                         dev_err(&pdev->dev, "no usable DMA configuration\n");
5537                         goto out_disable_device;
5538                 }
5539         }
5540
5541         pci_enable_pcie_error_reporting(pdev);
5542         enable_pcie_relaxed_ordering(pdev);
5543         pci_set_master(pdev);
5544         pci_save_state(pdev);
5545
5546         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5547         if (!adapter) {
5548                 err = -ENOMEM;
5549                 goto out_disable_device;
5550         }
5551
5552         adapter->regs = pci_ioremap_bar(pdev, 0);
5553         if (!adapter->regs) {
5554                 dev_err(&pdev->dev, "cannot map device registers\n");
5555                 err = -ENOMEM;
5556                 goto out_free_adapter;
5557         }
5558
5559         adapter->pdev = pdev;
5560         adapter->pdev_dev = &pdev->dev;
5561         adapter->mbox = func;
5562         adapter->fn = func;
5563         adapter->msg_enable = dflt_msg_enable;
5564         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5565
5566         spin_lock_init(&adapter->stats_lock);
5567         spin_lock_init(&adapter->tid_release_lock);
5568
5569         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
5570         INIT_WORK(&adapter->db_full_task, process_db_full);
5571         INIT_WORK(&adapter->db_drop_task, process_db_drop);
5572
5573         err = t4_prep_adapter(adapter);
5574         if (err)
5575                 goto out_unmap_bar0;
5576
5577         if (!is_t4(adapter->chip)) {
5578                 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
5579                 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
5580                       SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
5581                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5582
5583                 /* Each segment size is 128B. Write coalescing is enabled only
5584                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
5585                  * queue is less no of segments that can be accommodated in
5586                  * a page size.
5587                  */
5588                 if (qpp > num_seg) {
5589                         dev_err(&pdev->dev,
5590                                 "Incorrect number of egress queues per page\n");
5591                         err = -EINVAL;
5592                         goto out_unmap_bar0;
5593                 }
5594                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5595                 pci_resource_len(pdev, 2));
5596                 if (!adapter->bar2) {
5597                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
5598                         err = -ENOMEM;
5599                         goto out_unmap_bar0;
5600                 }
5601         }
5602
5603         setup_memwin(adapter);
5604         err = adap_init0(adapter);
5605         setup_memwin_rdma(adapter);
5606         if (err)
5607                 goto out_unmap_bar;
5608
5609         for_each_port(adapter, i) {
5610                 struct net_device *netdev;
5611
5612                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5613                                            MAX_ETH_QSETS);
5614                 if (!netdev) {
5615                         err = -ENOMEM;
5616                         goto out_free_dev;
5617                 }
5618
5619                 SET_NETDEV_DEV(netdev, &pdev->dev);
5620
5621                 adapter->port[i] = netdev;
5622                 pi = netdev_priv(netdev);
5623                 pi->adapter = adapter;
5624                 pi->xact_addr_filt = -1;
5625                 pi->port_id = i;
5626                 netdev->irq = pdev->irq;
5627
5628                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5629                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5630                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
5631                         NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5632                 if (highdma)
5633                         netdev->hw_features |= NETIF_F_HIGHDMA;
5634                 netdev->features |= netdev->hw_features;
5635                 netdev->vlan_features = netdev->features & VLAN_FEAT;
5636
5637                 netdev->priv_flags |= IFF_UNICAST_FLT;
5638
5639                 netdev->netdev_ops = &cxgb4_netdev_ops;
5640                 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
5641         }
5642
5643         pci_set_drvdata(pdev, adapter);
5644
5645         if (adapter->flags & FW_OK) {
5646                 err = t4_port_init(adapter, func, func, 0);
5647                 if (err)
5648                         goto out_free_dev;
5649         }
5650
5651         /*
5652          * Configure queues and allocate tables now, they can be needed as
5653          * soon as the first register_netdev completes.
5654          */
5655         cfg_queues(adapter);
5656
5657         adapter->l2t = t4_init_l2t();
5658         if (!adapter->l2t) {
5659                 /* We tolerate a lack of L2T, giving up some functionality */
5660                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5661                 adapter->params.offload = 0;
5662         }
5663
5664         if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
5665                 dev_warn(&pdev->dev, "could not allocate TID table, "
5666                          "continuing\n");
5667                 adapter->params.offload = 0;
5668         }
5669
5670         /* See what interrupts we'll be using */
5671         if (msi > 1 && enable_msix(adapter) == 0)
5672                 adapter->flags |= USING_MSIX;
5673         else if (msi > 0 && pci_enable_msi(pdev) == 0)
5674                 adapter->flags |= USING_MSI;
5675
5676         err = init_rss(adapter);
5677         if (err)
5678                 goto out_free_dev;
5679
5680         /*
5681          * The card is now ready to go.  If any errors occur during device
5682          * registration we do not fail the whole card but rather proceed only
5683          * with the ports we manage to register successfully.  However we must
5684          * register at least one net device.
5685          */
5686         for_each_port(adapter, i) {
5687                 pi = adap2pinfo(adapter, i);
5688                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5689                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5690
5691                 err = register_netdev(adapter->port[i]);
5692                 if (err)
5693                         break;
5694                 adapter->chan_map[pi->tx_chan] = i;
5695                 print_port_info(adapter->port[i]);
5696         }
5697         if (i == 0) {
5698                 dev_err(&pdev->dev, "could not register any net devices\n");
5699                 goto out_free_dev;
5700         }
5701         if (err) {
5702                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5703                 err = 0;
5704         }
5705
5706         if (cxgb4_debugfs_root) {
5707                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5708                                                            cxgb4_debugfs_root);
5709                 setup_debugfs(adapter);
5710         }
5711
5712         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5713         pdev->needs_freset = 1;
5714
5715         if (is_offload(adapter))
5716                 attach_ulds(adapter);
5717
5718 sriov:
5719 #ifdef CONFIG_PCI_IOV
5720         if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
5721                 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
5722                         dev_info(&pdev->dev,
5723                                  "instantiated %u virtual functions\n",
5724                                  num_vf[func]);
5725 #endif
5726         return 0;
5727
5728  out_free_dev:
5729         free_some_resources(adapter);
5730  out_unmap_bar:
5731         if (!is_t4(adapter->chip))
5732                 iounmap(adapter->bar2);
5733  out_unmap_bar0:
5734         iounmap(adapter->regs);
5735  out_free_adapter:
5736         kfree(adapter);
5737  out_disable_device:
5738         pci_disable_pcie_error_reporting(pdev);
5739         pci_disable_device(pdev);
5740  out_release_regions:
5741         pci_release_regions(pdev);
5742         pci_set_drvdata(pdev, NULL);
5743         return err;
5744 }
5745
5746 static void remove_one(struct pci_dev *pdev)
5747 {
5748         struct adapter *adapter = pci_get_drvdata(pdev);
5749
5750 #ifdef CONFIG_PCI_IOV
5751         pci_disable_sriov(pdev);
5752
5753 #endif
5754
5755         if (adapter) {
5756                 int i;
5757
5758                 if (is_offload(adapter))
5759                         detach_ulds(adapter);
5760
5761                 for_each_port(adapter, i)
5762                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5763                                 unregister_netdev(adapter->port[i]);
5764
5765                 if (adapter->debugfs_root)
5766                         debugfs_remove_recursive(adapter->debugfs_root);
5767
5768                 /* If we allocated filters, free up state associated with any
5769                  * valid filters ...
5770                  */
5771                 if (adapter->tids.ftid_tab) {
5772                         struct filter_entry *f = &adapter->tids.ftid_tab[0];
5773                         for (i = 0; i < (adapter->tids.nftids +
5774                                         adapter->tids.nsftids); i++, f++)
5775                                 if (f->valid)
5776                                         clear_filter(adapter, f);
5777                 }
5778
5779                 if (adapter->flags & FULL_INIT_DONE)
5780                         cxgb_down(adapter);
5781
5782                 free_some_resources(adapter);
5783                 iounmap(adapter->regs);
5784                 if (!is_t4(adapter->chip))
5785                         iounmap(adapter->bar2);
5786                 kfree(adapter);
5787                 pci_disable_pcie_error_reporting(pdev);
5788                 pci_disable_device(pdev);
5789                 pci_release_regions(pdev);
5790                 pci_set_drvdata(pdev, NULL);
5791         } else
5792                 pci_release_regions(pdev);
5793 }
5794
5795 static struct pci_driver cxgb4_driver = {
5796         .name     = KBUILD_MODNAME,
5797         .id_table = cxgb4_pci_tbl,
5798         .probe    = init_one,
5799         .remove   = remove_one,
5800         .err_handler = &cxgb4_eeh,
5801 };
5802
5803 static int __init cxgb4_init_module(void)
5804 {
5805         int ret;
5806
5807         workq = create_singlethread_workqueue("cxgb4");
5808         if (!workq)
5809                 return -ENOMEM;
5810
5811         /* Debugfs support is optional, just warn if this fails */
5812         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5813         if (!cxgb4_debugfs_root)
5814                 pr_warn("could not create debugfs entry, continuing\n");
5815
5816         ret = pci_register_driver(&cxgb4_driver);
5817         if (ret < 0)
5818                 debugfs_remove(cxgb4_debugfs_root);
5819         return ret;
5820 }
5821
5822 static void __exit cxgb4_cleanup_module(void)
5823 {
5824         pci_unregister_driver(&cxgb4_driver);
5825         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
5826         flush_workqueue(workq);
5827         destroy_workqueue(workq);
5828 }
5829
5830 module_init(cxgb4_init_module);
5831 module_exit(cxgb4_cleanup_module);