drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <linux/uaccess.h>
  66 #include <linux/crash_dump.h>
  67 #include <net/udp_tunnel.h>
  68 #include <net/xfrm.h>
  69
  70 #include "cxgb4.h"
  71 #include "cxgb4_filter.h"
  72 #include "t4_regs.h"
  73 #include "t4_values.h"
  74 #include "t4_msg.h"
  75 #include "t4fw_api.h"
  76 #include "t4fw_version.h"
  77 #include "cxgb4_dcb.h"
  78 #include "srq.h"
  79 #include "cxgb4_debugfs.h"
  80 #include "clip_tbl.h"
  81 #include "l2t.h"
  82 #include "smt.h"
  83 #include "sched.h"
  84 #include "cxgb4_tc_u32.h"
  85 #include "cxgb4_tc_flower.h"
  86 #include "cxgb4_tc_mqprio.h"
  87 #include "cxgb4_tc_matchall.h"
  88 #include "cxgb4_ptp.h"
  89 #include "cxgb4_cudbg.h"
  90
  91 char cxgb4_driver_name[] = KBUILD_MODNAME;
  92
  93 #ifdef DRV_VERSION
  94 #undef DRV_VERSION
  95 #endif
  96 #define DRV_VERSION "2.0.0-ko"
  97 const char cxgb4_driver_version[] = DRV_VERSION;
  98 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
  99
 100 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
 101                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
 102                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 103
 104 /* Macros needed to support the PCI Device ID Table ...
 105  */
 106 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
 107         static const struct pci_device_id cxgb4_pci_tbl[] = {
 108 #define CXGB4_UNIFIED_PF 0x4
 109
 110 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
 111
 112 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 113  * called for both.
 114  */
 115 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 116
 117 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 118                 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
 119
 120 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 121                 { 0, } \
 122         }
 123
 124 #include "t4_pci_id_tbl.h"
 125
 126 #define FW4_FNAME "cxgb4/t4fw.bin"
 127 #define FW5_FNAME "cxgb4/t5fw.bin"
 128 #define FW6_FNAME "cxgb4/t6fw.bin"
 129 #define FW4_CFNAME "cxgb4/t4-config.txt"
 130 #define FW5_CFNAME "cxgb4/t5-config.txt"
 131 #define FW6_CFNAME "cxgb4/t6-config.txt"
 132 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
 133 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
 134 #define PHY_AQ1202_DEVICEID 0x4409
 135 #define PHY_BCM84834_DEVICEID 0x4486
 136
 137 MODULE_DESCRIPTION(DRV_DESC);
 138 MODULE_AUTHOR("Chelsio Communications");
 139 MODULE_LICENSE("Dual BSD/GPL");
 140 MODULE_VERSION(DRV_VERSION);
 141 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 142 MODULE_FIRMWARE(FW4_FNAME);
 143 MODULE_FIRMWARE(FW5_FNAME);
 144 MODULE_FIRMWARE(FW6_FNAME);
 145
 146 /*
 147  * The driver uses the best interrupt scheme available on a platform in the
 148  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 149  * of these schemes the driver may consider as follows:
 150  *
 151  * msi = 2: choose from among all three options
 152  * msi = 1: only consider MSI and INTx interrupts
 153  * msi = 0: force INTx interrupts
 154  */
 155 static int msi = 2;
 156
 157 module_param(msi, int, 0644);
 158 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 159
 160 /*
 161  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 162  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 163  * boundaries.  This is a requirement for many architectures which will throw
 164  * a machine check fault if an attempt is made to access one of the 4-byte IP
 165  * header fields on a non-4-byte boundary.  And it's a major performance issue
 166  * even on some architectures which allow it like some implementations of the
 167  * x86 ISA.  However, some architectures don't mind this and for some very
 168  * edge-case performance sensitive applications (like forwarding large volumes
 169  * of small packets), setting this DMA offset to 0 will decrease the number of
 170  * PCI-E Bus transfers enough to measurably affect performance.
 171  */
 172 static int rx_dma_offset = 2;
 173
 174 /* TX Queue select used to determine what algorithm to use for selecting TX
 175  * queue. Select between the kernel provided function (select_queue=0) or user
 176  * cxgb_select_queue function (select_queue=1)
 177  *
 178  * Default: select_queue=0
 179  */
 180 static int select_queue;
 181 module_param(select_queue, int, 0644);
 182 MODULE_PARM_DESC(select_queue,
 183                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 184
 185 static struct dentry *cxgb4_debugfs_root;
 186
 187 LIST_HEAD(adapter_list);
 188 DEFINE_MUTEX(uld_mutex);
 189
 190 static int cfg_queues(struct adapter *adap);
 191
 192 static void link_report(struct net_device *dev)
 193 {
 194         if (!netif_carrier_ok(dev))
 195                 netdev_info(dev, "link down\n");
 196         else {
 197                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 198
 199                 const char *s;
 200                 const struct port_info *p = netdev_priv(dev);
 201
 202                 switch (p->link_cfg.speed) {
 203                 case 100:
 204                         s = "100Mbps";
 205                         break;
 206                 case 1000:
 207                         s = "1Gbps";
 208                         break;
 209                 case 10000:
 210                         s = "10Gbps";
 211                         break;
 212                 case 25000:
 213                         s = "25Gbps";
 214                         break;
 215                 case 40000:
 216                         s = "40Gbps";
 217                         break;
 218                 case 50000:
 219                         s = "50Gbps";
 220                         break;
 221                 case 100000:
 222                         s = "100Gbps";
 223                         break;
 224                 default:
 225                         pr_info("%s: unsupported speed: %d\n",
 226                                 dev->name, p->link_cfg.speed);
 227                         return;
 228                 }
 229
 230                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 231                             fc[p->link_cfg.fc]);
 232         }
 233 }
 234
 235 #ifdef CONFIG_CHELSIO_T4_DCB
 236 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 237 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 238 {
 239         struct port_info *pi = netdev_priv(dev);
 240         struct adapter *adap = pi->adapter;
 241         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 242         int i;
 243
 244         /* We use a simple mapping of Port TX Queue Index to DCB
 245          * Priority when we're enabling DCB.
 246          */
 247         for (i = 0; i < pi->nqsets; i++, txq++) {
 248                 u32 name, value;
 249                 int err;
 250
 251                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 252                         FW_PARAMS_PARAM_X_V(
 253                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 254                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 255                 value = enable ? i : 0xffffffff;
 256
 257                 /* Since we can be called while atomic (from "interrupt
 258                  * level") we need to issue the Set Parameters Commannd
 259                  * without sleeping (timeout < 0).
 260                  */
 261                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
 262                                             &name, &value,
 263                                             -FW_CMD_MAX_TIMEOUT);
 264
 265                 if (err)
 266                         dev_err(adap->pdev_dev,
 267                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 268                                 enable ? "set" : "unset", pi->port_id, i, -err);
 269                 else
 270                         txq->dcb_prio = enable ? value : 0;
 271         }
 272 }
 273
 274 int cxgb4_dcb_enabled(const struct net_device *dev)
 275 {
 276         struct port_info *pi = netdev_priv(dev);
 277
 278         if (!pi->dcb.enabled)
 279                 return 0;
 280
 281         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 282                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 283 }
 284 #endif /* CONFIG_CHELSIO_T4_DCB */
 285
 286 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 287 {
 288         struct net_device *dev = adapter->port[port_id];
 289
 290         /* Skip changes from disabled ports. */
 291         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 292                 if (link_stat)
 293                         netif_carrier_on(dev);
 294                 else {
 295 #ifdef CONFIG_CHELSIO_T4_DCB
 296                         if (cxgb4_dcb_enabled(dev)) {
 297                                 cxgb4_dcb_reset(dev);
 298                                 dcb_tx_queue_prio_enable(dev, false);
 299                         }
 300 #endif /* CONFIG_CHELSIO_T4_DCB */
 301                         netif_carrier_off(dev);
 302                 }
 303
 304                 link_report(dev);
 305         }
 306 }
 307
 308 void t4_os_portmod_changed(struct adapter *adap, int port_id)
 309 {
 310         static const char *mod_str[] = {
 311                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 312         };
 313
 314         struct net_device *dev = adap->port[port_id];
 315         struct port_info *pi = netdev_priv(dev);
 316
 317         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 318                 netdev_info(dev, "port module unplugged\n");
 319         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 320                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 321         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 322                 netdev_info(dev, "%s: unsupported port module inserted\n",
 323                             dev->name);
 324         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 325                 netdev_info(dev, "%s: unknown port module inserted\n",
 326                             dev->name);
 327         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 328                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
 329         else
 330                 netdev_info(dev, "%s: unknown module type %d inserted\n",
 331                             dev->name, pi->mod_type);
 332
 333         /* If the interface is running, then we'll need any "sticky" Link
 334          * Parameters redone with a new Transceiver Module.
 335          */
 336         pi->link_cfg.redo_l1cfg = netif_running(dev);
 337 }
 338
 339 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 340 module_param(dbfifo_int_thresh, int, 0644);
 341 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 342
 343 /*
 344  * usecs to sleep while draining the dbfifo
 345  */
 346 static int dbfifo_drain_delay = 1000;
 347 module_param(dbfifo_drain_delay, int, 0644);
 348 MODULE_PARM_DESC(dbfifo_drain_delay,
 349                  "usecs to sleep while draining the dbfifo");
 350
 351 static inline int cxgb4_set_addr_hash(struct port_info *pi)
 352 {
 353         struct adapter *adap = pi->adapter;
 354         u64 vec = 0;
 355         bool ucast = false;
 356         struct hash_mac_addr *entry;
 357
 358         /* Calculate the hash vector for the updated list and program it */
 359         list_for_each_entry(entry, &adap->mac_hlist, list) {
 360                 ucast |= is_unicast_ether_addr(entry->addr);
 361                 vec |= (1ULL << hash_mac_addr(entry->addr));
 362         }
 363         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
 364                                 vec, false);
 365 }
 366
 367 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
 368 {
 369         struct port_info *pi = netdev_priv(netdev);
 370         struct adapter *adap = pi->adapter;
 371         int ret;
 372         u64 mhash = 0;
 373         u64 uhash = 0;
 374         /* idx stores the index of allocated filters,
 375          * its size should be modified based on the number of
 376          * MAC addresses that we allocate filters for
 377          */
 378
 379         u16 idx[1] = {};
 380         bool free = false;
 381         bool ucast = is_unicast_ether_addr(mac_addr);
 382         const u8 *maclist[1] = {mac_addr};
 383         struct hash_mac_addr *new_entry;
 384
 385         ret = cxgb4_alloc_mac_filt(adap, pi->viid, free, 1, maclist,
 386                                    idx, ucast ? &uhash : &mhash, false);
 387         if (ret < 0)
 388                 goto out;
 389         /* if hash != 0, then add the addr to hash addr list
 390          * so on the end we will calculate the hash for the
 391          * list and program it
 392          */
 393         if (uhash || mhash) {
 394                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
 395                 if (!new_entry)
 396                         return -ENOMEM;
 397                 ether_addr_copy(new_entry->addr, mac_addr);
 398                 list_add_tail(&new_entry->list, &adap->mac_hlist);
 399                 ret = cxgb4_set_addr_hash(pi);
 400         }
 401 out:
 402         return ret < 0 ? ret : 0;
 403 }
 404
 405 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
 406 {
 407         struct port_info *pi = netdev_priv(netdev);
 408         struct adapter *adap = pi->adapter;
 409         int ret;
 410         const u8 *maclist[1] = {mac_addr};
 411         struct hash_mac_addr *entry, *tmp;
 412
 413         /* If the MAC address to be removed is in the hash addr
 414          * list, delete it from the list and update hash vector
 415          */
 416         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
 417                 if (ether_addr_equal(entry->addr, mac_addr)) {
 418                         list_del(&entry->list);
 419                         kfree(entry);
 420                         return cxgb4_set_addr_hash(pi);
 421                 }
 422         }
 423
 424         ret = cxgb4_free_mac_filt(adap, pi->viid, 1, maclist, false);
 425         return ret < 0 ? -EINVAL : 0;
 426 }
 427
 428 /*
 429  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 430  * If @mtu is -1 it is left unchanged.
 431  */
 432 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 433 {
 434         struct port_info *pi = netdev_priv(dev);
 435         struct adapter *adapter = pi->adapter;
 436
 437         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 438         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 439
 440         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
 441                              (dev->flags & IFF_PROMISC) ? 1 : 0,
 442                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 443                              sleep_ok);
 444 }
 445
 446 /**
 447  *      cxgb4_change_mac - Update match filter for a MAC address.
 448  *      @pi: the port_info
 449  *      @viid: the VI id
 450  *      @tcam_idx: TCAM index of existing filter for old value of MAC address,
 451  *                 or -1
 452  *      @addr: the new MAC address value
 453  *      @persist: whether a new MAC allocation should be persistent
 454  *      @add_smt: if true also add the address to the HW SMT
 455  *
 456  *      Modifies an MPS filter and sets it to the new MAC address if
 457  *      @tcam_idx >= 0, or adds the MAC address to a new filter if
 458  *      @tcam_idx < 0. In the latter case the address is added persistently
 459  *      if @persist is %true.
 460  *      Addresses are programmed to hash region, if tcam runs out of entries.
 461  *
 462  */
 463 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
 464                      int *tcam_idx, const u8 *addr, bool persist,
 465                      u8 *smt_idx)
 466 {
 467         struct adapter *adapter = pi->adapter;
 468         struct hash_mac_addr *entry, *new_entry;
 469         int ret;
 470
 471         ret = t4_change_mac(adapter, adapter->mbox, viid,
 472                             *tcam_idx, addr, persist, smt_idx);
 473         /* We ran out of TCAM entries. try programming hash region. */
 474         if (ret == -ENOMEM) {
 475                 /* If the MAC address to be updated is in the hash addr
 476                  * list, update it from the list
 477                  */
 478                 list_for_each_entry(entry, &adapter->mac_hlist, list) {
 479                         if (entry->iface_mac) {
 480                                 ether_addr_copy(entry->addr, addr);
 481                                 goto set_hash;
 482                         }
 483                 }
 484                 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
 485                 if (!new_entry)
 486                         return -ENOMEM;
 487                 ether_addr_copy(new_entry->addr, addr);
 488                 new_entry->iface_mac = true;
 489                 list_add_tail(&new_entry->list, &adapter->mac_hlist);
 490 set_hash:
 491                 ret = cxgb4_set_addr_hash(pi);
 492         } else if (ret >= 0) {
 493                 *tcam_idx = ret;
 494                 ret = 0;
 495         }
 496
 497         return ret;
 498 }
 499
 500 /*
 501  *      link_start - enable a port
 502  *      @dev: the port to enable
 503  *
 504  *      Performs the MAC and PHY actions needed to enable a port.
 505  */
 506 static int link_start(struct net_device *dev)
 507 {
 508         int ret;
 509         struct port_info *pi = netdev_priv(dev);
 510         unsigned int mb = pi->adapter->pf;
 511
 512         /*
 513          * We do not set address filters and promiscuity here, the stack does
 514          * that step explicitly.
 515          */
 516         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 517                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 518         if (ret == 0)
 519                 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
 520                                             dev->dev_addr, true, &pi->smt_idx);
 521         if (ret == 0)
 522                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
 523                                     &pi->link_cfg);
 524         if (ret == 0) {
 525                 local_bh_disable();
 526                 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
 527                                           true, CXGB4_DCB_ENABLED);
 528                 local_bh_enable();
 529         }
 530
 531         return ret;
 532 }
 533
 534 #ifdef CONFIG_CHELSIO_T4_DCB
 535 /* Handle a Data Center Bridging update message from the firmware. */
 536 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 537 {
 538         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 539         struct net_device *dev = adap->port[adap->chan_map[port]];
 540         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 541         int new_dcb_enabled;
 542
 543         cxgb4_dcb_handle_fw_update(adap, pcmd);
 544         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 545
 546         /* If the DCB has become enabled or disabled on the port then we're
 547          * going to need to set up/tear down DCB Priority parameters for the
 548          * TX Queues associated with the port.
 549          */
 550         if (new_dcb_enabled != old_dcb_enabled)
 551                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 552 }
 553 #endif /* CONFIG_CHELSIO_T4_DCB */
 554
 555 /* Response queue handler for the FW event queue.
 556  */
 557 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 558                           const struct pkt_gl *gl)
 559 {
 560         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 561
 562         rsp++;                                          /* skip RSS header */
 563
 564         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 565          */
 566         if (unlikely(opcode == CPL_FW4_MSG &&
 567            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 568                 rsp++;
 569                 opcode = ((const struct rss_header *)rsp)->opcode;
 570                 rsp++;
 571                 if (opcode != CPL_SGE_EGR_UPDATE) {
 572                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 573                                 , opcode);
 574                         goto out;
 575                 }
 576         }
 577
 578         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 579                 const struct cpl_sge_egr_update *p = (void *)rsp;
 580                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
 581                 struct sge_txq *txq;
 582
 583                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 584                 txq->restarts++;
 585                 if (txq->q_type == CXGB4_TXQ_ETH) {
 586                         struct sge_eth_txq *eq;
 587
 588                         eq = container_of(txq, struct sge_eth_txq, q);
 589                         t4_sge_eth_txq_egress_update(q->adap, eq, -1);
 590                 } else {
 591                         struct sge_uld_txq *oq;
 592
 593                         oq = container_of(txq, struct sge_uld_txq, q);
 594                         tasklet_schedule(&oq->qresume_tsk);
 595                 }
 596         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 597                 const struct cpl_fw6_msg *p = (void *)rsp;
 598
 599 #ifdef CONFIG_CHELSIO_T4_DCB
 600                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 601                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 602                 unsigned int action =
 603                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 604
 605                 if (cmd == FW_PORT_CMD &&
 606                     (action == FW_PORT_ACTION_GET_PORT_INFO ||
 607                      action == FW_PORT_ACTION_GET_PORT_INFO32)) {
 608                         int port = FW_PORT_CMD_PORTID_G(
 609                                         be32_to_cpu(pcmd->op_to_portid));
 610                         struct net_device *dev;
 611                         int dcbxdis, state_input;
 612
 613                         dev = q->adap->port[q->adap->chan_map[port]];
 614                         dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
 615                           ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
 616                           : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
 617                                & FW_PORT_CMD_DCBXDIS32_F));
 618                         state_input = (dcbxdis
 619                                        ? CXGB4_DCB_INPUT_FW_DISABLED
 620                                        : CXGB4_DCB_INPUT_FW_ENABLED);
 621
 622                         cxgb4_dcb_state_fsm(dev, state_input);
 623                 }
 624
 625                 if (cmd == FW_PORT_CMD &&
 626                     action == FW_PORT_ACTION_L2_DCB_CFG)
 627                         dcb_rpl(q->adap, pcmd);
 628                 else
 629 #endif
 630                         if (p->type == 0)
 631                                 t4_handle_fw_rpl(q->adap, p->data);
 632         } else if (opcode == CPL_L2T_WRITE_RPL) {
 633                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 634
 635                 do_l2t_write_rpl(q->adap, p);
 636         } else if (opcode == CPL_SMT_WRITE_RPL) {
 637                 const struct cpl_smt_write_rpl *p = (void *)rsp;
 638
 639                 do_smt_write_rpl(q->adap, p);
 640         } else if (opcode == CPL_SET_TCB_RPL) {
 641                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 642
 643                 filter_rpl(q->adap, p);
 644         } else if (opcode == CPL_ACT_OPEN_RPL) {
 645                 const struct cpl_act_open_rpl *p = (void *)rsp;
 646
 647                 hash_filter_rpl(q->adap, p);
 648         } else if (opcode == CPL_ABORT_RPL_RSS) {
 649                 const struct cpl_abort_rpl_rss *p = (void *)rsp;
 650
 651                 hash_del_filter_rpl(q->adap, p);
 652         } else if (opcode == CPL_SRQ_TABLE_RPL) {
 653                 const struct cpl_srq_table_rpl *p = (void *)rsp;
 654
 655                 do_srq_table_rpl(q->adap, p);
 656         } else
 657                 dev_err(q->adap->pdev_dev,
 658                         "unexpected CPL %#x on FW event queue\n", opcode);
 659 out:
 660         return 0;
 661 }
 662
 663 static void disable_msi(struct adapter *adapter)
 664 {
 665         if (adapter->flags & CXGB4_USING_MSIX) {
 666                 pci_disable_msix(adapter->pdev);
 667                 adapter->flags &= ~CXGB4_USING_MSIX;
 668         } else if (adapter->flags & CXGB4_USING_MSI) {
 669                 pci_disable_msi(adapter->pdev);
 670                 adapter->flags &= ~CXGB4_USING_MSI;
 671         }
 672 }
 673
 674 /*
 675  * Interrupt handler for non-data events used with MSI-X.
 676  */
 677 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 678 {
 679         struct adapter *adap = cookie;
 680         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
 681
 682         if (v & PFSW_F) {
 683                 adap->swintr = 1;
 684                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
 685         }
 686         if (adap->flags & CXGB4_MASTER_PF)
 687                 t4_slow_intr_handler(adap);
 688         return IRQ_HANDLED;
 689 }
 690
 691 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
 692                        cpumask_var_t *aff_mask, int idx)
 693 {
 694         int rv;
 695
 696         if (!zalloc_cpumask_var(aff_mask, GFP_KERNEL)) {
 697                 dev_err(adap->pdev_dev, "alloc_cpumask_var failed\n");
 698                 return -ENOMEM;
 699         }
 700
 701         cpumask_set_cpu(cpumask_local_spread(idx, dev_to_node(adap->pdev_dev)),
 702                         *aff_mask);
 703
 704         rv = irq_set_affinity_hint(vec, *aff_mask);
 705         if (rv)
 706                 dev_warn(adap->pdev_dev,
 707                          "irq_set_affinity_hint %u failed %d\n",
 708                          vec, rv);
 709
 710         return 0;
 711 }
 712
 713 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask)
 714 {
 715         irq_set_affinity_hint(vec, NULL);
 716         free_cpumask_var(aff_mask);
 717 }
 718
 719 static int request_msix_queue_irqs(struct adapter *adap)
 720 {
 721         struct sge *s = &adap->sge;
 722         struct msix_info *minfo;
 723         int err, ethqidx;
 724
 725         if (s->fwevtq_msix_idx < 0)
 726                 return -ENOMEM;
 727
 728         err = request_irq(adap->msix_info[s->fwevtq_msix_idx].vec,
 729                           t4_sge_intr_msix, 0,
 730                           adap->msix_info[s->fwevtq_msix_idx].desc,
 731                           &s->fw_evtq);
 732         if (err)
 733                 return err;
 734
 735         for_each_ethrxq(s, ethqidx) {
 736                 minfo = s->ethrxq[ethqidx].msix;
 737                 err = request_irq(minfo->vec,
 738                                   t4_sge_intr_msix, 0,
 739                                   minfo->desc,
 740                                   &s->ethrxq[ethqidx].rspq);
 741                 if (err)
 742                         goto unwind;
 743
 744                 cxgb4_set_msix_aff(adap, minfo->vec,
 745                                    &minfo->aff_mask, ethqidx);
 746         }
 747         return 0;
 748
 749 unwind:
 750         while (--ethqidx >= 0) {
 751                 minfo = s->ethrxq[ethqidx].msix;
 752                 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
 753                 free_irq(minfo->vec, &s->ethrxq[ethqidx].rspq);
 754         }
 755         free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq);
 756         return err;
 757 }
 758
 759 static void free_msix_queue_irqs(struct adapter *adap)
 760 {
 761         struct sge *s = &adap->sge;
 762         struct msix_info *minfo;
 763         int i;
 764
 765         free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq);
 766         for_each_ethrxq(s, i) {
 767                 minfo = s->ethrxq[i].msix;
 768                 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
 769                 free_irq(minfo->vec, &s->ethrxq[i].rspq);
 770         }
 771 }
 772
 773 static int setup_ppod_edram(struct adapter *adap)
 774 {
 775         unsigned int param, val;
 776         int ret;
 777
 778         /* Driver sends FW_PARAMS_PARAM_DEV_PPOD_EDRAM read command to check
 779          * if firmware supports ppod edram feature or not. If firmware
 780          * returns 1, then driver can enable this feature by sending
 781          * FW_PARAMS_PARAM_DEV_PPOD_EDRAM write command with value 1 to
 782          * enable ppod edram feature.
 783          */
 784         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
 785                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PPOD_EDRAM));
 786
 787         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
 788         if (ret < 0) {
 789                 dev_warn(adap->pdev_dev,
 790                          "querying PPOD_EDRAM support failed: %d\n",
 791                          ret);
 792                 return -1;
 793         }
 794
 795         if (val != 1)
 796                 return -1;
 797
 798         ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
 799         if (ret < 0) {
 800                 dev_err(adap->pdev_dev,
 801                         "setting PPOD_EDRAM failed: %d\n", ret);
 802                 return -1;
 803         }
 804         return 0;
 805 }
 806
 807 /**
 808  *      cxgb4_write_rss - write the RSS table for a given port
 809  *      @pi: the port
 810  *      @queues: array of queue indices for RSS
 811  *
 812  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 813  *      packets to the Rx queues in @queues.
 814  *      Should never be called before setting up sge eth rx queues
 815  */
 816 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 817 {
 818         u16 *rss;
 819         int i, err;
 820         struct adapter *adapter = pi->adapter;
 821         const struct sge_eth_rxq *rxq;
 822
 823         rxq = &adapter->sge.ethrxq[pi->first_qset];
 824         rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
 825         if (!rss)
 826                 return -ENOMEM;
 827
 828         /* map the queue indices to queue ids */
 829         for (i = 0; i < pi->rss_size; i++, queues++)
 830                 rss[i] = rxq[*queues].rspq.abs_id;
 831
 832         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 833                                   pi->rss_size, rss, pi->rss_size);
 834         /* If Tunnel All Lookup isn't specified in the global RSS
 835          * Configuration, then we need to specify a default Ingress
 836          * Queue for any ingress packets which aren't hashed.  We'll
 837          * use our first ingress queue ...
 838          */
 839         if (!err)
 840                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 841                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
 842                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
 843                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
 844                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
 845                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
 846                                        rss[0]);
 847         kfree(rss);
 848         return err;
 849 }
 850
 851 /**
 852  *      setup_rss - configure RSS
 853  *      @adap: the adapter
 854  *
 855  *      Sets up RSS for each port.
 856  */
 857 static int setup_rss(struct adapter *adap)
 858 {
 859         int i, j, err;
 860
 861         for_each_port(adap, i) {
 862                 const struct port_info *pi = adap2pinfo(adap, i);
 863
 864                 /* Fill default values with equal distribution */
 865                 for (j = 0; j < pi->rss_size; j++)
 866                         pi->rss[j] = j % pi->nqsets;
 867
 868                 err = cxgb4_write_rss(pi, pi->rss);
 869                 if (err)
 870                         return err;
 871         }
 872         return 0;
 873 }
 874
 875 /*
 876  * Return the channel of the ingress queue with the given qid.
 877  */
 878 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
 879 {
 880         qid -= p->ingr_start;
 881         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
 882 }
 883
 884 void cxgb4_quiesce_rx(struct sge_rspq *q)
 885 {
 886         if (q->handler)
 887                 napi_disable(&q->napi);
 888 }
 889
 890 /*
 891  * Wait until all NAPI handlers are descheduled.
 892  */
 893 static void quiesce_rx(struct adapter *adap)
 894 {
 895         int i;
 896
 897         for (i = 0; i < adap->sge.ingr_sz; i++) {
 898                 struct sge_rspq *q = adap->sge.ingr_map[i];
 899
 900                 if (!q)
 901                         continue;
 902
 903                 cxgb4_quiesce_rx(q);
 904         }
 905 }
 906
 907 /* Disable interrupt and napi handler */
 908 static void disable_interrupts(struct adapter *adap)
 909 {
 910         struct sge *s = &adap->sge;
 911
 912         if (adap->flags & CXGB4_FULL_INIT_DONE) {
 913                 t4_intr_disable(adap);
 914                 if (adap->flags & CXGB4_USING_MSIX) {
 915                         free_msix_queue_irqs(adap);
 916                         free_irq(adap->msix_info[s->nd_msix_idx].vec,
 917                                  adap);
 918                 } else {
 919                         free_irq(adap->pdev->irq, adap);
 920                 }
 921                 quiesce_rx(adap);
 922         }
 923 }
 924
 925 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q)
 926 {
 927         if (q->handler)
 928                 napi_enable(&q->napi);
 929
 930         /* 0-increment GTS to start the timer and enable interrupts */
 931         t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 932                      SEINTARM_V(q->intr_params) |
 933                      INGRESSQID_V(q->cntxt_id));
 934 }
 935
 936 /*
 937  * Enable NAPI scheduling and interrupt generation for all Rx queues.
 938  */
 939 static void enable_rx(struct adapter *adap)
 940 {
 941         int i;
 942
 943         for (i = 0; i < adap->sge.ingr_sz; i++) {
 944                 struct sge_rspq *q = adap->sge.ingr_map[i];
 945
 946                 if (!q)
 947                         continue;
 948
 949                 cxgb4_enable_rx(adap, q);
 950         }
 951 }
 952
 953 static int setup_non_data_intr(struct adapter *adap)
 954 {
 955         int msix;
 956
 957         adap->sge.nd_msix_idx = -1;
 958         if (!(adap->flags & CXGB4_USING_MSIX))
 959                 return 0;
 960
 961         /* Request MSI-X vector for non-data interrupt */
 962         msix = cxgb4_get_msix_idx_from_bmap(adap);
 963         if (msix < 0)
 964                 return -ENOMEM;
 965
 966         snprintf(adap->msix_info[msix].desc,
 967                  sizeof(adap->msix_info[msix].desc),
 968                  "%s", adap->port[0]->name);
 969
 970         adap->sge.nd_msix_idx = msix;
 971         return 0;
 972 }
 973
 974 static int setup_fw_sge_queues(struct adapter *adap)
 975 {
 976         struct sge *s = &adap->sge;
 977         int msix, err = 0;
 978
 979         bitmap_zero(s->starving_fl, s->egr_sz);
 980         bitmap_zero(s->txq_maperr, s->egr_sz);
 981
 982         if (adap->flags & CXGB4_USING_MSIX) {
 983                 s->fwevtq_msix_idx = -1;
 984                 msix = cxgb4_get_msix_idx_from_bmap(adap);
 985                 if (msix < 0)
 986                         return -ENOMEM;
 987
 988                 snprintf(adap->msix_info[msix].desc,
 989                          sizeof(adap->msix_info[msix].desc),
 990                          "%s-FWeventq", adap->port[0]->name);
 991         } else {
 992                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
 993                                        NULL, NULL, NULL, -1);
 994                 if (err)
 995                         return err;
 996                 msix = -((int)s->intrq.abs_id + 1);
 997         }
 998
 999         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1000                                msix, NULL, fwevtq_handler, NULL, -1);
1001         if (err && msix >= 0)
1002                 cxgb4_free_msix_idx_in_bmap(adap, msix);
1003
1004         s->fwevtq_msix_idx = msix;
1005         return err;
1006 }
1007
1008 /**
1009  *      setup_sge_queues - configure SGE Tx/Rx/response queues
1010  *      @adap: the adapter
1011  *
1012  *      Determines how many sets of SGE queues to use and initializes them.
1013  *      We support multiple queue sets per port if we have MSI-X, otherwise
1014  *      just one queue set per port.
1015  */
1016 static int setup_sge_queues(struct adapter *adap)
1017 {
1018         struct sge_uld_rxq_info *rxq_info = NULL;
1019         struct sge *s = &adap->sge;
1020         unsigned int cmplqid = 0;
1021         int err, i, j, msix = 0;
1022
1023         if (is_uld(adap))
1024                 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
1025
1026         if (!(adap->flags & CXGB4_USING_MSIX))
1027                 msix = -((int)s->intrq.abs_id + 1);
1028
1029         for_each_port(adap, i) {
1030                 struct net_device *dev = adap->port[i];
1031                 struct port_info *pi = netdev_priv(dev);
1032                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1033                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1034
1035                 for (j = 0; j < pi->nqsets; j++, q++) {
1036                         if (msix >= 0) {
1037                                 msix = cxgb4_get_msix_idx_from_bmap(adap);
1038                                 if (msix < 0) {
1039                                         err = msix;
1040                                         goto freeout;
1041                                 }
1042
1043                                 snprintf(adap->msix_info[msix].desc,
1044                                          sizeof(adap->msix_info[msix].desc),
1045                                          "%s-Rx%d", dev->name, j);
1046                                 q->msix = &adap->msix_info[msix];
1047                         }
1048
1049                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1050                                                msix, &q->fl,
1051                                                t4_ethrx_handler,
1052                                                NULL,
1053                                                t4_get_tp_ch_map(adap,
1054                                                                 pi->tx_chan));
1055                         if (err)
1056                                 goto freeout;
1057                         q->rspq.idx = j;
1058                         memset(&q->stats, 0, sizeof(q->stats));
1059                 }
1060
1061                 q = &s->ethrxq[pi->first_qset];
1062                 for (j = 0; j < pi->nqsets; j++, t++, q++) {
1063                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1064                                         netdev_get_tx_queue(dev, j),
1065                                         q->rspq.cntxt_id,
1066                                         !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
1067                         if (err)
1068                                 goto freeout;
1069                 }
1070         }
1071
1072         for_each_port(adap, i) {
1073                 /* Note that cmplqid below is 0 if we don't
1074                  * have RDMA queues, and that's the right value.
1075                  */
1076                 if (rxq_info)
1077                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
1078
1079                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1080                                             s->fw_evtq.cntxt_id, cmplqid);
1081                 if (err)
1082                         goto freeout;
1083         }
1084
1085         if (!is_t4(adap->params.chip)) {
1086                 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
1087                                            netdev_get_tx_queue(adap->port[0], 0)
1088                                            , s->fw_evtq.cntxt_id, false);
1089                 if (err)
1090                         goto freeout;
1091         }
1092
1093         t4_write_reg(adap, is_t4(adap->params.chip) ?
1094                                 MPS_TRC_RSS_CONTROL_A :
1095                                 MPS_T5_TRC_RSS_CONTROL_A,
1096                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1097                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1098         return 0;
1099 freeout:
1100         dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
1101         t4_free_sge_resources(adap);
1102         return err;
1103 }
1104
1105 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1106                              struct net_device *sb_dev)
1107 {
1108         int txq;
1109
1110 #ifdef CONFIG_CHELSIO_T4_DCB
1111         /* If a Data Center Bridging has been successfully negotiated on this
1112          * link then we'll use the skb's priority to map it to a TX Queue.
1113          * The skb's priority is determined via the VLAN Tag Priority Code
1114          * Point field.
1115          */
1116         if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
1117                 u16 vlan_tci;
1118                 int err;
1119
1120                 err = vlan_get_tag(skb, &vlan_tci);
1121                 if (unlikely(err)) {
1122                         if (net_ratelimit())
1123                                 netdev_warn(dev,
1124                                             "TX Packet without VLAN Tag on DCB Link\n");
1125                         txq = 0;
1126                 } else {
1127                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1128 #ifdef CONFIG_CHELSIO_T4_FCOE
1129                         if (skb->protocol == htons(ETH_P_FCOE))
1130                                 txq = skb->priority & 0x7;
1131 #endif /* CONFIG_CHELSIO_T4_FCOE */
1132                 }
1133                 return txq;
1134         }
1135 #endif /* CONFIG_CHELSIO_T4_DCB */
1136
1137         if (dev->num_tc) {
1138                 struct port_info *pi = netdev2pinfo(dev);
1139
1140                 /* Send unsupported traffic pattern to normal NIC queues. */
1141                 txq = netdev_pick_tx(dev, skb, sb_dev);
1142                 if (xfrm_offload(skb) || is_ptp_enabled(skb, dev) ||
1143                     ip_hdr(skb)->protocol != IPPROTO_TCP)
1144                         txq = txq % pi->nqsets;
1145
1146                 return txq;
1147         }
1148
1149         if (select_queue) {
1150                 txq = (skb_rx_queue_recorded(skb)
1151                         ? skb_get_rx_queue(skb)
1152                         : smp_processor_id());
1153
1154                 while (unlikely(txq >= dev->real_num_tx_queues))
1155                         txq -= dev->real_num_tx_queues;
1156
1157                 return txq;
1158         }
1159
1160         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
1161 }
1162
1163 static int closest_timer(const struct sge *s, int time)
1164 {
1165         int i, delta, match = 0, min_delta = INT_MAX;
1166
1167         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1168                 delta = time - s->timer_val[i];
1169                 if (delta < 0)
1170                         delta = -delta;
1171                 if (delta < min_delta) {
1172                         min_delta = delta;
1173                         match = i;
1174                 }
1175         }
1176         return match;
1177 }
1178
1179 static int closest_thres(const struct sge *s, int thres)
1180 {
1181         int i, delta, match = 0, min_delta = INT_MAX;
1182
1183         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1184                 delta = thres - s->counter_val[i];
1185                 if (delta < 0)
1186                         delta = -delta;
1187                 if (delta < min_delta) {
1188                         min_delta = delta;
1189                         match = i;
1190                 }
1191         }
1192         return match;
1193 }
1194
1195 /**
1196  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1197  *      @q: the Rx queue
1198  *      @us: the hold-off time in us, or 0 to disable timer
1199  *      @cnt: the hold-off packet count, or 0 to disable counter
1200  *
1201  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
1202  *      one of the two needs to be enabled for the queue to generate interrupts.
1203  */
1204 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1205                                unsigned int us, unsigned int cnt)
1206 {
1207         struct adapter *adap = q->adap;
1208
1209         if ((us | cnt) == 0)
1210                 cnt = 1;
1211
1212         if (cnt) {
1213                 int err;
1214                 u32 v, new_idx;
1215
1216                 new_idx = closest_thres(&adap->sge, cnt);
1217                 if (q->desc && q->pktcnt_idx != new_idx) {
1218                         /* the queue has already been created, update it */
1219                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1220                             FW_PARAMS_PARAM_X_V(
1221                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1222                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1223                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1224                                             &v, &new_idx);
1225                         if (err)
1226                                 return err;
1227                 }
1228                 q->pktcnt_idx = new_idx;
1229         }
1230
1231         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1232         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1233         return 0;
1234 }
1235
1236 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1237 {
1238         const struct port_info *pi = netdev_priv(dev);
1239         netdev_features_t changed = dev->features ^ features;
1240         int err;
1241
1242         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1243                 return 0;
1244
1245         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1246                             -1, -1, -1,
1247                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1248         if (unlikely(err))
1249                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1250         return err;
1251 }
1252
1253 static int setup_debugfs(struct adapter *adap)
1254 {
1255         if (IS_ERR_OR_NULL(adap->debugfs_root))
1256                 return -1;
1257
1258 #ifdef CONFIG_DEBUG_FS
1259         t4_setup_debugfs(adap);
1260 #endif
1261         return 0;
1262 }
1263
1264 /*
1265  * upper-layer driver support
1266  */
1267
1268 /*
1269  * Allocate an active-open TID and set it to the supplied value.
1270  */
1271 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1272 {
1273         int atid = -1;
1274
1275         spin_lock_bh(&t->atid_lock);
1276         if (t->afree) {
1277                 union aopen_entry *p = t->afree;
1278
1279                 atid = (p - t->atid_tab) + t->atid_base;
1280                 t->afree = p->next;
1281                 p->data = data;
1282                 t->atids_in_use++;
1283         }
1284         spin_unlock_bh(&t->atid_lock);
1285         return atid;
1286 }
1287 EXPORT_SYMBOL(cxgb4_alloc_atid);
1288
1289 /*
1290  * Release an active-open TID.
1291  */
1292 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1293 {
1294         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1295
1296         spin_lock_bh(&t->atid_lock);
1297         p->next = t->afree;
1298         t->afree = p;
1299         t->atids_in_use--;
1300         spin_unlock_bh(&t->atid_lock);
1301 }
1302 EXPORT_SYMBOL(cxgb4_free_atid);
1303
1304 /*
1305  * Allocate a server TID and set it to the supplied value.
1306  */
1307 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1308 {
1309         int stid;
1310
1311         spin_lock_bh(&t->stid_lock);
1312         if (family == PF_INET) {
1313                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1314                 if (stid < t->nstids)
1315                         __set_bit(stid, t->stid_bmap);
1316                 else
1317                         stid = -1;
1318         } else {
1319                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1320                 if (stid < 0)
1321                         stid = -1;
1322         }
1323         if (stid >= 0) {
1324                 t->stid_tab[stid].data = data;
1325                 stid += t->stid_base;
1326                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1327                  * This is equivalent to 4 TIDs. With CLIP enabled it
1328                  * needs 2 TIDs.
1329                  */
1330                 if (family == PF_INET6) {
1331                         t->stids_in_use += 2;
1332                         t->v6_stids_in_use += 2;
1333                 } else {
1334                         t->stids_in_use++;
1335                 }
1336         }
1337         spin_unlock_bh(&t->stid_lock);
1338         return stid;
1339 }
1340 EXPORT_SYMBOL(cxgb4_alloc_stid);
1341
1342 /* Allocate a server filter TID and set it to the supplied value.
1343  */
1344 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1345 {
1346         int stid;
1347
1348         spin_lock_bh(&t->stid_lock);
1349         if (family == PF_INET) {
1350                 stid = find_next_zero_bit(t->stid_bmap,
1351                                 t->nstids + t->nsftids, t->nstids);
1352                 if (stid < (t->nstids + t->nsftids))
1353                         __set_bit(stid, t->stid_bmap);
1354                 else
1355                         stid = -1;
1356         } else {
1357                 stid = -1;
1358         }
1359         if (stid >= 0) {
1360                 t->stid_tab[stid].data = data;
1361                 stid -= t->nstids;
1362                 stid += t->sftid_base;
1363                 t->sftids_in_use++;
1364         }
1365         spin_unlock_bh(&t->stid_lock);
1366         return stid;
1367 }
1368 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1369
1370 /* Release a server TID.
1371  */
1372 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1373 {
1374         /* Is it a server filter TID? */
1375         if (t->nsftids && (stid >= t->sftid_base)) {
1376                 stid -= t->sftid_base;
1377                 stid += t->nstids;
1378         } else {
1379                 stid -= t->stid_base;
1380         }
1381
1382         spin_lock_bh(&t->stid_lock);
1383         if (family == PF_INET)
1384                 __clear_bit(stid, t->stid_bmap);
1385         else
1386                 bitmap_release_region(t->stid_bmap, stid, 1);
1387         t->stid_tab[stid].data = NULL;
1388         if (stid < t->nstids) {
1389                 if (family == PF_INET6) {
1390                         t->stids_in_use -= 2;
1391                         t->v6_stids_in_use -= 2;
1392                 } else {
1393                         t->stids_in_use--;
1394                 }
1395         } else {
1396                 t->sftids_in_use--;
1397         }
1398
1399         spin_unlock_bh(&t->stid_lock);
1400 }
1401 EXPORT_SYMBOL(cxgb4_free_stid);
1402
1403 /*
1404  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1405  */
1406 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1407                            unsigned int tid)
1408 {
1409         struct cpl_tid_release *req;
1410
1411         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1412         req = __skb_put(skb, sizeof(*req));
1413         INIT_TP_WR(req, tid);
1414         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1415 }
1416
1417 /*
1418  * Queue a TID release request and if necessary schedule a work queue to
1419  * process it.
1420  */
1421 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1422                                     unsigned int tid)
1423 {
1424         void **p = &t->tid_tab[tid];
1425         struct adapter *adap = container_of(t, struct adapter, tids);
1426
1427         spin_lock_bh(&adap->tid_release_lock);
1428         *p = adap->tid_release_head;
1429         /* Low 2 bits encode the Tx channel number */
1430         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1431         if (!adap->tid_release_task_busy) {
1432                 adap->tid_release_task_busy = true;
1433                 queue_work(adap->workq, &adap->tid_release_task);
1434         }
1435         spin_unlock_bh(&adap->tid_release_lock);
1436 }
1437
1438 /*
1439  * Process the list of pending TID release requests.
1440  */
1441 static void process_tid_release_list(struct work_struct *work)
1442 {
1443         struct sk_buff *skb;
1444         struct adapter *adap;
1445
1446         adap = container_of(work, struct adapter, tid_release_task);
1447
1448         spin_lock_bh(&adap->tid_release_lock);
1449         while (adap->tid_release_head) {
1450                 void **p = adap->tid_release_head;
1451                 unsigned int chan = (uintptr_t)p & 3;
1452                 p = (void *)p - chan;
1453
1454                 adap->tid_release_head = *p;
1455                 *p = NULL;
1456                 spin_unlock_bh(&adap->tid_release_lock);
1457
1458                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1459                                          GFP_KERNEL)))
1460                         schedule_timeout_uninterruptible(1);
1461
1462                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1463                 t4_ofld_send(adap, skb);
1464                 spin_lock_bh(&adap->tid_release_lock);
1465         }
1466         adap->tid_release_task_busy = false;
1467         spin_unlock_bh(&adap->tid_release_lock);
1468 }
1469
1470 /*
1471  * Release a TID and inform HW.  If we are unable to allocate the release
1472  * message we defer to a work queue.
1473  */
1474 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1475                       unsigned short family)
1476 {
1477         struct sk_buff *skb;
1478         struct adapter *adap = container_of(t, struct adapter, tids);
1479
1480         WARN_ON(tid >= t->ntids);
1481
1482         if (t->tid_tab[tid]) {
1483                 t->tid_tab[tid] = NULL;
1484                 atomic_dec(&t->conns_in_use);
1485                 if (t->hash_base && (tid >= t->hash_base)) {
1486                         if (family == AF_INET6)
1487                                 atomic_sub(2, &t->hash_tids_in_use);
1488                         else
1489                                 atomic_dec(&t->hash_tids_in_use);
1490                 } else {
1491                         if (family == AF_INET6)
1492                                 atomic_sub(2, &t->tids_in_use);
1493                         else
1494                                 atomic_dec(&t->tids_in_use);
1495                 }
1496         }
1497
1498         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1499         if (likely(skb)) {
1500                 mk_tid_release(skb, chan, tid);
1501                 t4_ofld_send(adap, skb);
1502         } else
1503                 cxgb4_queue_tid_release(t, chan, tid);
1504 }
1505 EXPORT_SYMBOL(cxgb4_remove_tid);
1506
1507 /*
1508  * Allocate and initialize the TID tables.  Returns 0 on success.
1509  */
1510 static int tid_init(struct tid_info *t)
1511 {
1512         struct adapter *adap = container_of(t, struct adapter, tids);
1513         unsigned int max_ftids = t->nftids + t->nsftids;
1514         unsigned int natids = t->natids;
1515         unsigned int eotid_bmap_size;
1516         unsigned int stid_bmap_size;
1517         unsigned int ftid_bmap_size;
1518         size_t size;
1519
1520         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1521         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1522         eotid_bmap_size = BITS_TO_LONGS(t->neotids);
1523         size = t->ntids * sizeof(*t->tid_tab) +
1524                natids * sizeof(*t->atid_tab) +
1525                t->nstids * sizeof(*t->stid_tab) +
1526                t->nsftids * sizeof(*t->stid_tab) +
1527                stid_bmap_size * sizeof(long) +
1528                max_ftids * sizeof(*t->ftid_tab) +
1529                ftid_bmap_size * sizeof(long) +
1530                t->neotids * sizeof(*t->eotid_tab) +
1531                eotid_bmap_size * sizeof(long);
1532
1533         t->tid_tab = kvzalloc(size, GFP_KERNEL);
1534         if (!t->tid_tab)
1535                 return -ENOMEM;
1536
1537         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1538         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1539         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1540         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1541         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1542         t->eotid_tab = (struct eotid_entry *)&t->ftid_bmap[ftid_bmap_size];
1543         t->eotid_bmap = (unsigned long *)&t->eotid_tab[t->neotids];
1544         spin_lock_init(&t->stid_lock);
1545         spin_lock_init(&t->atid_lock);
1546         spin_lock_init(&t->ftid_lock);
1547
1548         t->stids_in_use = 0;
1549         t->v6_stids_in_use = 0;
1550         t->sftids_in_use = 0;
1551         t->afree = NULL;
1552         t->atids_in_use = 0;
1553         atomic_set(&t->tids_in_use, 0);
1554         atomic_set(&t->conns_in_use, 0);
1555         atomic_set(&t->hash_tids_in_use, 0);
1556
1557         /* Setup the free list for atid_tab and clear the stid bitmap. */
1558         if (natids) {
1559                 while (--natids)
1560                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1561                 t->afree = t->atid_tab;
1562         }
1563
1564         if (is_offload(adap)) {
1565                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1566                 /* Reserve stid 0 for T4/T5 adapters */
1567                 if (!t->stid_base &&
1568                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1569                         __set_bit(0, t->stid_bmap);
1570
1571                 if (t->neotids)
1572                         bitmap_zero(t->eotid_bmap, t->neotids);
1573         }
1574
1575         bitmap_zero(t->ftid_bmap, t->nftids);
1576         return 0;
1577 }
1578
1579 /**
1580  *      cxgb4_create_server - create an IP server
1581  *      @dev: the device
1582  *      @stid: the server TID
1583  *      @sip: local IP address to bind server to
1584  *      @sport: the server's TCP port
1585  *      @queue: queue to direct messages from this server to
1586  *
1587  *      Create an IP server for the given port and address.
1588  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1589  */
1590 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1591                         __be32 sip, __be16 sport, __be16 vlan,
1592                         unsigned int queue)
1593 {
1594         unsigned int chan;
1595         struct sk_buff *skb;
1596         struct adapter *adap;
1597         struct cpl_pass_open_req *req;
1598         int ret;
1599
1600         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1601         if (!skb)
1602                 return -ENOMEM;
1603
1604         adap = netdev2adap(dev);
1605         req = __skb_put(skb, sizeof(*req));
1606         INIT_TP_WR(req, 0);
1607         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1608         req->local_port = sport;
1609         req->peer_port = htons(0);
1610         req->local_ip = sip;
1611         req->peer_ip = htonl(0);
1612         chan = rxq_to_chan(&adap->sge, queue);
1613         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1614         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1615                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1616         ret = t4_mgmt_tx(adap, skb);
1617         return net_xmit_eval(ret);
1618 }
1619 EXPORT_SYMBOL(cxgb4_create_server);
1620
1621 /*      cxgb4_create_server6 - create an IPv6 server
1622  *      @dev: the device
1623  *      @stid: the server TID
1624  *      @sip: local IPv6 address to bind server to
1625  *      @sport: the server's TCP port
1626  *      @queue: queue to direct messages from this server to
1627  *
1628  *      Create an IPv6 server for the given port and address.
1629  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1630  */
1631 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1632                          const struct in6_addr *sip, __be16 sport,
1633                          unsigned int queue)
1634 {
1635         unsigned int chan;
1636         struct sk_buff *skb;
1637         struct adapter *adap;
1638         struct cpl_pass_open_req6 *req;
1639         int ret;
1640
1641         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1642         if (!skb)
1643                 return -ENOMEM;
1644
1645         adap = netdev2adap(dev);
1646         req = __skb_put(skb, sizeof(*req));
1647         INIT_TP_WR(req, 0);
1648         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1649         req->local_port = sport;
1650         req->peer_port = htons(0);
1651         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1652         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1653         req->peer_ip_hi = cpu_to_be64(0);
1654         req->peer_ip_lo = cpu_to_be64(0);
1655         chan = rxq_to_chan(&adap->sge, queue);
1656         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1657         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1658                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1659         ret = t4_mgmt_tx(adap, skb);
1660         return net_xmit_eval(ret);
1661 }
1662 EXPORT_SYMBOL(cxgb4_create_server6);
1663
1664 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1665                         unsigned int queue, bool ipv6)
1666 {
1667         struct sk_buff *skb;
1668         struct adapter *adap;
1669         struct cpl_close_listsvr_req *req;
1670         int ret;
1671
1672         adap = netdev2adap(dev);
1673
1674         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1675         if (!skb)
1676                 return -ENOMEM;
1677
1678         req = __skb_put(skb, sizeof(*req));
1679         INIT_TP_WR(req, 0);
1680         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1681         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1682                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1683         ret = t4_mgmt_tx(adap, skb);
1684         return net_xmit_eval(ret);
1685 }
1686 EXPORT_SYMBOL(cxgb4_remove_server);
1687
1688 /**
1689  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1690  *      @mtus: the HW MTU table
1691  *      @mtu: the target MTU
1692  *      @idx: index of selected entry in the MTU table
1693  *
1694  *      Returns the index and the value in the HW MTU table that is closest to
1695  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1696  *      table, in which case that smallest available value is selected.
1697  */
1698 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1699                             unsigned int *idx)
1700 {
1701         unsigned int i = 0;
1702
1703         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1704                 ++i;
1705         if (idx)
1706                 *idx = i;
1707         return mtus[i];
1708 }
1709 EXPORT_SYMBOL(cxgb4_best_mtu);
1710
1711 /**
1712  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1713  *     @mtus: the HW MTU table
1714  *     @header_size: Header Size
1715  *     @data_size_max: maximum Data Segment Size
1716  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1717  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1718  *
1719  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1720  *     MTU Table based solely on a Maximum MTU parameter, we break that
1721  *     parameter up into a Header Size and Maximum Data Segment Size, and
1722  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1723  *     the Hardware MTU Table which will result in a Data Segment Size with
1724  *     the requested alignment _and_ that MTU isn't "too far" from the
1725  *     closest MTU, then we'll return that rather than the closest MTU.
1726  */
1727 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1728                                     unsigned short header_size,
1729                                     unsigned short data_size_max,
1730                                     unsigned short data_size_align,
1731                                     unsigned int *mtu_idxp)
1732 {
1733         unsigned short max_mtu = header_size + data_size_max;
1734         unsigned short data_size_align_mask = data_size_align - 1;
1735         int mtu_idx, aligned_mtu_idx;
1736
1737         /* Scan the MTU Table till we find an MTU which is larger than our
1738          * Maximum MTU or we reach the end of the table.  Along the way,
1739          * record the last MTU found, if any, which will result in a Data
1740          * Segment Length matching the requested alignment.
1741          */
1742         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1743                 unsigned short data_size = mtus[mtu_idx] - header_size;
1744
1745                 /* If this MTU minus the Header Size would result in a
1746                  * Data Segment Size of the desired alignment, remember it.
1747                  */
1748                 if ((data_size & data_size_align_mask) == 0)
1749                         aligned_mtu_idx = mtu_idx;
1750
1751                 /* If we're not at the end of the Hardware MTU Table and the
1752                  * next element is larger than our Maximum MTU, drop out of
1753                  * the loop.
1754                  */
1755                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1756                         break;
1757         }
1758
1759         /* If we fell out of the loop because we ran to the end of the table,
1760          * then we just have to use the last [largest] entry.
1761          */
1762         if (mtu_idx == NMTUS)
1763                 mtu_idx--;
1764
1765         /* If we found an MTU which resulted in the requested Data Segment
1766          * Length alignment and that's "not far" from the largest MTU which is
1767          * less than or equal to the maximum MTU, then use that.
1768          */
1769         if (aligned_mtu_idx >= 0 &&
1770             mtu_idx - aligned_mtu_idx <= 1)
1771                 mtu_idx = aligned_mtu_idx;
1772
1773         /* If the caller has passed in an MTU Index pointer, pass the
1774          * MTU Index back.  Return the MTU value.
1775          */
1776         if (mtu_idxp)
1777                 *mtu_idxp = mtu_idx;
1778         return mtus[mtu_idx];
1779 }
1780 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1781
1782 /**
1783  *      cxgb4_port_chan - get the HW channel of a port
1784  *      @dev: the net device for the port
1785  *
1786  *      Return the HW Tx channel of the given port.
1787  */
1788 unsigned int cxgb4_port_chan(const struct net_device *dev)
1789 {
1790         return netdev2pinfo(dev)->tx_chan;
1791 }
1792 EXPORT_SYMBOL(cxgb4_port_chan);
1793
1794 /**
1795  *      cxgb4_port_e2cchan - get the HW c-channel of a port
1796  *      @dev: the net device for the port
1797  *
1798  *      Return the HW RX c-channel of the given port.
1799  */
1800 unsigned int cxgb4_port_e2cchan(const struct net_device *dev)
1801 {
1802         return netdev2pinfo(dev)->rx_cchan;
1803 }
1804 EXPORT_SYMBOL(cxgb4_port_e2cchan);
1805
1806 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1807 {
1808         struct adapter *adap = netdev2adap(dev);
1809         u32 v1, v2, lp_count, hp_count;
1810
1811         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1812         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1813         if (is_t4(adap->params.chip)) {
1814                 lp_count = LP_COUNT_G(v1);
1815                 hp_count = HP_COUNT_G(v1);
1816         } else {
1817                 lp_count = LP_COUNT_T5_G(v1);
1818                 hp_count = HP_COUNT_T5_G(v2);
1819         }
1820         return lpfifo ? lp_count : hp_count;
1821 }
1822 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1823
1824 /**
1825  *      cxgb4_port_viid - get the VI id of a port
1826  *      @dev: the net device for the port
1827  *
1828  *      Return the VI id of the given port.
1829  */
1830 unsigned int cxgb4_port_viid(const struct net_device *dev)
1831 {
1832         return netdev2pinfo(dev)->viid;
1833 }
1834 EXPORT_SYMBOL(cxgb4_port_viid);
1835
1836 /**
1837  *      cxgb4_port_idx - get the index of a port
1838  *      @dev: the net device for the port
1839  *
1840  *      Return the index of the given port.
1841  */
1842 unsigned int cxgb4_port_idx(const struct net_device *dev)
1843 {
1844         return netdev2pinfo(dev)->port_id;
1845 }
1846 EXPORT_SYMBOL(cxgb4_port_idx);
1847
1848 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1849                          struct tp_tcp_stats *v6)
1850 {
1851         struct adapter *adap = pci_get_drvdata(pdev);
1852
1853         spin_lock(&adap->stats_lock);
1854         t4_tp_get_tcp_stats(adap, v4, v6, false);
1855         spin_unlock(&adap->stats_lock);
1856 }
1857 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1858
1859 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1860                       const unsigned int *pgsz_order)
1861 {
1862         struct adapter *adap = netdev2adap(dev);
1863
1864         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1865         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1866                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1867                      HPZ3_V(pgsz_order[3]));
1868 }
1869 EXPORT_SYMBOL(cxgb4_iscsi_init);
1870
1871 int cxgb4_flush_eq_cache(struct net_device *dev)
1872 {
1873         struct adapter *adap = netdev2adap(dev);
1874
1875         return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1876 }
1877 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1878
1879 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1880 {
1881         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1882         __be64 indices;
1883         int ret;
1884
1885         spin_lock(&adap->win0_lock);
1886         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1887                            sizeof(indices), (__be32 *)&indices,
1888                            T4_MEMORY_READ);
1889         spin_unlock(&adap->win0_lock);
1890         if (!ret) {
1891                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1892                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1893         }
1894         return ret;
1895 }
1896
1897 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1898                         u16 size)
1899 {
1900         struct adapter *adap = netdev2adap(dev);
1901         u16 hw_pidx, hw_cidx;
1902         int ret;
1903
1904         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1905         if (ret)
1906                 goto out;
1907
1908         if (pidx != hw_pidx) {
1909                 u16 delta;
1910                 u32 val;
1911
1912                 if (pidx >= hw_pidx)
1913                         delta = pidx - hw_pidx;
1914                 else
1915                         delta = size - hw_pidx + pidx;
1916
1917                 if (is_t4(adap->params.chip))
1918                         val = PIDX_V(delta);
1919                 else
1920                         val = PIDX_T5_V(delta);
1921                 wmb();
1922                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1923                              QID_V(qid) | val);
1924         }
1925 out:
1926         return ret;
1927 }
1928 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1929
1930 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1931 {
1932         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1933         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1934         u32 offset, memtype, memaddr;
1935         struct adapter *adap;
1936         u32 hma_size = 0;
1937         int ret;
1938
1939         adap = netdev2adap(dev);
1940
1941         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1942
1943         /* Figure out where the offset lands in the Memory Type/Address scheme.
1944          * This code assumes that the memory is laid out starting at offset 0
1945          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1946          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1947          * MC0, and some have both MC0 and MC1.
1948          */
1949         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1950         edc0_size = EDRAM0_SIZE_G(size) << 20;
1951         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1952         edc1_size = EDRAM1_SIZE_G(size) << 20;
1953         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1954         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1955
1956         if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1957                 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1958                 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1959         }
1960         edc0_end = edc0_size;
1961         edc1_end = edc0_end + edc1_size;
1962         mc0_end = edc1_end + mc0_size;
1963
1964         if (offset < edc0_end) {
1965                 memtype = MEM_EDC0;
1966                 memaddr = offset;
1967         } else if (offset < edc1_end) {
1968                 memtype = MEM_EDC1;
1969                 memaddr = offset - edc0_end;
1970         } else {
1971                 if (hma_size && (offset < (edc1_end + hma_size))) {
1972                         memtype = MEM_HMA;
1973                         memaddr = offset - edc1_end;
1974                 } else if (offset < mc0_end) {
1975                         memtype = MEM_MC0;
1976                         memaddr = offset - edc1_end;
1977                 } else if (is_t5(adap->params.chip)) {
1978                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1979                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1980                         mc1_end = mc0_end + mc1_size;
1981                         if (offset < mc1_end) {
1982                                 memtype = MEM_MC1;
1983                                 memaddr = offset - mc0_end;
1984                         } else {
1985                                 /* offset beyond the end of any memory */
1986                                 goto err;
1987                         }
1988                 } else {
1989                         /* T4/T6 only has a single memory channel */
1990                         goto err;
1991                 }
1992         }
1993
1994         spin_lock(&adap->win0_lock);
1995         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1996         spin_unlock(&adap->win0_lock);
1997         return ret;
1998
1999 err:
2000         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2001                 stag, offset);
2002         return -EINVAL;
2003 }
2004 EXPORT_SYMBOL(cxgb4_read_tpte);
2005
2006 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2007 {
2008         u32 hi, lo;
2009         struct adapter *adap;
2010
2011         adap = netdev2adap(dev);
2012         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2013         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2014
2015         return ((u64)hi << 32) | (u64)lo;
2016 }
2017 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2018
2019 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2020                          unsigned int qid,
2021                          enum cxgb4_bar2_qtype qtype,
2022                          int user,
2023                          u64 *pbar2_qoffset,
2024                          unsigned int *pbar2_qid)
2025 {
2026         return t4_bar2_sge_qregs(netdev2adap(dev),
2027                                  qid,
2028                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
2029                                   ? T4_BAR2_QTYPE_EGRESS
2030                                   : T4_BAR2_QTYPE_INGRESS),
2031                                  user,
2032                                  pbar2_qoffset,
2033                                  pbar2_qid);
2034 }
2035 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2036
2037 static struct pci_driver cxgb4_driver;
2038
2039 static void check_neigh_update(struct neighbour *neigh)
2040 {
2041         const struct device *parent;
2042         const struct net_device *netdev = neigh->dev;
2043
2044         if (is_vlan_dev(netdev))
2045                 netdev = vlan_dev_real_dev(netdev);
2046         parent = netdev->dev.parent;
2047         if (parent && parent->driver == &cxgb4_driver.driver)
2048                 t4_l2t_update(dev_get_drvdata(parent), neigh);
2049 }
2050
2051 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2052                        void *data)
2053 {
2054         switch (event) {
2055         case NETEVENT_NEIGH_UPDATE:
2056                 check_neigh_update(data);
2057                 break;
2058         case NETEVENT_REDIRECT:
2059         default:
2060                 break;
2061         }
2062         return 0;
2063 }
2064
2065 static bool netevent_registered;
2066 static struct notifier_block cxgb4_netevent_nb = {
2067         .notifier_call = netevent_cb
2068 };
2069
2070 static void drain_db_fifo(struct adapter *adap, int usecs)
2071 {
2072         u32 v1, v2, lp_count, hp_count;
2073
2074         do {
2075                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2076                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2077                 if (is_t4(adap->params.chip)) {
2078                         lp_count = LP_COUNT_G(v1);
2079                         hp_count = HP_COUNT_G(v1);
2080                 } else {
2081                         lp_count = LP_COUNT_T5_G(v1);
2082                         hp_count = HP_COUNT_T5_G(v2);
2083                 }
2084
2085                 if (lp_count == 0 && hp_count == 0)
2086                         break;
2087                 set_current_state(TASK_UNINTERRUPTIBLE);
2088                 schedule_timeout(usecs_to_jiffies(usecs));
2089         } while (1);
2090 }
2091
2092 static void disable_txq_db(struct sge_txq *q)
2093 {
2094         unsigned long flags;
2095
2096         spin_lock_irqsave(&q->db_lock, flags);
2097         q->db_disabled = 1;
2098         spin_unlock_irqrestore(&q->db_lock, flags);
2099 }
2100
2101 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2102 {
2103         spin_lock_irq(&q->db_lock);
2104         if (q->db_pidx_inc) {
2105                 /* Make sure that all writes to the TX descriptors
2106                  * are committed before we tell HW about them.
2107                  */
2108                 wmb();
2109                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2110                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2111                 q->db_pidx_inc = 0;
2112         }
2113         q->db_disabled = 0;
2114         spin_unlock_irq(&q->db_lock);
2115 }
2116
2117 static void disable_dbs(struct adapter *adap)
2118 {
2119         int i;
2120
2121         for_each_ethrxq(&adap->sge, i)
2122                 disable_txq_db(&adap->sge.ethtxq[i].q);
2123         if (is_offload(adap)) {
2124                 struct sge_uld_txq_info *txq_info =
2125                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2126
2127                 if (txq_info) {
2128                         for_each_ofldtxq(&adap->sge, i) {
2129                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2130
2131                                 disable_txq_db(&txq->q);
2132                         }
2133                 }
2134         }
2135         for_each_port(adap, i)
2136                 disable_txq_db(&adap->sge.ctrlq[i].q);
2137 }
2138
2139 static void enable_dbs(struct adapter *adap)
2140 {
2141         int i;
2142
2143         for_each_ethrxq(&adap->sge, i)
2144                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2145         if (is_offload(adap)) {
2146                 struct sge_uld_txq_info *txq_info =
2147                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2148
2149                 if (txq_info) {
2150                         for_each_ofldtxq(&adap->sge, i) {
2151                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2152
2153                                 enable_txq_db(adap, &txq->q);
2154                         }
2155                 }
2156         }
2157         for_each_port(adap, i)
2158                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2159 }
2160
2161 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2162 {
2163         enum cxgb4_uld type = CXGB4_ULD_RDMA;
2164
2165         if (adap->uld && adap->uld[type].handle)
2166                 adap->uld[type].control(adap->uld[type].handle, cmd);
2167 }
2168
2169 static void process_db_full(struct work_struct *work)
2170 {
2171         struct adapter *adap;
2172
2173         adap = container_of(work, struct adapter, db_full_task);
2174
2175         drain_db_fifo(adap, dbfifo_drain_delay);
2176         enable_dbs(adap);
2177         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2178         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2179                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2180                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2181                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2182         else
2183                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2184                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2185 }
2186
2187 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2188 {
2189         u16 hw_pidx, hw_cidx;
2190         int ret;
2191
2192         spin_lock_irq(&q->db_lock);
2193         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2194         if (ret)
2195                 goto out;
2196         if (q->db_pidx != hw_pidx) {
2197                 u16 delta;
2198                 u32 val;
2199
2200                 if (q->db_pidx >= hw_pidx)
2201                         delta = q->db_pidx - hw_pidx;
2202                 else
2203                         delta = q->size - hw_pidx + q->db_pidx;
2204
2205                 if (is_t4(adap->params.chip))
2206                         val = PIDX_V(delta);
2207                 else
2208                         val = PIDX_T5_V(delta);
2209                 wmb();
2210                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2211                              QID_V(q->cntxt_id) | val);
2212         }
2213 out:
2214         q->db_disabled = 0;
2215         q->db_pidx_inc = 0;
2216         spin_unlock_irq(&q->db_lock);
2217         if (ret)
2218                 CH_WARN(adap, "DB drop recovery failed.\n");
2219 }
2220
2221 static void recover_all_queues(struct adapter *adap)
2222 {
2223         int i;
2224
2225         for_each_ethrxq(&adap->sge, i)
2226                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2227         if (is_offload(adap)) {
2228                 struct sge_uld_txq_info *txq_info =
2229                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2230                 if (txq_info) {
2231                         for_each_ofldtxq(&adap->sge, i) {
2232                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2233
2234                                 sync_txq_pidx(adap, &txq->q);
2235                         }
2236                 }
2237         }
2238         for_each_port(adap, i)
2239                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2240 }
2241
2242 static void process_db_drop(struct work_struct *work)
2243 {
2244         struct adapter *adap;
2245
2246         adap = container_of(work, struct adapter, db_drop_task);
2247
2248         if (is_t4(adap->params.chip)) {
2249                 drain_db_fifo(adap, dbfifo_drain_delay);
2250                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2251                 drain_db_fifo(adap, dbfifo_drain_delay);
2252                 recover_all_queues(adap);
2253                 drain_db_fifo(adap, dbfifo_drain_delay);
2254                 enable_dbs(adap);
2255                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2256         } else if (is_t5(adap->params.chip)) {
2257                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2258                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2259                 u16 pidx_inc = dropped_db & 0x1fff;
2260                 u64 bar2_qoffset;
2261                 unsigned int bar2_qid;
2262                 int ret;
2263
2264                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2265                                         0, &bar2_qoffset, &bar2_qid);
2266                 if (ret)
2267                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2268                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2269                 else
2270                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2271                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2272
2273                 /* Re-enable BAR2 WC */
2274                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2275         }
2276
2277         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2278                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2279 }
2280
2281 void t4_db_full(struct adapter *adap)
2282 {
2283         if (is_t4(adap->params.chip)) {
2284                 disable_dbs(adap);
2285                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2286                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2287                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2288                 queue_work(adap->workq, &adap->db_full_task);
2289         }
2290 }
2291
2292 void t4_db_dropped(struct adapter *adap)
2293 {
2294         if (is_t4(adap->params.chip)) {
2295                 disable_dbs(adap);
2296                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2297         }
2298         queue_work(adap->workq, &adap->db_drop_task);
2299 }
2300
2301 void t4_register_netevent_notifier(void)
2302 {
2303         if (!netevent_registered) {
2304                 register_netevent_notifier(&cxgb4_netevent_nb);
2305                 netevent_registered = true;
2306         }
2307 }
2308
2309 static void detach_ulds(struct adapter *adap)
2310 {
2311         unsigned int i;
2312
2313         mutex_lock(&uld_mutex);
2314         list_del(&adap->list_node);
2315
2316         for (i = 0; i < CXGB4_ULD_MAX; i++)
2317                 if (adap->uld && adap->uld[i].handle)
2318                         adap->uld[i].state_change(adap->uld[i].handle,
2319                                              CXGB4_STATE_DETACH);
2320
2321         if (netevent_registered && list_empty(&adapter_list)) {
2322                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2323                 netevent_registered = false;
2324         }
2325         mutex_unlock(&uld_mutex);
2326 }
2327
2328 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2329 {
2330         unsigned int i;
2331
2332         mutex_lock(&uld_mutex);
2333         for (i = 0; i < CXGB4_ULD_MAX; i++)
2334                 if (adap->uld && adap->uld[i].handle)
2335                         adap->uld[i].state_change(adap->uld[i].handle,
2336                                                   new_state);
2337         mutex_unlock(&uld_mutex);
2338 }
2339
2340 #if IS_ENABLED(CONFIG_IPV6)
2341 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2342                                    unsigned long event, void *data)
2343 {
2344         struct inet6_ifaddr *ifa = data;
2345         struct net_device *event_dev = ifa->idev->dev;
2346         const struct device *parent = NULL;
2347 #if IS_ENABLED(CONFIG_BONDING)
2348         struct adapter *adap;
2349 #endif
2350         if (is_vlan_dev(event_dev))
2351                 event_dev = vlan_dev_real_dev(event_dev);
2352 #if IS_ENABLED(CONFIG_BONDING)
2353         if (event_dev->flags & IFF_MASTER) {
2354                 list_for_each_entry(adap, &adapter_list, list_node) {
2355                         switch (event) {
2356                         case NETDEV_UP:
2357                                 cxgb4_clip_get(adap->port[0],
2358                                                (const u32 *)ifa, 1);
2359                                 break;
2360                         case NETDEV_DOWN:
2361                                 cxgb4_clip_release(adap->port[0],
2362                                                    (const u32 *)ifa, 1);
2363                                 break;
2364                         default:
2365                                 break;
2366                         }
2367                 }
2368                 return NOTIFY_OK;
2369         }
2370 #endif
2371
2372         if (event_dev)
2373                 parent = event_dev->dev.parent;
2374
2375         if (parent && parent->driver == &cxgb4_driver.driver) {
2376                 switch (event) {
2377                 case NETDEV_UP:
2378                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2379                         break;
2380                 case NETDEV_DOWN:
2381                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2382                         break;
2383                 default:
2384                         break;
2385                 }
2386         }
2387         return NOTIFY_OK;
2388 }
2389
2390 static bool inet6addr_registered;
2391 static struct notifier_block cxgb4_inet6addr_notifier = {
2392         .notifier_call = cxgb4_inet6addr_handler
2393 };
2394
2395 static void update_clip(const struct adapter *adap)
2396 {
2397         int i;
2398         struct net_device *dev;
2399         int ret;
2400
2401         rcu_read_lock();
2402
2403         for (i = 0; i < MAX_NPORTS; i++) {
2404                 dev = adap->port[i];
2405                 ret = 0;
2406
2407                 if (dev)
2408                         ret = cxgb4_update_root_dev_clip(dev);
2409
2410                 if (ret < 0)
2411                         break;
2412         }
2413         rcu_read_unlock();
2414 }
2415 #endif /* IS_ENABLED(CONFIG_IPV6) */
2416
2417 /**
2418  *      cxgb_up - enable the adapter
2419  *      @adap: adapter being enabled
2420  *
2421  *      Called when the first port is enabled, this function performs the
2422  *      actions necessary to make an adapter operational, such as completing
2423  *      the initialization of HW modules, and enabling interrupts.
2424  *
2425  *      Must be called with the rtnl lock held.
2426  */
2427 static int cxgb_up(struct adapter *adap)
2428 {
2429         struct sge *s = &adap->sge;
2430         int err;
2431
2432         mutex_lock(&uld_mutex);
2433         err = setup_sge_queues(adap);
2434         if (err)
2435                 goto rel_lock;
2436         err = setup_rss(adap);
2437         if (err)
2438                 goto freeq;
2439
2440         if (adap->flags & CXGB4_USING_MSIX) {
2441                 if (s->nd_msix_idx < 0) {
2442                         err = -ENOMEM;
2443                         goto irq_err;
2444                 }
2445
2446                 err = request_irq(adap->msix_info[s->nd_msix_idx].vec,
2447                                   t4_nondata_intr, 0,
2448                                   adap->msix_info[s->nd_msix_idx].desc, adap);
2449                 if (err)
2450                         goto irq_err;
2451
2452                 err = request_msix_queue_irqs(adap);
2453                 if (err)
2454                         goto irq_err_free_nd_msix;
2455         } else {
2456                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2457                                   (adap->flags & CXGB4_USING_MSI) ? 0
2458                                                                   : IRQF_SHARED,
2459                                   adap->port[0]->name, adap);
2460                 if (err)
2461                         goto irq_err;
2462         }
2463
2464         enable_rx(adap);
2465         t4_sge_start(adap);
2466         t4_intr_enable(adap);
2467         adap->flags |= CXGB4_FULL_INIT_DONE;
2468         mutex_unlock(&uld_mutex);
2469
2470         notify_ulds(adap, CXGB4_STATE_UP);
2471 #if IS_ENABLED(CONFIG_IPV6)
2472         update_clip(adap);
2473 #endif
2474         return err;
2475
2476 irq_err_free_nd_msix:
2477         free_irq(adap->msix_info[s->nd_msix_idx].vec, adap);
2478 irq_err:
2479         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2480 freeq:
2481         t4_free_sge_resources(adap);
2482 rel_lock:
2483         mutex_unlock(&uld_mutex);
2484         return err;
2485 }
2486
2487 static void cxgb_down(struct adapter *adapter)
2488 {
2489         cancel_work_sync(&adapter->tid_release_task);
2490         cancel_work_sync(&adapter->db_full_task);
2491         cancel_work_sync(&adapter->db_drop_task);
2492         adapter->tid_release_task_busy = false;
2493         adapter->tid_release_head = NULL;
2494
2495         t4_sge_stop(adapter);
2496         t4_free_sge_resources(adapter);
2497
2498         adapter->flags &= ~CXGB4_FULL_INIT_DONE;
2499 }
2500
2501 /*
2502  * net_device operations
2503  */
2504 int cxgb_open(struct net_device *dev)
2505 {
2506         struct port_info *pi = netdev_priv(dev);
2507         struct adapter *adapter = pi->adapter;
2508         int err;
2509
2510         netif_carrier_off(dev);
2511
2512         if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
2513                 err = cxgb_up(adapter);
2514                 if (err < 0)
2515                         return err;
2516         }
2517
2518         /* It's possible that the basic port information could have
2519          * changed since we first read it.
2520          */
2521         err = t4_update_port_info(pi);
2522         if (err < 0)
2523                 return err;
2524
2525         err = link_start(dev);
2526         if (!err)
2527                 netif_tx_start_all_queues(dev);
2528         return err;
2529 }
2530
2531 int cxgb_close(struct net_device *dev)
2532 {
2533         struct port_info *pi = netdev_priv(dev);
2534         struct adapter *adapter = pi->adapter;
2535         int ret;
2536
2537         netif_tx_stop_all_queues(dev);
2538         netif_carrier_off(dev);
2539         ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2540                                   false, false, false);
2541 #ifdef CONFIG_CHELSIO_T4_DCB
2542         cxgb4_dcb_reset(dev);
2543         dcb_tx_queue_prio_enable(dev, false);
2544 #endif
2545         return ret;
2546 }
2547
2548 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2549                 __be32 sip, __be16 sport, __be16 vlan,
2550                 unsigned int queue, unsigned char port, unsigned char mask)
2551 {
2552         int ret;
2553         struct filter_entry *f;
2554         struct adapter *adap;
2555         int i;
2556         u8 *val;
2557
2558         adap = netdev2adap(dev);
2559
2560         /* Adjust stid to correct filter index */
2561         stid -= adap->tids.sftid_base;
2562         stid += adap->tids.nftids;
2563
2564         /* Check to make sure the filter requested is writable ...
2565          */
2566         f = &adap->tids.ftid_tab[stid];
2567         ret = writable_filter(f);
2568         if (ret)
2569                 return ret;
2570
2571         /* Clear out any old resources being used by the filter before
2572          * we start constructing the new filter.
2573          */
2574         if (f->valid)
2575                 clear_filter(adap, f);
2576
2577         /* Clear out filter specifications */
2578         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2579         f->fs.val.lport = cpu_to_be16(sport);
2580         f->fs.mask.lport  = ~0;
2581         val = (u8 *)&sip;
2582         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2583                 for (i = 0; i < 4; i++) {
2584                         f->fs.val.lip[i] = val[i];
2585                         f->fs.mask.lip[i] = ~0;
2586                 }
2587                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2588                         f->fs.val.iport = port;
2589                         f->fs.mask.iport = mask;
2590                 }
2591         }
2592
2593         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2594                 f->fs.val.proto = IPPROTO_TCP;
2595                 f->fs.mask.proto = ~0;
2596         }
2597
2598         f->fs.dirsteer = 1;
2599         f->fs.iq = queue;
2600         /* Mark filter as locked */
2601         f->locked = 1;
2602         f->fs.rpttid = 1;
2603
2604         /* Save the actual tid. We need this to get the corresponding
2605          * filter entry structure in filter_rpl.
2606          */
2607         f->tid = stid + adap->tids.ftid_base;
2608         ret = set_filter_wr(adap, stid);
2609         if (ret) {
2610                 clear_filter(adap, f);
2611                 return ret;
2612         }
2613
2614         return 0;
2615 }
2616 EXPORT_SYMBOL(cxgb4_create_server_filter);
2617
2618 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2619                 unsigned int queue, bool ipv6)
2620 {
2621         struct filter_entry *f;
2622         struct adapter *adap;
2623
2624         adap = netdev2adap(dev);
2625
2626         /* Adjust stid to correct filter index */
2627         stid -= adap->tids.sftid_base;
2628         stid += adap->tids.nftids;
2629
2630         f = &adap->tids.ftid_tab[stid];
2631         /* Unlock the filter */
2632         f->locked = 0;
2633
2634         return delete_filter(adap, stid);
2635 }
2636 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2637
2638 static void cxgb_get_stats(struct net_device *dev,
2639                            struct rtnl_link_stats64 *ns)
2640 {
2641         struct port_stats stats;
2642         struct port_info *p = netdev_priv(dev);
2643         struct adapter *adapter = p->adapter;
2644
2645         /* Block retrieving statistics during EEH error
2646          * recovery. Otherwise, the recovery might fail
2647          * and the PCI device will be removed permanently
2648          */
2649         spin_lock(&adapter->stats_lock);
2650         if (!netif_device_present(dev)) {
2651                 spin_unlock(&adapter->stats_lock);
2652                 return;
2653         }
2654         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2655                                  &p->stats_base);
2656         spin_unlock(&adapter->stats_lock);
2657
2658         ns->tx_bytes   = stats.tx_octets;
2659         ns->tx_packets = stats.tx_frames;
2660         ns->rx_bytes   = stats.rx_octets;
2661         ns->rx_packets = stats.rx_frames;
2662         ns->multicast  = stats.rx_mcast_frames;
2663
2664         /* detailed rx_errors */
2665         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2666                                stats.rx_runt;
2667         ns->rx_over_errors   = 0;
2668         ns->rx_crc_errors    = stats.rx_fcs_err;
2669         ns->rx_frame_errors  = stats.rx_symbol_err;
2670         ns->rx_dropped       = stats.rx_ovflow0 + stats.rx_ovflow1 +
2671                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2672                                stats.rx_trunc0 + stats.rx_trunc1 +
2673                                stats.rx_trunc2 + stats.rx_trunc3;
2674         ns->rx_missed_errors = 0;
2675
2676         /* detailed tx_errors */
2677         ns->tx_aborted_errors   = 0;
2678         ns->tx_carrier_errors   = 0;
2679         ns->tx_fifo_errors      = 0;
2680         ns->tx_heartbeat_errors = 0;
2681         ns->tx_window_errors    = 0;
2682
2683         ns->tx_errors = stats.tx_error_frames;
2684         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2685                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2686 }
2687
2688 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2689 {
2690         unsigned int mbox;
2691         int ret = 0, prtad, devad;
2692         struct port_info *pi = netdev_priv(dev);
2693         struct adapter *adapter = pi->adapter;
2694         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2695
2696         switch (cmd) {
2697         case SIOCGMIIPHY:
2698                 if (pi->mdio_addr < 0)
2699                         return -EOPNOTSUPP;
2700                 data->phy_id = pi->mdio_addr;
2701                 break;
2702         case SIOCGMIIREG:
2703         case SIOCSMIIREG:
2704                 if (mdio_phy_id_is_c45(data->phy_id)) {
2705                         prtad = mdio_phy_id_prtad(data->phy_id);
2706                         devad = mdio_phy_id_devad(data->phy_id);
2707                 } else if (data->phy_id < 32) {
2708                         prtad = data->phy_id;
2709                         devad = 0;
2710                         data->reg_num &= 0x1f;
2711                 } else
2712                         return -EINVAL;
2713
2714                 mbox = pi->adapter->pf;
2715                 if (cmd == SIOCGMIIREG)
2716                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2717                                          data->reg_num, &data->val_out);
2718                 else
2719                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2720                                          data->reg_num, data->val_in);
2721                 break;
2722         case SIOCGHWTSTAMP:
2723                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2724                                     sizeof(pi->tstamp_config)) ?
2725                         -EFAULT : 0;
2726         case SIOCSHWTSTAMP:
2727                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2728                                    sizeof(pi->tstamp_config)))
2729                         return -EFAULT;
2730
2731                 if (!is_t4(adapter->params.chip)) {
2732                         switch (pi->tstamp_config.tx_type) {
2733                         case HWTSTAMP_TX_OFF:
2734                         case HWTSTAMP_TX_ON:
2735                                 break;
2736                         default:
2737                                 return -ERANGE;
2738                         }
2739
2740                         switch (pi->tstamp_config.rx_filter) {
2741                         case HWTSTAMP_FILTER_NONE:
2742                                 pi->rxtstamp = false;
2743                                 break;
2744                         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2745                         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2746                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2747                                                          PTP_TS_L4);
2748                                 break;
2749                         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2750                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2751                                                          PTP_TS_L2_L4);
2752                                 break;
2753                         case HWTSTAMP_FILTER_ALL:
2754                         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2755                         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2756                         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2757                         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2758                                 pi->rxtstamp = true;
2759                                 break;
2760                         default:
2761                                 pi->tstamp_config.rx_filter =
2762                                         HWTSTAMP_FILTER_NONE;
2763                                 return -ERANGE;
2764                         }
2765
2766                         if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2767                             (pi->tstamp_config.rx_filter ==
2768                                 HWTSTAMP_FILTER_NONE)) {
2769                                 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2770                                         pi->ptp_enable = false;
2771                         }
2772
2773                         if (pi->tstamp_config.rx_filter !=
2774                                 HWTSTAMP_FILTER_NONE) {
2775                                 if (cxgb4_ptp_redirect_rx_packet(adapter,
2776                                                                  pi) >= 0)
2777                                         pi->ptp_enable = true;
2778                         }
2779                 } else {
2780                         /* For T4 Adapters */
2781                         switch (pi->tstamp_config.rx_filter) {
2782                         case HWTSTAMP_FILTER_NONE:
2783                         pi->rxtstamp = false;
2784                         break;
2785                         case HWTSTAMP_FILTER_ALL:
2786                         pi->rxtstamp = true;
2787                         break;
2788                         default:
2789                         pi->tstamp_config.rx_filter =
2790                         HWTSTAMP_FILTER_NONE;
2791                         return -ERANGE;
2792                         }
2793                 }
2794                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2795                                     sizeof(pi->tstamp_config)) ?
2796                         -EFAULT : 0;
2797         default:
2798                 return -EOPNOTSUPP;
2799         }
2800         return ret;
2801 }
2802
2803 static void cxgb_set_rxmode(struct net_device *dev)
2804 {
2805         /* unfortunately we can't return errors to the stack */
2806         set_rxmode(dev, -1, false);
2807 }
2808
2809 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2810 {
2811         int ret;
2812         struct port_info *pi = netdev_priv(dev);
2813
2814         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2815                             -1, -1, -1, true);
2816         if (!ret)
2817                 dev->mtu = new_mtu;
2818         return ret;
2819 }
2820
2821 #ifdef CONFIG_PCI_IOV
2822 static int cxgb4_mgmt_open(struct net_device *dev)
2823 {
2824         /* Turn carrier off since we don't have to transmit anything on this
2825          * interface.
2826          */
2827         netif_carrier_off(dev);
2828         return 0;
2829 }
2830
2831 /* Fill MAC address that will be assigned by the FW */
2832 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2833 {
2834         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2835         unsigned int i, vf, nvfs;
2836         u16 a, b;
2837         int err;
2838         u8 *na;
2839
2840         adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2841                                                             PCI_CAP_ID_VPD);
2842         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2843         if (err)
2844                 return;
2845
2846         na = adap->params.vpd.na;
2847         for (i = 0; i < ETH_ALEN; i++)
2848                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2849                               hex2val(na[2 * i + 1]));
2850
2851         a = (hw_addr[0] << 8) | hw_addr[1];
2852         b = (hw_addr[1] << 8) | hw_addr[2];
2853         a ^= b;
2854         a |= 0x0200;    /* locally assigned Ethernet MAC address */
2855         a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2856         macaddr[0] = a >> 8;
2857         macaddr[1] = a & 0xff;
2858
2859         for (i = 2; i < 5; i++)
2860                 macaddr[i] = hw_addr[i + 1];
2861
2862         for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2863                 vf < nvfs; vf++) {
2864                 macaddr[5] = adap->pf * nvfs + vf;
2865                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2866         }
2867 }
2868
2869 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2870 {
2871         struct port_info *pi = netdev_priv(dev);
2872         struct adapter *adap = pi->adapter;
2873         int ret;
2874
2875         /* verify MAC addr is valid */
2876         if (!is_valid_ether_addr(mac)) {
2877                 dev_err(pi->adapter->pdev_dev,
2878                         "Invalid Ethernet address %pM for VF %d\n",
2879                         mac, vf);
2880                 return -EINVAL;
2881         }
2882
2883         dev_info(pi->adapter->pdev_dev,
2884                  "Setting MAC %pM on VF %d\n", mac, vf);
2885         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2886         if (!ret)
2887                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2888         return ret;
2889 }
2890
2891 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2892                                     int vf, struct ifla_vf_info *ivi)
2893 {
2894         struct port_info *pi = netdev_priv(dev);
2895         struct adapter *adap = pi->adapter;
2896         struct vf_info *vfinfo;
2897
2898         if (vf >= adap->num_vfs)
2899                 return -EINVAL;
2900         vfinfo = &adap->vfinfo[vf];
2901
2902         ivi->vf = vf;
2903         ivi->max_tx_rate = vfinfo->tx_rate;
2904         ivi->min_tx_rate = 0;
2905         ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2906         ivi->vlan = vfinfo->vlan;
2907         ivi->linkstate = vfinfo->link_state;
2908         return 0;
2909 }
2910
2911 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2912                                        struct netdev_phys_item_id *ppid)
2913 {
2914         struct port_info *pi = netdev_priv(dev);
2915         unsigned int phy_port_id;
2916
2917         phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2918         ppid->id_len = sizeof(phy_port_id);
2919         memcpy(ppid->id, &phy_port_id, ppid->id_len);
2920         return 0;
2921 }
2922
2923 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2924                                   int min_tx_rate, int max_tx_rate)
2925 {
2926         struct port_info *pi = netdev_priv(dev);
2927         struct adapter *adap = pi->adapter;
2928         unsigned int link_ok, speed, mtu;
2929         u32 fw_pfvf, fw_class;
2930         int class_id = vf;
2931         int ret;
2932         u16 pktsize;
2933
2934         if (vf >= adap->num_vfs)
2935                 return -EINVAL;
2936
2937         if (min_tx_rate) {
2938                 dev_err(adap->pdev_dev,
2939                         "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2940                         min_tx_rate, vf);
2941                 return -EINVAL;
2942         }
2943
2944         if (max_tx_rate == 0) {
2945                 /* unbind VF to to any Traffic Class */
2946                 fw_pfvf =
2947                     (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2948                      FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2949                 fw_class = 0xffffffff;
2950                 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2951                                     &fw_pfvf, &fw_class);
2952                 if (ret) {
2953                         dev_err(adap->pdev_dev,
2954                                 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2955                                 ret, adap->pf, vf);
2956                         return -EINVAL;
2957                 }
2958                 dev_info(adap->pdev_dev,
2959                          "PF %d VF %d is unbound from TX Rate Limiting\n",
2960                          adap->pf, vf);
2961                 adap->vfinfo[vf].tx_rate = 0;
2962                 return 0;
2963         }
2964
2965         ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2966         if (ret != FW_SUCCESS) {
2967                 dev_err(adap->pdev_dev,
2968                         "Failed to get link information for VF %d\n", vf);
2969                 return -EINVAL;
2970         }
2971
2972         if (!link_ok) {
2973                 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2974                 return -EINVAL;
2975         }
2976
2977         if (max_tx_rate > speed) {
2978                 dev_err(adap->pdev_dev,
2979                         "Max tx rate %d for VF %d can't be > link-speed %u",
2980                         max_tx_rate, vf, speed);
2981                 return -EINVAL;
2982         }
2983
2984         pktsize = mtu;
2985         /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2986         pktsize = pktsize - sizeof(struct ethhdr) - 4;
2987         /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2988         pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2989         /* configure Traffic Class for rate-limiting */
2990         ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2991                               SCHED_CLASS_LEVEL_CL_RL,
2992                               SCHED_CLASS_MODE_CLASS,
2993                               SCHED_CLASS_RATEUNIT_BITS,
2994                               SCHED_CLASS_RATEMODE_ABS,
2995                               pi->tx_chan, class_id, 0,
2996                               max_tx_rate * 1000, 0, pktsize);
2997         if (ret) {
2998                 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2999                         ret);
3000                 return -EINVAL;
3001         }
3002         dev_info(adap->pdev_dev,
3003                  "Class %d with MSS %u configured with rate %u\n",
3004                  class_id, pktsize, max_tx_rate);
3005
3006         /* bind VF to configured Traffic Class */
3007         fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
3008                    FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
3009         fw_class = class_id;
3010         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
3011                             &fw_class);
3012         if (ret) {
3013                 dev_err(adap->pdev_dev,
3014                         "Err %d in binding PF %d VF %d to Traffic Class %d\n",
3015                         ret, adap->pf, vf, class_id);
3016                 return -EINVAL;
3017         }
3018         dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
3019                  adap->pf, vf, class_id);
3020         adap->vfinfo[vf].tx_rate = max_tx_rate;
3021         return 0;
3022 }
3023
3024 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
3025                                   u16 vlan, u8 qos, __be16 vlan_proto)
3026 {
3027         struct port_info *pi = netdev_priv(dev);
3028         struct adapter *adap = pi->adapter;
3029         int ret;
3030
3031         if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
3032                 return -EINVAL;
3033
3034         if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
3035                 return -EPROTONOSUPPORT;
3036
3037         ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
3038         if (!ret) {
3039                 adap->vfinfo[vf].vlan = vlan;
3040                 return 0;
3041         }
3042
3043         dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
3044                 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
3045         return ret;
3046 }
3047
3048 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
3049                                         int link)
3050 {
3051         struct port_info *pi = netdev_priv(dev);
3052         struct adapter *adap = pi->adapter;
3053         u32 param, val;
3054         int ret = 0;
3055
3056         if (vf >= adap->num_vfs)
3057                 return -EINVAL;
3058
3059         switch (link) {
3060         case IFLA_VF_LINK_STATE_AUTO:
3061                 val = FW_VF_LINK_STATE_AUTO;
3062                 break;
3063
3064         case IFLA_VF_LINK_STATE_ENABLE:
3065                 val = FW_VF_LINK_STATE_ENABLE;
3066                 break;
3067
3068         case IFLA_VF_LINK_STATE_DISABLE:
3069                 val = FW_VF_LINK_STATE_DISABLE;
3070                 break;
3071
3072         default:
3073                 return -EINVAL;
3074         }
3075
3076         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
3077                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
3078         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
3079                             &param, &val);
3080         if (ret) {
3081                 dev_err(adap->pdev_dev,
3082                         "Error %d in setting PF %d VF %d link state\n",
3083                         ret, adap->pf, vf);
3084                 return -EINVAL;
3085         }
3086
3087         adap->vfinfo[vf].link_state = link;
3088         return ret;
3089 }
3090 #endif /* CONFIG_PCI_IOV */
3091
3092 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3093 {
3094         int ret;
3095         struct sockaddr *addr = p;
3096         struct port_info *pi = netdev_priv(dev);
3097
3098         if (!is_valid_ether_addr(addr->sa_data))
3099                 return -EADDRNOTAVAIL;
3100
3101         ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
3102                                     addr->sa_data, true, &pi->smt_idx);
3103         if (ret < 0)
3104                 return ret;
3105
3106         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3107         pi->xact_addr_filt = ret;
3108         return 0;
3109 }
3110
3111 #ifdef CONFIG_NET_POLL_CONTROLLER
3112 static void cxgb_netpoll(struct net_device *dev)
3113 {
3114         struct port_info *pi = netdev_priv(dev);
3115         struct adapter *adap = pi->adapter;
3116
3117         if (adap->flags & CXGB4_USING_MSIX) {
3118                 int i;
3119                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3120
3121                 for (i = pi->nqsets; i; i--, rx++)
3122                         t4_sge_intr_msix(0, &rx->rspq);
3123         } else
3124                 t4_intr_handler(adap)(0, adap);
3125 }
3126 #endif
3127
3128 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
3129 {
3130         struct port_info *pi = netdev_priv(dev);
3131         struct adapter *adap = pi->adapter;
3132         struct sched_class *e;
3133         struct ch_sched_params p;
3134         struct ch_sched_queue qe;
3135         u32 req_rate;
3136         int err = 0;
3137
3138         if (!can_sched(dev))
3139                 return -ENOTSUPP;
3140
3141         if (index < 0 || index > pi->nqsets - 1)
3142                 return -EINVAL;
3143
3144         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3145                 dev_err(adap->pdev_dev,
3146                         "Failed to rate limit on queue %d. Link Down?\n",
3147                         index);
3148                 return -EINVAL;
3149         }
3150
3151         /* Convert from Mbps to Kbps */
3152         req_rate = rate * 1000;
3153
3154         /* Max rate is 100 Gbps */
3155         if (req_rate > SCHED_MAX_RATE_KBPS) {
3156                 dev_err(adap->pdev_dev,
3157                         "Invalid rate %u Mbps, Max rate is %u Mbps\n",
3158                         rate, SCHED_MAX_RATE_KBPS / 1000);
3159                 return -ERANGE;
3160         }
3161
3162         /* First unbind the queue from any existing class */
3163         memset(&qe, 0, sizeof(qe));
3164         qe.queue = index;
3165         qe.class = SCHED_CLS_NONE;
3166
3167         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3168         if (err) {
3169                 dev_err(adap->pdev_dev,
3170                         "Unbinding Queue %d on port %d fail. Err: %d\n",
3171                         index, pi->port_id, err);
3172                 return err;
3173         }
3174
3175         /* Queue already unbound */
3176         if (!req_rate)
3177                 return 0;
3178
3179         /* Fetch any available unused or matching scheduling class */
3180         memset(&p, 0, sizeof(p));
3181         p.type = SCHED_CLASS_TYPE_PACKET;
3182         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
3183         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
3184         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3185         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3186         p.u.params.channel  = pi->tx_chan;
3187         p.u.params.class    = SCHED_CLS_NONE;
3188         p.u.params.minrate  = 0;
3189         p.u.params.maxrate  = req_rate;
3190         p.u.params.weight   = 0;
3191         p.u.params.pktsize  = dev->mtu;
3192
3193         e = cxgb4_sched_class_alloc(dev, &p);
3194         if (!e)
3195                 return -ENOMEM;
3196
3197         /* Bind the queue to a scheduling class */
3198         memset(&qe, 0, sizeof(qe));
3199         qe.queue = index;
3200         qe.class = e->idx;
3201
3202         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3203         if (err)
3204                 dev_err(adap->pdev_dev,
3205                         "Queue rate limiting failed. Err: %d\n", err);
3206         return err;
3207 }
3208
3209 static int cxgb_setup_tc_flower(struct net_device *dev,
3210                                 struct flow_cls_offload *cls_flower)
3211 {
3212         switch (cls_flower->command) {
3213         case FLOW_CLS_REPLACE:
3214                 return cxgb4_tc_flower_replace(dev, cls_flower);
3215         case FLOW_CLS_DESTROY:
3216                 return cxgb4_tc_flower_destroy(dev, cls_flower);
3217         case FLOW_CLS_STATS:
3218                 return cxgb4_tc_flower_stats(dev, cls_flower);
3219         default:
3220                 return -EOPNOTSUPP;
3221         }
3222 }
3223
3224 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
3225                                  struct tc_cls_u32_offload *cls_u32)
3226 {
3227         switch (cls_u32->command) {
3228         case TC_CLSU32_NEW_KNODE:
3229         case TC_CLSU32_REPLACE_KNODE:
3230                 return cxgb4_config_knode(dev, cls_u32);
3231         case TC_CLSU32_DELETE_KNODE:
3232                 return cxgb4_delete_knode(dev, cls_u32);
3233         default:
3234                 return -EOPNOTSUPP;
3235         }
3236 }
3237
3238 static int cxgb_setup_tc_matchall(struct net_device *dev,
3239                                   struct tc_cls_matchall_offload *cls_matchall)
3240 {
3241         struct adapter *adap = netdev2adap(dev);
3242
3243         if (!adap->tc_matchall)
3244                 return -ENOMEM;
3245
3246         switch (cls_matchall->command) {
3247         case TC_CLSMATCHALL_REPLACE:
3248                 return cxgb4_tc_matchall_replace(dev, cls_matchall);
3249         case TC_CLSMATCHALL_DESTROY:
3250                 return cxgb4_tc_matchall_destroy(dev, cls_matchall);
3251         default:
3252                 break;
3253         }
3254
3255         return -EOPNOTSUPP;
3256 }
3257
3258 static int cxgb_setup_tc_block_ingress_cb(enum tc_setup_type type,
3259                                           void *type_data, void *cb_priv)
3260 {
3261         struct net_device *dev = cb_priv;
3262         struct port_info *pi = netdev2pinfo(dev);
3263         struct adapter *adap = netdev2adap(dev);
3264
3265         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3266                 dev_err(adap->pdev_dev,
3267                         "Failed to setup tc on port %d. Link Down?\n",
3268                         pi->port_id);
3269                 return -EINVAL;
3270         }
3271
3272         if (!tc_cls_can_offload_and_chain0(dev, type_data))
3273                 return -EOPNOTSUPP;
3274
3275         switch (type) {
3276         case TC_SETUP_CLSU32:
3277                 return cxgb_setup_tc_cls_u32(dev, type_data);
3278         case TC_SETUP_CLSFLOWER:
3279                 return cxgb_setup_tc_flower(dev, type_data);
3280         default:
3281                 return -EOPNOTSUPP;
3282         }
3283 }
3284
3285 static int cxgb_setup_tc_block_egress_cb(enum tc_setup_type type,
3286                                          void *type_data, void *cb_priv)
3287 {
3288         struct net_device *dev = cb_priv;
3289         struct port_info *pi = netdev2pinfo(dev);
3290         struct adapter *adap = netdev2adap(dev);
3291
3292         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3293                 dev_err(adap->pdev_dev,
3294                         "Failed to setup tc on port %d. Link Down?\n",
3295                         pi->port_id);
3296                 return -EINVAL;
3297         }
3298
3299         if (!tc_cls_can_offload_and_chain0(dev, type_data))
3300                 return -EOPNOTSUPP;
3301
3302         switch (type) {
3303         case TC_SETUP_CLSMATCHALL:
3304                 return cxgb_setup_tc_matchall(dev, type_data);
3305         default:
3306                 break;
3307         }
3308
3309         return -EOPNOTSUPP;
3310 }
3311
3312 static int cxgb_setup_tc_mqprio(struct net_device *dev,
3313                                 struct tc_mqprio_qopt_offload *mqprio)
3314 {
3315         struct adapter *adap = netdev2adap(dev);
3316
3317         if (!is_ethofld(adap) || !adap->tc_mqprio)
3318                 return -ENOMEM;
3319
3320         return cxgb4_setup_tc_mqprio(dev, mqprio);
3321 }
3322
3323 static LIST_HEAD(cxgb_block_cb_list);
3324
3325 static int cxgb_setup_tc_block(struct net_device *dev,
3326                                struct flow_block_offload *f)
3327 {
3328         struct port_info *pi = netdev_priv(dev);
3329         flow_setup_cb_t *cb;
3330         bool ingress_only;
3331
3332         pi->tc_block_shared = f->block_shared;
3333         if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
3334                 cb = cxgb_setup_tc_block_egress_cb;
3335                 ingress_only = false;
3336         } else {
3337                 cb = cxgb_setup_tc_block_ingress_cb;
3338                 ingress_only = true;
3339         }
3340
3341         return flow_block_cb_setup_simple(f, &cxgb_block_cb_list,
3342                                           cb, pi, dev, ingress_only);
3343 }
3344
3345 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3346                          void *type_data)
3347 {
3348         switch (type) {
3349         case TC_SETUP_QDISC_MQPRIO:
3350                 return cxgb_setup_tc_mqprio(dev, type_data);
3351         case TC_SETUP_BLOCK:
3352                 return cxgb_setup_tc_block(dev, type_data);
3353         default:
3354                 return -EOPNOTSUPP;
3355         }
3356 }
3357
3358 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3359                                 struct udp_tunnel_info *ti)
3360 {
3361         struct port_info *pi = netdev_priv(netdev);
3362         struct adapter *adapter = pi->adapter;
3363         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3364         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3365         int ret = 0, i;
3366
3367         if (chip_ver < CHELSIO_T6)
3368                 return;
3369
3370         switch (ti->type) {
3371         case UDP_TUNNEL_TYPE_VXLAN:
3372                 if (!adapter->vxlan_port_cnt ||
3373                     adapter->vxlan_port != ti->port)
3374                         return; /* Invalid VxLAN destination port */
3375
3376                 adapter->vxlan_port_cnt--;
3377                 if (adapter->vxlan_port_cnt)
3378                         return;
3379
3380                 adapter->vxlan_port = 0;
3381                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3382                 break;
3383         case UDP_TUNNEL_TYPE_GENEVE:
3384                 if (!adapter->geneve_port_cnt ||
3385                     adapter->geneve_port != ti->port)
3386                         return; /* Invalid GENEVE destination port */
3387
3388                 adapter->geneve_port_cnt--;
3389                 if (adapter->geneve_port_cnt)
3390                         return;
3391
3392                 adapter->geneve_port = 0;
3393                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
3394                 break;
3395         default:
3396                 return;
3397         }
3398
3399         /* Matchall mac entries can be deleted only after all tunnel ports
3400          * are brought down or removed.
3401          */
3402         if (!adapter->rawf_cnt)
3403                 return;
3404         for_each_port(adapter, i) {
3405                 pi = adap2pinfo(adapter, i);
3406                 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3407                                            match_all_mac, match_all_mac,
3408                                            adapter->rawf_start +
3409                                             pi->port_id,
3410                                            1, pi->port_id, false);
3411                 if (ret < 0) {
3412                         netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3413                                     i);
3414                         return;
3415                 }
3416         }
3417 }
3418
3419 static void cxgb_add_udp_tunnel(struct net_device *netdev,
3420                                 struct udp_tunnel_info *ti)
3421 {
3422         struct port_info *pi = netdev_priv(netdev);
3423         struct adapter *adapter = pi->adapter;
3424         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3425         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3426         int i, ret;
3427
3428         if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
3429                 return;
3430
3431         switch (ti->type) {
3432         case UDP_TUNNEL_TYPE_VXLAN:
3433                 /* Callback for adding vxlan port can be called with the same
3434                  * port for both IPv4 and IPv6. We should not disable the
3435                  * offloading when the same port for both protocols is added
3436                  * and later one of them is removed.
3437                  */
3438                 if (adapter->vxlan_port_cnt &&
3439                     adapter->vxlan_port == ti->port) {
3440                         adapter->vxlan_port_cnt++;
3441                         return;
3442                 }
3443
3444                 /* We will support only one VxLAN port */
3445                 if (adapter->vxlan_port_cnt) {
3446                         netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3447                                     be16_to_cpu(adapter->vxlan_port),
3448                                     be16_to_cpu(ti->port));
3449                         return;
3450                 }
3451
3452                 adapter->vxlan_port = ti->port;
3453                 adapter->vxlan_port_cnt = 1;
3454
3455                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3456                              VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3457                 break;
3458         case UDP_TUNNEL_TYPE_GENEVE:
3459                 if (adapter->geneve_port_cnt &&
3460                     adapter->geneve_port == ti->port) {
3461                         adapter->geneve_port_cnt++;
3462                         return;
3463                 }
3464
3465                 /* We will support only one GENEVE port */
3466                 if (adapter->geneve_port_cnt) {
3467                         netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3468                                     be16_to_cpu(adapter->geneve_port),
3469                                     be16_to_cpu(ti->port));
3470                         return;
3471                 }
3472
3473                 adapter->geneve_port = ti->port;
3474                 adapter->geneve_port_cnt = 1;
3475
3476                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3477                              GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
3478                 break;
3479         default:
3480                 return;
3481         }
3482
3483         /* Create a 'match all' mac filter entry for inner mac,
3484          * if raw mac interface is supported. Once the linux kernel provides
3485          * driver entry points for adding/deleting the inner mac addresses,
3486          * we will remove this 'match all' entry and fallback to adding
3487          * exact match filters.
3488          */
3489         for_each_port(adapter, i) {
3490                 pi = adap2pinfo(adapter, i);
3491
3492                 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3493                                             match_all_mac,
3494                                             match_all_mac,
3495                                             adapter->rawf_start +
3496                                             pi->port_id,
3497                                             1, pi->port_id, false);
3498                 if (ret < 0) {
3499                         netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3500                                     be16_to_cpu(ti->port));
3501                         cxgb_del_udp_tunnel(netdev, ti);
3502                         return;
3503                 }
3504         }
3505 }
3506
3507 static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3508                                              struct net_device *dev,
3509                                              netdev_features_t features)
3510 {
3511         struct port_info *pi = netdev_priv(dev);
3512         struct adapter *adapter = pi->adapter;
3513
3514         if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3515                 return features;
3516
3517         /* Check if hw supports offload for this packet */
3518         if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3519                 return features;
3520
3521         /* Offload is not supported for this encapsulated packet */
3522         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3523 }
3524
3525 static netdev_features_t cxgb_fix_features(struct net_device *dev,
3526                                            netdev_features_t features)
3527 {
3528         /* Disable GRO, if RX_CSUM is disabled */
3529         if (!(features & NETIF_F_RXCSUM))
3530                 features &= ~NETIF_F_GRO;
3531
3532         return features;
3533 }
3534
3535 static const struct net_device_ops cxgb4_netdev_ops = {
3536         .ndo_open             = cxgb_open,
3537         .ndo_stop             = cxgb_close,
3538         .ndo_start_xmit       = t4_start_xmit,
3539         .ndo_select_queue     = cxgb_select_queue,
3540         .ndo_get_stats64      = cxgb_get_stats,
3541         .ndo_set_rx_mode      = cxgb_set_rxmode,
3542         .ndo_set_mac_address  = cxgb_set_mac_addr,
3543         .ndo_set_features     = cxgb_set_features,
3544         .ndo_validate_addr    = eth_validate_addr,
3545         .ndo_do_ioctl         = cxgb_ioctl,
3546         .ndo_change_mtu       = cxgb_change_mtu,
3547 #ifdef CONFIG_NET_POLL_CONTROLLER
3548         .ndo_poll_controller  = cxgb_netpoll,
3549 #endif
3550 #ifdef CONFIG_CHELSIO_T4_FCOE
3551         .ndo_fcoe_enable      = cxgb_fcoe_enable,
3552         .ndo_fcoe_disable     = cxgb_fcoe_disable,
3553 #endif /* CONFIG_CHELSIO_T4_FCOE */
3554         .ndo_set_tx_maxrate   = cxgb_set_tx_maxrate,
3555         .ndo_setup_tc         = cxgb_setup_tc,
3556         .ndo_udp_tunnel_add   = cxgb_add_udp_tunnel,
3557         .ndo_udp_tunnel_del   = cxgb_del_udp_tunnel,
3558         .ndo_features_check   = cxgb_features_check,
3559         .ndo_fix_features     = cxgb_fix_features,
3560 };
3561
3562 #ifdef CONFIG_PCI_IOV
3563 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
3564         .ndo_open               = cxgb4_mgmt_open,
3565         .ndo_set_vf_mac         = cxgb4_mgmt_set_vf_mac,
3566         .ndo_get_vf_config      = cxgb4_mgmt_get_vf_config,
3567         .ndo_set_vf_rate        = cxgb4_mgmt_set_vf_rate,
3568         .ndo_get_phys_port_id   = cxgb4_mgmt_get_phys_port_id,
3569         .ndo_set_vf_vlan        = cxgb4_mgmt_set_vf_vlan,
3570         .ndo_set_vf_link_state  = cxgb4_mgmt_set_vf_link_state,
3571 };
3572 #endif
3573
3574 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3575                                    struct ethtool_drvinfo *info)
3576 {
3577         struct adapter *adapter = netdev2adap(dev);
3578
3579         strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3580         strlcpy(info->version, cxgb4_driver_version,
3581                 sizeof(info->version));
3582         strlcpy(info->bus_info, pci_name(adapter->pdev),
3583                 sizeof(info->bus_info));
3584 }
3585
3586 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
3587         .get_drvinfo       = cxgb4_mgmt_get_drvinfo,
3588 };
3589
3590 static void notify_fatal_err(struct work_struct *work)
3591 {
3592         struct adapter *adap;
3593
3594         adap = container_of(work, struct adapter, fatal_err_notify_task);
3595         notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3596 }
3597
3598 void t4_fatal_err(struct adapter *adap)
3599 {
3600         int port;
3601
3602         if (pci_channel_offline(adap->pdev))
3603                 return;
3604
3605         /* Disable the SGE since ULDs are going to free resources that
3606          * could be exposed to the adapter.  RDMA MWs for example...
3607          */
3608         t4_shutdown_adapter(adap);
3609         for_each_port(adap, port) {
3610                 struct net_device *dev = adap->port[port];
3611
3612                 /* If we get here in very early initialization the network
3613                  * devices may not have been set up yet.
3614                  */
3615                 if (!dev)
3616                         continue;
3617
3618                 netif_tx_stop_all_queues(dev);
3619                 netif_carrier_off(dev);
3620         }
3621         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3622         queue_work(adap->workq, &adap->fatal_err_notify_task);
3623 }
3624
3625 static void setup_memwin(struct adapter *adap)
3626 {
3627         u32 nic_win_base = t4_get_util_window(adap);
3628
3629         t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3630 }
3631
3632 static void setup_memwin_rdma(struct adapter *adap)
3633 {
3634         if (adap->vres.ocq.size) {
3635                 u32 start;
3636                 unsigned int sz_kb;
3637
3638                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3639                 start &= PCI_BASE_ADDRESS_MEM_MASK;
3640                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3641                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3642                 t4_write_reg(adap,
3643                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3644                              start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3645                 t4_write_reg(adap,
3646                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3647                              adap->vres.ocq.start);
3648                 t4_read_reg(adap,
3649                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3650         }
3651 }
3652
3653 /* HMA Definitions */
3654
3655 /* The maximum number of address that can be send in a single FW cmd */
3656 #define HMA_MAX_ADDR_IN_CMD     5
3657
3658 #define HMA_PAGE_SIZE           PAGE_SIZE
3659
3660 #define HMA_MAX_NO_FW_ADDRESS   (16 << 10)  /* FW supports 16K addresses */
3661
3662 #define HMA_PAGE_ORDER                                  \
3663         ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ?      \
3664         ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3665
3666 /* The minimum and maximum possible HMA sizes that can be specified in the FW
3667  * configuration(in units of MB).
3668  */
3669 #define HMA_MIN_TOTAL_SIZE      1
3670 #define HMA_MAX_TOTAL_SIZE                              \
3671         (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) *           \
3672           HMA_MAX_NO_FW_ADDRESS) >> 20)
3673
3674 static void adap_free_hma_mem(struct adapter *adapter)
3675 {
3676         struct scatterlist *iter;
3677         struct page *page;
3678         int i;
3679
3680         if (!adapter->hma.sgt)
3681                 return;
3682
3683         if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3684                 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3685                              adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3686                 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3687         }
3688
3689         for_each_sg(adapter->hma.sgt->sgl, iter,
3690                     adapter->hma.sgt->orig_nents, i) {
3691                 page = sg_page(iter);
3692                 if (page)
3693                         __free_pages(page, HMA_PAGE_ORDER);
3694         }
3695
3696         kfree(adapter->hma.phy_addr);
3697         sg_free_table(adapter->hma.sgt);
3698         kfree(adapter->hma.sgt);
3699         adapter->hma.sgt = NULL;
3700 }
3701
3702 static int adap_config_hma(struct adapter *adapter)
3703 {
3704         struct scatterlist *sgl, *iter;
3705         struct sg_table *sgt;
3706         struct page *newpage;
3707         unsigned int i, j, k;
3708         u32 param, hma_size;
3709         unsigned int ncmds;
3710         size_t page_size;
3711         u32 page_order;
3712         int node, ret;
3713
3714         /* HMA is supported only for T6+ cards.
3715          * Avoid initializing HMA in kdump kernels.
3716          */
3717         if (is_kdump_kernel() ||
3718             CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3719                 return 0;
3720
3721         /* Get the HMA region size required by fw */
3722         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3723                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3724         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3725                               1, &param, &hma_size);
3726         /* An error means card has its own memory or HMA is not supported by
3727          * the firmware. Return without any errors.
3728          */
3729         if (ret || !hma_size)
3730                 return 0;
3731
3732         if (hma_size < HMA_MIN_TOTAL_SIZE ||
3733             hma_size > HMA_MAX_TOTAL_SIZE) {
3734                 dev_err(adapter->pdev_dev,
3735                         "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3736                         hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3737                 return -EINVAL;
3738         }
3739
3740         page_size = HMA_PAGE_SIZE;
3741         page_order = HMA_PAGE_ORDER;
3742         adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3743         if (unlikely(!adapter->hma.sgt)) {
3744                 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3745                 return -ENOMEM;
3746         }
3747         sgt = adapter->hma.sgt;
3748         /* FW returned value will be in MB's
3749          */
3750         sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3751         if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3752                 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3753                 kfree(adapter->hma.sgt);
3754                 adapter->hma.sgt = NULL;
3755                 return -ENOMEM;
3756         }
3757
3758         sgl = adapter->hma.sgt->sgl;
3759         node = dev_to_node(adapter->pdev_dev);
3760         for_each_sg(sgl, iter, sgt->orig_nents, i) {
3761                 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3762                                            __GFP_ZERO, page_order);
3763                 if (!newpage) {
3764                         dev_err(adapter->pdev_dev,
3765                                 "Not enough memory for HMA page allocation\n");
3766                         ret = -ENOMEM;
3767                         goto free_hma;
3768                 }
3769                 sg_set_page(iter, newpage, page_size << page_order, 0);
3770         }
3771
3772         sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3773                                 DMA_BIDIRECTIONAL);
3774         if (!sgt->nents) {
3775                 dev_err(adapter->pdev_dev,
3776                         "Not enough memory for HMA DMA mapping");
3777                 ret = -ENOMEM;
3778                 goto free_hma;
3779         }
3780         adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3781
3782         adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3783                                         GFP_KERNEL);
3784         if (unlikely(!adapter->hma.phy_addr))
3785                 goto free_hma;
3786
3787         for_each_sg(sgl, iter, sgt->nents, i) {
3788                 newpage = sg_page(iter);
3789                 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3790         }
3791
3792         ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3793         /* Pass on the addresses to firmware */
3794         for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3795                 struct fw_hma_cmd hma_cmd;
3796                 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3797                 u8 soc = 0, eoc = 0;
3798                 u8 hma_mode = 1; /* Presently we support only Page table mode */
3799
3800                 soc = (i == 0) ? 1 : 0;
3801                 eoc = (i == ncmds - 1) ? 1 : 0;
3802
3803                 /* For last cmd, set naddr corresponding to remaining
3804                  * addresses
3805                  */
3806                 if (i == ncmds - 1) {
3807                         naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3808                         naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3809                 }
3810                 memset(&hma_cmd, 0, sizeof(hma_cmd));
3811                 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3812                                        FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3813                 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3814
3815                 hma_cmd.mode_to_pcie_params =
3816                         htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3817                               FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3818
3819                 /* HMA cmd size specified in MB's */
3820                 hma_cmd.naddr_size =
3821                         htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3822                               FW_HMA_CMD_NADDR_V(naddr));
3823
3824                 /* Total Page size specified in units of 4K */
3825                 hma_cmd.addr_size_pkd =
3826                         htonl(FW_HMA_CMD_ADDR_SIZE_V
3827                                 ((page_size << page_order) >> 12));
3828
3829                 /* Fill the 5 addresses */
3830                 for (j = 0; j < naddr; j++) {
3831                         hma_cmd.phy_address[j] =
3832                                 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3833                 }
3834                 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3835                                  sizeof(hma_cmd), &hma_cmd);
3836                 if (ret) {
3837                         dev_err(adapter->pdev_dev,
3838                                 "HMA FW command failed with err %d\n", ret);
3839                         goto free_hma;
3840                 }
3841         }
3842
3843         if (!ret)
3844                 dev_info(adapter->pdev_dev,
3845                          "Reserved %uMB host memory for HMA\n", hma_size);
3846         return ret;
3847
3848 free_hma:
3849         adap_free_hma_mem(adapter);
3850         return ret;
3851 }
3852
3853 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3854 {
3855         u32 v;
3856         int ret;
3857
3858         /* Now that we've successfully configured and initialized the adapter
3859          * can ask the Firmware what resources it has provisioned for us.
3860          */
3861         ret = t4_get_pfres(adap);
3862         if (ret) {
3863                 dev_err(adap->pdev_dev,
3864                         "Unable to retrieve resource provisioning information\n");
3865                 return ret;
3866         }
3867
3868         /* get device capabilities */
3869         memset(c, 0, sizeof(*c));
3870         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3871                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
3872         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3873         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3874         if (ret < 0)
3875                 return ret;
3876
3877         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3878                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3879         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3880         if (ret < 0)
3881                 return ret;
3882
3883         ret = t4_config_glbl_rss(adap, adap->pf,
3884                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3885                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3886                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3887         if (ret < 0)
3888                 return ret;
3889
3890         ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3891                           MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3892                           FW_CMD_CAP_PF);
3893         if (ret < 0)
3894                 return ret;
3895
3896         t4_sge_init(adap);
3897
3898         /* tweak some settings */
3899         t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3900         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3901         t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3902         v = t4_read_reg(adap, TP_PIO_DATA_A);
3903         t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3904
3905         /* first 4 Tx modulation queues point to consecutive Tx channels */
3906         adap->params.tp.tx_modq_map = 0xE4;
3907         t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3908                      TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3909
3910         /* associate each Tx modulation queue with consecutive Tx channels */
3911         v = 0x84218421;
3912         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3913                           &v, 1, TP_TX_SCHED_HDR_A);
3914         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3915                           &v, 1, TP_TX_SCHED_FIFO_A);
3916         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3917                           &v, 1, TP_TX_SCHED_PCMD_A);
3918
3919 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3920         if (is_offload(adap)) {
3921                 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3922                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3923                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3924                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3925                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3926                 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3927                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3928                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3929                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3930                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3931         }
3932
3933         /* get basic stuff going */
3934         return t4_early_init(adap, adap->pf);
3935 }
3936
3937 /*
3938  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
3939  */
3940 #define MAX_ATIDS 8192U
3941
3942 /*
3943  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3944  *
3945  * If the firmware we're dealing with has Configuration File support, then
3946  * we use that to perform all configuration
3947  */
3948
3949 /*
3950  * Tweak configuration based on module parameters, etc.  Most of these have
3951  * defaults assigned to them by Firmware Configuration Files (if we're using
3952  * them) but need to be explicitly set if we're using hard-coded
3953  * initialization.  But even in the case of using Firmware Configuration
3954  * Files, we'd like to expose the ability to change these via module
3955  * parameters so these are essentially common tweaks/settings for
3956  * Configuration Files and hard-coded initialization ...
3957  */
3958 static int adap_init0_tweaks(struct adapter *adapter)
3959 {
3960         /*
3961          * Fix up various Host-Dependent Parameters like Page Size, Cache
3962          * Line Size, etc.  The firmware default is for a 4KB Page Size and
3963          * 64B Cache Line Size ...
3964          */
3965         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3966
3967         /*
3968          * Process module parameters which affect early initialization.
3969          */
3970         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3971                 dev_err(&adapter->pdev->dev,
3972                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
3973                         rx_dma_offset);
3974                 rx_dma_offset = 2;
3975         }
3976         t4_set_reg_field(adapter, SGE_CONTROL_A,
3977                          PKTSHIFT_V(PKTSHIFT_M),
3978                          PKTSHIFT_V(rx_dma_offset));
3979
3980         /*
3981          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3982          * adds the pseudo header itself.
3983          */
3984         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3985                                CSUM_HAS_PSEUDO_HDR_F, 0);
3986
3987         return 0;
3988 }
3989
3990 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3991  * unto themselves and they contain their own firmware to perform their
3992  * tasks ...
3993  */
3994 static int phy_aq1202_version(const u8 *phy_fw_data,
3995                               size_t phy_fw_size)
3996 {
3997         int offset;
3998
3999         /* At offset 0x8 you're looking for the primary image's
4000          * starting offset which is 3 Bytes wide
4001          *
4002          * At offset 0xa of the primary image, you look for the offset
4003          * of the DRAM segment which is 3 Bytes wide.
4004          *
4005          * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
4006          * wide
4007          */
4008         #define be16(__p) (((__p)[0] << 8) | (__p)[1])
4009         #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
4010         #define le24(__p) (le16(__p) | ((__p)[2] << 16))
4011
4012         offset = le24(phy_fw_data + 0x8) << 12;
4013         offset = le24(phy_fw_data + offset + 0xa);
4014         return be16(phy_fw_data + offset + 0x27e);
4015
4016         #undef be16
4017         #undef le16
4018         #undef le24
4019 }
4020
4021 static struct info_10gbt_phy_fw {
4022         unsigned int phy_fw_id;         /* PCI Device ID */
4023         char *phy_fw_file;              /* /lib/firmware/ PHY Firmware file */
4024         int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
4025         int phy_flash;                  /* Has FLASH for PHY Firmware */
4026 } phy_info_array[] = {
4027         {
4028                 PHY_AQ1202_DEVICEID,
4029                 PHY_AQ1202_FIRMWARE,
4030                 phy_aq1202_version,
4031                 1,
4032         },
4033         {
4034                 PHY_BCM84834_DEVICEID,
4035                 PHY_BCM84834_FIRMWARE,
4036                 NULL,
4037                 0,
4038         },
4039         { 0, NULL, NULL },
4040 };
4041
4042 static struct info_10gbt_phy_fw *find_phy_info(int devid)
4043 {
4044         int i;
4045
4046         for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
4047                 if (phy_info_array[i].phy_fw_id == devid)
4048                         return &phy_info_array[i];
4049         }
4050         return NULL;
4051 }
4052
4053 /* Handle updating of chip-external 10Gb/s-BT PHY firmware.  This needs to
4054  * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD.  On error
4055  * we return a negative error number.  If we transfer new firmware we return 1
4056  * (from t4_load_phy_fw()).  If we don't do anything we return 0.
4057  */
4058 static int adap_init0_phy(struct adapter *adap)
4059 {
4060         const struct firmware *phyf;
4061         int ret;
4062         struct info_10gbt_phy_fw *phy_info;
4063
4064         /* Use the device ID to determine which PHY file to flash.
4065          */
4066         phy_info = find_phy_info(adap->pdev->device);
4067         if (!phy_info) {
4068                 dev_warn(adap->pdev_dev,
4069                          "No PHY Firmware file found for this PHY\n");
4070                 return -EOPNOTSUPP;
4071         }
4072
4073         /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
4074          * use that. The adapter firmware provides us with a memory buffer
4075          * where we can load a PHY firmware file from the host if we want to
4076          * override the PHY firmware File in flash.
4077          */
4078         ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
4079                                       adap->pdev_dev);
4080         if (ret < 0) {
4081                 /* For adapters without FLASH attached to PHY for their
4082                  * firmware, it's obviously a fatal error if we can't get the
4083                  * firmware to the adapter.  For adapters with PHY firmware
4084                  * FLASH storage, it's worth a warning if we can't find the
4085                  * PHY Firmware but we'll neuter the error ...
4086                  */
4087                 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
4088                         "/lib/firmware/%s, error %d\n",
4089                         phy_info->phy_fw_file, -ret);
4090                 if (phy_info->phy_flash) {
4091                         int cur_phy_fw_ver = 0;
4092
4093                         t4_phy_fw_ver(adap, &cur_phy_fw_ver);
4094                         dev_warn(adap->pdev_dev, "continuing with, on-adapter "
4095                                  "FLASH copy, version %#x\n", cur_phy_fw_ver);
4096                         ret = 0;
4097                 }
4098
4099                 return ret;
4100         }
4101
4102         /* Load PHY Firmware onto adapter.
4103          */
4104         ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
4105                              phy_info->phy_fw_version,
4106                              (u8 *)phyf->data, phyf->size);
4107         if (ret < 0)
4108                 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
4109                         -ret);
4110         else if (ret > 0) {
4111                 int new_phy_fw_ver = 0;
4112
4113                 if (phy_info->phy_fw_version)
4114                         new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
4115                                                                   phyf->size);
4116                 dev_info(adap->pdev_dev, "Successfully transferred PHY "
4117                          "Firmware /lib/firmware/%s, version %#x\n",
4118                          phy_info->phy_fw_file, new_phy_fw_ver);
4119         }
4120
4121         release_firmware(phyf);
4122
4123         return ret;
4124 }
4125
4126 /*
4127  * Attempt to initialize the adapter via a Firmware Configuration File.
4128  */
4129 static int adap_init0_config(struct adapter *adapter, int reset)
4130 {
4131         char *fw_config_file, fw_config_file_path[256];
4132         u32 finiver, finicsum, cfcsum, param, val;
4133         struct fw_caps_config_cmd caps_cmd;
4134         unsigned long mtype = 0, maddr = 0;
4135         const struct firmware *cf;
4136         char *config_name = NULL;
4137         int config_issued = 0;
4138         int ret;
4139
4140         /*
4141          * Reset device if necessary.
4142          */
4143         if (reset) {
4144                 ret = t4_fw_reset(adapter, adapter->mbox,
4145                                   PIORSTMODE_F | PIORST_F);
4146                 if (ret < 0)
4147                         goto bye;
4148         }
4149
4150         /* If this is a 10Gb/s-BT adapter make sure the chip-external
4151          * 10Gb/s-BT PHYs have up-to-date firmware.  Note that this step needs
4152          * to be performed after any global adapter RESET above since some
4153          * PHYs only have local RAM copies of the PHY firmware.
4154          */
4155         if (is_10gbt_device(adapter->pdev->device)) {
4156                 ret = adap_init0_phy(adapter);
4157                 if (ret < 0)
4158                         goto bye;
4159         }
4160         /*
4161          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
4162          * then use that.  Otherwise, use the configuration file stored
4163          * in the adapter flash ...
4164          */
4165         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
4166         case CHELSIO_T4:
4167                 fw_config_file = FW4_CFNAME;
4168                 break;
4169         case CHELSIO_T5:
4170                 fw_config_file = FW5_CFNAME;
4171                 break;
4172         case CHELSIO_T6:
4173                 fw_config_file = FW6_CFNAME;
4174                 break;
4175         default:
4176                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
4177                        adapter->pdev->device);
4178                 ret = -EINVAL;
4179                 goto bye;
4180         }
4181
4182         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
4183         if (ret < 0) {
4184                 config_name = "On FLASH";
4185                 mtype = FW_MEMTYPE_CF_FLASH;
4186                 maddr = t4_flash_cfg_addr(adapter);
4187         } else {
4188                 u32 params[7], val[7];
4189
4190                 sprintf(fw_config_file_path,
4191                         "/lib/firmware/%s", fw_config_file);
4192                 config_name = fw_config_file_path;
4193
4194                 if (cf->size >= FLASH_CFG_MAX_SIZE)
4195                         ret = -ENOMEM;
4196                 else {
4197                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4198                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4199                         ret = t4_query_params(adapter, adapter->mbox,
4200                                               adapter->pf, 0, 1, params, val);
4201                         if (ret == 0) {
4202                                 /*
4203                                  * For t4_memory_rw() below addresses and
4204                                  * sizes have to be in terms of multiples of 4
4205                                  * bytes.  So, if the Configuration File isn't
4206                                  * a multiple of 4 bytes in length we'll have
4207                                  * to write that out separately since we can't
4208                                  * guarantee that the bytes following the
4209                                  * residual byte in the buffer returned by
4210                                  * request_firmware() are zeroed out ...
4211                                  */
4212                                 size_t resid = cf->size & 0x3;
4213                                 size_t size = cf->size & ~0x3;
4214                                 __be32 *data = (__be32 *)cf->data;
4215
4216                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
4217                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
4218
4219                                 spin_lock(&adapter->win0_lock);
4220                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
4221                                                    size, data, T4_MEMORY_WRITE);
4222                                 if (ret == 0 && resid != 0) {
4223                                         union {
4224                                                 __be32 word;
4225                                                 char buf[4];
4226                                         } last;
4227                                         int i;
4228
4229                                         last.word = data[size >> 2];
4230                                         for (i = resid; i < 4; i++)
4231                                                 last.buf[i] = 0;
4232                                         ret = t4_memory_rw(adapter, 0, mtype,
4233                                                            maddr + size,
4234                                                            4, &last.word,
4235                                                            T4_MEMORY_WRITE);
4236                                 }
4237                                 spin_unlock(&adapter->win0_lock);
4238                         }
4239                 }
4240
4241                 release_firmware(cf);
4242                 if (ret)
4243                         goto bye;
4244         }
4245
4246         val = 0;
4247
4248         /* Ofld + Hash filter is supported. Older fw will fail this request and
4249          * it is fine.
4250          */
4251         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4252                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD));
4253         ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0,
4254                             1, &param, &val);
4255
4256         /* FW doesn't know about Hash filter + ofld support,
4257          * it's not a problem, don't return an error.
4258          */
4259         if (ret < 0) {
4260                 dev_warn(adapter->pdev_dev,
4261                          "Hash filter with ofld is not supported by FW\n");
4262         }
4263
4264         /*
4265          * Issue a Capability Configuration command to the firmware to get it
4266          * to parse the Configuration File.  We don't use t4_fw_config_file()
4267          * because we want the ability to modify various features after we've
4268          * processed the configuration file ...
4269          */
4270         memset(&caps_cmd, 0, sizeof(caps_cmd));
4271         caps_cmd.op_to_write =
4272                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4273                       FW_CMD_REQUEST_F |
4274                       FW_CMD_READ_F);
4275         caps_cmd.cfvalid_to_len16 =
4276                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
4277                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
4278                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
4279                       FW_LEN16(caps_cmd));
4280         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4281                          &caps_cmd);
4282
4283         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
4284          * Configuration File in FLASH), our last gasp effort is to use the
4285          * Firmware Configuration File which is embedded in the firmware.  A
4286          * very few early versions of the firmware didn't have one embedded
4287          * but we can ignore those.
4288          */
4289         if (ret == -ENOENT) {
4290                 memset(&caps_cmd, 0, sizeof(caps_cmd));
4291                 caps_cmd.op_to_write =
4292                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4293                                         FW_CMD_REQUEST_F |
4294                                         FW_CMD_READ_F);
4295                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4296                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
4297                                 sizeof(caps_cmd), &caps_cmd);
4298                 config_name = "Firmware Default";
4299         }
4300
4301         config_issued = 1;
4302         if (ret < 0)
4303                 goto bye;
4304
4305         finiver = ntohl(caps_cmd.finiver);
4306         finicsum = ntohl(caps_cmd.finicsum);
4307         cfcsum = ntohl(caps_cmd.cfcsum);
4308         if (finicsum != cfcsum)
4309                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4310                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4311                          finicsum, cfcsum);
4312
4313         /*
4314          * And now tell the firmware to use the configuration we just loaded.
4315          */
4316         caps_cmd.op_to_write =
4317                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4318                       FW_CMD_REQUEST_F |
4319                       FW_CMD_WRITE_F);
4320         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4321         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4322                          NULL);
4323         if (ret < 0)
4324                 goto bye;
4325
4326         /*
4327          * Tweak configuration based on system architecture, module
4328          * parameters, etc.
4329          */
4330         ret = adap_init0_tweaks(adapter);
4331         if (ret < 0)
4332                 goto bye;
4333
4334         /* We will proceed even if HMA init fails. */
4335         ret = adap_config_hma(adapter);
4336         if (ret)
4337                 dev_err(adapter->pdev_dev,
4338                         "HMA configuration failed with error %d\n", ret);
4339
4340         if (is_t6(adapter->params.chip)) {
4341                 ret = setup_ppod_edram(adapter);
4342                 if (!ret)
4343                         dev_info(adapter->pdev_dev, "Successfully enabled "
4344                                  "ppod edram feature\n");
4345         }
4346
4347         /*
4348          * And finally tell the firmware to initialize itself using the
4349          * parameters from the Configuration File.
4350          */
4351         ret = t4_fw_initialize(adapter, adapter->mbox);
4352         if (ret < 0)
4353                 goto bye;
4354
4355         /* Emit Firmware Configuration File information and return
4356          * successfully.
4357          */
4358         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
4359                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4360                  config_name, finiver, cfcsum);
4361         return 0;
4362
4363         /*
4364          * Something bad happened.  Return the error ...  (If the "error"
4365          * is that there's no Configuration File on the adapter we don't
4366          * want to issue a warning since this is fairly common.)
4367          */
4368 bye:
4369         if (config_issued && ret != -ENOENT)
4370                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4371                          config_name, -ret);
4372         return ret;
4373 }
4374
4375 static struct fw_info fw_info_array[] = {
4376         {
4377                 .chip = CHELSIO_T4,
4378                 .fs_name = FW4_CFNAME,
4379                 .fw_mod_name = FW4_FNAME,
4380                 .fw_hdr = {
4381                         .chip = FW_HDR_CHIP_T4,
4382                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4383                         .intfver_nic = FW_INTFVER(T4, NIC),
4384                         .intfver_vnic = FW_INTFVER(T4, VNIC),
4385                         .intfver_ri = FW_INTFVER(T4, RI),
4386                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4387                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
4388                 },
4389         }, {
4390                 .chip = CHELSIO_T5,
4391                 .fs_name = FW5_CFNAME,
4392                 .fw_mod_name = FW5_FNAME,
4393                 .fw_hdr = {
4394                         .chip = FW_HDR_CHIP_T5,
4395                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4396                         .intfver_nic = FW_INTFVER(T5, NIC),
4397                         .intfver_vnic = FW_INTFVER(T5, VNIC),
4398                         .intfver_ri = FW_INTFVER(T5, RI),
4399                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4400                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
4401                 },
4402         }, {
4403                 .chip = CHELSIO_T6,
4404                 .fs_name = FW6_CFNAME,
4405                 .fw_mod_name = FW6_FNAME,
4406                 .fw_hdr = {
4407                         .chip = FW_HDR_CHIP_T6,
4408                         .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4409                         .intfver_nic = FW_INTFVER(T6, NIC),
4410                         .intfver_vnic = FW_INTFVER(T6, VNIC),
4411                         .intfver_ofld = FW_INTFVER(T6, OFLD),
4412                         .intfver_ri = FW_INTFVER(T6, RI),
4413                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4414                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4415                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4416                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
4417                 },
4418         }
4419
4420 };
4421
4422 static struct fw_info *find_fw_info(int chip)
4423 {
4424         int i;
4425
4426         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4427                 if (fw_info_array[i].chip == chip)
4428                         return &fw_info_array[i];
4429         }
4430         return NULL;
4431 }
4432
4433 /*
4434  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4435  */
4436 static int adap_init0(struct adapter *adap, int vpd_skip)
4437 {
4438         struct fw_caps_config_cmd caps_cmd;
4439         u32 params[7], val[7];
4440         enum dev_state state;
4441         u32 v, port_vec;
4442         int reset = 1;
4443         int ret;
4444
4445         /* Grab Firmware Device Log parameters as early as possible so we have
4446          * access to it for debugging, etc.
4447          */
4448         ret = t4_init_devlog_params(adap);
4449         if (ret < 0)
4450                 return ret;
4451
4452         /* Contact FW, advertising Master capability */
4453         ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4454                           is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
4455         if (ret < 0) {
4456                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4457                         ret);
4458                 return ret;
4459         }
4460         if (ret == adap->mbox)
4461                 adap->flags |= CXGB4_MASTER_PF;
4462
4463         /*
4464          * If we're the Master PF Driver and the device is uninitialized,
4465          * then let's consider upgrading the firmware ...  (We always want
4466          * to check the firmware version number in order to A. get it for
4467          * later reporting and B. to warn if the currently loaded firmware
4468          * is excessively mismatched relative to the driver.)
4469          */
4470
4471         t4_get_version_info(adap);
4472         ret = t4_check_fw_version(adap);
4473         /* If firmware is too old (not supported by driver) force an update. */
4474         if (ret)
4475                 state = DEV_STATE_UNINIT;
4476         if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
4477                 struct fw_info *fw_info;
4478                 struct fw_hdr *card_fw;
4479                 const struct firmware *fw;
4480                 const u8 *fw_data = NULL;
4481                 unsigned int fw_size = 0;
4482
4483                 /* This is the firmware whose headers the driver was compiled
4484                  * against
4485                  */
4486                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4487                 if (fw_info == NULL) {
4488                         dev_err(adap->pdev_dev,
4489                                 "unable to get firmware info for chip %d.\n",
4490                                 CHELSIO_CHIP_VERSION(adap->params.chip));
4491                         return -EINVAL;
4492                 }
4493
4494                 /* allocate memory to read the header of the firmware on the
4495                  * card
4496                  */
4497                 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
4498                 if (!card_fw) {
4499                         ret = -ENOMEM;
4500                         goto bye;
4501                 }
4502
4503                 /* Get FW from from /lib/firmware/ */
4504                 ret = request_firmware(&fw, fw_info->fw_mod_name,
4505                                        adap->pdev_dev);
4506                 if (ret < 0) {
4507                         dev_err(adap->pdev_dev,
4508                                 "unable to load firmware image %s, error %d\n",
4509                                 fw_info->fw_mod_name, ret);
4510                 } else {
4511                         fw_data = fw->data;
4512                         fw_size = fw->size;
4513                 }
4514
4515                 /* upgrade FW logic */
4516                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4517                                  state, &reset);
4518
4519                 /* Cleaning up */
4520                 release_firmware(fw);
4521                 kvfree(card_fw);
4522
4523                 if (ret < 0)
4524                         goto bye;
4525         }
4526
4527         /* If the firmware is initialized already, emit a simply note to that
4528          * effect. Otherwise, it's time to try initializing the adapter.
4529          */
4530         if (state == DEV_STATE_INIT) {
4531                 ret = adap_config_hma(adap);
4532                 if (ret)
4533                         dev_err(adap->pdev_dev,
4534                                 "HMA configuration failed with error %d\n",
4535                                 ret);
4536                 dev_info(adap->pdev_dev, "Coming up as %s: "\
4537                          "Adapter already initialized\n",
4538                          adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE");
4539         } else {
4540                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4541                          "Initializing adapter\n");
4542
4543                 /* Find out whether we're dealing with a version of the
4544                  * firmware which has configuration file support.
4545                  */
4546                 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4547                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4548                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
4549                                       params, val);
4550
4551                 /* If the firmware doesn't support Configuration Files,
4552                  * return an error.
4553                  */
4554                 if (ret < 0) {
4555                         dev_err(adap->pdev_dev, "firmware doesn't support "
4556                                 "Firmware Configuration Files\n");
4557                         goto bye;
4558                 }
4559
4560                 /* The firmware provides us with a memory buffer where we can
4561                  * load a Configuration File from the host if we want to
4562                  * override the Configuration File in flash.
4563                  */
4564                 ret = adap_init0_config(adap, reset);
4565                 if (ret == -ENOENT) {
4566                         dev_err(adap->pdev_dev, "no Configuration File "
4567                                 "present on adapter.\n");
4568                         goto bye;
4569                 }
4570                 if (ret < 0) {
4571                         dev_err(adap->pdev_dev, "could not initialize "
4572                                 "adapter, error %d\n", -ret);
4573                         goto bye;
4574                 }
4575         }
4576
4577         /* Now that we've successfully configured and initialized the adapter
4578          * (or found it already initialized), we can ask the Firmware what
4579          * resources it has provisioned for us.
4580          */
4581         ret = t4_get_pfres(adap);
4582         if (ret) {
4583                 dev_err(adap->pdev_dev,
4584                         "Unable to retrieve resource provisioning information\n");
4585                 goto bye;
4586         }
4587
4588         /* Grab VPD parameters.  This should be done after we establish a
4589          * connection to the firmware since some of the VPD parameters
4590          * (notably the Core Clock frequency) are retrieved via requests to
4591          * the firmware.  On the other hand, we need these fairly early on
4592          * so we do this right after getting ahold of the firmware.
4593          *
4594          * We need to do this after initializing the adapter because someone
4595          * could have FLASHed a new VPD which won't be read by the firmware
4596          * until we do the RESET ...
4597          */
4598         if (!vpd_skip) {
4599                 ret = t4_get_vpd_params(adap, &adap->params.vpd);
4600                 if (ret < 0)
4601                         goto bye;
4602         }
4603
4604         /* Find out what ports are available to us.  Note that we need to do
4605          * this before calling adap_init0_no_config() since it needs nports
4606          * and portvec ...
4607          */
4608         v =
4609             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4610             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4611         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4612         if (ret < 0)
4613                 goto bye;
4614
4615         adap->params.nports = hweight32(port_vec);
4616         adap->params.portvec = port_vec;
4617
4618         /* Give the SGE code a chance to pull in anything that it needs ...
4619          * Note that this must be called after we retrieve our VPD parameters
4620          * in order to know how to convert core ticks to seconds, etc.
4621          */
4622         ret = t4_sge_init(adap);
4623         if (ret < 0)
4624                 goto bye;
4625
4626         /* Grab the SGE Doorbell Queue Timer values.  If successful, that
4627          * indicates that the Firmware and Hardware support this.
4628          */
4629         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4630                     FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
4631         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4632                               1, params, val);
4633
4634         if (!ret) {
4635                 adap->sge.dbqtimer_tick = val[0];
4636                 ret = t4_read_sge_dbqtimers(adap,
4637                                             ARRAY_SIZE(adap->sge.dbqtimer_val),
4638                                             adap->sge.dbqtimer_val);
4639         }
4640
4641         if (!ret)
4642                 adap->flags |= CXGB4_SGE_DBQ_TIMER;
4643
4644         if (is_bypass_device(adap->pdev->device))
4645                 adap->params.bypass = 1;
4646
4647         /*
4648          * Grab some of our basic fundamental operating parameters.
4649          */
4650 #define FW_PARAM_DEV(param) \
4651         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
4652         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
4653
4654 #define FW_PARAM_PFVF(param) \
4655         FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
4656         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)|  \
4657         FW_PARAMS_PARAM_Y_V(0) | \
4658         FW_PARAMS_PARAM_Z_V(0)
4659
4660         params[0] = FW_PARAM_PFVF(EQ_START);
4661         params[1] = FW_PARAM_PFVF(L2T_START);
4662         params[2] = FW_PARAM_PFVF(L2T_END);
4663         params[3] = FW_PARAM_PFVF(FILTER_START);
4664         params[4] = FW_PARAM_PFVF(FILTER_END);
4665         params[5] = FW_PARAM_PFVF(IQFLINT_START);
4666         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
4667         if (ret < 0)
4668                 goto bye;
4669         adap->sge.egr_start = val[0];
4670         adap->l2t_start = val[1];
4671         adap->l2t_end = val[2];
4672         adap->tids.ftid_base = val[3];
4673         adap->tids.nftids = val[4] - val[3] + 1;
4674         adap->sge.ingr_start = val[5];
4675
4676         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4677                 /* Read the raw mps entries. In T6, the last 2 tcam entries
4678                  * are reserved for raw mac addresses (rawf = 2, one per port).
4679                  */
4680                 params[0] = FW_PARAM_PFVF(RAWF_START);
4681                 params[1] = FW_PARAM_PFVF(RAWF_END);
4682                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4683                                       params, val);
4684                 if (ret == 0) {
4685                         adap->rawf_start = val[0];
4686                         adap->rawf_cnt = val[1] - val[0] + 1;
4687                 }
4688         }
4689
4690         /* qids (ingress/egress) returned from firmware can be anywhere
4691          * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4692          * Hence driver needs to allocate memory for this range to
4693          * store the queue info. Get the highest IQFLINT/EQ index returned
4694          * in FW_EQ_*_CMD.alloc command.
4695          */
4696         params[0] = FW_PARAM_PFVF(EQ_END);
4697         params[1] = FW_PARAM_PFVF(IQFLINT_END);
4698         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4699         if (ret < 0)
4700                 goto bye;
4701         adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4702         adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4703
4704         adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4705                                     sizeof(*adap->sge.egr_map), GFP_KERNEL);
4706         if (!adap->sge.egr_map) {
4707                 ret = -ENOMEM;
4708                 goto bye;
4709         }
4710
4711         adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4712                                      sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4713         if (!adap->sge.ingr_map) {
4714                 ret = -ENOMEM;
4715                 goto bye;
4716         }
4717
4718         /* Allocate the memory for the vaious egress queue bitmaps
4719          * ie starving_fl, txq_maperr and blocked_fl.
4720          */
4721         adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4722                                         sizeof(long), GFP_KERNEL);
4723         if (!adap->sge.starving_fl) {
4724                 ret = -ENOMEM;
4725                 goto bye;
4726         }
4727
4728         adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4729                                        sizeof(long), GFP_KERNEL);
4730         if (!adap->sge.txq_maperr) {
4731                 ret = -ENOMEM;
4732                 goto bye;
4733         }
4734
4735 #ifdef CONFIG_DEBUG_FS
4736         adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4737                                        sizeof(long), GFP_KERNEL);
4738         if (!adap->sge.blocked_fl) {
4739                 ret = -ENOMEM;
4740                 goto bye;
4741         }
4742 #endif
4743
4744         params[0] = FW_PARAM_PFVF(CLIP_START);
4745         params[1] = FW_PARAM_PFVF(CLIP_END);
4746         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4747         if (ret < 0)
4748                 goto bye;
4749         adap->clipt_start = val[0];
4750         adap->clipt_end = val[1];
4751
4752         /* Get the supported number of traffic classes */
4753         params[0] = FW_PARAM_DEV(NUM_TM_CLASS);
4754         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4755         if (ret < 0) {
4756                 /* We couldn't retrieve the number of Traffic Classes
4757                  * supported by the hardware/firmware. So we hard
4758                  * code it here.
4759                  */
4760                 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4761         } else {
4762                 adap->params.nsched_cls = val[0];
4763         }
4764
4765         /* query params related to active filter region */
4766         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4767         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4768         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4769         /* If Active filter size is set we enable establishing
4770          * offload connection through firmware work request
4771          */
4772         if ((val[0] != val[1]) && (ret >= 0)) {
4773                 adap->flags |= CXGB4_FW_OFLD_CONN;
4774                 adap->tids.aftid_base = val[0];
4775                 adap->tids.aftid_end = val[1];
4776         }
4777
4778         /* If we're running on newer firmware, let it know that we're
4779          * prepared to deal with encapsulated CPL messages.  Older
4780          * firmware won't understand this and we'll just get
4781          * unencapsulated messages ...
4782          */
4783         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4784         val[0] = 1;
4785         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4786
4787         /*
4788          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4789          * capability.  Earlier versions of the firmware didn't have the
4790          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4791          * permission to use ULPTX MEMWRITE DSGL.
4792          */
4793         if (is_t4(adap->params.chip)) {
4794                 adap->params.ulptx_memwrite_dsgl = false;
4795         } else {
4796                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4797                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4798                                       1, params, val);
4799                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4800         }
4801
4802         /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4803         params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4804         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4805                               1, params, val);
4806         adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4807
4808         /* See if FW supports FW_FILTER2 work request */
4809         if (is_t4(adap->params.chip)) {
4810                 adap->params.filter2_wr_support = 0;
4811         } else {
4812                 params[0] = FW_PARAM_DEV(FILTER2_WR);
4813                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4814                                       1, params, val);
4815                 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4816         }
4817
4818         /* Check if FW supports returning vin and smt index.
4819          * If this is not supported, driver will interpret
4820          * these values from viid.
4821          */
4822         params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4823         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4824                               1, params, val);
4825         adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4826
4827         /*
4828          * Get device capabilities so we can determine what resources we need
4829          * to manage.
4830          */
4831         memset(&caps_cmd, 0, sizeof(caps_cmd));
4832         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4833                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
4834         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4835         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4836                          &caps_cmd);
4837         if (ret < 0)
4838                 goto bye;
4839
4840         /* hash filter has some mandatory register settings to be tested and for
4841          * that it needs to test whether offload is enabled or not, hence
4842          * checking and setting it here.
4843          */
4844         if (caps_cmd.ofldcaps)
4845                 adap->params.offload = 1;
4846
4847         if (caps_cmd.ofldcaps ||
4848             (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) ||
4849             (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD))) {
4850                 /* query offload-related parameters */
4851                 params[0] = FW_PARAM_DEV(NTID);
4852                 params[1] = FW_PARAM_PFVF(SERVER_START);
4853                 params[2] = FW_PARAM_PFVF(SERVER_END);
4854                 params[3] = FW_PARAM_PFVF(TDDP_START);
4855                 params[4] = FW_PARAM_PFVF(TDDP_END);
4856                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4857                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4858                                       params, val);
4859                 if (ret < 0)
4860                         goto bye;
4861                 adap->tids.ntids = val[0];
4862                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4863                 adap->tids.stid_base = val[1];
4864                 adap->tids.nstids = val[2] - val[1] + 1;
4865                 /*
4866                  * Setup server filter region. Divide the available filter
4867                  * region into two parts. Regular filters get 1/3rd and server
4868                  * filters get 2/3rd part. This is only enabled if workarond
4869                  * path is enabled.
4870                  * 1. For regular filters.
4871                  * 2. Server filter: This are special filters which are used
4872                  * to redirect SYN packets to offload queue.
4873                  */
4874                 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) {
4875                         adap->tids.sftid_base = adap->tids.ftid_base +
4876                                         DIV_ROUND_UP(adap->tids.nftids, 3);
4877                         adap->tids.nsftids = adap->tids.nftids -
4878                                          DIV_ROUND_UP(adap->tids.nftids, 3);
4879                         adap->tids.nftids = adap->tids.sftid_base -
4880                                                 adap->tids.ftid_base;
4881                 }
4882                 adap->vres.ddp.start = val[3];
4883                 adap->vres.ddp.size = val[4] - val[3] + 1;
4884                 adap->params.ofldq_wr_cred = val[5];
4885
4886                 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4887                         init_hash_filter(adap);
4888                 } else {
4889                         adap->num_ofld_uld += 1;
4890                 }
4891
4892                 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD)) {
4893                         params[0] = FW_PARAM_PFVF(ETHOFLD_START);
4894                         params[1] = FW_PARAM_PFVF(ETHOFLD_END);
4895                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4896                                               params, val);
4897                         if (!ret) {
4898                                 adap->tids.eotid_base = val[0];
4899                                 adap->tids.neotids = min_t(u32, MAX_ATIDS,
4900                                                            val[1] - val[0] + 1);
4901                                 adap->params.ethofld = 1;
4902                         }
4903                 }
4904         }
4905         if (caps_cmd.rdmacaps) {
4906                 params[0] = FW_PARAM_PFVF(STAG_START);
4907                 params[1] = FW_PARAM_PFVF(STAG_END);
4908                 params[2] = FW_PARAM_PFVF(RQ_START);
4909                 params[3] = FW_PARAM_PFVF(RQ_END);
4910                 params[4] = FW_PARAM_PFVF(PBL_START);
4911                 params[5] = FW_PARAM_PFVF(PBL_END);
4912                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4913                                       params, val);
4914                 if (ret < 0)
4915                         goto bye;
4916                 adap->vres.stag.start = val[0];
4917                 adap->vres.stag.size = val[1] - val[0] + 1;
4918                 adap->vres.rq.start = val[2];
4919                 adap->vres.rq.size = val[3] - val[2] + 1;
4920                 adap->vres.pbl.start = val[4];
4921                 adap->vres.pbl.size = val[5] - val[4] + 1;
4922
4923                 params[0] = FW_PARAM_PFVF(SRQ_START);
4924                 params[1] = FW_PARAM_PFVF(SRQ_END);
4925                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4926                                       params, val);
4927                 if (!ret) {
4928                         adap->vres.srq.start = val[0];
4929                         adap->vres.srq.size = val[1] - val[0] + 1;
4930                 }
4931                 if (adap->vres.srq.size) {
4932                         adap->srq = t4_init_srq(adap->vres.srq.size);
4933                         if (!adap->srq)
4934                                 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4935                 }
4936
4937                 params[0] = FW_PARAM_PFVF(SQRQ_START);
4938                 params[1] = FW_PARAM_PFVF(SQRQ_END);
4939                 params[2] = FW_PARAM_PFVF(CQ_START);
4940                 params[3] = FW_PARAM_PFVF(CQ_END);
4941                 params[4] = FW_PARAM_PFVF(OCQ_START);
4942                 params[5] = FW_PARAM_PFVF(OCQ_END);
4943                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4944                                       val);
4945                 if (ret < 0)
4946                         goto bye;
4947                 adap->vres.qp.start = val[0];
4948                 adap->vres.qp.size = val[1] - val[0] + 1;
4949                 adap->vres.cq.start = val[2];
4950                 adap->vres.cq.size = val[3] - val[2] + 1;
4951                 adap->vres.ocq.start = val[4];
4952                 adap->vres.ocq.size = val[5] - val[4] + 1;
4953
4954                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4955                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4956                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4957                                       val);
4958                 if (ret < 0) {
4959                         adap->params.max_ordird_qp = 8;
4960                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4961                         ret = 0;
4962                 } else {
4963                         adap->params.max_ordird_qp = val[0];
4964                         adap->params.max_ird_adapter = val[1];
4965                 }
4966                 dev_info(adap->pdev_dev,
4967                          "max_ordird_qp %d max_ird_adapter %d\n",
4968                          adap->params.max_ordird_qp,
4969                          adap->params.max_ird_adapter);
4970
4971                 /* Enable write_with_immediate if FW supports it */
4972                 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
4973                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4974                                       val);
4975                 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
4976
4977                 /* Enable write_cmpl if FW supports it */
4978                 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
4979                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4980                                       val);
4981                 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
4982                 adap->num_ofld_uld += 2;
4983         }
4984         if (caps_cmd.iscsicaps) {
4985                 params[0] = FW_PARAM_PFVF(ISCSI_START);
4986                 params[1] = FW_PARAM_PFVF(ISCSI_END);
4987                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4988                                       params, val);
4989                 if (ret < 0)
4990                         goto bye;
4991                 adap->vres.iscsi.start = val[0];
4992                 adap->vres.iscsi.size = val[1] - val[0] + 1;
4993                 if (is_t6(adap->params.chip)) {
4994                         params[0] = FW_PARAM_PFVF(PPOD_EDRAM_START);
4995                         params[1] = FW_PARAM_PFVF(PPOD_EDRAM_END);
4996                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4997                                               params, val);
4998                         if (!ret) {
4999                                 adap->vres.ppod_edram.start = val[0];
5000                                 adap->vres.ppod_edram.size =
5001                                         val[1] - val[0] + 1;
5002
5003                                 dev_info(adap->pdev_dev,
5004                                          "ppod edram start 0x%x end 0x%x size 0x%x\n",
5005                                          val[0], val[1],
5006                                          adap->vres.ppod_edram.size);
5007                         }
5008                 }
5009                 /* LIO target and cxgb4i initiaitor */
5010                 adap->num_ofld_uld += 2;
5011         }
5012         if (caps_cmd.cryptocaps) {
5013                 if (ntohs(caps_cmd.cryptocaps) &
5014                     FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
5015                         params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
5016                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
5017                                               2, params, val);
5018                         if (ret < 0) {
5019                                 if (ret != -EINVAL)
5020                                         goto bye;
5021                         } else {
5022                                 adap->vres.ncrypto_fc = val[0];
5023                         }
5024                         adap->num_ofld_uld += 1;
5025                 }
5026                 if (ntohs(caps_cmd.cryptocaps) &
5027                     FW_CAPS_CONFIG_TLS_INLINE) {
5028                         params[0] = FW_PARAM_PFVF(TLS_START);
5029                         params[1] = FW_PARAM_PFVF(TLS_END);
5030                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
5031                                               2, params, val);
5032                         if (ret < 0)
5033                                 goto bye;
5034                         adap->vres.key.start = val[0];
5035                         adap->vres.key.size = val[1] - val[0] + 1;
5036                         adap->num_uld += 1;
5037                 }
5038                 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
5039         }
5040 #undef FW_PARAM_PFVF
5041 #undef FW_PARAM_DEV
5042
5043         /* The MTU/MSS Table is initialized by now, so load their values.  If
5044          * we're initializing the adapter, then we'll make any modifications
5045          * we want to the MTU/MSS Table and also initialize the congestion
5046          * parameters.
5047          */
5048         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5049         if (state != DEV_STATE_INIT) {
5050                 int i;
5051
5052                 /* The default MTU Table contains values 1492 and 1500.
5053                  * However, for TCP, it's better to have two values which are
5054                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5055                  * This allows us to have a TCP Data Payload which is a
5056                  * multiple of 8 regardless of what combination of TCP Options
5057                  * are in use (always a multiple of 4 bytes) which is
5058                  * important for performance reasons.  For instance, if no
5059                  * options are in use, then we have a 20-byte IP header and a
5060                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
5061                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5062                  * which is not a multiple of 8.  So using an MSS of 1488 in
5063                  * this case results in a TCP Data Payload of 1448 bytes which
5064                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
5065                  * Stamps have been negotiated, then an MTU of 1500 bytes
5066                  * results in a TCP Data Payload of 1448 bytes which, as
5067                  * above, is a multiple of 8 bytes ...
5068                  */
5069                 for (i = 0; i < NMTUS; i++)
5070                         if (adap->params.mtus[i] == 1492) {
5071                                 adap->params.mtus[i] = 1488;
5072                                 break;
5073                         }
5074
5075                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5076                              adap->params.b_wnd);
5077         }
5078         t4_init_sge_params(adap);
5079         adap->flags |= CXGB4_FW_OK;
5080         t4_init_tp_params(adap, true);
5081         return 0;
5082
5083         /*
5084          * Something bad happened.  If a command timed out or failed with EIO
5085          * FW does not operate within its spec or something catastrophic
5086          * happened to HW/FW, stop issuing commands.
5087          */
5088 bye:
5089         adap_free_hma_mem(adap);
5090         kfree(adap->sge.egr_map);
5091         kfree(adap->sge.ingr_map);
5092         kfree(adap->sge.starving_fl);
5093         kfree(adap->sge.txq_maperr);
5094 #ifdef CONFIG_DEBUG_FS
5095         kfree(adap->sge.blocked_fl);
5096 #endif
5097         if (ret != -ETIMEDOUT && ret != -EIO)
5098                 t4_fw_bye(adap, adap->mbox);
5099         return ret;
5100 }
5101
5102 /* EEH callbacks */
5103
5104 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5105                                          pci_channel_state_t state)
5106 {
5107         int i;
5108         struct adapter *adap = pci_get_drvdata(pdev);
5109
5110         if (!adap)
5111                 goto out;
5112
5113         rtnl_lock();
5114         adap->flags &= ~CXGB4_FW_OK;
5115         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
5116         spin_lock(&adap->stats_lock);
5117         for_each_port(adap, i) {
5118                 struct net_device *dev = adap->port[i];
5119                 if (dev) {
5120                         netif_device_detach(dev);
5121                         netif_carrier_off(dev);
5122                 }
5123         }
5124         spin_unlock(&adap->stats_lock);
5125         disable_interrupts(adap);
5126         if (adap->flags & CXGB4_FULL_INIT_DONE)
5127                 cxgb_down(adap);
5128         rtnl_unlock();
5129         if ((adap->flags & CXGB4_DEV_ENABLED)) {
5130                 pci_disable_device(pdev);
5131                 adap->flags &= ~CXGB4_DEV_ENABLED;
5132         }
5133 out:    return state == pci_channel_io_perm_failure ?
5134                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5135 }
5136
5137 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5138 {
5139         int i, ret;
5140         struct fw_caps_config_cmd c;
5141         struct adapter *adap = pci_get_drvdata(pdev);
5142
5143         if (!adap) {
5144                 pci_restore_state(pdev);
5145                 pci_save_state(pdev);
5146                 return PCI_ERS_RESULT_RECOVERED;
5147         }
5148
5149         if (!(adap->flags & CXGB4_DEV_ENABLED)) {
5150                 if (pci_enable_device(pdev)) {
5151                         dev_err(&pdev->dev, "Cannot reenable PCI "
5152                                             "device after reset\n");
5153                         return PCI_ERS_RESULT_DISCONNECT;
5154                 }
5155                 adap->flags |= CXGB4_DEV_ENABLED;
5156         }
5157
5158         pci_set_master(pdev);
5159         pci_restore_state(pdev);
5160         pci_save_state(pdev);
5161
5162         if (t4_wait_dev_ready(adap->regs) < 0)
5163                 return PCI_ERS_RESULT_DISCONNECT;
5164         if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
5165                 return PCI_ERS_RESULT_DISCONNECT;
5166         adap->flags |= CXGB4_FW_OK;
5167         if (adap_init1(adap, &c))
5168                 return PCI_ERS_RESULT_DISCONNECT;
5169
5170         for_each_port(adap, i) {
5171                 struct port_info *pi = adap2pinfo(adap, i);
5172                 u8 vivld = 0, vin = 0;
5173
5174                 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
5175                                   NULL, NULL, &vivld, &vin);
5176                 if (ret < 0)
5177                         return PCI_ERS_RESULT_DISCONNECT;
5178                 pi->viid = ret;
5179                 pi->xact_addr_filt = -1;
5180                 /* If fw supports returning the VIN as part of FW_VI_CMD,
5181                  * save the returned values.
5182                  */
5183                 if (adap->params.viid_smt_extn_support) {
5184                         pi->vivld = vivld;
5185                         pi->vin = vin;
5186                 } else {
5187                         /* Retrieve the values from VIID */
5188                         pi->vivld = FW_VIID_VIVLD_G(pi->viid);
5189                         pi->vin = FW_VIID_VIN_G(pi->viid);
5190                 }
5191         }
5192
5193         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5194                      adap->params.b_wnd);
5195         setup_memwin(adap);
5196         if (cxgb_up(adap))
5197                 return PCI_ERS_RESULT_DISCONNECT;
5198         return PCI_ERS_RESULT_RECOVERED;
5199 }
5200
5201 static void eeh_resume(struct pci_dev *pdev)
5202 {
5203         int i;
5204         struct adapter *adap = pci_get_drvdata(pdev);
5205
5206         if (!adap)
5207                 return;
5208
5209         rtnl_lock();
5210         for_each_port(adap, i) {
5211                 struct net_device *dev = adap->port[i];
5212                 if (dev) {
5213                         if (netif_running(dev)) {
5214                                 link_start(dev);
5215                                 cxgb_set_rxmode(dev);
5216                         }
5217                         netif_device_attach(dev);
5218                 }
5219         }
5220         rtnl_unlock();
5221 }
5222
5223 static void eeh_reset_prepare(struct pci_dev *pdev)
5224 {
5225         struct adapter *adapter = pci_get_drvdata(pdev);
5226         int i;
5227
5228         if (adapter->pf != 4)
5229                 return;
5230
5231         adapter->flags &= ~CXGB4_FW_OK;
5232
5233         notify_ulds(adapter, CXGB4_STATE_DOWN);
5234
5235         for_each_port(adapter, i)
5236                 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5237                         cxgb_close(adapter->port[i]);
5238
5239         disable_interrupts(adapter);
5240         cxgb4_free_mps_ref_entries(adapter);
5241
5242         adap_free_hma_mem(adapter);
5243
5244         if (adapter->flags & CXGB4_FULL_INIT_DONE)
5245                 cxgb_down(adapter);
5246 }
5247
5248 static void eeh_reset_done(struct pci_dev *pdev)
5249 {
5250         struct adapter *adapter = pci_get_drvdata(pdev);
5251         int err, i;
5252
5253         if (adapter->pf != 4)
5254                 return;
5255
5256         err = t4_wait_dev_ready(adapter->regs);
5257         if (err < 0) {
5258                 dev_err(adapter->pdev_dev,
5259                         "Device not ready, err %d", err);
5260                 return;
5261         }
5262
5263         setup_memwin(adapter);
5264
5265         err = adap_init0(adapter, 1);
5266         if (err) {
5267                 dev_err(adapter->pdev_dev,
5268                         "Adapter init failed, err %d", err);
5269                 return;
5270         }
5271
5272         setup_memwin_rdma(adapter);
5273
5274         if (adapter->flags & CXGB4_FW_OK) {
5275                 err = t4_port_init(adapter, adapter->pf, adapter->pf, 0);
5276                 if (err) {
5277                         dev_err(adapter->pdev_dev,
5278                                 "Port init failed, err %d", err);
5279                         return;
5280                 }
5281         }
5282
5283         err = cfg_queues(adapter);
5284         if (err) {
5285                 dev_err(adapter->pdev_dev,
5286                         "Config queues failed, err %d", err);
5287                 return;
5288         }
5289
5290         cxgb4_init_mps_ref_entries(adapter);
5291
5292         err = setup_fw_sge_queues(adapter);
5293         if (err) {
5294                 dev_err(adapter->pdev_dev,
5295                         "FW sge queue allocation failed, err %d", err);
5296                 return;
5297         }
5298
5299         for_each_port(adapter, i)
5300                 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5301                         cxgb_open(adapter->port[i]);
5302 }
5303
5304 static const struct pci_error_handlers cxgb4_eeh = {
5305         .error_detected = eeh_err_detected,
5306         .slot_reset     = eeh_slot_reset,
5307         .resume         = eeh_resume,
5308         .reset_prepare  = eeh_reset_prepare,
5309         .reset_done     = eeh_reset_done,
5310 };
5311
5312 /* Return true if the Link Configuration supports "High Speeds" (those greater
5313  * than 1Gb/s).
5314  */
5315 static inline bool is_x_10g_port(const struct link_config *lc)
5316 {
5317         unsigned int speeds, high_speeds;
5318
5319         speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
5320         high_speeds = speeds &
5321                         ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
5322
5323         return high_speeds != 0;
5324 }
5325
5326 /* Perform default configuration of DMA queues depending on the number and type
5327  * of ports we found and the number of available CPUs.  Most settings can be
5328  * modified by the admin prior to actual use.
5329  */
5330 static int cfg_queues(struct adapter *adap)
5331 {
5332         u32 avail_qsets, avail_eth_qsets, avail_uld_qsets;
5333         u32 niqflint, neq, num_ulds;
5334         struct sge *s = &adap->sge;
5335         u32 i, n10g = 0, qidx = 0;
5336 #ifndef CONFIG_CHELSIO_T4_DCB
5337         int q10g = 0;
5338 #endif
5339
5340         /* Reduce memory usage in kdump environment, disable all offload. */
5341         if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
5342                 adap->params.offload = 0;
5343                 adap->params.crypto = 0;
5344                 adap->params.ethofld = 0;
5345         }
5346
5347         /* Calculate the number of Ethernet Queue Sets available based on
5348          * resources provisioned for us.  We always have an Asynchronous
5349          * Firmware Event Ingress Queue.  If we're operating in MSI or Legacy
5350          * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
5351          * Ingress Queue.  Meanwhile, we need two Egress Queues for each
5352          * Queue Set: one for the Free List and one for the Ethernet TX Queue.
5353          *
5354          * Note that we should also take into account all of the various
5355          * Offload Queues.  But, in any situation where we're operating in
5356          * a Resource Constrained Provisioning environment, doing any Offload
5357          * at all is problematic ...
5358          */
5359         niqflint = adap->params.pfres.niqflint - 1;
5360         if (!(adap->flags & CXGB4_USING_MSIX))
5361                 niqflint--;
5362         neq = adap->params.pfres.neq / 2;
5363         avail_qsets = min(niqflint, neq);
5364
5365         if (avail_qsets < adap->params.nports) {
5366                 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
5367                         avail_qsets, adap->params.nports);
5368                 return -ENOMEM;
5369         }
5370
5371         /* Count the number of 10Gb/s or better ports */
5372         for_each_port(adap, i)
5373                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
5374
5375         avail_eth_qsets = min_t(u32, avail_qsets, MAX_ETH_QSETS);
5376 #ifdef CONFIG_CHELSIO_T4_DCB
5377         /* For Data Center Bridging support we need to be able to support up
5378          * to 8 Traffic Priorities; each of which will be assigned to its
5379          * own TX Queue in order to prevent Head-Of-Line Blocking.
5380          */
5381         if (adap->params.nports * 8 > avail_eth_qsets) {
5382                 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
5383                         avail_eth_qsets, adap->params.nports * 8);
5384                 return -ENOMEM;
5385         }
5386
5387         for_each_port(adap, i) {
5388                 struct port_info *pi = adap2pinfo(adap, i);
5389
5390                 pi->first_qset = qidx;
5391                 pi->nqsets = is_kdump_kernel() ? 1 : 8;
5392                 qidx += pi->nqsets;
5393         }
5394 #else /* !CONFIG_CHELSIO_T4_DCB */
5395         /* We default to 1 queue per non-10G port and up to # of cores queues
5396          * per 10G port.
5397          */
5398         if (n10g)
5399                 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5400         if (q10g > netif_get_num_default_rss_queues())
5401                 q10g = netif_get_num_default_rss_queues();
5402
5403         if (is_kdump_kernel())
5404                 q10g = 1;
5405
5406         for_each_port(adap, i) {
5407                 struct port_info *pi = adap2pinfo(adap, i);
5408
5409                 pi->first_qset = qidx;
5410                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
5411                 qidx += pi->nqsets;
5412         }
5413 #endif /* !CONFIG_CHELSIO_T4_DCB */
5414
5415         s->ethqsets = qidx;
5416         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
5417         avail_qsets -= qidx;
5418
5419         if (is_uld(adap)) {
5420                 /* For offload we use 1 queue/channel if all ports are up to 1G,
5421                  * otherwise we divide all available queues amongst the channels
5422                  * capped by the number of available cores.
5423                  */
5424                 num_ulds = adap->num_uld + adap->num_ofld_uld;
5425                 i = min_t(u32, MAX_OFLD_QSETS, num_online_cpus());
5426                 avail_uld_qsets = roundup(i, adap->params.nports);
5427                 if (avail_qsets < num_ulds * adap->params.nports) {
5428                         adap->params.offload = 0;
5429                         adap->params.crypto = 0;
5430                         s->ofldqsets = 0;
5431                 } else if (avail_qsets < num_ulds * avail_uld_qsets || !n10g) {
5432                         s->ofldqsets = adap->params.nports;
5433                 } else {
5434                         s->ofldqsets = avail_uld_qsets;
5435                 }
5436
5437                 avail_qsets -= num_ulds * s->ofldqsets;
5438         }
5439
5440         /* ETHOFLD Queues used for QoS offload should follow same
5441          * allocation scheme as normal Ethernet Queues.
5442          */
5443         if (is_ethofld(adap)) {
5444                 if (avail_qsets < s->max_ethqsets) {
5445                         adap->params.ethofld = 0;
5446                         s->eoqsets = 0;
5447                 } else {
5448                         s->eoqsets = s->max_ethqsets;
5449                 }
5450                 avail_qsets -= s->eoqsets;
5451         }
5452
5453         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5454                 struct sge_eth_rxq *r = &s->ethrxq[i];
5455
5456                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
5457                 r->fl.size = 72;
5458         }
5459
5460         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5461                 s->ethtxq[i].q.size = 1024;
5462
5463         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5464                 s->ctrlq[i].q.size = 512;
5465
5466         if (!is_t4(adap->params.chip))
5467                 s->ptptxq.q.size = 8;
5468
5469         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
5470         init_rspq(adap, &s->intrq, 0, 1, 512, 64);
5471
5472         return 0;
5473 }
5474
5475 /*
5476  * Reduce the number of Ethernet queues across all ports to at most n.
5477  * n provides at least one queue per port.
5478  */
5479 static void reduce_ethqs(struct adapter *adap, int n)
5480 {
5481         int i;
5482         struct port_info *pi;
5483
5484         while (n < adap->sge.ethqsets)
5485                 for_each_port(adap, i) {
5486                         pi = adap2pinfo(adap, i);
5487                         if (pi->nqsets > 1) {
5488                                 pi->nqsets--;
5489                                 adap->sge.ethqsets--;
5490                                 if (adap->sge.ethqsets <= n)
5491                                         break;
5492                         }
5493                 }
5494
5495         n = 0;
5496         for_each_port(adap, i) {
5497                 pi = adap2pinfo(adap, i);
5498                 pi->first_qset = n;
5499                 n += pi->nqsets;
5500         }
5501 }
5502
5503 static int alloc_msix_info(struct adapter *adap, u32 num_vec)
5504 {
5505         struct msix_info *msix_info;
5506
5507         msix_info = kcalloc(num_vec, sizeof(*msix_info), GFP_KERNEL);
5508         if (!msix_info)
5509                 return -ENOMEM;
5510
5511         adap->msix_bmap.msix_bmap = kcalloc(BITS_TO_LONGS(num_vec),
5512                                             sizeof(long), GFP_KERNEL);
5513         if (!adap->msix_bmap.msix_bmap) {
5514                 kfree(msix_info);
5515                 return -ENOMEM;
5516         }
5517
5518         spin_lock_init(&adap->msix_bmap.lock);
5519         adap->msix_bmap.mapsize = num_vec;
5520
5521         adap->msix_info = msix_info;
5522         return 0;
5523 }
5524
5525 static void free_msix_info(struct adapter *adap)
5526 {
5527         kfree(adap->msix_bmap.msix_bmap);
5528         kfree(adap->msix_info);
5529 }
5530
5531 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap)
5532 {
5533         struct msix_bmap *bmap = &adap->msix_bmap;
5534         unsigned int msix_idx;
5535         unsigned long flags;
5536
5537         spin_lock_irqsave(&bmap->lock, flags);
5538         msix_idx = find_first_zero_bit(bmap->msix_bmap, bmap->mapsize);
5539         if (msix_idx < bmap->mapsize) {
5540                 __set_bit(msix_idx, bmap->msix_bmap);
5541         } else {
5542                 spin_unlock_irqrestore(&bmap->lock, flags);
5543                 return -ENOSPC;
5544         }
5545
5546         spin_unlock_irqrestore(&bmap->lock, flags);
5547         return msix_idx;
5548 }
5549
5550 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap,
5551                                  unsigned int msix_idx)
5552 {
5553         struct msix_bmap *bmap = &adap->msix_bmap;
5554         unsigned long flags;
5555
5556         spin_lock_irqsave(&bmap->lock, flags);
5557         __clear_bit(msix_idx, bmap->msix_bmap);
5558         spin_unlock_irqrestore(&bmap->lock, flags);
5559 }
5560
5561 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5562 #define EXTRA_VECS 2
5563
5564 static int enable_msix(struct adapter *adap)
5565 {
5566         u32 eth_need, uld_need = 0, ethofld_need = 0;
5567         u32 ethqsets = 0, ofldqsets = 0, eoqsets = 0;
5568         u8 num_uld = 0, nchan = adap->params.nports;
5569         u32 i, want, need, num_vec;
5570         struct sge *s = &adap->sge;
5571         struct msix_entry *entries;
5572         struct port_info *pi;
5573         int allocated, ret;
5574
5575         want = s->max_ethqsets;
5576 #ifdef CONFIG_CHELSIO_T4_DCB
5577         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5578          * each port.
5579          */
5580         need = 8 * nchan;
5581 #else
5582         need = nchan;
5583 #endif
5584         eth_need = need;
5585         if (is_uld(adap)) {
5586                 num_uld = adap->num_ofld_uld + adap->num_uld;
5587                 want += num_uld * s->ofldqsets;
5588                 uld_need = num_uld * nchan;
5589                 need += uld_need;
5590         }
5591
5592         if (is_ethofld(adap)) {
5593                 want += s->eoqsets;
5594                 ethofld_need = eth_need;
5595                 need += ethofld_need;
5596         }
5597
5598         want += EXTRA_VECS;
5599         need += EXTRA_VECS;
5600
5601         entries = kmalloc_array(want, sizeof(*entries), GFP_KERNEL);
5602         if (!entries)
5603                 return -ENOMEM;
5604
5605         for (i = 0; i < want; i++)
5606                 entries[i].entry = i;
5607
5608         allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5609         if (allocated < 0) {
5610                 /* Disable offload and attempt to get vectors for NIC
5611                  * only mode.
5612                  */
5613                 want = s->max_ethqsets + EXTRA_VECS;
5614                 need = eth_need + EXTRA_VECS;
5615                 allocated = pci_enable_msix_range(adap->pdev, entries,
5616                                                   need, want);
5617                 if (allocated < 0) {
5618                         dev_info(adap->pdev_dev,
5619                                  "Disabling MSI-X due to insufficient MSI-X vectors\n");
5620                         ret = allocated;
5621                         goto out_free;
5622                 }
5623
5624                 dev_info(adap->pdev_dev,
5625                          "Disabling offload due to insufficient MSI-X vectors\n");
5626                 adap->params.offload = 0;
5627                 adap->params.crypto = 0;
5628                 adap->params.ethofld = 0;
5629                 s->ofldqsets = 0;
5630                 s->eoqsets = 0;
5631                 uld_need = 0;
5632                 ethofld_need = 0;
5633         }
5634
5635         num_vec = allocated;
5636         if (num_vec < want) {
5637                 /* Distribute available vectors to the various queue groups.
5638                  * Every group gets its minimum requirement and NIC gets top
5639                  * priority for leftovers.
5640                  */
5641                 ethqsets = eth_need;
5642                 if (is_uld(adap))
5643                         ofldqsets = nchan;
5644                 if (is_ethofld(adap))
5645                         eoqsets = ethofld_need;
5646
5647                 num_vec -= need;
5648                 while (num_vec) {
5649                         if (num_vec < eth_need + ethofld_need ||
5650                             ethqsets > s->max_ethqsets)
5651                                 break;
5652
5653                         for_each_port(adap, i) {
5654                                 pi = adap2pinfo(adap, i);
5655                                 if (pi->nqsets < 2)
5656                                         continue;
5657
5658                                 ethqsets++;
5659                                 num_vec--;
5660                                 if (ethofld_need) {
5661                                         eoqsets++;
5662                                         num_vec--;
5663                                 }
5664                         }
5665                 }
5666
5667                 if (is_uld(adap)) {
5668                         while (num_vec) {
5669                                 if (num_vec < uld_need ||
5670                                     ofldqsets > s->ofldqsets)
5671                                         break;
5672
5673                                 ofldqsets++;
5674                                 num_vec -= uld_need;
5675                         }
5676                 }
5677         } else {
5678                 ethqsets = s->max_ethqsets;
5679                 if (is_uld(adap))
5680                         ofldqsets = s->ofldqsets;
5681                 if (is_ethofld(adap))
5682                         eoqsets = s->eoqsets;
5683         }
5684
5685         if (ethqsets < s->max_ethqsets) {
5686                 s->max_ethqsets = ethqsets;
5687                 reduce_ethqs(adap, ethqsets);
5688         }
5689
5690         if (is_uld(adap)) {
5691                 s->ofldqsets = ofldqsets;
5692                 s->nqs_per_uld = s->ofldqsets;
5693         }
5694
5695         if (is_ethofld(adap))
5696                 s->eoqsets = eoqsets;
5697
5698         /* map for msix */
5699         ret = alloc_msix_info(adap, allocated);
5700         if (ret)
5701                 goto out_disable_msix;
5702
5703         for (i = 0; i < allocated; i++) {
5704                 adap->msix_info[i].vec = entries[i].vector;
5705                 adap->msix_info[i].idx = i;
5706         }
5707
5708         dev_info(adap->pdev_dev,
5709                  "%d MSI-X vectors allocated, nic %d eoqsets %d per uld %d\n",
5710                  allocated, s->max_ethqsets, s->eoqsets, s->nqs_per_uld);
5711
5712         kfree(entries);
5713         return 0;
5714
5715 out_disable_msix:
5716         pci_disable_msix(adap->pdev);
5717
5718 out_free:
5719         kfree(entries);
5720         return ret;
5721 }
5722
5723 #undef EXTRA_VECS
5724
5725 static int init_rss(struct adapter *adap)
5726 {
5727         unsigned int i;
5728         int err;
5729
5730         err = t4_init_rss_mode(adap, adap->mbox);
5731         if (err)
5732                 return err;
5733
5734         for_each_port(adap, i) {
5735                 struct port_info *pi = adap2pinfo(adap, i);
5736
5737                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5738                 if (!pi->rss)
5739                         return -ENOMEM;
5740         }
5741         return 0;
5742 }
5743
5744 /* Dump basic information about the adapter */
5745 static void print_adapter_info(struct adapter *adapter)
5746 {
5747         /* Hardware/Firmware/etc. Version/Revision IDs */
5748         t4_dump_version_info(adapter);
5749
5750         /* Software/Hardware configuration */
5751         dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5752                  is_offload(adapter) ? "R" : "",
5753                  ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
5754                   (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
5755                  is_offload(adapter) ? "Offload" : "non-Offload");
5756 }
5757
5758 static void print_port_info(const struct net_device *dev)
5759 {
5760         char buf[80];
5761         char *bufp = buf;
5762         const struct port_info *pi = netdev_priv(dev);
5763         const struct adapter *adap = pi->adapter;
5764
5765         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5766                 bufp += sprintf(bufp, "100M/");
5767         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5768                 bufp += sprintf(bufp, "1G/");
5769         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
5770                 bufp += sprintf(bufp, "10G/");
5771         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
5772                 bufp += sprintf(bufp, "25G/");
5773         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
5774                 bufp += sprintf(bufp, "40G/");
5775         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5776                 bufp += sprintf(bufp, "50G/");
5777         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
5778                 bufp += sprintf(bufp, "100G/");
5779         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5780                 bufp += sprintf(bufp, "200G/");
5781         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5782                 bufp += sprintf(bufp, "400G/");
5783         if (bufp != buf)
5784                 --bufp;
5785         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
5786
5787         netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5788                     dev->name, adap->params.vpd.id, adap->name, buf);
5789 }
5790
5791 /*
5792  * Free the following resources:
5793  * - memory used for tables
5794  * - MSI/MSI-X
5795  * - net devices
5796  * - resources FW is holding for us
5797  */
5798 static void free_some_resources(struct adapter *adapter)
5799 {
5800         unsigned int i;
5801
5802         kvfree(adapter->smt);
5803         kvfree(adapter->l2t);
5804         kvfree(adapter->srq);
5805         t4_cleanup_sched(adapter);
5806         kvfree(adapter->tids.tid_tab);
5807         cxgb4_cleanup_tc_matchall(adapter);
5808         cxgb4_cleanup_tc_mqprio(adapter);
5809         cxgb4_cleanup_tc_flower(adapter);
5810         cxgb4_cleanup_tc_u32(adapter);
5811         kfree(adapter->sge.egr_map);
5812         kfree(adapter->sge.ingr_map);
5813         kfree(adapter->sge.starving_fl);
5814         kfree(adapter->sge.txq_maperr);
5815 #ifdef CONFIG_DEBUG_FS
5816         kfree(adapter->sge.blocked_fl);
5817 #endif
5818         disable_msi(adapter);
5819
5820         for_each_port(adapter, i)
5821                 if (adapter->port[i]) {
5822                         struct port_info *pi = adap2pinfo(adapter, i);
5823
5824                         if (pi->viid != 0)
5825                                 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5826                                            0, pi->viid);
5827                         kfree(adap2pinfo(adapter, i)->rss);
5828                         free_netdev(adapter->port[i]);
5829                 }
5830         if (adapter->flags & CXGB4_FW_OK)
5831                 t4_fw_bye(adapter, adapter->pf);
5832 }
5833
5834 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
5835 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
5836                    NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
5837 #define SEGMENT_SIZE 128
5838
5839 static int t4_get_chip_type(struct adapter *adap, int ver)
5840 {
5841         u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
5842
5843         switch (ver) {
5844         case CHELSIO_T4:
5845                 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
5846         case CHELSIO_T5:
5847                 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5848         case CHELSIO_T6:
5849                 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5850         default:
5851                 break;
5852         }
5853         return -EINVAL;
5854 }
5855
5856 #ifdef CONFIG_PCI_IOV
5857 static void cxgb4_mgmt_setup(struct net_device *dev)
5858 {
5859         dev->type = ARPHRD_NONE;
5860         dev->mtu = 0;
5861         dev->hard_header_len = 0;
5862         dev->addr_len = 0;
5863         dev->tx_queue_len = 0;
5864         dev->flags |= IFF_NOARP;
5865         dev->priv_flags |= IFF_NO_QUEUE;
5866
5867         /* Initialize the device structure. */
5868         dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5869         dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
5870 }
5871
5872 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5873 {
5874         struct adapter *adap = pci_get_drvdata(pdev);
5875         int err = 0;
5876         int current_vfs = pci_num_vf(pdev);
5877         u32 pcie_fw;
5878
5879         pcie_fw = readl(adap->regs + PCIE_FW_A);
5880         /* Check if fw is initialized */
5881         if (!(pcie_fw & PCIE_FW_INIT_F)) {
5882                 dev_warn(&pdev->dev, "Device not initialized\n");
5883                 return -EOPNOTSUPP;
5884         }
5885
5886         /* If any of the VF's is already assigned to Guest OS, then
5887          * SRIOV for the same cannot be modified
5888          */
5889         if (current_vfs && pci_vfs_assigned(pdev)) {
5890                 dev_err(&pdev->dev,
5891                         "Cannot modify SR-IOV while VFs are assigned\n");
5892                 return current_vfs;
5893         }
5894         /* Note that the upper-level code ensures that we're never called with
5895          * a non-zero "num_vfs" when we already have VFs instantiated.  But
5896          * it never hurts to code defensively.
5897          */
5898         if (num_vfs != 0 && current_vfs != 0)
5899                 return -EBUSY;
5900
5901         /* Nothing to do for no change. */
5902         if (num_vfs == current_vfs)
5903                 return num_vfs;
5904
5905         /* Disable SRIOV when zero is passed. */
5906         if (!num_vfs) {
5907                 pci_disable_sriov(pdev);
5908                 /* free VF Management Interface */
5909                 unregister_netdev(adap->port[0]);
5910                 free_netdev(adap->port[0]);
5911                 adap->port[0] = NULL;
5912
5913                 /* free VF resources */
5914                 adap->num_vfs = 0;
5915                 kfree(adap->vfinfo);
5916                 adap->vfinfo = NULL;
5917                 return 0;
5918         }
5919
5920         if (!current_vfs) {
5921                 struct fw_pfvf_cmd port_cmd, port_rpl;
5922                 struct net_device *netdev;
5923                 unsigned int pmask, port;
5924                 struct pci_dev *pbridge;
5925                 struct port_info *pi;
5926                 char name[IFNAMSIZ];
5927                 u32 devcap2;
5928                 u16 flags;
5929
5930                 /* If we want to instantiate Virtual Functions, then our
5931                  * parent bridge's PCI-E needs to support Alternative Routing
5932                  * ID (ARI) because our VFs will show up at function offset 8
5933                  * and above.
5934                  */
5935                 pbridge = pdev->bus->self;
5936                 pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags);
5937                 pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2);
5938
5939                 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5940                     !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5941                         /* Our parent bridge does not support ARI so issue a
5942                          * warning and skip instantiating the VFs.  They
5943                          * won't be reachable.
5944                          */
5945                         dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5946                                  pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5947                                  PCI_FUNC(pbridge->devfn));
5948                         return -ENOTSUPP;
5949                 }
5950                 memset(&port_cmd, 0, sizeof(port_cmd));
5951                 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
5952                                                  FW_CMD_REQUEST_F |
5953                                                  FW_CMD_READ_F |
5954                                                  FW_PFVF_CMD_PFN_V(adap->pf) |
5955                                                  FW_PFVF_CMD_VFN_V(0));
5956                 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
5957                 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
5958                                  &port_rpl);
5959                 if (err)
5960                         return err;
5961                 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
5962                 port = ffs(pmask) - 1;
5963                 /* Allocate VF Management Interface. */
5964                 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
5965                          adap->pf);
5966                 netdev = alloc_netdev(sizeof(struct port_info),
5967                                       name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
5968                 if (!netdev)
5969                         return -ENOMEM;
5970
5971                 pi = netdev_priv(netdev);
5972                 pi->adapter = adap;
5973                 pi->lport = port;
5974                 pi->tx_chan = port;
5975                 SET_NETDEV_DEV(netdev, &pdev->dev);
5976
5977                 adap->port[0] = netdev;
5978                 pi->port_id = 0;
5979
5980                 err = register_netdev(adap->port[0]);
5981                 if (err) {
5982                         pr_info("Unable to register VF mgmt netdev %s\n", name);
5983                         free_netdev(adap->port[0]);
5984                         adap->port[0] = NULL;
5985                         return err;
5986                 }
5987                 /* Allocate and set up VF Information. */
5988                 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
5989                                        sizeof(struct vf_info), GFP_KERNEL);
5990                 if (!adap->vfinfo) {
5991                         unregister_netdev(adap->port[0]);
5992                         free_netdev(adap->port[0]);
5993                         adap->port[0] = NULL;
5994                         return -ENOMEM;
5995                 }
5996                 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
5997         }
5998         /* Instantiate the requested number of VFs. */
5999         err = pci_enable_sriov(pdev, num_vfs);
6000         if (err) {
6001                 pr_info("Unable to instantiate %d VFs\n", num_vfs);
6002                 if (!current_vfs) {
6003                         unregister_netdev(adap->port[0]);
6004                         free_netdev(adap->port[0]);
6005                         adap->port[0] = NULL;
6006                         kfree(adap->vfinfo);
6007                         adap->vfinfo = NULL;
6008                 }
6009                 return err;
6010         }
6011
6012         adap->num_vfs = num_vfs;
6013         return num_vfs;
6014 }
6015 #endif /* CONFIG_PCI_IOV */
6016
6017 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6018 {
6019         struct net_device *netdev;
6020         struct adapter *adapter;
6021         static int adap_idx = 1;
6022         int s_qpp, qpp, num_seg;
6023         struct port_info *pi;
6024         bool highdma = false;
6025         enum chip_type chip;
6026         void __iomem *regs;
6027         int func, chip_ver;
6028         u16 device_id;
6029         int i, err;
6030         u32 whoami;
6031
6032         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6033
6034         err = pci_request_regions(pdev, KBUILD_MODNAME);
6035         if (err) {
6036                 /* Just info, some other driver may have claimed the device. */
6037                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6038                 return err;
6039         }
6040
6041         err = pci_enable_device(pdev);
6042         if (err) {
6043                 dev_err(&pdev->dev, "cannot enable PCI device\n");
6044                 goto out_release_regions;
6045         }
6046
6047         regs = pci_ioremap_bar(pdev, 0);
6048         if (!regs) {
6049                 dev_err(&pdev->dev, "cannot map device registers\n");
6050                 err = -ENOMEM;
6051                 goto out_disable_device;
6052         }
6053
6054         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6055         if (!adapter) {
6056                 err = -ENOMEM;
6057                 goto out_unmap_bar0;
6058         }
6059
6060         adapter->regs = regs;
6061         err = t4_wait_dev_ready(regs);
6062         if (err < 0)
6063                 goto out_free_adapter;
6064
6065         /* We control everything through one PF */
6066         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
6067         pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
6068         chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
6069         if ((int)chip < 0) {
6070                 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
6071                 err = chip;
6072                 goto out_free_adapter;
6073         }
6074         chip_ver = CHELSIO_CHIP_VERSION(chip);
6075         func = chip_ver <= CHELSIO_T5 ?
6076                SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
6077
6078         adapter->pdev = pdev;
6079         adapter->pdev_dev = &pdev->dev;
6080         adapter->name = pci_name(pdev);
6081         adapter->mbox = func;
6082         adapter->pf = func;
6083         adapter->params.chip = chip;
6084         adapter->adap_idx = adap_idx;
6085         adapter->msg_enable = DFLT_MSG_ENABLE;
6086         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
6087                                     (sizeof(struct mbox_cmd) *
6088                                      T4_OS_LOG_MBOX_CMDS),
6089                                     GFP_KERNEL);
6090         if (!adapter->mbox_log) {
6091                 err = -ENOMEM;
6092                 goto out_free_adapter;
6093         }
6094         spin_lock_init(&adapter->mbox_lock);
6095         INIT_LIST_HEAD(&adapter->mlist.list);
6096         adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
6097         pci_set_drvdata(pdev, adapter);
6098
6099         if (func != ent->driver_data) {
6100                 pci_disable_device(pdev);
6101                 pci_save_state(pdev);        /* to restore SR-IOV later */
6102                 return 0;
6103         }
6104
6105         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6106                 highdma = true;
6107                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6108                 if (err) {
6109                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6110                                 "coherent allocations\n");
6111                         goto out_free_adapter;
6112                 }
6113         } else {
6114                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6115                 if (err) {
6116                         dev_err(&pdev->dev, "no usable DMA configuration\n");
6117                         goto out_free_adapter;
6118                 }
6119         }
6120
6121         pci_enable_pcie_error_reporting(pdev);
6122         pci_set_master(pdev);
6123         pci_save_state(pdev);
6124         adap_idx++;
6125         adapter->workq = create_singlethread_workqueue("cxgb4");
6126         if (!adapter->workq) {
6127                 err = -ENOMEM;
6128                 goto out_free_adapter;
6129         }
6130
6131         /* PCI device has been enabled */
6132         adapter->flags |= CXGB4_DEV_ENABLED;
6133         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6134
6135         /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
6136          * Ingress Packet Data to Free List Buffers in order to allow for
6137          * chipset performance optimizations between the Root Complex and
6138          * Memory Controllers.  (Messages to the associated Ingress Queue
6139          * notifying new Packet Placement in the Free Lists Buffers will be
6140          * send without the Relaxed Ordering Attribute thus guaranteeing that
6141          * all preceding PCIe Transaction Layer Packets will be processed
6142          * first.)  But some Root Complexes have various issues with Upstream
6143          * Transaction Layer Packets with the Relaxed Ordering Attribute set.
6144          * The PCIe devices which under the Root Complexes will be cleared the
6145          * Relaxed Ordering bit in the configuration space, So we check our
6146          * PCIe configuration space to see if it's flagged with advice against
6147          * using Relaxed Ordering.
6148          */
6149         if (!pcie_relaxed_ordering_enabled(pdev))
6150                 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
6151
6152         spin_lock_init(&adapter->stats_lock);
6153         spin_lock_init(&adapter->tid_release_lock);
6154         spin_lock_init(&adapter->win0_lock);
6155
6156         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6157         INIT_WORK(&adapter->db_full_task, process_db_full);
6158         INIT_WORK(&adapter->db_drop_task, process_db_drop);
6159         INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
6160
6161         err = t4_prep_adapter(adapter);
6162         if (err)
6163                 goto out_free_adapter;
6164
6165         if (is_kdump_kernel()) {
6166                 /* Collect hardware state and append to /proc/vmcore */
6167                 err = cxgb4_cudbg_vmcore_add_dump(adapter);
6168                 if (err) {
6169                         dev_warn(adapter->pdev_dev,
6170                                  "Fail collecting vmcore device dump, err: %d. Continuing\n",
6171                                  err);
6172                         err = 0;
6173                 }
6174         }
6175
6176         if (!is_t4(adapter->params.chip)) {
6177                 s_qpp = (QUEUESPERPAGEPF0_S +
6178                         (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
6179                         adapter->pf);
6180                 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
6181                       SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
6182                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6183
6184                 /* Each segment size is 128B. Write coalescing is enabled only
6185                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6186                  * queue is less no of segments that can be accommodated in
6187                  * a page size.
6188                  */
6189                 if (qpp > num_seg) {
6190                         dev_err(&pdev->dev,
6191                                 "Incorrect number of egress queues per page\n");
6192                         err = -EINVAL;
6193                         goto out_free_adapter;
6194                 }
6195                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6196                 pci_resource_len(pdev, 2));
6197                 if (!adapter->bar2) {
6198                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
6199                         err = -ENOMEM;
6200                         goto out_free_adapter;
6201                 }
6202         }
6203
6204         setup_memwin(adapter);
6205         err = adap_init0(adapter, 0);
6206 #ifdef CONFIG_DEBUG_FS
6207         bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
6208 #endif
6209         setup_memwin_rdma(adapter);
6210         if (err)
6211                 goto out_unmap_bar;
6212
6213         /* configure SGE_STAT_CFG_A to read WC stats */
6214         if (!is_t4(adapter->params.chip))
6215                 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
6216                              (is_t5(adapter->params.chip) ? STATMODE_V(0) :
6217                               T6_STATMODE_V(0)));
6218
6219         /* Initialize hash mac addr list */
6220         INIT_LIST_HEAD(&adapter->mac_hlist);
6221
6222         for_each_port(adapter, i) {
6223                 /* For supporting MQPRIO Offload, need some extra
6224                  * queues for each ETHOFLD TIDs. Keep it equal to
6225                  * MAX_ATIDs for now. Once we connect to firmware
6226                  * later and query the EOTID params, we'll come to
6227                  * know the actual # of EOTIDs supported.
6228                  */
6229                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6230                                            MAX_ETH_QSETS + MAX_ATIDS);
6231                 if (!netdev) {
6232                         err = -ENOMEM;
6233                         goto out_free_dev;
6234                 }
6235
6236                 SET_NETDEV_DEV(netdev, &pdev->dev);
6237
6238                 adapter->port[i] = netdev;
6239                 pi = netdev_priv(netdev);
6240                 pi->adapter = adapter;
6241                 pi->xact_addr_filt = -1;
6242                 pi->port_id = i;
6243                 netdev->irq = pdev->irq;
6244
6245                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6246                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6247                         NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO |
6248                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
6249                         NETIF_F_HW_TC;
6250
6251                 if (chip_ver > CHELSIO_T5) {
6252                         netdev->hw_enc_features |= NETIF_F_IP_CSUM |
6253                                                    NETIF_F_IPV6_CSUM |
6254                                                    NETIF_F_RXCSUM |
6255                                                    NETIF_F_GSO_UDP_TUNNEL |
6256                                                    NETIF_F_GSO_UDP_TUNNEL_CSUM |
6257                                                    NETIF_F_TSO | NETIF_F_TSO6;
6258
6259                         netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
6260                                                NETIF_F_GSO_UDP_TUNNEL_CSUM |
6261                                                NETIF_F_HW_TLS_RECORD;
6262                 }
6263
6264                 if (highdma)
6265                         netdev->hw_features |= NETIF_F_HIGHDMA;
6266                 netdev->features |= netdev->hw_features;
6267                 netdev->vlan_features = netdev->features & VLAN_FEAT;
6268
6269                 netdev->priv_flags |= IFF_UNICAST_FLT;
6270
6271                 /* MTU range: 81 - 9600 */
6272                 netdev->min_mtu = 81;              /* accommodate SACK */
6273                 netdev->max_mtu = MAX_MTU;
6274
6275                 netdev->netdev_ops = &cxgb4_netdev_ops;
6276 #ifdef CONFIG_CHELSIO_T4_DCB
6277                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6278                 cxgb4_dcb_state_init(netdev);
6279                 cxgb4_dcb_version_init(netdev);
6280 #endif
6281                 cxgb4_set_ethtool_ops(netdev);
6282         }
6283
6284         cxgb4_init_ethtool_dump(adapter);
6285
6286         pci_set_drvdata(pdev, adapter);
6287
6288         if (adapter->flags & CXGB4_FW_OK) {
6289                 err = t4_port_init(adapter, func, func, 0);
6290                 if (err)
6291                         goto out_free_dev;
6292         } else if (adapter->params.nports == 1) {
6293                 /* If we don't have a connection to the firmware -- possibly
6294                  * because of an error -- grab the raw VPD parameters so we
6295                  * can set the proper MAC Address on the debug network
6296                  * interface that we've created.
6297                  */
6298                 u8 hw_addr[ETH_ALEN];
6299                 u8 *na = adapter->params.vpd.na;
6300
6301                 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
6302                 if (!err) {
6303                         for (i = 0; i < ETH_ALEN; i++)
6304                                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
6305                                               hex2val(na[2 * i + 1]));
6306                         t4_set_hw_addr(adapter, 0, hw_addr);
6307                 }
6308         }
6309
6310         if (!(adapter->flags & CXGB4_FW_OK))
6311                 goto fw_attach_fail;
6312
6313         /* Configure queues and allocate tables now, they can be needed as
6314          * soon as the first register_netdev completes.
6315          */
6316         err = cfg_queues(adapter);
6317         if (err)
6318                 goto out_free_dev;
6319
6320         adapter->smt = t4_init_smt();
6321         if (!adapter->smt) {
6322                 /* We tolerate a lack of SMT, giving up some functionality */
6323                 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
6324         }
6325
6326         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
6327         if (!adapter->l2t) {
6328                 /* We tolerate a lack of L2T, giving up some functionality */
6329                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6330                 adapter->params.offload = 0;
6331         }
6332
6333 #if IS_ENABLED(CONFIG_IPV6)
6334         if (chip_ver <= CHELSIO_T5 &&
6335             (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
6336                 /* CLIP functionality is not present in hardware,
6337                  * hence disable all offload features
6338                  */
6339                 dev_warn(&pdev->dev,
6340                          "CLIP not enabled in hardware, continuing\n");
6341                 adapter->params.offload = 0;
6342         } else {
6343                 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
6344                                                   adapter->clipt_end);
6345                 if (!adapter->clipt) {
6346                         /* We tolerate a lack of clip_table, giving up
6347                          * some functionality
6348                          */
6349                         dev_warn(&pdev->dev,
6350                                  "could not allocate Clip table, continuing\n");
6351                         adapter->params.offload = 0;
6352                 }
6353         }
6354 #endif
6355
6356         for_each_port(adapter, i) {
6357                 pi = adap2pinfo(adapter, i);
6358                 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
6359                 if (!pi->sched_tbl)
6360                         dev_warn(&pdev->dev,
6361                                  "could not activate scheduling on port %d\n",
6362                                  i);
6363         }
6364
6365         if (tid_init(&adapter->tids) < 0) {
6366                 dev_warn(&pdev->dev, "could not allocate TID table, "
6367                          "continuing\n");
6368                 adapter->params.offload = 0;
6369         } else {
6370                 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
6371                 if (!adapter->tc_u32)
6372                         dev_warn(&pdev->dev,
6373                                  "could not offload tc u32, continuing\n");
6374
6375                 if (cxgb4_init_tc_flower(adapter))
6376                         dev_warn(&pdev->dev,
6377                                  "could not offload tc flower, continuing\n");
6378
6379                 if (cxgb4_init_tc_mqprio(adapter))
6380                         dev_warn(&pdev->dev,
6381                                  "could not offload tc mqprio, continuing\n");
6382
6383                 if (cxgb4_init_tc_matchall(adapter))
6384                         dev_warn(&pdev->dev,
6385                                  "could not offload tc matchall, continuing\n");
6386         }
6387
6388         if (is_offload(adapter) || is_hashfilter(adapter)) {
6389                 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
6390                         u32 hash_base, hash_reg;
6391
6392                         if (chip_ver <= CHELSIO_T5) {
6393                                 hash_reg = LE_DB_TID_HASHBASE_A;
6394                                 hash_base = t4_read_reg(adapter, hash_reg);
6395                                 adapter->tids.hash_base = hash_base / 4;
6396                         } else {
6397                                 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
6398                                 hash_base = t4_read_reg(adapter, hash_reg);
6399                                 adapter->tids.hash_base = hash_base;
6400                         }
6401                 }
6402         }
6403
6404         /* See what interrupts we'll be using */
6405         if (msi > 1 && enable_msix(adapter) == 0)
6406                 adapter->flags |= CXGB4_USING_MSIX;
6407         else if (msi > 0 && pci_enable_msi(pdev) == 0) {
6408                 adapter->flags |= CXGB4_USING_MSI;
6409                 if (msi > 1)
6410                         free_msix_info(adapter);
6411         }
6412
6413         /* check for PCI Express bandwidth capabiltites */
6414         pcie_print_link_status(pdev);
6415
6416         cxgb4_init_mps_ref_entries(adapter);
6417
6418         err = init_rss(adapter);
6419         if (err)
6420                 goto out_free_dev;
6421
6422         err = setup_non_data_intr(adapter);
6423         if (err) {
6424                 dev_err(adapter->pdev_dev,
6425                         "Non Data interrupt allocation failed, err: %d\n", err);
6426                 goto out_free_dev;
6427         }
6428
6429         err = setup_fw_sge_queues(adapter);
6430         if (err) {
6431                 dev_err(adapter->pdev_dev,
6432                         "FW sge queue allocation failed, err %d", err);
6433                 goto out_free_dev;
6434         }
6435
6436 fw_attach_fail:
6437         /*
6438          * The card is now ready to go.  If any errors occur during device
6439          * registration we do not fail the whole card but rather proceed only
6440          * with the ports we manage to register successfully.  However we must
6441          * register at least one net device.
6442          */
6443         for_each_port(adapter, i) {
6444                 pi = adap2pinfo(adapter, i);
6445                 adapter->port[i]->dev_port = pi->lport;
6446                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6447                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6448
6449                 netif_carrier_off(adapter->port[i]);
6450
6451                 err = register_netdev(adapter->port[i]);
6452                 if (err)
6453                         break;
6454                 adapter->chan_map[pi->tx_chan] = i;
6455                 print_port_info(adapter->port[i]);
6456         }
6457         if (i == 0) {
6458                 dev_err(&pdev->dev, "could not register any net devices\n");
6459                 goto out_free_dev;
6460         }
6461         if (err) {
6462                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6463                 err = 0;
6464         }
6465
6466         if (cxgb4_debugfs_root) {
6467                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6468                                                            cxgb4_debugfs_root);
6469                 setup_debugfs(adapter);
6470         }
6471
6472         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6473         pdev->needs_freset = 1;
6474
6475         if (is_uld(adapter)) {
6476                 mutex_lock(&uld_mutex);
6477                 list_add_tail(&adapter->list_node, &adapter_list);
6478                 mutex_unlock(&uld_mutex);
6479         }
6480
6481         if (!is_t4(adapter->params.chip))
6482                 cxgb4_ptp_init(adapter);
6483
6484         if (IS_REACHABLE(CONFIG_THERMAL) &&
6485             !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK))
6486                 cxgb4_thermal_init(adapter);
6487
6488         print_adapter_info(adapter);
6489         return 0;
6490
6491  out_free_dev:
6492         t4_free_sge_resources(adapter);
6493         free_some_resources(adapter);
6494         if (adapter->flags & CXGB4_USING_MSIX)
6495                 free_msix_info(adapter);
6496         if (adapter->num_uld || adapter->num_ofld_uld)
6497                 t4_uld_mem_free(adapter);
6498  out_unmap_bar:
6499         if (!is_t4(adapter->params.chip))
6500                 iounmap(adapter->bar2);
6501  out_free_adapter:
6502         if (adapter->workq)
6503                 destroy_workqueue(adapter->workq);
6504
6505         kfree(adapter->mbox_log);
6506         kfree(adapter);
6507  out_unmap_bar0:
6508         iounmap(regs);
6509  out_disable_device:
6510         pci_disable_pcie_error_reporting(pdev);
6511         pci_disable_device(pdev);
6512  out_release_regions:
6513         pci_release_regions(pdev);
6514         return err;
6515 }
6516
6517 static void remove_one(struct pci_dev *pdev)
6518 {
6519         struct adapter *adapter = pci_get_drvdata(pdev);
6520         struct hash_mac_addr *entry, *tmp;
6521
6522         if (!adapter) {
6523                 pci_release_regions(pdev);
6524                 return;
6525         }
6526
6527         /* If we allocated filters, free up state associated with any
6528          * valid filters ...
6529          */
6530         clear_all_filters(adapter);
6531
6532         adapter->flags |= CXGB4_SHUTTING_DOWN;
6533
6534         if (adapter->pf == 4) {
6535                 int i;
6536
6537                 /* Tear down per-adapter Work Queue first since it can contain
6538                  * references to our adapter data structure.
6539                  */
6540                 destroy_workqueue(adapter->workq);
6541
6542                 if (is_uld(adapter)) {
6543                         detach_ulds(adapter);
6544                         t4_uld_clean_up(adapter);
6545                 }
6546
6547                 adap_free_hma_mem(adapter);
6548
6549                 disable_interrupts(adapter);
6550
6551                 cxgb4_free_mps_ref_entries(adapter);
6552
6553                 for_each_port(adapter, i)
6554                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6555                                 unregister_netdev(adapter->port[i]);
6556
6557                 debugfs_remove_recursive(adapter->debugfs_root);
6558
6559                 if (!is_t4(adapter->params.chip))
6560                         cxgb4_ptp_stop(adapter);
6561                 if (IS_REACHABLE(CONFIG_THERMAL))
6562                         cxgb4_thermal_remove(adapter);
6563
6564                 if (adapter->flags & CXGB4_FULL_INIT_DONE)
6565                         cxgb_down(adapter);
6566
6567                 if (adapter->flags & CXGB4_USING_MSIX)
6568                         free_msix_info(adapter);
6569                 if (adapter->num_uld || adapter->num_ofld_uld)
6570                         t4_uld_mem_free(adapter);
6571                 free_some_resources(adapter);
6572                 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
6573                                          list) {
6574                         list_del(&entry->list);
6575                         kfree(entry);
6576                 }
6577
6578 #if IS_ENABLED(CONFIG_IPV6)
6579                 t4_cleanup_clip_tbl(adapter);
6580 #endif
6581                 if (!is_t4(adapter->params.chip))
6582                         iounmap(adapter->bar2);
6583         }
6584 #ifdef CONFIG_PCI_IOV
6585         else {
6586                 cxgb4_iov_configure(adapter->pdev, 0);
6587         }
6588 #endif
6589         iounmap(adapter->regs);
6590         pci_disable_pcie_error_reporting(pdev);
6591         if ((adapter->flags & CXGB4_DEV_ENABLED)) {
6592                 pci_disable_device(pdev);
6593                 adapter->flags &= ~CXGB4_DEV_ENABLED;
6594         }
6595         pci_release_regions(pdev);
6596         kfree(adapter->mbox_log);
6597         synchronize_rcu();
6598         kfree(adapter);
6599 }
6600
6601 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
6602  * delivery.  This is essentially a stripped down version of the PCI remove()
6603  * function where we do the minimal amount of work necessary to shutdown any
6604  * further activity.
6605  */
6606 static void shutdown_one(struct pci_dev *pdev)
6607 {
6608         struct adapter *adapter = pci_get_drvdata(pdev);
6609
6610         /* As with remove_one() above (see extended comment), we only want do
6611          * do cleanup on PCI Devices which went all the way through init_one()
6612          * ...
6613          */
6614         if (!adapter) {
6615                 pci_release_regions(pdev);
6616                 return;
6617         }
6618
6619         adapter->flags |= CXGB4_SHUTTING_DOWN;
6620
6621         if (adapter->pf == 4) {
6622                 int i;
6623
6624                 for_each_port(adapter, i)
6625                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6626                                 cxgb_close(adapter->port[i]);
6627
6628                 if (is_uld(adapter)) {
6629                         detach_ulds(adapter);
6630                         t4_uld_clean_up(adapter);
6631                 }
6632
6633                 disable_interrupts(adapter);
6634                 disable_msi(adapter);
6635
6636                 t4_sge_stop(adapter);
6637                 if (adapter->flags & CXGB4_FW_OK)
6638                         t4_fw_bye(adapter, adapter->mbox);
6639         }
6640 }
6641
6642 static struct pci_driver cxgb4_driver = {
6643         .name     = KBUILD_MODNAME,
6644         .id_table = cxgb4_pci_tbl,
6645         .probe    = init_one,
6646         .remove   = remove_one,
6647         .shutdown = shutdown_one,
6648 #ifdef CONFIG_PCI_IOV
6649         .sriov_configure = cxgb4_iov_configure,
6650 #endif
6651         .err_handler = &cxgb4_eeh,
6652 };
6653
6654 static int __init cxgb4_init_module(void)
6655 {
6656         int ret;
6657
6658         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6659
6660         ret = pci_register_driver(&cxgb4_driver);
6661         if (ret < 0)
6662                 goto err_pci;
6663
6664 #if IS_ENABLED(CONFIG_IPV6)
6665         if (!inet6addr_registered) {
6666                 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6667                 if (ret)
6668                         pci_unregister_driver(&cxgb4_driver);
6669                 else
6670                         inet6addr_registered = true;
6671         }
6672 #endif
6673
6674         if (ret == 0)
6675                 return ret;
6676
6677 err_pci:
6678         debugfs_remove(cxgb4_debugfs_root);
6679
6680         return ret;
6681 }
6682
6683 static void __exit cxgb4_cleanup_module(void)
6684 {
6685 #if IS_ENABLED(CONFIG_IPV6)
6686         if (inet6addr_registered) {
6687                 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6688                 inet6addr_registered = false;
6689         }
6690 #endif
6691         pci_unregister_driver(&cxgb4_driver);
6692         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6693 }
6694
6695 module_init(cxgb4_init_module);
6696 module_exit(cxgb4_cleanup_module);