2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <net/addrconf.h>
66 #include <asm/uaccess.h>
70 #include "t4_values.h"
73 #include "t4fw_version.h"
74 #include "cxgb4_dcb.h"
75 #include "cxgb4_debugfs.h"
79 char cxgb4_driver_name[] = KBUILD_MODNAME;
84 #define DRV_VERSION "2.0.0-ko"
85 const char cxgb4_driver_version[] = DRV_VERSION;
86 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
88 /* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
95 /* Administrative fields for filter.
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
109 struct ch_filter_specification fs;
112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116 /* Macros needed to support the PCI Device ID Table ...
118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
119 static const struct pci_device_id cxgb4_pci_tbl[] = {
120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127 #define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
134 #include "t4_pci_id_tbl.h"
136 #define FW4_FNAME "cxgb4/t4fw.bin"
137 #define FW5_FNAME "cxgb4/t5fw.bin"
138 #define FW6_FNAME "cxgb4/t6fw.bin"
139 #define FW4_CFNAME "cxgb4/t4-config.txt"
140 #define FW5_CFNAME "cxgb4/t5-config.txt"
141 #define FW6_CFNAME "cxgb4/t6-config.txt"
142 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
143 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
144 #define PHY_AQ1202_DEVICEID 0x4409
145 #define PHY_BCM84834_DEVICEID 0x4486
147 MODULE_DESCRIPTION(DRV_DESC);
148 MODULE_AUTHOR("Chelsio Communications");
149 MODULE_LICENSE("Dual BSD/GPL");
150 MODULE_VERSION(DRV_VERSION);
151 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
152 MODULE_FIRMWARE(FW4_FNAME);
153 MODULE_FIRMWARE(FW5_FNAME);
154 MODULE_FIRMWARE(FW6_FNAME);
157 * Normally we're willing to become the firmware's Master PF but will be happy
158 * if another PF has already become the Master and initialized the adapter.
159 * Setting "force_init" will cause this driver to forcibly establish itself as
160 * the Master PF and initialize the adapter.
162 static uint force_init;
164 module_param(force_init, uint, 0644);
165 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter,"
166 "deprecated parameter");
168 static int dflt_msg_enable = DFLT_MSG_ENABLE;
170 module_param(dflt_msg_enable, int, 0644);
171 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
174 * The driver uses the best interrupt scheme available on a platform in the
175 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
176 * of these schemes the driver may consider as follows:
178 * msi = 2: choose from among all three options
179 * msi = 1: only consider MSI and INTx interrupts
180 * msi = 0: force INTx interrupts
184 module_param(msi, int, 0644);
185 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
188 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
189 * offset by 2 bytes in order to have the IP headers line up on 4-byte
190 * boundaries. This is a requirement for many architectures which will throw
191 * a machine check fault if an attempt is made to access one of the 4-byte IP
192 * header fields on a non-4-byte boundary. And it's a major performance issue
193 * even on some architectures which allow it like some implementations of the
194 * x86 ISA. However, some architectures don't mind this and for some very
195 * edge-case performance sensitive applications (like forwarding large volumes
196 * of small packets), setting this DMA offset to 0 will decrease the number of
197 * PCI-E Bus transfers enough to measurably affect performance.
199 static int rx_dma_offset = 2;
201 #ifdef CONFIG_PCI_IOV
202 /* Configure the number of PCI-E Virtual Function which are to be instantiated
203 * on SR-IOV Capable Physical Functions.
205 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
207 module_param_array(num_vf, uint, NULL, 0644);
208 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
211 /* TX Queue select used to determine what algorithm to use for selecting TX
212 * queue. Select between the kernel provided function (select_queue=0) or user
213 * cxgb_select_queue function (select_queue=1)
215 * Default: select_queue=0
217 static int select_queue;
218 module_param(select_queue, int, 0644);
219 MODULE_PARM_DESC(select_queue,
220 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
222 static struct dentry *cxgb4_debugfs_root;
224 static LIST_HEAD(adapter_list);
225 static DEFINE_MUTEX(uld_mutex);
226 /* Adapter list to be accessed from atomic context */
227 static LIST_HEAD(adap_rcu_list);
228 static DEFINE_SPINLOCK(adap_rcu_lock);
229 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
230 static const char *const uld_str[] = { "RDMA", "iSCSI", "iSCSIT" };
232 static void link_report(struct net_device *dev)
234 if (!netif_carrier_ok(dev))
235 netdev_info(dev, "link down\n");
237 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
240 const struct port_info *p = netdev_priv(dev);
242 switch (p->link_cfg.speed) {
256 pr_info("%s: unsupported speed: %d\n",
257 dev->name, p->link_cfg.speed);
261 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
266 #ifdef CONFIG_CHELSIO_T4_DCB
267 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
268 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
270 struct port_info *pi = netdev_priv(dev);
271 struct adapter *adap = pi->adapter;
272 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
275 /* We use a simple mapping of Port TX Queue Index to DCB
276 * Priority when we're enabling DCB.
278 for (i = 0; i < pi->nqsets; i++, txq++) {
282 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
284 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
285 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
286 value = enable ? i : 0xffffffff;
288 /* Since we can be called while atomic (from "interrupt
289 * level") we need to issue the Set Parameters Commannd
290 * without sleeping (timeout < 0).
292 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
294 -FW_CMD_MAX_TIMEOUT);
297 dev_err(adap->pdev_dev,
298 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
299 enable ? "set" : "unset", pi->port_id, i, -err);
301 txq->dcb_prio = value;
304 #endif /* CONFIG_CHELSIO_T4_DCB */
306 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
308 struct net_device *dev = adapter->port[port_id];
310 /* Skip changes from disabled ports. */
311 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
313 netif_carrier_on(dev);
315 #ifdef CONFIG_CHELSIO_T4_DCB
316 cxgb4_dcb_state_init(dev);
317 dcb_tx_queue_prio_enable(dev, false);
318 #endif /* CONFIG_CHELSIO_T4_DCB */
319 netif_carrier_off(dev);
326 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
328 static const char *mod_str[] = {
329 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
332 const struct net_device *dev = adap->port[port_id];
333 const struct port_info *pi = netdev_priv(dev);
335 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
336 netdev_info(dev, "port module unplugged\n");
337 else if (pi->mod_type < ARRAY_SIZE(mod_str))
338 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
341 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
342 module_param(dbfifo_int_thresh, int, 0644);
343 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
346 * usecs to sleep while draining the dbfifo
348 static int dbfifo_drain_delay = 1000;
349 module_param(dbfifo_drain_delay, int, 0644);
350 MODULE_PARM_DESC(dbfifo_drain_delay,
351 "usecs to sleep while draining the dbfifo");
353 static inline int cxgb4_set_addr_hash(struct port_info *pi)
355 struct adapter *adap = pi->adapter;
358 struct hash_mac_addr *entry;
360 /* Calculate the hash vector for the updated list and program it */
361 list_for_each_entry(entry, &adap->mac_hlist, list) {
362 ucast |= is_unicast_ether_addr(entry->addr);
363 vec |= (1ULL << hash_mac_addr(entry->addr));
365 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
369 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
371 struct port_info *pi = netdev_priv(netdev);
372 struct adapter *adap = pi->adapter;
377 bool ucast = is_unicast_ether_addr(mac_addr);
378 const u8 *maclist[1] = {mac_addr};
379 struct hash_mac_addr *new_entry;
381 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
382 NULL, ucast ? &uhash : &mhash, false);
385 /* if hash != 0, then add the addr to hash addr list
386 * so on the end we will calculate the hash for the
387 * list and program it
389 if (uhash || mhash) {
390 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
393 ether_addr_copy(new_entry->addr, mac_addr);
394 list_add_tail(&new_entry->list, &adap->mac_hlist);
395 ret = cxgb4_set_addr_hash(pi);
398 return ret < 0 ? ret : 0;
401 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
403 struct port_info *pi = netdev_priv(netdev);
404 struct adapter *adap = pi->adapter;
406 const u8 *maclist[1] = {mac_addr};
407 struct hash_mac_addr *entry, *tmp;
409 /* If the MAC address to be removed is in the hash addr
410 * list, delete it from the list and update hash vector
412 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
413 if (ether_addr_equal(entry->addr, mac_addr)) {
414 list_del(&entry->list);
416 return cxgb4_set_addr_hash(pi);
420 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
421 return ret < 0 ? -EINVAL : 0;
425 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
426 * If @mtu is -1 it is left unchanged.
428 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
430 struct port_info *pi = netdev_priv(dev);
431 struct adapter *adapter = pi->adapter;
433 if (!(dev->flags & IFF_PROMISC)) {
434 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
435 if (!(dev->flags & IFF_ALLMULTI))
436 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
439 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
440 (dev->flags & IFF_PROMISC) ? 1 : 0,
441 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
446 * link_start - enable a port
447 * @dev: the port to enable
449 * Performs the MAC and PHY actions needed to enable a port.
451 static int link_start(struct net_device *dev)
454 struct port_info *pi = netdev_priv(dev);
455 unsigned int mb = pi->adapter->pf;
458 * We do not set address filters and promiscuity here, the stack does
459 * that step explicitly.
461 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
462 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
464 ret = t4_change_mac(pi->adapter, mb, pi->viid,
465 pi->xact_addr_filt, dev->dev_addr, true,
468 pi->xact_addr_filt = ret;
473 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
477 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
478 true, CXGB4_DCB_ENABLED);
485 int cxgb4_dcb_enabled(const struct net_device *dev)
487 #ifdef CONFIG_CHELSIO_T4_DCB
488 struct port_info *pi = netdev_priv(dev);
490 if (!pi->dcb.enabled)
493 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
494 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
499 EXPORT_SYMBOL(cxgb4_dcb_enabled);
501 #ifdef CONFIG_CHELSIO_T4_DCB
502 /* Handle a Data Center Bridging update message from the firmware. */
503 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
505 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
506 struct net_device *dev = adap->port[port];
507 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
510 cxgb4_dcb_handle_fw_update(adap, pcmd);
511 new_dcb_enabled = cxgb4_dcb_enabled(dev);
513 /* If the DCB has become enabled or disabled on the port then we're
514 * going to need to set up/tear down DCB Priority parameters for the
515 * TX Queues associated with the port.
517 if (new_dcb_enabled != old_dcb_enabled)
518 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
520 #endif /* CONFIG_CHELSIO_T4_DCB */
522 /* Clear a filter and release any of its resources that we own. This also
523 * clears the filter's "pending" status.
525 static void clear_filter(struct adapter *adap, struct filter_entry *f)
527 /* If the new or old filter have loopback rewriteing rules then we'll
528 * need to free any existing Layer Two Table (L2T) entries of the old
529 * filter rule. The firmware will handle freeing up any Source MAC
530 * Table (SMT) entries used for rewriting Source MAC Addresses in
534 cxgb4_l2t_release(f->l2t);
536 /* The zeroing of the filter rule below clears the filter valid,
537 * pending, locked flags, l2t pointer, etc. so it's all we need for
540 memset(f, 0, sizeof(*f));
543 /* Handle a filter write/deletion reply.
545 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
547 unsigned int idx = GET_TID(rpl);
548 unsigned int nidx = idx - adap->tids.ftid_base;
550 struct filter_entry *f;
552 if (idx >= adap->tids.ftid_base && nidx <
553 (adap->tids.nftids + adap->tids.nsftids)) {
555 ret = TCB_COOKIE_G(rpl->cookie);
556 f = &adap->tids.ftid_tab[idx];
558 if (ret == FW_FILTER_WR_FLT_DELETED) {
559 /* Clear the filter when we get confirmation from the
560 * hardware that the filter has been deleted.
562 clear_filter(adap, f);
563 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
564 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
566 clear_filter(adap, f);
567 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
568 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
569 f->pending = 0; /* asynchronous setup completed */
572 /* Something went wrong. Issue a warning about the
573 * problem and clear everything out.
575 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
577 clear_filter(adap, f);
582 /* Response queue handler for the FW event queue.
584 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
585 const struct pkt_gl *gl)
587 u8 opcode = ((const struct rss_header *)rsp)->opcode;
589 rsp++; /* skip RSS header */
591 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
593 if (unlikely(opcode == CPL_FW4_MSG &&
594 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
596 opcode = ((const struct rss_header *)rsp)->opcode;
598 if (opcode != CPL_SGE_EGR_UPDATE) {
599 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
605 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
606 const struct cpl_sge_egr_update *p = (void *)rsp;
607 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
610 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
612 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
613 struct sge_eth_txq *eq;
615 eq = container_of(txq, struct sge_eth_txq, q);
616 netif_tx_wake_queue(eq->txq);
618 struct sge_ofld_txq *oq;
620 oq = container_of(txq, struct sge_ofld_txq, q);
621 tasklet_schedule(&oq->qresume_tsk);
623 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
624 const struct cpl_fw6_msg *p = (void *)rsp;
626 #ifdef CONFIG_CHELSIO_T4_DCB
627 const struct fw_port_cmd *pcmd = (const void *)p->data;
628 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
629 unsigned int action =
630 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
632 if (cmd == FW_PORT_CMD &&
633 action == FW_PORT_ACTION_GET_PORT_INFO) {
634 int port = FW_PORT_CMD_PORTID_G(
635 be32_to_cpu(pcmd->op_to_portid));
636 struct net_device *dev = q->adap->port[port];
637 int state_input = ((pcmd->u.info.dcbxdis_pkd &
638 FW_PORT_CMD_DCBXDIS_F)
639 ? CXGB4_DCB_INPUT_FW_DISABLED
640 : CXGB4_DCB_INPUT_FW_ENABLED);
642 cxgb4_dcb_state_fsm(dev, state_input);
645 if (cmd == FW_PORT_CMD &&
646 action == FW_PORT_ACTION_L2_DCB_CFG)
647 dcb_rpl(q->adap, pcmd);
651 t4_handle_fw_rpl(q->adap, p->data);
652 } else if (opcode == CPL_L2T_WRITE_RPL) {
653 const struct cpl_l2t_write_rpl *p = (void *)rsp;
655 do_l2t_write_rpl(q->adap, p);
656 } else if (opcode == CPL_SET_TCB_RPL) {
657 const struct cpl_set_tcb_rpl *p = (void *)rsp;
659 filter_rpl(q->adap, p);
661 dev_err(q->adap->pdev_dev,
662 "unexpected CPL %#x on FW event queue\n", opcode);
667 /* Flush the aggregated lro sessions */
668 static void uldrx_flush_handler(struct sge_rspq *q)
670 if (ulds[q->uld].lro_flush)
671 ulds[q->uld].lro_flush(&q->lro_mgr);
675 * uldrx_handler - response queue handler for ULD queues
676 * @q: the response queue that received the packet
677 * @rsp: the response queue descriptor holding the offload message
678 * @gl: the gather list of packet fragments
680 * Deliver an ingress offload packet to a ULD. All processing is done by
681 * the ULD, we just maintain statistics.
683 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
684 const struct pkt_gl *gl)
686 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
689 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
691 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
692 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
695 if (q->flush_handler)
696 ret = ulds[q->uld].lro_rx_handler(q->adap->uld_handle[q->uld],
697 rsp, gl, &q->lro_mgr,
700 ret = ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld],
710 else if (gl == CXGB4_MSG_AN)
717 static void disable_msi(struct adapter *adapter)
719 if (adapter->flags & USING_MSIX) {
720 pci_disable_msix(adapter->pdev);
721 adapter->flags &= ~USING_MSIX;
722 } else if (adapter->flags & USING_MSI) {
723 pci_disable_msi(adapter->pdev);
724 adapter->flags &= ~USING_MSI;
729 * Interrupt handler for non-data events used with MSI-X.
731 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
733 struct adapter *adap = cookie;
734 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
738 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
740 if (adap->flags & MASTER_PF)
741 t4_slow_intr_handler(adap);
746 * Name the MSI-X interrupts.
748 static void name_msix_vecs(struct adapter *adap)
750 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
752 /* non-data interrupts */
753 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
756 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
757 adap->port[0]->name);
759 /* Ethernet queues */
760 for_each_port(adap, j) {
761 struct net_device *d = adap->port[j];
762 const struct port_info *pi = netdev_priv(d);
764 for (i = 0; i < pi->nqsets; i++, msi_idx++)
765 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
770 for_each_iscsirxq(&adap->sge, i)
771 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iscsi%d",
772 adap->port[0]->name, i);
774 for_each_iscsitrxq(&adap->sge, i)
775 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iSCSIT%d",
776 adap->port[0]->name, i);
778 for_each_rdmarxq(&adap->sge, i)
779 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
780 adap->port[0]->name, i);
782 for_each_rdmaciq(&adap->sge, i)
783 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
784 adap->port[0]->name, i);
787 static int request_msix_queue_irqs(struct adapter *adap)
789 struct sge *s = &adap->sge;
790 int err, ethqidx, iscsiqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
794 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
795 adap->msix_info[1].desc, &s->fw_evtq);
799 for_each_ethrxq(s, ethqidx) {
800 err = request_irq(adap->msix_info[msi_index].vec,
802 adap->msix_info[msi_index].desc,
803 &s->ethrxq[ethqidx].rspq);
808 for_each_iscsirxq(s, iscsiqidx) {
809 err = request_irq(adap->msix_info[msi_index].vec,
811 adap->msix_info[msi_index].desc,
812 &s->iscsirxq[iscsiqidx].rspq);
817 for_each_iscsitrxq(s, iscsitqidx) {
818 err = request_irq(adap->msix_info[msi_index].vec,
820 adap->msix_info[msi_index].desc,
821 &s->iscsitrxq[iscsitqidx].rspq);
826 for_each_rdmarxq(s, rdmaqidx) {
827 err = request_irq(adap->msix_info[msi_index].vec,
829 adap->msix_info[msi_index].desc,
830 &s->rdmarxq[rdmaqidx].rspq);
835 for_each_rdmaciq(s, rdmaciqqidx) {
836 err = request_irq(adap->msix_info[msi_index].vec,
838 adap->msix_info[msi_index].desc,
839 &s->rdmaciq[rdmaciqqidx].rspq);
847 while (--rdmaciqqidx >= 0)
848 free_irq(adap->msix_info[--msi_index].vec,
849 &s->rdmaciq[rdmaciqqidx].rspq);
850 while (--rdmaqidx >= 0)
851 free_irq(adap->msix_info[--msi_index].vec,
852 &s->rdmarxq[rdmaqidx].rspq);
853 while (--iscsitqidx >= 0)
854 free_irq(adap->msix_info[--msi_index].vec,
855 &s->iscsitrxq[iscsitqidx].rspq);
856 while (--iscsiqidx >= 0)
857 free_irq(adap->msix_info[--msi_index].vec,
858 &s->iscsirxq[iscsiqidx].rspq);
859 while (--ethqidx >= 0)
860 free_irq(adap->msix_info[--msi_index].vec,
861 &s->ethrxq[ethqidx].rspq);
862 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
866 static void free_msix_queue_irqs(struct adapter *adap)
868 int i, msi_index = 2;
869 struct sge *s = &adap->sge;
871 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
872 for_each_ethrxq(s, i)
873 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
874 for_each_iscsirxq(s, i)
875 free_irq(adap->msix_info[msi_index++].vec,
876 &s->iscsirxq[i].rspq);
877 for_each_iscsitrxq(s, i)
878 free_irq(adap->msix_info[msi_index++].vec,
879 &s->iscsitrxq[i].rspq);
880 for_each_rdmarxq(s, i)
881 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
882 for_each_rdmaciq(s, i)
883 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
887 * cxgb4_write_rss - write the RSS table for a given port
889 * @queues: array of queue indices for RSS
891 * Sets up the portion of the HW RSS table for the port's VI to distribute
892 * packets to the Rx queues in @queues.
893 * Should never be called before setting up sge eth rx queues
895 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
899 struct adapter *adapter = pi->adapter;
900 const struct sge_eth_rxq *rxq;
902 rxq = &adapter->sge.ethrxq[pi->first_qset];
903 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
907 /* map the queue indices to queue ids */
908 for (i = 0; i < pi->rss_size; i++, queues++)
909 rss[i] = rxq[*queues].rspq.abs_id;
911 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
912 pi->rss_size, rss, pi->rss_size);
913 /* If Tunnel All Lookup isn't specified in the global RSS
914 * Configuration, then we need to specify a default Ingress
915 * Queue for any ingress packets which aren't hashed. We'll
916 * use our first ingress queue ...
919 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
920 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
921 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
922 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
923 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
924 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
931 * setup_rss - configure RSS
934 * Sets up RSS for each port.
936 static int setup_rss(struct adapter *adap)
940 for_each_port(adap, i) {
941 const struct port_info *pi = adap2pinfo(adap, i);
943 /* Fill default values with equal distribution */
944 for (j = 0; j < pi->rss_size; j++)
945 pi->rss[j] = j % pi->nqsets;
947 err = cxgb4_write_rss(pi, pi->rss);
955 * Return the channel of the ingress queue with the given qid.
957 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
959 qid -= p->ingr_start;
960 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
964 * Wait until all NAPI handlers are descheduled.
966 static void quiesce_rx(struct adapter *adap)
970 for (i = 0; i < adap->sge.ingr_sz; i++) {
971 struct sge_rspq *q = adap->sge.ingr_map[i];
973 if (q && q->handler) {
974 napi_disable(&q->napi);
976 while (!cxgb_poll_lock_napi(q))
984 /* Disable interrupt and napi handler */
985 static void disable_interrupts(struct adapter *adap)
987 if (adap->flags & FULL_INIT_DONE) {
988 t4_intr_disable(adap);
989 if (adap->flags & USING_MSIX) {
990 free_msix_queue_irqs(adap);
991 free_irq(adap->msix_info[0].vec, adap);
993 free_irq(adap->pdev->irq, adap);
1000 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1002 static void enable_rx(struct adapter *adap)
1006 for (i = 0; i < adap->sge.ingr_sz; i++) {
1007 struct sge_rspq *q = adap->sge.ingr_map[i];
1012 cxgb_busy_poll_init_lock(q);
1013 napi_enable(&q->napi);
1015 /* 0-increment GTS to start the timer and enable interrupts */
1016 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
1017 SEINTARM_V(q->intr_params) |
1018 INGRESSQID_V(q->cntxt_id));
1022 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
1023 unsigned int nq, unsigned int per_chan, int msi_idx,
1028 for (i = 0; i < nq; i++, q++) {
1031 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
1032 adap->port[i / per_chan],
1033 msi_idx, q->fl.size ? &q->fl : NULL,
1035 lro ? uldrx_flush_handler : NULL,
1039 memset(&q->stats, 0, sizeof(q->stats));
1041 ids[i] = q->rspq.abs_id;
1047 * setup_sge_queues - configure SGE Tx/Rx/response queues
1048 * @adap: the adapter
1050 * Determines how many sets of SGE queues to use and initializes them.
1051 * We support multiple queue sets per port if we have MSI-X, otherwise
1052 * just one queue set per port.
1054 static int setup_sge_queues(struct adapter *adap)
1056 int err, msi_idx, i, j;
1057 struct sge *s = &adap->sge;
1059 bitmap_zero(s->starving_fl, s->egr_sz);
1060 bitmap_zero(s->txq_maperr, s->egr_sz);
1062 if (adap->flags & USING_MSIX)
1063 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1065 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1066 NULL, NULL, NULL, -1);
1069 msi_idx = -((int)s->intrq.abs_id + 1);
1072 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1073 * don't forget to update the following which need to be
1074 * synchronized to and changes here.
1076 * 1. The calculations of MAX_INGQ in cxgb4.h.
1078 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1079 * to accommodate any new/deleted Ingress Queues
1080 * which need MSI-X Vectors.
1082 * 3. Update sge_qinfo_show() to include information on the
1083 * new/deleted queues.
1085 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1086 msi_idx, NULL, fwevtq_handler, NULL, -1);
1088 freeout: t4_free_sge_resources(adap);
1092 for_each_port(adap, i) {
1093 struct net_device *dev = adap->port[i];
1094 struct port_info *pi = netdev_priv(dev);
1095 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1096 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1098 for (j = 0; j < pi->nqsets; j++, q++) {
1101 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1105 t4_get_mps_bg_map(adap,
1110 memset(&q->stats, 0, sizeof(q->stats));
1112 for (j = 0; j < pi->nqsets; j++, t++) {
1113 err = t4_sge_alloc_eth_txq(adap, t, dev,
1114 netdev_get_tx_queue(dev, j),
1115 s->fw_evtq.cntxt_id);
1121 j = s->iscsiqsets / adap->params.nports; /* iscsi queues per channel */
1122 for_each_iscsirxq(s, i) {
1123 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1125 s->fw_evtq.cntxt_id);
1130 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids, lro) do { \
1131 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids, lro); \
1138 ALLOC_OFLD_RXQS(s->iscsirxq, s->iscsiqsets, j, s->iscsi_rxq, false);
1139 ALLOC_OFLD_RXQS(s->iscsitrxq, s->niscsitq, j, s->iscsit_rxq, true);
1140 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq, false);
1141 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1142 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq, false);
1144 #undef ALLOC_OFLD_RXQS
1146 for_each_port(adap, i) {
1148 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1149 * have RDMA queues, and that's the right value.
1151 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1152 s->fw_evtq.cntxt_id,
1153 s->rdmarxq[i].rspq.cntxt_id);
1158 t4_write_reg(adap, is_t4(adap->params.chip) ?
1159 MPS_TRC_RSS_CONTROL_A :
1160 MPS_T5_TRC_RSS_CONTROL_A,
1161 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1162 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1167 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1168 * The allocated memory is cleared.
1170 void *t4_alloc_mem(size_t size)
1172 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1180 * Free memory allocated through alloc_mem().
1182 void t4_free_mem(void *addr)
1187 /* Send a Work Request to write the filter at a specified index. We construct
1188 * a Firmware Filter Work Request to have the work done and put the indicated
1189 * filter into "pending" mode which will prevent any further actions against
1190 * it till we get a reply from the firmware on the completion status of the
1193 static int set_filter_wr(struct adapter *adapter, int fidx)
1195 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1196 struct sk_buff *skb;
1197 struct fw_filter_wr *fwr;
1200 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1204 /* If the new filter requires loopback Destination MAC and/or VLAN
1205 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1208 if (f->fs.newdmac || f->fs.newvlan) {
1209 /* allocate L2T entry for new filter */
1210 f->l2t = t4_l2t_alloc_switching(adapter, f->fs.vlan,
1211 f->fs.eport, f->fs.dmac);
1212 if (f->l2t == NULL) {
1218 ftid = adapter->tids.ftid_base + fidx;
1220 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1221 memset(fwr, 0, sizeof(*fwr));
1223 /* It would be nice to put most of the following in t4_hw.c but most
1224 * of the work is translating the cxgbtool ch_filter_specification
1225 * into the Work Request and the definition of that structure is
1226 * currently in cxgbtool.h which isn't appropriate to pull into the
1227 * common code. We may eventually try to come up with a more neutral
1228 * filter specification structure but for now it's easiest to simply
1229 * put this fairly direct code in line ...
1231 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1232 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1234 htonl(FW_FILTER_WR_TID_V(ftid) |
1235 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1236 FW_FILTER_WR_NOREPLY_V(0) |
1237 FW_FILTER_WR_IQ_V(f->fs.iq));
1238 fwr->del_filter_to_l2tix =
1239 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1240 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1241 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1242 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1243 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1244 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1245 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1246 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1247 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1248 f->fs.newvlan == VLAN_REWRITE) |
1249 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1250 f->fs.newvlan == VLAN_REWRITE) |
1251 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1252 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1253 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1254 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1255 fwr->ethtype = htons(f->fs.val.ethtype);
1256 fwr->ethtypem = htons(f->fs.mask.ethtype);
1257 fwr->frag_to_ovlan_vldm =
1258 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1259 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1260 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1261 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1262 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1263 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1265 fwr->rx_chan_rx_rpl_iq =
1266 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1267 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1268 fwr->maci_to_matchtypem =
1269 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1270 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1271 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1272 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1273 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1274 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1275 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1276 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1277 fwr->ptcl = f->fs.val.proto;
1278 fwr->ptclm = f->fs.mask.proto;
1279 fwr->ttyp = f->fs.val.tos;
1280 fwr->ttypm = f->fs.mask.tos;
1281 fwr->ivlan = htons(f->fs.val.ivlan);
1282 fwr->ivlanm = htons(f->fs.mask.ivlan);
1283 fwr->ovlan = htons(f->fs.val.ovlan);
1284 fwr->ovlanm = htons(f->fs.mask.ovlan);
1285 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1286 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1287 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1288 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1289 fwr->lp = htons(f->fs.val.lport);
1290 fwr->lpm = htons(f->fs.mask.lport);
1291 fwr->fp = htons(f->fs.val.fport);
1292 fwr->fpm = htons(f->fs.mask.fport);
1294 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1296 /* Mark the filter as "pending" and ship off the Filter Work Request.
1297 * When we get the Work Request Reply we'll clear the pending status.
1300 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1301 t4_ofld_send(adapter, skb);
1305 /* Delete the filter at a specified index.
1307 static int del_filter_wr(struct adapter *adapter, int fidx)
1309 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1310 struct sk_buff *skb;
1311 struct fw_filter_wr *fwr;
1312 unsigned int len, ftid;
1315 ftid = adapter->tids.ftid_base + fidx;
1317 skb = alloc_skb(len, GFP_KERNEL);
1321 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1322 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1324 /* Mark the filter as "pending" and ship off the Filter Work Request.
1325 * When we get the Work Request Reply we'll clear the pending status.
1328 t4_mgmt_tx(adapter, skb);
1332 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1333 void *accel_priv, select_queue_fallback_t fallback)
1337 #ifdef CONFIG_CHELSIO_T4_DCB
1338 /* If a Data Center Bridging has been successfully negotiated on this
1339 * link then we'll use the skb's priority to map it to a TX Queue.
1340 * The skb's priority is determined via the VLAN Tag Priority Code
1343 if (cxgb4_dcb_enabled(dev)) {
1347 err = vlan_get_tag(skb, &vlan_tci);
1348 if (unlikely(err)) {
1349 if (net_ratelimit())
1351 "TX Packet without VLAN Tag on DCB Link\n");
1354 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1355 #ifdef CONFIG_CHELSIO_T4_FCOE
1356 if (skb->protocol == htons(ETH_P_FCOE))
1357 txq = skb->priority & 0x7;
1358 #endif /* CONFIG_CHELSIO_T4_FCOE */
1362 #endif /* CONFIG_CHELSIO_T4_DCB */
1365 txq = (skb_rx_queue_recorded(skb)
1366 ? skb_get_rx_queue(skb)
1367 : smp_processor_id());
1369 while (unlikely(txq >= dev->real_num_tx_queues))
1370 txq -= dev->real_num_tx_queues;
1375 return fallback(dev, skb) % dev->real_num_tx_queues;
1378 static int closest_timer(const struct sge *s, int time)
1380 int i, delta, match = 0, min_delta = INT_MAX;
1382 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1383 delta = time - s->timer_val[i];
1386 if (delta < min_delta) {
1394 static int closest_thres(const struct sge *s, int thres)
1396 int i, delta, match = 0, min_delta = INT_MAX;
1398 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1399 delta = thres - s->counter_val[i];
1402 if (delta < min_delta) {
1411 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1413 * @us: the hold-off time in us, or 0 to disable timer
1414 * @cnt: the hold-off packet count, or 0 to disable counter
1416 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1417 * one of the two needs to be enabled for the queue to generate interrupts.
1419 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1420 unsigned int us, unsigned int cnt)
1422 struct adapter *adap = q->adap;
1424 if ((us | cnt) == 0)
1431 new_idx = closest_thres(&adap->sge, cnt);
1432 if (q->desc && q->pktcnt_idx != new_idx) {
1433 /* the queue has already been created, update it */
1434 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1435 FW_PARAMS_PARAM_X_V(
1436 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1437 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1438 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1443 q->pktcnt_idx = new_idx;
1446 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1447 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1451 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1453 const struct port_info *pi = netdev_priv(dev);
1454 netdev_features_t changed = dev->features ^ features;
1457 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1460 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1462 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1464 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1468 static int setup_debugfs(struct adapter *adap)
1470 if (IS_ERR_OR_NULL(adap->debugfs_root))
1473 #ifdef CONFIG_DEBUG_FS
1474 t4_setup_debugfs(adap);
1480 * upper-layer driver support
1484 * Allocate an active-open TID and set it to the supplied value.
1486 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1490 spin_lock_bh(&t->atid_lock);
1492 union aopen_entry *p = t->afree;
1494 atid = (p - t->atid_tab) + t->atid_base;
1499 spin_unlock_bh(&t->atid_lock);
1502 EXPORT_SYMBOL(cxgb4_alloc_atid);
1505 * Release an active-open TID.
1507 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1509 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1511 spin_lock_bh(&t->atid_lock);
1515 spin_unlock_bh(&t->atid_lock);
1517 EXPORT_SYMBOL(cxgb4_free_atid);
1520 * Allocate a server TID and set it to the supplied value.
1522 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1526 spin_lock_bh(&t->stid_lock);
1527 if (family == PF_INET) {
1528 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1529 if (stid < t->nstids)
1530 __set_bit(stid, t->stid_bmap);
1534 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1539 t->stid_tab[stid].data = data;
1540 stid += t->stid_base;
1541 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1542 * This is equivalent to 4 TIDs. With CLIP enabled it
1545 if (family == PF_INET)
1548 t->stids_in_use += 2;
1550 spin_unlock_bh(&t->stid_lock);
1553 EXPORT_SYMBOL(cxgb4_alloc_stid);
1555 /* Allocate a server filter TID and set it to the supplied value.
1557 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1561 spin_lock_bh(&t->stid_lock);
1562 if (family == PF_INET) {
1563 stid = find_next_zero_bit(t->stid_bmap,
1564 t->nstids + t->nsftids, t->nstids);
1565 if (stid < (t->nstids + t->nsftids))
1566 __set_bit(stid, t->stid_bmap);
1573 t->stid_tab[stid].data = data;
1575 stid += t->sftid_base;
1578 spin_unlock_bh(&t->stid_lock);
1581 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1583 /* Release a server TID.
1585 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1587 /* Is it a server filter TID? */
1588 if (t->nsftids && (stid >= t->sftid_base)) {
1589 stid -= t->sftid_base;
1592 stid -= t->stid_base;
1595 spin_lock_bh(&t->stid_lock);
1596 if (family == PF_INET)
1597 __clear_bit(stid, t->stid_bmap);
1599 bitmap_release_region(t->stid_bmap, stid, 1);
1600 t->stid_tab[stid].data = NULL;
1601 if (stid < t->nstids) {
1602 if (family == PF_INET)
1605 t->stids_in_use -= 2;
1609 spin_unlock_bh(&t->stid_lock);
1611 EXPORT_SYMBOL(cxgb4_free_stid);
1614 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1616 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1619 struct cpl_tid_release *req;
1621 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1622 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1623 INIT_TP_WR(req, tid);
1624 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1628 * Queue a TID release request and if necessary schedule a work queue to
1631 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1634 void **p = &t->tid_tab[tid];
1635 struct adapter *adap = container_of(t, struct adapter, tids);
1637 spin_lock_bh(&adap->tid_release_lock);
1638 *p = adap->tid_release_head;
1639 /* Low 2 bits encode the Tx channel number */
1640 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1641 if (!adap->tid_release_task_busy) {
1642 adap->tid_release_task_busy = true;
1643 queue_work(adap->workq, &adap->tid_release_task);
1645 spin_unlock_bh(&adap->tid_release_lock);
1649 * Process the list of pending TID release requests.
1651 static void process_tid_release_list(struct work_struct *work)
1653 struct sk_buff *skb;
1654 struct adapter *adap;
1656 adap = container_of(work, struct adapter, tid_release_task);
1658 spin_lock_bh(&adap->tid_release_lock);
1659 while (adap->tid_release_head) {
1660 void **p = adap->tid_release_head;
1661 unsigned int chan = (uintptr_t)p & 3;
1662 p = (void *)p - chan;
1664 adap->tid_release_head = *p;
1666 spin_unlock_bh(&adap->tid_release_lock);
1668 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1670 schedule_timeout_uninterruptible(1);
1672 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1673 t4_ofld_send(adap, skb);
1674 spin_lock_bh(&adap->tid_release_lock);
1676 adap->tid_release_task_busy = false;
1677 spin_unlock_bh(&adap->tid_release_lock);
1681 * Release a TID and inform HW. If we are unable to allocate the release
1682 * message we defer to a work queue.
1684 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1686 struct sk_buff *skb;
1687 struct adapter *adap = container_of(t, struct adapter, tids);
1689 WARN_ON(tid >= t->ntids);
1691 if (t->tid_tab[tid]) {
1692 t->tid_tab[tid] = NULL;
1693 if (t->hash_base && (tid >= t->hash_base))
1694 atomic_dec(&t->hash_tids_in_use);
1696 atomic_dec(&t->tids_in_use);
1699 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1701 mk_tid_release(skb, chan, tid);
1702 t4_ofld_send(adap, skb);
1704 cxgb4_queue_tid_release(t, chan, tid);
1706 EXPORT_SYMBOL(cxgb4_remove_tid);
1709 * Allocate and initialize the TID tables. Returns 0 on success.
1711 static int tid_init(struct tid_info *t)
1714 unsigned int stid_bmap_size;
1715 unsigned int natids = t->natids;
1716 struct adapter *adap = container_of(t, struct adapter, tids);
1718 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1719 size = t->ntids * sizeof(*t->tid_tab) +
1720 natids * sizeof(*t->atid_tab) +
1721 t->nstids * sizeof(*t->stid_tab) +
1722 t->nsftids * sizeof(*t->stid_tab) +
1723 stid_bmap_size * sizeof(long) +
1724 t->nftids * sizeof(*t->ftid_tab) +
1725 t->nsftids * sizeof(*t->ftid_tab);
1727 t->tid_tab = t4_alloc_mem(size);
1731 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1732 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1733 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1734 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1735 spin_lock_init(&t->stid_lock);
1736 spin_lock_init(&t->atid_lock);
1738 t->stids_in_use = 0;
1739 t->sftids_in_use = 0;
1741 t->atids_in_use = 0;
1742 atomic_set(&t->tids_in_use, 0);
1743 atomic_set(&t->hash_tids_in_use, 0);
1745 /* Setup the free list for atid_tab and clear the stid bitmap. */
1748 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1749 t->afree = t->atid_tab;
1751 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1752 /* Reserve stid 0 for T4/T5 adapters */
1753 if (!t->stid_base &&
1754 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
1755 __set_bit(0, t->stid_bmap);
1761 * cxgb4_create_server - create an IP server
1763 * @stid: the server TID
1764 * @sip: local IP address to bind server to
1765 * @sport: the server's TCP port
1766 * @queue: queue to direct messages from this server to
1768 * Create an IP server for the given port and address.
1769 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1771 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1772 __be32 sip, __be16 sport, __be16 vlan,
1776 struct sk_buff *skb;
1777 struct adapter *adap;
1778 struct cpl_pass_open_req *req;
1781 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1785 adap = netdev2adap(dev);
1786 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1788 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1789 req->local_port = sport;
1790 req->peer_port = htons(0);
1791 req->local_ip = sip;
1792 req->peer_ip = htonl(0);
1793 chan = rxq_to_chan(&adap->sge, queue);
1794 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1795 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1796 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1797 ret = t4_mgmt_tx(adap, skb);
1798 return net_xmit_eval(ret);
1800 EXPORT_SYMBOL(cxgb4_create_server);
1802 /* cxgb4_create_server6 - create an IPv6 server
1804 * @stid: the server TID
1805 * @sip: local IPv6 address to bind server to
1806 * @sport: the server's TCP port
1807 * @queue: queue to direct messages from this server to
1809 * Create an IPv6 server for the given port and address.
1810 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1812 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1813 const struct in6_addr *sip, __be16 sport,
1817 struct sk_buff *skb;
1818 struct adapter *adap;
1819 struct cpl_pass_open_req6 *req;
1822 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1826 adap = netdev2adap(dev);
1827 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1829 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1830 req->local_port = sport;
1831 req->peer_port = htons(0);
1832 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1833 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1834 req->peer_ip_hi = cpu_to_be64(0);
1835 req->peer_ip_lo = cpu_to_be64(0);
1836 chan = rxq_to_chan(&adap->sge, queue);
1837 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1838 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1839 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1840 ret = t4_mgmt_tx(adap, skb);
1841 return net_xmit_eval(ret);
1843 EXPORT_SYMBOL(cxgb4_create_server6);
1845 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1846 unsigned int queue, bool ipv6)
1848 struct sk_buff *skb;
1849 struct adapter *adap;
1850 struct cpl_close_listsvr_req *req;
1853 adap = netdev2adap(dev);
1855 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1859 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1861 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1862 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1863 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1864 ret = t4_mgmt_tx(adap, skb);
1865 return net_xmit_eval(ret);
1867 EXPORT_SYMBOL(cxgb4_remove_server);
1870 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1871 * @mtus: the HW MTU table
1872 * @mtu: the target MTU
1873 * @idx: index of selected entry in the MTU table
1875 * Returns the index and the value in the HW MTU table that is closest to
1876 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1877 * table, in which case that smallest available value is selected.
1879 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1884 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1890 EXPORT_SYMBOL(cxgb4_best_mtu);
1893 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1894 * @mtus: the HW MTU table
1895 * @header_size: Header Size
1896 * @data_size_max: maximum Data Segment Size
1897 * @data_size_align: desired Data Segment Size Alignment (2^N)
1898 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1900 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1901 * MTU Table based solely on a Maximum MTU parameter, we break that
1902 * parameter up into a Header Size and Maximum Data Segment Size, and
1903 * provide a desired Data Segment Size Alignment. If we find an MTU in
1904 * the Hardware MTU Table which will result in a Data Segment Size with
1905 * the requested alignment _and_ that MTU isn't "too far" from the
1906 * closest MTU, then we'll return that rather than the closest MTU.
1908 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1909 unsigned short header_size,
1910 unsigned short data_size_max,
1911 unsigned short data_size_align,
1912 unsigned int *mtu_idxp)
1914 unsigned short max_mtu = header_size + data_size_max;
1915 unsigned short data_size_align_mask = data_size_align - 1;
1916 int mtu_idx, aligned_mtu_idx;
1918 /* Scan the MTU Table till we find an MTU which is larger than our
1919 * Maximum MTU or we reach the end of the table. Along the way,
1920 * record the last MTU found, if any, which will result in a Data
1921 * Segment Length matching the requested alignment.
1923 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1924 unsigned short data_size = mtus[mtu_idx] - header_size;
1926 /* If this MTU minus the Header Size would result in a
1927 * Data Segment Size of the desired alignment, remember it.
1929 if ((data_size & data_size_align_mask) == 0)
1930 aligned_mtu_idx = mtu_idx;
1932 /* If we're not at the end of the Hardware MTU Table and the
1933 * next element is larger than our Maximum MTU, drop out of
1936 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1940 /* If we fell out of the loop because we ran to the end of the table,
1941 * then we just have to use the last [largest] entry.
1943 if (mtu_idx == NMTUS)
1946 /* If we found an MTU which resulted in the requested Data Segment
1947 * Length alignment and that's "not far" from the largest MTU which is
1948 * less than or equal to the maximum MTU, then use that.
1950 if (aligned_mtu_idx >= 0 &&
1951 mtu_idx - aligned_mtu_idx <= 1)
1952 mtu_idx = aligned_mtu_idx;
1954 /* If the caller has passed in an MTU Index pointer, pass the
1955 * MTU Index back. Return the MTU value.
1958 *mtu_idxp = mtu_idx;
1959 return mtus[mtu_idx];
1961 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1964 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1966 * @viid: VI id of the given port
1968 * Return the SMT index for this VI.
1970 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1972 /* In T4/T5, SMT contains 256 SMAC entries organized in
1973 * 128 rows of 2 entries each.
1974 * In T6, SMT contains 256 SMAC entries in 256 rows.
1975 * TODO: The below code needs to be updated when we add support
1978 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1979 return ((viid & 0x7f) << 1);
1981 return (viid & 0x7f);
1983 EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1986 * cxgb4_port_chan - get the HW channel of a port
1987 * @dev: the net device for the port
1989 * Return the HW Tx channel of the given port.
1991 unsigned int cxgb4_port_chan(const struct net_device *dev)
1993 return netdev2pinfo(dev)->tx_chan;
1995 EXPORT_SYMBOL(cxgb4_port_chan);
1997 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1999 struct adapter *adap = netdev2adap(dev);
2000 u32 v1, v2, lp_count, hp_count;
2002 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2003 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2004 if (is_t4(adap->params.chip)) {
2005 lp_count = LP_COUNT_G(v1);
2006 hp_count = HP_COUNT_G(v1);
2008 lp_count = LP_COUNT_T5_G(v1);
2009 hp_count = HP_COUNT_T5_G(v2);
2011 return lpfifo ? lp_count : hp_count;
2013 EXPORT_SYMBOL(cxgb4_dbfifo_count);
2016 * cxgb4_port_viid - get the VI id of a port
2017 * @dev: the net device for the port
2019 * Return the VI id of the given port.
2021 unsigned int cxgb4_port_viid(const struct net_device *dev)
2023 return netdev2pinfo(dev)->viid;
2025 EXPORT_SYMBOL(cxgb4_port_viid);
2028 * cxgb4_port_idx - get the index of a port
2029 * @dev: the net device for the port
2031 * Return the index of the given port.
2033 unsigned int cxgb4_port_idx(const struct net_device *dev)
2035 return netdev2pinfo(dev)->port_id;
2037 EXPORT_SYMBOL(cxgb4_port_idx);
2039 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
2040 struct tp_tcp_stats *v6)
2042 struct adapter *adap = pci_get_drvdata(pdev);
2044 spin_lock(&adap->stats_lock);
2045 t4_tp_get_tcp_stats(adap, v4, v6);
2046 spin_unlock(&adap->stats_lock);
2048 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
2050 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
2051 const unsigned int *pgsz_order)
2053 struct adapter *adap = netdev2adap(dev);
2055 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
2056 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
2057 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
2058 HPZ3_V(pgsz_order[3]));
2060 EXPORT_SYMBOL(cxgb4_iscsi_init);
2062 int cxgb4_flush_eq_cache(struct net_device *dev)
2064 struct adapter *adap = netdev2adap(dev);
2066 return t4_sge_ctxt_flush(adap, adap->mbox);
2068 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2070 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2072 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
2076 spin_lock(&adap->win0_lock);
2077 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2078 sizeof(indices), (__be32 *)&indices,
2080 spin_unlock(&adap->win0_lock);
2082 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2083 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2088 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2091 struct adapter *adap = netdev2adap(dev);
2092 u16 hw_pidx, hw_cidx;
2095 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2099 if (pidx != hw_pidx) {
2103 if (pidx >= hw_pidx)
2104 delta = pidx - hw_pidx;
2106 delta = size - hw_pidx + pidx;
2108 if (is_t4(adap->params.chip))
2109 val = PIDX_V(delta);
2111 val = PIDX_T5_V(delta);
2113 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2119 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2121 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2123 struct adapter *adap;
2124 u32 offset, memtype, memaddr;
2125 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2126 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2129 adap = netdev2adap(dev);
2131 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2133 /* Figure out where the offset lands in the Memory Type/Address scheme.
2134 * This code assumes that the memory is laid out starting at offset 0
2135 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2136 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2137 * MC0, and some have both MC0 and MC1.
2139 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2140 edc0_size = EDRAM0_SIZE_G(size) << 20;
2141 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2142 edc1_size = EDRAM1_SIZE_G(size) << 20;
2143 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2144 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2146 edc0_end = edc0_size;
2147 edc1_end = edc0_end + edc1_size;
2148 mc0_end = edc1_end + mc0_size;
2150 if (offset < edc0_end) {
2153 } else if (offset < edc1_end) {
2155 memaddr = offset - edc0_end;
2157 if (offset < mc0_end) {
2159 memaddr = offset - edc1_end;
2160 } else if (is_t5(adap->params.chip)) {
2161 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2162 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2163 mc1_end = mc0_end + mc1_size;
2164 if (offset < mc1_end) {
2166 memaddr = offset - mc0_end;
2168 /* offset beyond the end of any memory */
2172 /* T4/T6 only has a single memory channel */
2177 spin_lock(&adap->win0_lock);
2178 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2179 spin_unlock(&adap->win0_lock);
2183 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2187 EXPORT_SYMBOL(cxgb4_read_tpte);
2189 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2192 struct adapter *adap;
2194 adap = netdev2adap(dev);
2195 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2196 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2198 return ((u64)hi << 32) | (u64)lo;
2200 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2202 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2204 enum cxgb4_bar2_qtype qtype,
2207 unsigned int *pbar2_qid)
2209 return t4_bar2_sge_qregs(netdev2adap(dev),
2211 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2212 ? T4_BAR2_QTYPE_EGRESS
2213 : T4_BAR2_QTYPE_INGRESS),
2218 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2220 static struct pci_driver cxgb4_driver;
2222 static void check_neigh_update(struct neighbour *neigh)
2224 const struct device *parent;
2225 const struct net_device *netdev = neigh->dev;
2227 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2228 netdev = vlan_dev_real_dev(netdev);
2229 parent = netdev->dev.parent;
2230 if (parent && parent->driver == &cxgb4_driver.driver)
2231 t4_l2t_update(dev_get_drvdata(parent), neigh);
2234 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2238 case NETEVENT_NEIGH_UPDATE:
2239 check_neigh_update(data);
2241 case NETEVENT_REDIRECT:
2248 static bool netevent_registered;
2249 static struct notifier_block cxgb4_netevent_nb = {
2250 .notifier_call = netevent_cb
2253 static void drain_db_fifo(struct adapter *adap, int usecs)
2255 u32 v1, v2, lp_count, hp_count;
2258 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2259 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2260 if (is_t4(adap->params.chip)) {
2261 lp_count = LP_COUNT_G(v1);
2262 hp_count = HP_COUNT_G(v1);
2264 lp_count = LP_COUNT_T5_G(v1);
2265 hp_count = HP_COUNT_T5_G(v2);
2268 if (lp_count == 0 && hp_count == 0)
2270 set_current_state(TASK_UNINTERRUPTIBLE);
2271 schedule_timeout(usecs_to_jiffies(usecs));
2275 static void disable_txq_db(struct sge_txq *q)
2277 unsigned long flags;
2279 spin_lock_irqsave(&q->db_lock, flags);
2281 spin_unlock_irqrestore(&q->db_lock, flags);
2284 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2286 spin_lock_irq(&q->db_lock);
2287 if (q->db_pidx_inc) {
2288 /* Make sure that all writes to the TX descriptors
2289 * are committed before we tell HW about them.
2292 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2293 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2297 spin_unlock_irq(&q->db_lock);
2300 static void disable_dbs(struct adapter *adap)
2304 for_each_ethrxq(&adap->sge, i)
2305 disable_txq_db(&adap->sge.ethtxq[i].q);
2306 for_each_iscsirxq(&adap->sge, i)
2307 disable_txq_db(&adap->sge.ofldtxq[i].q);
2308 for_each_port(adap, i)
2309 disable_txq_db(&adap->sge.ctrlq[i].q);
2312 static void enable_dbs(struct adapter *adap)
2316 for_each_ethrxq(&adap->sge, i)
2317 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2318 for_each_iscsirxq(&adap->sge, i)
2319 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2320 for_each_port(adap, i)
2321 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2324 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2326 if (adap->uld_handle[CXGB4_ULD_RDMA])
2327 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2331 static void process_db_full(struct work_struct *work)
2333 struct adapter *adap;
2335 adap = container_of(work, struct adapter, db_full_task);
2337 drain_db_fifo(adap, dbfifo_drain_delay);
2339 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2340 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2341 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2342 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2343 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2345 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2346 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2349 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2351 u16 hw_pidx, hw_cidx;
2354 spin_lock_irq(&q->db_lock);
2355 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2358 if (q->db_pidx != hw_pidx) {
2362 if (q->db_pidx >= hw_pidx)
2363 delta = q->db_pidx - hw_pidx;
2365 delta = q->size - hw_pidx + q->db_pidx;
2367 if (is_t4(adap->params.chip))
2368 val = PIDX_V(delta);
2370 val = PIDX_T5_V(delta);
2372 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2373 QID_V(q->cntxt_id) | val);
2378 spin_unlock_irq(&q->db_lock);
2380 CH_WARN(adap, "DB drop recovery failed.\n");
2382 static void recover_all_queues(struct adapter *adap)
2386 for_each_ethrxq(&adap->sge, i)
2387 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2388 for_each_iscsirxq(&adap->sge, i)
2389 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2390 for_each_port(adap, i)
2391 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2394 static void process_db_drop(struct work_struct *work)
2396 struct adapter *adap;
2398 adap = container_of(work, struct adapter, db_drop_task);
2400 if (is_t4(adap->params.chip)) {
2401 drain_db_fifo(adap, dbfifo_drain_delay);
2402 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2403 drain_db_fifo(adap, dbfifo_drain_delay);
2404 recover_all_queues(adap);
2405 drain_db_fifo(adap, dbfifo_drain_delay);
2407 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2408 } else if (is_t5(adap->params.chip)) {
2409 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2410 u16 qid = (dropped_db >> 15) & 0x1ffff;
2411 u16 pidx_inc = dropped_db & 0x1fff;
2413 unsigned int bar2_qid;
2416 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2417 0, &bar2_qoffset, &bar2_qid);
2419 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2420 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2422 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2423 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2425 /* Re-enable BAR2 WC */
2426 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2429 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2430 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2433 void t4_db_full(struct adapter *adap)
2435 if (is_t4(adap->params.chip)) {
2437 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2438 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2439 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2440 queue_work(adap->workq, &adap->db_full_task);
2444 void t4_db_dropped(struct adapter *adap)
2446 if (is_t4(adap->params.chip)) {
2448 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2450 queue_work(adap->workq, &adap->db_drop_task);
2453 static void uld_attach(struct adapter *adap, unsigned int uld)
2456 struct cxgb4_lld_info lli;
2459 lli.pdev = adap->pdev;
2461 lli.l2t = adap->l2t;
2462 lli.tids = &adap->tids;
2463 lli.ports = adap->port;
2464 lli.vr = &adap->vres;
2465 lli.mtus = adap->params.mtus;
2466 if (uld == CXGB4_ULD_RDMA) {
2467 lli.rxq_ids = adap->sge.rdma_rxq;
2468 lli.ciq_ids = adap->sge.rdma_ciq;
2469 lli.nrxq = adap->sge.rdmaqs;
2470 lli.nciq = adap->sge.rdmaciqs;
2471 } else if (uld == CXGB4_ULD_ISCSI) {
2472 lli.rxq_ids = adap->sge.iscsi_rxq;
2473 lli.nrxq = adap->sge.iscsiqsets;
2474 } else if (uld == CXGB4_ULD_ISCSIT) {
2475 lli.rxq_ids = adap->sge.iscsit_rxq;
2476 lli.nrxq = adap->sge.niscsitq;
2478 lli.ntxq = adap->sge.iscsiqsets;
2479 lli.nchan = adap->params.nports;
2480 lli.nports = adap->params.nports;
2481 lli.wr_cred = adap->params.ofldq_wr_cred;
2482 lli.adapter_type = adap->params.chip;
2483 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2484 lli.iscsi_tagmask = t4_read_reg(adap, ULP_RX_ISCSI_TAGMASK_A);
2485 lli.iscsi_pgsz_order = t4_read_reg(adap, ULP_RX_ISCSI_PSZ_A);
2486 lli.iscsi_llimit = t4_read_reg(adap, ULP_RX_ISCSI_LLIMIT_A);
2487 lli.iscsi_ppm = &adap->iscsi_ppm;
2488 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2489 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2490 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2491 lli.filt_mode = adap->params.tp.vlan_pri_map;
2492 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2493 for (i = 0; i < NCHAN; i++)
2495 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2496 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2497 lli.fw_vers = adap->params.fw_vers;
2498 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2499 lli.sge_ingpadboundary = adap->sge.fl_align;
2500 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2501 lli.sge_pktshift = adap->sge.pktshift;
2502 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2503 lli.max_ordird_qp = adap->params.max_ordird_qp;
2504 lli.max_ird_adapter = adap->params.max_ird_adapter;
2505 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2506 lli.nodeid = dev_to_node(adap->pdev_dev);
2508 handle = ulds[uld].add(&lli);
2509 if (IS_ERR(handle)) {
2510 dev_warn(adap->pdev_dev,
2511 "could not attach to the %s driver, error %ld\n",
2512 uld_str[uld], PTR_ERR(handle));
2516 adap->uld_handle[uld] = handle;
2518 if (!netevent_registered) {
2519 register_netevent_notifier(&cxgb4_netevent_nb);
2520 netevent_registered = true;
2523 if (adap->flags & FULL_INIT_DONE)
2524 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2527 static void attach_ulds(struct adapter *adap)
2531 spin_lock(&adap_rcu_lock);
2532 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2533 spin_unlock(&adap_rcu_lock);
2535 mutex_lock(&uld_mutex);
2536 list_add_tail(&adap->list_node, &adapter_list);
2537 for (i = 0; i < CXGB4_ULD_MAX; i++)
2539 uld_attach(adap, i);
2540 mutex_unlock(&uld_mutex);
2543 static void detach_ulds(struct adapter *adap)
2547 mutex_lock(&uld_mutex);
2548 list_del(&adap->list_node);
2549 for (i = 0; i < CXGB4_ULD_MAX; i++)
2550 if (adap->uld_handle[i]) {
2551 ulds[i].state_change(adap->uld_handle[i],
2552 CXGB4_STATE_DETACH);
2553 adap->uld_handle[i] = NULL;
2555 if (netevent_registered && list_empty(&adapter_list)) {
2556 unregister_netevent_notifier(&cxgb4_netevent_nb);
2557 netevent_registered = false;
2559 mutex_unlock(&uld_mutex);
2561 spin_lock(&adap_rcu_lock);
2562 list_del_rcu(&adap->rcu_node);
2563 spin_unlock(&adap_rcu_lock);
2566 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2570 mutex_lock(&uld_mutex);
2571 for (i = 0; i < CXGB4_ULD_MAX; i++)
2572 if (adap->uld_handle[i])
2573 ulds[i].state_change(adap->uld_handle[i], new_state);
2574 mutex_unlock(&uld_mutex);
2578 * cxgb4_register_uld - register an upper-layer driver
2579 * @type: the ULD type
2580 * @p: the ULD methods
2582 * Registers an upper-layer driver with this driver and notifies the ULD
2583 * about any presently available devices that support its type. Returns
2584 * %-EBUSY if a ULD of the same type is already registered.
2586 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2589 struct adapter *adap;
2591 if (type >= CXGB4_ULD_MAX)
2593 mutex_lock(&uld_mutex);
2594 if (ulds[type].add) {
2599 list_for_each_entry(adap, &adapter_list, list_node)
2600 uld_attach(adap, type);
2601 out: mutex_unlock(&uld_mutex);
2604 EXPORT_SYMBOL(cxgb4_register_uld);
2607 * cxgb4_unregister_uld - unregister an upper-layer driver
2608 * @type: the ULD type
2610 * Unregisters an existing upper-layer driver.
2612 int cxgb4_unregister_uld(enum cxgb4_uld type)
2614 struct adapter *adap;
2616 if (type >= CXGB4_ULD_MAX)
2618 mutex_lock(&uld_mutex);
2619 list_for_each_entry(adap, &adapter_list, list_node)
2620 adap->uld_handle[type] = NULL;
2621 ulds[type].add = NULL;
2622 mutex_unlock(&uld_mutex);
2625 EXPORT_SYMBOL(cxgb4_unregister_uld);
2627 #if IS_ENABLED(CONFIG_IPV6)
2628 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2629 unsigned long event, void *data)
2631 struct inet6_ifaddr *ifa = data;
2632 struct net_device *event_dev = ifa->idev->dev;
2633 const struct device *parent = NULL;
2634 #if IS_ENABLED(CONFIG_BONDING)
2635 struct adapter *adap;
2637 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2638 event_dev = vlan_dev_real_dev(event_dev);
2639 #if IS_ENABLED(CONFIG_BONDING)
2640 if (event_dev->flags & IFF_MASTER) {
2641 list_for_each_entry(adap, &adapter_list, list_node) {
2644 cxgb4_clip_get(adap->port[0],
2645 (const u32 *)ifa, 1);
2648 cxgb4_clip_release(adap->port[0],
2649 (const u32 *)ifa, 1);
2660 parent = event_dev->dev.parent;
2662 if (parent && parent->driver == &cxgb4_driver.driver) {
2665 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2668 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2677 static bool inet6addr_registered;
2678 static struct notifier_block cxgb4_inet6addr_notifier = {
2679 .notifier_call = cxgb4_inet6addr_handler
2682 static void update_clip(const struct adapter *adap)
2685 struct net_device *dev;
2690 for (i = 0; i < MAX_NPORTS; i++) {
2691 dev = adap->port[i];
2695 ret = cxgb4_update_root_dev_clip(dev);
2702 #endif /* IS_ENABLED(CONFIG_IPV6) */
2705 * cxgb_up - enable the adapter
2706 * @adap: adapter being enabled
2708 * Called when the first port is enabled, this function performs the
2709 * actions necessary to make an adapter operational, such as completing
2710 * the initialization of HW modules, and enabling interrupts.
2712 * Must be called with the rtnl lock held.
2714 static int cxgb_up(struct adapter *adap)
2718 err = setup_sge_queues(adap);
2721 err = setup_rss(adap);
2725 if (adap->flags & USING_MSIX) {
2726 name_msix_vecs(adap);
2727 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2728 adap->msix_info[0].desc, adap);
2732 err = request_msix_queue_irqs(adap);
2734 free_irq(adap->msix_info[0].vec, adap);
2738 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2739 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2740 adap->port[0]->name, adap);
2746 t4_intr_enable(adap);
2747 adap->flags |= FULL_INIT_DONE;
2748 notify_ulds(adap, CXGB4_STATE_UP);
2749 #if IS_ENABLED(CONFIG_IPV6)
2752 /* Initialize hash mac addr list*/
2753 INIT_LIST_HEAD(&adap->mac_hlist);
2757 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2759 t4_free_sge_resources(adap);
2763 static void cxgb_down(struct adapter *adapter)
2765 cancel_work_sync(&adapter->tid_release_task);
2766 cancel_work_sync(&adapter->db_full_task);
2767 cancel_work_sync(&adapter->db_drop_task);
2768 adapter->tid_release_task_busy = false;
2769 adapter->tid_release_head = NULL;
2771 t4_sge_stop(adapter);
2772 t4_free_sge_resources(adapter);
2773 adapter->flags &= ~FULL_INIT_DONE;
2777 * net_device operations
2779 static int cxgb_open(struct net_device *dev)
2782 struct port_info *pi = netdev_priv(dev);
2783 struct adapter *adapter = pi->adapter;
2785 netif_carrier_off(dev);
2787 if (!(adapter->flags & FULL_INIT_DONE)) {
2788 err = cxgb_up(adapter);
2793 err = link_start(dev);
2795 netif_tx_start_all_queues(dev);
2799 static int cxgb_close(struct net_device *dev)
2801 struct port_info *pi = netdev_priv(dev);
2802 struct adapter *adapter = pi->adapter;
2804 netif_tx_stop_all_queues(dev);
2805 netif_carrier_off(dev);
2806 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2809 /* Return an error number if the indicated filter isn't writable ...
2811 static int writable_filter(struct filter_entry *f)
2821 /* Delete the filter at the specified index (if valid). The checks for all
2822 * the common problems with doing this like the filter being locked, currently
2823 * pending in another operation, etc.
2825 static int delete_filter(struct adapter *adapter, unsigned int fidx)
2827 struct filter_entry *f;
2830 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2833 f = &adapter->tids.ftid_tab[fidx];
2834 ret = writable_filter(f);
2838 return del_filter_wr(adapter, fidx);
2843 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2844 __be32 sip, __be16 sport, __be16 vlan,
2845 unsigned int queue, unsigned char port, unsigned char mask)
2848 struct filter_entry *f;
2849 struct adapter *adap;
2853 adap = netdev2adap(dev);
2855 /* Adjust stid to correct filter index */
2856 stid -= adap->tids.sftid_base;
2857 stid += adap->tids.nftids;
2859 /* Check to make sure the filter requested is writable ...
2861 f = &adap->tids.ftid_tab[stid];
2862 ret = writable_filter(f);
2866 /* Clear out any old resources being used by the filter before
2867 * we start constructing the new filter.
2870 clear_filter(adap, f);
2872 /* Clear out filter specifications */
2873 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2874 f->fs.val.lport = cpu_to_be16(sport);
2875 f->fs.mask.lport = ~0;
2877 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2878 for (i = 0; i < 4; i++) {
2879 f->fs.val.lip[i] = val[i];
2880 f->fs.mask.lip[i] = ~0;
2882 if (adap->params.tp.vlan_pri_map & PORT_F) {
2883 f->fs.val.iport = port;
2884 f->fs.mask.iport = mask;
2888 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2889 f->fs.val.proto = IPPROTO_TCP;
2890 f->fs.mask.proto = ~0;
2895 /* Mark filter as locked */
2899 ret = set_filter_wr(adap, stid);
2901 clear_filter(adap, f);
2907 EXPORT_SYMBOL(cxgb4_create_server_filter);
2909 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2910 unsigned int queue, bool ipv6)
2913 struct filter_entry *f;
2914 struct adapter *adap;
2916 adap = netdev2adap(dev);
2918 /* Adjust stid to correct filter index */
2919 stid -= adap->tids.sftid_base;
2920 stid += adap->tids.nftids;
2922 f = &adap->tids.ftid_tab[stid];
2923 /* Unlock the filter */
2926 ret = delete_filter(adap, stid);
2932 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2934 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2935 struct rtnl_link_stats64 *ns)
2937 struct port_stats stats;
2938 struct port_info *p = netdev_priv(dev);
2939 struct adapter *adapter = p->adapter;
2941 /* Block retrieving statistics during EEH error
2942 * recovery. Otherwise, the recovery might fail
2943 * and the PCI device will be removed permanently
2945 spin_lock(&adapter->stats_lock);
2946 if (!netif_device_present(dev)) {
2947 spin_unlock(&adapter->stats_lock);
2950 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2952 spin_unlock(&adapter->stats_lock);
2954 ns->tx_bytes = stats.tx_octets;
2955 ns->tx_packets = stats.tx_frames;
2956 ns->rx_bytes = stats.rx_octets;
2957 ns->rx_packets = stats.rx_frames;
2958 ns->multicast = stats.rx_mcast_frames;
2960 /* detailed rx_errors */
2961 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2963 ns->rx_over_errors = 0;
2964 ns->rx_crc_errors = stats.rx_fcs_err;
2965 ns->rx_frame_errors = stats.rx_symbol_err;
2966 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2967 stats.rx_ovflow2 + stats.rx_ovflow3 +
2968 stats.rx_trunc0 + stats.rx_trunc1 +
2969 stats.rx_trunc2 + stats.rx_trunc3;
2970 ns->rx_missed_errors = 0;
2972 /* detailed tx_errors */
2973 ns->tx_aborted_errors = 0;
2974 ns->tx_carrier_errors = 0;
2975 ns->tx_fifo_errors = 0;
2976 ns->tx_heartbeat_errors = 0;
2977 ns->tx_window_errors = 0;
2979 ns->tx_errors = stats.tx_error_frames;
2980 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2981 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2985 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2988 int ret = 0, prtad, devad;
2989 struct port_info *pi = netdev_priv(dev);
2990 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2994 if (pi->mdio_addr < 0)
2996 data->phy_id = pi->mdio_addr;
3000 if (mdio_phy_id_is_c45(data->phy_id)) {
3001 prtad = mdio_phy_id_prtad(data->phy_id);
3002 devad = mdio_phy_id_devad(data->phy_id);
3003 } else if (data->phy_id < 32) {
3004 prtad = data->phy_id;
3006 data->reg_num &= 0x1f;
3010 mbox = pi->adapter->pf;
3011 if (cmd == SIOCGMIIREG)
3012 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
3013 data->reg_num, &data->val_out);
3015 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
3016 data->reg_num, data->val_in);
3019 return copy_to_user(req->ifr_data, &pi->tstamp_config,
3020 sizeof(pi->tstamp_config)) ?
3023 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
3024 sizeof(pi->tstamp_config)))
3027 switch (pi->tstamp_config.rx_filter) {
3028 case HWTSTAMP_FILTER_NONE:
3029 pi->rxtstamp = false;
3031 case HWTSTAMP_FILTER_ALL:
3032 pi->rxtstamp = true;
3035 pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
3039 return copy_to_user(req->ifr_data, &pi->tstamp_config,
3040 sizeof(pi->tstamp_config)) ?
3048 static void cxgb_set_rxmode(struct net_device *dev)
3050 /* unfortunately we can't return errors to the stack */
3051 set_rxmode(dev, -1, false);
3054 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
3057 struct port_info *pi = netdev_priv(dev);
3059 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
3061 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
3068 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3071 struct sockaddr *addr = p;
3072 struct port_info *pi = netdev_priv(dev);
3074 if (!is_valid_ether_addr(addr->sa_data))
3075 return -EADDRNOTAVAIL;
3077 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
3078 pi->xact_addr_filt, addr->sa_data, true, true);
3082 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3083 pi->xact_addr_filt = ret;
3087 #ifdef CONFIG_NET_POLL_CONTROLLER
3088 static void cxgb_netpoll(struct net_device *dev)
3090 struct port_info *pi = netdev_priv(dev);
3091 struct adapter *adap = pi->adapter;
3093 if (adap->flags & USING_MSIX) {
3095 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3097 for (i = pi->nqsets; i; i--, rx++)
3098 t4_sge_intr_msix(0, &rx->rspq);
3100 t4_intr_handler(adap)(0, adap);
3104 static const struct net_device_ops cxgb4_netdev_ops = {
3105 .ndo_open = cxgb_open,
3106 .ndo_stop = cxgb_close,
3107 .ndo_start_xmit = t4_eth_xmit,
3108 .ndo_select_queue = cxgb_select_queue,
3109 .ndo_get_stats64 = cxgb_get_stats,
3110 .ndo_set_rx_mode = cxgb_set_rxmode,
3111 .ndo_set_mac_address = cxgb_set_mac_addr,
3112 .ndo_set_features = cxgb_set_features,
3113 .ndo_validate_addr = eth_validate_addr,
3114 .ndo_do_ioctl = cxgb_ioctl,
3115 .ndo_change_mtu = cxgb_change_mtu,
3116 #ifdef CONFIG_NET_POLL_CONTROLLER
3117 .ndo_poll_controller = cxgb_netpoll,
3119 #ifdef CONFIG_CHELSIO_T4_FCOE
3120 .ndo_fcoe_enable = cxgb_fcoe_enable,
3121 .ndo_fcoe_disable = cxgb_fcoe_disable,
3122 #endif /* CONFIG_CHELSIO_T4_FCOE */
3123 #ifdef CONFIG_NET_RX_BUSY_POLL
3124 .ndo_busy_poll = cxgb_busy_poll,
3129 void t4_fatal_err(struct adapter *adap)
3131 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3132 t4_intr_disable(adap);
3133 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3136 static void setup_memwin(struct adapter *adap)
3138 u32 nic_win_base = t4_get_util_window(adap);
3140 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3143 static void setup_memwin_rdma(struct adapter *adap)
3145 if (adap->vres.ocq.size) {
3149 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3150 start &= PCI_BASE_ADDRESS_MEM_MASK;
3151 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3152 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3154 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3155 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3157 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3158 adap->vres.ocq.start);
3160 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3164 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3169 /* get device capabilities */
3170 memset(c, 0, sizeof(*c));
3171 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3172 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3173 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3174 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3178 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3179 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3180 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3184 ret = t4_config_glbl_rss(adap, adap->pf,
3185 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3186 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3187 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3191 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3192 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3199 /* tweak some settings */
3200 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3201 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3202 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3203 v = t4_read_reg(adap, TP_PIO_DATA_A);
3204 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3206 /* first 4 Tx modulation queues point to consecutive Tx channels */
3207 adap->params.tp.tx_modq_map = 0xE4;
3208 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3209 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3211 /* associate each Tx modulation queue with consecutive Tx channels */
3213 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3214 &v, 1, TP_TX_SCHED_HDR_A);
3215 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3216 &v, 1, TP_TX_SCHED_FIFO_A);
3217 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3218 &v, 1, TP_TX_SCHED_PCMD_A);
3220 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3221 if (is_offload(adap)) {
3222 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3223 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3224 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3225 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3226 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3227 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3228 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3229 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3230 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3231 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3234 /* get basic stuff going */
3235 return t4_early_init(adap, adap->pf);
3239 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3241 #define MAX_ATIDS 8192U
3244 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3246 * If the firmware we're dealing with has Configuration File support, then
3247 * we use that to perform all configuration
3251 * Tweak configuration based on module parameters, etc. Most of these have
3252 * defaults assigned to them by Firmware Configuration Files (if we're using
3253 * them) but need to be explicitly set if we're using hard-coded
3254 * initialization. But even in the case of using Firmware Configuration
3255 * Files, we'd like to expose the ability to change these via module
3256 * parameters so these are essentially common tweaks/settings for
3257 * Configuration Files and hard-coded initialization ...
3259 static int adap_init0_tweaks(struct adapter *adapter)
3262 * Fix up various Host-Dependent Parameters like Page Size, Cache
3263 * Line Size, etc. The firmware default is for a 4KB Page Size and
3264 * 64B Cache Line Size ...
3266 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3269 * Process module parameters which affect early initialization.
3271 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3272 dev_err(&adapter->pdev->dev,
3273 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3277 t4_set_reg_field(adapter, SGE_CONTROL_A,
3278 PKTSHIFT_V(PKTSHIFT_M),
3279 PKTSHIFT_V(rx_dma_offset));
3282 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3283 * adds the pseudo header itself.
3285 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3286 CSUM_HAS_PSEUDO_HDR_F, 0);
3291 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3292 * unto themselves and they contain their own firmware to perform their
3295 static int phy_aq1202_version(const u8 *phy_fw_data,
3300 /* At offset 0x8 you're looking for the primary image's
3301 * starting offset which is 3 Bytes wide
3303 * At offset 0xa of the primary image, you look for the offset
3304 * of the DRAM segment which is 3 Bytes wide.
3306 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3309 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3310 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3311 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3313 offset = le24(phy_fw_data + 0x8) << 12;
3314 offset = le24(phy_fw_data + offset + 0xa);
3315 return be16(phy_fw_data + offset + 0x27e);
3322 static struct info_10gbt_phy_fw {
3323 unsigned int phy_fw_id; /* PCI Device ID */
3324 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3325 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3326 int phy_flash; /* Has FLASH for PHY Firmware */
3327 } phy_info_array[] = {
3329 PHY_AQ1202_DEVICEID,
3330 PHY_AQ1202_FIRMWARE,
3335 PHY_BCM84834_DEVICEID,
3336 PHY_BCM84834_FIRMWARE,
3343 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3347 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3348 if (phy_info_array[i].phy_fw_id == devid)
3349 return &phy_info_array[i];
3354 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3355 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3356 * we return a negative error number. If we transfer new firmware we return 1
3357 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3359 static int adap_init0_phy(struct adapter *adap)
3361 const struct firmware *phyf;
3363 struct info_10gbt_phy_fw *phy_info;
3365 /* Use the device ID to determine which PHY file to flash.
3367 phy_info = find_phy_info(adap->pdev->device);
3369 dev_warn(adap->pdev_dev,
3370 "No PHY Firmware file found for this PHY\n");
3374 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3375 * use that. The adapter firmware provides us with a memory buffer
3376 * where we can load a PHY firmware file from the host if we want to
3377 * override the PHY firmware File in flash.
3379 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3382 /* For adapters without FLASH attached to PHY for their
3383 * firmware, it's obviously a fatal error if we can't get the
3384 * firmware to the adapter. For adapters with PHY firmware
3385 * FLASH storage, it's worth a warning if we can't find the
3386 * PHY Firmware but we'll neuter the error ...
3388 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3389 "/lib/firmware/%s, error %d\n",
3390 phy_info->phy_fw_file, -ret);
3391 if (phy_info->phy_flash) {
3392 int cur_phy_fw_ver = 0;
3394 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3395 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3396 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3403 /* Load PHY Firmware onto adapter.
3405 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3406 phy_info->phy_fw_version,
3407 (u8 *)phyf->data, phyf->size);
3409 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3412 int new_phy_fw_ver = 0;
3414 if (phy_info->phy_fw_version)
3415 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3417 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3418 "Firmware /lib/firmware/%s, version %#x\n",
3419 phy_info->phy_fw_file, new_phy_fw_ver);
3422 release_firmware(phyf);
3428 * Attempt to initialize the adapter via a Firmware Configuration File.
3430 static int adap_init0_config(struct adapter *adapter, int reset)
3432 struct fw_caps_config_cmd caps_cmd;
3433 const struct firmware *cf;
3434 unsigned long mtype = 0, maddr = 0;
3435 u32 finiver, finicsum, cfcsum;
3437 int config_issued = 0;
3438 char *fw_config_file, fw_config_file_path[256];
3439 char *config_name = NULL;
3442 * Reset device if necessary.
3445 ret = t4_fw_reset(adapter, adapter->mbox,
3446 PIORSTMODE_F | PIORST_F);
3451 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3452 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3453 * to be performed after any global adapter RESET above since some
3454 * PHYs only have local RAM copies of the PHY firmware.
3456 if (is_10gbt_device(adapter->pdev->device)) {
3457 ret = adap_init0_phy(adapter);
3462 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3463 * then use that. Otherwise, use the configuration file stored
3464 * in the adapter flash ...
3466 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3468 fw_config_file = FW4_CFNAME;
3471 fw_config_file = FW5_CFNAME;
3474 fw_config_file = FW6_CFNAME;
3477 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3478 adapter->pdev->device);
3483 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3485 config_name = "On FLASH";
3486 mtype = FW_MEMTYPE_CF_FLASH;
3487 maddr = t4_flash_cfg_addr(adapter);
3489 u32 params[7], val[7];
3491 sprintf(fw_config_file_path,
3492 "/lib/firmware/%s", fw_config_file);
3493 config_name = fw_config_file_path;
3495 if (cf->size >= FLASH_CFG_MAX_SIZE)
3498 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3499 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3500 ret = t4_query_params(adapter, adapter->mbox,
3501 adapter->pf, 0, 1, params, val);
3504 * For t4_memory_rw() below addresses and
3505 * sizes have to be in terms of multiples of 4
3506 * bytes. So, if the Configuration File isn't
3507 * a multiple of 4 bytes in length we'll have
3508 * to write that out separately since we can't
3509 * guarantee that the bytes following the
3510 * residual byte in the buffer returned by
3511 * request_firmware() are zeroed out ...
3513 size_t resid = cf->size & 0x3;
3514 size_t size = cf->size & ~0x3;
3515 __be32 *data = (__be32 *)cf->data;
3517 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3518 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3520 spin_lock(&adapter->win0_lock);
3521 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3522 size, data, T4_MEMORY_WRITE);
3523 if (ret == 0 && resid != 0) {
3530 last.word = data[size >> 2];
3531 for (i = resid; i < 4; i++)
3533 ret = t4_memory_rw(adapter, 0, mtype,
3538 spin_unlock(&adapter->win0_lock);
3542 release_firmware(cf);
3548 * Issue a Capability Configuration command to the firmware to get it
3549 * to parse the Configuration File. We don't use t4_fw_config_file()
3550 * because we want the ability to modify various features after we've
3551 * processed the configuration file ...
3553 memset(&caps_cmd, 0, sizeof(caps_cmd));
3554 caps_cmd.op_to_write =
3555 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3558 caps_cmd.cfvalid_to_len16 =
3559 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3560 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3561 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3562 FW_LEN16(caps_cmd));
3563 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3566 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3567 * Configuration File in FLASH), our last gasp effort is to use the
3568 * Firmware Configuration File which is embedded in the firmware. A
3569 * very few early versions of the firmware didn't have one embedded
3570 * but we can ignore those.
3572 if (ret == -ENOENT) {
3573 memset(&caps_cmd, 0, sizeof(caps_cmd));
3574 caps_cmd.op_to_write =
3575 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3578 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3579 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3580 sizeof(caps_cmd), &caps_cmd);
3581 config_name = "Firmware Default";
3588 finiver = ntohl(caps_cmd.finiver);
3589 finicsum = ntohl(caps_cmd.finicsum);
3590 cfcsum = ntohl(caps_cmd.cfcsum);
3591 if (finicsum != cfcsum)
3592 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3593 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3597 * And now tell the firmware to use the configuration we just loaded.
3599 caps_cmd.op_to_write =
3600 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3603 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3604 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3610 * Tweak configuration based on system architecture, module
3613 ret = adap_init0_tweaks(adapter);
3618 * And finally tell the firmware to initialize itself using the
3619 * parameters from the Configuration File.
3621 ret = t4_fw_initialize(adapter, adapter->mbox);
3625 /* Emit Firmware Configuration File information and return
3628 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3629 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3630 config_name, finiver, cfcsum);
3634 * Something bad happened. Return the error ... (If the "error"
3635 * is that there's no Configuration File on the adapter we don't
3636 * want to issue a warning since this is fairly common.)
3639 if (config_issued && ret != -ENOENT)
3640 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3645 static struct fw_info fw_info_array[] = {
3648 .fs_name = FW4_CFNAME,
3649 .fw_mod_name = FW4_FNAME,
3651 .chip = FW_HDR_CHIP_T4,
3652 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3653 .intfver_nic = FW_INTFVER(T4, NIC),
3654 .intfver_vnic = FW_INTFVER(T4, VNIC),
3655 .intfver_ri = FW_INTFVER(T4, RI),
3656 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3657 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3661 .fs_name = FW5_CFNAME,
3662 .fw_mod_name = FW5_FNAME,
3664 .chip = FW_HDR_CHIP_T5,
3665 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3666 .intfver_nic = FW_INTFVER(T5, NIC),
3667 .intfver_vnic = FW_INTFVER(T5, VNIC),
3668 .intfver_ri = FW_INTFVER(T5, RI),
3669 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3670 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3674 .fs_name = FW6_CFNAME,
3675 .fw_mod_name = FW6_FNAME,
3677 .chip = FW_HDR_CHIP_T6,
3678 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3679 .intfver_nic = FW_INTFVER(T6, NIC),
3680 .intfver_vnic = FW_INTFVER(T6, VNIC),
3681 .intfver_ofld = FW_INTFVER(T6, OFLD),
3682 .intfver_ri = FW_INTFVER(T6, RI),
3683 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3684 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3685 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3686 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3692 static struct fw_info *find_fw_info(int chip)
3696 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3697 if (fw_info_array[i].chip == chip)
3698 return &fw_info_array[i];
3704 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3706 static int adap_init0(struct adapter *adap)
3710 enum dev_state state;
3711 u32 params[7], val[7];
3712 struct fw_caps_config_cmd caps_cmd;
3715 /* Grab Firmware Device Log parameters as early as possible so we have
3716 * access to it for debugging, etc.
3718 ret = t4_init_devlog_params(adap);
3722 /* Contact FW, advertising Master capability */
3723 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
3725 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3729 if (ret == adap->mbox)
3730 adap->flags |= MASTER_PF;
3733 * If we're the Master PF Driver and the device is uninitialized,
3734 * then let's consider upgrading the firmware ... (We always want
3735 * to check the firmware version number in order to A. get it for
3736 * later reporting and B. to warn if the currently loaded firmware
3737 * is excessively mismatched relative to the driver.)
3739 t4_get_fw_version(adap, &adap->params.fw_vers);
3740 t4_get_tp_version(adap, &adap->params.tp_vers);
3741 ret = t4_check_fw_version(adap);
3742 /* If firmware is too old (not supported by driver) force an update. */
3744 state = DEV_STATE_UNINIT;
3745 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3746 struct fw_info *fw_info;
3747 struct fw_hdr *card_fw;
3748 const struct firmware *fw;
3749 const u8 *fw_data = NULL;
3750 unsigned int fw_size = 0;
3752 /* This is the firmware whose headers the driver was compiled
3755 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3756 if (fw_info == NULL) {
3757 dev_err(adap->pdev_dev,
3758 "unable to get firmware info for chip %d.\n",
3759 CHELSIO_CHIP_VERSION(adap->params.chip));
3763 /* allocate memory to read the header of the firmware on the
3766 card_fw = t4_alloc_mem(sizeof(*card_fw));
3768 /* Get FW from from /lib/firmware/ */
3769 ret = request_firmware(&fw, fw_info->fw_mod_name,
3772 dev_err(adap->pdev_dev,
3773 "unable to load firmware image %s, error %d\n",
3774 fw_info->fw_mod_name, ret);
3780 /* upgrade FW logic */
3781 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3785 release_firmware(fw);
3786 t4_free_mem(card_fw);
3793 * Grab VPD parameters. This should be done after we establish a
3794 * connection to the firmware since some of the VPD parameters
3795 * (notably the Core Clock frequency) are retrieved via requests to
3796 * the firmware. On the other hand, we need these fairly early on
3797 * so we do this right after getting ahold of the firmware.
3799 ret = t4_get_vpd_params(adap, &adap->params.vpd);
3804 * Find out what ports are available to us. Note that we need to do
3805 * this before calling adap_init0_no_config() since it needs nports
3809 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3810 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3811 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3815 adap->params.nports = hweight32(port_vec);
3816 adap->params.portvec = port_vec;
3818 /* If the firmware is initialized already, emit a simply note to that
3819 * effect. Otherwise, it's time to try initializing the adapter.
3821 if (state == DEV_STATE_INIT) {
3822 dev_info(adap->pdev_dev, "Coming up as %s: "\
3823 "Adapter already initialized\n",
3824 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3826 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3827 "Initializing adapter\n");
3829 /* Find out whether we're dealing with a version of the
3830 * firmware which has configuration file support.
3832 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3833 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3834 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3837 /* If the firmware doesn't support Configuration Files,
3841 dev_err(adap->pdev_dev, "firmware doesn't support "
3842 "Firmware Configuration Files\n");
3846 /* The firmware provides us with a memory buffer where we can
3847 * load a Configuration File from the host if we want to
3848 * override the Configuration File in flash.
3850 ret = adap_init0_config(adap, reset);
3851 if (ret == -ENOENT) {
3852 dev_err(adap->pdev_dev, "no Configuration File "
3853 "present on adapter.\n");
3857 dev_err(adap->pdev_dev, "could not initialize "
3858 "adapter, error %d\n", -ret);
3863 /* Give the SGE code a chance to pull in anything that it needs ...
3864 * Note that this must be called after we retrieve our VPD parameters
3865 * in order to know how to convert core ticks to seconds, etc.
3867 ret = t4_sge_init(adap);
3871 if (is_bypass_device(adap->pdev->device))
3872 adap->params.bypass = 1;
3875 * Grab some of our basic fundamental operating parameters.
3877 #define FW_PARAM_DEV(param) \
3878 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3879 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3881 #define FW_PARAM_PFVF(param) \
3882 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3883 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3884 FW_PARAMS_PARAM_Y_V(0) | \
3885 FW_PARAMS_PARAM_Z_V(0)
3887 params[0] = FW_PARAM_PFVF(EQ_START);
3888 params[1] = FW_PARAM_PFVF(L2T_START);
3889 params[2] = FW_PARAM_PFVF(L2T_END);
3890 params[3] = FW_PARAM_PFVF(FILTER_START);
3891 params[4] = FW_PARAM_PFVF(FILTER_END);
3892 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3893 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3896 adap->sge.egr_start = val[0];
3897 adap->l2t_start = val[1];
3898 adap->l2t_end = val[2];
3899 adap->tids.ftid_base = val[3];
3900 adap->tids.nftids = val[4] - val[3] + 1;
3901 adap->sge.ingr_start = val[5];
3903 /* qids (ingress/egress) returned from firmware can be anywhere
3904 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3905 * Hence driver needs to allocate memory for this range to
3906 * store the queue info. Get the highest IQFLINT/EQ index returned
3907 * in FW_EQ_*_CMD.alloc command.
3909 params[0] = FW_PARAM_PFVF(EQ_END);
3910 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3911 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3914 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3915 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3917 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3918 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3919 if (!adap->sge.egr_map) {
3924 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3925 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3926 if (!adap->sge.ingr_map) {
3931 /* Allocate the memory for the vaious egress queue bitmaps
3932 * ie starving_fl, txq_maperr and blocked_fl.
3934 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3935 sizeof(long), GFP_KERNEL);
3936 if (!adap->sge.starving_fl) {
3941 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3942 sizeof(long), GFP_KERNEL);
3943 if (!adap->sge.txq_maperr) {
3948 #ifdef CONFIG_DEBUG_FS
3949 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3950 sizeof(long), GFP_KERNEL);
3951 if (!adap->sge.blocked_fl) {
3957 params[0] = FW_PARAM_PFVF(CLIP_START);
3958 params[1] = FW_PARAM_PFVF(CLIP_END);
3959 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3962 adap->clipt_start = val[0];
3963 adap->clipt_end = val[1];
3965 /* query params related to active filter region */
3966 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3967 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3968 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3969 /* If Active filter size is set we enable establishing
3970 * offload connection through firmware work request
3972 if ((val[0] != val[1]) && (ret >= 0)) {
3973 adap->flags |= FW_OFLD_CONN;
3974 adap->tids.aftid_base = val[0];
3975 adap->tids.aftid_end = val[1];
3978 /* If we're running on newer firmware, let it know that we're
3979 * prepared to deal with encapsulated CPL messages. Older
3980 * firmware won't understand this and we'll just get
3981 * unencapsulated messages ...
3983 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3985 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
3988 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3989 * capability. Earlier versions of the firmware didn't have the
3990 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3991 * permission to use ULPTX MEMWRITE DSGL.
3993 if (is_t4(adap->params.chip)) {
3994 adap->params.ulptx_memwrite_dsgl = false;
3996 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3997 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3999 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4003 * Get device capabilities so we can determine what resources we need
4006 memset(&caps_cmd, 0, sizeof(caps_cmd));
4007 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4008 FW_CMD_REQUEST_F | FW_CMD_READ_F);
4009 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4010 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4015 if (caps_cmd.ofldcaps) {
4016 /* query offload-related parameters */
4017 params[0] = FW_PARAM_DEV(NTID);
4018 params[1] = FW_PARAM_PFVF(SERVER_START);
4019 params[2] = FW_PARAM_PFVF(SERVER_END);
4020 params[3] = FW_PARAM_PFVF(TDDP_START);
4021 params[4] = FW_PARAM_PFVF(TDDP_END);
4022 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4023 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4027 adap->tids.ntids = val[0];
4028 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4029 adap->tids.stid_base = val[1];
4030 adap->tids.nstids = val[2] - val[1] + 1;
4032 * Setup server filter region. Divide the available filter
4033 * region into two parts. Regular filters get 1/3rd and server
4034 * filters get 2/3rd part. This is only enabled if workarond
4036 * 1. For regular filters.
4037 * 2. Server filter: This are special filters which are used
4038 * to redirect SYN packets to offload queue.
4040 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
4041 adap->tids.sftid_base = adap->tids.ftid_base +
4042 DIV_ROUND_UP(adap->tids.nftids, 3);
4043 adap->tids.nsftids = adap->tids.nftids -
4044 DIV_ROUND_UP(adap->tids.nftids, 3);
4045 adap->tids.nftids = adap->tids.sftid_base -
4046 adap->tids.ftid_base;
4048 adap->vres.ddp.start = val[3];
4049 adap->vres.ddp.size = val[4] - val[3] + 1;
4050 adap->params.ofldq_wr_cred = val[5];
4052 adap->params.offload = 1;
4054 if (caps_cmd.rdmacaps) {
4055 params[0] = FW_PARAM_PFVF(STAG_START);
4056 params[1] = FW_PARAM_PFVF(STAG_END);
4057 params[2] = FW_PARAM_PFVF(RQ_START);
4058 params[3] = FW_PARAM_PFVF(RQ_END);
4059 params[4] = FW_PARAM_PFVF(PBL_START);
4060 params[5] = FW_PARAM_PFVF(PBL_END);
4061 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4065 adap->vres.stag.start = val[0];
4066 adap->vres.stag.size = val[1] - val[0] + 1;
4067 adap->vres.rq.start = val[2];
4068 adap->vres.rq.size = val[3] - val[2] + 1;
4069 adap->vres.pbl.start = val[4];
4070 adap->vres.pbl.size = val[5] - val[4] + 1;
4072 params[0] = FW_PARAM_PFVF(SQRQ_START);
4073 params[1] = FW_PARAM_PFVF(SQRQ_END);
4074 params[2] = FW_PARAM_PFVF(CQ_START);
4075 params[3] = FW_PARAM_PFVF(CQ_END);
4076 params[4] = FW_PARAM_PFVF(OCQ_START);
4077 params[5] = FW_PARAM_PFVF(OCQ_END);
4078 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4082 adap->vres.qp.start = val[0];
4083 adap->vres.qp.size = val[1] - val[0] + 1;
4084 adap->vres.cq.start = val[2];
4085 adap->vres.cq.size = val[3] - val[2] + 1;
4086 adap->vres.ocq.start = val[4];
4087 adap->vres.ocq.size = val[5] - val[4] + 1;
4089 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4090 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4091 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4094 adap->params.max_ordird_qp = 8;
4095 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4098 adap->params.max_ordird_qp = val[0];
4099 adap->params.max_ird_adapter = val[1];
4101 dev_info(adap->pdev_dev,
4102 "max_ordird_qp %d max_ird_adapter %d\n",
4103 adap->params.max_ordird_qp,
4104 adap->params.max_ird_adapter);
4106 if (caps_cmd.iscsicaps) {
4107 params[0] = FW_PARAM_PFVF(ISCSI_START);
4108 params[1] = FW_PARAM_PFVF(ISCSI_END);
4109 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4113 adap->vres.iscsi.start = val[0];
4114 adap->vres.iscsi.size = val[1] - val[0] + 1;
4116 #undef FW_PARAM_PFVF
4119 /* The MTU/MSS Table is initialized by now, so load their values. If
4120 * we're initializing the adapter, then we'll make any modifications
4121 * we want to the MTU/MSS Table and also initialize the congestion
4124 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4125 if (state != DEV_STATE_INIT) {
4128 /* The default MTU Table contains values 1492 and 1500.
4129 * However, for TCP, it's better to have two values which are
4130 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4131 * This allows us to have a TCP Data Payload which is a
4132 * multiple of 8 regardless of what combination of TCP Options
4133 * are in use (always a multiple of 4 bytes) which is
4134 * important for performance reasons. For instance, if no
4135 * options are in use, then we have a 20-byte IP header and a
4136 * 20-byte TCP header. In this case, a 1500-byte MSS would
4137 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4138 * which is not a multiple of 8. So using an MSS of 1488 in
4139 * this case results in a TCP Data Payload of 1448 bytes which
4140 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4141 * Stamps have been negotiated, then an MTU of 1500 bytes
4142 * results in a TCP Data Payload of 1448 bytes which, as
4143 * above, is a multiple of 8 bytes ...
4145 for (i = 0; i < NMTUS; i++)
4146 if (adap->params.mtus[i] == 1492) {
4147 adap->params.mtus[i] = 1488;
4151 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4152 adap->params.b_wnd);
4154 t4_init_sge_params(adap);
4155 adap->flags |= FW_OK;
4156 t4_init_tp_params(adap);
4160 * Something bad happened. If a command timed out or failed with EIO
4161 * FW does not operate within its spec or something catastrophic
4162 * happened to HW/FW, stop issuing commands.
4165 kfree(adap->sge.egr_map);
4166 kfree(adap->sge.ingr_map);
4167 kfree(adap->sge.starving_fl);
4168 kfree(adap->sge.txq_maperr);
4169 #ifdef CONFIG_DEBUG_FS
4170 kfree(adap->sge.blocked_fl);
4172 if (ret != -ETIMEDOUT && ret != -EIO)
4173 t4_fw_bye(adap, adap->mbox);
4179 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4180 pci_channel_state_t state)
4183 struct adapter *adap = pci_get_drvdata(pdev);
4189 adap->flags &= ~FW_OK;
4190 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4191 spin_lock(&adap->stats_lock);
4192 for_each_port(adap, i) {
4193 struct net_device *dev = adap->port[i];
4195 netif_device_detach(dev);
4196 netif_carrier_off(dev);
4198 spin_unlock(&adap->stats_lock);
4199 disable_interrupts(adap);
4200 if (adap->flags & FULL_INIT_DONE)
4203 if ((adap->flags & DEV_ENABLED)) {
4204 pci_disable_device(pdev);
4205 adap->flags &= ~DEV_ENABLED;
4207 out: return state == pci_channel_io_perm_failure ?
4208 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4211 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4214 struct fw_caps_config_cmd c;
4215 struct adapter *adap = pci_get_drvdata(pdev);
4218 pci_restore_state(pdev);
4219 pci_save_state(pdev);
4220 return PCI_ERS_RESULT_RECOVERED;
4223 if (!(adap->flags & DEV_ENABLED)) {
4224 if (pci_enable_device(pdev)) {
4225 dev_err(&pdev->dev, "Cannot reenable PCI "
4226 "device after reset\n");
4227 return PCI_ERS_RESULT_DISCONNECT;
4229 adap->flags |= DEV_ENABLED;
4232 pci_set_master(pdev);
4233 pci_restore_state(pdev);
4234 pci_save_state(pdev);
4235 pci_cleanup_aer_uncorrect_error_status(pdev);
4237 if (t4_wait_dev_ready(adap->regs) < 0)
4238 return PCI_ERS_RESULT_DISCONNECT;
4239 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4240 return PCI_ERS_RESULT_DISCONNECT;
4241 adap->flags |= FW_OK;
4242 if (adap_init1(adap, &c))
4243 return PCI_ERS_RESULT_DISCONNECT;
4245 for_each_port(adap, i) {
4246 struct port_info *p = adap2pinfo(adap, i);
4248 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
4251 return PCI_ERS_RESULT_DISCONNECT;
4253 p->xact_addr_filt = -1;
4256 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4257 adap->params.b_wnd);
4260 return PCI_ERS_RESULT_DISCONNECT;
4261 return PCI_ERS_RESULT_RECOVERED;
4264 static void eeh_resume(struct pci_dev *pdev)
4267 struct adapter *adap = pci_get_drvdata(pdev);
4273 for_each_port(adap, i) {
4274 struct net_device *dev = adap->port[i];
4276 if (netif_running(dev)) {
4278 cxgb_set_rxmode(dev);
4280 netif_device_attach(dev);
4285 static const struct pci_error_handlers cxgb4_eeh = {
4286 .error_detected = eeh_err_detected,
4287 .slot_reset = eeh_slot_reset,
4288 .resume = eeh_resume,
4291 static inline bool is_x_10g_port(const struct link_config *lc)
4293 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4294 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
4297 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4298 unsigned int us, unsigned int cnt,
4299 unsigned int size, unsigned int iqe_size)
4302 cxgb4_set_rspq_intr_params(q, us, cnt);
4303 q->iqe_len = iqe_size;
4308 * Perform default configuration of DMA queues depending on the number and type
4309 * of ports we found and the number of available CPUs. Most settings can be
4310 * modified by the admin prior to actual use.
4312 static void cfg_queues(struct adapter *adap)
4314 struct sge *s = &adap->sge;
4315 int i, n10g = 0, qidx = 0;
4316 #ifndef CONFIG_CHELSIO_T4_DCB
4321 for_each_port(adap, i)
4322 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4323 #ifdef CONFIG_CHELSIO_T4_DCB
4324 /* For Data Center Bridging support we need to be able to support up
4325 * to 8 Traffic Priorities; each of which will be assigned to its
4326 * own TX Queue in order to prevent Head-Of-Line Blocking.
4328 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4329 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4330 MAX_ETH_QSETS, adap->params.nports * 8);
4334 for_each_port(adap, i) {
4335 struct port_info *pi = adap2pinfo(adap, i);
4337 pi->first_qset = qidx;
4341 #else /* !CONFIG_CHELSIO_T4_DCB */
4343 * We default to 1 queue per non-10G port and up to # of cores queues
4347 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4348 if (q10g > netif_get_num_default_rss_queues())
4349 q10g = netif_get_num_default_rss_queues();
4351 for_each_port(adap, i) {
4352 struct port_info *pi = adap2pinfo(adap, i);
4354 pi->first_qset = qidx;
4355 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4358 #endif /* !CONFIG_CHELSIO_T4_DCB */
4361 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4363 if (is_offload(adap)) {
4365 * For offload we use 1 queue/channel if all ports are up to 1G,
4366 * otherwise we divide all available queues amongst the channels
4367 * capped by the number of available cores.
4370 i = min_t(int, ARRAY_SIZE(s->iscsirxq),
4372 s->iscsiqsets = roundup(i, adap->params.nports);
4374 s->iscsiqsets = adap->params.nports;
4375 /* For RDMA one Rx queue per channel suffices */
4376 s->rdmaqs = adap->params.nports;
4377 /* Try and allow at least 1 CIQ per cpu rounding down
4378 * to the number of ports, with a minimum of 1 per port.
4379 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4380 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4381 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4383 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4384 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4385 adap->params.nports;
4386 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4388 if (!is_t4(adap->params.chip))
4389 s->niscsitq = s->iscsiqsets;
4392 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4393 struct sge_eth_rxq *r = &s->ethrxq[i];
4395 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4399 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4400 s->ethtxq[i].q.size = 1024;
4402 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4403 s->ctrlq[i].q.size = 512;
4405 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4406 s->ofldtxq[i].q.size = 1024;
4408 for (i = 0; i < ARRAY_SIZE(s->iscsirxq); i++) {
4409 struct sge_ofld_rxq *r = &s->iscsirxq[i];
4411 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4412 r->rspq.uld = CXGB4_ULD_ISCSI;
4416 if (!is_t4(adap->params.chip)) {
4417 for (i = 0; i < ARRAY_SIZE(s->iscsitrxq); i++) {
4418 struct sge_ofld_rxq *r = &s->iscsitrxq[i];
4420 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4421 r->rspq.uld = CXGB4_ULD_ISCSIT;
4426 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4427 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4429 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4430 r->rspq.uld = CXGB4_ULD_RDMA;
4434 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4435 if (ciq_size > SGE_MAX_IQ_SIZE) {
4436 CH_WARN(adap, "CIQ size too small for available IQs\n");
4437 ciq_size = SGE_MAX_IQ_SIZE;
4440 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4441 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4443 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4444 r->rspq.uld = CXGB4_ULD_RDMA;
4447 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4448 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4452 * Reduce the number of Ethernet queues across all ports to at most n.
4453 * n provides at least one queue per port.
4455 static void reduce_ethqs(struct adapter *adap, int n)
4458 struct port_info *pi;
4460 while (n < adap->sge.ethqsets)
4461 for_each_port(adap, i) {
4462 pi = adap2pinfo(adap, i);
4463 if (pi->nqsets > 1) {
4465 adap->sge.ethqsets--;
4466 if (adap->sge.ethqsets <= n)
4472 for_each_port(adap, i) {
4473 pi = adap2pinfo(adap, i);
4479 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4480 #define EXTRA_VECS 2
4482 static int enable_msix(struct adapter *adap)
4485 int i, want, need, allocated;
4486 struct sge *s = &adap->sge;
4487 unsigned int nchan = adap->params.nports;
4488 struct msix_entry *entries;
4490 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4495 for (i = 0; i < MAX_INGQ + 1; ++i)
4496 entries[i].entry = i;
4498 want = s->max_ethqsets + EXTRA_VECS;
4499 if (is_offload(adap)) {
4500 want += s->rdmaqs + s->rdmaciqs + s->iscsiqsets +
4502 /* need nchan for each possible ULD */
4503 if (is_t4(adap->params.chip))
4504 ofld_need = 3 * nchan;
4506 ofld_need = 4 * nchan;
4508 #ifdef CONFIG_CHELSIO_T4_DCB
4509 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4512 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4514 need = adap->params.nports + EXTRA_VECS + ofld_need;
4516 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4517 if (allocated < 0) {
4518 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4519 " not using MSI-X\n");
4524 /* Distribute available vectors to the various queue groups.
4525 * Every group gets its minimum requirement and NIC gets top
4526 * priority for leftovers.
4528 i = allocated - EXTRA_VECS - ofld_need;
4529 if (i < s->max_ethqsets) {
4530 s->max_ethqsets = i;
4531 if (i < s->ethqsets)
4532 reduce_ethqs(adap, i);
4534 if (is_offload(adap)) {
4535 if (allocated < want) {
4537 s->rdmaciqs = nchan;
4539 if (!is_t4(adap->params.chip))
4540 s->niscsitq = nchan;
4543 /* leftovers go to OFLD */
4544 i = allocated - EXTRA_VECS - s->max_ethqsets -
4545 s->rdmaqs - s->rdmaciqs - s->niscsitq;
4546 s->iscsiqsets = (i / nchan) * nchan; /* round down */
4549 for (i = 0; i < allocated; ++i)
4550 adap->msix_info[i].vec = entries[i].vector;
4551 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4552 "nic %d iscsi %d rdma cpl %d rdma ciq %d\n",
4553 allocated, s->max_ethqsets, s->iscsiqsets, s->rdmaqs,
4562 static int init_rss(struct adapter *adap)
4567 err = t4_init_rss_mode(adap, adap->mbox);
4571 for_each_port(adap, i) {
4572 struct port_info *pi = adap2pinfo(adap, i);
4574 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4581 static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
4582 enum pci_bus_speed *speed,
4583 enum pcie_link_width *width)
4585 u32 lnkcap1, lnkcap2;
4588 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
4590 *speed = PCI_SPEED_UNKNOWN;
4591 *width = PCIE_LNK_WIDTH_UNKNOWN;
4593 err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
4595 err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
4597 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
4598 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
4599 *speed = PCIE_SPEED_8_0GT;
4600 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
4601 *speed = PCIE_SPEED_5_0GT;
4602 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
4603 *speed = PCIE_SPEED_2_5GT;
4606 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
4607 if (!lnkcap2) { /* pre-r3.0 */
4608 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
4609 *speed = PCIE_SPEED_5_0GT;
4610 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
4611 *speed = PCIE_SPEED_2_5GT;
4615 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
4616 return err1 ? err1 : err2 ? err2 : -EINVAL;
4620 static void cxgb4_check_pcie_caps(struct adapter *adap)
4622 enum pcie_link_width width, width_cap;
4623 enum pci_bus_speed speed, speed_cap;
4625 #define PCIE_SPEED_STR(speed) \
4626 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
4627 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
4628 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
4631 if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
4632 dev_warn(adap->pdev_dev,
4633 "Unable to determine PCIe device BW capabilities\n");
4637 if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
4638 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
4639 dev_warn(adap->pdev_dev,
4640 "Unable to determine PCI Express bandwidth.\n");
4644 dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
4645 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
4646 dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
4648 if (speed < speed_cap || width < width_cap)
4649 dev_info(adap->pdev_dev,
4650 "A slot with more lanes and/or higher speed is "
4651 "suggested for optimal performance.\n");
4654 static void print_port_info(const struct net_device *dev)
4658 const char *spd = "";
4659 const struct port_info *pi = netdev_priv(dev);
4660 const struct adapter *adap = pi->adapter;
4662 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4664 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4666 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4669 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4670 bufp += sprintf(bufp, "100/");
4671 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4672 bufp += sprintf(bufp, "1000/");
4673 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4674 bufp += sprintf(bufp, "10G/");
4675 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4676 bufp += sprintf(bufp, "40G/");
4679 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4681 netdev_info(dev, "Chelsio %s rev %d %s %sNIC %s\n",
4682 adap->params.vpd.id,
4683 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
4684 is_offload(adap) ? "R" : "",
4685 (adap->flags & USING_MSIX) ? " MSI-X" :
4686 (adap->flags & USING_MSI) ? " MSI" : "");
4687 netdev_info(dev, "S/N: %s, P/N: %s\n",
4688 adap->params.vpd.sn, adap->params.vpd.pn);
4691 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4693 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4697 * Free the following resources:
4698 * - memory used for tables
4701 * - resources FW is holding for us
4703 static void free_some_resources(struct adapter *adapter)
4707 t4_free_mem(adapter->l2t);
4708 t4_free_mem(adapter->tids.tid_tab);
4709 kfree(adapter->sge.egr_map);
4710 kfree(adapter->sge.ingr_map);
4711 kfree(adapter->sge.starving_fl);
4712 kfree(adapter->sge.txq_maperr);
4713 #ifdef CONFIG_DEBUG_FS
4714 kfree(adapter->sge.blocked_fl);
4716 disable_msi(adapter);
4718 for_each_port(adapter, i)
4719 if (adapter->port[i]) {
4720 struct port_info *pi = adap2pinfo(adapter, i);
4723 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4725 kfree(adap2pinfo(adapter, i)->rss);
4726 free_netdev(adapter->port[i]);
4728 if (adapter->flags & FW_OK)
4729 t4_fw_bye(adapter, adapter->pf);
4732 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4733 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4734 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4735 #define SEGMENT_SIZE 128
4737 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4741 /* Retrieve adapter's device ID */
4742 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4744 switch (device_id >> 12) {
4746 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4748 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4750 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4752 dev_err(&pdev->dev, "Device %d is not supported\n",
4758 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4760 int func, i, err, s_qpp, qpp, num_seg;
4761 struct port_info *pi;
4762 bool highdma = false;
4763 struct adapter *adapter = NULL;
4766 enum chip_type chip;
4768 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4770 err = pci_request_regions(pdev, KBUILD_MODNAME);
4772 /* Just info, some other driver may have claimed the device. */
4773 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4777 err = pci_enable_device(pdev);
4779 dev_err(&pdev->dev, "cannot enable PCI device\n");
4780 goto out_release_regions;
4783 regs = pci_ioremap_bar(pdev, 0);
4785 dev_err(&pdev->dev, "cannot map device registers\n");
4787 goto out_disable_device;
4790 err = t4_wait_dev_ready(regs);
4792 goto out_unmap_bar0;
4794 /* We control everything through one PF */
4795 whoami = readl(regs + PL_WHOAMI_A);
4796 pl_rev = REV_G(readl(regs + PL_REV_A));
4797 chip = get_chip_type(pdev, pl_rev);
4798 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4799 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4800 if (func != ent->driver_data) {
4802 pci_disable_device(pdev);
4803 pci_save_state(pdev); /* to restore SR-IOV later */
4807 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4809 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4811 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4812 "coherent allocations\n");
4813 goto out_unmap_bar0;
4816 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4818 dev_err(&pdev->dev, "no usable DMA configuration\n");
4819 goto out_unmap_bar0;
4823 pci_enable_pcie_error_reporting(pdev);
4824 enable_pcie_relaxed_ordering(pdev);
4825 pci_set_master(pdev);
4826 pci_save_state(pdev);
4828 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4831 goto out_unmap_bar0;
4834 adapter->workq = create_singlethread_workqueue("cxgb4");
4835 if (!adapter->workq) {
4837 goto out_free_adapter;
4840 /* PCI device has been enabled */
4841 adapter->flags |= DEV_ENABLED;
4843 adapter->regs = regs;
4844 adapter->pdev = pdev;
4845 adapter->pdev_dev = &pdev->dev;
4846 adapter->mbox = func;
4848 adapter->msg_enable = dflt_msg_enable;
4849 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4851 spin_lock_init(&adapter->stats_lock);
4852 spin_lock_init(&adapter->tid_release_lock);
4853 spin_lock_init(&adapter->win0_lock);
4855 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4856 INIT_WORK(&adapter->db_full_task, process_db_full);
4857 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4859 err = t4_prep_adapter(adapter);
4861 goto out_free_adapter;
4864 if (!is_t4(adapter->params.chip)) {
4865 s_qpp = (QUEUESPERPAGEPF0_S +
4866 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4868 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4869 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4870 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4872 /* Each segment size is 128B. Write coalescing is enabled only
4873 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4874 * queue is less no of segments that can be accommodated in
4877 if (qpp > num_seg) {
4879 "Incorrect number of egress queues per page\n");
4881 goto out_free_adapter;
4883 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4884 pci_resource_len(pdev, 2));
4885 if (!adapter->bar2) {
4886 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4888 goto out_free_adapter;
4892 setup_memwin(adapter);
4893 err = adap_init0(adapter);
4894 #ifdef CONFIG_DEBUG_FS
4895 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4897 setup_memwin_rdma(adapter);
4901 /* configure SGE_STAT_CFG_A to read WC stats */
4902 if (!is_t4(adapter->params.chip))
4903 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
4904 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
4907 for_each_port(adapter, i) {
4908 struct net_device *netdev;
4910 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4917 SET_NETDEV_DEV(netdev, &pdev->dev);
4919 adapter->port[i] = netdev;
4920 pi = netdev_priv(netdev);
4921 pi->adapter = adapter;
4922 pi->xact_addr_filt = -1;
4924 netdev->irq = pdev->irq;
4926 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4927 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4928 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4929 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
4931 netdev->hw_features |= NETIF_F_HIGHDMA;
4932 netdev->features |= netdev->hw_features;
4933 netdev->vlan_features = netdev->features & VLAN_FEAT;
4935 netdev->priv_flags |= IFF_UNICAST_FLT;
4937 netdev->netdev_ops = &cxgb4_netdev_ops;
4938 #ifdef CONFIG_CHELSIO_T4_DCB
4939 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4940 cxgb4_dcb_state_init(netdev);
4942 cxgb4_set_ethtool_ops(netdev);
4945 pci_set_drvdata(pdev, adapter);
4947 if (adapter->flags & FW_OK) {
4948 err = t4_port_init(adapter, func, func, 0);
4951 } else if (adapter->params.nports == 1) {
4952 /* If we don't have a connection to the firmware -- possibly
4953 * because of an error -- grab the raw VPD parameters so we
4954 * can set the proper MAC Address on the debug network
4955 * interface that we've created.
4957 u8 hw_addr[ETH_ALEN];
4958 u8 *na = adapter->params.vpd.na;
4960 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
4962 for (i = 0; i < ETH_ALEN; i++)
4963 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
4964 hex2val(na[2 * i + 1]));
4965 t4_set_hw_addr(adapter, 0, hw_addr);
4969 /* Configure queues and allocate tables now, they can be needed as
4970 * soon as the first register_netdev completes.
4972 cfg_queues(adapter);
4974 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
4975 if (!adapter->l2t) {
4976 /* We tolerate a lack of L2T, giving up some functionality */
4977 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4978 adapter->params.offload = 0;
4981 #if IS_ENABLED(CONFIG_IPV6)
4982 if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
4983 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
4984 /* CLIP functionality is not present in hardware,
4985 * hence disable all offload features
4987 dev_warn(&pdev->dev,
4988 "CLIP not enabled in hardware, continuing\n");
4989 adapter->params.offload = 0;
4991 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4992 adapter->clipt_end);
4993 if (!adapter->clipt) {
4994 /* We tolerate a lack of clip_table, giving up
4995 * some functionality
4997 dev_warn(&pdev->dev,
4998 "could not allocate Clip table, continuing\n");
4999 adapter->params.offload = 0;
5003 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
5004 dev_warn(&pdev->dev, "could not allocate TID table, "
5006 adapter->params.offload = 0;
5009 if (is_offload(adapter)) {
5010 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5011 u32 hash_base, hash_reg;
5013 if (chip <= CHELSIO_T5) {
5014 hash_reg = LE_DB_TID_HASHBASE_A;
5015 hash_base = t4_read_reg(adapter, hash_reg);
5016 adapter->tids.hash_base = hash_base / 4;
5018 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5019 hash_base = t4_read_reg(adapter, hash_reg);
5020 adapter->tids.hash_base = hash_base;
5025 /* See what interrupts we'll be using */
5026 if (msi > 1 && enable_msix(adapter) == 0)
5027 adapter->flags |= USING_MSIX;
5028 else if (msi > 0 && pci_enable_msi(pdev) == 0)
5029 adapter->flags |= USING_MSI;
5031 /* check for PCI Express bandwidth capabiltites */
5032 cxgb4_check_pcie_caps(adapter);
5034 err = init_rss(adapter);
5039 * The card is now ready to go. If any errors occur during device
5040 * registration we do not fail the whole card but rather proceed only
5041 * with the ports we manage to register successfully. However we must
5042 * register at least one net device.
5044 for_each_port(adapter, i) {
5045 pi = adap2pinfo(adapter, i);
5046 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5047 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5049 err = register_netdev(adapter->port[i]);
5052 adapter->chan_map[pi->tx_chan] = i;
5053 print_port_info(adapter->port[i]);
5056 dev_err(&pdev->dev, "could not register any net devices\n");
5060 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5064 if (cxgb4_debugfs_root) {
5065 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5066 cxgb4_debugfs_root);
5067 setup_debugfs(adapter);
5070 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5071 pdev->needs_freset = 1;
5073 if (is_offload(adapter))
5074 attach_ulds(adapter);
5077 #ifdef CONFIG_PCI_IOV
5078 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
5079 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
5080 dev_info(&pdev->dev,
5081 "instantiated %u virtual functions\n",
5087 free_some_resources(adapter);
5089 if (!is_t4(adapter->params.chip))
5090 iounmap(adapter->bar2);
5093 destroy_workqueue(adapter->workq);
5099 pci_disable_pcie_error_reporting(pdev);
5100 pci_disable_device(pdev);
5101 out_release_regions:
5102 pci_release_regions(pdev);
5106 static void remove_one(struct pci_dev *pdev)
5108 struct adapter *adapter = pci_get_drvdata(pdev);
5110 #ifdef CONFIG_PCI_IOV
5111 pci_disable_sriov(pdev);
5118 /* Tear down per-adapter Work Queue first since it can contain
5119 * references to our adapter data structure.
5121 destroy_workqueue(adapter->workq);
5123 if (is_offload(adapter))
5124 detach_ulds(adapter);
5126 disable_interrupts(adapter);
5128 for_each_port(adapter, i)
5129 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5130 unregister_netdev(adapter->port[i]);
5132 debugfs_remove_recursive(adapter->debugfs_root);
5134 /* If we allocated filters, free up state associated with any
5137 if (adapter->tids.ftid_tab) {
5138 struct filter_entry *f = &adapter->tids.ftid_tab[0];
5139 for (i = 0; i < (adapter->tids.nftids +
5140 adapter->tids.nsftids); i++, f++)
5142 clear_filter(adapter, f);
5145 if (adapter->flags & FULL_INIT_DONE)
5148 free_some_resources(adapter);
5149 #if IS_ENABLED(CONFIG_IPV6)
5150 t4_cleanup_clip_tbl(adapter);
5152 iounmap(adapter->regs);
5153 if (!is_t4(adapter->params.chip))
5154 iounmap(adapter->bar2);
5155 pci_disable_pcie_error_reporting(pdev);
5156 if ((adapter->flags & DEV_ENABLED)) {
5157 pci_disable_device(pdev);
5158 adapter->flags &= ~DEV_ENABLED;
5160 pci_release_regions(pdev);
5164 pci_release_regions(pdev);
5167 static struct pci_driver cxgb4_driver = {
5168 .name = KBUILD_MODNAME,
5169 .id_table = cxgb4_pci_tbl,
5171 .remove = remove_one,
5172 .shutdown = remove_one,
5173 .err_handler = &cxgb4_eeh,
5176 static int __init cxgb4_init_module(void)
5180 /* Debugfs support is optional, just warn if this fails */
5181 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5182 if (!cxgb4_debugfs_root)
5183 pr_warn("could not create debugfs entry, continuing\n");
5185 ret = pci_register_driver(&cxgb4_driver);
5187 debugfs_remove(cxgb4_debugfs_root);
5189 #if IS_ENABLED(CONFIG_IPV6)
5190 if (!inet6addr_registered) {
5191 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5192 inet6addr_registered = true;
5199 static void __exit cxgb4_cleanup_module(void)
5201 #if IS_ENABLED(CONFIG_IPV6)
5202 if (inet6addr_registered) {
5203 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5204 inet6addr_registered = false;
5207 pci_unregister_driver(&cxgb4_driver);
5208 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5211 module_init(cxgb4_init_module);
5212 module_exit(cxgb4_cleanup_module);