drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <linux/uaccess.h>
  66 #include <linux/crash_dump.h>
  67 #include <net/udp_tunnel.h>
  68 #include <net/xfrm.h>
  69
  70 #include "cxgb4.h"
  71 #include "cxgb4_filter.h"
  72 #include "t4_regs.h"
  73 #include "t4_values.h"
  74 #include "t4_msg.h"
  75 #include "t4fw_api.h"
  76 #include "t4fw_version.h"
  77 #include "cxgb4_dcb.h"
  78 #include "srq.h"
  79 #include "cxgb4_debugfs.h"
  80 #include "clip_tbl.h"
  81 #include "l2t.h"
  82 #include "smt.h"
  83 #include "sched.h"
  84 #include "cxgb4_tc_u32.h"
  85 #include "cxgb4_tc_flower.h"
  86 #include "cxgb4_tc_mqprio.h"
  87 #include "cxgb4_tc_matchall.h"
  88 #include "cxgb4_ptp.h"
  89 #include "cxgb4_cudbg.h"
  90
  91 char cxgb4_driver_name[] = KBUILD_MODNAME;
  92
  93 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
  94
  95 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  96                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
  97                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
  98
  99 /* Macros needed to support the PCI Device ID Table ...
 100  */
 101 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
 102         static const struct pci_device_id cxgb4_pci_tbl[] = {
 103 #define CXGB4_UNIFIED_PF 0x4
 104
 105 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
 106
 107 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 108  * called for both.
 109  */
 110 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 111
 112 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 113                 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
 114
 115 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 116                 { 0, } \
 117         }
 118
 119 #include "t4_pci_id_tbl.h"
 120
 121 #define FW4_FNAME "cxgb4/t4fw.bin"
 122 #define FW5_FNAME "cxgb4/t5fw.bin"
 123 #define FW6_FNAME "cxgb4/t6fw.bin"
 124 #define FW4_CFNAME "cxgb4/t4-config.txt"
 125 #define FW5_CFNAME "cxgb4/t5-config.txt"
 126 #define FW6_CFNAME "cxgb4/t6-config.txt"
 127 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
 128 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
 129 #define PHY_AQ1202_DEVICEID 0x4409
 130 #define PHY_BCM84834_DEVICEID 0x4486
 131
 132 MODULE_DESCRIPTION(DRV_DESC);
 133 MODULE_AUTHOR("Chelsio Communications");
 134 MODULE_LICENSE("Dual BSD/GPL");
 135 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 136 MODULE_FIRMWARE(FW4_FNAME);
 137 MODULE_FIRMWARE(FW5_FNAME);
 138 MODULE_FIRMWARE(FW6_FNAME);
 139
 140 /*
 141  * The driver uses the best interrupt scheme available on a platform in the
 142  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 143  * of these schemes the driver may consider as follows:
 144  *
 145  * msi = 2: choose from among all three options
 146  * msi = 1: only consider MSI and INTx interrupts
 147  * msi = 0: force INTx interrupts
 148  */
 149 static int msi = 2;
 150
 151 module_param(msi, int, 0644);
 152 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 153
 154 /*
 155  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 156  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 157  * boundaries.  This is a requirement for many architectures which will throw
 158  * a machine check fault if an attempt is made to access one of the 4-byte IP
 159  * header fields on a non-4-byte boundary.  And it's a major performance issue
 160  * even on some architectures which allow it like some implementations of the
 161  * x86 ISA.  However, some architectures don't mind this and for some very
 162  * edge-case performance sensitive applications (like forwarding large volumes
 163  * of small packets), setting this DMA offset to 0 will decrease the number of
 164  * PCI-E Bus transfers enough to measurably affect performance.
 165  */
 166 static int rx_dma_offset = 2;
 167
 168 /* TX Queue select used to determine what algorithm to use for selecting TX
 169  * queue. Select between the kernel provided function (select_queue=0) or user
 170  * cxgb_select_queue function (select_queue=1)
 171  *
 172  * Default: select_queue=0
 173  */
 174 static int select_queue;
 175 module_param(select_queue, int, 0644);
 176 MODULE_PARM_DESC(select_queue,
 177                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 178
 179 static struct dentry *cxgb4_debugfs_root;
 180
 181 LIST_HEAD(adapter_list);
 182 DEFINE_MUTEX(uld_mutex);
 183
 184 static int cfg_queues(struct adapter *adap);
 185
 186 static void link_report(struct net_device *dev)
 187 {
 188         if (!netif_carrier_ok(dev))
 189                 netdev_info(dev, "link down\n");
 190         else {
 191                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 192
 193                 const char *s;
 194                 const struct port_info *p = netdev_priv(dev);
 195
 196                 switch (p->link_cfg.speed) {
 197                 case 100:
 198                         s = "100Mbps";
 199                         break;
 200                 case 1000:
 201                         s = "1Gbps";
 202                         break;
 203                 case 10000:
 204                         s = "10Gbps";
 205                         break;
 206                 case 25000:
 207                         s = "25Gbps";
 208                         break;
 209                 case 40000:
 210                         s = "40Gbps";
 211                         break;
 212                 case 50000:
 213                         s = "50Gbps";
 214                         break;
 215                 case 100000:
 216                         s = "100Gbps";
 217                         break;
 218                 default:
 219                         pr_info("%s: unsupported speed: %d\n",
 220                                 dev->name, p->link_cfg.speed);
 221                         return;
 222                 }
 223
 224                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 225                             fc[p->link_cfg.fc]);
 226         }
 227 }
 228
 229 #ifdef CONFIG_CHELSIO_T4_DCB
 230 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 231 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 232 {
 233         struct port_info *pi = netdev_priv(dev);
 234         struct adapter *adap = pi->adapter;
 235         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 236         int i;
 237
 238         /* We use a simple mapping of Port TX Queue Index to DCB
 239          * Priority when we're enabling DCB.
 240          */
 241         for (i = 0; i < pi->nqsets; i++, txq++) {
 242                 u32 name, value;
 243                 int err;
 244
 245                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 246                         FW_PARAMS_PARAM_X_V(
 247                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 248                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 249                 value = enable ? i : 0xffffffff;
 250
 251                 /* Since we can be called while atomic (from "interrupt
 252                  * level") we need to issue the Set Parameters Commannd
 253                  * without sleeping (timeout < 0).
 254                  */
 255                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
 256                                             &name, &value,
 257                                             -FW_CMD_MAX_TIMEOUT);
 258
 259                 if (err)
 260                         dev_err(adap->pdev_dev,
 261                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 262                                 enable ? "set" : "unset", pi->port_id, i, -err);
 263                 else
 264                         txq->dcb_prio = enable ? value : 0;
 265         }
 266 }
 267
 268 int cxgb4_dcb_enabled(const struct net_device *dev)
 269 {
 270         struct port_info *pi = netdev_priv(dev);
 271
 272         if (!pi->dcb.enabled)
 273                 return 0;
 274
 275         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 276                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 277 }
 278 #endif /* CONFIG_CHELSIO_T4_DCB */
 279
 280 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 281 {
 282         struct net_device *dev = adapter->port[port_id];
 283
 284         /* Skip changes from disabled ports. */
 285         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 286                 if (link_stat)
 287                         netif_carrier_on(dev);
 288                 else {
 289 #ifdef CONFIG_CHELSIO_T4_DCB
 290                         if (cxgb4_dcb_enabled(dev)) {
 291                                 cxgb4_dcb_reset(dev);
 292                                 dcb_tx_queue_prio_enable(dev, false);
 293                         }
 294 #endif /* CONFIG_CHELSIO_T4_DCB */
 295                         netif_carrier_off(dev);
 296                 }
 297
 298                 link_report(dev);
 299         }
 300 }
 301
 302 void t4_os_portmod_changed(struct adapter *adap, int port_id)
 303 {
 304         static const char *mod_str[] = {
 305                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 306         };
 307
 308         struct net_device *dev = adap->port[port_id];
 309         struct port_info *pi = netdev_priv(dev);
 310
 311         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 312                 netdev_info(dev, "port module unplugged\n");
 313         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 314                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 315         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 316                 netdev_info(dev, "%s: unsupported port module inserted\n",
 317                             dev->name);
 318         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 319                 netdev_info(dev, "%s: unknown port module inserted\n",
 320                             dev->name);
 321         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 322                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
 323         else
 324                 netdev_info(dev, "%s: unknown module type %d inserted\n",
 325                             dev->name, pi->mod_type);
 326
 327         /* If the interface is running, then we'll need any "sticky" Link
 328          * Parameters redone with a new Transceiver Module.
 329          */
 330         pi->link_cfg.redo_l1cfg = netif_running(dev);
 331 }
 332
 333 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 334 module_param(dbfifo_int_thresh, int, 0644);
 335 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 336
 337 /*
 338  * usecs to sleep while draining the dbfifo
 339  */
 340 static int dbfifo_drain_delay = 1000;
 341 module_param(dbfifo_drain_delay, int, 0644);
 342 MODULE_PARM_DESC(dbfifo_drain_delay,
 343                  "usecs to sleep while draining the dbfifo");
 344
 345 static inline int cxgb4_set_addr_hash(struct port_info *pi)
 346 {
 347         struct adapter *adap = pi->adapter;
 348         u64 vec = 0;
 349         bool ucast = false;
 350         struct hash_mac_addr *entry;
 351
 352         /* Calculate the hash vector for the updated list and program it */
 353         list_for_each_entry(entry, &adap->mac_hlist, list) {
 354                 ucast |= is_unicast_ether_addr(entry->addr);
 355                 vec |= (1ULL << hash_mac_addr(entry->addr));
 356         }
 357         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
 358                                 vec, false);
 359 }
 360
 361 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
 362 {
 363         struct port_info *pi = netdev_priv(netdev);
 364         struct adapter *adap = pi->adapter;
 365         int ret;
 366         u64 mhash = 0;
 367         u64 uhash = 0;
 368         /* idx stores the index of allocated filters,
 369          * its size should be modified based on the number of
 370          * MAC addresses that we allocate filters for
 371          */
 372
 373         u16 idx[1] = {};
 374         bool free = false;
 375         bool ucast = is_unicast_ether_addr(mac_addr);
 376         const u8 *maclist[1] = {mac_addr};
 377         struct hash_mac_addr *new_entry;
 378
 379         ret = cxgb4_alloc_mac_filt(adap, pi->viid, free, 1, maclist,
 380                                    idx, ucast ? &uhash : &mhash, false);
 381         if (ret < 0)
 382                 goto out;
 383         /* if hash != 0, then add the addr to hash addr list
 384          * so on the end we will calculate the hash for the
 385          * list and program it
 386          */
 387         if (uhash || mhash) {
 388                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
 389                 if (!new_entry)
 390                         return -ENOMEM;
 391                 ether_addr_copy(new_entry->addr, mac_addr);
 392                 list_add_tail(&new_entry->list, &adap->mac_hlist);
 393                 ret = cxgb4_set_addr_hash(pi);
 394         }
 395 out:
 396         return ret < 0 ? ret : 0;
 397 }
 398
 399 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
 400 {
 401         struct port_info *pi = netdev_priv(netdev);
 402         struct adapter *adap = pi->adapter;
 403         int ret;
 404         const u8 *maclist[1] = {mac_addr};
 405         struct hash_mac_addr *entry, *tmp;
 406
 407         /* If the MAC address to be removed is in the hash addr
 408          * list, delete it from the list and update hash vector
 409          */
 410         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
 411                 if (ether_addr_equal(entry->addr, mac_addr)) {
 412                         list_del(&entry->list);
 413                         kfree(entry);
 414                         return cxgb4_set_addr_hash(pi);
 415                 }
 416         }
 417
 418         ret = cxgb4_free_mac_filt(adap, pi->viid, 1, maclist, false);
 419         return ret < 0 ? -EINVAL : 0;
 420 }
 421
 422 /*
 423  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 424  * If @mtu is -1 it is left unchanged.
 425  */
 426 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 427 {
 428         struct port_info *pi = netdev_priv(dev);
 429         struct adapter *adapter = pi->adapter;
 430
 431         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 432         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 433
 434         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
 435                              (dev->flags & IFF_PROMISC) ? 1 : 0,
 436                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 437                              sleep_ok);
 438 }
 439
 440 /**
 441  *      cxgb4_change_mac - Update match filter for a MAC address.
 442  *      @pi: the port_info
 443  *      @viid: the VI id
 444  *      @tcam_idx: TCAM index of existing filter for old value of MAC address,
 445  *                 or -1
 446  *      @addr: the new MAC address value
 447  *      @persist: whether a new MAC allocation should be persistent
 448  *      @add_smt: if true also add the address to the HW SMT
 449  *
 450  *      Modifies an MPS filter and sets it to the new MAC address if
 451  *      @tcam_idx >= 0, or adds the MAC address to a new filter if
 452  *      @tcam_idx < 0. In the latter case the address is added persistently
 453  *      if @persist is %true.
 454  *      Addresses are programmed to hash region, if tcam runs out of entries.
 455  *
 456  */
 457 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
 458                      int *tcam_idx, const u8 *addr, bool persist,
 459                      u8 *smt_idx)
 460 {
 461         struct adapter *adapter = pi->adapter;
 462         struct hash_mac_addr *entry, *new_entry;
 463         int ret;
 464
 465         ret = t4_change_mac(adapter, adapter->mbox, viid,
 466                             *tcam_idx, addr, persist, smt_idx);
 467         /* We ran out of TCAM entries. try programming hash region. */
 468         if (ret == -ENOMEM) {
 469                 /* If the MAC address to be updated is in the hash addr
 470                  * list, update it from the list
 471                  */
 472                 list_for_each_entry(entry, &adapter->mac_hlist, list) {
 473                         if (entry->iface_mac) {
 474                                 ether_addr_copy(entry->addr, addr);
 475                                 goto set_hash;
 476                         }
 477                 }
 478                 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
 479                 if (!new_entry)
 480                         return -ENOMEM;
 481                 ether_addr_copy(new_entry->addr, addr);
 482                 new_entry->iface_mac = true;
 483                 list_add_tail(&new_entry->list, &adapter->mac_hlist);
 484 set_hash:
 485                 ret = cxgb4_set_addr_hash(pi);
 486         } else if (ret >= 0) {
 487                 *tcam_idx = ret;
 488                 ret = 0;
 489         }
 490
 491         return ret;
 492 }
 493
 494 /*
 495  *      link_start - enable a port
 496  *      @dev: the port to enable
 497  *
 498  *      Performs the MAC and PHY actions needed to enable a port.
 499  */
 500 static int link_start(struct net_device *dev)
 501 {
 502         int ret;
 503         struct port_info *pi = netdev_priv(dev);
 504         unsigned int mb = pi->adapter->pf;
 505
 506         /*
 507          * We do not set address filters and promiscuity here, the stack does
 508          * that step explicitly.
 509          */
 510         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 511                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 512         if (ret == 0)
 513                 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
 514                                             dev->dev_addr, true, &pi->smt_idx);
 515         if (ret == 0)
 516                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
 517                                     &pi->link_cfg);
 518         if (ret == 0) {
 519                 local_bh_disable();
 520                 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
 521                                           true, CXGB4_DCB_ENABLED);
 522                 local_bh_enable();
 523         }
 524
 525         return ret;
 526 }
 527
 528 #ifdef CONFIG_CHELSIO_T4_DCB
 529 /* Handle a Data Center Bridging update message from the firmware. */
 530 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 531 {
 532         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 533         struct net_device *dev = adap->port[adap->chan_map[port]];
 534         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 535         int new_dcb_enabled;
 536
 537         cxgb4_dcb_handle_fw_update(adap, pcmd);
 538         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 539
 540         /* If the DCB has become enabled or disabled on the port then we're
 541          * going to need to set up/tear down DCB Priority parameters for the
 542          * TX Queues associated with the port.
 543          */
 544         if (new_dcb_enabled != old_dcb_enabled)
 545                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 546 }
 547 #endif /* CONFIG_CHELSIO_T4_DCB */
 548
 549 /* Response queue handler for the FW event queue.
 550  */
 551 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 552                           const struct pkt_gl *gl)
 553 {
 554         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 555
 556         rsp++;                                          /* skip RSS header */
 557
 558         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 559          */
 560         if (unlikely(opcode == CPL_FW4_MSG &&
 561            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 562                 rsp++;
 563                 opcode = ((const struct rss_header *)rsp)->opcode;
 564                 rsp++;
 565                 if (opcode != CPL_SGE_EGR_UPDATE) {
 566                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 567                                 , opcode);
 568                         goto out;
 569                 }
 570         }
 571
 572         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 573                 const struct cpl_sge_egr_update *p = (void *)rsp;
 574                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
 575                 struct sge_txq *txq;
 576
 577                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 578                 txq->restarts++;
 579                 if (txq->q_type == CXGB4_TXQ_ETH) {
 580                         struct sge_eth_txq *eq;
 581
 582                         eq = container_of(txq, struct sge_eth_txq, q);
 583                         t4_sge_eth_txq_egress_update(q->adap, eq, -1);
 584                 } else {
 585                         struct sge_uld_txq *oq;
 586
 587                         oq = container_of(txq, struct sge_uld_txq, q);
 588                         tasklet_schedule(&oq->qresume_tsk);
 589                 }
 590         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 591                 const struct cpl_fw6_msg *p = (void *)rsp;
 592
 593 #ifdef CONFIG_CHELSIO_T4_DCB
 594                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 595                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 596                 unsigned int action =
 597                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 598
 599                 if (cmd == FW_PORT_CMD &&
 600                     (action == FW_PORT_ACTION_GET_PORT_INFO ||
 601                      action == FW_PORT_ACTION_GET_PORT_INFO32)) {
 602                         int port = FW_PORT_CMD_PORTID_G(
 603                                         be32_to_cpu(pcmd->op_to_portid));
 604                         struct net_device *dev;
 605                         int dcbxdis, state_input;
 606
 607                         dev = q->adap->port[q->adap->chan_map[port]];
 608                         dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
 609                           ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
 610                           : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
 611                                & FW_PORT_CMD_DCBXDIS32_F));
 612                         state_input = (dcbxdis
 613                                        ? CXGB4_DCB_INPUT_FW_DISABLED
 614                                        : CXGB4_DCB_INPUT_FW_ENABLED);
 615
 616                         cxgb4_dcb_state_fsm(dev, state_input);
 617                 }
 618
 619                 if (cmd == FW_PORT_CMD &&
 620                     action == FW_PORT_ACTION_L2_DCB_CFG)
 621                         dcb_rpl(q->adap, pcmd);
 622                 else
 623 #endif
 624                         if (p->type == 0)
 625                                 t4_handle_fw_rpl(q->adap, p->data);
 626         } else if (opcode == CPL_L2T_WRITE_RPL) {
 627                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 628
 629                 do_l2t_write_rpl(q->adap, p);
 630         } else if (opcode == CPL_SMT_WRITE_RPL) {
 631                 const struct cpl_smt_write_rpl *p = (void *)rsp;
 632
 633                 do_smt_write_rpl(q->adap, p);
 634         } else if (opcode == CPL_SET_TCB_RPL) {
 635                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 636
 637                 filter_rpl(q->adap, p);
 638         } else if (opcode == CPL_ACT_OPEN_RPL) {
 639                 const struct cpl_act_open_rpl *p = (void *)rsp;
 640
 641                 hash_filter_rpl(q->adap, p);
 642         } else if (opcode == CPL_ABORT_RPL_RSS) {
 643                 const struct cpl_abort_rpl_rss *p = (void *)rsp;
 644
 645                 hash_del_filter_rpl(q->adap, p);
 646         } else if (opcode == CPL_SRQ_TABLE_RPL) {
 647                 const struct cpl_srq_table_rpl *p = (void *)rsp;
 648
 649                 do_srq_table_rpl(q->adap, p);
 650         } else
 651                 dev_err(q->adap->pdev_dev,
 652                         "unexpected CPL %#x on FW event queue\n", opcode);
 653 out:
 654         return 0;
 655 }
 656
 657 static void disable_msi(struct adapter *adapter)
 658 {
 659         if (adapter->flags & CXGB4_USING_MSIX) {
 660                 pci_disable_msix(adapter->pdev);
 661                 adapter->flags &= ~CXGB4_USING_MSIX;
 662         } else if (adapter->flags & CXGB4_USING_MSI) {
 663                 pci_disable_msi(adapter->pdev);
 664                 adapter->flags &= ~CXGB4_USING_MSI;
 665         }
 666 }
 667
 668 /*
 669  * Interrupt handler for non-data events used with MSI-X.
 670  */
 671 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 672 {
 673         struct adapter *adap = cookie;
 674         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
 675
 676         if (v & PFSW_F) {
 677                 adap->swintr = 1;
 678                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
 679         }
 680         if (adap->flags & CXGB4_MASTER_PF)
 681                 t4_slow_intr_handler(adap);
 682         return IRQ_HANDLED;
 683 }
 684
 685 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
 686                        cpumask_var_t *aff_mask, int idx)
 687 {
 688         int rv;
 689
 690         if (!zalloc_cpumask_var(aff_mask, GFP_KERNEL)) {
 691                 dev_err(adap->pdev_dev, "alloc_cpumask_var failed\n");
 692                 return -ENOMEM;
 693         }
 694
 695         cpumask_set_cpu(cpumask_local_spread(idx, dev_to_node(adap->pdev_dev)),
 696                         *aff_mask);
 697
 698         rv = irq_set_affinity_hint(vec, *aff_mask);
 699         if (rv)
 700                 dev_warn(adap->pdev_dev,
 701                          "irq_set_affinity_hint %u failed %d\n",
 702                          vec, rv);
 703
 704         return 0;
 705 }
 706
 707 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask)
 708 {
 709         irq_set_affinity_hint(vec, NULL);
 710         free_cpumask_var(aff_mask);
 711 }
 712
 713 static int request_msix_queue_irqs(struct adapter *adap)
 714 {
 715         struct sge *s = &adap->sge;
 716         struct msix_info *minfo;
 717         int err, ethqidx;
 718
 719         if (s->fwevtq_msix_idx < 0)
 720                 return -ENOMEM;
 721
 722         err = request_irq(adap->msix_info[s->fwevtq_msix_idx].vec,
 723                           t4_sge_intr_msix, 0,
 724                           adap->msix_info[s->fwevtq_msix_idx].desc,
 725                           &s->fw_evtq);
 726         if (err)
 727                 return err;
 728
 729         for_each_ethrxq(s, ethqidx) {
 730                 minfo = s->ethrxq[ethqidx].msix;
 731                 err = request_irq(minfo->vec,
 732                                   t4_sge_intr_msix, 0,
 733                                   minfo->desc,
 734                                   &s->ethrxq[ethqidx].rspq);
 735                 if (err)
 736                         goto unwind;
 737
 738                 cxgb4_set_msix_aff(adap, minfo->vec,
 739                                    &minfo->aff_mask, ethqidx);
 740         }
 741         return 0;
 742
 743 unwind:
 744         while (--ethqidx >= 0) {
 745                 minfo = s->ethrxq[ethqidx].msix;
 746                 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
 747                 free_irq(minfo->vec, &s->ethrxq[ethqidx].rspq);
 748         }
 749         free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq);
 750         return err;
 751 }
 752
 753 static void free_msix_queue_irqs(struct adapter *adap)
 754 {
 755         struct sge *s = &adap->sge;
 756         struct msix_info *minfo;
 757         int i;
 758
 759         free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq);
 760         for_each_ethrxq(s, i) {
 761                 minfo = s->ethrxq[i].msix;
 762                 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
 763                 free_irq(minfo->vec, &s->ethrxq[i].rspq);
 764         }
 765 }
 766
 767 static int setup_ppod_edram(struct adapter *adap)
 768 {
 769         unsigned int param, val;
 770         int ret;
 771
 772         /* Driver sends FW_PARAMS_PARAM_DEV_PPOD_EDRAM read command to check
 773          * if firmware supports ppod edram feature or not. If firmware
 774          * returns 1, then driver can enable this feature by sending
 775          * FW_PARAMS_PARAM_DEV_PPOD_EDRAM write command with value 1 to
 776          * enable ppod edram feature.
 777          */
 778         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
 779                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PPOD_EDRAM));
 780
 781         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
 782         if (ret < 0) {
 783                 dev_warn(adap->pdev_dev,
 784                          "querying PPOD_EDRAM support failed: %d\n",
 785                          ret);
 786                 return -1;
 787         }
 788
 789         if (val != 1)
 790                 return -1;
 791
 792         ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
 793         if (ret < 0) {
 794                 dev_err(adap->pdev_dev,
 795                         "setting PPOD_EDRAM failed: %d\n", ret);
 796                 return -1;
 797         }
 798         return 0;
 799 }
 800
 801 static void adap_config_hpfilter(struct adapter *adapter)
 802 {
 803         u32 param, val = 0;
 804         int ret;
 805
 806         /* Enable HP filter region. Older fw will fail this request and
 807          * it is fine.
 808          */
 809         param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
 810         ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0,
 811                             1, &param, &val);
 812
 813         /* An error means FW doesn't know about HP filter support,
 814          * it's not a problem, don't return an error.
 815          */
 816         if (ret < 0)
 817                 dev_err(adapter->pdev_dev,
 818                         "HP filter region isn't supported by FW\n");
 819 }
 820
 821 /**
 822  *      cxgb4_write_rss - write the RSS table for a given port
 823  *      @pi: the port
 824  *      @queues: array of queue indices for RSS
 825  *
 826  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 827  *      packets to the Rx queues in @queues.
 828  *      Should never be called before setting up sge eth rx queues
 829  */
 830 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 831 {
 832         u16 *rss;
 833         int i, err;
 834         struct adapter *adapter = pi->adapter;
 835         const struct sge_eth_rxq *rxq;
 836
 837         rxq = &adapter->sge.ethrxq[pi->first_qset];
 838         rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
 839         if (!rss)
 840                 return -ENOMEM;
 841
 842         /* map the queue indices to queue ids */
 843         for (i = 0; i < pi->rss_size; i++, queues++)
 844                 rss[i] = rxq[*queues].rspq.abs_id;
 845
 846         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 847                                   pi->rss_size, rss, pi->rss_size);
 848         /* If Tunnel All Lookup isn't specified in the global RSS
 849          * Configuration, then we need to specify a default Ingress
 850          * Queue for any ingress packets which aren't hashed.  We'll
 851          * use our first ingress queue ...
 852          */
 853         if (!err)
 854                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 855                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
 856                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
 857                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
 858                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
 859                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
 860                                        rss[0]);
 861         kfree(rss);
 862         return err;
 863 }
 864
 865 /**
 866  *      setup_rss - configure RSS
 867  *      @adap: the adapter
 868  *
 869  *      Sets up RSS for each port.
 870  */
 871 static int setup_rss(struct adapter *adap)
 872 {
 873         int i, j, err;
 874
 875         for_each_port(adap, i) {
 876                 const struct port_info *pi = adap2pinfo(adap, i);
 877
 878                 /* Fill default values with equal distribution */
 879                 for (j = 0; j < pi->rss_size; j++)
 880                         pi->rss[j] = j % pi->nqsets;
 881
 882                 err = cxgb4_write_rss(pi, pi->rss);
 883                 if (err)
 884                         return err;
 885         }
 886         return 0;
 887 }
 888
 889 /*
 890  * Return the channel of the ingress queue with the given qid.
 891  */
 892 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
 893 {
 894         qid -= p->ingr_start;
 895         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
 896 }
 897
 898 void cxgb4_quiesce_rx(struct sge_rspq *q)
 899 {
 900         if (q->handler)
 901                 napi_disable(&q->napi);
 902 }
 903
 904 /*
 905  * Wait until all NAPI handlers are descheduled.
 906  */
 907 static void quiesce_rx(struct adapter *adap)
 908 {
 909         int i;
 910
 911         for (i = 0; i < adap->sge.ingr_sz; i++) {
 912                 struct sge_rspq *q = adap->sge.ingr_map[i];
 913
 914                 if (!q)
 915                         continue;
 916
 917                 cxgb4_quiesce_rx(q);
 918         }
 919 }
 920
 921 /* Disable interrupt and napi handler */
 922 static void disable_interrupts(struct adapter *adap)
 923 {
 924         struct sge *s = &adap->sge;
 925
 926         if (adap->flags & CXGB4_FULL_INIT_DONE) {
 927                 t4_intr_disable(adap);
 928                 if (adap->flags & CXGB4_USING_MSIX) {
 929                         free_msix_queue_irqs(adap);
 930                         free_irq(adap->msix_info[s->nd_msix_idx].vec,
 931                                  adap);
 932                 } else {
 933                         free_irq(adap->pdev->irq, adap);
 934                 }
 935                 quiesce_rx(adap);
 936         }
 937 }
 938
 939 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q)
 940 {
 941         if (q->handler)
 942                 napi_enable(&q->napi);
 943
 944         /* 0-increment GTS to start the timer and enable interrupts */
 945         t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 946                      SEINTARM_V(q->intr_params) |
 947                      INGRESSQID_V(q->cntxt_id));
 948 }
 949
 950 /*
 951  * Enable NAPI scheduling and interrupt generation for all Rx queues.
 952  */
 953 static void enable_rx(struct adapter *adap)
 954 {
 955         int i;
 956
 957         for (i = 0; i < adap->sge.ingr_sz; i++) {
 958                 struct sge_rspq *q = adap->sge.ingr_map[i];
 959
 960                 if (!q)
 961                         continue;
 962
 963                 cxgb4_enable_rx(adap, q);
 964         }
 965 }
 966
 967 static int setup_non_data_intr(struct adapter *adap)
 968 {
 969         int msix;
 970
 971         adap->sge.nd_msix_idx = -1;
 972         if (!(adap->flags & CXGB4_USING_MSIX))
 973                 return 0;
 974
 975         /* Request MSI-X vector for non-data interrupt */
 976         msix = cxgb4_get_msix_idx_from_bmap(adap);
 977         if (msix < 0)
 978                 return -ENOMEM;
 979
 980         snprintf(adap->msix_info[msix].desc,
 981                  sizeof(adap->msix_info[msix].desc),
 982                  "%s", adap->port[0]->name);
 983
 984         adap->sge.nd_msix_idx = msix;
 985         return 0;
 986 }
 987
 988 static int setup_fw_sge_queues(struct adapter *adap)
 989 {
 990         struct sge *s = &adap->sge;
 991         int msix, err = 0;
 992
 993         bitmap_zero(s->starving_fl, s->egr_sz);
 994         bitmap_zero(s->txq_maperr, s->egr_sz);
 995
 996         if (adap->flags & CXGB4_USING_MSIX) {
 997                 s->fwevtq_msix_idx = -1;
 998                 msix = cxgb4_get_msix_idx_from_bmap(adap);
 999                 if (msix < 0)
1000                         return -ENOMEM;
1001
1002                 snprintf(adap->msix_info[msix].desc,
1003                          sizeof(adap->msix_info[msix].desc),
1004                          "%s-FWeventq", adap->port[0]->name);
1005         } else {
1006                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1007                                        NULL, NULL, NULL, -1);
1008                 if (err)
1009                         return err;
1010                 msix = -((int)s->intrq.abs_id + 1);
1011         }
1012
1013         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1014                                msix, NULL, fwevtq_handler, NULL, -1);
1015         if (err && msix >= 0)
1016                 cxgb4_free_msix_idx_in_bmap(adap, msix);
1017
1018         s->fwevtq_msix_idx = msix;
1019         return err;
1020 }
1021
1022 /**
1023  *      setup_sge_queues - configure SGE Tx/Rx/response queues
1024  *      @adap: the adapter
1025  *
1026  *      Determines how many sets of SGE queues to use and initializes them.
1027  *      We support multiple queue sets per port if we have MSI-X, otherwise
1028  *      just one queue set per port.
1029  */
1030 static int setup_sge_queues(struct adapter *adap)
1031 {
1032         struct sge_uld_rxq_info *rxq_info = NULL;
1033         struct sge *s = &adap->sge;
1034         unsigned int cmplqid = 0;
1035         int err, i, j, msix = 0;
1036
1037         if (is_uld(adap))
1038                 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
1039
1040         if (!(adap->flags & CXGB4_USING_MSIX))
1041                 msix = -((int)s->intrq.abs_id + 1);
1042
1043         for_each_port(adap, i) {
1044                 struct net_device *dev = adap->port[i];
1045                 struct port_info *pi = netdev_priv(dev);
1046                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1047                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1048
1049                 for (j = 0; j < pi->nqsets; j++, q++) {
1050                         if (msix >= 0) {
1051                                 msix = cxgb4_get_msix_idx_from_bmap(adap);
1052                                 if (msix < 0) {
1053                                         err = msix;
1054                                         goto freeout;
1055                                 }
1056
1057                                 snprintf(adap->msix_info[msix].desc,
1058                                          sizeof(adap->msix_info[msix].desc),
1059                                          "%s-Rx%d", dev->name, j);
1060                                 q->msix = &adap->msix_info[msix];
1061                         }
1062
1063                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1064                                                msix, &q->fl,
1065                                                t4_ethrx_handler,
1066                                                NULL,
1067                                                t4_get_tp_ch_map(adap,
1068                                                                 pi->tx_chan));
1069                         if (err)
1070                                 goto freeout;
1071                         q->rspq.idx = j;
1072                         memset(&q->stats, 0, sizeof(q->stats));
1073                 }
1074
1075                 q = &s->ethrxq[pi->first_qset];
1076                 for (j = 0; j < pi->nqsets; j++, t++, q++) {
1077                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1078                                         netdev_get_tx_queue(dev, j),
1079                                         q->rspq.cntxt_id,
1080                                         !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
1081                         if (err)
1082                                 goto freeout;
1083                 }
1084         }
1085
1086         for_each_port(adap, i) {
1087                 /* Note that cmplqid below is 0 if we don't
1088                  * have RDMA queues, and that's the right value.
1089                  */
1090                 if (rxq_info)
1091                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
1092
1093                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1094                                             s->fw_evtq.cntxt_id, cmplqid);
1095                 if (err)
1096                         goto freeout;
1097         }
1098
1099         if (!is_t4(adap->params.chip)) {
1100                 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
1101                                            netdev_get_tx_queue(adap->port[0], 0)
1102                                            , s->fw_evtq.cntxt_id, false);
1103                 if (err)
1104                         goto freeout;
1105         }
1106
1107         t4_write_reg(adap, is_t4(adap->params.chip) ?
1108                                 MPS_TRC_RSS_CONTROL_A :
1109                                 MPS_T5_TRC_RSS_CONTROL_A,
1110                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1111                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1112         return 0;
1113 freeout:
1114         dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
1115         t4_free_sge_resources(adap);
1116         return err;
1117 }
1118
1119 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1120                              struct net_device *sb_dev)
1121 {
1122         int txq;
1123
1124 #ifdef CONFIG_CHELSIO_T4_DCB
1125         /* If a Data Center Bridging has been successfully negotiated on this
1126          * link then we'll use the skb's priority to map it to a TX Queue.
1127          * The skb's priority is determined via the VLAN Tag Priority Code
1128          * Point field.
1129          */
1130         if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
1131                 u16 vlan_tci;
1132                 int err;
1133
1134                 err = vlan_get_tag(skb, &vlan_tci);
1135                 if (unlikely(err)) {
1136                         if (net_ratelimit())
1137                                 netdev_warn(dev,
1138                                             "TX Packet without VLAN Tag on DCB Link\n");
1139                         txq = 0;
1140                 } else {
1141                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1142 #ifdef CONFIG_CHELSIO_T4_FCOE
1143                         if (skb->protocol == htons(ETH_P_FCOE))
1144                                 txq = skb->priority & 0x7;
1145 #endif /* CONFIG_CHELSIO_T4_FCOE */
1146                 }
1147                 return txq;
1148         }
1149 #endif /* CONFIG_CHELSIO_T4_DCB */
1150
1151         if (dev->num_tc) {
1152                 struct port_info *pi = netdev2pinfo(dev);
1153                 u8 ver, proto;
1154
1155                 ver = ip_hdr(skb)->version;
1156                 proto = (ver == 6) ? ipv6_hdr(skb)->nexthdr :
1157                                      ip_hdr(skb)->protocol;
1158
1159                 /* Send unsupported traffic pattern to normal NIC queues. */
1160                 txq = netdev_pick_tx(dev, skb, sb_dev);
1161                 if (xfrm_offload(skb) || is_ptp_enabled(skb, dev) ||
1162                     skb->encapsulation ||
1163                     (proto != IPPROTO_TCP && proto != IPPROTO_UDP))
1164                         txq = txq % pi->nqsets;
1165
1166                 return txq;
1167         }
1168
1169         if (select_queue) {
1170                 txq = (skb_rx_queue_recorded(skb)
1171                         ? skb_get_rx_queue(skb)
1172                         : smp_processor_id());
1173
1174                 while (unlikely(txq >= dev->real_num_tx_queues))
1175                         txq -= dev->real_num_tx_queues;
1176
1177                 return txq;
1178         }
1179
1180         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
1181 }
1182
1183 static int closest_timer(const struct sge *s, int time)
1184 {
1185         int i, delta, match = 0, min_delta = INT_MAX;
1186
1187         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1188                 delta = time - s->timer_val[i];
1189                 if (delta < 0)
1190                         delta = -delta;
1191                 if (delta < min_delta) {
1192                         min_delta = delta;
1193                         match = i;
1194                 }
1195         }
1196         return match;
1197 }
1198
1199 static int closest_thres(const struct sge *s, int thres)
1200 {
1201         int i, delta, match = 0, min_delta = INT_MAX;
1202
1203         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1204                 delta = thres - s->counter_val[i];
1205                 if (delta < 0)
1206                         delta = -delta;
1207                 if (delta < min_delta) {
1208                         min_delta = delta;
1209                         match = i;
1210                 }
1211         }
1212         return match;
1213 }
1214
1215 /**
1216  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1217  *      @q: the Rx queue
1218  *      @us: the hold-off time in us, or 0 to disable timer
1219  *      @cnt: the hold-off packet count, or 0 to disable counter
1220  *
1221  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
1222  *      one of the two needs to be enabled for the queue to generate interrupts.
1223  */
1224 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1225                                unsigned int us, unsigned int cnt)
1226 {
1227         struct adapter *adap = q->adap;
1228
1229         if ((us | cnt) == 0)
1230                 cnt = 1;
1231
1232         if (cnt) {
1233                 int err;
1234                 u32 v, new_idx;
1235
1236                 new_idx = closest_thres(&adap->sge, cnt);
1237                 if (q->desc && q->pktcnt_idx != new_idx) {
1238                         /* the queue has already been created, update it */
1239                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1240                             FW_PARAMS_PARAM_X_V(
1241                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1242                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1243                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1244                                             &v, &new_idx);
1245                         if (err)
1246                                 return err;
1247                 }
1248                 q->pktcnt_idx = new_idx;
1249         }
1250
1251         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1252         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1253         return 0;
1254 }
1255
1256 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1257 {
1258         const struct port_info *pi = netdev_priv(dev);
1259         netdev_features_t changed = dev->features ^ features;
1260         int err;
1261
1262         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1263                 return 0;
1264
1265         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1266                             -1, -1, -1,
1267                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1268         if (unlikely(err))
1269                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1270         return err;
1271 }
1272
1273 static int setup_debugfs(struct adapter *adap)
1274 {
1275         if (IS_ERR_OR_NULL(adap->debugfs_root))
1276                 return -1;
1277
1278 #ifdef CONFIG_DEBUG_FS
1279         t4_setup_debugfs(adap);
1280 #endif
1281         return 0;
1282 }
1283
1284 /*
1285  * upper-layer driver support
1286  */
1287
1288 /*
1289  * Allocate an active-open TID and set it to the supplied value.
1290  */
1291 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1292 {
1293         int atid = -1;
1294
1295         spin_lock_bh(&t->atid_lock);
1296         if (t->afree) {
1297                 union aopen_entry *p = t->afree;
1298
1299                 atid = (p - t->atid_tab) + t->atid_base;
1300                 t->afree = p->next;
1301                 p->data = data;
1302                 t->atids_in_use++;
1303         }
1304         spin_unlock_bh(&t->atid_lock);
1305         return atid;
1306 }
1307 EXPORT_SYMBOL(cxgb4_alloc_atid);
1308
1309 /*
1310  * Release an active-open TID.
1311  */
1312 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1313 {
1314         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1315
1316         spin_lock_bh(&t->atid_lock);
1317         p->next = t->afree;
1318         t->afree = p;
1319         t->atids_in_use--;
1320         spin_unlock_bh(&t->atid_lock);
1321 }
1322 EXPORT_SYMBOL(cxgb4_free_atid);
1323
1324 /*
1325  * Allocate a server TID and set it to the supplied value.
1326  */
1327 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1328 {
1329         int stid;
1330
1331         spin_lock_bh(&t->stid_lock);
1332         if (family == PF_INET) {
1333                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1334                 if (stid < t->nstids)
1335                         __set_bit(stid, t->stid_bmap);
1336                 else
1337                         stid = -1;
1338         } else {
1339                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1340                 if (stid < 0)
1341                         stid = -1;
1342         }
1343         if (stid >= 0) {
1344                 t->stid_tab[stid].data = data;
1345                 stid += t->stid_base;
1346                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1347                  * This is equivalent to 4 TIDs. With CLIP enabled it
1348                  * needs 2 TIDs.
1349                  */
1350                 if (family == PF_INET6) {
1351                         t->stids_in_use += 2;
1352                         t->v6_stids_in_use += 2;
1353                 } else {
1354                         t->stids_in_use++;
1355                 }
1356         }
1357         spin_unlock_bh(&t->stid_lock);
1358         return stid;
1359 }
1360 EXPORT_SYMBOL(cxgb4_alloc_stid);
1361
1362 /* Allocate a server filter TID and set it to the supplied value.
1363  */
1364 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1365 {
1366         int stid;
1367
1368         spin_lock_bh(&t->stid_lock);
1369         if (family == PF_INET) {
1370                 stid = find_next_zero_bit(t->stid_bmap,
1371                                 t->nstids + t->nsftids, t->nstids);
1372                 if (stid < (t->nstids + t->nsftids))
1373                         __set_bit(stid, t->stid_bmap);
1374                 else
1375                         stid = -1;
1376         } else {
1377                 stid = -1;
1378         }
1379         if (stid >= 0) {
1380                 t->stid_tab[stid].data = data;
1381                 stid -= t->nstids;
1382                 stid += t->sftid_base;
1383                 t->sftids_in_use++;
1384         }
1385         spin_unlock_bh(&t->stid_lock);
1386         return stid;
1387 }
1388 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1389
1390 /* Release a server TID.
1391  */
1392 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1393 {
1394         /* Is it a server filter TID? */
1395         if (t->nsftids && (stid >= t->sftid_base)) {
1396                 stid -= t->sftid_base;
1397                 stid += t->nstids;
1398         } else {
1399                 stid -= t->stid_base;
1400         }
1401
1402         spin_lock_bh(&t->stid_lock);
1403         if (family == PF_INET)
1404                 __clear_bit(stid, t->stid_bmap);
1405         else
1406                 bitmap_release_region(t->stid_bmap, stid, 1);
1407         t->stid_tab[stid].data = NULL;
1408         if (stid < t->nstids) {
1409                 if (family == PF_INET6) {
1410                         t->stids_in_use -= 2;
1411                         t->v6_stids_in_use -= 2;
1412                 } else {
1413                         t->stids_in_use--;
1414                 }
1415         } else {
1416                 t->sftids_in_use--;
1417         }
1418
1419         spin_unlock_bh(&t->stid_lock);
1420 }
1421 EXPORT_SYMBOL(cxgb4_free_stid);
1422
1423 /*
1424  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1425  */
1426 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1427                            unsigned int tid)
1428 {
1429         struct cpl_tid_release *req;
1430
1431         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1432         req = __skb_put(skb, sizeof(*req));
1433         INIT_TP_WR(req, tid);
1434         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1435 }
1436
1437 /*
1438  * Queue a TID release request and if necessary schedule a work queue to
1439  * process it.
1440  */
1441 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1442                                     unsigned int tid)
1443 {
1444         struct adapter *adap = container_of(t, struct adapter, tids);
1445         void **p = &t->tid_tab[tid - t->tid_base];
1446
1447         spin_lock_bh(&adap->tid_release_lock);
1448         *p = adap->tid_release_head;
1449         /* Low 2 bits encode the Tx channel number */
1450         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1451         if (!adap->tid_release_task_busy) {
1452                 adap->tid_release_task_busy = true;
1453                 queue_work(adap->workq, &adap->tid_release_task);
1454         }
1455         spin_unlock_bh(&adap->tid_release_lock);
1456 }
1457
1458 /*
1459  * Process the list of pending TID release requests.
1460  */
1461 static void process_tid_release_list(struct work_struct *work)
1462 {
1463         struct sk_buff *skb;
1464         struct adapter *adap;
1465
1466         adap = container_of(work, struct adapter, tid_release_task);
1467
1468         spin_lock_bh(&adap->tid_release_lock);
1469         while (adap->tid_release_head) {
1470                 void **p = adap->tid_release_head;
1471                 unsigned int chan = (uintptr_t)p & 3;
1472                 p = (void *)p - chan;
1473
1474                 adap->tid_release_head = *p;
1475                 *p = NULL;
1476                 spin_unlock_bh(&adap->tid_release_lock);
1477
1478                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1479                                          GFP_KERNEL)))
1480                         schedule_timeout_uninterruptible(1);
1481
1482                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1483                 t4_ofld_send(adap, skb);
1484                 spin_lock_bh(&adap->tid_release_lock);
1485         }
1486         adap->tid_release_task_busy = false;
1487         spin_unlock_bh(&adap->tid_release_lock);
1488 }
1489
1490 /*
1491  * Release a TID and inform HW.  If we are unable to allocate the release
1492  * message we defer to a work queue.
1493  */
1494 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1495                       unsigned short family)
1496 {
1497         struct adapter *adap = container_of(t, struct adapter, tids);
1498         struct sk_buff *skb;
1499
1500         WARN_ON(tid_out_of_range(&adap->tids, tid));
1501
1502         if (t->tid_tab[tid - adap->tids.tid_base]) {
1503                 t->tid_tab[tid - adap->tids.tid_base] = NULL;
1504                 atomic_dec(&t->conns_in_use);
1505                 if (t->hash_base && (tid >= t->hash_base)) {
1506                         if (family == AF_INET6)
1507                                 atomic_sub(2, &t->hash_tids_in_use);
1508                         else
1509                                 atomic_dec(&t->hash_tids_in_use);
1510                 } else {
1511                         if (family == AF_INET6)
1512                                 atomic_sub(2, &t->tids_in_use);
1513                         else
1514                                 atomic_dec(&t->tids_in_use);
1515                 }
1516         }
1517
1518         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1519         if (likely(skb)) {
1520                 mk_tid_release(skb, chan, tid);
1521                 t4_ofld_send(adap, skb);
1522         } else
1523                 cxgb4_queue_tid_release(t, chan, tid);
1524 }
1525 EXPORT_SYMBOL(cxgb4_remove_tid);
1526
1527 /*
1528  * Allocate and initialize the TID tables.  Returns 0 on success.
1529  */
1530 static int tid_init(struct tid_info *t)
1531 {
1532         struct adapter *adap = container_of(t, struct adapter, tids);
1533         unsigned int max_ftids = t->nftids + t->nsftids;
1534         unsigned int natids = t->natids;
1535         unsigned int hpftid_bmap_size;
1536         unsigned int eotid_bmap_size;
1537         unsigned int stid_bmap_size;
1538         unsigned int ftid_bmap_size;
1539         size_t size;
1540
1541         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1542         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1543         hpftid_bmap_size = BITS_TO_LONGS(t->nhpftids);
1544         eotid_bmap_size = BITS_TO_LONGS(t->neotids);
1545         size = t->ntids * sizeof(*t->tid_tab) +
1546                natids * sizeof(*t->atid_tab) +
1547                t->nstids * sizeof(*t->stid_tab) +
1548                t->nsftids * sizeof(*t->stid_tab) +
1549                stid_bmap_size * sizeof(long) +
1550                t->nhpftids * sizeof(*t->hpftid_tab) +
1551                hpftid_bmap_size * sizeof(long) +
1552                max_ftids * sizeof(*t->ftid_tab) +
1553                ftid_bmap_size * sizeof(long) +
1554                t->neotids * sizeof(*t->eotid_tab) +
1555                eotid_bmap_size * sizeof(long);
1556
1557         t->tid_tab = kvzalloc(size, GFP_KERNEL);
1558         if (!t->tid_tab)
1559                 return -ENOMEM;
1560
1561         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1562         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1563         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1564         t->hpftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1565         t->hpftid_bmap = (unsigned long *)&t->hpftid_tab[t->nhpftids];
1566         t->ftid_tab = (struct filter_entry *)&t->hpftid_bmap[hpftid_bmap_size];
1567         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1568         t->eotid_tab = (struct eotid_entry *)&t->ftid_bmap[ftid_bmap_size];
1569         t->eotid_bmap = (unsigned long *)&t->eotid_tab[t->neotids];
1570         spin_lock_init(&t->stid_lock);
1571         spin_lock_init(&t->atid_lock);
1572         spin_lock_init(&t->ftid_lock);
1573
1574         t->stids_in_use = 0;
1575         t->v6_stids_in_use = 0;
1576         t->sftids_in_use = 0;
1577         t->afree = NULL;
1578         t->atids_in_use = 0;
1579         atomic_set(&t->tids_in_use, 0);
1580         atomic_set(&t->conns_in_use, 0);
1581         atomic_set(&t->hash_tids_in_use, 0);
1582         atomic_set(&t->eotids_in_use, 0);
1583
1584         /* Setup the free list for atid_tab and clear the stid bitmap. */
1585         if (natids) {
1586                 while (--natids)
1587                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1588                 t->afree = t->atid_tab;
1589         }
1590
1591         if (is_offload(adap)) {
1592                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1593                 /* Reserve stid 0 for T4/T5 adapters */
1594                 if (!t->stid_base &&
1595                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1596                         __set_bit(0, t->stid_bmap);
1597
1598                 if (t->neotids)
1599                         bitmap_zero(t->eotid_bmap, t->neotids);
1600         }
1601
1602         if (t->nhpftids)
1603                 bitmap_zero(t->hpftid_bmap, t->nhpftids);
1604         bitmap_zero(t->ftid_bmap, t->nftids);
1605         return 0;
1606 }
1607
1608 /**
1609  *      cxgb4_create_server - create an IP server
1610  *      @dev: the device
1611  *      @stid: the server TID
1612  *      @sip: local IP address to bind server to
1613  *      @sport: the server's TCP port
1614  *      @queue: queue to direct messages from this server to
1615  *
1616  *      Create an IP server for the given port and address.
1617  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1618  */
1619 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1620                         __be32 sip, __be16 sport, __be16 vlan,
1621                         unsigned int queue)
1622 {
1623         unsigned int chan;
1624         struct sk_buff *skb;
1625         struct adapter *adap;
1626         struct cpl_pass_open_req *req;
1627         int ret;
1628
1629         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1630         if (!skb)
1631                 return -ENOMEM;
1632
1633         adap = netdev2adap(dev);
1634         req = __skb_put(skb, sizeof(*req));
1635         INIT_TP_WR(req, 0);
1636         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1637         req->local_port = sport;
1638         req->peer_port = htons(0);
1639         req->local_ip = sip;
1640         req->peer_ip = htonl(0);
1641         chan = rxq_to_chan(&adap->sge, queue);
1642         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1643         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1644                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1645         ret = t4_mgmt_tx(adap, skb);
1646         return net_xmit_eval(ret);
1647 }
1648 EXPORT_SYMBOL(cxgb4_create_server);
1649
1650 /*      cxgb4_create_server6 - create an IPv6 server
1651  *      @dev: the device
1652  *      @stid: the server TID
1653  *      @sip: local IPv6 address to bind server to
1654  *      @sport: the server's TCP port
1655  *      @queue: queue to direct messages from this server to
1656  *
1657  *      Create an IPv6 server for the given port and address.
1658  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1659  */
1660 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1661                          const struct in6_addr *sip, __be16 sport,
1662                          unsigned int queue)
1663 {
1664         unsigned int chan;
1665         struct sk_buff *skb;
1666         struct adapter *adap;
1667         struct cpl_pass_open_req6 *req;
1668         int ret;
1669
1670         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1671         if (!skb)
1672                 return -ENOMEM;
1673
1674         adap = netdev2adap(dev);
1675         req = __skb_put(skb, sizeof(*req));
1676         INIT_TP_WR(req, 0);
1677         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1678         req->local_port = sport;
1679         req->peer_port = htons(0);
1680         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1681         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1682         req->peer_ip_hi = cpu_to_be64(0);
1683         req->peer_ip_lo = cpu_to_be64(0);
1684         chan = rxq_to_chan(&adap->sge, queue);
1685         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1686         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1687                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1688         ret = t4_mgmt_tx(adap, skb);
1689         return net_xmit_eval(ret);
1690 }
1691 EXPORT_SYMBOL(cxgb4_create_server6);
1692
1693 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1694                         unsigned int queue, bool ipv6)
1695 {
1696         struct sk_buff *skb;
1697         struct adapter *adap;
1698         struct cpl_close_listsvr_req *req;
1699         int ret;
1700
1701         adap = netdev2adap(dev);
1702
1703         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1704         if (!skb)
1705                 return -ENOMEM;
1706
1707         req = __skb_put(skb, sizeof(*req));
1708         INIT_TP_WR(req, 0);
1709         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1710         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1711                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1712         ret = t4_mgmt_tx(adap, skb);
1713         return net_xmit_eval(ret);
1714 }
1715 EXPORT_SYMBOL(cxgb4_remove_server);
1716
1717 /**
1718  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1719  *      @mtus: the HW MTU table
1720  *      @mtu: the target MTU
1721  *      @idx: index of selected entry in the MTU table
1722  *
1723  *      Returns the index and the value in the HW MTU table that is closest to
1724  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1725  *      table, in which case that smallest available value is selected.
1726  */
1727 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1728                             unsigned int *idx)
1729 {
1730         unsigned int i = 0;
1731
1732         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1733                 ++i;
1734         if (idx)
1735                 *idx = i;
1736         return mtus[i];
1737 }
1738 EXPORT_SYMBOL(cxgb4_best_mtu);
1739
1740 /**
1741  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1742  *     @mtus: the HW MTU table
1743  *     @header_size: Header Size
1744  *     @data_size_max: maximum Data Segment Size
1745  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1746  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1747  *
1748  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1749  *     MTU Table based solely on a Maximum MTU parameter, we break that
1750  *     parameter up into a Header Size and Maximum Data Segment Size, and
1751  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1752  *     the Hardware MTU Table which will result in a Data Segment Size with
1753  *     the requested alignment _and_ that MTU isn't "too far" from the
1754  *     closest MTU, then we'll return that rather than the closest MTU.
1755  */
1756 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1757                                     unsigned short header_size,
1758                                     unsigned short data_size_max,
1759                                     unsigned short data_size_align,
1760                                     unsigned int *mtu_idxp)
1761 {
1762         unsigned short max_mtu = header_size + data_size_max;
1763         unsigned short data_size_align_mask = data_size_align - 1;
1764         int mtu_idx, aligned_mtu_idx;
1765
1766         /* Scan the MTU Table till we find an MTU which is larger than our
1767          * Maximum MTU or we reach the end of the table.  Along the way,
1768          * record the last MTU found, if any, which will result in a Data
1769          * Segment Length matching the requested alignment.
1770          */
1771         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1772                 unsigned short data_size = mtus[mtu_idx] - header_size;
1773
1774                 /* If this MTU minus the Header Size would result in a
1775                  * Data Segment Size of the desired alignment, remember it.
1776                  */
1777                 if ((data_size & data_size_align_mask) == 0)
1778                         aligned_mtu_idx = mtu_idx;
1779
1780                 /* If we're not at the end of the Hardware MTU Table and the
1781                  * next element is larger than our Maximum MTU, drop out of
1782                  * the loop.
1783                  */
1784                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1785                         break;
1786         }
1787
1788         /* If we fell out of the loop because we ran to the end of the table,
1789          * then we just have to use the last [largest] entry.
1790          */
1791         if (mtu_idx == NMTUS)
1792                 mtu_idx--;
1793
1794         /* If we found an MTU which resulted in the requested Data Segment
1795          * Length alignment and that's "not far" from the largest MTU which is
1796          * less than or equal to the maximum MTU, then use that.
1797          */
1798         if (aligned_mtu_idx >= 0 &&
1799             mtu_idx - aligned_mtu_idx <= 1)
1800                 mtu_idx = aligned_mtu_idx;
1801
1802         /* If the caller has passed in an MTU Index pointer, pass the
1803          * MTU Index back.  Return the MTU value.
1804          */
1805         if (mtu_idxp)
1806                 *mtu_idxp = mtu_idx;
1807         return mtus[mtu_idx];
1808 }
1809 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1810
1811 /**
1812  *      cxgb4_port_chan - get the HW channel of a port
1813  *      @dev: the net device for the port
1814  *
1815  *      Return the HW Tx channel of the given port.
1816  */
1817 unsigned int cxgb4_port_chan(const struct net_device *dev)
1818 {
1819         return netdev2pinfo(dev)->tx_chan;
1820 }
1821 EXPORT_SYMBOL(cxgb4_port_chan);
1822
1823 /**
1824  *      cxgb4_port_e2cchan - get the HW c-channel of a port
1825  *      @dev: the net device for the port
1826  *
1827  *      Return the HW RX c-channel of the given port.
1828  */
1829 unsigned int cxgb4_port_e2cchan(const struct net_device *dev)
1830 {
1831         return netdev2pinfo(dev)->rx_cchan;
1832 }
1833 EXPORT_SYMBOL(cxgb4_port_e2cchan);
1834
1835 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1836 {
1837         struct adapter *adap = netdev2adap(dev);
1838         u32 v1, v2, lp_count, hp_count;
1839
1840         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1841         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1842         if (is_t4(adap->params.chip)) {
1843                 lp_count = LP_COUNT_G(v1);
1844                 hp_count = HP_COUNT_G(v1);
1845         } else {
1846                 lp_count = LP_COUNT_T5_G(v1);
1847                 hp_count = HP_COUNT_T5_G(v2);
1848         }
1849         return lpfifo ? lp_count : hp_count;
1850 }
1851 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1852
1853 /**
1854  *      cxgb4_port_viid - get the VI id of a port
1855  *      @dev: the net device for the port
1856  *
1857  *      Return the VI id of the given port.
1858  */
1859 unsigned int cxgb4_port_viid(const struct net_device *dev)
1860 {
1861         return netdev2pinfo(dev)->viid;
1862 }
1863 EXPORT_SYMBOL(cxgb4_port_viid);
1864
1865 /**
1866  *      cxgb4_port_idx - get the index of a port
1867  *      @dev: the net device for the port
1868  *
1869  *      Return the index of the given port.
1870  */
1871 unsigned int cxgb4_port_idx(const struct net_device *dev)
1872 {
1873         return netdev2pinfo(dev)->port_id;
1874 }
1875 EXPORT_SYMBOL(cxgb4_port_idx);
1876
1877 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1878                          struct tp_tcp_stats *v6)
1879 {
1880         struct adapter *adap = pci_get_drvdata(pdev);
1881
1882         spin_lock(&adap->stats_lock);
1883         t4_tp_get_tcp_stats(adap, v4, v6, false);
1884         spin_unlock(&adap->stats_lock);
1885 }
1886 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1887
1888 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1889                       const unsigned int *pgsz_order)
1890 {
1891         struct adapter *adap = netdev2adap(dev);
1892
1893         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1894         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1895                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1896                      HPZ3_V(pgsz_order[3]));
1897 }
1898 EXPORT_SYMBOL(cxgb4_iscsi_init);
1899
1900 int cxgb4_flush_eq_cache(struct net_device *dev)
1901 {
1902         struct adapter *adap = netdev2adap(dev);
1903
1904         return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1905 }
1906 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1907
1908 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1909 {
1910         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1911         __be64 indices;
1912         int ret;
1913
1914         spin_lock(&adap->win0_lock);
1915         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1916                            sizeof(indices), (__be32 *)&indices,
1917                            T4_MEMORY_READ);
1918         spin_unlock(&adap->win0_lock);
1919         if (!ret) {
1920                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1921                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1922         }
1923         return ret;
1924 }
1925
1926 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1927                         u16 size)
1928 {
1929         struct adapter *adap = netdev2adap(dev);
1930         u16 hw_pidx, hw_cidx;
1931         int ret;
1932
1933         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1934         if (ret)
1935                 goto out;
1936
1937         if (pidx != hw_pidx) {
1938                 u16 delta;
1939                 u32 val;
1940
1941                 if (pidx >= hw_pidx)
1942                         delta = pidx - hw_pidx;
1943                 else
1944                         delta = size - hw_pidx + pidx;
1945
1946                 if (is_t4(adap->params.chip))
1947                         val = PIDX_V(delta);
1948                 else
1949                         val = PIDX_T5_V(delta);
1950                 wmb();
1951                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1952                              QID_V(qid) | val);
1953         }
1954 out:
1955         return ret;
1956 }
1957 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1958
1959 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1960 {
1961         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1962         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1963         u32 offset, memtype, memaddr;
1964         struct adapter *adap;
1965         u32 hma_size = 0;
1966         int ret;
1967
1968         adap = netdev2adap(dev);
1969
1970         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1971
1972         /* Figure out where the offset lands in the Memory Type/Address scheme.
1973          * This code assumes that the memory is laid out starting at offset 0
1974          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1975          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1976          * MC0, and some have both MC0 and MC1.
1977          */
1978         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1979         edc0_size = EDRAM0_SIZE_G(size) << 20;
1980         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1981         edc1_size = EDRAM1_SIZE_G(size) << 20;
1982         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1983         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1984
1985         if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1986                 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1987                 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1988         }
1989         edc0_end = edc0_size;
1990         edc1_end = edc0_end + edc1_size;
1991         mc0_end = edc1_end + mc0_size;
1992
1993         if (offset < edc0_end) {
1994                 memtype = MEM_EDC0;
1995                 memaddr = offset;
1996         } else if (offset < edc1_end) {
1997                 memtype = MEM_EDC1;
1998                 memaddr = offset - edc0_end;
1999         } else {
2000                 if (hma_size && (offset < (edc1_end + hma_size))) {
2001                         memtype = MEM_HMA;
2002                         memaddr = offset - edc1_end;
2003                 } else if (offset < mc0_end) {
2004                         memtype = MEM_MC0;
2005                         memaddr = offset - edc1_end;
2006                 } else if (is_t5(adap->params.chip)) {
2007                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2008                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2009                         mc1_end = mc0_end + mc1_size;
2010                         if (offset < mc1_end) {
2011                                 memtype = MEM_MC1;
2012                                 memaddr = offset - mc0_end;
2013                         } else {
2014                                 /* offset beyond the end of any memory */
2015                                 goto err;
2016                         }
2017                 } else {
2018                         /* T4/T6 only has a single memory channel */
2019                         goto err;
2020                 }
2021         }
2022
2023         spin_lock(&adap->win0_lock);
2024         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2025         spin_unlock(&adap->win0_lock);
2026         return ret;
2027
2028 err:
2029         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2030                 stag, offset);
2031         return -EINVAL;
2032 }
2033 EXPORT_SYMBOL(cxgb4_read_tpte);
2034
2035 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2036 {
2037         u32 hi, lo;
2038         struct adapter *adap;
2039
2040         adap = netdev2adap(dev);
2041         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2042         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2043
2044         return ((u64)hi << 32) | (u64)lo;
2045 }
2046 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2047
2048 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2049                          unsigned int qid,
2050                          enum cxgb4_bar2_qtype qtype,
2051                          int user,
2052                          u64 *pbar2_qoffset,
2053                          unsigned int *pbar2_qid)
2054 {
2055         return t4_bar2_sge_qregs(netdev2adap(dev),
2056                                  qid,
2057                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
2058                                   ? T4_BAR2_QTYPE_EGRESS
2059                                   : T4_BAR2_QTYPE_INGRESS),
2060                                  user,
2061                                  pbar2_qoffset,
2062                                  pbar2_qid);
2063 }
2064 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2065
2066 static struct pci_driver cxgb4_driver;
2067
2068 static void check_neigh_update(struct neighbour *neigh)
2069 {
2070         const struct device *parent;
2071         const struct net_device *netdev = neigh->dev;
2072
2073         if (is_vlan_dev(netdev))
2074                 netdev = vlan_dev_real_dev(netdev);
2075         parent = netdev->dev.parent;
2076         if (parent && parent->driver == &cxgb4_driver.driver)
2077                 t4_l2t_update(dev_get_drvdata(parent), neigh);
2078 }
2079
2080 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2081                        void *data)
2082 {
2083         switch (event) {
2084         case NETEVENT_NEIGH_UPDATE:
2085                 check_neigh_update(data);
2086                 break;
2087         case NETEVENT_REDIRECT:
2088         default:
2089                 break;
2090         }
2091         return 0;
2092 }
2093
2094 static bool netevent_registered;
2095 static struct notifier_block cxgb4_netevent_nb = {
2096         .notifier_call = netevent_cb
2097 };
2098
2099 static void drain_db_fifo(struct adapter *adap, int usecs)
2100 {
2101         u32 v1, v2, lp_count, hp_count;
2102
2103         do {
2104                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2105                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2106                 if (is_t4(adap->params.chip)) {
2107                         lp_count = LP_COUNT_G(v1);
2108                         hp_count = HP_COUNT_G(v1);
2109                 } else {
2110                         lp_count = LP_COUNT_T5_G(v1);
2111                         hp_count = HP_COUNT_T5_G(v2);
2112                 }
2113
2114                 if (lp_count == 0 && hp_count == 0)
2115                         break;
2116                 set_current_state(TASK_UNINTERRUPTIBLE);
2117                 schedule_timeout(usecs_to_jiffies(usecs));
2118         } while (1);
2119 }
2120
2121 static void disable_txq_db(struct sge_txq *q)
2122 {
2123         unsigned long flags;
2124
2125         spin_lock_irqsave(&q->db_lock, flags);
2126         q->db_disabled = 1;
2127         spin_unlock_irqrestore(&q->db_lock, flags);
2128 }
2129
2130 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2131 {
2132         spin_lock_irq(&q->db_lock);
2133         if (q->db_pidx_inc) {
2134                 /* Make sure that all writes to the TX descriptors
2135                  * are committed before we tell HW about them.
2136                  */
2137                 wmb();
2138                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2139                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2140                 q->db_pidx_inc = 0;
2141         }
2142         q->db_disabled = 0;
2143         spin_unlock_irq(&q->db_lock);
2144 }
2145
2146 static void disable_dbs(struct adapter *adap)
2147 {
2148         int i;
2149
2150         for_each_ethrxq(&adap->sge, i)
2151                 disable_txq_db(&adap->sge.ethtxq[i].q);
2152         if (is_offload(adap)) {
2153                 struct sge_uld_txq_info *txq_info =
2154                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2155
2156                 if (txq_info) {
2157                         for_each_ofldtxq(&adap->sge, i) {
2158                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2159
2160                                 disable_txq_db(&txq->q);
2161                         }
2162                 }
2163         }
2164         for_each_port(adap, i)
2165                 disable_txq_db(&adap->sge.ctrlq[i].q);
2166 }
2167
2168 static void enable_dbs(struct adapter *adap)
2169 {
2170         int i;
2171
2172         for_each_ethrxq(&adap->sge, i)
2173                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2174         if (is_offload(adap)) {
2175                 struct sge_uld_txq_info *txq_info =
2176                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2177
2178                 if (txq_info) {
2179                         for_each_ofldtxq(&adap->sge, i) {
2180                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2181
2182                                 enable_txq_db(adap, &txq->q);
2183                         }
2184                 }
2185         }
2186         for_each_port(adap, i)
2187                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2188 }
2189
2190 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2191 {
2192         enum cxgb4_uld type = CXGB4_ULD_RDMA;
2193
2194         if (adap->uld && adap->uld[type].handle)
2195                 adap->uld[type].control(adap->uld[type].handle, cmd);
2196 }
2197
2198 static void process_db_full(struct work_struct *work)
2199 {
2200         struct adapter *adap;
2201
2202         adap = container_of(work, struct adapter, db_full_task);
2203
2204         drain_db_fifo(adap, dbfifo_drain_delay);
2205         enable_dbs(adap);
2206         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2207         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2208                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2209                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2210                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2211         else
2212                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2213                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2214 }
2215
2216 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2217 {
2218         u16 hw_pidx, hw_cidx;
2219         int ret;
2220
2221         spin_lock_irq(&q->db_lock);
2222         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2223         if (ret)
2224                 goto out;
2225         if (q->db_pidx != hw_pidx) {
2226                 u16 delta;
2227                 u32 val;
2228
2229                 if (q->db_pidx >= hw_pidx)
2230                         delta = q->db_pidx - hw_pidx;
2231                 else
2232                         delta = q->size - hw_pidx + q->db_pidx;
2233
2234                 if (is_t4(adap->params.chip))
2235                         val = PIDX_V(delta);
2236                 else
2237                         val = PIDX_T5_V(delta);
2238                 wmb();
2239                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2240                              QID_V(q->cntxt_id) | val);
2241         }
2242 out:
2243         q->db_disabled = 0;
2244         q->db_pidx_inc = 0;
2245         spin_unlock_irq(&q->db_lock);
2246         if (ret)
2247                 CH_WARN(adap, "DB drop recovery failed.\n");
2248 }
2249
2250 static void recover_all_queues(struct adapter *adap)
2251 {
2252         int i;
2253
2254         for_each_ethrxq(&adap->sge, i)
2255                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2256         if (is_offload(adap)) {
2257                 struct sge_uld_txq_info *txq_info =
2258                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2259                 if (txq_info) {
2260                         for_each_ofldtxq(&adap->sge, i) {
2261                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2262
2263                                 sync_txq_pidx(adap, &txq->q);
2264                         }
2265                 }
2266         }
2267         for_each_port(adap, i)
2268                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2269 }
2270
2271 static void process_db_drop(struct work_struct *work)
2272 {
2273         struct adapter *adap;
2274
2275         adap = container_of(work, struct adapter, db_drop_task);
2276
2277         if (is_t4(adap->params.chip)) {
2278                 drain_db_fifo(adap, dbfifo_drain_delay);
2279                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2280                 drain_db_fifo(adap, dbfifo_drain_delay);
2281                 recover_all_queues(adap);
2282                 drain_db_fifo(adap, dbfifo_drain_delay);
2283                 enable_dbs(adap);
2284                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2285         } else if (is_t5(adap->params.chip)) {
2286                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2287                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2288                 u16 pidx_inc = dropped_db & 0x1fff;
2289                 u64 bar2_qoffset;
2290                 unsigned int bar2_qid;
2291                 int ret;
2292
2293                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2294                                         0, &bar2_qoffset, &bar2_qid);
2295                 if (ret)
2296                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2297                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2298                 else
2299                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2300                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2301
2302                 /* Re-enable BAR2 WC */
2303                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2304         }
2305
2306         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2307                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2308 }
2309
2310 void t4_db_full(struct adapter *adap)
2311 {
2312         if (is_t4(adap->params.chip)) {
2313                 disable_dbs(adap);
2314                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2315                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2316                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2317                 queue_work(adap->workq, &adap->db_full_task);
2318         }
2319 }
2320
2321 void t4_db_dropped(struct adapter *adap)
2322 {
2323         if (is_t4(adap->params.chip)) {
2324                 disable_dbs(adap);
2325                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2326         }
2327         queue_work(adap->workq, &adap->db_drop_task);
2328 }
2329
2330 void t4_register_netevent_notifier(void)
2331 {
2332         if (!netevent_registered) {
2333                 register_netevent_notifier(&cxgb4_netevent_nb);
2334                 netevent_registered = true;
2335         }
2336 }
2337
2338 static void detach_ulds(struct adapter *adap)
2339 {
2340         unsigned int i;
2341
2342         mutex_lock(&uld_mutex);
2343         list_del(&adap->list_node);
2344
2345         for (i = 0; i < CXGB4_ULD_MAX; i++)
2346                 if (adap->uld && adap->uld[i].handle)
2347                         adap->uld[i].state_change(adap->uld[i].handle,
2348                                              CXGB4_STATE_DETACH);
2349
2350         if (netevent_registered && list_empty(&adapter_list)) {
2351                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2352                 netevent_registered = false;
2353         }
2354         mutex_unlock(&uld_mutex);
2355 }
2356
2357 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2358 {
2359         unsigned int i;
2360
2361         mutex_lock(&uld_mutex);
2362         for (i = 0; i < CXGB4_ULD_MAX; i++)
2363                 if (adap->uld && adap->uld[i].handle)
2364                         adap->uld[i].state_change(adap->uld[i].handle,
2365                                                   new_state);
2366         mutex_unlock(&uld_mutex);
2367 }
2368
2369 #if IS_ENABLED(CONFIG_IPV6)
2370 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2371                                    unsigned long event, void *data)
2372 {
2373         struct inet6_ifaddr *ifa = data;
2374         struct net_device *event_dev = ifa->idev->dev;
2375         const struct device *parent = NULL;
2376 #if IS_ENABLED(CONFIG_BONDING)
2377         struct adapter *adap;
2378 #endif
2379         if (is_vlan_dev(event_dev))
2380                 event_dev = vlan_dev_real_dev(event_dev);
2381 #if IS_ENABLED(CONFIG_BONDING)
2382         if (event_dev->flags & IFF_MASTER) {
2383                 list_for_each_entry(adap, &adapter_list, list_node) {
2384                         switch (event) {
2385                         case NETDEV_UP:
2386                                 cxgb4_clip_get(adap->port[0],
2387                                                (const u32 *)ifa, 1);
2388                                 break;
2389                         case NETDEV_DOWN:
2390                                 cxgb4_clip_release(adap->port[0],
2391                                                    (const u32 *)ifa, 1);
2392                                 break;
2393                         default:
2394                                 break;
2395                         }
2396                 }
2397                 return NOTIFY_OK;
2398         }
2399 #endif
2400
2401         if (event_dev)
2402                 parent = event_dev->dev.parent;
2403
2404         if (parent && parent->driver == &cxgb4_driver.driver) {
2405                 switch (event) {
2406                 case NETDEV_UP:
2407                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2408                         break;
2409                 case NETDEV_DOWN:
2410                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2411                         break;
2412                 default:
2413                         break;
2414                 }
2415         }
2416         return NOTIFY_OK;
2417 }
2418
2419 static bool inet6addr_registered;
2420 static struct notifier_block cxgb4_inet6addr_notifier = {
2421         .notifier_call = cxgb4_inet6addr_handler
2422 };
2423
2424 static void update_clip(const struct adapter *adap)
2425 {
2426         int i;
2427         struct net_device *dev;
2428         int ret;
2429
2430         rcu_read_lock();
2431
2432         for (i = 0; i < MAX_NPORTS; i++) {
2433                 dev = adap->port[i];
2434                 ret = 0;
2435
2436                 if (dev)
2437                         ret = cxgb4_update_root_dev_clip(dev);
2438
2439                 if (ret < 0)
2440                         break;
2441         }
2442         rcu_read_unlock();
2443 }
2444 #endif /* IS_ENABLED(CONFIG_IPV6) */
2445
2446 /**
2447  *      cxgb_up - enable the adapter
2448  *      @adap: adapter being enabled
2449  *
2450  *      Called when the first port is enabled, this function performs the
2451  *      actions necessary to make an adapter operational, such as completing
2452  *      the initialization of HW modules, and enabling interrupts.
2453  *
2454  *      Must be called with the rtnl lock held.
2455  */
2456 static int cxgb_up(struct adapter *adap)
2457 {
2458         struct sge *s = &adap->sge;
2459         int err;
2460
2461         mutex_lock(&uld_mutex);
2462         err = setup_sge_queues(adap);
2463         if (err)
2464                 goto rel_lock;
2465         err = setup_rss(adap);
2466         if (err)
2467                 goto freeq;
2468
2469         if (adap->flags & CXGB4_USING_MSIX) {
2470                 if (s->nd_msix_idx < 0) {
2471                         err = -ENOMEM;
2472                         goto irq_err;
2473                 }
2474
2475                 err = request_irq(adap->msix_info[s->nd_msix_idx].vec,
2476                                   t4_nondata_intr, 0,
2477                                   adap->msix_info[s->nd_msix_idx].desc, adap);
2478                 if (err)
2479                         goto irq_err;
2480
2481                 err = request_msix_queue_irqs(adap);
2482                 if (err)
2483                         goto irq_err_free_nd_msix;
2484         } else {
2485                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2486                                   (adap->flags & CXGB4_USING_MSI) ? 0
2487                                                                   : IRQF_SHARED,
2488                                   adap->port[0]->name, adap);
2489                 if (err)
2490                         goto irq_err;
2491         }
2492
2493         enable_rx(adap);
2494         t4_sge_start(adap);
2495         t4_intr_enable(adap);
2496         adap->flags |= CXGB4_FULL_INIT_DONE;
2497         mutex_unlock(&uld_mutex);
2498
2499         notify_ulds(adap, CXGB4_STATE_UP);
2500 #if IS_ENABLED(CONFIG_IPV6)
2501         update_clip(adap);
2502 #endif
2503         return err;
2504
2505 irq_err_free_nd_msix:
2506         free_irq(adap->msix_info[s->nd_msix_idx].vec, adap);
2507 irq_err:
2508         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2509 freeq:
2510         t4_free_sge_resources(adap);
2511 rel_lock:
2512         mutex_unlock(&uld_mutex);
2513         return err;
2514 }
2515
2516 static void cxgb_down(struct adapter *adapter)
2517 {
2518         cancel_work_sync(&adapter->tid_release_task);
2519         cancel_work_sync(&adapter->db_full_task);
2520         cancel_work_sync(&adapter->db_drop_task);
2521         adapter->tid_release_task_busy = false;
2522         adapter->tid_release_head = NULL;
2523
2524         t4_sge_stop(adapter);
2525         t4_free_sge_resources(adapter);
2526
2527         adapter->flags &= ~CXGB4_FULL_INIT_DONE;
2528 }
2529
2530 /*
2531  * net_device operations
2532  */
2533 int cxgb_open(struct net_device *dev)
2534 {
2535         struct port_info *pi = netdev_priv(dev);
2536         struct adapter *adapter = pi->adapter;
2537         int err;
2538
2539         netif_carrier_off(dev);
2540
2541         if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
2542                 err = cxgb_up(adapter);
2543                 if (err < 0)
2544                         return err;
2545         }
2546
2547         /* It's possible that the basic port information could have
2548          * changed since we first read it.
2549          */
2550         err = t4_update_port_info(pi);
2551         if (err < 0)
2552                 return err;
2553
2554         err = link_start(dev);
2555         if (!err)
2556                 netif_tx_start_all_queues(dev);
2557         return err;
2558 }
2559
2560 int cxgb_close(struct net_device *dev)
2561 {
2562         struct port_info *pi = netdev_priv(dev);
2563         struct adapter *adapter = pi->adapter;
2564         int ret;
2565
2566         netif_tx_stop_all_queues(dev);
2567         netif_carrier_off(dev);
2568         ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2569                                   false, false, false);
2570 #ifdef CONFIG_CHELSIO_T4_DCB
2571         cxgb4_dcb_reset(dev);
2572         dcb_tx_queue_prio_enable(dev, false);
2573 #endif
2574         return ret;
2575 }
2576
2577 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2578                 __be32 sip, __be16 sport, __be16 vlan,
2579                 unsigned int queue, unsigned char port, unsigned char mask)
2580 {
2581         int ret;
2582         struct filter_entry *f;
2583         struct adapter *adap;
2584         int i;
2585         u8 *val;
2586
2587         adap = netdev2adap(dev);
2588
2589         /* Adjust stid to correct filter index */
2590         stid -= adap->tids.sftid_base;
2591         stid += adap->tids.nftids;
2592
2593         /* Check to make sure the filter requested is writable ...
2594          */
2595         f = &adap->tids.ftid_tab[stid];
2596         ret = writable_filter(f);
2597         if (ret)
2598                 return ret;
2599
2600         /* Clear out any old resources being used by the filter before
2601          * we start constructing the new filter.
2602          */
2603         if (f->valid)
2604                 clear_filter(adap, f);
2605
2606         /* Clear out filter specifications */
2607         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2608         f->fs.val.lport = cpu_to_be16(sport);
2609         f->fs.mask.lport  = ~0;
2610         val = (u8 *)&sip;
2611         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2612                 for (i = 0; i < 4; i++) {
2613                         f->fs.val.lip[i] = val[i];
2614                         f->fs.mask.lip[i] = ~0;
2615                 }
2616                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2617                         f->fs.val.iport = port;
2618                         f->fs.mask.iport = mask;
2619                 }
2620         }
2621
2622         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2623                 f->fs.val.proto = IPPROTO_TCP;
2624                 f->fs.mask.proto = ~0;
2625         }
2626
2627         f->fs.dirsteer = 1;
2628         f->fs.iq = queue;
2629         /* Mark filter as locked */
2630         f->locked = 1;
2631         f->fs.rpttid = 1;
2632
2633         /* Save the actual tid. We need this to get the corresponding
2634          * filter entry structure in filter_rpl.
2635          */
2636         f->tid = stid + adap->tids.ftid_base;
2637         ret = set_filter_wr(adap, stid);
2638         if (ret) {
2639                 clear_filter(adap, f);
2640                 return ret;
2641         }
2642
2643         return 0;
2644 }
2645 EXPORT_SYMBOL(cxgb4_create_server_filter);
2646
2647 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2648                 unsigned int queue, bool ipv6)
2649 {
2650         struct filter_entry *f;
2651         struct adapter *adap;
2652
2653         adap = netdev2adap(dev);
2654
2655         /* Adjust stid to correct filter index */
2656         stid -= adap->tids.sftid_base;
2657         stid += adap->tids.nftids;
2658
2659         f = &adap->tids.ftid_tab[stid];
2660         /* Unlock the filter */
2661         f->locked = 0;
2662
2663         return delete_filter(adap, stid);
2664 }
2665 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2666
2667 static void cxgb_get_stats(struct net_device *dev,
2668                            struct rtnl_link_stats64 *ns)
2669 {
2670         struct port_stats stats;
2671         struct port_info *p = netdev_priv(dev);
2672         struct adapter *adapter = p->adapter;
2673
2674         /* Block retrieving statistics during EEH error
2675          * recovery. Otherwise, the recovery might fail
2676          * and the PCI device will be removed permanently
2677          */
2678         spin_lock(&adapter->stats_lock);
2679         if (!netif_device_present(dev)) {
2680                 spin_unlock(&adapter->stats_lock);
2681                 return;
2682         }
2683         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2684                                  &p->stats_base);
2685         spin_unlock(&adapter->stats_lock);
2686
2687         ns->tx_bytes   = stats.tx_octets;
2688         ns->tx_packets = stats.tx_frames;
2689         ns->rx_bytes   = stats.rx_octets;
2690         ns->rx_packets = stats.rx_frames;
2691         ns->multicast  = stats.rx_mcast_frames;
2692
2693         /* detailed rx_errors */
2694         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2695                                stats.rx_runt;
2696         ns->rx_over_errors   = 0;
2697         ns->rx_crc_errors    = stats.rx_fcs_err;
2698         ns->rx_frame_errors  = stats.rx_symbol_err;
2699         ns->rx_dropped       = stats.rx_ovflow0 + stats.rx_ovflow1 +
2700                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2701                                stats.rx_trunc0 + stats.rx_trunc1 +
2702                                stats.rx_trunc2 + stats.rx_trunc3;
2703         ns->rx_missed_errors = 0;
2704
2705         /* detailed tx_errors */
2706         ns->tx_aborted_errors   = 0;
2707         ns->tx_carrier_errors   = 0;
2708         ns->tx_fifo_errors      = 0;
2709         ns->tx_heartbeat_errors = 0;
2710         ns->tx_window_errors    = 0;
2711
2712         ns->tx_errors = stats.tx_error_frames;
2713         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2714                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2715 }
2716
2717 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2718 {
2719         unsigned int mbox;
2720         int ret = 0, prtad, devad;
2721         struct port_info *pi = netdev_priv(dev);
2722         struct adapter *adapter = pi->adapter;
2723         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2724
2725         switch (cmd) {
2726         case SIOCGMIIPHY:
2727                 if (pi->mdio_addr < 0)
2728                         return -EOPNOTSUPP;
2729                 data->phy_id = pi->mdio_addr;
2730                 break;
2731         case SIOCGMIIREG:
2732         case SIOCSMIIREG:
2733                 if (mdio_phy_id_is_c45(data->phy_id)) {
2734                         prtad = mdio_phy_id_prtad(data->phy_id);
2735                         devad = mdio_phy_id_devad(data->phy_id);
2736                 } else if (data->phy_id < 32) {
2737                         prtad = data->phy_id;
2738                         devad = 0;
2739                         data->reg_num &= 0x1f;
2740                 } else
2741                         return -EINVAL;
2742
2743                 mbox = pi->adapter->pf;
2744                 if (cmd == SIOCGMIIREG)
2745                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2746                                          data->reg_num, &data->val_out);
2747                 else
2748                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2749                                          data->reg_num, data->val_in);
2750                 break;
2751         case SIOCGHWTSTAMP:
2752                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2753                                     sizeof(pi->tstamp_config)) ?
2754                         -EFAULT : 0;
2755         case SIOCSHWTSTAMP:
2756                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2757                                    sizeof(pi->tstamp_config)))
2758                         return -EFAULT;
2759
2760                 if (!is_t4(adapter->params.chip)) {
2761                         switch (pi->tstamp_config.tx_type) {
2762                         case HWTSTAMP_TX_OFF:
2763                         case HWTSTAMP_TX_ON:
2764                                 break;
2765                         default:
2766                                 return -ERANGE;
2767                         }
2768
2769                         switch (pi->tstamp_config.rx_filter) {
2770                         case HWTSTAMP_FILTER_NONE:
2771                                 pi->rxtstamp = false;
2772                                 break;
2773                         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2774                         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2775                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2776                                                          PTP_TS_L4);
2777                                 break;
2778                         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2779                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2780                                                          PTP_TS_L2_L4);
2781                                 break;
2782                         case HWTSTAMP_FILTER_ALL:
2783                         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2784                         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2785                         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2786                         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2787                                 pi->rxtstamp = true;
2788                                 break;
2789                         default:
2790                                 pi->tstamp_config.rx_filter =
2791                                         HWTSTAMP_FILTER_NONE;
2792                                 return -ERANGE;
2793                         }
2794
2795                         if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2796                             (pi->tstamp_config.rx_filter ==
2797                                 HWTSTAMP_FILTER_NONE)) {
2798                                 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2799                                         pi->ptp_enable = false;
2800                         }
2801
2802                         if (pi->tstamp_config.rx_filter !=
2803                                 HWTSTAMP_FILTER_NONE) {
2804                                 if (cxgb4_ptp_redirect_rx_packet(adapter,
2805                                                                  pi) >= 0)
2806                                         pi->ptp_enable = true;
2807                         }
2808                 } else {
2809                         /* For T4 Adapters */
2810                         switch (pi->tstamp_config.rx_filter) {
2811                         case HWTSTAMP_FILTER_NONE:
2812                         pi->rxtstamp = false;
2813                         break;
2814                         case HWTSTAMP_FILTER_ALL:
2815                         pi->rxtstamp = true;
2816                         break;
2817                         default:
2818                         pi->tstamp_config.rx_filter =
2819                         HWTSTAMP_FILTER_NONE;
2820                         return -ERANGE;
2821                         }
2822                 }
2823                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2824                                     sizeof(pi->tstamp_config)) ?
2825                         -EFAULT : 0;
2826         default:
2827                 return -EOPNOTSUPP;
2828         }
2829         return ret;
2830 }
2831
2832 static void cxgb_set_rxmode(struct net_device *dev)
2833 {
2834         /* unfortunately we can't return errors to the stack */
2835         set_rxmode(dev, -1, false);
2836 }
2837
2838 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2839 {
2840         int ret;
2841         struct port_info *pi = netdev_priv(dev);
2842
2843         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2844                             -1, -1, -1, true);
2845         if (!ret)
2846                 dev->mtu = new_mtu;
2847         return ret;
2848 }
2849
2850 #ifdef CONFIG_PCI_IOV
2851 static int cxgb4_mgmt_open(struct net_device *dev)
2852 {
2853         /* Turn carrier off since we don't have to transmit anything on this
2854          * interface.
2855          */
2856         netif_carrier_off(dev);
2857         return 0;
2858 }
2859
2860 /* Fill MAC address that will be assigned by the FW */
2861 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2862 {
2863         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2864         unsigned int i, vf, nvfs;
2865         u16 a, b;
2866         int err;
2867         u8 *na;
2868
2869         adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2870                                                             PCI_CAP_ID_VPD);
2871         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2872         if (err)
2873                 return;
2874
2875         na = adap->params.vpd.na;
2876         for (i = 0; i < ETH_ALEN; i++)
2877                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2878                               hex2val(na[2 * i + 1]));
2879
2880         a = (hw_addr[0] << 8) | hw_addr[1];
2881         b = (hw_addr[1] << 8) | hw_addr[2];
2882         a ^= b;
2883         a |= 0x0200;    /* locally assigned Ethernet MAC address */
2884         a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2885         macaddr[0] = a >> 8;
2886         macaddr[1] = a & 0xff;
2887
2888         for (i = 2; i < 5; i++)
2889                 macaddr[i] = hw_addr[i + 1];
2890
2891         for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2892                 vf < nvfs; vf++) {
2893                 macaddr[5] = adap->pf * nvfs + vf;
2894                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2895         }
2896 }
2897
2898 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2899 {
2900         struct port_info *pi = netdev_priv(dev);
2901         struct adapter *adap = pi->adapter;
2902         int ret;
2903
2904         /* verify MAC addr is valid */
2905         if (!is_valid_ether_addr(mac)) {
2906                 dev_err(pi->adapter->pdev_dev,
2907                         "Invalid Ethernet address %pM for VF %d\n",
2908                         mac, vf);
2909                 return -EINVAL;
2910         }
2911
2912         dev_info(pi->adapter->pdev_dev,
2913                  "Setting MAC %pM on VF %d\n", mac, vf);
2914         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2915         if (!ret)
2916                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2917         return ret;
2918 }
2919
2920 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2921                                     int vf, struct ifla_vf_info *ivi)
2922 {
2923         struct port_info *pi = netdev_priv(dev);
2924         struct adapter *adap = pi->adapter;
2925         struct vf_info *vfinfo;
2926
2927         if (vf >= adap->num_vfs)
2928                 return -EINVAL;
2929         vfinfo = &adap->vfinfo[vf];
2930
2931         ivi->vf = vf;
2932         ivi->max_tx_rate = vfinfo->tx_rate;
2933         ivi->min_tx_rate = 0;
2934         ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2935         ivi->vlan = vfinfo->vlan;
2936         ivi->linkstate = vfinfo->link_state;
2937         return 0;
2938 }
2939
2940 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2941                                        struct netdev_phys_item_id *ppid)
2942 {
2943         struct port_info *pi = netdev_priv(dev);
2944         unsigned int phy_port_id;
2945
2946         phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2947         ppid->id_len = sizeof(phy_port_id);
2948         memcpy(ppid->id, &phy_port_id, ppid->id_len);
2949         return 0;
2950 }
2951
2952 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2953                                   int min_tx_rate, int max_tx_rate)
2954 {
2955         struct port_info *pi = netdev_priv(dev);
2956         struct adapter *adap = pi->adapter;
2957         unsigned int link_ok, speed, mtu;
2958         u32 fw_pfvf, fw_class;
2959         int class_id = vf;
2960         int ret;
2961         u16 pktsize;
2962
2963         if (vf >= adap->num_vfs)
2964                 return -EINVAL;
2965
2966         if (min_tx_rate) {
2967                 dev_err(adap->pdev_dev,
2968                         "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2969                         min_tx_rate, vf);
2970                 return -EINVAL;
2971         }
2972
2973         if (max_tx_rate == 0) {
2974                 /* unbind VF to to any Traffic Class */
2975                 fw_pfvf =
2976                     (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2977                      FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2978                 fw_class = 0xffffffff;
2979                 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2980                                     &fw_pfvf, &fw_class);
2981                 if (ret) {
2982                         dev_err(adap->pdev_dev,
2983                                 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2984                                 ret, adap->pf, vf);
2985                         return -EINVAL;
2986                 }
2987                 dev_info(adap->pdev_dev,
2988                          "PF %d VF %d is unbound from TX Rate Limiting\n",
2989                          adap->pf, vf);
2990                 adap->vfinfo[vf].tx_rate = 0;
2991                 return 0;
2992         }
2993
2994         ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2995         if (ret != FW_SUCCESS) {
2996                 dev_err(adap->pdev_dev,
2997                         "Failed to get link information for VF %d\n", vf);
2998                 return -EINVAL;
2999         }
3000
3001         if (!link_ok) {
3002                 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
3003                 return -EINVAL;
3004         }
3005
3006         if (max_tx_rate > speed) {
3007                 dev_err(adap->pdev_dev,
3008                         "Max tx rate %d for VF %d can't be > link-speed %u",
3009                         max_tx_rate, vf, speed);
3010                 return -EINVAL;
3011         }
3012
3013         pktsize = mtu;
3014         /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
3015         pktsize = pktsize - sizeof(struct ethhdr) - 4;
3016         /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
3017         pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
3018         /* configure Traffic Class for rate-limiting */
3019         ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
3020                               SCHED_CLASS_LEVEL_CL_RL,
3021                               SCHED_CLASS_MODE_CLASS,
3022                               SCHED_CLASS_RATEUNIT_BITS,
3023                               SCHED_CLASS_RATEMODE_ABS,
3024                               pi->tx_chan, class_id, 0,
3025                               max_tx_rate * 1000, 0, pktsize, 0);
3026         if (ret) {
3027                 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
3028                         ret);
3029                 return -EINVAL;
3030         }
3031         dev_info(adap->pdev_dev,
3032                  "Class %d with MSS %u configured with rate %u\n",
3033                  class_id, pktsize, max_tx_rate);
3034
3035         /* bind VF to configured Traffic Class */
3036         fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
3037                    FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
3038         fw_class = class_id;
3039         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
3040                             &fw_class);
3041         if (ret) {
3042                 dev_err(adap->pdev_dev,
3043                         "Err %d in binding PF %d VF %d to Traffic Class %d\n",
3044                         ret, adap->pf, vf, class_id);
3045                 return -EINVAL;
3046         }
3047         dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
3048                  adap->pf, vf, class_id);
3049         adap->vfinfo[vf].tx_rate = max_tx_rate;
3050         return 0;
3051 }
3052
3053 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
3054                                   u16 vlan, u8 qos, __be16 vlan_proto)
3055 {
3056         struct port_info *pi = netdev_priv(dev);
3057         struct adapter *adap = pi->adapter;
3058         int ret;
3059
3060         if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
3061                 return -EINVAL;
3062
3063         if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
3064                 return -EPROTONOSUPPORT;
3065
3066         ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
3067         if (!ret) {
3068                 adap->vfinfo[vf].vlan = vlan;
3069                 return 0;
3070         }
3071
3072         dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
3073                 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
3074         return ret;
3075 }
3076
3077 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
3078                                         int link)
3079 {
3080         struct port_info *pi = netdev_priv(dev);
3081         struct adapter *adap = pi->adapter;
3082         u32 param, val;
3083         int ret = 0;
3084
3085         if (vf >= adap->num_vfs)
3086                 return -EINVAL;
3087
3088         switch (link) {
3089         case IFLA_VF_LINK_STATE_AUTO:
3090                 val = FW_VF_LINK_STATE_AUTO;
3091                 break;
3092
3093         case IFLA_VF_LINK_STATE_ENABLE:
3094                 val = FW_VF_LINK_STATE_ENABLE;
3095                 break;
3096
3097         case IFLA_VF_LINK_STATE_DISABLE:
3098                 val = FW_VF_LINK_STATE_DISABLE;
3099                 break;
3100
3101         default:
3102                 return -EINVAL;
3103         }
3104
3105         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
3106                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
3107         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
3108                             &param, &val);
3109         if (ret) {
3110                 dev_err(adap->pdev_dev,
3111                         "Error %d in setting PF %d VF %d link state\n",
3112                         ret, adap->pf, vf);
3113                 return -EINVAL;
3114         }
3115
3116         adap->vfinfo[vf].link_state = link;
3117         return ret;
3118 }
3119 #endif /* CONFIG_PCI_IOV */
3120
3121 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3122 {
3123         int ret;
3124         struct sockaddr *addr = p;
3125         struct port_info *pi = netdev_priv(dev);
3126
3127         if (!is_valid_ether_addr(addr->sa_data))
3128                 return -EADDRNOTAVAIL;
3129
3130         ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
3131                                     addr->sa_data, true, &pi->smt_idx);
3132         if (ret < 0)
3133                 return ret;
3134
3135         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3136         return 0;
3137 }
3138
3139 #ifdef CONFIG_NET_POLL_CONTROLLER
3140 static void cxgb_netpoll(struct net_device *dev)
3141 {
3142         struct port_info *pi = netdev_priv(dev);
3143         struct adapter *adap = pi->adapter;
3144
3145         if (adap->flags & CXGB4_USING_MSIX) {
3146                 int i;
3147                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3148
3149                 for (i = pi->nqsets; i; i--, rx++)
3150                         t4_sge_intr_msix(0, &rx->rspq);
3151         } else
3152                 t4_intr_handler(adap)(0, adap);
3153 }
3154 #endif
3155
3156 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
3157 {
3158         struct port_info *pi = netdev_priv(dev);
3159         struct adapter *adap = pi->adapter;
3160         struct ch_sched_queue qe = { 0 };
3161         struct ch_sched_params p = { 0 };
3162         struct sched_class *e;
3163         u32 req_rate;
3164         int err = 0;
3165
3166         if (!can_sched(dev))
3167                 return -ENOTSUPP;
3168
3169         if (index < 0 || index > pi->nqsets - 1)
3170                 return -EINVAL;
3171
3172         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3173                 dev_err(adap->pdev_dev,
3174                         "Failed to rate limit on queue %d. Link Down?\n",
3175                         index);
3176                 return -EINVAL;
3177         }
3178
3179         qe.queue = index;
3180         e = cxgb4_sched_queue_lookup(dev, &qe);
3181         if (e && e->info.u.params.level != SCHED_CLASS_LEVEL_CL_RL) {
3182                 dev_err(adap->pdev_dev,
3183                         "Queue %u already bound to class %u of type: %u\n",
3184                         index, e->idx, e->info.u.params.level);
3185                 return -EBUSY;
3186         }
3187
3188         /* Convert from Mbps to Kbps */
3189         req_rate = rate * 1000;
3190
3191         /* Max rate is 100 Gbps */
3192         if (req_rate > SCHED_MAX_RATE_KBPS) {
3193                 dev_err(adap->pdev_dev,
3194                         "Invalid rate %u Mbps, Max rate is %u Mbps\n",
3195                         rate, SCHED_MAX_RATE_KBPS / 1000);
3196                 return -ERANGE;
3197         }
3198
3199         /* First unbind the queue from any existing class */
3200         memset(&qe, 0, sizeof(qe));
3201         qe.queue = index;
3202         qe.class = SCHED_CLS_NONE;
3203
3204         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3205         if (err) {
3206                 dev_err(adap->pdev_dev,
3207                         "Unbinding Queue %d on port %d fail. Err: %d\n",
3208                         index, pi->port_id, err);
3209                 return err;
3210         }
3211
3212         /* Queue already unbound */
3213         if (!req_rate)
3214                 return 0;
3215
3216         /* Fetch any available unused or matching scheduling class */
3217         p.type = SCHED_CLASS_TYPE_PACKET;
3218         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
3219         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
3220         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3221         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3222         p.u.params.channel  = pi->tx_chan;
3223         p.u.params.class    = SCHED_CLS_NONE;
3224         p.u.params.minrate  = 0;
3225         p.u.params.maxrate  = req_rate;
3226         p.u.params.weight   = 0;
3227         p.u.params.pktsize  = dev->mtu;
3228
3229         e = cxgb4_sched_class_alloc(dev, &p);
3230         if (!e)
3231                 return -ENOMEM;
3232
3233         /* Bind the queue to a scheduling class */
3234         memset(&qe, 0, sizeof(qe));
3235         qe.queue = index;
3236         qe.class = e->idx;
3237
3238         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3239         if (err)
3240                 dev_err(adap->pdev_dev,
3241                         "Queue rate limiting failed. Err: %d\n", err);
3242         return err;
3243 }
3244
3245 static int cxgb_setup_tc_flower(struct net_device *dev,
3246                                 struct flow_cls_offload *cls_flower)
3247 {
3248         switch (cls_flower->command) {
3249         case FLOW_CLS_REPLACE:
3250                 return cxgb4_tc_flower_replace(dev, cls_flower);
3251         case FLOW_CLS_DESTROY:
3252                 return cxgb4_tc_flower_destroy(dev, cls_flower);
3253         case FLOW_CLS_STATS:
3254                 return cxgb4_tc_flower_stats(dev, cls_flower);
3255         default:
3256                 return -EOPNOTSUPP;
3257         }
3258 }
3259
3260 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
3261                                  struct tc_cls_u32_offload *cls_u32)
3262 {
3263         switch (cls_u32->command) {
3264         case TC_CLSU32_NEW_KNODE:
3265         case TC_CLSU32_REPLACE_KNODE:
3266                 return cxgb4_config_knode(dev, cls_u32);
3267         case TC_CLSU32_DELETE_KNODE:
3268                 return cxgb4_delete_knode(dev, cls_u32);
3269         default:
3270                 return -EOPNOTSUPP;
3271         }
3272 }
3273
3274 static int cxgb_setup_tc_matchall(struct net_device *dev,
3275                                   struct tc_cls_matchall_offload *cls_matchall,
3276                                   bool ingress)
3277 {
3278         struct adapter *adap = netdev2adap(dev);
3279
3280         if (!adap->tc_matchall)
3281                 return -ENOMEM;
3282
3283         switch (cls_matchall->command) {
3284         case TC_CLSMATCHALL_REPLACE:
3285                 return cxgb4_tc_matchall_replace(dev, cls_matchall, ingress);
3286         case TC_CLSMATCHALL_DESTROY:
3287                 return cxgb4_tc_matchall_destroy(dev, cls_matchall, ingress);
3288         case TC_CLSMATCHALL_STATS:
3289                 if (ingress)
3290                         return cxgb4_tc_matchall_stats(dev, cls_matchall);
3291                 break;
3292         default:
3293                 break;
3294         }
3295
3296         return -EOPNOTSUPP;
3297 }
3298
3299 static int cxgb_setup_tc_block_ingress_cb(enum tc_setup_type type,
3300                                           void *type_data, void *cb_priv)
3301 {
3302         struct net_device *dev = cb_priv;
3303         struct port_info *pi = netdev2pinfo(dev);
3304         struct adapter *adap = netdev2adap(dev);
3305
3306         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3307                 dev_err(adap->pdev_dev,
3308                         "Failed to setup tc on port %d. Link Down?\n",
3309                         pi->port_id);
3310                 return -EINVAL;
3311         }
3312
3313         if (!tc_cls_can_offload_and_chain0(dev, type_data))
3314                 return -EOPNOTSUPP;
3315
3316         switch (type) {
3317         case TC_SETUP_CLSU32:
3318                 return cxgb_setup_tc_cls_u32(dev, type_data);
3319         case TC_SETUP_CLSFLOWER:
3320                 return cxgb_setup_tc_flower(dev, type_data);
3321         case TC_SETUP_CLSMATCHALL:
3322                 return cxgb_setup_tc_matchall(dev, type_data, true);
3323         default:
3324                 return -EOPNOTSUPP;
3325         }
3326 }
3327
3328 static int cxgb_setup_tc_block_egress_cb(enum tc_setup_type type,
3329                                          void *type_data, void *cb_priv)
3330 {
3331         struct net_device *dev = cb_priv;
3332         struct port_info *pi = netdev2pinfo(dev);
3333         struct adapter *adap = netdev2adap(dev);
3334
3335         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3336                 dev_err(adap->pdev_dev,
3337                         "Failed to setup tc on port %d. Link Down?\n",
3338                         pi->port_id);
3339                 return -EINVAL;
3340         }
3341
3342         if (!tc_cls_can_offload_and_chain0(dev, type_data))
3343                 return -EOPNOTSUPP;
3344
3345         switch (type) {
3346         case TC_SETUP_CLSMATCHALL:
3347                 return cxgb_setup_tc_matchall(dev, type_data, false);
3348         default:
3349                 break;
3350         }
3351
3352         return -EOPNOTSUPP;
3353 }
3354
3355 static int cxgb_setup_tc_mqprio(struct net_device *dev,
3356                                 struct tc_mqprio_qopt_offload *mqprio)
3357 {
3358         struct adapter *adap = netdev2adap(dev);
3359
3360         if (!is_ethofld(adap) || !adap->tc_mqprio)
3361                 return -ENOMEM;
3362
3363         return cxgb4_setup_tc_mqprio(dev, mqprio);
3364 }
3365
3366 static LIST_HEAD(cxgb_block_cb_list);
3367
3368 static int cxgb_setup_tc_block(struct net_device *dev,
3369                                struct flow_block_offload *f)
3370 {
3371         struct port_info *pi = netdev_priv(dev);
3372         flow_setup_cb_t *cb;
3373         bool ingress_only;
3374
3375         pi->tc_block_shared = f->block_shared;
3376         if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
3377                 cb = cxgb_setup_tc_block_egress_cb;
3378                 ingress_only = false;
3379         } else {
3380                 cb = cxgb_setup_tc_block_ingress_cb;
3381                 ingress_only = true;
3382         }
3383
3384         return flow_block_cb_setup_simple(f, &cxgb_block_cb_list,
3385                                           cb, pi, dev, ingress_only);
3386 }
3387
3388 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3389                          void *type_data)
3390 {
3391         switch (type) {
3392         case TC_SETUP_QDISC_MQPRIO:
3393                 return cxgb_setup_tc_mqprio(dev, type_data);
3394         case TC_SETUP_BLOCK:
3395                 return cxgb_setup_tc_block(dev, type_data);
3396         default:
3397                 return -EOPNOTSUPP;
3398         }
3399 }
3400
3401 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3402                                 struct udp_tunnel_info *ti)
3403 {
3404         struct port_info *pi = netdev_priv(netdev);
3405         struct adapter *adapter = pi->adapter;
3406         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3407         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3408         int ret = 0, i;
3409
3410         if (chip_ver < CHELSIO_T6)
3411                 return;
3412
3413         switch (ti->type) {
3414         case UDP_TUNNEL_TYPE_VXLAN:
3415                 if (!adapter->vxlan_port_cnt ||
3416                     adapter->vxlan_port != ti->port)
3417                         return; /* Invalid VxLAN destination port */
3418
3419                 adapter->vxlan_port_cnt--;
3420                 if (adapter->vxlan_port_cnt)
3421                         return;
3422
3423                 adapter->vxlan_port = 0;
3424                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3425                 break;
3426         case UDP_TUNNEL_TYPE_GENEVE:
3427                 if (!adapter->geneve_port_cnt ||
3428                     adapter->geneve_port != ti->port)
3429                         return; /* Invalid GENEVE destination port */
3430
3431                 adapter->geneve_port_cnt--;
3432                 if (adapter->geneve_port_cnt)
3433                         return;
3434
3435                 adapter->geneve_port = 0;
3436                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
3437                 break;
3438         default:
3439                 return;
3440         }
3441
3442         /* Matchall mac entries can be deleted only after all tunnel ports
3443          * are brought down or removed.
3444          */
3445         if (!adapter->rawf_cnt)
3446                 return;
3447         for_each_port(adapter, i) {
3448                 pi = adap2pinfo(adapter, i);
3449                 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3450                                            match_all_mac, match_all_mac,
3451                                            adapter->rawf_start +
3452                                             pi->port_id,
3453                                            1, pi->port_id, false);
3454                 if (ret < 0) {
3455                         netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3456                                     i);
3457                         return;
3458                 }
3459         }
3460 }
3461
3462 static void cxgb_add_udp_tunnel(struct net_device *netdev,
3463                                 struct udp_tunnel_info *ti)
3464 {
3465         struct port_info *pi = netdev_priv(netdev);
3466         struct adapter *adapter = pi->adapter;
3467         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3468         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3469         int i, ret;
3470
3471         if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
3472                 return;
3473
3474         switch (ti->type) {
3475         case UDP_TUNNEL_TYPE_VXLAN:
3476                 /* Callback for adding vxlan port can be called with the same
3477                  * port for both IPv4 and IPv6. We should not disable the
3478                  * offloading when the same port for both protocols is added
3479                  * and later one of them is removed.
3480                  */
3481                 if (adapter->vxlan_port_cnt &&
3482                     adapter->vxlan_port == ti->port) {
3483                         adapter->vxlan_port_cnt++;
3484                         return;
3485                 }
3486
3487                 /* We will support only one VxLAN port */
3488                 if (adapter->vxlan_port_cnt) {
3489                         netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3490                                     be16_to_cpu(adapter->vxlan_port),
3491                                     be16_to_cpu(ti->port));
3492                         return;
3493                 }
3494
3495                 adapter->vxlan_port = ti->port;
3496                 adapter->vxlan_port_cnt = 1;
3497
3498                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3499                              VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3500                 break;
3501         case UDP_TUNNEL_TYPE_GENEVE:
3502                 if (adapter->geneve_port_cnt &&
3503                     adapter->geneve_port == ti->port) {
3504                         adapter->geneve_port_cnt++;
3505                         return;
3506                 }
3507
3508                 /* We will support only one GENEVE port */
3509                 if (adapter->geneve_port_cnt) {
3510                         netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3511                                     be16_to_cpu(adapter->geneve_port),
3512                                     be16_to_cpu(ti->port));
3513                         return;
3514                 }
3515
3516                 adapter->geneve_port = ti->port;
3517                 adapter->geneve_port_cnt = 1;
3518
3519                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3520                              GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
3521                 break;
3522         default:
3523                 return;
3524         }
3525
3526         /* Create a 'match all' mac filter entry for inner mac,
3527          * if raw mac interface is supported. Once the linux kernel provides
3528          * driver entry points for adding/deleting the inner mac addresses,
3529          * we will remove this 'match all' entry and fallback to adding
3530          * exact match filters.
3531          */
3532         for_each_port(adapter, i) {
3533                 pi = adap2pinfo(adapter, i);
3534
3535                 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3536                                             match_all_mac,
3537                                             match_all_mac,
3538                                             adapter->rawf_start +
3539                                             pi->port_id,
3540                                             1, pi->port_id, false);
3541                 if (ret < 0) {
3542                         netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3543                                     be16_to_cpu(ti->port));
3544                         cxgb_del_udp_tunnel(netdev, ti);
3545                         return;
3546                 }
3547         }
3548 }
3549
3550 static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3551                                              struct net_device *dev,
3552                                              netdev_features_t features)
3553 {
3554         struct port_info *pi = netdev_priv(dev);
3555         struct adapter *adapter = pi->adapter;
3556
3557         if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3558                 return features;
3559
3560         /* Check if hw supports offload for this packet */
3561         if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3562                 return features;
3563
3564         /* Offload is not supported for this encapsulated packet */
3565         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3566 }
3567
3568 static netdev_features_t cxgb_fix_features(struct net_device *dev,
3569                                            netdev_features_t features)
3570 {
3571         /* Disable GRO, if RX_CSUM is disabled */
3572         if (!(features & NETIF_F_RXCSUM))
3573                 features &= ~NETIF_F_GRO;
3574
3575         return features;
3576 }
3577
3578 static const struct net_device_ops cxgb4_netdev_ops = {
3579         .ndo_open             = cxgb_open,
3580         .ndo_stop             = cxgb_close,
3581         .ndo_start_xmit       = t4_start_xmit,
3582         .ndo_select_queue     = cxgb_select_queue,
3583         .ndo_get_stats64      = cxgb_get_stats,
3584         .ndo_set_rx_mode      = cxgb_set_rxmode,
3585         .ndo_set_mac_address  = cxgb_set_mac_addr,
3586         .ndo_set_features     = cxgb_set_features,
3587         .ndo_validate_addr    = eth_validate_addr,
3588         .ndo_do_ioctl         = cxgb_ioctl,
3589         .ndo_change_mtu       = cxgb_change_mtu,
3590 #ifdef CONFIG_NET_POLL_CONTROLLER
3591         .ndo_poll_controller  = cxgb_netpoll,
3592 #endif
3593 #ifdef CONFIG_CHELSIO_T4_FCOE
3594         .ndo_fcoe_enable      = cxgb_fcoe_enable,
3595         .ndo_fcoe_disable     = cxgb_fcoe_disable,
3596 #endif /* CONFIG_CHELSIO_T4_FCOE */
3597         .ndo_set_tx_maxrate   = cxgb_set_tx_maxrate,
3598         .ndo_setup_tc         = cxgb_setup_tc,
3599         .ndo_udp_tunnel_add   = cxgb_add_udp_tunnel,
3600         .ndo_udp_tunnel_del   = cxgb_del_udp_tunnel,
3601         .ndo_features_check   = cxgb_features_check,
3602         .ndo_fix_features     = cxgb_fix_features,
3603 };
3604
3605 #ifdef CONFIG_PCI_IOV
3606 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
3607         .ndo_open               = cxgb4_mgmt_open,
3608         .ndo_set_vf_mac         = cxgb4_mgmt_set_vf_mac,
3609         .ndo_get_vf_config      = cxgb4_mgmt_get_vf_config,
3610         .ndo_set_vf_rate        = cxgb4_mgmt_set_vf_rate,
3611         .ndo_get_phys_port_id   = cxgb4_mgmt_get_phys_port_id,
3612         .ndo_set_vf_vlan        = cxgb4_mgmt_set_vf_vlan,
3613         .ndo_set_vf_link_state  = cxgb4_mgmt_set_vf_link_state,
3614 };
3615 #endif
3616
3617 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3618                                    struct ethtool_drvinfo *info)
3619 {
3620         struct adapter *adapter = netdev2adap(dev);
3621
3622         strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3623         strlcpy(info->bus_info, pci_name(adapter->pdev),
3624                 sizeof(info->bus_info));
3625 }
3626
3627 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
3628         .get_drvinfo       = cxgb4_mgmt_get_drvinfo,
3629 };
3630
3631 static void notify_fatal_err(struct work_struct *work)
3632 {
3633         struct adapter *adap;
3634
3635         adap = container_of(work, struct adapter, fatal_err_notify_task);
3636         notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3637 }
3638
3639 void t4_fatal_err(struct adapter *adap)
3640 {
3641         int port;
3642
3643         if (pci_channel_offline(adap->pdev))
3644                 return;
3645
3646         /* Disable the SGE since ULDs are going to free resources that
3647          * could be exposed to the adapter.  RDMA MWs for example...
3648          */
3649         t4_shutdown_adapter(adap);
3650         for_each_port(adap, port) {
3651                 struct net_device *dev = adap->port[port];
3652
3653                 /* If we get here in very early initialization the network
3654                  * devices may not have been set up yet.
3655                  */
3656                 if (!dev)
3657                         continue;
3658
3659                 netif_tx_stop_all_queues(dev);
3660                 netif_carrier_off(dev);
3661         }
3662         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3663         queue_work(adap->workq, &adap->fatal_err_notify_task);
3664 }
3665
3666 static void setup_memwin(struct adapter *adap)
3667 {
3668         u32 nic_win_base = t4_get_util_window(adap);
3669
3670         t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3671 }
3672
3673 static void setup_memwin_rdma(struct adapter *adap)
3674 {
3675         if (adap->vres.ocq.size) {
3676                 u32 start;
3677                 unsigned int sz_kb;
3678
3679                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3680                 start &= PCI_BASE_ADDRESS_MEM_MASK;
3681                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3682                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3683                 t4_write_reg(adap,
3684                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3685                              start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3686                 t4_write_reg(adap,
3687                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3688                              adap->vres.ocq.start);
3689                 t4_read_reg(adap,
3690                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3691         }
3692 }
3693
3694 /* HMA Definitions */
3695
3696 /* The maximum number of address that can be send in a single FW cmd */
3697 #define HMA_MAX_ADDR_IN_CMD     5
3698
3699 #define HMA_PAGE_SIZE           PAGE_SIZE
3700
3701 #define HMA_MAX_NO_FW_ADDRESS   (16 << 10)  /* FW supports 16K addresses */
3702
3703 #define HMA_PAGE_ORDER                                  \
3704         ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ?      \
3705         ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3706
3707 /* The minimum and maximum possible HMA sizes that can be specified in the FW
3708  * configuration(in units of MB).
3709  */
3710 #define HMA_MIN_TOTAL_SIZE      1
3711 #define HMA_MAX_TOTAL_SIZE                              \
3712         (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) *           \
3713           HMA_MAX_NO_FW_ADDRESS) >> 20)
3714
3715 static void adap_free_hma_mem(struct adapter *adapter)
3716 {
3717         struct scatterlist *iter;
3718         struct page *page;
3719         int i;
3720
3721         if (!adapter->hma.sgt)
3722                 return;
3723
3724         if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3725                 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3726                              adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3727                 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3728         }
3729
3730         for_each_sg(adapter->hma.sgt->sgl, iter,
3731                     adapter->hma.sgt->orig_nents, i) {
3732                 page = sg_page(iter);
3733                 if (page)
3734                         __free_pages(page, HMA_PAGE_ORDER);
3735         }
3736
3737         kfree(adapter->hma.phy_addr);
3738         sg_free_table(adapter->hma.sgt);
3739         kfree(adapter->hma.sgt);
3740         adapter->hma.sgt = NULL;
3741 }
3742
3743 static int adap_config_hma(struct adapter *adapter)
3744 {
3745         struct scatterlist *sgl, *iter;
3746         struct sg_table *sgt;
3747         struct page *newpage;
3748         unsigned int i, j, k;
3749         u32 param, hma_size;
3750         unsigned int ncmds;
3751         size_t page_size;
3752         u32 page_order;
3753         int node, ret;
3754
3755         /* HMA is supported only for T6+ cards.
3756          * Avoid initializing HMA in kdump kernels.
3757          */
3758         if (is_kdump_kernel() ||
3759             CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3760                 return 0;
3761
3762         /* Get the HMA region size required by fw */
3763         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3764                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3765         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3766                               1, &param, &hma_size);
3767         /* An error means card has its own memory or HMA is not supported by
3768          * the firmware. Return without any errors.
3769          */
3770         if (ret || !hma_size)
3771                 return 0;
3772
3773         if (hma_size < HMA_MIN_TOTAL_SIZE ||
3774             hma_size > HMA_MAX_TOTAL_SIZE) {
3775                 dev_err(adapter->pdev_dev,
3776                         "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3777                         hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3778                 return -EINVAL;
3779         }
3780
3781         page_size = HMA_PAGE_SIZE;
3782         page_order = HMA_PAGE_ORDER;
3783         adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3784         if (unlikely(!adapter->hma.sgt)) {
3785                 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3786                 return -ENOMEM;
3787         }
3788         sgt = adapter->hma.sgt;
3789         /* FW returned value will be in MB's
3790          */
3791         sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3792         if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3793                 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3794                 kfree(adapter->hma.sgt);
3795                 adapter->hma.sgt = NULL;
3796                 return -ENOMEM;
3797         }
3798
3799         sgl = adapter->hma.sgt->sgl;
3800         node = dev_to_node(adapter->pdev_dev);
3801         for_each_sg(sgl, iter, sgt->orig_nents, i) {
3802                 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3803                                            __GFP_ZERO, page_order);
3804                 if (!newpage) {
3805                         dev_err(adapter->pdev_dev,
3806                                 "Not enough memory for HMA page allocation\n");
3807                         ret = -ENOMEM;
3808                         goto free_hma;
3809                 }
3810                 sg_set_page(iter, newpage, page_size << page_order, 0);
3811         }
3812
3813         sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3814                                 DMA_BIDIRECTIONAL);
3815         if (!sgt->nents) {
3816                 dev_err(adapter->pdev_dev,
3817                         "Not enough memory for HMA DMA mapping");
3818                 ret = -ENOMEM;
3819                 goto free_hma;
3820         }
3821         adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3822
3823         adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3824                                         GFP_KERNEL);
3825         if (unlikely(!adapter->hma.phy_addr))
3826                 goto free_hma;
3827
3828         for_each_sg(sgl, iter, sgt->nents, i) {
3829                 newpage = sg_page(iter);
3830                 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3831         }
3832
3833         ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3834         /* Pass on the addresses to firmware */
3835         for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3836                 struct fw_hma_cmd hma_cmd;
3837                 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3838                 u8 soc = 0, eoc = 0;
3839                 u8 hma_mode = 1; /* Presently we support only Page table mode */
3840
3841                 soc = (i == 0) ? 1 : 0;
3842                 eoc = (i == ncmds - 1) ? 1 : 0;
3843
3844                 /* For last cmd, set naddr corresponding to remaining
3845                  * addresses
3846                  */
3847                 if (i == ncmds - 1) {
3848                         naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3849                         naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3850                 }
3851                 memset(&hma_cmd, 0, sizeof(hma_cmd));
3852                 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3853                                        FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3854                 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3855
3856                 hma_cmd.mode_to_pcie_params =
3857                         htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3858                               FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3859
3860                 /* HMA cmd size specified in MB's */
3861                 hma_cmd.naddr_size =
3862                         htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3863                               FW_HMA_CMD_NADDR_V(naddr));
3864
3865                 /* Total Page size specified in units of 4K */
3866                 hma_cmd.addr_size_pkd =
3867                         htonl(FW_HMA_CMD_ADDR_SIZE_V
3868                                 ((page_size << page_order) >> 12));
3869
3870                 /* Fill the 5 addresses */
3871                 for (j = 0; j < naddr; j++) {
3872                         hma_cmd.phy_address[j] =
3873                                 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3874                 }
3875                 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3876                                  sizeof(hma_cmd), &hma_cmd);
3877                 if (ret) {
3878                         dev_err(adapter->pdev_dev,
3879                                 "HMA FW command failed with err %d\n", ret);
3880                         goto free_hma;
3881                 }
3882         }
3883
3884         if (!ret)
3885                 dev_info(adapter->pdev_dev,
3886                          "Reserved %uMB host memory for HMA\n", hma_size);
3887         return ret;
3888
3889 free_hma:
3890         adap_free_hma_mem(adapter);
3891         return ret;
3892 }
3893
3894 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3895 {
3896         u32 v;
3897         int ret;
3898
3899         /* Now that we've successfully configured and initialized the adapter
3900          * can ask the Firmware what resources it has provisioned for us.
3901          */
3902         ret = t4_get_pfres(adap);
3903         if (ret) {
3904                 dev_err(adap->pdev_dev,
3905                         "Unable to retrieve resource provisioning information\n");
3906                 return ret;
3907         }
3908
3909         /* get device capabilities */
3910         memset(c, 0, sizeof(*c));
3911         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3912                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
3913         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3914         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3915         if (ret < 0)
3916                 return ret;
3917
3918         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3919                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3920         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3921         if (ret < 0)
3922                 return ret;
3923
3924         ret = t4_config_glbl_rss(adap, adap->pf,
3925                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3926                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3927                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3928         if (ret < 0)
3929                 return ret;
3930
3931         ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3932                           MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3933                           FW_CMD_CAP_PF);
3934         if (ret < 0)
3935                 return ret;
3936
3937         t4_sge_init(adap);
3938
3939         /* tweak some settings */
3940         t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3941         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3942         t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3943         v = t4_read_reg(adap, TP_PIO_DATA_A);
3944         t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3945
3946         /* first 4 Tx modulation queues point to consecutive Tx channels */
3947         adap->params.tp.tx_modq_map = 0xE4;
3948         t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3949                      TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3950
3951         /* associate each Tx modulation queue with consecutive Tx channels */
3952         v = 0x84218421;
3953         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3954                           &v, 1, TP_TX_SCHED_HDR_A);
3955         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3956                           &v, 1, TP_TX_SCHED_FIFO_A);
3957         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3958                           &v, 1, TP_TX_SCHED_PCMD_A);
3959
3960 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3961         if (is_offload(adap)) {
3962                 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3963                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3964                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3965                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3966                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3967                 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3968                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3969                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3970                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3971                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3972         }
3973
3974         /* get basic stuff going */
3975         return t4_early_init(adap, adap->pf);
3976 }
3977
3978 /*
3979  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
3980  */
3981 #define MAX_ATIDS 8192U
3982
3983 /*
3984  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3985  *
3986  * If the firmware we're dealing with has Configuration File support, then
3987  * we use that to perform all configuration
3988  */
3989
3990 /*
3991  * Tweak configuration based on module parameters, etc.  Most of these have
3992  * defaults assigned to them by Firmware Configuration Files (if we're using
3993  * them) but need to be explicitly set if we're using hard-coded
3994  * initialization.  But even in the case of using Firmware Configuration
3995  * Files, we'd like to expose the ability to change these via module
3996  * parameters so these are essentially common tweaks/settings for
3997  * Configuration Files and hard-coded initialization ...
3998  */
3999 static int adap_init0_tweaks(struct adapter *adapter)
4000 {
4001         /*
4002          * Fix up various Host-Dependent Parameters like Page Size, Cache
4003          * Line Size, etc.  The firmware default is for a 4KB Page Size and
4004          * 64B Cache Line Size ...
4005          */
4006         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
4007
4008         /*
4009          * Process module parameters which affect early initialization.
4010          */
4011         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
4012                 dev_err(&adapter->pdev->dev,
4013                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
4014                         rx_dma_offset);
4015                 rx_dma_offset = 2;
4016         }
4017         t4_set_reg_field(adapter, SGE_CONTROL_A,
4018                          PKTSHIFT_V(PKTSHIFT_M),
4019                          PKTSHIFT_V(rx_dma_offset));
4020
4021         /*
4022          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
4023          * adds the pseudo header itself.
4024          */
4025         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
4026                                CSUM_HAS_PSEUDO_HDR_F, 0);
4027
4028         return 0;
4029 }
4030
4031 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
4032  * unto themselves and they contain their own firmware to perform their
4033  * tasks ...
4034  */
4035 static int phy_aq1202_version(const u8 *phy_fw_data,
4036                               size_t phy_fw_size)
4037 {
4038         int offset;
4039
4040         /* At offset 0x8 you're looking for the primary image's
4041          * starting offset which is 3 Bytes wide
4042          *
4043          * At offset 0xa of the primary image, you look for the offset
4044          * of the DRAM segment which is 3 Bytes wide.
4045          *
4046          * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
4047          * wide
4048          */
4049         #define be16(__p) (((__p)[0] << 8) | (__p)[1])
4050         #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
4051         #define le24(__p) (le16(__p) | ((__p)[2] << 16))
4052
4053         offset = le24(phy_fw_data + 0x8) << 12;
4054         offset = le24(phy_fw_data + offset + 0xa);
4055         return be16(phy_fw_data + offset + 0x27e);
4056
4057         #undef be16
4058         #undef le16
4059         #undef le24
4060 }
4061
4062 static struct info_10gbt_phy_fw {
4063         unsigned int phy_fw_id;         /* PCI Device ID */
4064         char *phy_fw_file;              /* /lib/firmware/ PHY Firmware file */
4065         int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
4066         int phy_flash;                  /* Has FLASH for PHY Firmware */
4067 } phy_info_array[] = {
4068         {
4069                 PHY_AQ1202_DEVICEID,
4070                 PHY_AQ1202_FIRMWARE,
4071                 phy_aq1202_version,
4072                 1,
4073         },
4074         {
4075                 PHY_BCM84834_DEVICEID,
4076                 PHY_BCM84834_FIRMWARE,
4077                 NULL,
4078                 0,
4079         },
4080         { 0, NULL, NULL },
4081 };
4082
4083 static struct info_10gbt_phy_fw *find_phy_info(int devid)
4084 {
4085         int i;
4086
4087         for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
4088                 if (phy_info_array[i].phy_fw_id == devid)
4089                         return &phy_info_array[i];
4090         }
4091         return NULL;
4092 }
4093
4094 /* Handle updating of chip-external 10Gb/s-BT PHY firmware.  This needs to
4095  * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD.  On error
4096  * we return a negative error number.  If we transfer new firmware we return 1
4097  * (from t4_load_phy_fw()).  If we don't do anything we return 0.
4098  */
4099 static int adap_init0_phy(struct adapter *adap)
4100 {
4101         const struct firmware *phyf;
4102         int ret;
4103         struct info_10gbt_phy_fw *phy_info;
4104
4105         /* Use the device ID to determine which PHY file to flash.
4106          */
4107         phy_info = find_phy_info(adap->pdev->device);
4108         if (!phy_info) {
4109                 dev_warn(adap->pdev_dev,
4110                          "No PHY Firmware file found for this PHY\n");
4111                 return -EOPNOTSUPP;
4112         }
4113
4114         /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
4115          * use that. The adapter firmware provides us with a memory buffer
4116          * where we can load a PHY firmware file from the host if we want to
4117          * override the PHY firmware File in flash.
4118          */
4119         ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
4120                                       adap->pdev_dev);
4121         if (ret < 0) {
4122                 /* For adapters without FLASH attached to PHY for their
4123                  * firmware, it's obviously a fatal error if we can't get the
4124                  * firmware to the adapter.  For adapters with PHY firmware
4125                  * FLASH storage, it's worth a warning if we can't find the
4126                  * PHY Firmware but we'll neuter the error ...
4127                  */
4128                 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
4129                         "/lib/firmware/%s, error %d\n",
4130                         phy_info->phy_fw_file, -ret);
4131                 if (phy_info->phy_flash) {
4132                         int cur_phy_fw_ver = 0;
4133
4134                         t4_phy_fw_ver(adap, &cur_phy_fw_ver);
4135                         dev_warn(adap->pdev_dev, "continuing with, on-adapter "
4136                                  "FLASH copy, version %#x\n", cur_phy_fw_ver);
4137                         ret = 0;
4138                 }
4139
4140                 return ret;
4141         }
4142
4143         /* Load PHY Firmware onto adapter.
4144          */
4145         ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
4146                              phy_info->phy_fw_version,
4147                              (u8 *)phyf->data, phyf->size);
4148         if (ret < 0)
4149                 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
4150                         -ret);
4151         else if (ret > 0) {
4152                 int new_phy_fw_ver = 0;
4153
4154                 if (phy_info->phy_fw_version)
4155                         new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
4156                                                                   phyf->size);
4157                 dev_info(adap->pdev_dev, "Successfully transferred PHY "
4158                          "Firmware /lib/firmware/%s, version %#x\n",
4159                          phy_info->phy_fw_file, new_phy_fw_ver);
4160         }
4161
4162         release_firmware(phyf);
4163
4164         return ret;
4165 }
4166
4167 /*
4168  * Attempt to initialize the adapter via a Firmware Configuration File.
4169  */
4170 static int adap_init0_config(struct adapter *adapter, int reset)
4171 {
4172         char *fw_config_file, fw_config_file_path[256];
4173         u32 finiver, finicsum, cfcsum, param, val;
4174         struct fw_caps_config_cmd caps_cmd;
4175         unsigned long mtype = 0, maddr = 0;
4176         const struct firmware *cf;
4177         char *config_name = NULL;
4178         int config_issued = 0;
4179         int ret;
4180
4181         /*
4182          * Reset device if necessary.
4183          */
4184         if (reset) {
4185                 ret = t4_fw_reset(adapter, adapter->mbox,
4186                                   PIORSTMODE_F | PIORST_F);
4187                 if (ret < 0)
4188                         goto bye;
4189         }
4190
4191         /* If this is a 10Gb/s-BT adapter make sure the chip-external
4192          * 10Gb/s-BT PHYs have up-to-date firmware.  Note that this step needs
4193          * to be performed after any global adapter RESET above since some
4194          * PHYs only have local RAM copies of the PHY firmware.
4195          */
4196         if (is_10gbt_device(adapter->pdev->device)) {
4197                 ret = adap_init0_phy(adapter);
4198                 if (ret < 0)
4199                         goto bye;
4200         }
4201         /*
4202          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
4203          * then use that.  Otherwise, use the configuration file stored
4204          * in the adapter flash ...
4205          */
4206         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
4207         case CHELSIO_T4:
4208                 fw_config_file = FW4_CFNAME;
4209                 break;
4210         case CHELSIO_T5:
4211                 fw_config_file = FW5_CFNAME;
4212                 break;
4213         case CHELSIO_T6:
4214                 fw_config_file = FW6_CFNAME;
4215                 break;
4216         default:
4217                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
4218                        adapter->pdev->device);
4219                 ret = -EINVAL;
4220                 goto bye;
4221         }
4222
4223         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
4224         if (ret < 0) {
4225                 config_name = "On FLASH";
4226                 mtype = FW_MEMTYPE_CF_FLASH;
4227                 maddr = t4_flash_cfg_addr(adapter);
4228         } else {
4229                 u32 params[7], val[7];
4230
4231                 sprintf(fw_config_file_path,
4232                         "/lib/firmware/%s", fw_config_file);
4233                 config_name = fw_config_file_path;
4234
4235                 if (cf->size >= FLASH_CFG_MAX_SIZE)
4236                         ret = -ENOMEM;
4237                 else {
4238                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4239                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4240                         ret = t4_query_params(adapter, adapter->mbox,
4241                                               adapter->pf, 0, 1, params, val);
4242                         if (ret == 0) {
4243                                 /*
4244                                  * For t4_memory_rw() below addresses and
4245                                  * sizes have to be in terms of multiples of 4
4246                                  * bytes.  So, if the Configuration File isn't
4247                                  * a multiple of 4 bytes in length we'll have
4248                                  * to write that out separately since we can't
4249                                  * guarantee that the bytes following the
4250                                  * residual byte in the buffer returned by
4251                                  * request_firmware() are zeroed out ...
4252                                  */
4253                                 size_t resid = cf->size & 0x3;
4254                                 size_t size = cf->size & ~0x3;
4255                                 __be32 *data = (__be32 *)cf->data;
4256
4257                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
4258                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
4259
4260                                 spin_lock(&adapter->win0_lock);
4261                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
4262                                                    size, data, T4_MEMORY_WRITE);
4263                                 if (ret == 0 && resid != 0) {
4264                                         union {
4265                                                 __be32 word;
4266                                                 char buf[4];
4267                                         } last;
4268                                         int i;
4269
4270                                         last.word = data[size >> 2];
4271                                         for (i = resid; i < 4; i++)
4272                                                 last.buf[i] = 0;
4273                                         ret = t4_memory_rw(adapter, 0, mtype,
4274                                                            maddr + size,
4275                                                            4, &last.word,
4276                                                            T4_MEMORY_WRITE);
4277                                 }
4278                                 spin_unlock(&adapter->win0_lock);
4279                         }
4280                 }
4281
4282                 release_firmware(cf);
4283                 if (ret)
4284                         goto bye;
4285         }
4286
4287         val = 0;
4288
4289         /* Ofld + Hash filter is supported. Older fw will fail this request and
4290          * it is fine.
4291          */
4292         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4293                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD));
4294         ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0,
4295                             1, &param, &val);
4296
4297         /* FW doesn't know about Hash filter + ofld support,
4298          * it's not a problem, don't return an error.
4299          */
4300         if (ret < 0) {
4301                 dev_warn(adapter->pdev_dev,
4302                          "Hash filter with ofld is not supported by FW\n");
4303         }
4304
4305         /*
4306          * Issue a Capability Configuration command to the firmware to get it
4307          * to parse the Configuration File.  We don't use t4_fw_config_file()
4308          * because we want the ability to modify various features after we've
4309          * processed the configuration file ...
4310          */
4311         memset(&caps_cmd, 0, sizeof(caps_cmd));
4312         caps_cmd.op_to_write =
4313                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4314                       FW_CMD_REQUEST_F |
4315                       FW_CMD_READ_F);
4316         caps_cmd.cfvalid_to_len16 =
4317                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
4318                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
4319                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
4320                       FW_LEN16(caps_cmd));
4321         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4322                          &caps_cmd);
4323
4324         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
4325          * Configuration File in FLASH), our last gasp effort is to use the
4326          * Firmware Configuration File which is embedded in the firmware.  A
4327          * very few early versions of the firmware didn't have one embedded
4328          * but we can ignore those.
4329          */
4330         if (ret == -ENOENT) {
4331                 memset(&caps_cmd, 0, sizeof(caps_cmd));
4332                 caps_cmd.op_to_write =
4333                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4334                                         FW_CMD_REQUEST_F |
4335                                         FW_CMD_READ_F);
4336                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4337                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
4338                                 sizeof(caps_cmd), &caps_cmd);
4339                 config_name = "Firmware Default";
4340         }
4341
4342         config_issued = 1;
4343         if (ret < 0)
4344                 goto bye;
4345
4346         finiver = ntohl(caps_cmd.finiver);
4347         finicsum = ntohl(caps_cmd.finicsum);
4348         cfcsum = ntohl(caps_cmd.cfcsum);
4349         if (finicsum != cfcsum)
4350                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4351                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4352                          finicsum, cfcsum);
4353
4354         /*
4355          * And now tell the firmware to use the configuration we just loaded.
4356          */
4357         caps_cmd.op_to_write =
4358                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4359                       FW_CMD_REQUEST_F |
4360                       FW_CMD_WRITE_F);
4361         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4362         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4363                          NULL);
4364         if (ret < 0)
4365                 goto bye;
4366
4367         /*
4368          * Tweak configuration based on system architecture, module
4369          * parameters, etc.
4370          */
4371         ret = adap_init0_tweaks(adapter);
4372         if (ret < 0)
4373                 goto bye;
4374
4375         /* We will proceed even if HMA init fails. */
4376         ret = adap_config_hma(adapter);
4377         if (ret)
4378                 dev_err(adapter->pdev_dev,
4379                         "HMA configuration failed with error %d\n", ret);
4380
4381         if (is_t6(adapter->params.chip)) {
4382                 adap_config_hpfilter(adapter);
4383                 ret = setup_ppod_edram(adapter);
4384                 if (!ret)
4385                         dev_info(adapter->pdev_dev, "Successfully enabled "
4386                                  "ppod edram feature\n");
4387         }
4388
4389         /*
4390          * And finally tell the firmware to initialize itself using the
4391          * parameters from the Configuration File.
4392          */
4393         ret = t4_fw_initialize(adapter, adapter->mbox);
4394         if (ret < 0)
4395                 goto bye;
4396
4397         /* Emit Firmware Configuration File information and return
4398          * successfully.
4399          */
4400         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
4401                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4402                  config_name, finiver, cfcsum);
4403         return 0;
4404
4405         /*
4406          * Something bad happened.  Return the error ...  (If the "error"
4407          * is that there's no Configuration File on the adapter we don't
4408          * want to issue a warning since this is fairly common.)
4409          */
4410 bye:
4411         if (config_issued && ret != -ENOENT)
4412                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4413                          config_name, -ret);
4414         return ret;
4415 }
4416
4417 static struct fw_info fw_info_array[] = {
4418         {
4419                 .chip = CHELSIO_T4,
4420                 .fs_name = FW4_CFNAME,
4421                 .fw_mod_name = FW4_FNAME,
4422                 .fw_hdr = {
4423                         .chip = FW_HDR_CHIP_T4,
4424                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4425                         .intfver_nic = FW_INTFVER(T4, NIC),
4426                         .intfver_vnic = FW_INTFVER(T4, VNIC),
4427                         .intfver_ri = FW_INTFVER(T4, RI),
4428                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4429                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
4430                 },
4431         }, {
4432                 .chip = CHELSIO_T5,
4433                 .fs_name = FW5_CFNAME,
4434                 .fw_mod_name = FW5_FNAME,
4435                 .fw_hdr = {
4436                         .chip = FW_HDR_CHIP_T5,
4437                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4438                         .intfver_nic = FW_INTFVER(T5, NIC),
4439                         .intfver_vnic = FW_INTFVER(T5, VNIC),
4440                         .intfver_ri = FW_INTFVER(T5, RI),
4441                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4442                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
4443                 },
4444         }, {
4445                 .chip = CHELSIO_T6,
4446                 .fs_name = FW6_CFNAME,
4447                 .fw_mod_name = FW6_FNAME,
4448                 .fw_hdr = {
4449                         .chip = FW_HDR_CHIP_T6,
4450                         .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4451                         .intfver_nic = FW_INTFVER(T6, NIC),
4452                         .intfver_vnic = FW_INTFVER(T6, VNIC),
4453                         .intfver_ofld = FW_INTFVER(T6, OFLD),
4454                         .intfver_ri = FW_INTFVER(T6, RI),
4455                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4456                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4457                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4458                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
4459                 },
4460         }
4461
4462 };
4463
4464 static struct fw_info *find_fw_info(int chip)
4465 {
4466         int i;
4467
4468         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4469                 if (fw_info_array[i].chip == chip)
4470                         return &fw_info_array[i];
4471         }
4472         return NULL;
4473 }
4474
4475 /*
4476  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4477  */
4478 static int adap_init0(struct adapter *adap, int vpd_skip)
4479 {
4480         struct fw_caps_config_cmd caps_cmd;
4481         u32 params[7], val[7];
4482         enum dev_state state;
4483         u32 v, port_vec;
4484         int reset = 1;
4485         int ret;
4486
4487         /* Grab Firmware Device Log parameters as early as possible so we have
4488          * access to it for debugging, etc.
4489          */
4490         ret = t4_init_devlog_params(adap);
4491         if (ret < 0)
4492                 return ret;
4493
4494         /* Contact FW, advertising Master capability */
4495         ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4496                           is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
4497         if (ret < 0) {
4498                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4499                         ret);
4500                 return ret;
4501         }
4502         if (ret == adap->mbox)
4503                 adap->flags |= CXGB4_MASTER_PF;
4504
4505         /*
4506          * If we're the Master PF Driver and the device is uninitialized,
4507          * then let's consider upgrading the firmware ...  (We always want
4508          * to check the firmware version number in order to A. get it for
4509          * later reporting and B. to warn if the currently loaded firmware
4510          * is excessively mismatched relative to the driver.)
4511          */
4512
4513         t4_get_version_info(adap);
4514         ret = t4_check_fw_version(adap);
4515         /* If firmware is too old (not supported by driver) force an update. */
4516         if (ret)
4517                 state = DEV_STATE_UNINIT;
4518         if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
4519                 struct fw_info *fw_info;
4520                 struct fw_hdr *card_fw;
4521                 const struct firmware *fw;
4522                 const u8 *fw_data = NULL;
4523                 unsigned int fw_size = 0;
4524
4525                 /* This is the firmware whose headers the driver was compiled
4526                  * against
4527                  */
4528                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4529                 if (fw_info == NULL) {
4530                         dev_err(adap->pdev_dev,
4531                                 "unable to get firmware info for chip %d.\n",
4532                                 CHELSIO_CHIP_VERSION(adap->params.chip));
4533                         return -EINVAL;
4534                 }
4535
4536                 /* allocate memory to read the header of the firmware on the
4537                  * card
4538                  */
4539                 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
4540                 if (!card_fw) {
4541                         ret = -ENOMEM;
4542                         goto bye;
4543                 }
4544
4545                 /* Get FW from from /lib/firmware/ */
4546                 ret = request_firmware(&fw, fw_info->fw_mod_name,
4547                                        adap->pdev_dev);
4548                 if (ret < 0) {
4549                         dev_err(adap->pdev_dev,
4550                                 "unable to load firmware image %s, error %d\n",
4551                                 fw_info->fw_mod_name, ret);
4552                 } else {
4553                         fw_data = fw->data;
4554                         fw_size = fw->size;
4555                 }
4556
4557                 /* upgrade FW logic */
4558                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4559                                  state, &reset);
4560
4561                 /* Cleaning up */
4562                 release_firmware(fw);
4563                 kvfree(card_fw);
4564
4565                 if (ret < 0)
4566                         goto bye;
4567         }
4568
4569         /* If the firmware is initialized already, emit a simply note to that
4570          * effect. Otherwise, it's time to try initializing the adapter.
4571          */
4572         if (state == DEV_STATE_INIT) {
4573                 ret = adap_config_hma(adap);
4574                 if (ret)
4575                         dev_err(adap->pdev_dev,
4576                                 "HMA configuration failed with error %d\n",
4577                                 ret);
4578                 dev_info(adap->pdev_dev, "Coming up as %s: "\
4579                          "Adapter already initialized\n",
4580                          adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE");
4581         } else {
4582                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4583                          "Initializing adapter\n");
4584
4585                 /* Find out whether we're dealing with a version of the
4586                  * firmware which has configuration file support.
4587                  */
4588                 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4589                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4590                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
4591                                       params, val);
4592
4593                 /* If the firmware doesn't support Configuration Files,
4594                  * return an error.
4595                  */
4596                 if (ret < 0) {
4597                         dev_err(adap->pdev_dev, "firmware doesn't support "
4598                                 "Firmware Configuration Files\n");
4599                         goto bye;
4600                 }
4601
4602                 /* The firmware provides us with a memory buffer where we can
4603                  * load a Configuration File from the host if we want to
4604                  * override the Configuration File in flash.
4605                  */
4606                 ret = adap_init0_config(adap, reset);
4607                 if (ret == -ENOENT) {
4608                         dev_err(adap->pdev_dev, "no Configuration File "
4609                                 "present on adapter.\n");
4610                         goto bye;
4611                 }
4612                 if (ret < 0) {
4613                         dev_err(adap->pdev_dev, "could not initialize "
4614                                 "adapter, error %d\n", -ret);
4615                         goto bye;
4616                 }
4617         }
4618
4619         /* Now that we've successfully configured and initialized the adapter
4620          * (or found it already initialized), we can ask the Firmware what
4621          * resources it has provisioned for us.
4622          */
4623         ret = t4_get_pfres(adap);
4624         if (ret) {
4625                 dev_err(adap->pdev_dev,
4626                         "Unable to retrieve resource provisioning information\n");
4627                 goto bye;
4628         }
4629
4630         /* Grab VPD parameters.  This should be done after we establish a
4631          * connection to the firmware since some of the VPD parameters
4632          * (notably the Core Clock frequency) are retrieved via requests to
4633          * the firmware.  On the other hand, we need these fairly early on
4634          * so we do this right after getting ahold of the firmware.
4635          *
4636          * We need to do this after initializing the adapter because someone
4637          * could have FLASHed a new VPD which won't be read by the firmware
4638          * until we do the RESET ...
4639          */
4640         if (!vpd_skip) {
4641                 ret = t4_get_vpd_params(adap, &adap->params.vpd);
4642                 if (ret < 0)
4643                         goto bye;
4644         }
4645
4646         /* Find out what ports are available to us.  Note that we need to do
4647          * this before calling adap_init0_no_config() since it needs nports
4648          * and portvec ...
4649          */
4650         v =
4651             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4652             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4653         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4654         if (ret < 0)
4655                 goto bye;
4656
4657         adap->params.nports = hweight32(port_vec);
4658         adap->params.portvec = port_vec;
4659
4660         /* Give the SGE code a chance to pull in anything that it needs ...
4661          * Note that this must be called after we retrieve our VPD parameters
4662          * in order to know how to convert core ticks to seconds, etc.
4663          */
4664         ret = t4_sge_init(adap);
4665         if (ret < 0)
4666                 goto bye;
4667
4668         /* Grab the SGE Doorbell Queue Timer values.  If successful, that
4669          * indicates that the Firmware and Hardware support this.
4670          */
4671         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4672                     FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
4673         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4674                               1, params, val);
4675
4676         if (!ret) {
4677                 adap->sge.dbqtimer_tick = val[0];
4678                 ret = t4_read_sge_dbqtimers(adap,
4679                                             ARRAY_SIZE(adap->sge.dbqtimer_val),
4680                                             adap->sge.dbqtimer_val);
4681         }
4682
4683         if (!ret)
4684                 adap->flags |= CXGB4_SGE_DBQ_TIMER;
4685
4686         if (is_bypass_device(adap->pdev->device))
4687                 adap->params.bypass = 1;
4688
4689         /*
4690          * Grab some of our basic fundamental operating parameters.
4691          */
4692         params[0] = FW_PARAM_PFVF(EQ_START);
4693         params[1] = FW_PARAM_PFVF(L2T_START);
4694         params[2] = FW_PARAM_PFVF(L2T_END);
4695         params[3] = FW_PARAM_PFVF(FILTER_START);
4696         params[4] = FW_PARAM_PFVF(FILTER_END);
4697         params[5] = FW_PARAM_PFVF(IQFLINT_START);
4698         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
4699         if (ret < 0)
4700                 goto bye;
4701         adap->sge.egr_start = val[0];
4702         adap->l2t_start = val[1];
4703         adap->l2t_end = val[2];
4704         adap->tids.ftid_base = val[3];
4705         adap->tids.nftids = val[4] - val[3] + 1;
4706         adap->sge.ingr_start = val[5];
4707
4708         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4709                 params[0] = FW_PARAM_PFVF(HPFILTER_START);
4710                 params[1] = FW_PARAM_PFVF(HPFILTER_END);
4711                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4712                                       params, val);
4713                 if (ret < 0)
4714                         goto bye;
4715
4716                 adap->tids.hpftid_base = val[0];
4717                 adap->tids.nhpftids = val[1] - val[0] + 1;
4718
4719                 /* Read the raw mps entries. In T6, the last 2 tcam entries
4720                  * are reserved for raw mac addresses (rawf = 2, one per port).
4721                  */
4722                 params[0] = FW_PARAM_PFVF(RAWF_START);
4723                 params[1] = FW_PARAM_PFVF(RAWF_END);
4724                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4725                                       params, val);
4726                 if (ret == 0) {
4727                         adap->rawf_start = val[0];
4728                         adap->rawf_cnt = val[1] - val[0] + 1;
4729                 }
4730
4731                 adap->tids.tid_base =
4732                         t4_read_reg(adap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
4733         }
4734
4735         /* qids (ingress/egress) returned from firmware can be anywhere
4736          * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4737          * Hence driver needs to allocate memory for this range to
4738          * store the queue info. Get the highest IQFLINT/EQ index returned
4739          * in FW_EQ_*_CMD.alloc command.
4740          */
4741         params[0] = FW_PARAM_PFVF(EQ_END);
4742         params[1] = FW_PARAM_PFVF(IQFLINT_END);
4743         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4744         if (ret < 0)
4745                 goto bye;
4746         adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4747         adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4748
4749         adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4750                                     sizeof(*adap->sge.egr_map), GFP_KERNEL);
4751         if (!adap->sge.egr_map) {
4752                 ret = -ENOMEM;
4753                 goto bye;
4754         }
4755
4756         adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4757                                      sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4758         if (!adap->sge.ingr_map) {
4759                 ret = -ENOMEM;
4760                 goto bye;
4761         }
4762
4763         /* Allocate the memory for the vaious egress queue bitmaps
4764          * ie starving_fl, txq_maperr and blocked_fl.
4765          */
4766         adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4767                                         sizeof(long), GFP_KERNEL);
4768         if (!adap->sge.starving_fl) {
4769                 ret = -ENOMEM;
4770                 goto bye;
4771         }
4772
4773         adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4774                                        sizeof(long), GFP_KERNEL);
4775         if (!adap->sge.txq_maperr) {
4776                 ret = -ENOMEM;
4777                 goto bye;
4778         }
4779
4780 #ifdef CONFIG_DEBUG_FS
4781         adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4782                                        sizeof(long), GFP_KERNEL);
4783         if (!adap->sge.blocked_fl) {
4784                 ret = -ENOMEM;
4785                 goto bye;
4786         }
4787 #endif
4788
4789         params[0] = FW_PARAM_PFVF(CLIP_START);
4790         params[1] = FW_PARAM_PFVF(CLIP_END);
4791         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4792         if (ret < 0)
4793                 goto bye;
4794         adap->clipt_start = val[0];
4795         adap->clipt_end = val[1];
4796
4797         /* Get the supported number of traffic classes */
4798         params[0] = FW_PARAM_DEV(NUM_TM_CLASS);
4799         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4800         if (ret < 0) {
4801                 /* We couldn't retrieve the number of Traffic Classes
4802                  * supported by the hardware/firmware. So we hard
4803                  * code it here.
4804                  */
4805                 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4806         } else {
4807                 adap->params.nsched_cls = val[0];
4808         }
4809
4810         /* query params related to active filter region */
4811         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4812         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4813         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4814         /* If Active filter size is set we enable establishing
4815          * offload connection through firmware work request
4816          */
4817         if ((val[0] != val[1]) && (ret >= 0)) {
4818                 adap->flags |= CXGB4_FW_OFLD_CONN;
4819                 adap->tids.aftid_base = val[0];
4820                 adap->tids.aftid_end = val[1];
4821         }
4822
4823         /* If we're running on newer firmware, let it know that we're
4824          * prepared to deal with encapsulated CPL messages.  Older
4825          * firmware won't understand this and we'll just get
4826          * unencapsulated messages ...
4827          */
4828         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4829         val[0] = 1;
4830         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4831
4832         /*
4833          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4834          * capability.  Earlier versions of the firmware didn't have the
4835          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4836          * permission to use ULPTX MEMWRITE DSGL.
4837          */
4838         if (is_t4(adap->params.chip)) {
4839                 adap->params.ulptx_memwrite_dsgl = false;
4840         } else {
4841                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4842                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4843                                       1, params, val);
4844                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4845         }
4846
4847         /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4848         params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4849         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4850                               1, params, val);
4851         adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4852
4853         /* See if FW supports FW_FILTER2 work request */
4854         if (is_t4(adap->params.chip)) {
4855                 adap->params.filter2_wr_support = 0;
4856         } else {
4857                 params[0] = FW_PARAM_DEV(FILTER2_WR);
4858                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4859                                       1, params, val);
4860                 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4861         }
4862
4863         /* Check if FW supports returning vin and smt index.
4864          * If this is not supported, driver will interpret
4865          * these values from viid.
4866          */
4867         params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4868         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4869                               1, params, val);
4870         adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4871
4872         /*
4873          * Get device capabilities so we can determine what resources we need
4874          * to manage.
4875          */
4876         memset(&caps_cmd, 0, sizeof(caps_cmd));
4877         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4878                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
4879         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4880         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4881                          &caps_cmd);
4882         if (ret < 0)
4883                 goto bye;
4884
4885         /* hash filter has some mandatory register settings to be tested and for
4886          * that it needs to test whether offload is enabled or not, hence
4887          * checking and setting it here.
4888          */
4889         if (caps_cmd.ofldcaps)
4890                 adap->params.offload = 1;
4891
4892         if (caps_cmd.ofldcaps ||
4893             (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) ||
4894             (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD))) {
4895                 /* query offload-related parameters */
4896                 params[0] = FW_PARAM_DEV(NTID);
4897                 params[1] = FW_PARAM_PFVF(SERVER_START);
4898                 params[2] = FW_PARAM_PFVF(SERVER_END);
4899                 params[3] = FW_PARAM_PFVF(TDDP_START);
4900                 params[4] = FW_PARAM_PFVF(TDDP_END);
4901                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4902                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4903                                       params, val);
4904                 if (ret < 0)
4905                         goto bye;
4906                 adap->tids.ntids = val[0];
4907                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4908                 adap->tids.stid_base = val[1];
4909                 adap->tids.nstids = val[2] - val[1] + 1;
4910                 /*
4911                  * Setup server filter region. Divide the available filter
4912                  * region into two parts. Regular filters get 1/3rd and server
4913                  * filters get 2/3rd part. This is only enabled if workarond
4914                  * path is enabled.
4915                  * 1. For regular filters.
4916                  * 2. Server filter: This are special filters which are used
4917                  * to redirect SYN packets to offload queue.
4918                  */
4919                 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) {
4920                         adap->tids.sftid_base = adap->tids.ftid_base +
4921                                         DIV_ROUND_UP(adap->tids.nftids, 3);
4922                         adap->tids.nsftids = adap->tids.nftids -
4923                                          DIV_ROUND_UP(adap->tids.nftids, 3);
4924                         adap->tids.nftids = adap->tids.sftid_base -
4925                                                 adap->tids.ftid_base;
4926                 }
4927                 adap->vres.ddp.start = val[3];
4928                 adap->vres.ddp.size = val[4] - val[3] + 1;
4929                 adap->params.ofldq_wr_cred = val[5];
4930
4931                 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4932                         init_hash_filter(adap);
4933                 } else {
4934                         adap->num_ofld_uld += 1;
4935                 }
4936
4937                 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD)) {
4938                         params[0] = FW_PARAM_PFVF(ETHOFLD_START);
4939                         params[1] = FW_PARAM_PFVF(ETHOFLD_END);
4940                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4941                                               params, val);
4942                         if (!ret) {
4943                                 adap->tids.eotid_base = val[0];
4944                                 adap->tids.neotids = min_t(u32, MAX_ATIDS,
4945                                                            val[1] - val[0] + 1);
4946                                 adap->params.ethofld = 1;
4947                         }
4948                 }
4949         }
4950         if (caps_cmd.rdmacaps) {
4951                 params[0] = FW_PARAM_PFVF(STAG_START);
4952                 params[1] = FW_PARAM_PFVF(STAG_END);
4953                 params[2] = FW_PARAM_PFVF(RQ_START);
4954                 params[3] = FW_PARAM_PFVF(RQ_END);
4955                 params[4] = FW_PARAM_PFVF(PBL_START);
4956                 params[5] = FW_PARAM_PFVF(PBL_END);
4957                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4958                                       params, val);
4959                 if (ret < 0)
4960                         goto bye;
4961                 adap->vres.stag.start = val[0];
4962                 adap->vres.stag.size = val[1] - val[0] + 1;
4963                 adap->vres.rq.start = val[2];
4964                 adap->vres.rq.size = val[3] - val[2] + 1;
4965                 adap->vres.pbl.start = val[4];
4966                 adap->vres.pbl.size = val[5] - val[4] + 1;
4967
4968                 params[0] = FW_PARAM_PFVF(SRQ_START);
4969                 params[1] = FW_PARAM_PFVF(SRQ_END);
4970                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4971                                       params, val);
4972                 if (!ret) {
4973                         adap->vres.srq.start = val[0];
4974                         adap->vres.srq.size = val[1] - val[0] + 1;
4975                 }
4976                 if (adap->vres.srq.size) {
4977                         adap->srq = t4_init_srq(adap->vres.srq.size);
4978                         if (!adap->srq)
4979                                 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4980                 }
4981
4982                 params[0] = FW_PARAM_PFVF(SQRQ_START);
4983                 params[1] = FW_PARAM_PFVF(SQRQ_END);
4984                 params[2] = FW_PARAM_PFVF(CQ_START);
4985                 params[3] = FW_PARAM_PFVF(CQ_END);
4986                 params[4] = FW_PARAM_PFVF(OCQ_START);
4987                 params[5] = FW_PARAM_PFVF(OCQ_END);
4988                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4989                                       val);
4990                 if (ret < 0)
4991                         goto bye;
4992                 adap->vres.qp.start = val[0];
4993                 adap->vres.qp.size = val[1] - val[0] + 1;
4994                 adap->vres.cq.start = val[2];
4995                 adap->vres.cq.size = val[3] - val[2] + 1;
4996                 adap->vres.ocq.start = val[4];
4997                 adap->vres.ocq.size = val[5] - val[4] + 1;
4998
4999                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5000                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5001                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
5002                                       val);
5003                 if (ret < 0) {
5004                         adap->params.max_ordird_qp = 8;
5005                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5006                         ret = 0;
5007                 } else {
5008                         adap->params.max_ordird_qp = val[0];
5009                         adap->params.max_ird_adapter = val[1];
5010                 }
5011                 dev_info(adap->pdev_dev,
5012                          "max_ordird_qp %d max_ird_adapter %d\n",
5013                          adap->params.max_ordird_qp,
5014                          adap->params.max_ird_adapter);
5015
5016                 /* Enable write_with_immediate if FW supports it */
5017                 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
5018                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
5019                                       val);
5020                 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
5021
5022                 /* Enable write_cmpl if FW supports it */
5023                 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
5024                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
5025                                       val);
5026                 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
5027                 adap->num_ofld_uld += 2;
5028         }
5029         if (caps_cmd.iscsicaps) {
5030                 params[0] = FW_PARAM_PFVF(ISCSI_START);
5031                 params[1] = FW_PARAM_PFVF(ISCSI_END);
5032                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
5033                                       params, val);
5034                 if (ret < 0)
5035                         goto bye;
5036                 adap->vres.iscsi.start = val[0];
5037                 adap->vres.iscsi.size = val[1] - val[0] + 1;
5038                 if (is_t6(adap->params.chip)) {
5039                         params[0] = FW_PARAM_PFVF(PPOD_EDRAM_START);
5040                         params[1] = FW_PARAM_PFVF(PPOD_EDRAM_END);
5041                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
5042                                               params, val);
5043                         if (!ret) {
5044                                 adap->vres.ppod_edram.start = val[0];
5045                                 adap->vres.ppod_edram.size =
5046                                         val[1] - val[0] + 1;
5047
5048                                 dev_info(adap->pdev_dev,
5049                                          "ppod edram start 0x%x end 0x%x size 0x%x\n",
5050                                          val[0], val[1],
5051                                          adap->vres.ppod_edram.size);
5052                         }
5053                 }
5054                 /* LIO target and cxgb4i initiaitor */
5055                 adap->num_ofld_uld += 2;
5056         }
5057         if (caps_cmd.cryptocaps) {
5058                 if (ntohs(caps_cmd.cryptocaps) &
5059                     FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
5060                         params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
5061                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
5062                                               2, params, val);
5063                         if (ret < 0) {
5064                                 if (ret != -EINVAL)
5065                                         goto bye;
5066                         } else {
5067                                 adap->vres.ncrypto_fc = val[0];
5068                         }
5069                         adap->num_ofld_uld += 1;
5070                 }
5071                 if (ntohs(caps_cmd.cryptocaps) &
5072                     FW_CAPS_CONFIG_TLS_INLINE) {
5073                         params[0] = FW_PARAM_PFVF(TLS_START);
5074                         params[1] = FW_PARAM_PFVF(TLS_END);
5075                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
5076                                               2, params, val);
5077                         if (ret < 0)
5078                                 goto bye;
5079                         adap->vres.key.start = val[0];
5080                         adap->vres.key.size = val[1] - val[0] + 1;
5081                         adap->num_uld += 1;
5082                 }
5083                 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
5084         }
5085
5086         /* The MTU/MSS Table is initialized by now, so load their values.  If
5087          * we're initializing the adapter, then we'll make any modifications
5088          * we want to the MTU/MSS Table and also initialize the congestion
5089          * parameters.
5090          */
5091         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5092         if (state != DEV_STATE_INIT) {
5093                 int i;
5094
5095                 /* The default MTU Table contains values 1492 and 1500.
5096                  * However, for TCP, it's better to have two values which are
5097                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5098                  * This allows us to have a TCP Data Payload which is a
5099                  * multiple of 8 regardless of what combination of TCP Options
5100                  * are in use (always a multiple of 4 bytes) which is
5101                  * important for performance reasons.  For instance, if no
5102                  * options are in use, then we have a 20-byte IP header and a
5103                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
5104                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5105                  * which is not a multiple of 8.  So using an MSS of 1488 in
5106                  * this case results in a TCP Data Payload of 1448 bytes which
5107                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
5108                  * Stamps have been negotiated, then an MTU of 1500 bytes
5109                  * results in a TCP Data Payload of 1448 bytes which, as
5110                  * above, is a multiple of 8 bytes ...
5111                  */
5112                 for (i = 0; i < NMTUS; i++)
5113                         if (adap->params.mtus[i] == 1492) {
5114                                 adap->params.mtus[i] = 1488;
5115                                 break;
5116                         }
5117
5118                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5119                              adap->params.b_wnd);
5120         }
5121         t4_init_sge_params(adap);
5122         adap->flags |= CXGB4_FW_OK;
5123         t4_init_tp_params(adap, true);
5124         return 0;
5125
5126         /*
5127          * Something bad happened.  If a command timed out or failed with EIO
5128          * FW does not operate within its spec or something catastrophic
5129          * happened to HW/FW, stop issuing commands.
5130          */
5131 bye:
5132         adap_free_hma_mem(adap);
5133         kfree(adap->sge.egr_map);
5134         kfree(adap->sge.ingr_map);
5135         kfree(adap->sge.starving_fl);
5136         kfree(adap->sge.txq_maperr);
5137 #ifdef CONFIG_DEBUG_FS
5138         kfree(adap->sge.blocked_fl);
5139 #endif
5140         if (ret != -ETIMEDOUT && ret != -EIO)
5141                 t4_fw_bye(adap, adap->mbox);
5142         return ret;
5143 }
5144
5145 /* EEH callbacks */
5146
5147 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5148                                          pci_channel_state_t state)
5149 {
5150         int i;
5151         struct adapter *adap = pci_get_drvdata(pdev);
5152
5153         if (!adap)
5154                 goto out;
5155
5156         rtnl_lock();
5157         adap->flags &= ~CXGB4_FW_OK;
5158         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
5159         spin_lock(&adap->stats_lock);
5160         for_each_port(adap, i) {
5161                 struct net_device *dev = adap->port[i];
5162                 if (dev) {
5163                         netif_device_detach(dev);
5164                         netif_carrier_off(dev);
5165                 }
5166         }
5167         spin_unlock(&adap->stats_lock);
5168         disable_interrupts(adap);
5169         if (adap->flags & CXGB4_FULL_INIT_DONE)
5170                 cxgb_down(adap);
5171         rtnl_unlock();
5172         if ((adap->flags & CXGB4_DEV_ENABLED)) {
5173                 pci_disable_device(pdev);
5174                 adap->flags &= ~CXGB4_DEV_ENABLED;
5175         }
5176 out:    return state == pci_channel_io_perm_failure ?
5177                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5178 }
5179
5180 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5181 {
5182         int i, ret;
5183         struct fw_caps_config_cmd c;
5184         struct adapter *adap = pci_get_drvdata(pdev);
5185
5186         if (!adap) {
5187                 pci_restore_state(pdev);
5188                 pci_save_state(pdev);
5189                 return PCI_ERS_RESULT_RECOVERED;
5190         }
5191
5192         if (!(adap->flags & CXGB4_DEV_ENABLED)) {
5193                 if (pci_enable_device(pdev)) {
5194                         dev_err(&pdev->dev, "Cannot reenable PCI "
5195                                             "device after reset\n");
5196                         return PCI_ERS_RESULT_DISCONNECT;
5197                 }
5198                 adap->flags |= CXGB4_DEV_ENABLED;
5199         }
5200
5201         pci_set_master(pdev);
5202         pci_restore_state(pdev);
5203         pci_save_state(pdev);
5204
5205         if (t4_wait_dev_ready(adap->regs) < 0)
5206                 return PCI_ERS_RESULT_DISCONNECT;
5207         if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
5208                 return PCI_ERS_RESULT_DISCONNECT;
5209         adap->flags |= CXGB4_FW_OK;
5210         if (adap_init1(adap, &c))
5211                 return PCI_ERS_RESULT_DISCONNECT;
5212
5213         for_each_port(adap, i) {
5214                 struct port_info *pi = adap2pinfo(adap, i);
5215                 u8 vivld = 0, vin = 0;
5216
5217                 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
5218                                   NULL, NULL, &vivld, &vin);
5219                 if (ret < 0)
5220                         return PCI_ERS_RESULT_DISCONNECT;
5221                 pi->viid = ret;
5222                 pi->xact_addr_filt = -1;
5223                 /* If fw supports returning the VIN as part of FW_VI_CMD,
5224                  * save the returned values.
5225                  */
5226                 if (adap->params.viid_smt_extn_support) {
5227                         pi->vivld = vivld;
5228                         pi->vin = vin;
5229                 } else {
5230                         /* Retrieve the values from VIID */
5231                         pi->vivld = FW_VIID_VIVLD_G(pi->viid);
5232                         pi->vin = FW_VIID_VIN_G(pi->viid);
5233                 }
5234         }
5235
5236         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5237                      adap->params.b_wnd);
5238         setup_memwin(adap);
5239         if (cxgb_up(adap))
5240                 return PCI_ERS_RESULT_DISCONNECT;
5241         return PCI_ERS_RESULT_RECOVERED;
5242 }
5243
5244 static void eeh_resume(struct pci_dev *pdev)
5245 {
5246         int i;
5247         struct adapter *adap = pci_get_drvdata(pdev);
5248
5249         if (!adap)
5250                 return;
5251
5252         rtnl_lock();
5253         for_each_port(adap, i) {
5254                 struct net_device *dev = adap->port[i];
5255                 if (dev) {
5256                         if (netif_running(dev)) {
5257                                 link_start(dev);
5258                                 cxgb_set_rxmode(dev);
5259                         }
5260                         netif_device_attach(dev);
5261                 }
5262         }
5263         rtnl_unlock();
5264 }
5265
5266 static void eeh_reset_prepare(struct pci_dev *pdev)
5267 {
5268         struct adapter *adapter = pci_get_drvdata(pdev);
5269         int i;
5270
5271         if (adapter->pf != 4)
5272                 return;
5273
5274         adapter->flags &= ~CXGB4_FW_OK;
5275
5276         notify_ulds(adapter, CXGB4_STATE_DOWN);
5277
5278         for_each_port(adapter, i)
5279                 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5280                         cxgb_close(adapter->port[i]);
5281
5282         disable_interrupts(adapter);
5283         cxgb4_free_mps_ref_entries(adapter);
5284
5285         adap_free_hma_mem(adapter);
5286
5287         if (adapter->flags & CXGB4_FULL_INIT_DONE)
5288                 cxgb_down(adapter);
5289 }
5290
5291 static void eeh_reset_done(struct pci_dev *pdev)
5292 {
5293         struct adapter *adapter = pci_get_drvdata(pdev);
5294         int err, i;
5295
5296         if (adapter->pf != 4)
5297                 return;
5298
5299         err = t4_wait_dev_ready(adapter->regs);
5300         if (err < 0) {
5301                 dev_err(adapter->pdev_dev,
5302                         "Device not ready, err %d", err);
5303                 return;
5304         }
5305
5306         setup_memwin(adapter);
5307
5308         err = adap_init0(adapter, 1);
5309         if (err) {
5310                 dev_err(adapter->pdev_dev,
5311                         "Adapter init failed, err %d", err);
5312                 return;
5313         }
5314
5315         setup_memwin_rdma(adapter);
5316
5317         if (adapter->flags & CXGB4_FW_OK) {
5318                 err = t4_port_init(adapter, adapter->pf, adapter->pf, 0);
5319                 if (err) {
5320                         dev_err(adapter->pdev_dev,
5321                                 "Port init failed, err %d", err);
5322                         return;
5323                 }
5324         }
5325
5326         err = cfg_queues(adapter);
5327         if (err) {
5328                 dev_err(adapter->pdev_dev,
5329                         "Config queues failed, err %d", err);
5330                 return;
5331         }
5332
5333         cxgb4_init_mps_ref_entries(adapter);
5334
5335         err = setup_fw_sge_queues(adapter);
5336         if (err) {
5337                 dev_err(adapter->pdev_dev,
5338                         "FW sge queue allocation failed, err %d", err);
5339                 return;
5340         }
5341
5342         for_each_port(adapter, i)
5343                 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5344                         cxgb_open(adapter->port[i]);
5345 }
5346
5347 static const struct pci_error_handlers cxgb4_eeh = {
5348         .error_detected = eeh_err_detected,
5349         .slot_reset     = eeh_slot_reset,
5350         .resume         = eeh_resume,
5351         .reset_prepare  = eeh_reset_prepare,
5352         .reset_done     = eeh_reset_done,
5353 };
5354
5355 /* Return true if the Link Configuration supports "High Speeds" (those greater
5356  * than 1Gb/s).
5357  */
5358 static inline bool is_x_10g_port(const struct link_config *lc)
5359 {
5360         unsigned int speeds, high_speeds;
5361
5362         speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
5363         high_speeds = speeds &
5364                         ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
5365
5366         return high_speeds != 0;
5367 }
5368
5369 /* Perform default configuration of DMA queues depending on the number and type
5370  * of ports we found and the number of available CPUs.  Most settings can be
5371  * modified by the admin prior to actual use.
5372  */
5373 static int cfg_queues(struct adapter *adap)
5374 {
5375         u32 avail_qsets, avail_eth_qsets, avail_uld_qsets;
5376         u32 i, n10g = 0, qidx = 0, n1g = 0;
5377         u32 ncpus = num_online_cpus();
5378         u32 niqflint, neq, num_ulds;
5379         struct sge *s = &adap->sge;
5380         u32 q10g = 0, q1g;
5381
5382         /* Reduce memory usage in kdump environment, disable all offload. */
5383         if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
5384                 adap->params.offload = 0;
5385                 adap->params.crypto = 0;
5386                 adap->params.ethofld = 0;
5387         }
5388
5389         /* Calculate the number of Ethernet Queue Sets available based on
5390          * resources provisioned for us.  We always have an Asynchronous
5391          * Firmware Event Ingress Queue.  If we're operating in MSI or Legacy
5392          * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
5393          * Ingress Queue.  Meanwhile, we need two Egress Queues for each
5394          * Queue Set: one for the Free List and one for the Ethernet TX Queue.
5395          *
5396          * Note that we should also take into account all of the various
5397          * Offload Queues.  But, in any situation where we're operating in
5398          * a Resource Constrained Provisioning environment, doing any Offload
5399          * at all is problematic ...
5400          */
5401         niqflint = adap->params.pfres.niqflint - 1;
5402         if (!(adap->flags & CXGB4_USING_MSIX))
5403                 niqflint--;
5404         neq = adap->params.pfres.neq / 2;
5405         avail_qsets = min(niqflint, neq);
5406
5407         if (avail_qsets < adap->params.nports) {
5408                 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
5409                         avail_qsets, adap->params.nports);
5410                 return -ENOMEM;
5411         }
5412
5413         /* Count the number of 10Gb/s or better ports */
5414         for_each_port(adap, i)
5415                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
5416
5417         avail_eth_qsets = min_t(u32, avail_qsets, MAX_ETH_QSETS);
5418
5419         /* We default to 1 queue per non-10G port and up to # of cores queues
5420          * per 10G port.
5421          */
5422         if (n10g)
5423                 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5424
5425         n1g = adap->params.nports - n10g;
5426 #ifdef CONFIG_CHELSIO_T4_DCB
5427         /* For Data Center Bridging support we need to be able to support up
5428          * to 8 Traffic Priorities; each of which will be assigned to its
5429          * own TX Queue in order to prevent Head-Of-Line Blocking.
5430          */
5431         q1g = 8;
5432         if (adap->params.nports * 8 > avail_eth_qsets) {
5433                 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
5434                         avail_eth_qsets, adap->params.nports * 8);
5435                 return -ENOMEM;
5436         }
5437
5438         if (adap->params.nports * ncpus < avail_eth_qsets)
5439                 q10g = max(8U, ncpus);
5440         else
5441                 q10g = max(8U, q10g);
5442
5443         while ((q10g * n10g) > (avail_eth_qsets - n1g * q1g))
5444                 q10g--;
5445
5446 #else /* !CONFIG_CHELSIO_T4_DCB */
5447         q1g = 1;
5448         q10g = min(q10g, ncpus);
5449 #endif /* !CONFIG_CHELSIO_T4_DCB */
5450         if (is_kdump_kernel()) {
5451                 q10g = 1;
5452                 q1g = 1;
5453         }
5454
5455         for_each_port(adap, i) {
5456                 struct port_info *pi = adap2pinfo(adap, i);
5457
5458                 pi->first_qset = qidx;
5459                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : q1g;
5460                 qidx += pi->nqsets;
5461         }
5462
5463         s->ethqsets = qidx;
5464         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
5465         avail_qsets -= qidx;
5466
5467         if (is_uld(adap)) {
5468                 /* For offload we use 1 queue/channel if all ports are up to 1G,
5469                  * otherwise we divide all available queues amongst the channels
5470                  * capped by the number of available cores.
5471                  */
5472                 num_ulds = adap->num_uld + adap->num_ofld_uld;
5473                 i = min_t(u32, MAX_OFLD_QSETS, ncpus);
5474                 avail_uld_qsets = roundup(i, adap->params.nports);
5475                 if (avail_qsets < num_ulds * adap->params.nports) {
5476                         adap->params.offload = 0;
5477                         adap->params.crypto = 0;
5478                         s->ofldqsets = 0;
5479                 } else if (avail_qsets < num_ulds * avail_uld_qsets || !n10g) {
5480                         s->ofldqsets = adap->params.nports;
5481                 } else {
5482                         s->ofldqsets = avail_uld_qsets;
5483                 }
5484
5485                 avail_qsets -= num_ulds * s->ofldqsets;
5486         }
5487
5488         /* ETHOFLD Queues used for QoS offload should follow same
5489          * allocation scheme as normal Ethernet Queues.
5490          */
5491         if (is_ethofld(adap)) {
5492                 if (avail_qsets < s->max_ethqsets) {
5493                         adap->params.ethofld = 0;
5494                         s->eoqsets = 0;
5495                 } else {
5496                         s->eoqsets = s->max_ethqsets;
5497                 }
5498                 avail_qsets -= s->eoqsets;
5499         }
5500
5501         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5502                 struct sge_eth_rxq *r = &s->ethrxq[i];
5503
5504                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
5505                 r->fl.size = 72;
5506         }
5507
5508         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5509                 s->ethtxq[i].q.size = 1024;
5510
5511         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5512                 s->ctrlq[i].q.size = 512;
5513
5514         if (!is_t4(adap->params.chip))
5515                 s->ptptxq.q.size = 8;
5516
5517         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
5518         init_rspq(adap, &s->intrq, 0, 1, 512, 64);
5519
5520         return 0;
5521 }
5522
5523 /*
5524  * Reduce the number of Ethernet queues across all ports to at most n.
5525  * n provides at least one queue per port.
5526  */
5527 static void reduce_ethqs(struct adapter *adap, int n)
5528 {
5529         int i;
5530         struct port_info *pi;
5531
5532         while (n < adap->sge.ethqsets)
5533                 for_each_port(adap, i) {
5534                         pi = adap2pinfo(adap, i);
5535                         if (pi->nqsets > 1) {
5536                                 pi->nqsets--;
5537                                 adap->sge.ethqsets--;
5538                                 if (adap->sge.ethqsets <= n)
5539                                         break;
5540                         }
5541                 }
5542
5543         n = 0;
5544         for_each_port(adap, i) {
5545                 pi = adap2pinfo(adap, i);
5546                 pi->first_qset = n;
5547                 n += pi->nqsets;
5548         }
5549 }
5550
5551 static int alloc_msix_info(struct adapter *adap, u32 num_vec)
5552 {
5553         struct msix_info *msix_info;
5554
5555         msix_info = kcalloc(num_vec, sizeof(*msix_info), GFP_KERNEL);
5556         if (!msix_info)
5557                 return -ENOMEM;
5558
5559         adap->msix_bmap.msix_bmap = kcalloc(BITS_TO_LONGS(num_vec),
5560                                             sizeof(long), GFP_KERNEL);
5561         if (!adap->msix_bmap.msix_bmap) {
5562                 kfree(msix_info);
5563                 return -ENOMEM;
5564         }
5565
5566         spin_lock_init(&adap->msix_bmap.lock);
5567         adap->msix_bmap.mapsize = num_vec;
5568
5569         adap->msix_info = msix_info;
5570         return 0;
5571 }
5572
5573 static void free_msix_info(struct adapter *adap)
5574 {
5575         kfree(adap->msix_bmap.msix_bmap);
5576         kfree(adap->msix_info);
5577 }
5578
5579 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap)
5580 {
5581         struct msix_bmap *bmap = &adap->msix_bmap;
5582         unsigned int msix_idx;
5583         unsigned long flags;
5584
5585         spin_lock_irqsave(&bmap->lock, flags);
5586         msix_idx = find_first_zero_bit(bmap->msix_bmap, bmap->mapsize);
5587         if (msix_idx < bmap->mapsize) {
5588                 __set_bit(msix_idx, bmap->msix_bmap);
5589         } else {
5590                 spin_unlock_irqrestore(&bmap->lock, flags);
5591                 return -ENOSPC;
5592         }
5593
5594         spin_unlock_irqrestore(&bmap->lock, flags);
5595         return msix_idx;
5596 }
5597
5598 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap,
5599                                  unsigned int msix_idx)
5600 {
5601         struct msix_bmap *bmap = &adap->msix_bmap;
5602         unsigned long flags;
5603
5604         spin_lock_irqsave(&bmap->lock, flags);
5605         __clear_bit(msix_idx, bmap->msix_bmap);
5606         spin_unlock_irqrestore(&bmap->lock, flags);
5607 }
5608
5609 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5610 #define EXTRA_VECS 2
5611
5612 static int enable_msix(struct adapter *adap)
5613 {
5614         u32 eth_need, uld_need = 0, ethofld_need = 0;
5615         u32 ethqsets = 0, ofldqsets = 0, eoqsets = 0;
5616         u8 num_uld = 0, nchan = adap->params.nports;
5617         u32 i, want, need, num_vec;
5618         struct sge *s = &adap->sge;
5619         struct msix_entry *entries;
5620         struct port_info *pi;
5621         int allocated, ret;
5622
5623         want = s->max_ethqsets;
5624 #ifdef CONFIG_CHELSIO_T4_DCB
5625         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5626          * each port.
5627          */
5628         need = 8 * nchan;
5629 #else
5630         need = nchan;
5631 #endif
5632         eth_need = need;
5633         if (is_uld(adap)) {
5634                 num_uld = adap->num_ofld_uld + adap->num_uld;
5635                 want += num_uld * s->ofldqsets;
5636                 uld_need = num_uld * nchan;
5637                 need += uld_need;
5638         }
5639
5640         if (is_ethofld(adap)) {
5641                 want += s->eoqsets;
5642                 ethofld_need = eth_need;
5643                 need += ethofld_need;
5644         }
5645
5646         want += EXTRA_VECS;
5647         need += EXTRA_VECS;
5648
5649         entries = kmalloc_array(want, sizeof(*entries), GFP_KERNEL);
5650         if (!entries)
5651                 return -ENOMEM;
5652
5653         for (i = 0; i < want; i++)
5654                 entries[i].entry = i;
5655
5656         allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5657         if (allocated < 0) {
5658                 /* Disable offload and attempt to get vectors for NIC
5659                  * only mode.
5660                  */
5661                 want = s->max_ethqsets + EXTRA_VECS;
5662                 need = eth_need + EXTRA_VECS;
5663                 allocated = pci_enable_msix_range(adap->pdev, entries,
5664                                                   need, want);
5665                 if (allocated < 0) {
5666                         dev_info(adap->pdev_dev,
5667                                  "Disabling MSI-X due to insufficient MSI-X vectors\n");
5668                         ret = allocated;
5669                         goto out_free;
5670                 }
5671
5672                 dev_info(adap->pdev_dev,
5673                          "Disabling offload due to insufficient MSI-X vectors\n");
5674                 adap->params.offload = 0;
5675                 adap->params.crypto = 0;
5676                 adap->params.ethofld = 0;
5677                 s->ofldqsets = 0;
5678                 s->eoqsets = 0;
5679                 uld_need = 0;
5680                 ethofld_need = 0;
5681         }
5682
5683         num_vec = allocated;
5684         if (num_vec < want) {
5685                 /* Distribute available vectors to the various queue groups.
5686                  * Every group gets its minimum requirement and NIC gets top
5687                  * priority for leftovers.
5688                  */
5689                 ethqsets = eth_need;
5690                 if (is_uld(adap))
5691                         ofldqsets = nchan;
5692                 if (is_ethofld(adap))
5693                         eoqsets = ethofld_need;
5694
5695                 num_vec -= need;
5696                 while (num_vec) {
5697                         if (num_vec < eth_need + ethofld_need ||
5698                             ethqsets > s->max_ethqsets)
5699                                 break;
5700
5701                         for_each_port(adap, i) {
5702                                 pi = adap2pinfo(adap, i);
5703                                 if (pi->nqsets < 2)
5704                                         continue;
5705
5706                                 ethqsets++;
5707                                 num_vec--;
5708                                 if (ethofld_need) {
5709                                         eoqsets++;
5710                                         num_vec--;
5711                                 }
5712                         }
5713                 }
5714
5715                 if (is_uld(adap)) {
5716                         while (num_vec) {
5717                                 if (num_vec < uld_need ||
5718                                     ofldqsets > s->ofldqsets)
5719                                         break;
5720
5721                                 ofldqsets++;
5722                                 num_vec -= uld_need;
5723                         }
5724                 }
5725         } else {
5726                 ethqsets = s->max_ethqsets;
5727                 if (is_uld(adap))
5728                         ofldqsets = s->ofldqsets;
5729                 if (is_ethofld(adap))
5730                         eoqsets = s->eoqsets;
5731         }
5732
5733         if (ethqsets < s->max_ethqsets) {
5734                 s->max_ethqsets = ethqsets;
5735                 reduce_ethqs(adap, ethqsets);
5736         }
5737
5738         if (is_uld(adap)) {
5739                 s->ofldqsets = ofldqsets;
5740                 s->nqs_per_uld = s->ofldqsets;
5741         }
5742
5743         if (is_ethofld(adap))
5744                 s->eoqsets = eoqsets;
5745
5746         /* map for msix */
5747         ret = alloc_msix_info(adap, allocated);
5748         if (ret)
5749                 goto out_disable_msix;
5750
5751         for (i = 0; i < allocated; i++) {
5752                 adap->msix_info[i].vec = entries[i].vector;
5753                 adap->msix_info[i].idx = i;
5754         }
5755
5756         dev_info(adap->pdev_dev,
5757                  "%d MSI-X vectors allocated, nic %d eoqsets %d per uld %d\n",
5758                  allocated, s->max_ethqsets, s->eoqsets, s->nqs_per_uld);
5759
5760         kfree(entries);
5761         return 0;
5762
5763 out_disable_msix:
5764         pci_disable_msix(adap->pdev);
5765
5766 out_free:
5767         kfree(entries);
5768         return ret;
5769 }
5770
5771 #undef EXTRA_VECS
5772
5773 static int init_rss(struct adapter *adap)
5774 {
5775         unsigned int i;
5776         int err;
5777
5778         err = t4_init_rss_mode(adap, adap->mbox);
5779         if (err)
5780                 return err;
5781
5782         for_each_port(adap, i) {
5783                 struct port_info *pi = adap2pinfo(adap, i);
5784
5785                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5786                 if (!pi->rss)
5787                         return -ENOMEM;
5788         }
5789         return 0;
5790 }
5791
5792 /* Dump basic information about the adapter */
5793 static void print_adapter_info(struct adapter *adapter)
5794 {
5795         /* Hardware/Firmware/etc. Version/Revision IDs */
5796         t4_dump_version_info(adapter);
5797
5798         /* Software/Hardware configuration */
5799         dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5800                  is_offload(adapter) ? "R" : "",
5801                  ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
5802                   (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
5803                  is_offload(adapter) ? "Offload" : "non-Offload");
5804 }
5805
5806 static void print_port_info(const struct net_device *dev)
5807 {
5808         char buf[80];
5809         char *bufp = buf;
5810         const struct port_info *pi = netdev_priv(dev);
5811         const struct adapter *adap = pi->adapter;
5812
5813         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5814                 bufp += sprintf(bufp, "100M/");
5815         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5816                 bufp += sprintf(bufp, "1G/");
5817         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
5818                 bufp += sprintf(bufp, "10G/");
5819         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
5820                 bufp += sprintf(bufp, "25G/");
5821         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
5822                 bufp += sprintf(bufp, "40G/");
5823         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5824                 bufp += sprintf(bufp, "50G/");
5825         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
5826                 bufp += sprintf(bufp, "100G/");
5827         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5828                 bufp += sprintf(bufp, "200G/");
5829         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5830                 bufp += sprintf(bufp, "400G/");
5831         if (bufp != buf)
5832                 --bufp;
5833         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
5834
5835         netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5836                     dev->name, adap->params.vpd.id, adap->name, buf);
5837 }
5838
5839 /*
5840  * Free the following resources:
5841  * - memory used for tables
5842  * - MSI/MSI-X
5843  * - net devices
5844  * - resources FW is holding for us
5845  */
5846 static void free_some_resources(struct adapter *adapter)
5847 {
5848         unsigned int i;
5849
5850         kvfree(adapter->smt);
5851         kvfree(adapter->l2t);
5852         kvfree(adapter->srq);
5853         t4_cleanup_sched(adapter);
5854         kvfree(adapter->tids.tid_tab);
5855         cxgb4_cleanup_tc_matchall(adapter);
5856         cxgb4_cleanup_tc_mqprio(adapter);
5857         cxgb4_cleanup_tc_flower(adapter);
5858         cxgb4_cleanup_tc_u32(adapter);
5859         kfree(adapter->sge.egr_map);
5860         kfree(adapter->sge.ingr_map);
5861         kfree(adapter->sge.starving_fl);
5862         kfree(adapter->sge.txq_maperr);
5863 #ifdef CONFIG_DEBUG_FS
5864         kfree(adapter->sge.blocked_fl);
5865 #endif
5866         disable_msi(adapter);
5867
5868         for_each_port(adapter, i)
5869                 if (adapter->port[i]) {
5870                         struct port_info *pi = adap2pinfo(adapter, i);
5871
5872                         if (pi->viid != 0)
5873                                 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5874                                            0, pi->viid);
5875                         kfree(adap2pinfo(adapter, i)->rss);
5876                         free_netdev(adapter->port[i]);
5877                 }
5878         if (adapter->flags & CXGB4_FW_OK)
5879                 t4_fw_bye(adapter, adapter->pf);
5880 }
5881
5882 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN | \
5883                    NETIF_F_GSO_UDP_L4)
5884 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
5885                    NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
5886 #define SEGMENT_SIZE 128
5887
5888 static int t4_get_chip_type(struct adapter *adap, int ver)
5889 {
5890         u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
5891
5892         switch (ver) {
5893         case CHELSIO_T4:
5894                 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
5895         case CHELSIO_T5:
5896                 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5897         case CHELSIO_T6:
5898                 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5899         default:
5900                 break;
5901         }
5902         return -EINVAL;
5903 }
5904
5905 #ifdef CONFIG_PCI_IOV
5906 static void cxgb4_mgmt_setup(struct net_device *dev)
5907 {
5908         dev->type = ARPHRD_NONE;
5909         dev->mtu = 0;
5910         dev->hard_header_len = 0;
5911         dev->addr_len = 0;
5912         dev->tx_queue_len = 0;
5913         dev->flags |= IFF_NOARP;
5914         dev->priv_flags |= IFF_NO_QUEUE;
5915
5916         /* Initialize the device structure. */
5917         dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5918         dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
5919 }
5920
5921 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5922 {
5923         struct adapter *adap = pci_get_drvdata(pdev);
5924         int err = 0;
5925         int current_vfs = pci_num_vf(pdev);
5926         u32 pcie_fw;
5927
5928         pcie_fw = readl(adap->regs + PCIE_FW_A);
5929         /* Check if fw is initialized */
5930         if (!(pcie_fw & PCIE_FW_INIT_F)) {
5931                 dev_warn(&pdev->dev, "Device not initialized\n");
5932                 return -EOPNOTSUPP;
5933         }
5934
5935         /* If any of the VF's is already assigned to Guest OS, then
5936          * SRIOV for the same cannot be modified
5937          */
5938         if (current_vfs && pci_vfs_assigned(pdev)) {
5939                 dev_err(&pdev->dev,
5940                         "Cannot modify SR-IOV while VFs are assigned\n");
5941                 return current_vfs;
5942         }
5943         /* Note that the upper-level code ensures that we're never called with
5944          * a non-zero "num_vfs" when we already have VFs instantiated.  But
5945          * it never hurts to code defensively.
5946          */
5947         if (num_vfs != 0 && current_vfs != 0)
5948                 return -EBUSY;
5949
5950         /* Nothing to do for no change. */
5951         if (num_vfs == current_vfs)
5952                 return num_vfs;
5953
5954         /* Disable SRIOV when zero is passed. */
5955         if (!num_vfs) {
5956                 pci_disable_sriov(pdev);
5957                 /* free VF Management Interface */
5958                 unregister_netdev(adap->port[0]);
5959                 free_netdev(adap->port[0]);
5960                 adap->port[0] = NULL;
5961
5962                 /* free VF resources */
5963                 adap->num_vfs = 0;
5964                 kfree(adap->vfinfo);
5965                 adap->vfinfo = NULL;
5966                 return 0;
5967         }
5968
5969         if (!current_vfs) {
5970                 struct fw_pfvf_cmd port_cmd, port_rpl;
5971                 struct net_device *netdev;
5972                 unsigned int pmask, port;
5973                 struct pci_dev *pbridge;
5974                 struct port_info *pi;
5975                 char name[IFNAMSIZ];
5976                 u32 devcap2;
5977                 u16 flags;
5978
5979                 /* If we want to instantiate Virtual Functions, then our
5980                  * parent bridge's PCI-E needs to support Alternative Routing
5981                  * ID (ARI) because our VFs will show up at function offset 8
5982                  * and above.
5983                  */
5984                 pbridge = pdev->bus->self;
5985                 pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags);
5986                 pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2);
5987
5988                 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5989                     !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5990                         /* Our parent bridge does not support ARI so issue a
5991                          * warning and skip instantiating the VFs.  They
5992                          * won't be reachable.
5993                          */
5994                         dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5995                                  pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5996                                  PCI_FUNC(pbridge->devfn));
5997                         return -ENOTSUPP;
5998                 }
5999                 memset(&port_cmd, 0, sizeof(port_cmd));
6000                 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
6001                                                  FW_CMD_REQUEST_F |
6002                                                  FW_CMD_READ_F |
6003                                                  FW_PFVF_CMD_PFN_V(adap->pf) |
6004                                                  FW_PFVF_CMD_VFN_V(0));
6005                 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
6006                 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
6007                                  &port_rpl);
6008                 if (err)
6009                         return err;
6010                 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
6011                 port = ffs(pmask) - 1;
6012                 /* Allocate VF Management Interface. */
6013                 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
6014                          adap->pf);
6015                 netdev = alloc_netdev(sizeof(struct port_info),
6016                                       name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
6017                 if (!netdev)
6018                         return -ENOMEM;
6019
6020                 pi = netdev_priv(netdev);
6021                 pi->adapter = adap;
6022                 pi->lport = port;
6023                 pi->tx_chan = port;
6024                 SET_NETDEV_DEV(netdev, &pdev->dev);
6025
6026                 adap->port[0] = netdev;
6027                 pi->port_id = 0;
6028
6029                 err = register_netdev(adap->port[0]);
6030                 if (err) {
6031                         pr_info("Unable to register VF mgmt netdev %s\n", name);
6032                         free_netdev(adap->port[0]);
6033                         adap->port[0] = NULL;
6034                         return err;
6035                 }
6036                 /* Allocate and set up VF Information. */
6037                 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
6038                                        sizeof(struct vf_info), GFP_KERNEL);
6039                 if (!adap->vfinfo) {
6040                         unregister_netdev(adap->port[0]);
6041                         free_netdev(adap->port[0]);
6042                         adap->port[0] = NULL;
6043                         return -ENOMEM;
6044                 }
6045                 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
6046         }
6047         /* Instantiate the requested number of VFs. */
6048         err = pci_enable_sriov(pdev, num_vfs);
6049         if (err) {
6050                 pr_info("Unable to instantiate %d VFs\n", num_vfs);
6051                 if (!current_vfs) {
6052                         unregister_netdev(adap->port[0]);
6053                         free_netdev(adap->port[0]);
6054                         adap->port[0] = NULL;
6055                         kfree(adap->vfinfo);
6056                         adap->vfinfo = NULL;
6057                 }
6058                 return err;
6059         }
6060
6061         adap->num_vfs = num_vfs;
6062         return num_vfs;
6063 }
6064 #endif /* CONFIG_PCI_IOV */
6065
6066 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6067 {
6068         struct net_device *netdev;
6069         struct adapter *adapter;
6070         static int adap_idx = 1;
6071         int s_qpp, qpp, num_seg;
6072         struct port_info *pi;
6073         bool highdma = false;
6074         enum chip_type chip;
6075         void __iomem *regs;
6076         int func, chip_ver;
6077         u16 device_id;
6078         int i, err;
6079         u32 whoami;
6080
6081         err = pci_request_regions(pdev, KBUILD_MODNAME);
6082         if (err) {
6083                 /* Just info, some other driver may have claimed the device. */
6084                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6085                 return err;
6086         }
6087
6088         err = pci_enable_device(pdev);
6089         if (err) {
6090                 dev_err(&pdev->dev, "cannot enable PCI device\n");
6091                 goto out_release_regions;
6092         }
6093
6094         regs = pci_ioremap_bar(pdev, 0);
6095         if (!regs) {
6096                 dev_err(&pdev->dev, "cannot map device registers\n");
6097                 err = -ENOMEM;
6098                 goto out_disable_device;
6099         }
6100
6101         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6102         if (!adapter) {
6103                 err = -ENOMEM;
6104                 goto out_unmap_bar0;
6105         }
6106
6107         adapter->regs = regs;
6108         err = t4_wait_dev_ready(regs);
6109         if (err < 0)
6110                 goto out_free_adapter;
6111
6112         /* We control everything through one PF */
6113         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
6114         pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
6115         chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
6116         if ((int)chip < 0) {
6117                 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
6118                 err = chip;
6119                 goto out_free_adapter;
6120         }
6121         chip_ver = CHELSIO_CHIP_VERSION(chip);
6122         func = chip_ver <= CHELSIO_T5 ?
6123                SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
6124
6125         adapter->pdev = pdev;
6126         adapter->pdev_dev = &pdev->dev;
6127         adapter->name = pci_name(pdev);
6128         adapter->mbox = func;
6129         adapter->pf = func;
6130         adapter->params.chip = chip;
6131         adapter->adap_idx = adap_idx;
6132         adapter->msg_enable = DFLT_MSG_ENABLE;
6133         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
6134                                     (sizeof(struct mbox_cmd) *
6135                                      T4_OS_LOG_MBOX_CMDS),
6136                                     GFP_KERNEL);
6137         if (!adapter->mbox_log) {
6138                 err = -ENOMEM;
6139                 goto out_free_adapter;
6140         }
6141         spin_lock_init(&adapter->mbox_lock);
6142         INIT_LIST_HEAD(&adapter->mlist.list);
6143         adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
6144         pci_set_drvdata(pdev, adapter);
6145
6146         if (func != ent->driver_data) {
6147                 pci_disable_device(pdev);
6148                 pci_save_state(pdev);        /* to restore SR-IOV later */
6149                 return 0;
6150         }
6151
6152         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6153                 highdma = true;
6154                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6155                 if (err) {
6156                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6157                                 "coherent allocations\n");
6158                         goto out_free_adapter;
6159                 }
6160         } else {
6161                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6162                 if (err) {
6163                         dev_err(&pdev->dev, "no usable DMA configuration\n");
6164                         goto out_free_adapter;
6165                 }
6166         }
6167
6168         pci_enable_pcie_error_reporting(pdev);
6169         pci_set_master(pdev);
6170         pci_save_state(pdev);
6171         adap_idx++;
6172         adapter->workq = create_singlethread_workqueue("cxgb4");
6173         if (!adapter->workq) {
6174                 err = -ENOMEM;
6175                 goto out_free_adapter;
6176         }
6177
6178         /* PCI device has been enabled */
6179         adapter->flags |= CXGB4_DEV_ENABLED;
6180         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6181
6182         /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
6183          * Ingress Packet Data to Free List Buffers in order to allow for
6184          * chipset performance optimizations between the Root Complex and
6185          * Memory Controllers.  (Messages to the associated Ingress Queue
6186          * notifying new Packet Placement in the Free Lists Buffers will be
6187          * send without the Relaxed Ordering Attribute thus guaranteeing that
6188          * all preceding PCIe Transaction Layer Packets will be processed
6189          * first.)  But some Root Complexes have various issues with Upstream
6190          * Transaction Layer Packets with the Relaxed Ordering Attribute set.
6191          * The PCIe devices which under the Root Complexes will be cleared the
6192          * Relaxed Ordering bit in the configuration space, So we check our
6193          * PCIe configuration space to see if it's flagged with advice against
6194          * using Relaxed Ordering.
6195          */
6196         if (!pcie_relaxed_ordering_enabled(pdev))
6197                 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
6198
6199         spin_lock_init(&adapter->stats_lock);
6200         spin_lock_init(&adapter->tid_release_lock);
6201         spin_lock_init(&adapter->win0_lock);
6202
6203         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6204         INIT_WORK(&adapter->db_full_task, process_db_full);
6205         INIT_WORK(&adapter->db_drop_task, process_db_drop);
6206         INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
6207
6208         err = t4_prep_adapter(adapter);
6209         if (err)
6210                 goto out_free_adapter;
6211
6212         if (is_kdump_kernel()) {
6213                 /* Collect hardware state and append to /proc/vmcore */
6214                 err = cxgb4_cudbg_vmcore_add_dump(adapter);
6215                 if (err) {
6216                         dev_warn(adapter->pdev_dev,
6217                                  "Fail collecting vmcore device dump, err: %d. Continuing\n",
6218                                  err);
6219                         err = 0;
6220                 }
6221         }
6222
6223         if (!is_t4(adapter->params.chip)) {
6224                 s_qpp = (QUEUESPERPAGEPF0_S +
6225                         (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
6226                         adapter->pf);
6227                 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
6228                       SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
6229                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6230
6231                 /* Each segment size is 128B. Write coalescing is enabled only
6232                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6233                  * queue is less no of segments that can be accommodated in
6234                  * a page size.
6235                  */
6236                 if (qpp > num_seg) {
6237                         dev_err(&pdev->dev,
6238                                 "Incorrect number of egress queues per page\n");
6239                         err = -EINVAL;
6240                         goto out_free_adapter;
6241                 }
6242                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6243                 pci_resource_len(pdev, 2));
6244                 if (!adapter->bar2) {
6245                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
6246                         err = -ENOMEM;
6247                         goto out_free_adapter;
6248                 }
6249         }
6250
6251         setup_memwin(adapter);
6252         err = adap_init0(adapter, 0);
6253 #ifdef CONFIG_DEBUG_FS
6254         bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
6255 #endif
6256         setup_memwin_rdma(adapter);
6257         if (err)
6258                 goto out_unmap_bar;
6259
6260         /* configure SGE_STAT_CFG_A to read WC stats */
6261         if (!is_t4(adapter->params.chip))
6262                 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
6263                              (is_t5(adapter->params.chip) ? STATMODE_V(0) :
6264                               T6_STATMODE_V(0)));
6265
6266         /* Initialize hash mac addr list */
6267         INIT_LIST_HEAD(&adapter->mac_hlist);
6268
6269         for_each_port(adapter, i) {
6270                 /* For supporting MQPRIO Offload, need some extra
6271                  * queues for each ETHOFLD TIDs. Keep it equal to
6272                  * MAX_ATIDs for now. Once we connect to firmware
6273                  * later and query the EOTID params, we'll come to
6274                  * know the actual # of EOTIDs supported.
6275                  */
6276                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6277                                            MAX_ETH_QSETS + MAX_ATIDS);
6278                 if (!netdev) {
6279                         err = -ENOMEM;
6280                         goto out_free_dev;
6281                 }
6282
6283                 SET_NETDEV_DEV(netdev, &pdev->dev);
6284
6285                 adapter->port[i] = netdev;
6286                 pi = netdev_priv(netdev);
6287                 pi->adapter = adapter;
6288                 pi->xact_addr_filt = -1;
6289                 pi->port_id = i;
6290                 netdev->irq = pdev->irq;
6291
6292                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6293                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6294                         NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO |
6295                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
6296                         NETIF_F_HW_TC;
6297
6298                 if (chip_ver > CHELSIO_T5) {
6299                         netdev->hw_enc_features |= NETIF_F_IP_CSUM |
6300                                                    NETIF_F_IPV6_CSUM |
6301                                                    NETIF_F_RXCSUM |
6302                                                    NETIF_F_GSO_UDP_TUNNEL |
6303                                                    NETIF_F_GSO_UDP_TUNNEL_CSUM |
6304                                                    NETIF_F_TSO | NETIF_F_TSO6;
6305
6306                         netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
6307                                                NETIF_F_GSO_UDP_TUNNEL_CSUM |
6308                                                NETIF_F_HW_TLS_RECORD;
6309                 }
6310
6311                 if (highdma)
6312                         netdev->hw_features |= NETIF_F_HIGHDMA;
6313                 netdev->features |= netdev->hw_features;
6314                 netdev->vlan_features = netdev->features & VLAN_FEAT;
6315
6316                 netdev->priv_flags |= IFF_UNICAST_FLT;
6317
6318                 /* MTU range: 81 - 9600 */
6319                 netdev->min_mtu = 81;              /* accommodate SACK */
6320                 netdev->max_mtu = MAX_MTU;
6321
6322                 netdev->netdev_ops = &cxgb4_netdev_ops;
6323 #ifdef CONFIG_CHELSIO_T4_DCB
6324                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6325                 cxgb4_dcb_state_init(netdev);
6326                 cxgb4_dcb_version_init(netdev);
6327 #endif
6328                 cxgb4_set_ethtool_ops(netdev);
6329         }
6330
6331         cxgb4_init_ethtool_dump(adapter);
6332
6333         pci_set_drvdata(pdev, adapter);
6334
6335         if (adapter->flags & CXGB4_FW_OK) {
6336                 err = t4_port_init(adapter, func, func, 0);
6337                 if (err)
6338                         goto out_free_dev;
6339         } else if (adapter->params.nports == 1) {
6340                 /* If we don't have a connection to the firmware -- possibly
6341                  * because of an error -- grab the raw VPD parameters so we
6342                  * can set the proper MAC Address on the debug network
6343                  * interface that we've created.
6344                  */
6345                 u8 hw_addr[ETH_ALEN];
6346                 u8 *na = adapter->params.vpd.na;
6347
6348                 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
6349                 if (!err) {
6350                         for (i = 0; i < ETH_ALEN; i++)
6351                                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
6352                                               hex2val(na[2 * i + 1]));
6353                         t4_set_hw_addr(adapter, 0, hw_addr);
6354                 }
6355         }
6356
6357         if (!(adapter->flags & CXGB4_FW_OK))
6358                 goto fw_attach_fail;
6359
6360         /* Configure queues and allocate tables now, they can be needed as
6361          * soon as the first register_netdev completes.
6362          */
6363         err = cfg_queues(adapter);
6364         if (err)
6365                 goto out_free_dev;
6366
6367         adapter->smt = t4_init_smt();
6368         if (!adapter->smt) {
6369                 /* We tolerate a lack of SMT, giving up some functionality */
6370                 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
6371         }
6372
6373         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
6374         if (!adapter->l2t) {
6375                 /* We tolerate a lack of L2T, giving up some functionality */
6376                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6377                 adapter->params.offload = 0;
6378         }
6379
6380 #if IS_ENABLED(CONFIG_IPV6)
6381         if (chip_ver <= CHELSIO_T5 &&
6382             (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
6383                 /* CLIP functionality is not present in hardware,
6384                  * hence disable all offload features
6385                  */
6386                 dev_warn(&pdev->dev,
6387                          "CLIP not enabled in hardware, continuing\n");
6388                 adapter->params.offload = 0;
6389         } else {
6390                 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
6391                                                   adapter->clipt_end);
6392                 if (!adapter->clipt) {
6393                         /* We tolerate a lack of clip_table, giving up
6394                          * some functionality
6395                          */
6396                         dev_warn(&pdev->dev,
6397                                  "could not allocate Clip table, continuing\n");
6398                         adapter->params.offload = 0;
6399                 }
6400         }
6401 #endif
6402
6403         for_each_port(adapter, i) {
6404                 pi = adap2pinfo(adapter, i);
6405                 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
6406                 if (!pi->sched_tbl)
6407                         dev_warn(&pdev->dev,
6408                                  "could not activate scheduling on port %d\n",
6409                                  i);
6410         }
6411
6412         if (tid_init(&adapter->tids) < 0) {
6413                 dev_warn(&pdev->dev, "could not allocate TID table, "
6414                          "continuing\n");
6415                 adapter->params.offload = 0;
6416         } else {
6417                 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
6418                 if (!adapter->tc_u32)
6419                         dev_warn(&pdev->dev,
6420                                  "could not offload tc u32, continuing\n");
6421
6422                 if (cxgb4_init_tc_flower(adapter))
6423                         dev_warn(&pdev->dev,
6424                                  "could not offload tc flower, continuing\n");
6425
6426                 if (cxgb4_init_tc_mqprio(adapter))
6427                         dev_warn(&pdev->dev,
6428                                  "could not offload tc mqprio, continuing\n");
6429
6430                 if (cxgb4_init_tc_matchall(adapter))
6431                         dev_warn(&pdev->dev,
6432                                  "could not offload tc matchall, continuing\n");
6433         }
6434
6435         if (is_offload(adapter) || is_hashfilter(adapter)) {
6436                 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
6437                         u32 hash_base, hash_reg;
6438
6439                         if (chip_ver <= CHELSIO_T5) {
6440                                 hash_reg = LE_DB_TID_HASHBASE_A;
6441                                 hash_base = t4_read_reg(adapter, hash_reg);
6442                                 adapter->tids.hash_base = hash_base / 4;
6443                         } else {
6444                                 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
6445                                 hash_base = t4_read_reg(adapter, hash_reg);
6446                                 adapter->tids.hash_base = hash_base;
6447                         }
6448                 }
6449         }
6450
6451         /* See what interrupts we'll be using */
6452         if (msi > 1 && enable_msix(adapter) == 0)
6453                 adapter->flags |= CXGB4_USING_MSIX;
6454         else if (msi > 0 && pci_enable_msi(pdev) == 0) {
6455                 adapter->flags |= CXGB4_USING_MSI;
6456                 if (msi > 1)
6457                         free_msix_info(adapter);
6458         }
6459
6460         /* check for PCI Express bandwidth capabiltites */
6461         pcie_print_link_status(pdev);
6462
6463         cxgb4_init_mps_ref_entries(adapter);
6464
6465         err = init_rss(adapter);
6466         if (err)
6467                 goto out_free_dev;
6468
6469         err = setup_non_data_intr(adapter);
6470         if (err) {
6471                 dev_err(adapter->pdev_dev,
6472                         "Non Data interrupt allocation failed, err: %d\n", err);
6473                 goto out_free_dev;
6474         }
6475
6476         err = setup_fw_sge_queues(adapter);
6477         if (err) {
6478                 dev_err(adapter->pdev_dev,
6479                         "FW sge queue allocation failed, err %d", err);
6480                 goto out_free_dev;
6481         }
6482
6483 fw_attach_fail:
6484         /*
6485          * The card is now ready to go.  If any errors occur during device
6486          * registration we do not fail the whole card but rather proceed only
6487          * with the ports we manage to register successfully.  However we must
6488          * register at least one net device.
6489          */
6490         for_each_port(adapter, i) {
6491                 pi = adap2pinfo(adapter, i);
6492                 adapter->port[i]->dev_port = pi->lport;
6493                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6494                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6495
6496                 netif_carrier_off(adapter->port[i]);
6497
6498                 err = register_netdev(adapter->port[i]);
6499                 if (err)
6500                         break;
6501                 adapter->chan_map[pi->tx_chan] = i;
6502                 print_port_info(adapter->port[i]);
6503         }
6504         if (i == 0) {
6505                 dev_err(&pdev->dev, "could not register any net devices\n");
6506                 goto out_free_dev;
6507         }
6508         if (err) {
6509                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6510                 err = 0;
6511         }
6512
6513         if (cxgb4_debugfs_root) {
6514                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6515                                                            cxgb4_debugfs_root);
6516                 setup_debugfs(adapter);
6517         }
6518
6519         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6520         pdev->needs_freset = 1;
6521
6522         if (is_uld(adapter)) {
6523                 mutex_lock(&uld_mutex);
6524                 list_add_tail(&adapter->list_node, &adapter_list);
6525                 mutex_unlock(&uld_mutex);
6526         }
6527
6528         if (!is_t4(adapter->params.chip))
6529                 cxgb4_ptp_init(adapter);
6530
6531         if (IS_REACHABLE(CONFIG_THERMAL) &&
6532             !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK))
6533                 cxgb4_thermal_init(adapter);
6534
6535         print_adapter_info(adapter);
6536         return 0;
6537
6538  out_free_dev:
6539         t4_free_sge_resources(adapter);
6540         free_some_resources(adapter);
6541         if (adapter->flags & CXGB4_USING_MSIX)
6542                 free_msix_info(adapter);
6543         if (adapter->num_uld || adapter->num_ofld_uld)
6544                 t4_uld_mem_free(adapter);
6545  out_unmap_bar:
6546         if (!is_t4(adapter->params.chip))
6547                 iounmap(adapter->bar2);
6548  out_free_adapter:
6549         if (adapter->workq)
6550                 destroy_workqueue(adapter->workq);
6551
6552         kfree(adapter->mbox_log);
6553         kfree(adapter);
6554  out_unmap_bar0:
6555         iounmap(regs);
6556  out_disable_device:
6557         pci_disable_pcie_error_reporting(pdev);
6558         pci_disable_device(pdev);
6559  out_release_regions:
6560         pci_release_regions(pdev);
6561         return err;
6562 }
6563
6564 static void remove_one(struct pci_dev *pdev)
6565 {
6566         struct adapter *adapter = pci_get_drvdata(pdev);
6567         struct hash_mac_addr *entry, *tmp;
6568
6569         if (!adapter) {
6570                 pci_release_regions(pdev);
6571                 return;
6572         }
6573
6574         /* If we allocated filters, free up state associated with any
6575          * valid filters ...
6576          */
6577         clear_all_filters(adapter);
6578
6579         adapter->flags |= CXGB4_SHUTTING_DOWN;
6580
6581         if (adapter->pf == 4) {
6582                 int i;
6583
6584                 /* Tear down per-adapter Work Queue first since it can contain
6585                  * references to our adapter data structure.
6586                  */
6587                 destroy_workqueue(adapter->workq);
6588
6589                 if (is_uld(adapter)) {
6590                         detach_ulds(adapter);
6591                         t4_uld_clean_up(adapter);
6592                 }
6593
6594                 adap_free_hma_mem(adapter);
6595
6596                 disable_interrupts(adapter);
6597
6598                 cxgb4_free_mps_ref_entries(adapter);
6599
6600                 for_each_port(adapter, i)
6601                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6602                                 unregister_netdev(adapter->port[i]);
6603
6604                 debugfs_remove_recursive(adapter->debugfs_root);
6605
6606                 if (!is_t4(adapter->params.chip))
6607                         cxgb4_ptp_stop(adapter);
6608                 if (IS_REACHABLE(CONFIG_THERMAL))
6609                         cxgb4_thermal_remove(adapter);
6610
6611                 if (adapter->flags & CXGB4_FULL_INIT_DONE)
6612                         cxgb_down(adapter);
6613
6614                 if (adapter->flags & CXGB4_USING_MSIX)
6615                         free_msix_info(adapter);
6616                 if (adapter->num_uld || adapter->num_ofld_uld)
6617                         t4_uld_mem_free(adapter);
6618                 free_some_resources(adapter);
6619                 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
6620                                          list) {
6621                         list_del(&entry->list);
6622                         kfree(entry);
6623                 }
6624
6625 #if IS_ENABLED(CONFIG_IPV6)
6626                 t4_cleanup_clip_tbl(adapter);
6627 #endif
6628                 if (!is_t4(adapter->params.chip))
6629                         iounmap(adapter->bar2);
6630         }
6631 #ifdef CONFIG_PCI_IOV
6632         else {
6633                 cxgb4_iov_configure(adapter->pdev, 0);
6634         }
6635 #endif
6636         iounmap(adapter->regs);
6637         pci_disable_pcie_error_reporting(pdev);
6638         if ((adapter->flags & CXGB4_DEV_ENABLED)) {
6639                 pci_disable_device(pdev);
6640                 adapter->flags &= ~CXGB4_DEV_ENABLED;
6641         }
6642         pci_release_regions(pdev);
6643         kfree(adapter->mbox_log);
6644         synchronize_rcu();
6645         kfree(adapter);
6646 }
6647
6648 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
6649  * delivery.  This is essentially a stripped down version of the PCI remove()
6650  * function where we do the minimal amount of work necessary to shutdown any
6651  * further activity.
6652  */
6653 static void shutdown_one(struct pci_dev *pdev)
6654 {
6655         struct adapter *adapter = pci_get_drvdata(pdev);
6656
6657         /* As with remove_one() above (see extended comment), we only want do
6658          * do cleanup on PCI Devices which went all the way through init_one()
6659          * ...
6660          */
6661         if (!adapter) {
6662                 pci_release_regions(pdev);
6663                 return;
6664         }
6665
6666         adapter->flags |= CXGB4_SHUTTING_DOWN;
6667
6668         if (adapter->pf == 4) {
6669                 int i;
6670
6671                 for_each_port(adapter, i)
6672                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6673                                 cxgb_close(adapter->port[i]);
6674
6675                 rtnl_lock();
6676                 cxgb4_mqprio_stop_offload(adapter);
6677                 rtnl_unlock();
6678
6679                 if (is_uld(adapter)) {
6680                         detach_ulds(adapter);
6681                         t4_uld_clean_up(adapter);
6682                 }
6683
6684                 disable_interrupts(adapter);
6685                 disable_msi(adapter);
6686
6687                 t4_sge_stop(adapter);
6688                 if (adapter->flags & CXGB4_FW_OK)
6689                         t4_fw_bye(adapter, adapter->mbox);
6690         }
6691 }
6692
6693 static struct pci_driver cxgb4_driver = {
6694         .name     = KBUILD_MODNAME,
6695         .id_table = cxgb4_pci_tbl,
6696         .probe    = init_one,
6697         .remove   = remove_one,
6698         .shutdown = shutdown_one,
6699 #ifdef CONFIG_PCI_IOV
6700         .sriov_configure = cxgb4_iov_configure,
6701 #endif
6702         .err_handler = &cxgb4_eeh,
6703 };
6704
6705 static int __init cxgb4_init_module(void)
6706 {
6707         int ret;
6708
6709         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6710
6711         ret = pci_register_driver(&cxgb4_driver);
6712         if (ret < 0)
6713                 goto err_pci;
6714
6715 #if IS_ENABLED(CONFIG_IPV6)
6716         if (!inet6addr_registered) {
6717                 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6718                 if (ret)
6719                         pci_unregister_driver(&cxgb4_driver);
6720                 else
6721                         inet6addr_registered = true;
6722         }
6723 #endif
6724
6725         if (ret == 0)
6726                 return ret;
6727
6728 err_pci:
6729         debugfs_remove(cxgb4_debugfs_root);
6730
6731         return ret;
6732 }
6733
6734 static void __exit cxgb4_cleanup_module(void)
6735 {
6736 #if IS_ENABLED(CONFIG_IPV6)
6737         if (inet6addr_registered) {
6738                 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6739                 inet6addr_registered = false;
6740         }
6741 #endif
6742         pci_unregister_driver(&cxgb4_driver);
6743         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6744 }
6745
6746 module_init(cxgb4_init_module);
6747 module_exit(cxgb4_cleanup_module);