2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/etherdevice.h>
50 #include <linux/net_tstamp.h>
52 #include "t4_chip_type.h"
53 #include "cxgb4_uld.h"
55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
56 extern struct list_head adapter_list;
57 extern struct mutex uld_mutex;
60 MAX_NPORTS = 4, /* max # of ports */
61 SERNUM_LEN = 24, /* Serial # length */
62 EC_LEN = 16, /* E/C length */
63 ID_LEN = 16, /* ID length */
64 PN_LEN = 16, /* Part Number length */
65 MACADDR_LEN = 12, /* MAC Address length */
69 T4_REGMAP_SIZE = (160 * 1024),
70 T5_REGMAP_SIZE = (332 * 1024),
82 MEMWIN0_APERTURE = 2048,
83 MEMWIN0_BASE = 0x1b800,
84 MEMWIN1_APERTURE = 32768,
85 MEMWIN1_BASE = 0x28000,
86 MEMWIN1_BASE_T5 = 0x52000,
87 MEMWIN2_APERTURE = 65536,
88 MEMWIN2_BASE = 0x30000,
89 MEMWIN2_APERTURE_T5 = 131072,
90 MEMWIN2_BASE_T5 = 0x60000,
108 PAUSE_AUTONEG = 1 << 2
112 u64 tx_octets; /* total # of octets in good frames */
113 u64 tx_frames; /* all good frames */
114 u64 tx_bcast_frames; /* all broadcast frames */
115 u64 tx_mcast_frames; /* all multicast frames */
116 u64 tx_ucast_frames; /* all unicast frames */
117 u64 tx_error_frames; /* all error frames */
119 u64 tx_frames_64; /* # of Tx frames in a particular range */
120 u64 tx_frames_65_127;
121 u64 tx_frames_128_255;
122 u64 tx_frames_256_511;
123 u64 tx_frames_512_1023;
124 u64 tx_frames_1024_1518;
125 u64 tx_frames_1519_max;
127 u64 tx_drop; /* # of dropped Tx frames */
128 u64 tx_pause; /* # of transmitted pause frames */
129 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
130 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
131 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
132 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
133 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
134 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
135 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
136 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
138 u64 rx_octets; /* total # of octets in good frames */
139 u64 rx_frames; /* all good frames */
140 u64 rx_bcast_frames; /* all broadcast frames */
141 u64 rx_mcast_frames; /* all multicast frames */
142 u64 rx_ucast_frames; /* all unicast frames */
143 u64 rx_too_long; /* # of frames exceeding MTU */
144 u64 rx_jabber; /* # of jabber frames */
145 u64 rx_fcs_err; /* # of received frames with bad FCS */
146 u64 rx_len_err; /* # of received frames with length error */
147 u64 rx_symbol_err; /* symbol errors */
148 u64 rx_runt; /* # of short frames */
150 u64 rx_frames_64; /* # of Rx frames in a particular range */
151 u64 rx_frames_65_127;
152 u64 rx_frames_128_255;
153 u64 rx_frames_256_511;
154 u64 rx_frames_512_1023;
155 u64 rx_frames_1024_1518;
156 u64 rx_frames_1519_max;
158 u64 rx_pause; /* # of received pause frames */
159 u64 rx_ppp0; /* # of received PPP prio 0 frames */
160 u64 rx_ppp1; /* # of received PPP prio 1 frames */
161 u64 rx_ppp2; /* # of received PPP prio 2 frames */
162 u64 rx_ppp3; /* # of received PPP prio 3 frames */
163 u64 rx_ppp4; /* # of received PPP prio 4 frames */
164 u64 rx_ppp5; /* # of received PPP prio 5 frames */
165 u64 rx_ppp6; /* # of received PPP prio 6 frames */
166 u64 rx_ppp7; /* # of received PPP prio 7 frames */
168 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
169 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
170 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
171 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
172 u64 rx_trunc0; /* buffer-group 0 truncated packets */
173 u64 rx_trunc1; /* buffer-group 1 truncated packets */
174 u64 rx_trunc2; /* buffer-group 2 truncated packets */
175 u64 rx_trunc3; /* buffer-group 3 truncated packets */
178 struct lb_port_stats {
191 u64 frames_1024_1518;
206 struct tp_tcp_stats {
210 u64 tcp_retrans_segs;
213 struct tp_usm_stats {
219 struct tp_fcoe_stats {
225 struct tp_err_stats {
229 u32 tnl_cong_drops[4];
230 u32 ofld_chan_drops[4];
232 u32 ofld_vlan_drops[4];
238 struct tp_cpl_stats {
243 struct tp_rdma_stats {
249 u32 hps; /* host page size for our PF/VF */
250 u32 eq_qpp; /* egress queues/page for our PF/VF */
251 u32 iq_qpp; /* egress queues/page for our PF/VF */
255 unsigned int tre; /* log2 of core clocks per TP tick */
256 unsigned int la_mask; /* what events are recorded by TP LA */
257 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
260 uint32_t dack_re; /* DACK timer resolution */
261 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
263 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
264 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
266 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
267 * subset of the set of fields which may be present in the Compressed
268 * Filter Tuple portion of filters and TCP TCB connections. The
269 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
270 * Since a variable number of fields may or may not be present, their
271 * shifted field positions within the Compressed Filter Tuple may
272 * vary, or not even be present if the field isn't selected in
273 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
274 * places we store their offsets here, or a -1 if the field isn't
286 u8 sn[SERNUM_LEN + 1];
289 u8 na[MACADDR_LEN + 1];
297 struct devlog_params {
298 u32 memtype; /* which memory (EDC0, EDC1, MC) */
299 u32 start; /* start of log in firmware memory */
300 u32 size; /* size of log */
303 /* Stores chip specific parameters */
304 struct arch_specific_params {
307 u8 cng_ch_bits_log; /* congestion channel map bits width */
314 struct adapter_params {
315 struct sge_params sge;
317 struct vpd_params vpd;
318 struct pci_params pci;
319 struct devlog_params devlog;
320 enum pcie_memwin drv_memwin;
322 unsigned int cim_la_size;
324 unsigned int sf_size; /* serial flash size in bytes */
325 unsigned int sf_nsec; /* # of flash sectors */
326 unsigned int sf_fw_start; /* start of FW image in flash */
328 unsigned int fw_vers;
329 unsigned int bs_vers; /* bootstrap version */
330 unsigned int tp_vers;
331 unsigned int er_vers; /* expansion ROM version */
334 unsigned short mtus[NMTUS];
335 unsigned short a_wnd[NCCTRL_WIN];
336 unsigned short b_wnd[NCCTRL_WIN];
338 unsigned char nports; /* # of ethernet ports */
339 unsigned char portvec;
340 enum chip_type chip; /* chip code */
341 struct arch_specific_params arch; /* chip specific params */
342 unsigned char offload;
343 unsigned char crypto; /* HW capability for crypto */
345 unsigned char bypass;
347 unsigned int ofldq_wr_cred;
348 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
350 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
351 unsigned int max_ird_adapter; /* Max read depth per adapter */
352 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
355 /* State needed to monitor the forward progress of SGE Ingress DMA activities
356 * and possible hangs.
358 struct sge_idma_monitor_state {
359 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
360 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
361 unsigned int idma_state[2]; /* IDMA Hang detect state */
362 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
363 unsigned int idma_warn[2]; /* time to warning in HZ */
366 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
367 * The access and execute times are signed in order to accommodate negative
371 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
372 u64 timestamp; /* OS-dependent timestamp */
373 u32 seqno; /* sequence number */
374 s16 access; /* time (ms) to access mailbox */
375 s16 execute; /* time (ms) to execute */
378 struct mbox_cmd_log {
379 unsigned int size; /* number of entries in the log */
380 unsigned int cursor; /* next position in the log to write */
381 u32 seqno; /* next sequence number */
382 /* variable length mailbox command log starts here */
385 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
386 * return a pointer to the specified entry.
388 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
389 unsigned int entry_idx)
391 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
394 #include "t4fw_api.h"
396 #define FW_VERSION(chip) ( \
397 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
398 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
399 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
400 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
401 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
407 struct fw_hdr fw_hdr;
410 struct trace_params {
411 u32 data[TRACE_LEN / 4];
412 u32 mask[TRACE_LEN / 4];
413 unsigned short snap_len;
414 unsigned short min_len;
415 unsigned char skip_ofst;
416 unsigned char skip_len;
417 unsigned char invert;
422 unsigned short supported; /* link capabilities */
423 unsigned short advertising; /* advertised capabilities */
424 unsigned short lp_advertising; /* peer advertised capabilities */
425 unsigned short requested_speed; /* speed user has requested */
426 unsigned short speed; /* actual link speed */
427 unsigned char requested_fc; /* flow control user has requested */
428 unsigned char fc; /* actual link flow control */
429 unsigned char autoneg; /* autonegotiating? */
430 unsigned char link_ok; /* link up? */
431 unsigned char link_down_rc; /* link down reason */
434 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
437 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
438 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
439 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
440 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
441 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
443 /* # of streaming iSCSIT Rx queues */
444 MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS,
448 MAX_TXQ_ENTRIES = 16384,
449 MAX_CTRL_TXQ_ENTRIES = 1024,
450 MAX_RSPQ_ENTRIES = 16384,
451 MAX_RX_BUFFERS = 16384,
452 MIN_TXQ_ENTRIES = 32,
453 MIN_CTRL_TXQ_ENTRIES = 32,
454 MIN_RSPQ_ENTRIES = 128,
459 INGQ_EXTRAS = 2, /* firmware event queue and */
460 /* forwarded interrupts */
461 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES +
462 MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS,
468 #include "cxgb4_dcb.h"
470 #ifdef CONFIG_CHELSIO_T4_FCOE
471 #include "cxgb4_fcoe.h"
472 #endif /* CONFIG_CHELSIO_T4_FCOE */
475 struct adapter *adapter;
477 s16 xact_addr_filt; /* index of exact MAC address filter */
478 u16 rss_size; /* size of VI's RSS table slice */
480 enum fw_port_type port_type;
484 u8 lport; /* associated offload logical port */
485 u8 nqsets; /* # of qsets */
486 u8 first_qset; /* index of first qset */
488 struct link_config link_cfg;
490 struct port_stats stats_base;
491 #ifdef CONFIG_CHELSIO_T4_DCB
492 struct port_dcb_info dcb; /* Data Center Bridging support */
494 #ifdef CONFIG_CHELSIO_T4_FCOE
495 struct cxgb_fcoe fcoe;
496 #endif /* CONFIG_CHELSIO_T4_FCOE */
497 bool rxtstamp; /* Enable TS */
498 struct hwtstamp_config tstamp_config;
504 enum { /* adapter flags */
505 FULL_INIT_DONE = (1 << 0),
506 DEV_ENABLED = (1 << 1),
507 USING_MSI = (1 << 2),
508 USING_MSIX = (1 << 3),
510 RSS_TNLALLLOOKUP = (1 << 5),
511 USING_SOFT_PARAMS = (1 << 6),
512 MASTER_PF = (1 << 7),
513 FW_OFLD_CONN = (1 << 9),
517 ULP_CRYPTO_LOOKASIDE = 1 << 0,
522 struct sge_fl { /* SGE free-buffer queue state */
523 unsigned int avail; /* # of available Rx buffers */
524 unsigned int pend_cred; /* new buffers since last FL DB ring */
525 unsigned int cidx; /* consumer index */
526 unsigned int pidx; /* producer index */
527 unsigned long alloc_failed; /* # of times buffer allocation failed */
528 unsigned long large_alloc_failed;
529 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
530 unsigned long low; /* # of times momentarily starving */
531 unsigned long starving;
533 unsigned int cntxt_id; /* SGE context id for the free list */
534 unsigned int size; /* capacity of free list */
535 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
536 __be64 *desc; /* address of HW Rx descriptor ring */
537 dma_addr_t addr; /* bus address of HW ring start */
538 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
539 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
542 /* A packet gather list */
544 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
545 struct page_frag frags[MAX_SKB_FRAGS];
546 void *va; /* virtual address of first byte */
547 unsigned int nfrags; /* # of fragments */
548 unsigned int tot_len; /* total length of fragments */
551 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
552 const struct pkt_gl *gl);
553 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
554 /* LRO related declarations for ULD */
556 #define MAX_LRO_SESSIONS 64
557 u8 lro_session_cnt; /* # of sessions to aggregate */
558 unsigned long lro_pkts; /* # of LRO super packets */
559 unsigned long lro_merged; /* # of wire packets merged by LRO */
560 struct sk_buff_head lroq; /* list of aggregated sessions */
563 struct sge_rspq { /* state for an SGE response queue */
564 struct napi_struct napi;
565 const __be64 *cur_desc; /* current descriptor in queue */
566 unsigned int cidx; /* consumer index */
567 u8 gen; /* current generation bit */
568 u8 intr_params; /* interrupt holdoff parameters */
569 u8 next_intr_params; /* holdoff params for next interrupt */
571 u8 pktcnt_idx; /* interrupt packet threshold */
572 u8 uld; /* ULD handling this queue */
573 u8 idx; /* queue index within its group */
574 int offset; /* offset into current Rx buffer */
575 u16 cntxt_id; /* SGE context id for the response q */
576 u16 abs_id; /* absolute SGE id for the response q */
577 __be64 *desc; /* address of HW response ring */
578 dma_addr_t phys_addr; /* physical address of the ring */
579 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
580 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
581 unsigned int iqe_len; /* entry size */
582 unsigned int size; /* capacity of response queue */
583 struct adapter *adap;
584 struct net_device *netdev; /* associated net device */
585 rspq_handler_t handler;
586 rspq_flush_handler_t flush_handler;
587 struct t4_lro_mgr lro_mgr;
588 #ifdef CONFIG_NET_RX_BUSY_POLL
589 #define CXGB_POLL_STATE_IDLE 0
590 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
591 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
592 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
593 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
594 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
595 CXGB_POLL_STATE_POLL_YIELD)
596 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
597 CXGB_POLL_STATE_POLL)
598 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
599 CXGB_POLL_STATE_POLL_YIELD)
600 unsigned int bpoll_state;
601 spinlock_t bpoll_lock; /* lock for busy poll */
602 #endif /* CONFIG_NET_RX_BUSY_POLL */
606 struct sge_eth_stats { /* Ethernet queue statistics */
607 unsigned long pkts; /* # of ethernet packets */
608 unsigned long lro_pkts; /* # of LRO super packets */
609 unsigned long lro_merged; /* # of wire packets merged by LRO */
610 unsigned long rx_cso; /* # of Rx checksum offloads */
611 unsigned long vlan_ex; /* # of Rx VLAN extractions */
612 unsigned long rx_drops; /* # of packets dropped due to no mem */
615 struct sge_eth_rxq { /* SW Ethernet Rx queue */
616 struct sge_rspq rspq;
618 struct sge_eth_stats stats;
619 } ____cacheline_aligned_in_smp;
621 struct sge_ofld_stats { /* offload queue statistics */
622 unsigned long pkts; /* # of packets */
623 unsigned long imm; /* # of immediate-data packets */
624 unsigned long an; /* # of asynchronous notifications */
625 unsigned long nomem; /* # of responses deferred due to no mem */
628 struct sge_ofld_rxq { /* SW offload Rx queue */
629 struct sge_rspq rspq;
631 struct sge_ofld_stats stats;
632 } ____cacheline_aligned_in_smp;
641 unsigned int in_use; /* # of in-use Tx descriptors */
642 unsigned int size; /* # of descriptors */
643 unsigned int cidx; /* SW consumer index */
644 unsigned int pidx; /* producer index */
645 unsigned long stops; /* # of times q has been stopped */
646 unsigned long restarts; /* # of queue restarts */
647 unsigned int cntxt_id; /* SGE context id for the Tx q */
648 struct tx_desc *desc; /* address of HW Tx descriptor ring */
649 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
650 struct sge_qstat *stat; /* queue status entry */
651 dma_addr_t phys_addr; /* physical address of the ring */
654 unsigned short db_pidx;
655 unsigned short db_pidx_inc;
656 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
657 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
660 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
662 struct netdev_queue *txq; /* associated netdev TX queue */
663 #ifdef CONFIG_CHELSIO_T4_DCB
664 u8 dcb_prio; /* DCB Priority bound to queue */
666 unsigned long tso; /* # of TSO requests */
667 unsigned long tx_cso; /* # of Tx checksum offloads */
668 unsigned long vlan_ins; /* # of Tx VLAN insertions */
669 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
670 } ____cacheline_aligned_in_smp;
672 struct sge_ofld_txq { /* state for an SGE offload Tx queue */
674 struct adapter *adap;
675 struct sk_buff_head sendq; /* list of backpressured packets */
676 struct tasklet_struct qresume_tsk; /* restarts the queue */
677 bool service_ofldq_running; /* service_ofldq() is processing sendq */
678 u8 full; /* the Tx ring is full */
679 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
680 } ____cacheline_aligned_in_smp;
682 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
684 struct adapter *adap;
685 struct sk_buff_head sendq; /* list of backpressured packets */
686 struct tasklet_struct qresume_tsk; /* restarts the queue */
687 u8 full; /* the Tx ring is full */
688 } ____cacheline_aligned_in_smp;
690 struct sge_uld_rxq_info {
691 char name[IFNAMSIZ]; /* name of ULD driver */
692 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
693 u16 *msix_tbl; /* msix_tbl for uld */
694 u16 *rspq_id; /* response queue id's of rxq */
695 u16 nrxq; /* # of ingress uld queues */
696 u16 nciq; /* # of completion queues */
697 u8 uld; /* uld type */
701 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
702 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
703 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
705 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
706 struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS];
707 struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES];
708 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
709 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
710 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
711 struct sge_uld_rxq_info **uld_rxq_info;
713 struct sge_rspq intrq ____cacheline_aligned_in_smp;
714 spinlock_t intrq_lock;
716 u16 max_ethqsets; /* # of available Ethernet queue sets */
717 u16 ethqsets; /* # of active Ethernet queue sets */
718 u16 ethtxq_rover; /* Tx queue to clean up next */
719 u16 iscsiqsets; /* # of active iSCSI queue sets */
720 u16 niscsitq; /* # of available iSCST Rx queues */
721 u16 rdmaqs; /* # of available RDMA Rx queues */
722 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
723 u16 nqs_per_uld; /* # of Rx queues per ULD */
724 u16 iscsi_rxq[MAX_OFLD_QSETS];
725 u16 iscsit_rxq[MAX_ISCSIT_QUEUES];
726 u16 rdma_rxq[MAX_RDMA_QUEUES];
727 u16 rdma_ciq[MAX_RDMA_CIQS];
728 u16 timer_val[SGE_NTIMERS];
729 u8 counter_val[SGE_NCOUNTERS];
730 u32 fl_pg_order; /* large page allocation size */
731 u32 stat_len; /* length of status page at ring end */
732 u32 pktshift; /* padding between CPL & packet data */
733 u32 fl_align; /* response queue message alignment */
734 u32 fl_starve_thres; /* Free List starvation threshold */
736 struct sge_idma_monitor_state idma_monitor;
737 unsigned int egr_start;
739 unsigned int ingr_start;
740 unsigned int ingr_sz;
741 void **egr_map; /* qid->queue egress queue map */
742 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
743 unsigned long *starving_fl;
744 unsigned long *txq_maperr;
745 unsigned long *blocked_fl;
746 struct timer_list rx_timer; /* refills starving FLs */
747 struct timer_list tx_timer; /* checks Tx queues */
750 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
751 #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++)
752 #define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++)
753 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
754 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
758 #ifdef CONFIG_PCI_IOV
760 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
761 * Configuration initialization for T5 only has SR-IOV functionality enabled
762 * on PF0-3 in order to simplify everything.
764 #define NUM_OF_PF_WITH_SRIOV 4
768 struct doorbell_stats {
774 struct hash_mac_addr {
775 struct list_head list;
779 struct uld_msix_bmap {
780 unsigned long *msix_bmap;
781 unsigned int mapsize;
782 spinlock_t lock; /* lock for acquiring bitmap */
785 struct uld_msix_info {
787 char desc[IFNAMSIZ + 10];
794 struct pci_dev *pdev;
795 struct device *pdev_dev;
804 struct adapter_params params;
805 struct cxgb4_virt_res vres;
810 char desc[IFNAMSIZ + 10];
811 } msix_info[MAX_INGQ + 1];
812 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
813 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
814 unsigned int msi_idx;
816 struct doorbell_stats db_stats;
819 struct net_device *port[MAX_NPORTS];
820 u8 chan_map[NCHAN]; /* channel -> port map */
823 unsigned int l2t_start;
824 unsigned int l2t_end;
825 struct l2t_data *l2t;
826 unsigned int clipt_start;
827 unsigned int clipt_end;
828 struct clip_tbl *clipt;
829 struct cxgb4_pci_uld_info *uld;
830 void *uld_handle[CXGB4_ULD_MAX];
831 unsigned int num_uld;
832 struct list_head list_node;
833 struct list_head rcu_node;
834 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
838 struct tid_info tids;
839 void **tid_release_head;
840 spinlock_t tid_release_lock;
841 struct workqueue_struct *workq;
842 struct work_struct tid_release_task;
843 struct work_struct db_full_task;
844 struct work_struct db_drop_task;
845 bool tid_release_task_busy;
847 /* support for mailbox command/reply logging */
848 #define T4_OS_LOG_MBOX_CMDS 256
849 struct mbox_cmd_log *mbox_log;
851 struct dentry *debugfs_root;
852 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
853 bool trace_rss; /* 1 implies that different RSS flit per filter is
854 * used per filter else if 0 default RSS flit is
855 * used for all 4 filters.
858 spinlock_t stats_lock;
859 spinlock_t win0_lock ____cacheline_aligned_in_smp;
862 /* Defined bit width of user definable filter tuples
864 #define ETHTYPE_BITWIDTH 16
865 #define FRAG_BITWIDTH 1
866 #define MACIDX_BITWIDTH 9
867 #define FCOE_BITWIDTH 1
868 #define IPORT_BITWIDTH 3
869 #define MATCHTYPE_BITWIDTH 3
870 #define PROTO_BITWIDTH 8
871 #define TOS_BITWIDTH 8
872 #define PF_BITWIDTH 8
873 #define VF_BITWIDTH 8
874 #define IVLAN_BITWIDTH 16
875 #define OVLAN_BITWIDTH 16
877 /* Filter matching rules. These consist of a set of ingress packet field
878 * (value, mask) tuples. The associated ingress packet field matches the
879 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
880 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
881 * matches an ingress packet when all of the individual individual field
882 * matching rules are true.
884 * Partial field masks are always valid, however, while it may be easy to
885 * understand their meanings for some fields (e.g. IP address to match a
886 * subnet), for others making sensible partial masks is less intuitive (e.g.
887 * MPS match type) ...
889 * Most of the following data structures are modeled on T4 capabilities.
890 * Drivers for earlier chips use the subsets which make sense for those chips.
891 * We really need to come up with a hardware-independent mechanism to
892 * represent hardware filter capabilities ...
894 struct ch_filter_tuple {
895 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
896 * register selects which of these fields will participate in the
897 * filter match rules -- up to a maximum of 36 bits. Because
898 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
901 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
902 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
903 uint32_t ivlan_vld:1; /* inner VLAN valid */
904 uint32_t ovlan_vld:1; /* outer VLAN valid */
905 uint32_t pfvf_vld:1; /* PF/VF valid */
906 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
907 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
908 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
909 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
910 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
911 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
912 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
913 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
914 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
915 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
917 /* Uncompressed header matching field rules. These are always
918 * available for field rules.
920 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
921 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
922 uint16_t lport; /* local port */
923 uint16_t fport; /* foreign port */
926 /* A filter ioctl command.
928 struct ch_filter_specification {
929 /* Administrative fields for filter.
931 uint32_t hitcnts:1; /* count filter hits in TCB */
932 uint32_t prio:1; /* filter has priority over active/server */
934 /* Fundamental filter typing. This is the one element of filter
935 * matching that doesn't exist as a (value, mask) tuple.
937 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
939 /* Packet dispatch information. Ingress packets which match the
940 * filter rules will be dropped, passed to the host or switched back
941 * out as egress packets.
943 uint32_t action:2; /* drop, pass, switch */
945 uint32_t rpttid:1; /* report TID in RSS hash field */
947 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
948 uint32_t iq:10; /* ingress queue */
950 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
951 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
952 /* 1 => TCB contains IQ ID */
954 /* Switch proxy/rewrite fields. An ingress packet which matches a
955 * filter with "switch" set will be looped back out as an egress
956 * packet -- potentially with some Ethernet header rewriting.
958 uint32_t eport:2; /* egress port to switch packet out */
959 uint32_t newdmac:1; /* rewrite destination MAC address */
960 uint32_t newsmac:1; /* rewrite source MAC address */
961 uint32_t newvlan:2; /* rewrite VLAN Tag */
962 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
963 uint8_t smac[ETH_ALEN]; /* new source MAC address */
964 uint16_t vlan; /* VLAN Tag to insert */
966 /* Filter rule value/mask pairs.
968 struct ch_filter_tuple val;
969 struct ch_filter_tuple mask;
973 FILTER_PASS = 0, /* default */
979 VLAN_NOCHANGE = 0, /* default */
985 static inline int is_offload(const struct adapter *adap)
987 return adap->params.offload;
990 static inline int is_pci_uld(const struct adapter *adap)
992 return adap->params.crypto;
995 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
997 return readl(adap->regs + reg_addr);
1000 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1002 writel(val, adap->regs + reg_addr);
1006 static inline u64 readq(const volatile void __iomem *addr)
1008 return readl(addr) + ((u64)readl(addr + 4) << 32);
1011 static inline void writeq(u64 val, volatile void __iomem *addr)
1014 writel(val >> 32, addr + 4);
1018 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1020 return readq(adap->regs + reg_addr);
1023 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1025 writeq(val, adap->regs + reg_addr);
1029 * t4_set_hw_addr - store a port's MAC address in SW
1030 * @adapter: the adapter
1031 * @port_idx: the port index
1032 * @hw_addr: the Ethernet address
1034 * Store the Ethernet address of the given port in SW. Called by the common
1035 * code when it retrieves a port's Ethernet address from EEPROM.
1037 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1040 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1041 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1045 * netdev2pinfo - return the port_info structure associated with a net_device
1048 * Return the struct port_info associated with a net_device
1050 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1052 return netdev_priv(dev);
1056 * adap2pinfo - return the port_info of a port
1057 * @adap: the adapter
1058 * @idx: the port index
1060 * Return the port_info structure for the port of the given index.
1062 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1064 return netdev_priv(adap->port[idx]);
1068 * netdev2adap - return the adapter structure associated with a net_device
1071 * Return the struct adapter associated with a net_device
1073 static inline struct adapter *netdev2adap(const struct net_device *dev)
1075 return netdev2pinfo(dev)->adapter;
1078 #ifdef CONFIG_NET_RX_BUSY_POLL
1079 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1081 spin_lock_init(&q->bpoll_lock);
1082 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1085 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1089 spin_lock(&q->bpoll_lock);
1090 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1091 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
1094 q->bpoll_state = CXGB_POLL_STATE_NAPI;
1096 spin_unlock(&q->bpoll_lock);
1100 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1104 spin_lock(&q->bpoll_lock);
1105 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1107 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1108 spin_unlock(&q->bpoll_lock);
1112 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1116 spin_lock_bh(&q->bpoll_lock);
1117 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1118 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1121 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1123 spin_unlock_bh(&q->bpoll_lock);
1127 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1131 spin_lock_bh(&q->bpoll_lock);
1132 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1134 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1135 spin_unlock_bh(&q->bpoll_lock);
1139 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1141 return q->bpoll_state & CXGB_POLL_USER_PEND;
1144 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1148 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1153 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1158 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1163 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1168 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1172 #endif /* CONFIG_NET_RX_BUSY_POLL */
1174 /* Return a version number to identify the type of adapter. The scheme is:
1175 * - bits 0..9: chip version
1176 * - bits 10..15: chip revision
1177 * - bits 16..23: register dump version
1179 static inline unsigned int mk_adap_vers(struct adapter *ap)
1181 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1182 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1185 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1186 static inline unsigned int qtimer_val(const struct adapter *adap,
1187 const struct sge_rspq *q)
1189 unsigned int idx = q->intr_params >> 1;
1191 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1194 /* driver version & name used for ethtool_drvinfo */
1195 extern char cxgb4_driver_name[];
1196 extern const char cxgb4_driver_version[];
1198 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1199 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1201 void *t4_alloc_mem(size_t size);
1203 void t4_free_sge_resources(struct adapter *adap);
1204 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1205 irq_handler_t t4_intr_handler(struct adapter *adap);
1206 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1207 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1208 const struct pkt_gl *gl);
1209 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1210 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1211 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1212 struct net_device *dev, int intr_idx,
1213 struct sge_fl *fl, rspq_handler_t hnd,
1214 rspq_flush_handler_t flush_handler, int cong);
1215 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1216 struct net_device *dev, struct netdev_queue *netdevq,
1218 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1219 struct net_device *dev, unsigned int iqid,
1220 unsigned int cmplqid);
1221 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1222 struct net_device *dev, unsigned int iqid);
1223 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1224 int t4_sge_init(struct adapter *adap);
1225 void t4_sge_start(struct adapter *adap);
1226 void t4_sge_stop(struct adapter *adap);
1227 int cxgb_busy_poll(struct napi_struct *napi);
1228 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1229 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1230 extern int dbfifo_int_thresh;
1232 #define for_each_port(adapter, iter) \
1233 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1235 static inline int is_bypass(struct adapter *adap)
1237 return adap->params.bypass;
1240 static inline int is_bypass_device(int device)
1242 /* this should be set based upon device capabilities */
1252 static inline int is_10gbt_device(int device)
1254 /* this should be set based upon device capabilities */
1265 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1267 return adap->params.vpd.cclk / 1000;
1270 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1273 return (us * adap->params.vpd.cclk) / 1000;
1276 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1279 /* add Core Clock / 2 to round ticks to nearest uS */
1280 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1281 adapter->params.vpd.cclk);
1284 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1287 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1288 int size, void *rpl, bool sleep_ok, int timeout);
1289 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1290 void *rpl, bool sleep_ok);
1292 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1293 const void *cmd, int size, void *rpl,
1296 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1300 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1301 int size, void *rpl)
1303 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1306 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1307 int size, void *rpl)
1309 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1313 * hash_mac_addr - return the hash value of a MAC address
1314 * @addr: the 48-bit Ethernet MAC address
1316 * Hashes a MAC address according to the hash function used by HW inexact
1317 * (hash) address matching.
1319 static inline int hash_mac_addr(const u8 *addr)
1321 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1322 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1330 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1332 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1333 unsigned int us, unsigned int cnt,
1334 unsigned int size, unsigned int iqe_size)
1337 cxgb4_set_rspq_intr_params(q, us, cnt);
1338 q->iqe_len = iqe_size;
1342 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1343 unsigned int data_reg, const u32 *vals,
1344 unsigned int nregs, unsigned int start_idx);
1345 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1346 unsigned int data_reg, u32 *vals, unsigned int nregs,
1347 unsigned int start_idx);
1348 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1350 struct fw_filter_wr;
1352 void t4_intr_enable(struct adapter *adapter);
1353 void t4_intr_disable(struct adapter *adapter);
1354 int t4_slow_intr_handler(struct adapter *adapter);
1356 int t4_wait_dev_ready(void __iomem *regs);
1357 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1358 struct link_config *lc);
1359 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1361 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1362 u32 t4_get_util_window(struct adapter *adap);
1363 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1365 #define T4_MEMORY_WRITE 0
1366 #define T4_MEMORY_READ 1
1367 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1368 void *buf, int dir);
1369 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1370 u32 len, __be32 *buf)
1372 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1375 unsigned int t4_get_regs_len(struct adapter *adapter);
1376 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1378 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1379 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1380 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1381 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1382 unsigned int nwords, u32 *data, int byte_oriented);
1383 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1384 int t4_load_phy_fw(struct adapter *adap,
1385 int win, spinlock_t *lock,
1386 int (*phy_fw_version)(const u8 *, size_t),
1387 const u8 *phy_fw_data, size_t phy_fw_size);
1388 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1389 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1390 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1391 const u8 *fw_data, unsigned int size, int force);
1392 int t4_fl_pkt_align(struct adapter *adap);
1393 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1394 int t4_check_fw_version(struct adapter *adap);
1395 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1396 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1397 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1398 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1399 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1400 const u8 *fw_data, unsigned int fw_size,
1401 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1402 int t4_prep_adapter(struct adapter *adapter);
1404 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1405 int t4_bar2_sge_qregs(struct adapter *adapter,
1407 enum t4_bar2_qtype qtype,
1410 unsigned int *pbar2_qid);
1412 unsigned int qtimer_val(const struct adapter *adap,
1413 const struct sge_rspq *q);
1415 int t4_init_devlog_params(struct adapter *adapter);
1416 int t4_init_sge_params(struct adapter *adapter);
1417 int t4_init_tp_params(struct adapter *adap);
1418 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1419 int t4_init_rss_mode(struct adapter *adap, int mbox);
1420 int t4_init_portinfo(struct port_info *pi, int mbox,
1421 int port, int pf, int vf, u8 mac[]);
1422 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1423 void t4_fatal_err(struct adapter *adapter);
1424 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1425 int start, int n, const u16 *rspq, unsigned int nrspq);
1426 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1427 unsigned int flags);
1428 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1429 unsigned int flags, unsigned int defq);
1430 int t4_read_rss(struct adapter *adapter, u16 *entries);
1431 void t4_read_rss_key(struct adapter *adapter, u32 *key);
1432 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1433 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1435 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1436 u32 *vfl, u32 *vfh);
1437 u32 t4_read_rss_pf_map(struct adapter *adapter);
1438 u32 t4_read_rss_pf_mask(struct adapter *adapter);
1440 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
1441 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1442 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1443 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1445 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1447 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1448 unsigned int *valp);
1449 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1450 const unsigned int *valp);
1451 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1452 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1453 unsigned int *pif_req_wrptr,
1454 unsigned int *pif_rsp_wrptr);
1455 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1456 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1457 const char *t4_get_port_type_description(enum fw_port_type port_type);
1458 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1459 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1460 struct port_stats *stats,
1461 struct port_stats *offset);
1462 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1463 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1464 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1465 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1466 unsigned int mask, unsigned int val);
1467 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1468 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
1469 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
1470 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1471 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
1472 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1473 struct tp_tcp_stats *v6);
1474 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1475 struct tp_fcoe_stats *st);
1476 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1477 const unsigned short *alpha, const unsigned short *beta);
1479 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1481 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1482 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1484 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1486 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1487 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1489 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1490 enum dev_master master, enum dev_state *state);
1491 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1492 int t4_early_init(struct adapter *adap, unsigned int mbox);
1493 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1494 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1495 unsigned int cache_line_size);
1496 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1497 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1498 unsigned int vf, unsigned int nparams, const u32 *params,
1500 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1501 unsigned int vf, unsigned int nparams, const u32 *params,
1503 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1504 unsigned int pf, unsigned int vf,
1505 unsigned int nparams, const u32 *params,
1506 const u32 *val, int timeout);
1507 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1508 unsigned int vf, unsigned int nparams, const u32 *params,
1510 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1511 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1512 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1513 unsigned int vi, unsigned int cmask, unsigned int pmask,
1514 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1515 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1516 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1517 unsigned int *rss_size);
1518 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1519 unsigned int pf, unsigned int vf,
1521 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1522 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1524 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1525 unsigned int viid, bool free, unsigned int naddr,
1526 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1527 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1528 unsigned int viid, unsigned int naddr,
1529 const u8 **addr, bool sleep_ok);
1530 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1531 int idx, const u8 *addr, bool persist, bool add_smt);
1532 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1533 bool ucast, u64 vec, bool sleep_ok);
1534 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1535 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1536 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1537 bool rx_en, bool tx_en);
1538 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1539 unsigned int nblinks);
1540 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1541 unsigned int mmd, unsigned int reg, u16 *valp);
1542 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1543 unsigned int mmd, unsigned int reg, u16 val);
1544 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1545 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1546 unsigned int fl0id, unsigned int fl1id);
1547 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1548 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1549 unsigned int fl0id, unsigned int fl1id);
1550 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1551 unsigned int vf, unsigned int eqid);
1552 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1553 unsigned int vf, unsigned int eqid);
1554 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1555 unsigned int vf, unsigned int eqid);
1556 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
1557 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1558 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1559 void t4_db_full(struct adapter *adapter);
1560 void t4_db_dropped(struct adapter *adapter);
1561 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1562 int filter_index, int enable);
1563 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1564 int filter_index, int *enabled);
1565 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1567 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1568 void t4_free_mem(void *addr);
1569 void t4_idma_monitor_init(struct adapter *adapter,
1570 struct sge_idma_monitor_state *idma);
1571 void t4_idma_monitor(struct adapter *adapter,
1572 struct sge_idma_monitor_state *idma,
1574 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1575 unsigned int naddr, u8 *addr);
1576 void uld_mem_free(struct adapter *adap);
1577 int uld_mem_alloc(struct adapter *adap);
1578 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1579 #endif /* __CXGB4_H__ */