2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/rhashtable.h>
50 #include <linux/etherdevice.h>
51 #include <linux/net_tstamp.h>
52 #include <linux/ptp_clock_kernel.h>
53 #include <linux/ptp_classify.h>
54 #include <linux/crash_dump.h>
55 #include <linux/thermal.h>
57 #include "t4_chip_type.h"
58 #include "cxgb4_uld.h"
61 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
62 extern struct list_head adapter_list;
63 extern struct list_head uld_list;
64 extern struct mutex uld_mutex;
66 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
67 * This is the same as calc_tx_descs() for a TSO packet with
68 * nr_frags == MAX_SKB_FRAGS.
70 #define ETHTXQ_STOP_THRES \
71 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
73 #define FW_PARAM_DEV(param) \
74 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
75 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
77 #define FW_PARAM_PFVF(param) \
78 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
79 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
80 FW_PARAMS_PARAM_Y_V(0) | \
81 FW_PARAMS_PARAM_Z_V(0))
84 MAX_NPORTS = 4, /* max # of ports */
85 SERNUM_LEN = 24, /* Serial # length */
86 EC_LEN = 16, /* E/C length */
87 ID_LEN = 16, /* ID length */
88 PN_LEN = 16, /* Part Number length */
89 MACADDR_LEN = 12, /* MAC Address length */
93 T4_REGMAP_SIZE = (160 * 1024),
94 T5_REGMAP_SIZE = (332 * 1024),
107 MEMWIN0_APERTURE = 2048,
108 MEMWIN0_BASE = 0x1b800,
109 MEMWIN1_APERTURE = 32768,
110 MEMWIN1_BASE = 0x28000,
111 MEMWIN1_BASE_T5 = 0x52000,
112 MEMWIN2_APERTURE = 65536,
113 MEMWIN2_BASE = 0x30000,
114 MEMWIN2_APERTURE_T5 = 131072,
115 MEMWIN2_BASE_T5 = 0x60000,
133 PAUSE_AUTONEG = 1 << 2
137 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
138 FEC_RS = 1 << 1, /* Reed-Solomon */
139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
143 CXGB4_ETHTOOL_FLASH_FW = 1,
144 CXGB4_ETHTOOL_FLASH_PHY = 2,
145 CXGB4_ETHTOOL_FLASH_BOOT = 3,
146 CXGB4_ETHTOOL_FLASH_BOOTCFG = 4
149 struct cxgb4_bootcfg_data {
154 struct cxgb4_pcir_data {
155 __le32 signature; /* Signature. The string "PCIR" */
156 __le16 vendor_id; /* Vendor Identification */
157 __le16 device_id; /* Device Identification */
158 __u8 vital_product[2]; /* Pointer to Vital Product Data */
159 __u8 length[2]; /* PCIR Data Structure Length */
160 __u8 revision; /* PCIR Data Structure Revision */
161 __u8 class_code[3]; /* Class Code */
162 __u8 image_length[2]; /* Image Length. Multiple of 512B */
163 __u8 code_revision[2]; /* Revision Level of Code/Data */
169 /* BIOS boot headers */
170 struct cxgb4_pci_exp_rom_header {
171 __le16 signature; /* ROM Signature. Should be 0xaa55 */
172 __u8 reserved[22]; /* Reserved per processor Architecture data */
173 __le16 pcir_offset; /* Offset to PCI Data Structure */
176 /* Legacy PCI Expansion ROM Header */
177 struct legacy_pci_rom_hdr {
178 __u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
179 __u8 size512; /* Current Image Size in units of 512 bytes */
180 __u8 initentry_point[4];
181 __u8 cksum; /* Checksum computed on the entire Image */
182 __u8 reserved[16]; /* Reserved */
183 __le16 pcir_offset; /* Offset to PCI Data Struture */
186 #define CXGB4_HDR_CODE1 0x00
187 #define CXGB4_HDR_CODE2 0x03
188 #define CXGB4_HDR_INDI 0x80
192 BOOT_CFG_SIG = 0x4243,
194 BOOT_SIGNATURE = 0xaa55,
195 BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header),
196 BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC,
197 PCIR_SIGNATURE = 0x52494350
201 u64 tx_octets; /* total # of octets in good frames */
202 u64 tx_frames; /* all good frames */
203 u64 tx_bcast_frames; /* all broadcast frames */
204 u64 tx_mcast_frames; /* all multicast frames */
205 u64 tx_ucast_frames; /* all unicast frames */
206 u64 tx_error_frames; /* all error frames */
208 u64 tx_frames_64; /* # of Tx frames in a particular range */
209 u64 tx_frames_65_127;
210 u64 tx_frames_128_255;
211 u64 tx_frames_256_511;
212 u64 tx_frames_512_1023;
213 u64 tx_frames_1024_1518;
214 u64 tx_frames_1519_max;
216 u64 tx_drop; /* # of dropped Tx frames */
217 u64 tx_pause; /* # of transmitted pause frames */
218 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
219 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
220 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
221 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
222 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
223 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
224 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
225 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
227 u64 rx_octets; /* total # of octets in good frames */
228 u64 rx_frames; /* all good frames */
229 u64 rx_bcast_frames; /* all broadcast frames */
230 u64 rx_mcast_frames; /* all multicast frames */
231 u64 rx_ucast_frames; /* all unicast frames */
232 u64 rx_too_long; /* # of frames exceeding MTU */
233 u64 rx_jabber; /* # of jabber frames */
234 u64 rx_fcs_err; /* # of received frames with bad FCS */
235 u64 rx_len_err; /* # of received frames with length error */
236 u64 rx_symbol_err; /* symbol errors */
237 u64 rx_runt; /* # of short frames */
239 u64 rx_frames_64; /* # of Rx frames in a particular range */
240 u64 rx_frames_65_127;
241 u64 rx_frames_128_255;
242 u64 rx_frames_256_511;
243 u64 rx_frames_512_1023;
244 u64 rx_frames_1024_1518;
245 u64 rx_frames_1519_max;
247 u64 rx_pause; /* # of received pause frames */
248 u64 rx_ppp0; /* # of received PPP prio 0 frames */
249 u64 rx_ppp1; /* # of received PPP prio 1 frames */
250 u64 rx_ppp2; /* # of received PPP prio 2 frames */
251 u64 rx_ppp3; /* # of received PPP prio 3 frames */
252 u64 rx_ppp4; /* # of received PPP prio 4 frames */
253 u64 rx_ppp5; /* # of received PPP prio 5 frames */
254 u64 rx_ppp6; /* # of received PPP prio 6 frames */
255 u64 rx_ppp7; /* # of received PPP prio 7 frames */
257 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
258 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
259 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
260 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
261 u64 rx_trunc0; /* buffer-group 0 truncated packets */
262 u64 rx_trunc1; /* buffer-group 1 truncated packets */
263 u64 rx_trunc2; /* buffer-group 2 truncated packets */
264 u64 rx_trunc3; /* buffer-group 3 truncated packets */
267 struct lb_port_stats {
280 u64 frames_1024_1518;
295 struct tp_tcp_stats {
299 u64 tcp_retrans_segs;
302 struct tp_usm_stats {
308 struct tp_fcoe_stats {
314 struct tp_err_stats {
318 u32 tnl_cong_drops[4];
319 u32 ofld_chan_drops[4];
321 u32 ofld_vlan_drops[4];
327 struct tp_cpl_stats {
332 struct tp_rdma_stats {
338 u32 hps; /* host page size for our PF/VF */
339 u32 eq_qpp; /* egress queues/page for our PF/VF */
340 u32 iq_qpp; /* egress queues/page for our PF/VF */
344 unsigned int tre; /* log2 of core clocks per TP tick */
345 unsigned int la_mask; /* what events are recorded by TP LA */
346 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
349 uint32_t dack_re; /* DACK timer resolution */
350 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
352 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
354 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
356 /* cached TP_OUT_CONFIG compressed error vector
357 * and passing outer header info for encapsulated packets.
361 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
362 * subset of the set of fields which may be present in the Compressed
363 * Filter Tuple portion of filters and TCP TCB connections. The
364 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
365 * Since a variable number of fields may or may not be present, their
366 * shifted field positions within the Compressed Filter Tuple may
367 * vary, or not even be present if the field isn't selected in
368 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
369 * places we store their offsets here, or a -1 if the field isn't
383 u64 hash_filter_mask;
389 u8 sn[SERNUM_LEN + 1];
392 u8 na[MACADDR_LEN + 1];
395 /* Maximum resources provisioned for a PCI PF.
397 struct pf_resources {
398 unsigned int nvi; /* N virtual interfaces */
399 unsigned int neq; /* N egress Qs */
400 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
401 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
402 unsigned int niq; /* N ingress Qs */
403 unsigned int tc; /* PCI-E traffic class */
404 unsigned int pmask; /* port access rights mask */
405 unsigned int nexactf; /* N exact MPS filters */
406 unsigned int r_caps; /* read capabilities */
407 unsigned int wx_caps; /* write/execute capabilities */
411 unsigned int vpd_cap_addr;
416 struct devlog_params {
417 u32 memtype; /* which memory (EDC0, EDC1, MC) */
418 u32 start; /* start of log in firmware memory */
419 u32 size; /* size of log */
422 /* Stores chip specific parameters */
423 struct arch_specific_params {
426 u8 cng_ch_bits_log; /* congestion channel map bits width */
433 struct adapter_params {
434 struct sge_params sge;
436 struct vpd_params vpd;
437 struct pf_resources pfres;
438 struct pci_params pci;
439 struct devlog_params devlog;
440 enum pcie_memwin drv_memwin;
442 unsigned int cim_la_size;
444 unsigned int sf_size; /* serial flash size in bytes */
445 unsigned int sf_nsec; /* # of flash sectors */
447 unsigned int fw_vers; /* firmware version */
448 unsigned int bs_vers; /* bootstrap version */
449 unsigned int tp_vers; /* TP microcode version */
450 unsigned int er_vers; /* expansion ROM version */
451 unsigned int scfg_vers; /* Serial Configuration version */
452 unsigned int vpd_vers; /* VPD Version */
455 unsigned short mtus[NMTUS];
456 unsigned short a_wnd[NCCTRL_WIN];
457 unsigned short b_wnd[NCCTRL_WIN];
459 unsigned char nports; /* # of ethernet ports */
460 unsigned char portvec;
461 enum chip_type chip; /* chip code */
462 struct arch_specific_params arch; /* chip specific params */
463 unsigned char offload;
464 unsigned char crypto; /* HW capability for crypto */
465 unsigned char ethofld; /* QoS support */
467 unsigned char bypass;
468 unsigned char hash_filter;
470 unsigned int ofldq_wr_cred;
471 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
473 unsigned int nsched_cls; /* number of traffic classes */
474 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
475 unsigned int max_ird_adapter; /* Max read depth per adapter */
476 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
477 u8 fw_caps_support; /* 32-bit Port Capabilities */
478 bool filter2_wr_support; /* FW support for FILTER2_WR */
479 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
481 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
484 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
485 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
486 bool write_cmpl_support; /* FW supports WRITE_CMPL */
489 /* State needed to monitor the forward progress of SGE Ingress DMA activities
490 * and possible hangs.
492 struct sge_idma_monitor_state {
493 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
494 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
495 unsigned int idma_state[2]; /* IDMA Hang detect state */
496 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
497 unsigned int idma_warn[2]; /* time to warning in HZ */
500 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
501 * The access and execute times are signed in order to accommodate negative
505 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
506 u64 timestamp; /* OS-dependent timestamp */
507 u32 seqno; /* sequence number */
508 s16 access; /* time (ms) to access mailbox */
509 s16 execute; /* time (ms) to execute */
512 struct mbox_cmd_log {
513 unsigned int size; /* number of entries in the log */
514 unsigned int cursor; /* next position in the log to write */
515 u32 seqno; /* next sequence number */
516 /* variable length mailbox command log starts here */
519 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
520 * return a pointer to the specified entry.
522 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
523 unsigned int entry_idx)
525 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
528 #define FW_VERSION(chip) ( \
529 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
530 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
531 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
532 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
533 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
539 struct fw_hdr fw_hdr;
542 struct trace_params {
543 u32 data[TRACE_LEN / 4];
544 u32 mask[TRACE_LEN / 4];
545 unsigned short snap_len;
546 unsigned short min_len;
547 unsigned char skip_ofst;
548 unsigned char skip_len;
549 unsigned char invert;
553 struct cxgb4_fw_data {
558 /* Firmware Port Capabilities types. */
560 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
561 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
564 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
565 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
566 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
570 fw_port_cap32_t pcaps; /* link capabilities */
571 fw_port_cap32_t def_acaps; /* default advertised capabilities */
572 fw_port_cap32_t acaps; /* advertised capabilities */
573 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
575 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
576 unsigned int speed; /* actual link speed (Mb/s) */
578 enum cc_pause requested_fc; /* flow control user has requested */
579 enum cc_pause fc; /* actual link flow control */
580 enum cc_pause advertised_fc; /* actual advertised flow control */
582 enum cc_fec requested_fec; /* Forward Error Correction: */
583 enum cc_fec fec; /* requested and actual in use */
585 unsigned char autoneg; /* autonegotiating? */
587 unsigned char link_ok; /* link up? */
588 unsigned char link_down_rc; /* link down reason */
590 bool new_module; /* ->OS Transceiver Module inserted */
591 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
594 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
597 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
598 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
599 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
603 MAX_TXQ_ENTRIES = 16384,
604 MAX_CTRL_TXQ_ENTRIES = 1024,
605 MAX_RSPQ_ENTRIES = 16384,
606 MAX_RX_BUFFERS = 16384,
607 MIN_TXQ_ENTRIES = 32,
608 MIN_CTRL_TXQ_ENTRIES = 32,
609 MIN_RSPQ_ENTRIES = 128,
614 MAX_TXQ_DESC_SIZE = 64,
615 MAX_RXQ_DESC_SIZE = 128,
616 MAX_FL_DESC_SIZE = 8,
617 MAX_CTRL_TXQ_DESC_SIZE = 64,
621 INGQ_EXTRAS = 2, /* firmware event queue and */
622 /* forwarded interrupts */
623 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
627 PRIV_FLAG_PORT_TX_VM_BIT,
630 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
632 #define PRIV_FLAGS_ADAP 0
633 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
638 #include "cxgb4_dcb.h"
640 #ifdef CONFIG_CHELSIO_T4_FCOE
641 #include "cxgb4_fcoe.h"
642 #endif /* CONFIG_CHELSIO_T4_FCOE */
645 struct adapter *adapter;
647 int xact_addr_filt; /* index of exact MAC address filter */
648 u16 rss_size; /* size of VI's RSS table slice */
650 enum fw_port_type port_type;
654 u8 lport; /* associated offload logical port */
655 u8 nqsets; /* # of qsets */
656 u8 first_qset; /* index of first qset */
658 struct link_config link_cfg;
660 struct port_stats stats_base;
661 #ifdef CONFIG_CHELSIO_T4_DCB
662 struct port_dcb_info dcb; /* Data Center Bridging support */
664 #ifdef CONFIG_CHELSIO_T4_FCOE
665 struct cxgb_fcoe fcoe;
666 #endif /* CONFIG_CHELSIO_T4_FCOE */
667 bool rxtstamp; /* Enable TS */
668 struct hwtstamp_config tstamp_config;
670 struct sched_table *sched_tbl;
673 /* viid and smt fields either returned by fw
674 * or decoded by parsing viid by driver.
681 bool tc_block_shared;
683 /* Mirror VI information */
687 struct mutex vi_mirror_mutex; /* Sync access to Mirror VI info */
693 enum { /* adapter flags */
694 CXGB4_FULL_INIT_DONE = (1 << 0),
695 CXGB4_DEV_ENABLED = (1 << 1),
696 CXGB4_USING_MSI = (1 << 2),
697 CXGB4_USING_MSIX = (1 << 3),
698 CXGB4_FW_OK = (1 << 4),
699 CXGB4_RSS_TNLALLLOOKUP = (1 << 5),
700 CXGB4_USING_SOFT_PARAMS = (1 << 6),
701 CXGB4_MASTER_PF = (1 << 7),
702 CXGB4_FW_OFLD_CONN = (1 << 9),
703 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10),
704 CXGB4_SHUTTING_DOWN = (1 << 11),
705 CXGB4_SGE_DBQ_TIMER = (1 << 12),
709 ULP_CRYPTO_LOOKASIDE = 1 << 0,
710 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
711 ULP_CRYPTO_KTLS_INLINE = 1 << 3,
714 #define CXGB4_MIRROR_RXQ_DEFAULT_DESC_NUM 1024
715 #define CXGB4_MIRROR_RXQ_DEFAULT_DESC_SIZE 64
716 #define CXGB4_MIRROR_RXQ_DEFAULT_INTR_USEC 5
717 #define CXGB4_MIRROR_RXQ_DEFAULT_PKT_CNT 8
719 #define CXGB4_MIRROR_FLQ_DEFAULT_DESC_NUM 72
723 struct sge_fl { /* SGE free-buffer queue state */
724 unsigned int avail; /* # of available Rx buffers */
725 unsigned int pend_cred; /* new buffers since last FL DB ring */
726 unsigned int cidx; /* consumer index */
727 unsigned int pidx; /* producer index */
728 unsigned long alloc_failed; /* # of times buffer allocation failed */
729 unsigned long large_alloc_failed;
730 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
731 unsigned long low; /* # of times momentarily starving */
732 unsigned long starving;
734 unsigned int cntxt_id; /* SGE context id for the free list */
735 unsigned int size; /* capacity of free list */
736 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
737 __be64 *desc; /* address of HW Rx descriptor ring */
738 dma_addr_t addr; /* bus address of HW ring start */
739 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
740 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
743 /* A packet gather list */
745 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
746 struct page_frag frags[MAX_SKB_FRAGS];
747 void *va; /* virtual address of first byte */
748 unsigned int nfrags; /* # of fragments */
749 unsigned int tot_len; /* total length of fragments */
752 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
753 const struct pkt_gl *gl);
754 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
755 /* LRO related declarations for ULD */
757 #define MAX_LRO_SESSIONS 64
758 u8 lro_session_cnt; /* # of sessions to aggregate */
759 unsigned long lro_pkts; /* # of LRO super packets */
760 unsigned long lro_merged; /* # of wire packets merged by LRO */
761 struct sk_buff_head lroq; /* list of aggregated sessions */
764 struct sge_rspq { /* state for an SGE response queue */
765 struct napi_struct napi;
766 const __be64 *cur_desc; /* current descriptor in queue */
767 unsigned int cidx; /* consumer index */
768 u8 gen; /* current generation bit */
769 u8 intr_params; /* interrupt holdoff parameters */
770 u8 next_intr_params; /* holdoff params for next interrupt */
772 u8 pktcnt_idx; /* interrupt packet threshold */
773 u8 uld; /* ULD handling this queue */
774 u8 idx; /* queue index within its group */
775 int offset; /* offset into current Rx buffer */
776 u16 cntxt_id; /* SGE context id for the response q */
777 u16 abs_id; /* absolute SGE id for the response q */
778 __be64 *desc; /* address of HW response ring */
779 dma_addr_t phys_addr; /* physical address of the ring */
780 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
781 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
782 unsigned int iqe_len; /* entry size */
783 unsigned int size; /* capacity of response queue */
784 struct adapter *adap;
785 struct net_device *netdev; /* associated net device */
786 rspq_handler_t handler;
787 rspq_flush_handler_t flush_handler;
788 struct t4_lro_mgr lro_mgr;
791 struct sge_eth_stats { /* Ethernet queue statistics */
792 unsigned long pkts; /* # of ethernet packets */
793 unsigned long lro_pkts; /* # of LRO super packets */
794 unsigned long lro_merged; /* # of wire packets merged by LRO */
795 unsigned long rx_cso; /* # of Rx checksum offloads */
796 unsigned long vlan_ex; /* # of Rx VLAN extractions */
797 unsigned long rx_drops; /* # of packets dropped due to no mem */
798 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */
801 struct sge_eth_rxq { /* SW Ethernet Rx queue */
802 struct sge_rspq rspq;
804 struct sge_eth_stats stats;
805 struct msix_info *msix;
806 } ____cacheline_aligned_in_smp;
808 struct sge_ofld_stats { /* offload queue statistics */
809 unsigned long pkts; /* # of packets */
810 unsigned long imm; /* # of immediate-data packets */
811 unsigned long an; /* # of asynchronous notifications */
812 unsigned long nomem; /* # of responses deferred due to no mem */
815 struct sge_ofld_rxq { /* SW offload Rx queue */
816 struct sge_rspq rspq;
818 struct sge_ofld_stats stats;
819 struct msix_info *msix;
820 } ____cacheline_aligned_in_smp;
829 struct sk_buff *skb; /* SKB to free after getting completion */
830 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */
834 unsigned int in_use; /* # of in-use Tx descriptors */
835 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */
836 unsigned int size; /* # of descriptors */
837 unsigned int cidx; /* SW consumer index */
838 unsigned int pidx; /* producer index */
839 unsigned long stops; /* # of times q has been stopped */
840 unsigned long restarts; /* # of queue restarts */
841 unsigned int cntxt_id; /* SGE context id for the Tx q */
842 struct tx_desc *desc; /* address of HW Tx descriptor ring */
843 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
844 struct sge_qstat *stat; /* queue status entry */
845 dma_addr_t phys_addr; /* physical address of the ring */
848 unsigned short db_pidx;
849 unsigned short db_pidx_inc;
850 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
851 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
854 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
856 struct netdev_queue *txq; /* associated netdev TX queue */
857 #ifdef CONFIG_CHELSIO_T4_DCB
858 u8 dcb_prio; /* DCB Priority bound to queue */
860 u8 dbqt; /* SGE Doorbell Queue Timer in use */
861 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */
862 unsigned long tso; /* # of TSO requests */
863 unsigned long uso; /* # of USO requests */
864 unsigned long tx_cso; /* # of Tx checksum offloads */
865 unsigned long vlan_ins; /* # of Tx VLAN insertions */
866 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
867 } ____cacheline_aligned_in_smp;
869 struct sge_uld_txq { /* state for an SGE offload Tx queue */
871 struct adapter *adap;
872 struct sk_buff_head sendq; /* list of backpressured packets */
873 struct tasklet_struct qresume_tsk; /* restarts the queue */
874 bool service_ofldq_running; /* service_ofldq() is processing sendq */
875 u8 full; /* the Tx ring is full */
876 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
877 } ____cacheline_aligned_in_smp;
879 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
881 struct adapter *adap;
882 struct sk_buff_head sendq; /* list of backpressured packets */
883 struct tasklet_struct qresume_tsk; /* restarts the queue */
884 u8 full; /* the Tx ring is full */
885 } ____cacheline_aligned_in_smp;
887 struct sge_uld_rxq_info {
888 char name[IFNAMSIZ]; /* name of ULD driver */
889 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
890 u16 *rspq_id; /* response queue id's of rxq */
891 u16 nrxq; /* # of ingress uld queues */
892 u16 nciq; /* # of completion queues */
893 u8 uld; /* uld type */
896 struct sge_uld_txq_info {
897 struct sge_uld_txq *uldtxq; /* Txq's for ULD */
898 atomic_t users; /* num users */
899 u16 ntxq; /* # of egress uld queues */
902 /* struct to maintain ULD list to reallocate ULD resources on hotplug */
903 struct cxgb4_uld_list {
904 struct cxgb4_uld_info uld_info;
905 struct list_head list_node;
906 enum cxgb4_uld uld_type;
909 enum sge_eosw_state {
910 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */
911 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */
912 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */
913 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */
914 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */
915 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */
918 struct sge_eosw_txq {
919 spinlock_t lock; /* Per queue lock to synchronize completions */
920 enum sge_eosw_state state; /* Current ETHOFLD State */
921 struct tx_sw_desc *desc; /* Descriptor ring to hold packets */
922 u32 ndesc; /* Number of descriptors */
923 u32 pidx; /* Current Producer Index */
924 u32 last_pidx; /* Last successfully transmitted Producer Index */
925 u32 cidx; /* Current Consumer Index */
926 u32 last_cidx; /* Last successfully reclaimed Consumer Index */
927 u32 flowc_idx; /* Descriptor containing a FLOWC request */
928 u32 inuse; /* Number of packets held in ring */
930 u32 cred; /* Current available credits */
931 u32 ncompl; /* # of completions posted */
932 u32 last_compl; /* # of credits consumed since last completion req */
934 u32 eotid; /* Index into EOTID table in software */
935 u32 hwtid; /* Hardware EOTID index */
937 u32 hwqid; /* Underlying hardware queue index */
938 struct net_device *netdev; /* Pointer to netdevice */
939 struct tasklet_struct qresume_tsk; /* Restarts the queue */
940 struct completion completion; /* completion for FLOWC rendezvous */
943 struct sge_eohw_txq {
944 spinlock_t lock; /* Per queue lock */
945 struct sge_txq q; /* HW Txq */
946 struct adapter *adap; /* Backpointer to adapter */
947 unsigned long tso; /* # of TSO requests */
948 unsigned long uso; /* # of USO requests */
949 unsigned long tx_cso; /* # of Tx checksum offloads */
950 unsigned long vlan_ins; /* # of Tx VLAN insertions */
951 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
955 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
956 struct sge_eth_txq ptptxq;
957 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
959 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
960 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
961 struct sge_uld_rxq_info **uld_rxq_info;
962 struct sge_uld_txq_info **uld_txq_info;
964 struct sge_rspq intrq ____cacheline_aligned_in_smp;
965 spinlock_t intrq_lock;
967 struct sge_eohw_txq *eohw_txq;
968 struct sge_ofld_rxq *eohw_rxq;
970 struct sge_eth_rxq *mirror_rxq[NCHAN];
972 u16 max_ethqsets; /* # of available Ethernet queue sets */
973 u16 ethqsets; /* # of active Ethernet queue sets */
974 u16 ethtxq_rover; /* Tx queue to clean up next */
975 u16 ofldqsets; /* # of active ofld queue sets */
976 u16 nqs_per_uld; /* # of Rx queues per ULD */
977 u16 eoqsets; /* # of ETHOFLD queues */
978 u16 mirrorqsets; /* # of Mirror queues */
980 u16 timer_val[SGE_NTIMERS];
981 u8 counter_val[SGE_NCOUNTERS];
983 u16 dbqtimer_val[SGE_NDBQTIMERS];
984 u32 fl_pg_order; /* large page allocation size */
985 u32 stat_len; /* length of status page at ring end */
986 u32 pktshift; /* padding between CPL & packet data */
987 u32 fl_align; /* response queue message alignment */
988 u32 fl_starve_thres; /* Free List starvation threshold */
990 struct sge_idma_monitor_state idma_monitor;
991 unsigned int egr_start;
993 unsigned int ingr_start;
994 unsigned int ingr_sz;
995 void **egr_map; /* qid->queue egress queue map */
996 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
997 unsigned long *starving_fl;
998 unsigned long *txq_maperr;
999 unsigned long *blocked_fl;
1000 struct timer_list rx_timer; /* refills starving FLs */
1001 struct timer_list tx_timer; /* checks Tx queues */
1003 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */
1004 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */
1007 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
1008 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
1012 #ifdef CONFIG_PCI_IOV
1014 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
1015 * Configuration initialization for T5 only has SR-IOV functionality enabled
1016 * on PF0-3 in order to simplify everything.
1018 #define NUM_OF_PF_WITH_SRIOV 4
1022 struct doorbell_stats {
1028 struct hash_mac_addr {
1029 struct list_head list;
1031 unsigned int iface_mac;
1035 unsigned long *msix_bmap;
1036 unsigned int mapsize;
1037 spinlock_t lock; /* lock for acquiring bitmap */
1042 char desc[IFNAMSIZ + 10];
1044 cpumask_var_t aff_mask;
1048 unsigned char vf_mac_addr[ETH_ALEN];
1049 unsigned int tx_rate;
1056 HMA_DMA_MAPPED_FLAG = 1
1060 unsigned char flags;
1061 struct sg_table *sgt;
1062 dma_addr_t *phy_addr; /* physical address of the page */
1066 struct list_head list;
1069 #if IS_ENABLED(CONFIG_THERMAL)
1071 struct thermal_zone_device *tzdev;
1077 struct mps_entries_ref {
1078 struct list_head list;
1085 struct cxgb4_ethtool_filter_info {
1086 u32 *loc_array; /* Array holding the actual TIDs set to filters */
1087 unsigned long *bmap; /* Bitmap for managing filters in use */
1088 u32 in_use; /* # of filters in use */
1091 struct cxgb4_ethtool_filter {
1092 u32 nentries; /* Adapter wide number of supported filters */
1093 struct cxgb4_ethtool_filter_info *port; /* Per port entry */
1100 struct pci_dev *pdev;
1101 struct device *pdev_dev;
1106 unsigned int adap_idx;
1107 enum chip_type chip;
1116 struct adapter_params params;
1117 struct cxgb4_virt_res vres;
1118 unsigned int swintr;
1120 /* MSI-X Info for NIC and OFLD queues */
1121 struct msix_info *msix_info;
1122 struct msix_bmap msix_bmap;
1124 struct doorbell_stats db_stats;
1127 struct net_device *port[MAX_NPORTS];
1128 u8 chan_map[NCHAN]; /* channel -> port map */
1130 struct vf_info *vfinfo;
1134 unsigned int l2t_start;
1135 unsigned int l2t_end;
1136 struct l2t_data *l2t;
1137 unsigned int clipt_start;
1138 unsigned int clipt_end;
1139 struct clip_tbl *clipt;
1140 unsigned int rawf_start;
1141 unsigned int rawf_cnt;
1142 struct smt_data *smt;
1143 struct cxgb4_uld_info *uld;
1144 void *uld_handle[CXGB4_ULD_MAX];
1145 unsigned int num_uld;
1146 unsigned int num_ofld_uld;
1147 struct list_head list_node;
1148 struct list_head rcu_node;
1149 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
1150 struct list_head mps_ref;
1151 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */
1155 struct tid_info tids;
1156 void **tid_release_head;
1157 spinlock_t tid_release_lock;
1158 struct workqueue_struct *workq;
1159 struct work_struct tid_release_task;
1160 struct work_struct db_full_task;
1161 struct work_struct db_drop_task;
1162 struct work_struct fatal_err_notify_task;
1163 bool tid_release_task_busy;
1165 /* lock for mailbox cmd list */
1166 spinlock_t mbox_lock;
1167 struct mbox_list mlist;
1169 /* support for mailbox command/reply logging */
1170 #define T4_OS_LOG_MBOX_CMDS 256
1171 struct mbox_cmd_log *mbox_log;
1173 struct mutex uld_mutex;
1175 struct dentry *debugfs_root;
1176 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
1177 bool trace_rss; /* 1 implies that different RSS flit per filter is
1178 * used per filter else if 0 default RSS flit is
1179 * used for all 4 filters.
1182 struct ptp_clock *ptp_clock;
1183 struct ptp_clock_info ptp_clock_info;
1184 struct sk_buff *ptp_tx_skb;
1186 spinlock_t ptp_lock;
1187 spinlock_t stats_lock;
1188 spinlock_t win0_lock ____cacheline_aligned_in_smp;
1190 /* TC u32 offload */
1191 struct cxgb4_tc_u32_table *tc_u32;
1192 struct chcr_ktls chcr_ktls;
1193 struct chcr_stats_debug chcr_stats;
1195 /* TC flower offload */
1196 bool tc_flower_initialized;
1197 struct rhashtable flower_tbl;
1198 struct rhashtable_params flower_ht_params;
1199 struct timer_list flower_stats_timer;
1200 struct work_struct flower_stats_work;
1203 struct ethtool_dump eth_dump;
1206 struct hma_data hma;
1208 struct srq_data *srq;
1210 /* Dump buffer for collecting logs in kdump kernel */
1211 struct vmcoredd_data vmcoredd;
1212 #if IS_ENABLED(CONFIG_THERMAL)
1213 struct ch_thermal ch_thermal;
1216 /* TC MQPRIO offload */
1217 struct cxgb4_tc_mqprio *tc_mqprio;
1219 /* TC MATCHALL classifier offload */
1220 struct cxgb4_tc_matchall *tc_matchall;
1222 /* Ethtool n-tuple */
1223 struct cxgb4_ethtool_filter *ethtool_filters;
1226 /* Support for "sched-class" command to allow a TX Scheduling Class to be
1227 * programmed with various parameters.
1229 struct ch_sched_params {
1230 u8 type; /* packet or flow */
1233 u8 level; /* scheduler hierarchy level */
1234 u8 mode; /* per-class or per-flow */
1235 u8 rateunit; /* bit or packet rate */
1236 u8 ratemode; /* %port relative or kbps absolute */
1237 u8 channel; /* scheduler channel [0..N] */
1238 u8 class; /* scheduler class [0..N] */
1239 u32 minrate; /* minimum rate */
1240 u32 maxrate; /* maximum rate */
1241 u16 weight; /* percent weight */
1242 u16 pktsize; /* average packet size */
1243 u16 burstsize; /* burst buffer size */
1249 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
1253 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
1254 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */
1258 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
1259 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */
1263 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
1267 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
1270 /* Support for "sched_queue" command to allow one or more NIC TX Queues
1271 * to be bound to a TX Scheduling Class.
1273 struct ch_sched_queue {
1274 s8 queue; /* queue index */
1275 s8 class; /* class index */
1278 /* Support for "sched_flowc" command to allow one or more FLOWC
1279 * to be bound to a TX Scheduling Class.
1281 struct ch_sched_flowc {
1282 s32 tid; /* TID to bind */
1283 s8 class; /* class index */
1286 /* Defined bit width of user definable filter tuples
1288 #define ETHTYPE_BITWIDTH 16
1289 #define FRAG_BITWIDTH 1
1290 #define MACIDX_BITWIDTH 9
1291 #define FCOE_BITWIDTH 1
1292 #define IPORT_BITWIDTH 3
1293 #define MATCHTYPE_BITWIDTH 3
1294 #define PROTO_BITWIDTH 8
1295 #define TOS_BITWIDTH 8
1296 #define PF_BITWIDTH 8
1297 #define VF_BITWIDTH 8
1298 #define IVLAN_BITWIDTH 16
1299 #define OVLAN_BITWIDTH 16
1300 #define ENCAP_VNI_BITWIDTH 24
1302 /* Filter matching rules. These consist of a set of ingress packet field
1303 * (value, mask) tuples. The associated ingress packet field matches the
1304 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
1305 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
1306 * matches an ingress packet when all of the individual individual field
1307 * matching rules are true.
1309 * Partial field masks are always valid, however, while it may be easy to
1310 * understand their meanings for some fields (e.g. IP address to match a
1311 * subnet), for others making sensible partial masks is less intuitive (e.g.
1312 * MPS match type) ...
1314 * Most of the following data structures are modeled on T4 capabilities.
1315 * Drivers for earlier chips use the subsets which make sense for those chips.
1316 * We really need to come up with a hardware-independent mechanism to
1317 * represent hardware filter capabilities ...
1319 struct ch_filter_tuple {
1320 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
1321 * register selects which of these fields will participate in the
1322 * filter match rules -- up to a maximum of 36 bits. Because
1323 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1326 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
1327 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
1328 uint32_t ivlan_vld:1; /* inner VLAN valid */
1329 uint32_t ovlan_vld:1; /* outer VLAN valid */
1330 uint32_t pfvf_vld:1; /* PF/VF valid */
1331 uint32_t encap_vld:1; /* Encapsulation valid */
1332 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
1333 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
1334 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
1335 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
1336 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
1337 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
1338 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1339 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1340 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
1341 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
1342 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
1344 /* Uncompressed header matching field rules. These are always
1345 * available for field rules.
1347 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
1348 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
1349 uint16_t lport; /* local port */
1350 uint16_t fport; /* foreign port */
1353 /* A filter ioctl command.
1355 struct ch_filter_specification {
1356 /* Administrative fields for filter.
1358 uint32_t hitcnts:1; /* count filter hits in TCB */
1359 uint32_t prio:1; /* filter has priority over active/server */
1361 /* Fundamental filter typing. This is the one element of filter
1362 * matching that doesn't exist as a (value, mask) tuple.
1364 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
1365 u32 hash:1; /* 0 => wild-card, 1 => exact-match */
1367 /* Packet dispatch information. Ingress packets which match the
1368 * filter rules will be dropped, passed to the host or switched back
1369 * out as egress packets.
1371 uint32_t action:2; /* drop, pass, switch */
1373 uint32_t rpttid:1; /* report TID in RSS hash field */
1375 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1376 uint32_t iq:10; /* ingress queue */
1378 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1379 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1380 /* 1 => TCB contains IQ ID */
1382 /* Switch proxy/rewrite fields. An ingress packet which matches a
1383 * filter with "switch" set will be looped back out as an egress
1384 * packet -- potentially with some Ethernet header rewriting.
1386 uint32_t eport:2; /* egress port to switch packet out */
1387 uint32_t newdmac:1; /* rewrite destination MAC address */
1388 uint32_t newsmac:1; /* rewrite source MAC address */
1389 uint32_t newvlan:2; /* rewrite VLAN Tag */
1390 uint32_t nat_mode:3; /* specify NAT operation mode */
1391 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1392 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1393 uint16_t vlan; /* VLAN Tag to insert */
1395 u8 nat_lip[16]; /* local IP to use after NAT'ing */
1396 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
1397 u16 nat_lport; /* local port to use after NAT'ing */
1398 u16 nat_fport; /* foreign port to use after NAT'ing */
1400 u32 tc_prio; /* TC's filter priority index */
1401 u64 tc_cookie; /* Unique cookie identifying TC rules */
1403 /* reservation for future additions */
1406 /* Filter rule value/mask pairs.
1408 struct ch_filter_tuple val;
1409 struct ch_filter_tuple mask;
1413 FILTER_PASS = 0, /* default */
1419 VLAN_NOCHANGE = 0, /* default */
1426 NAT_MODE_NONE = 0, /* No NAT performed */
1427 NAT_MODE_DIP, /* NAT on Dst IP */
1428 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */
1429 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */
1430 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */
1431 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */
1432 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */
1433 NAT_MODE_ALL /* NAT on entire 4-tuple */
1436 /* Host shadow copy of ingress filter entry. This is in host native format
1437 * and doesn't match the ordering or bit order, etc. of the hardware of the
1438 * firmware command. The use of bit-field structure elements is purely to
1439 * remind ourselves of the field size limitations and save memory in the case
1440 * where the filter table is large.
1442 struct filter_entry {
1443 /* Administrative fields for filter. */
1444 u32 valid:1; /* filter allocated and valid */
1445 u32 locked:1; /* filter is administratively locked */
1447 u32 pending:1; /* filter action is pending firmware reply */
1448 struct filter_ctx *ctx; /* Caller's completion hook */
1449 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
1450 struct smt_entry *smt; /* Source Mac Table entry for smac */
1451 struct net_device *dev; /* Associated net device */
1452 u32 tid; /* This will store the actual tid */
1454 /* The filter itself. Most of this is a straight copy of information
1455 * provided by the extended ioctl(). Some fields are translated to
1456 * internal forms -- for instance the Ingress Queue ID passed in from
1457 * the ioctl() is translated into the Absolute Ingress Queue ID.
1459 struct ch_filter_specification fs;
1462 static inline int is_offload(const struct adapter *adap)
1464 return adap->params.offload;
1467 static inline int is_hashfilter(const struct adapter *adap)
1469 return adap->params.hash_filter;
1472 static inline int is_pci_uld(const struct adapter *adap)
1474 return adap->params.crypto;
1477 static inline int is_uld(const struct adapter *adap)
1479 return (adap->params.offload || adap->params.crypto);
1482 static inline int is_ethofld(const struct adapter *adap)
1484 return adap->params.ethofld;
1487 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1489 return readl(adap->regs + reg_addr);
1492 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1494 writel(val, adap->regs + reg_addr);
1498 static inline u64 readq(const volatile void __iomem *addr)
1500 return readl(addr) + ((u64)readl(addr + 4) << 32);
1503 static inline void writeq(u64 val, volatile void __iomem *addr)
1506 writel(val >> 32, addr + 4);
1510 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1512 return readq(adap->regs + reg_addr);
1515 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1517 writeq(val, adap->regs + reg_addr);
1521 * t4_set_hw_addr - store a port's MAC address in SW
1522 * @adapter: the adapter
1523 * @port_idx: the port index
1524 * @hw_addr: the Ethernet address
1526 * Store the Ethernet address of the given port in SW. Called by the common
1527 * code when it retrieves a port's Ethernet address from EEPROM.
1529 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1532 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1533 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1537 * netdev2pinfo - return the port_info structure associated with a net_device
1540 * Return the struct port_info associated with a net_device
1542 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1544 return netdev_priv(dev);
1548 * adap2pinfo - return the port_info of a port
1549 * @adap: the adapter
1550 * @idx: the port index
1552 * Return the port_info structure for the port of the given index.
1554 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1556 return netdev_priv(adap->port[idx]);
1560 * netdev2adap - return the adapter structure associated with a net_device
1563 * Return the struct adapter associated with a net_device
1565 static inline struct adapter *netdev2adap(const struct net_device *dev)
1567 return netdev2pinfo(dev)->adapter;
1570 /* Return a version number to identify the type of adapter. The scheme is:
1571 * - bits 0..9: chip version
1572 * - bits 10..15: chip revision
1573 * - bits 16..23: register dump version
1575 static inline unsigned int mk_adap_vers(struct adapter *ap)
1577 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1578 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1581 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1582 static inline unsigned int qtimer_val(const struct adapter *adap,
1583 const struct sge_rspq *q)
1585 unsigned int idx = q->intr_params >> 1;
1587 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1590 /* driver name used for ethtool_drvinfo */
1591 extern char cxgb4_driver_name[];
1593 void t4_os_portmod_changed(struct adapter *adap, int port_id);
1594 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1596 void t4_free_sge_resources(struct adapter *adap);
1597 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1598 irq_handler_t t4_intr_handler(struct adapter *adap);
1599 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1600 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1601 const struct pkt_gl *gl);
1602 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1603 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1604 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1605 struct net_device *dev, int intr_idx,
1606 struct sge_fl *fl, rspq_handler_t hnd,
1607 rspq_flush_handler_t flush_handler, int cong);
1608 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1609 struct net_device *dev, struct netdev_queue *netdevq,
1610 unsigned int iqid, u8 dbqt);
1611 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1612 struct net_device *dev, unsigned int iqid,
1613 unsigned int cmplqid);
1614 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1615 unsigned int cmplqid);
1616 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1617 struct net_device *dev, unsigned int iqid,
1618 unsigned int uld_type);
1619 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
1620 struct net_device *dev, u32 iqid);
1621 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq);
1622 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1623 int t4_sge_init(struct adapter *adap);
1624 void t4_sge_start(struct adapter *adap);
1625 void t4_sge_stop(struct adapter *adap);
1626 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1628 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1629 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1630 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1631 extern int dbfifo_int_thresh;
1633 #define for_each_port(adapter, iter) \
1634 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1636 static inline int is_bypass(struct adapter *adap)
1638 return adap->params.bypass;
1641 static inline int is_bypass_device(int device)
1643 /* this should be set based upon device capabilities */
1653 static inline int is_10gbt_device(int device)
1655 /* this should be set based upon device capabilities */
1666 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1668 return adap->params.vpd.cclk / 1000;
1671 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1674 return (us * adap->params.vpd.cclk) / 1000;
1677 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1680 /* add Core Clock / 2 to round ticks to nearest uS */
1681 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1682 adapter->params.vpd.cclk);
1685 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1688 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1691 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1694 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1695 int size, void *rpl, bool sleep_ok, int timeout);
1696 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1697 void *rpl, bool sleep_ok);
1699 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1700 const void *cmd, int size, void *rpl,
1703 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1707 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1708 int size, void *rpl)
1710 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1713 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1714 int size, void *rpl)
1716 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1720 * hash_mac_addr - return the hash value of a MAC address
1721 * @addr: the 48-bit Ethernet MAC address
1723 * Hashes a MAC address according to the hash function used by HW inexact
1724 * (hash) address matching.
1726 static inline int hash_mac_addr(const u8 *addr)
1728 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1729 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1737 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1739 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1740 unsigned int us, unsigned int cnt,
1741 unsigned int size, unsigned int iqe_size)
1744 cxgb4_set_rspq_intr_params(q, us, cnt);
1745 q->iqe_len = iqe_size;
1750 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1751 * @fw_mod_type: the Firmware Mofule Type
1753 * Return whether the Firmware Module Type represents a real Transceiver
1754 * Module/Cable Module Type which has been inserted.
1756 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1758 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1759 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1760 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1761 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1764 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1765 unsigned int data_reg, const u32 *vals,
1766 unsigned int nregs, unsigned int start_idx);
1767 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1768 unsigned int data_reg, u32 *vals, unsigned int nregs,
1769 unsigned int start_idx);
1770 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1772 struct fw_filter_wr;
1774 void t4_intr_enable(struct adapter *adapter);
1775 void t4_intr_disable(struct adapter *adapter);
1776 int t4_slow_intr_handler(struct adapter *adapter);
1778 int t4_wait_dev_ready(void __iomem *regs);
1780 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
1781 struct link_config *lc);
1782 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1783 unsigned int port, struct link_config *lc,
1784 u8 sleep_ok, int timeout);
1786 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1787 unsigned int port, struct link_config *lc)
1789 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1790 true, FW_CMD_MAX_TIMEOUT);
1793 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1794 unsigned int port, struct link_config *lc)
1796 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1797 false, FW_CMD_MAX_TIMEOUT);
1800 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1802 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1803 u32 t4_get_util_window(struct adapter *adap);
1804 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1806 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1807 u32 *mem_base, u32 *mem_aperture);
1808 void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1809 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1811 #define T4_MEMORY_WRITE 0
1812 #define T4_MEMORY_READ 1
1813 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1814 void *buf, int dir);
1815 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1816 u32 len, __be32 *buf)
1818 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1821 unsigned int t4_get_regs_len(struct adapter *adapter);
1822 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1824 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1825 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1826 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1827 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1828 int t4_get_pfres(struct adapter *adapter);
1829 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1830 unsigned int nwords, u32 *data, int byte_oriented);
1831 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1832 int t4_load_phy_fw(struct adapter *adap, int win,
1833 int (*phy_fw_version)(const u8 *, size_t),
1834 const u8 *phy_fw_data, size_t phy_fw_size);
1835 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1836 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1837 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1838 const u8 *fw_data, unsigned int size, int force);
1839 int t4_fl_pkt_align(struct adapter *adap);
1840 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1841 int t4_check_fw_version(struct adapter *adap);
1842 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1843 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1844 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1845 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1846 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1847 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1848 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1849 int t4_get_version_info(struct adapter *adapter);
1850 void t4_dump_version_info(struct adapter *adapter);
1851 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1852 const u8 *fw_data, unsigned int fw_size,
1853 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1854 int t4_prep_adapter(struct adapter *adapter);
1855 int t4_shutdown_adapter(struct adapter *adapter);
1857 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1858 int t4_bar2_sge_qregs(struct adapter *adapter,
1860 enum t4_bar2_qtype qtype,
1863 unsigned int *pbar2_qid);
1865 unsigned int qtimer_val(const struct adapter *adap,
1866 const struct sge_rspq *q);
1868 int t4_init_devlog_params(struct adapter *adapter);
1869 int t4_init_sge_params(struct adapter *adapter);
1870 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1871 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1872 int t4_init_rss_mode(struct adapter *adap, int mbox);
1873 int t4_init_portinfo(struct port_info *pi, int mbox,
1874 int port, int pf, int vf, u8 mac[]);
1875 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1876 int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
1878 void t4_fatal_err(struct adapter *adapter);
1879 unsigned int t4_chip_rss_size(struct adapter *adapter);
1880 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1881 int start, int n, const u16 *rspq, unsigned int nrspq);
1882 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1883 unsigned int flags);
1884 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1885 unsigned int flags, unsigned int defq);
1886 int t4_read_rss(struct adapter *adapter, u16 *entries);
1887 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1888 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1890 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1891 u32 *valp, bool sleep_ok);
1892 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1893 u32 *vfl, u32 *vfh, bool sleep_ok);
1894 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1895 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1897 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1898 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1899 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1900 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1901 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1903 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1905 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1906 unsigned int *valp);
1907 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1908 const unsigned int *valp);
1909 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1910 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1911 unsigned int *pif_req_wrptr,
1912 unsigned int *pif_rsp_wrptr);
1913 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1914 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1915 const char *t4_get_port_type_description(enum fw_port_type port_type);
1916 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1917 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1918 struct port_stats *stats,
1919 struct port_stats *offset);
1920 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1921 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1922 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1923 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1924 unsigned int mask, unsigned int val);
1925 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1926 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1928 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1930 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1932 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1934 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1935 struct tp_tcp_stats *v6, bool sleep_ok);
1936 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1937 struct tp_fcoe_stats *st, bool sleep_ok);
1938 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1939 const unsigned short *alpha, const unsigned short *beta);
1941 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1943 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1944 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1946 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1948 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1949 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1951 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1952 enum dev_master master, enum dev_state *state);
1953 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1954 int t4_early_init(struct adapter *adap, unsigned int mbox);
1955 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1956 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1957 unsigned int cache_line_size);
1958 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1959 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1960 unsigned int vf, unsigned int nparams, const u32 *params,
1962 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1963 unsigned int vf, unsigned int nparams, const u32 *params,
1965 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1966 unsigned int vf, unsigned int nparams, const u32 *params,
1967 u32 *val, int rw, bool sleep_ok);
1968 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1969 unsigned int pf, unsigned int vf,
1970 unsigned int nparams, const u32 *params,
1971 const u32 *val, int timeout);
1972 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1973 unsigned int vf, unsigned int nparams, const u32 *params,
1975 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1976 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1977 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1978 unsigned int vi, unsigned int cmask, unsigned int pmask,
1979 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1980 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1981 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1982 unsigned int *rss_size, u8 *vivld, u8 *vin);
1983 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1984 unsigned int pf, unsigned int vf,
1986 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1987 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1989 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1990 const u8 *addr, const u8 *mask, unsigned int idx,
1991 u8 lookup_type, u8 port_id, bool sleep_ok);
1992 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1994 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1995 const u8 *addr, const u8 *mask, unsigned int vni,
1996 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1998 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1999 const u8 *addr, const u8 *mask, unsigned int idx,
2000 u8 lookup_type, u8 port_id, bool sleep_ok);
2001 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
2002 unsigned int viid, bool free, unsigned int naddr,
2003 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
2004 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
2005 unsigned int viid, unsigned int naddr,
2006 const u8 **addr, bool sleep_ok);
2007 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
2008 int idx, const u8 *addr, bool persist, u8 *smt_idx);
2009 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
2010 bool ucast, u64 vec, bool sleep_ok);
2011 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
2012 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
2013 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
2014 struct port_info *pi,
2015 bool rx_en, bool tx_en, bool dcb_en);
2016 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
2017 bool rx_en, bool tx_en);
2018 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
2019 unsigned int nblinks);
2020 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2021 unsigned int mmd, unsigned int reg, u16 *valp);
2022 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2023 unsigned int mmd, unsigned int reg, u16 val);
2024 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
2025 unsigned int vf, unsigned int iqtype, unsigned int iqid,
2026 unsigned int fl0id, unsigned int fl1id);
2027 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2028 unsigned int vf, unsigned int iqtype, unsigned int iqid,
2029 unsigned int fl0id, unsigned int fl1id);
2030 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2031 unsigned int vf, unsigned int eqid);
2032 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2033 unsigned int vf, unsigned int eqid);
2034 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
2035 unsigned int vf, unsigned int eqid);
2036 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
2037 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
2039 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
2040 int t4_update_port_info(struct port_info *pi);
2041 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
2042 unsigned int *speedp, unsigned int *mtup);
2043 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
2044 void t4_db_full(struct adapter *adapter);
2045 void t4_db_dropped(struct adapter *adapter);
2046 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
2047 int filter_index, int enable);
2048 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
2049 int filter_index, int *enabled);
2050 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2052 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
2053 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
2054 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
2055 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
2056 enum ctxt_type ctype, u32 *data);
2057 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
2058 enum ctxt_type ctype, u32 *data);
2059 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
2060 u8 rateunit, u8 ratemode, u8 channel, u8 class,
2061 u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
2063 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
2064 void t4_idma_monitor_init(struct adapter *adapter,
2065 struct sge_idma_monitor_state *idma);
2066 void t4_idma_monitor(struct adapter *adapter,
2067 struct sge_idma_monitor_state *idma,
2069 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
2070 unsigned int naddr, u8 *addr);
2071 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
2072 u32 start_index, bool sleep_ok);
2073 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
2074 u32 start_index, bool sleep_ok);
2075 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
2076 u32 start_index, bool sleep_ok);
2078 void t4_uld_mem_free(struct adapter *adap);
2079 int t4_uld_mem_alloc(struct adapter *adap);
2080 void t4_uld_clean_up(struct adapter *adap);
2081 void t4_register_netevent_notifier(void);
2082 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
2083 unsigned int devid, unsigned int offset,
2084 unsigned int len, u8 *buf);
2085 int t4_load_boot(struct adapter *adap, u8 *boot_data,
2086 unsigned int boot_addr, unsigned int size);
2087 int t4_load_bootcfg(struct adapter *adap,
2088 const u8 *cfg_data, unsigned int size);
2089 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
2090 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
2091 unsigned int n, bool unmap);
2092 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq,
2094 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc);
2095 void cxgb4_ethofld_restart(unsigned long data);
2096 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp,
2097 const struct pkt_gl *si);
2098 void free_txq(struct adapter *adap, struct sge_txq *q);
2099 void cxgb4_reclaim_completed_tx(struct adapter *adap,
2100 struct sge_txq *q, bool unmap);
2101 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
2103 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
2105 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
2106 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
2107 const dma_addr_t *addr);
2108 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
2109 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
2111 int cxgb4_dcb_enabled(const struct net_device *dev);
2113 int cxgb4_thermal_init(struct adapter *adap);
2114 int cxgb4_thermal_remove(struct adapter *adap);
2115 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
2116 cpumask_var_t *aff_mask, int idx);
2117 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
2119 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
2120 int *tcam_idx, const u8 *addr,
2121 bool persistent, u8 *smt_idx);
2123 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
2124 bool free, unsigned int naddr,
2125 const u8 **addr, u16 *idx,
2126 u64 *hash, bool sleep_ok);
2127 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
2128 unsigned int naddr, const u8 **addr, bool sleep_ok);
2129 int cxgb4_init_mps_ref_entries(struct adapter *adap);
2130 void cxgb4_free_mps_ref_entries(struct adapter *adap);
2131 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
2132 const u8 *addr, const u8 *mask,
2133 unsigned int vni, unsigned int vni_mask,
2134 u8 dip_hit, u8 lookup_type, bool sleep_ok);
2135 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
2136 int idx, bool sleep_ok);
2137 int cxgb4_free_raw_mac_filt(struct adapter *adap,
2145 int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
2153 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
2154 int *tcam_idx, const u8 *addr,
2155 bool persistent, u8 *smt_idx);
2156 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap);
2157 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx);
2158 int cxgb_open(struct net_device *dev);
2159 int cxgb_close(struct net_device *dev);
2160 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q);
2161 void cxgb4_quiesce_rx(struct sge_rspq *q);
2162 int cxgb4_port_mirror_alloc(struct net_device *dev);
2163 void cxgb4_port_mirror_free(struct net_device *dev);
2164 #ifdef CONFIG_CHELSIO_TLS_DEVICE
2165 int cxgb4_set_ktls_feature(struct adapter *adap, bool enable);
2167 #endif /* __CXGB4_H__ */