2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/rhashtable.h>
50 #include <linux/etherdevice.h>
51 #include <linux/net_tstamp.h>
52 #include <linux/ptp_clock_kernel.h>
53 #include <linux/ptp_classify.h>
54 #include <linux/crash_dump.h>
55 #include <linux/thermal.h>
57 #include "t4_chip_type.h"
58 #include "cxgb4_uld.h"
61 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
62 extern struct list_head adapter_list;
63 extern struct list_head uld_list;
64 extern struct mutex uld_mutex;
66 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
67 * This is the same as calc_tx_descs() for a TSO packet with
68 * nr_frags == MAX_SKB_FRAGS.
70 #define ETHTXQ_STOP_THRES \
71 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
73 #define FW_PARAM_DEV(param) \
74 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
75 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
77 #define FW_PARAM_PFVF(param) \
78 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
79 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
80 FW_PARAMS_PARAM_Y_V(0) | \
81 FW_PARAMS_PARAM_Z_V(0))
84 MAX_NPORTS = 4, /* max # of ports */
85 SERNUM_LEN = 24, /* Serial # length */
86 EC_LEN = 16, /* E/C length */
87 ID_LEN = 16, /* ID length */
88 PN_LEN = 16, /* Part Number length */
89 MACADDR_LEN = 12, /* MAC Address length */
93 T4_REGMAP_SIZE = (160 * 1024),
94 T5_REGMAP_SIZE = (332 * 1024),
107 MEMWIN0_APERTURE = 2048,
108 MEMWIN0_BASE = 0x1b800,
109 MEMWIN1_APERTURE = 32768,
110 MEMWIN1_BASE = 0x28000,
111 MEMWIN1_BASE_T5 = 0x52000,
112 MEMWIN2_APERTURE = 65536,
113 MEMWIN2_BASE = 0x30000,
114 MEMWIN2_APERTURE_T5 = 131072,
115 MEMWIN2_BASE_T5 = 0x60000,
133 PAUSE_AUTONEG = 1 << 2
137 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
138 FEC_RS = 1 << 1, /* Reed-Solomon */
139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
143 CXGB4_ETHTOOL_FLASH_FW = 1,
144 CXGB4_ETHTOOL_FLASH_PHY = 2,
145 CXGB4_ETHTOOL_FLASH_BOOT = 3,
148 struct cxgb4_pcir_data {
149 __le32 signature; /* Signature. The string "PCIR" */
150 __le16 vendor_id; /* Vendor Identification */
151 __le16 device_id; /* Device Identification */
152 __u8 vital_product[2]; /* Pointer to Vital Product Data */
153 __u8 length[2]; /* PCIR Data Structure Length */
154 __u8 revision; /* PCIR Data Structure Revision */
155 __u8 class_code[3]; /* Class Code */
156 __u8 image_length[2]; /* Image Length. Multiple of 512B */
157 __u8 code_revision[2]; /* Revision Level of Code/Data */
163 /* BIOS boot headers */
164 struct cxgb4_pci_exp_rom_header {
165 __le16 signature; /* ROM Signature. Should be 0xaa55 */
166 __u8 reserved[22]; /* Reserved per processor Architecture data */
167 __le16 pcir_offset; /* Offset to PCI Data Structure */
170 /* Legacy PCI Expansion ROM Header */
171 struct legacy_pci_rom_hdr {
172 __u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
173 __u8 size512; /* Current Image Size in units of 512 bytes */
174 __u8 initentry_point[4];
175 __u8 cksum; /* Checksum computed on the entire Image */
176 __u8 reserved[16]; /* Reserved */
177 __le16 pcir_offset; /* Offset to PCI Data Struture */
180 #define CXGB4_HDR_CODE1 0x00
181 #define CXGB4_HDR_CODE2 0x03
182 #define CXGB4_HDR_INDI 0x80
187 BOOT_SIGNATURE = 0xaa55,
188 BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header),
189 BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC,
190 PCIR_SIGNATURE = 0x52494350
194 u64 tx_octets; /* total # of octets in good frames */
195 u64 tx_frames; /* all good frames */
196 u64 tx_bcast_frames; /* all broadcast frames */
197 u64 tx_mcast_frames; /* all multicast frames */
198 u64 tx_ucast_frames; /* all unicast frames */
199 u64 tx_error_frames; /* all error frames */
201 u64 tx_frames_64; /* # of Tx frames in a particular range */
202 u64 tx_frames_65_127;
203 u64 tx_frames_128_255;
204 u64 tx_frames_256_511;
205 u64 tx_frames_512_1023;
206 u64 tx_frames_1024_1518;
207 u64 tx_frames_1519_max;
209 u64 tx_drop; /* # of dropped Tx frames */
210 u64 tx_pause; /* # of transmitted pause frames */
211 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
212 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
213 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
214 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
215 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
216 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
217 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
218 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
220 u64 rx_octets; /* total # of octets in good frames */
221 u64 rx_frames; /* all good frames */
222 u64 rx_bcast_frames; /* all broadcast frames */
223 u64 rx_mcast_frames; /* all multicast frames */
224 u64 rx_ucast_frames; /* all unicast frames */
225 u64 rx_too_long; /* # of frames exceeding MTU */
226 u64 rx_jabber; /* # of jabber frames */
227 u64 rx_fcs_err; /* # of received frames with bad FCS */
228 u64 rx_len_err; /* # of received frames with length error */
229 u64 rx_symbol_err; /* symbol errors */
230 u64 rx_runt; /* # of short frames */
232 u64 rx_frames_64; /* # of Rx frames in a particular range */
233 u64 rx_frames_65_127;
234 u64 rx_frames_128_255;
235 u64 rx_frames_256_511;
236 u64 rx_frames_512_1023;
237 u64 rx_frames_1024_1518;
238 u64 rx_frames_1519_max;
240 u64 rx_pause; /* # of received pause frames */
241 u64 rx_ppp0; /* # of received PPP prio 0 frames */
242 u64 rx_ppp1; /* # of received PPP prio 1 frames */
243 u64 rx_ppp2; /* # of received PPP prio 2 frames */
244 u64 rx_ppp3; /* # of received PPP prio 3 frames */
245 u64 rx_ppp4; /* # of received PPP prio 4 frames */
246 u64 rx_ppp5; /* # of received PPP prio 5 frames */
247 u64 rx_ppp6; /* # of received PPP prio 6 frames */
248 u64 rx_ppp7; /* # of received PPP prio 7 frames */
250 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
251 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
252 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
253 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
254 u64 rx_trunc0; /* buffer-group 0 truncated packets */
255 u64 rx_trunc1; /* buffer-group 1 truncated packets */
256 u64 rx_trunc2; /* buffer-group 2 truncated packets */
257 u64 rx_trunc3; /* buffer-group 3 truncated packets */
260 struct lb_port_stats {
273 u64 frames_1024_1518;
288 struct tp_tcp_stats {
292 u64 tcp_retrans_segs;
295 struct tp_usm_stats {
301 struct tp_fcoe_stats {
307 struct tp_err_stats {
311 u32 tnl_cong_drops[4];
312 u32 ofld_chan_drops[4];
314 u32 ofld_vlan_drops[4];
320 struct tp_cpl_stats {
325 struct tp_rdma_stats {
331 u32 hps; /* host page size for our PF/VF */
332 u32 eq_qpp; /* egress queues/page for our PF/VF */
333 u32 iq_qpp; /* egress queues/page for our PF/VF */
337 unsigned int tre; /* log2 of core clocks per TP tick */
338 unsigned int la_mask; /* what events are recorded by TP LA */
339 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
342 uint32_t dack_re; /* DACK timer resolution */
343 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
345 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
347 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
349 /* cached TP_OUT_CONFIG compressed error vector
350 * and passing outer header info for encapsulated packets.
354 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
355 * subset of the set of fields which may be present in the Compressed
356 * Filter Tuple portion of filters and TCP TCB connections. The
357 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
358 * Since a variable number of fields may or may not be present, their
359 * shifted field positions within the Compressed Filter Tuple may
360 * vary, or not even be present if the field isn't selected in
361 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
362 * places we store their offsets here, or a -1 if the field isn't
376 u64 hash_filter_mask;
382 u8 sn[SERNUM_LEN + 1];
385 u8 na[MACADDR_LEN + 1];
388 /* Maximum resources provisioned for a PCI PF.
390 struct pf_resources {
391 unsigned int nvi; /* N virtual interfaces */
392 unsigned int neq; /* N egress Qs */
393 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
394 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
395 unsigned int niq; /* N ingress Qs */
396 unsigned int tc; /* PCI-E traffic class */
397 unsigned int pmask; /* port access rights mask */
398 unsigned int nexactf; /* N exact MPS filters */
399 unsigned int r_caps; /* read capabilities */
400 unsigned int wx_caps; /* write/execute capabilities */
404 unsigned int vpd_cap_addr;
409 struct devlog_params {
410 u32 memtype; /* which memory (EDC0, EDC1, MC) */
411 u32 start; /* start of log in firmware memory */
412 u32 size; /* size of log */
415 /* Stores chip specific parameters */
416 struct arch_specific_params {
419 u8 cng_ch_bits_log; /* congestion channel map bits width */
426 struct adapter_params {
427 struct sge_params sge;
429 struct vpd_params vpd;
430 struct pf_resources pfres;
431 struct pci_params pci;
432 struct devlog_params devlog;
433 enum pcie_memwin drv_memwin;
435 unsigned int cim_la_size;
437 unsigned int sf_size; /* serial flash size in bytes */
438 unsigned int sf_nsec; /* # of flash sectors */
440 unsigned int fw_vers; /* firmware version */
441 unsigned int bs_vers; /* bootstrap version */
442 unsigned int tp_vers; /* TP microcode version */
443 unsigned int er_vers; /* expansion ROM version */
444 unsigned int scfg_vers; /* Serial Configuration version */
445 unsigned int vpd_vers; /* VPD Version */
448 unsigned short mtus[NMTUS];
449 unsigned short a_wnd[NCCTRL_WIN];
450 unsigned short b_wnd[NCCTRL_WIN];
452 unsigned char nports; /* # of ethernet ports */
453 unsigned char portvec;
454 enum chip_type chip; /* chip code */
455 struct arch_specific_params arch; /* chip specific params */
456 unsigned char offload;
457 unsigned char crypto; /* HW capability for crypto */
458 unsigned char ethofld; /* QoS support */
460 unsigned char bypass;
461 unsigned char hash_filter;
463 unsigned int ofldq_wr_cred;
464 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
466 unsigned int nsched_cls; /* number of traffic classes */
467 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
468 unsigned int max_ird_adapter; /* Max read depth per adapter */
469 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
470 u8 fw_caps_support; /* 32-bit Port Capabilities */
471 bool filter2_wr_support; /* FW support for FILTER2_WR */
472 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
474 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
477 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
478 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
479 bool write_cmpl_support; /* FW supports WRITE_CMPL */
482 /* State needed to monitor the forward progress of SGE Ingress DMA activities
483 * and possible hangs.
485 struct sge_idma_monitor_state {
486 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
487 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
488 unsigned int idma_state[2]; /* IDMA Hang detect state */
489 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
490 unsigned int idma_warn[2]; /* time to warning in HZ */
493 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
494 * The access and execute times are signed in order to accommodate negative
498 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
499 u64 timestamp; /* OS-dependent timestamp */
500 u32 seqno; /* sequence number */
501 s16 access; /* time (ms) to access mailbox */
502 s16 execute; /* time (ms) to execute */
505 struct mbox_cmd_log {
506 unsigned int size; /* number of entries in the log */
507 unsigned int cursor; /* next position in the log to write */
508 u32 seqno; /* next sequence number */
509 /* variable length mailbox command log starts here */
512 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
513 * return a pointer to the specified entry.
515 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
516 unsigned int entry_idx)
518 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
521 #define FW_VERSION(chip) ( \
522 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
523 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
524 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
525 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
526 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
532 struct fw_hdr fw_hdr;
535 struct trace_params {
536 u32 data[TRACE_LEN / 4];
537 u32 mask[TRACE_LEN / 4];
538 unsigned short snap_len;
539 unsigned short min_len;
540 unsigned char skip_ofst;
541 unsigned char skip_len;
542 unsigned char invert;
546 struct cxgb4_fw_data {
551 /* Firmware Port Capabilities types. */
553 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
554 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
557 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
558 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
559 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
563 fw_port_cap32_t pcaps; /* link capabilities */
564 fw_port_cap32_t def_acaps; /* default advertised capabilities */
565 fw_port_cap32_t acaps; /* advertised capabilities */
566 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
568 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
569 unsigned int speed; /* actual link speed (Mb/s) */
571 enum cc_pause requested_fc; /* flow control user has requested */
572 enum cc_pause fc; /* actual link flow control */
573 enum cc_pause advertised_fc; /* actual advertised flow control */
575 enum cc_fec requested_fec; /* Forward Error Correction: */
576 enum cc_fec fec; /* requested and actual in use */
578 unsigned char autoneg; /* autonegotiating? */
580 unsigned char link_ok; /* link up? */
581 unsigned char link_down_rc; /* link down reason */
583 bool new_module; /* ->OS Transceiver Module inserted */
584 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
587 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
590 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
591 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
592 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
596 MAX_TXQ_ENTRIES = 16384,
597 MAX_CTRL_TXQ_ENTRIES = 1024,
598 MAX_RSPQ_ENTRIES = 16384,
599 MAX_RX_BUFFERS = 16384,
600 MIN_TXQ_ENTRIES = 32,
601 MIN_CTRL_TXQ_ENTRIES = 32,
602 MIN_RSPQ_ENTRIES = 128,
607 MAX_TXQ_DESC_SIZE = 64,
608 MAX_RXQ_DESC_SIZE = 128,
609 MAX_FL_DESC_SIZE = 8,
610 MAX_CTRL_TXQ_DESC_SIZE = 64,
614 INGQ_EXTRAS = 2, /* firmware event queue and */
615 /* forwarded interrupts */
616 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
620 PRIV_FLAG_PORT_TX_VM_BIT,
623 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
625 #define PRIV_FLAGS_ADAP 0
626 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
631 #include "cxgb4_dcb.h"
633 #ifdef CONFIG_CHELSIO_T4_FCOE
634 #include "cxgb4_fcoe.h"
635 #endif /* CONFIG_CHELSIO_T4_FCOE */
638 struct adapter *adapter;
640 int xact_addr_filt; /* index of exact MAC address filter */
641 u16 rss_size; /* size of VI's RSS table slice */
643 enum fw_port_type port_type;
647 u8 lport; /* associated offload logical port */
648 u8 nqsets; /* # of qsets */
649 u8 first_qset; /* index of first qset */
651 struct link_config link_cfg;
653 struct port_stats stats_base;
654 #ifdef CONFIG_CHELSIO_T4_DCB
655 struct port_dcb_info dcb; /* Data Center Bridging support */
657 #ifdef CONFIG_CHELSIO_T4_FCOE
658 struct cxgb_fcoe fcoe;
659 #endif /* CONFIG_CHELSIO_T4_FCOE */
660 bool rxtstamp; /* Enable TS */
661 struct hwtstamp_config tstamp_config;
663 struct sched_table *sched_tbl;
666 /* viid and smt fields either returned by fw
667 * or decoded by parsing viid by driver.
674 bool tc_block_shared;
680 enum { /* adapter flags */
681 CXGB4_FULL_INIT_DONE = (1 << 0),
682 CXGB4_DEV_ENABLED = (1 << 1),
683 CXGB4_USING_MSI = (1 << 2),
684 CXGB4_USING_MSIX = (1 << 3),
685 CXGB4_FW_OK = (1 << 4),
686 CXGB4_RSS_TNLALLLOOKUP = (1 << 5),
687 CXGB4_USING_SOFT_PARAMS = (1 << 6),
688 CXGB4_MASTER_PF = (1 << 7),
689 CXGB4_FW_OFLD_CONN = (1 << 9),
690 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10),
691 CXGB4_SHUTTING_DOWN = (1 << 11),
692 CXGB4_SGE_DBQ_TIMER = (1 << 12),
696 ULP_CRYPTO_LOOKASIDE = 1 << 0,
697 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
698 ULP_CRYPTO_KTLS_INLINE = 1 << 3,
703 struct sge_fl { /* SGE free-buffer queue state */
704 unsigned int avail; /* # of available Rx buffers */
705 unsigned int pend_cred; /* new buffers since last FL DB ring */
706 unsigned int cidx; /* consumer index */
707 unsigned int pidx; /* producer index */
708 unsigned long alloc_failed; /* # of times buffer allocation failed */
709 unsigned long large_alloc_failed;
710 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
711 unsigned long low; /* # of times momentarily starving */
712 unsigned long starving;
714 unsigned int cntxt_id; /* SGE context id for the free list */
715 unsigned int size; /* capacity of free list */
716 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
717 __be64 *desc; /* address of HW Rx descriptor ring */
718 dma_addr_t addr; /* bus address of HW ring start */
719 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
720 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
723 /* A packet gather list */
725 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
726 struct page_frag frags[MAX_SKB_FRAGS];
727 void *va; /* virtual address of first byte */
728 unsigned int nfrags; /* # of fragments */
729 unsigned int tot_len; /* total length of fragments */
732 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
733 const struct pkt_gl *gl);
734 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
735 /* LRO related declarations for ULD */
737 #define MAX_LRO_SESSIONS 64
738 u8 lro_session_cnt; /* # of sessions to aggregate */
739 unsigned long lro_pkts; /* # of LRO super packets */
740 unsigned long lro_merged; /* # of wire packets merged by LRO */
741 struct sk_buff_head lroq; /* list of aggregated sessions */
744 struct sge_rspq { /* state for an SGE response queue */
745 struct napi_struct napi;
746 const __be64 *cur_desc; /* current descriptor in queue */
747 unsigned int cidx; /* consumer index */
748 u8 gen; /* current generation bit */
749 u8 intr_params; /* interrupt holdoff parameters */
750 u8 next_intr_params; /* holdoff params for next interrupt */
752 u8 pktcnt_idx; /* interrupt packet threshold */
753 u8 uld; /* ULD handling this queue */
754 u8 idx; /* queue index within its group */
755 int offset; /* offset into current Rx buffer */
756 u16 cntxt_id; /* SGE context id for the response q */
757 u16 abs_id; /* absolute SGE id for the response q */
758 __be64 *desc; /* address of HW response ring */
759 dma_addr_t phys_addr; /* physical address of the ring */
760 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
761 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
762 unsigned int iqe_len; /* entry size */
763 unsigned int size; /* capacity of response queue */
764 struct adapter *adap;
765 struct net_device *netdev; /* associated net device */
766 rspq_handler_t handler;
767 rspq_flush_handler_t flush_handler;
768 struct t4_lro_mgr lro_mgr;
771 struct sge_eth_stats { /* Ethernet queue statistics */
772 unsigned long pkts; /* # of ethernet packets */
773 unsigned long lro_pkts; /* # of LRO super packets */
774 unsigned long lro_merged; /* # of wire packets merged by LRO */
775 unsigned long rx_cso; /* # of Rx checksum offloads */
776 unsigned long vlan_ex; /* # of Rx VLAN extractions */
777 unsigned long rx_drops; /* # of packets dropped due to no mem */
778 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */
781 struct sge_eth_rxq { /* SW Ethernet Rx queue */
782 struct sge_rspq rspq;
784 struct sge_eth_stats stats;
785 struct msix_info *msix;
786 } ____cacheline_aligned_in_smp;
788 struct sge_ofld_stats { /* offload queue statistics */
789 unsigned long pkts; /* # of packets */
790 unsigned long imm; /* # of immediate-data packets */
791 unsigned long an; /* # of asynchronous notifications */
792 unsigned long nomem; /* # of responses deferred due to no mem */
795 struct sge_ofld_rxq { /* SW offload Rx queue */
796 struct sge_rspq rspq;
798 struct sge_ofld_stats stats;
799 struct msix_info *msix;
800 } ____cacheline_aligned_in_smp;
809 struct sk_buff *skb; /* SKB to free after getting completion */
810 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */
814 unsigned int in_use; /* # of in-use Tx descriptors */
815 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */
816 unsigned int size; /* # of descriptors */
817 unsigned int cidx; /* SW consumer index */
818 unsigned int pidx; /* producer index */
819 unsigned long stops; /* # of times q has been stopped */
820 unsigned long restarts; /* # of queue restarts */
821 unsigned int cntxt_id; /* SGE context id for the Tx q */
822 struct tx_desc *desc; /* address of HW Tx descriptor ring */
823 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
824 struct sge_qstat *stat; /* queue status entry */
825 dma_addr_t phys_addr; /* physical address of the ring */
828 unsigned short db_pidx;
829 unsigned short db_pidx_inc;
830 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
831 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
834 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
836 struct netdev_queue *txq; /* associated netdev TX queue */
837 #ifdef CONFIG_CHELSIO_T4_DCB
838 u8 dcb_prio; /* DCB Priority bound to queue */
840 u8 dbqt; /* SGE Doorbell Queue Timer in use */
841 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */
842 unsigned long tso; /* # of TSO requests */
843 unsigned long uso; /* # of USO requests */
844 unsigned long tx_cso; /* # of Tx checksum offloads */
845 unsigned long vlan_ins; /* # of Tx VLAN insertions */
846 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
847 } ____cacheline_aligned_in_smp;
849 struct sge_uld_txq { /* state for an SGE offload Tx queue */
851 struct adapter *adap;
852 struct sk_buff_head sendq; /* list of backpressured packets */
853 struct tasklet_struct qresume_tsk; /* restarts the queue */
854 bool service_ofldq_running; /* service_ofldq() is processing sendq */
855 u8 full; /* the Tx ring is full */
856 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
857 } ____cacheline_aligned_in_smp;
859 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
861 struct adapter *adap;
862 struct sk_buff_head sendq; /* list of backpressured packets */
863 struct tasklet_struct qresume_tsk; /* restarts the queue */
864 u8 full; /* the Tx ring is full */
865 } ____cacheline_aligned_in_smp;
867 struct sge_uld_rxq_info {
868 char name[IFNAMSIZ]; /* name of ULD driver */
869 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
870 u16 *rspq_id; /* response queue id's of rxq */
871 u16 nrxq; /* # of ingress uld queues */
872 u16 nciq; /* # of completion queues */
873 u8 uld; /* uld type */
876 struct sge_uld_txq_info {
877 struct sge_uld_txq *uldtxq; /* Txq's for ULD */
878 atomic_t users; /* num users */
879 u16 ntxq; /* # of egress uld queues */
882 /* struct to maintain ULD list to reallocate ULD resources on hotplug */
883 struct cxgb4_uld_list {
884 struct cxgb4_uld_info uld_info;
885 struct list_head list_node;
886 enum cxgb4_uld uld_type;
889 enum sge_eosw_state {
890 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */
891 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */
892 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */
893 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */
894 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */
895 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */
898 struct sge_eosw_txq {
899 spinlock_t lock; /* Per queue lock to synchronize completions */
900 enum sge_eosw_state state; /* Current ETHOFLD State */
901 struct tx_sw_desc *desc; /* Descriptor ring to hold packets */
902 u32 ndesc; /* Number of descriptors */
903 u32 pidx; /* Current Producer Index */
904 u32 last_pidx; /* Last successfully transmitted Producer Index */
905 u32 cidx; /* Current Consumer Index */
906 u32 last_cidx; /* Last successfully reclaimed Consumer Index */
907 u32 flowc_idx; /* Descriptor containing a FLOWC request */
908 u32 inuse; /* Number of packets held in ring */
910 u32 cred; /* Current available credits */
911 u32 ncompl; /* # of completions posted */
912 u32 last_compl; /* # of credits consumed since last completion req */
914 u32 eotid; /* Index into EOTID table in software */
915 u32 hwtid; /* Hardware EOTID index */
917 u32 hwqid; /* Underlying hardware queue index */
918 struct net_device *netdev; /* Pointer to netdevice */
919 struct tasklet_struct qresume_tsk; /* Restarts the queue */
920 struct completion completion; /* completion for FLOWC rendezvous */
923 struct sge_eohw_txq {
924 spinlock_t lock; /* Per queue lock */
925 struct sge_txq q; /* HW Txq */
926 struct adapter *adap; /* Backpointer to adapter */
927 unsigned long tso; /* # of TSO requests */
928 unsigned long uso; /* # of USO requests */
929 unsigned long tx_cso; /* # of Tx checksum offloads */
930 unsigned long vlan_ins; /* # of Tx VLAN insertions */
931 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
935 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
936 struct sge_eth_txq ptptxq;
937 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
939 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
940 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
941 struct sge_uld_rxq_info **uld_rxq_info;
942 struct sge_uld_txq_info **uld_txq_info;
944 struct sge_rspq intrq ____cacheline_aligned_in_smp;
945 spinlock_t intrq_lock;
947 struct sge_eohw_txq *eohw_txq;
948 struct sge_ofld_rxq *eohw_rxq;
950 u16 max_ethqsets; /* # of available Ethernet queue sets */
951 u16 ethqsets; /* # of active Ethernet queue sets */
952 u16 ethtxq_rover; /* Tx queue to clean up next */
953 u16 ofldqsets; /* # of active ofld queue sets */
954 u16 nqs_per_uld; /* # of Rx queues per ULD */
955 u16 eoqsets; /* # of ETHOFLD queues */
957 u16 timer_val[SGE_NTIMERS];
958 u8 counter_val[SGE_NCOUNTERS];
960 u16 dbqtimer_val[SGE_NDBQTIMERS];
961 u32 fl_pg_order; /* large page allocation size */
962 u32 stat_len; /* length of status page at ring end */
963 u32 pktshift; /* padding between CPL & packet data */
964 u32 fl_align; /* response queue message alignment */
965 u32 fl_starve_thres; /* Free List starvation threshold */
967 struct sge_idma_monitor_state idma_monitor;
968 unsigned int egr_start;
970 unsigned int ingr_start;
971 unsigned int ingr_sz;
972 void **egr_map; /* qid->queue egress queue map */
973 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
974 unsigned long *starving_fl;
975 unsigned long *txq_maperr;
976 unsigned long *blocked_fl;
977 struct timer_list rx_timer; /* refills starving FLs */
978 struct timer_list tx_timer; /* checks Tx queues */
980 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */
981 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */
984 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
985 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
989 #ifdef CONFIG_PCI_IOV
991 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
992 * Configuration initialization for T5 only has SR-IOV functionality enabled
993 * on PF0-3 in order to simplify everything.
995 #define NUM_OF_PF_WITH_SRIOV 4
999 struct doorbell_stats {
1005 struct hash_mac_addr {
1006 struct list_head list;
1008 unsigned int iface_mac;
1012 unsigned long *msix_bmap;
1013 unsigned int mapsize;
1014 spinlock_t lock; /* lock for acquiring bitmap */
1019 char desc[IFNAMSIZ + 10];
1021 cpumask_var_t aff_mask;
1025 unsigned char vf_mac_addr[ETH_ALEN];
1026 unsigned int tx_rate;
1033 HMA_DMA_MAPPED_FLAG = 1
1037 unsigned char flags;
1038 struct sg_table *sgt;
1039 dma_addr_t *phy_addr; /* physical address of the page */
1043 struct list_head list;
1046 #if IS_ENABLED(CONFIG_THERMAL)
1048 struct thermal_zone_device *tzdev;
1054 struct mps_entries_ref {
1055 struct list_head list;
1066 struct pci_dev *pdev;
1067 struct device *pdev_dev;
1072 unsigned int adap_idx;
1073 enum chip_type chip;
1082 struct adapter_params params;
1083 struct cxgb4_virt_res vres;
1084 unsigned int swintr;
1086 /* MSI-X Info for NIC and OFLD queues */
1087 struct msix_info *msix_info;
1088 struct msix_bmap msix_bmap;
1090 struct doorbell_stats db_stats;
1093 struct net_device *port[MAX_NPORTS];
1094 u8 chan_map[NCHAN]; /* channel -> port map */
1096 struct vf_info *vfinfo;
1100 unsigned int l2t_start;
1101 unsigned int l2t_end;
1102 struct l2t_data *l2t;
1103 unsigned int clipt_start;
1104 unsigned int clipt_end;
1105 struct clip_tbl *clipt;
1106 unsigned int rawf_start;
1107 unsigned int rawf_cnt;
1108 struct smt_data *smt;
1109 struct cxgb4_uld_info *uld;
1110 void *uld_handle[CXGB4_ULD_MAX];
1111 unsigned int num_uld;
1112 unsigned int num_ofld_uld;
1113 struct list_head list_node;
1114 struct list_head rcu_node;
1115 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
1116 struct list_head mps_ref;
1117 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */
1121 struct tid_info tids;
1122 void **tid_release_head;
1123 spinlock_t tid_release_lock;
1124 struct workqueue_struct *workq;
1125 struct work_struct tid_release_task;
1126 struct work_struct db_full_task;
1127 struct work_struct db_drop_task;
1128 struct work_struct fatal_err_notify_task;
1129 bool tid_release_task_busy;
1131 /* lock for mailbox cmd list */
1132 spinlock_t mbox_lock;
1133 struct mbox_list mlist;
1135 /* support for mailbox command/reply logging */
1136 #define T4_OS_LOG_MBOX_CMDS 256
1137 struct mbox_cmd_log *mbox_log;
1139 struct mutex uld_mutex;
1141 struct dentry *debugfs_root;
1142 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
1143 bool trace_rss; /* 1 implies that different RSS flit per filter is
1144 * used per filter else if 0 default RSS flit is
1145 * used for all 4 filters.
1148 struct ptp_clock *ptp_clock;
1149 struct ptp_clock_info ptp_clock_info;
1150 struct sk_buff *ptp_tx_skb;
1152 spinlock_t ptp_lock;
1153 spinlock_t stats_lock;
1154 spinlock_t win0_lock ____cacheline_aligned_in_smp;
1156 /* TC u32 offload */
1157 struct cxgb4_tc_u32_table *tc_u32;
1158 struct chcr_ktls chcr_ktls;
1159 struct chcr_stats_debug chcr_stats;
1161 /* TC flower offload */
1162 bool tc_flower_initialized;
1163 struct rhashtable flower_tbl;
1164 struct rhashtable_params flower_ht_params;
1165 struct timer_list flower_stats_timer;
1166 struct work_struct flower_stats_work;
1169 struct ethtool_dump eth_dump;
1172 struct hma_data hma;
1174 struct srq_data *srq;
1176 /* Dump buffer for collecting logs in kdump kernel */
1177 struct vmcoredd_data vmcoredd;
1178 #if IS_ENABLED(CONFIG_THERMAL)
1179 struct ch_thermal ch_thermal;
1182 /* TC MQPRIO offload */
1183 struct cxgb4_tc_mqprio *tc_mqprio;
1185 /* TC MATCHALL classifier offload */
1186 struct cxgb4_tc_matchall *tc_matchall;
1189 /* Support for "sched-class" command to allow a TX Scheduling Class to be
1190 * programmed with various parameters.
1192 struct ch_sched_params {
1193 u8 type; /* packet or flow */
1196 u8 level; /* scheduler hierarchy level */
1197 u8 mode; /* per-class or per-flow */
1198 u8 rateunit; /* bit or packet rate */
1199 u8 ratemode; /* %port relative or kbps absolute */
1200 u8 channel; /* scheduler channel [0..N] */
1201 u8 class; /* scheduler class [0..N] */
1202 u32 minrate; /* minimum rate */
1203 u32 maxrate; /* maximum rate */
1204 u16 weight; /* percent weight */
1205 u16 pktsize; /* average packet size */
1206 u16 burstsize; /* burst buffer size */
1212 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
1216 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
1217 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */
1221 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
1222 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */
1226 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
1230 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
1233 /* Support for "sched_queue" command to allow one or more NIC TX Queues
1234 * to be bound to a TX Scheduling Class.
1236 struct ch_sched_queue {
1237 s8 queue; /* queue index */
1238 s8 class; /* class index */
1241 /* Support for "sched_flowc" command to allow one or more FLOWC
1242 * to be bound to a TX Scheduling Class.
1244 struct ch_sched_flowc {
1245 s32 tid; /* TID to bind */
1246 s8 class; /* class index */
1249 /* Defined bit width of user definable filter tuples
1251 #define ETHTYPE_BITWIDTH 16
1252 #define FRAG_BITWIDTH 1
1253 #define MACIDX_BITWIDTH 9
1254 #define FCOE_BITWIDTH 1
1255 #define IPORT_BITWIDTH 3
1256 #define MATCHTYPE_BITWIDTH 3
1257 #define PROTO_BITWIDTH 8
1258 #define TOS_BITWIDTH 8
1259 #define PF_BITWIDTH 8
1260 #define VF_BITWIDTH 8
1261 #define IVLAN_BITWIDTH 16
1262 #define OVLAN_BITWIDTH 16
1263 #define ENCAP_VNI_BITWIDTH 24
1265 /* Filter matching rules. These consist of a set of ingress packet field
1266 * (value, mask) tuples. The associated ingress packet field matches the
1267 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
1268 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
1269 * matches an ingress packet when all of the individual individual field
1270 * matching rules are true.
1272 * Partial field masks are always valid, however, while it may be easy to
1273 * understand their meanings for some fields (e.g. IP address to match a
1274 * subnet), for others making sensible partial masks is less intuitive (e.g.
1275 * MPS match type) ...
1277 * Most of the following data structures are modeled on T4 capabilities.
1278 * Drivers for earlier chips use the subsets which make sense for those chips.
1279 * We really need to come up with a hardware-independent mechanism to
1280 * represent hardware filter capabilities ...
1282 struct ch_filter_tuple {
1283 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
1284 * register selects which of these fields will participate in the
1285 * filter match rules -- up to a maximum of 36 bits. Because
1286 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1289 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
1290 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
1291 uint32_t ivlan_vld:1; /* inner VLAN valid */
1292 uint32_t ovlan_vld:1; /* outer VLAN valid */
1293 uint32_t pfvf_vld:1; /* PF/VF valid */
1294 uint32_t encap_vld:1; /* Encapsulation valid */
1295 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
1296 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
1297 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
1298 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
1299 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
1300 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
1301 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1302 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1303 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
1304 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
1305 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
1307 /* Uncompressed header matching field rules. These are always
1308 * available for field rules.
1310 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
1311 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
1312 uint16_t lport; /* local port */
1313 uint16_t fport; /* foreign port */
1316 /* A filter ioctl command.
1318 struct ch_filter_specification {
1319 /* Administrative fields for filter.
1321 uint32_t hitcnts:1; /* count filter hits in TCB */
1322 uint32_t prio:1; /* filter has priority over active/server */
1324 /* Fundamental filter typing. This is the one element of filter
1325 * matching that doesn't exist as a (value, mask) tuple.
1327 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
1328 u32 hash:1; /* 0 => wild-card, 1 => exact-match */
1330 /* Packet dispatch information. Ingress packets which match the
1331 * filter rules will be dropped, passed to the host or switched back
1332 * out as egress packets.
1334 uint32_t action:2; /* drop, pass, switch */
1336 uint32_t rpttid:1; /* report TID in RSS hash field */
1338 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1339 uint32_t iq:10; /* ingress queue */
1341 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1342 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1343 /* 1 => TCB contains IQ ID */
1345 /* Switch proxy/rewrite fields. An ingress packet which matches a
1346 * filter with "switch" set will be looped back out as an egress
1347 * packet -- potentially with some Ethernet header rewriting.
1349 uint32_t eport:2; /* egress port to switch packet out */
1350 uint32_t newdmac:1; /* rewrite destination MAC address */
1351 uint32_t newsmac:1; /* rewrite source MAC address */
1352 uint32_t newvlan:2; /* rewrite VLAN Tag */
1353 uint32_t nat_mode:3; /* specify NAT operation mode */
1354 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1355 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1356 uint16_t vlan; /* VLAN Tag to insert */
1358 u8 nat_lip[16]; /* local IP to use after NAT'ing */
1359 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
1360 u16 nat_lport; /* local port to use after NAT'ing */
1361 u16 nat_fport; /* foreign port to use after NAT'ing */
1363 u32 tc_prio; /* TC's filter priority index */
1364 u64 tc_cookie; /* Unique cookie identifying TC rules */
1366 /* reservation for future additions */
1369 /* Filter rule value/mask pairs.
1371 struct ch_filter_tuple val;
1372 struct ch_filter_tuple mask;
1376 FILTER_PASS = 0, /* default */
1382 VLAN_NOCHANGE = 0, /* default */
1389 NAT_MODE_NONE = 0, /* No NAT performed */
1390 NAT_MODE_DIP, /* NAT on Dst IP */
1391 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */
1392 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */
1393 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */
1394 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */
1395 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */
1396 NAT_MODE_ALL /* NAT on entire 4-tuple */
1399 /* Host shadow copy of ingress filter entry. This is in host native format
1400 * and doesn't match the ordering or bit order, etc. of the hardware of the
1401 * firmware command. The use of bit-field structure elements is purely to
1402 * remind ourselves of the field size limitations and save memory in the case
1403 * where the filter table is large.
1405 struct filter_entry {
1406 /* Administrative fields for filter. */
1407 u32 valid:1; /* filter allocated and valid */
1408 u32 locked:1; /* filter is administratively locked */
1410 u32 pending:1; /* filter action is pending firmware reply */
1411 struct filter_ctx *ctx; /* Caller's completion hook */
1412 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
1413 struct smt_entry *smt; /* Source Mac Table entry for smac */
1414 struct net_device *dev; /* Associated net device */
1415 u32 tid; /* This will store the actual tid */
1417 /* The filter itself. Most of this is a straight copy of information
1418 * provided by the extended ioctl(). Some fields are translated to
1419 * internal forms -- for instance the Ingress Queue ID passed in from
1420 * the ioctl() is translated into the Absolute Ingress Queue ID.
1422 struct ch_filter_specification fs;
1425 static inline int is_offload(const struct adapter *adap)
1427 return adap->params.offload;
1430 static inline int is_hashfilter(const struct adapter *adap)
1432 return adap->params.hash_filter;
1435 static inline int is_pci_uld(const struct adapter *adap)
1437 return adap->params.crypto;
1440 static inline int is_uld(const struct adapter *adap)
1442 return (adap->params.offload || adap->params.crypto);
1445 static inline int is_ethofld(const struct adapter *adap)
1447 return adap->params.ethofld;
1450 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1452 return readl(adap->regs + reg_addr);
1455 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1457 writel(val, adap->regs + reg_addr);
1461 static inline u64 readq(const volatile void __iomem *addr)
1463 return readl(addr) + ((u64)readl(addr + 4) << 32);
1466 static inline void writeq(u64 val, volatile void __iomem *addr)
1469 writel(val >> 32, addr + 4);
1473 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1475 return readq(adap->regs + reg_addr);
1478 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1480 writeq(val, adap->regs + reg_addr);
1484 * t4_set_hw_addr - store a port's MAC address in SW
1485 * @adapter: the adapter
1486 * @port_idx: the port index
1487 * @hw_addr: the Ethernet address
1489 * Store the Ethernet address of the given port in SW. Called by the common
1490 * code when it retrieves a port's Ethernet address from EEPROM.
1492 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1495 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1496 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1500 * netdev2pinfo - return the port_info structure associated with a net_device
1503 * Return the struct port_info associated with a net_device
1505 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1507 return netdev_priv(dev);
1511 * adap2pinfo - return the port_info of a port
1512 * @adap: the adapter
1513 * @idx: the port index
1515 * Return the port_info structure for the port of the given index.
1517 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1519 return netdev_priv(adap->port[idx]);
1523 * netdev2adap - return the adapter structure associated with a net_device
1526 * Return the struct adapter associated with a net_device
1528 static inline struct adapter *netdev2adap(const struct net_device *dev)
1530 return netdev2pinfo(dev)->adapter;
1533 /* Return a version number to identify the type of adapter. The scheme is:
1534 * - bits 0..9: chip version
1535 * - bits 10..15: chip revision
1536 * - bits 16..23: register dump version
1538 static inline unsigned int mk_adap_vers(struct adapter *ap)
1540 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1541 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1544 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1545 static inline unsigned int qtimer_val(const struct adapter *adap,
1546 const struct sge_rspq *q)
1548 unsigned int idx = q->intr_params >> 1;
1550 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1553 /* driver name used for ethtool_drvinfo */
1554 extern char cxgb4_driver_name[];
1556 void t4_os_portmod_changed(struct adapter *adap, int port_id);
1557 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1559 void t4_free_sge_resources(struct adapter *adap);
1560 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1561 irq_handler_t t4_intr_handler(struct adapter *adap);
1562 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1563 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1564 const struct pkt_gl *gl);
1565 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1566 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1567 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1568 struct net_device *dev, int intr_idx,
1569 struct sge_fl *fl, rspq_handler_t hnd,
1570 rspq_flush_handler_t flush_handler, int cong);
1571 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1572 struct net_device *dev, struct netdev_queue *netdevq,
1573 unsigned int iqid, u8 dbqt);
1574 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1575 struct net_device *dev, unsigned int iqid,
1576 unsigned int cmplqid);
1577 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1578 unsigned int cmplqid);
1579 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1580 struct net_device *dev, unsigned int iqid,
1581 unsigned int uld_type);
1582 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
1583 struct net_device *dev, u32 iqid);
1584 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq);
1585 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1586 int t4_sge_init(struct adapter *adap);
1587 void t4_sge_start(struct adapter *adap);
1588 void t4_sge_stop(struct adapter *adap);
1589 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1591 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1592 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1593 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1594 extern int dbfifo_int_thresh;
1596 #define for_each_port(adapter, iter) \
1597 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1599 static inline int is_bypass(struct adapter *adap)
1601 return adap->params.bypass;
1604 static inline int is_bypass_device(int device)
1606 /* this should be set based upon device capabilities */
1616 static inline int is_10gbt_device(int device)
1618 /* this should be set based upon device capabilities */
1629 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1631 return adap->params.vpd.cclk / 1000;
1634 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1637 return (us * adap->params.vpd.cclk) / 1000;
1640 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1643 /* add Core Clock / 2 to round ticks to nearest uS */
1644 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1645 adapter->params.vpd.cclk);
1648 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1651 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1654 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1657 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1658 int size, void *rpl, bool sleep_ok, int timeout);
1659 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1660 void *rpl, bool sleep_ok);
1662 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1663 const void *cmd, int size, void *rpl,
1666 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1670 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1671 int size, void *rpl)
1673 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1676 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1677 int size, void *rpl)
1679 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1683 * hash_mac_addr - return the hash value of a MAC address
1684 * @addr: the 48-bit Ethernet MAC address
1686 * Hashes a MAC address according to the hash function used by HW inexact
1687 * (hash) address matching.
1689 static inline int hash_mac_addr(const u8 *addr)
1691 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1692 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1700 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1702 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1703 unsigned int us, unsigned int cnt,
1704 unsigned int size, unsigned int iqe_size)
1707 cxgb4_set_rspq_intr_params(q, us, cnt);
1708 q->iqe_len = iqe_size;
1713 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1714 * @fw_mod_type: the Firmware Mofule Type
1716 * Return whether the Firmware Module Type represents a real Transceiver
1717 * Module/Cable Module Type which has been inserted.
1719 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1721 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1722 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1723 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1724 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1727 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1728 unsigned int data_reg, const u32 *vals,
1729 unsigned int nregs, unsigned int start_idx);
1730 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1731 unsigned int data_reg, u32 *vals, unsigned int nregs,
1732 unsigned int start_idx);
1733 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1735 struct fw_filter_wr;
1737 void t4_intr_enable(struct adapter *adapter);
1738 void t4_intr_disable(struct adapter *adapter);
1739 int t4_slow_intr_handler(struct adapter *adapter);
1741 int t4_wait_dev_ready(void __iomem *regs);
1743 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
1744 struct link_config *lc);
1745 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1746 unsigned int port, struct link_config *lc,
1747 u8 sleep_ok, int timeout);
1749 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1750 unsigned int port, struct link_config *lc)
1752 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1753 true, FW_CMD_MAX_TIMEOUT);
1756 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1757 unsigned int port, struct link_config *lc)
1759 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1760 false, FW_CMD_MAX_TIMEOUT);
1763 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1765 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1766 u32 t4_get_util_window(struct adapter *adap);
1767 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1769 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1770 u32 *mem_base, u32 *mem_aperture);
1771 void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1772 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1774 #define T4_MEMORY_WRITE 0
1775 #define T4_MEMORY_READ 1
1776 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1777 void *buf, int dir);
1778 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1779 u32 len, __be32 *buf)
1781 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1784 unsigned int t4_get_regs_len(struct adapter *adapter);
1785 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1787 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1788 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1789 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1790 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1791 int t4_get_pfres(struct adapter *adapter);
1792 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1793 unsigned int nwords, u32 *data, int byte_oriented);
1794 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1795 int t4_load_phy_fw(struct adapter *adap,
1796 int win, spinlock_t *lock,
1797 int (*phy_fw_version)(const u8 *, size_t),
1798 const u8 *phy_fw_data, size_t phy_fw_size);
1799 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1800 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1801 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1802 const u8 *fw_data, unsigned int size, int force);
1803 int t4_fl_pkt_align(struct adapter *adap);
1804 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1805 int t4_check_fw_version(struct adapter *adap);
1806 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1807 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1808 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1809 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1810 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1811 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1812 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1813 int t4_get_version_info(struct adapter *adapter);
1814 void t4_dump_version_info(struct adapter *adapter);
1815 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1816 const u8 *fw_data, unsigned int fw_size,
1817 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1818 int t4_prep_adapter(struct adapter *adapter);
1819 int t4_shutdown_adapter(struct adapter *adapter);
1821 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1822 int t4_bar2_sge_qregs(struct adapter *adapter,
1824 enum t4_bar2_qtype qtype,
1827 unsigned int *pbar2_qid);
1829 unsigned int qtimer_val(const struct adapter *adap,
1830 const struct sge_rspq *q);
1832 int t4_init_devlog_params(struct adapter *adapter);
1833 int t4_init_sge_params(struct adapter *adapter);
1834 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1835 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1836 int t4_init_rss_mode(struct adapter *adap, int mbox);
1837 int t4_init_portinfo(struct port_info *pi, int mbox,
1838 int port, int pf, int vf, u8 mac[]);
1839 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1840 void t4_fatal_err(struct adapter *adapter);
1841 unsigned int t4_chip_rss_size(struct adapter *adapter);
1842 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1843 int start, int n, const u16 *rspq, unsigned int nrspq);
1844 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1845 unsigned int flags);
1846 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1847 unsigned int flags, unsigned int defq);
1848 int t4_read_rss(struct adapter *adapter, u16 *entries);
1849 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1850 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1852 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1853 u32 *valp, bool sleep_ok);
1854 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1855 u32 *vfl, u32 *vfh, bool sleep_ok);
1856 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1857 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1859 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1860 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1861 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1862 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1863 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1865 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1867 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1868 unsigned int *valp);
1869 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1870 const unsigned int *valp);
1871 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1872 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1873 unsigned int *pif_req_wrptr,
1874 unsigned int *pif_rsp_wrptr);
1875 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1876 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1877 const char *t4_get_port_type_description(enum fw_port_type port_type);
1878 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1879 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1880 struct port_stats *stats,
1881 struct port_stats *offset);
1882 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1883 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1884 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1885 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1886 unsigned int mask, unsigned int val);
1887 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1888 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1890 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1892 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1894 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1896 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1897 struct tp_tcp_stats *v6, bool sleep_ok);
1898 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1899 struct tp_fcoe_stats *st, bool sleep_ok);
1900 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1901 const unsigned short *alpha, const unsigned short *beta);
1903 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1905 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1906 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1908 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1910 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1911 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1913 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1914 enum dev_master master, enum dev_state *state);
1915 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1916 int t4_early_init(struct adapter *adap, unsigned int mbox);
1917 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1918 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1919 unsigned int cache_line_size);
1920 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1921 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1922 unsigned int vf, unsigned int nparams, const u32 *params,
1924 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1925 unsigned int vf, unsigned int nparams, const u32 *params,
1927 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1928 unsigned int vf, unsigned int nparams, const u32 *params,
1929 u32 *val, int rw, bool sleep_ok);
1930 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1931 unsigned int pf, unsigned int vf,
1932 unsigned int nparams, const u32 *params,
1933 const u32 *val, int timeout);
1934 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1935 unsigned int vf, unsigned int nparams, const u32 *params,
1937 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1938 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1939 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1940 unsigned int vi, unsigned int cmask, unsigned int pmask,
1941 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1942 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1943 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1944 unsigned int *rss_size, u8 *vivld, u8 *vin);
1945 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1946 unsigned int pf, unsigned int vf,
1948 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1949 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1951 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1952 const u8 *addr, const u8 *mask, unsigned int idx,
1953 u8 lookup_type, u8 port_id, bool sleep_ok);
1954 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1956 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1957 const u8 *addr, const u8 *mask, unsigned int vni,
1958 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1960 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1961 const u8 *addr, const u8 *mask, unsigned int idx,
1962 u8 lookup_type, u8 port_id, bool sleep_ok);
1963 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1964 unsigned int viid, bool free, unsigned int naddr,
1965 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1966 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1967 unsigned int viid, unsigned int naddr,
1968 const u8 **addr, bool sleep_ok);
1969 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1970 int idx, const u8 *addr, bool persist, u8 *smt_idx);
1971 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1972 bool ucast, u64 vec, bool sleep_ok);
1973 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1974 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1975 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1976 struct port_info *pi,
1977 bool rx_en, bool tx_en, bool dcb_en);
1978 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1979 bool rx_en, bool tx_en);
1980 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1981 unsigned int nblinks);
1982 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1983 unsigned int mmd, unsigned int reg, u16 *valp);
1984 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1985 unsigned int mmd, unsigned int reg, u16 val);
1986 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1987 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1988 unsigned int fl0id, unsigned int fl1id);
1989 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1990 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1991 unsigned int fl0id, unsigned int fl1id);
1992 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1993 unsigned int vf, unsigned int eqid);
1994 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1995 unsigned int vf, unsigned int eqid);
1996 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1997 unsigned int vf, unsigned int eqid);
1998 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1999 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
2001 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
2002 int t4_update_port_info(struct port_info *pi);
2003 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
2004 unsigned int *speedp, unsigned int *mtup);
2005 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
2006 void t4_db_full(struct adapter *adapter);
2007 void t4_db_dropped(struct adapter *adapter);
2008 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
2009 int filter_index, int enable);
2010 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
2011 int filter_index, int *enabled);
2012 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2014 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
2015 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
2016 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
2017 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
2018 enum ctxt_type ctype, u32 *data);
2019 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
2020 enum ctxt_type ctype, u32 *data);
2021 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
2022 u8 rateunit, u8 ratemode, u8 channel, u8 class,
2023 u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
2025 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
2026 void t4_idma_monitor_init(struct adapter *adapter,
2027 struct sge_idma_monitor_state *idma);
2028 void t4_idma_monitor(struct adapter *adapter,
2029 struct sge_idma_monitor_state *idma,
2031 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
2032 unsigned int naddr, u8 *addr);
2033 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
2034 u32 start_index, bool sleep_ok);
2035 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
2036 u32 start_index, bool sleep_ok);
2037 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
2038 u32 start_index, bool sleep_ok);
2040 void t4_uld_mem_free(struct adapter *adap);
2041 int t4_uld_mem_alloc(struct adapter *adap);
2042 void t4_uld_clean_up(struct adapter *adap);
2043 void t4_register_netevent_notifier(void);
2044 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
2045 unsigned int devid, unsigned int offset,
2046 unsigned int len, u8 *buf);
2047 int t4_load_boot(struct adapter *adap, u8 *boot_data,
2048 unsigned int boot_addr, unsigned int size);
2049 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
2050 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
2051 unsigned int n, bool unmap);
2052 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq,
2054 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc);
2055 void cxgb4_ethofld_restart(unsigned long data);
2056 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp,
2057 const struct pkt_gl *si);
2058 void free_txq(struct adapter *adap, struct sge_txq *q);
2059 void cxgb4_reclaim_completed_tx(struct adapter *adap,
2060 struct sge_txq *q, bool unmap);
2061 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
2063 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
2065 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
2066 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
2067 const dma_addr_t *addr);
2068 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
2069 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
2071 int cxgb4_dcb_enabled(const struct net_device *dev);
2073 int cxgb4_thermal_init(struct adapter *adap);
2074 int cxgb4_thermal_remove(struct adapter *adap);
2075 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
2076 cpumask_var_t *aff_mask, int idx);
2077 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
2079 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
2080 int *tcam_idx, const u8 *addr,
2081 bool persistent, u8 *smt_idx);
2083 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
2084 bool free, unsigned int naddr,
2085 const u8 **addr, u16 *idx,
2086 u64 *hash, bool sleep_ok);
2087 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
2088 unsigned int naddr, const u8 **addr, bool sleep_ok);
2089 int cxgb4_init_mps_ref_entries(struct adapter *adap);
2090 void cxgb4_free_mps_ref_entries(struct adapter *adap);
2091 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
2092 const u8 *addr, const u8 *mask,
2093 unsigned int vni, unsigned int vni_mask,
2094 u8 dip_hit, u8 lookup_type, bool sleep_ok);
2095 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
2096 int idx, bool sleep_ok);
2097 int cxgb4_free_raw_mac_filt(struct adapter *adap,
2105 int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
2113 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
2114 int *tcam_idx, const u8 *addr,
2115 bool persistent, u8 *smt_idx);
2116 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap);
2117 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx);
2118 int cxgb_open(struct net_device *dev);
2119 int cxgb_close(struct net_device *dev);
2120 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q);
2121 void cxgb4_quiesce_rx(struct sge_rspq *q);
2122 #ifdef CONFIG_CHELSIO_TLS_DEVICE
2123 int cxgb4_set_ktls_feature(struct adapter *adap, bool enable);
2125 #endif /* __CXGB4_H__ */