drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
   4  */
   5
   6 #include <linux/sort.h>
   7 #include <linux/string.h>
   8
   9 #include "t4_regs.h"
  10 #include "cxgb4.h"
  11 #include "cxgb4_cudbg.h"
  12 #include "cudbg_if.h"
  13 #include "cudbg_lib_common.h"
  14 #include "cudbg_entity.h"
  15 #include "cudbg_lib.h"
  16 #include "cudbg_zlib.h"
  17
  18 static int cudbg_do_compression(struct cudbg_init *pdbg_init,
  19                                 struct cudbg_buffer *pin_buff,
  20                                 struct cudbg_buffer *dbg_buff)
  21 {
  22         struct cudbg_buffer temp_in_buff = { 0 };
  23         int bytes_left, bytes_read, bytes;
  24         u32 offset = dbg_buff->offset;
  25         int rc;
  26
  27         temp_in_buff.offset = pin_buff->offset;
  28         temp_in_buff.data = pin_buff->data;
  29         temp_in_buff.size = pin_buff->size;
  30
  31         bytes_left = pin_buff->size;
  32         bytes_read = 0;
  33         while (bytes_left > 0) {
  34                 /* Do compression in smaller chunks */
  35                 bytes = min_t(unsigned long, bytes_left,
  36                               (unsigned long)CUDBG_CHUNK_SIZE);
  37                 temp_in_buff.data = (char *)pin_buff->data + bytes_read;
  38                 temp_in_buff.size = bytes;
  39                 rc = cudbg_compress_buff(pdbg_init, &temp_in_buff, dbg_buff);
  40                 if (rc)
  41                         return rc;
  42                 bytes_left -= bytes;
  43                 bytes_read += bytes;
  44         }
  45
  46         pin_buff->size = dbg_buff->offset - offset;
  47         return 0;
  48 }
  49
  50 static int cudbg_write_and_release_buff(struct cudbg_init *pdbg_init,
  51                                         struct cudbg_buffer *pin_buff,
  52                                         struct cudbg_buffer *dbg_buff)
  53 {
  54         int rc = 0;
  55
  56         if (pdbg_init->compress_type == CUDBG_COMPRESSION_NONE) {
  57                 cudbg_update_buff(pin_buff, dbg_buff);
  58         } else {
  59                 rc = cudbg_do_compression(pdbg_init, pin_buff, dbg_buff);
  60                 if (rc)
  61                         goto out;
  62         }
  63
  64 out:
  65         cudbg_put_buff(pdbg_init, pin_buff);
  66         return rc;
  67 }
  68
  69 static int is_fw_attached(struct cudbg_init *pdbg_init)
  70 {
  71         struct adapter *padap = pdbg_init->adap;
  72
  73         if (!(padap->flags & CXGB4_FW_OK) || padap->use_bd)
  74                 return 0;
  75
  76         return 1;
  77 }
  78
  79 /* This function will add additional padding bytes into debug_buffer to make it
  80  * 4 byte aligned.
  81  */
  82 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
  83                               struct cudbg_entity_hdr *entity_hdr)
  84 {
  85         u8 zero_buf[4] = {0};
  86         u8 padding, remain;
  87
  88         remain = (dbg_buff->offset - entity_hdr->start_offset) % 4;
  89         padding = 4 - remain;
  90         if (remain) {
  91                 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf,
  92                        padding);
  93                 dbg_buff->offset += padding;
  94                 entity_hdr->num_pad = padding;
  95         }
  96         entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset;
  97 }
  98
  99 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i)
 100 {
 101         struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf;
 102
 103         return (struct cudbg_entity_hdr *)
 104                ((char *)outbuf + cudbg_hdr->hdr_len +
 105                 (sizeof(struct cudbg_entity_hdr) * (i - 1)));
 106 }
 107
 108 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len,
 109                               void *dest)
 110 {
 111         int vaddr, rc;
 112
 113         vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE);
 114         if (vaddr < 0)
 115                 return vaddr;
 116
 117         rc = pci_read_vpd(padap->pdev, vaddr, len, dest);
 118         if (rc < 0)
 119                 return rc;
 120
 121         return 0;
 122 }
 123
 124 static int cudbg_mem_desc_cmp(const void *a, const void *b)
 125 {
 126         return ((const struct cudbg_mem_desc *)a)->base -
 127                ((const struct cudbg_mem_desc *)b)->base;
 128 }
 129
 130 int cudbg_fill_meminfo(struct adapter *padap,
 131                        struct cudbg_meminfo *meminfo_buff)
 132 {
 133         struct cudbg_mem_desc *md;
 134         u32 lo, hi, used, alloc;
 135         int n, i;
 136
 137         memset(meminfo_buff->avail, 0,
 138                ARRAY_SIZE(meminfo_buff->avail) *
 139                sizeof(struct cudbg_mem_desc));
 140         memset(meminfo_buff->mem, 0,
 141                (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc));
 142         md  = meminfo_buff->mem;
 143
 144         for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) {
 145                 meminfo_buff->mem[i].limit = 0;
 146                 meminfo_buff->mem[i].idx = i;
 147         }
 148
 149         /* Find and sort the populated memory ranges */
 150         i = 0;
 151         lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A);
 152         if (lo & EDRAM0_ENABLE_F) {
 153                 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A);
 154                 meminfo_buff->avail[i].base =
 155                         cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi));
 156                 meminfo_buff->avail[i].limit =
 157                         meminfo_buff->avail[i].base +
 158                         cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi));
 159                 meminfo_buff->avail[i].idx = 0;
 160                 i++;
 161         }
 162
 163         if (lo & EDRAM1_ENABLE_F) {
 164                 hi =  t4_read_reg(padap, MA_EDRAM1_BAR_A);
 165                 meminfo_buff->avail[i].base =
 166                         cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi));
 167                 meminfo_buff->avail[i].limit =
 168                         meminfo_buff->avail[i].base +
 169                         cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi));
 170                 meminfo_buff->avail[i].idx = 1;
 171                 i++;
 172         }
 173
 174         if (is_t5(padap->params.chip)) {
 175                 if (lo & EXT_MEM0_ENABLE_F) {
 176                         hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
 177                         meminfo_buff->avail[i].base =
 178                                 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
 179                         meminfo_buff->avail[i].limit =
 180                                 meminfo_buff->avail[i].base +
 181                                 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
 182                         meminfo_buff->avail[i].idx = 3;
 183                         i++;
 184                 }
 185
 186                 if (lo & EXT_MEM1_ENABLE_F) {
 187                         hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
 188                         meminfo_buff->avail[i].base =
 189                                 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
 190                         meminfo_buff->avail[i].limit =
 191                                 meminfo_buff->avail[i].base +
 192                                 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
 193                         meminfo_buff->avail[i].idx = 4;
 194                         i++;
 195                 }
 196         } else {
 197                 if (lo & EXT_MEM_ENABLE_F) {
 198                         hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A);
 199                         meminfo_buff->avail[i].base =
 200                                 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
 201                         meminfo_buff->avail[i].limit =
 202                                 meminfo_buff->avail[i].base +
 203                                 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
 204                         meminfo_buff->avail[i].idx = 2;
 205                         i++;
 206                 }
 207
 208                 if (lo & HMA_MUX_F) {
 209                         hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
 210                         meminfo_buff->avail[i].base =
 211                                 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
 212                         meminfo_buff->avail[i].limit =
 213                                 meminfo_buff->avail[i].base +
 214                                 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
 215                         meminfo_buff->avail[i].idx = 5;
 216                         i++;
 217                 }
 218         }
 219
 220         if (!i) /* no memory available */
 221                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
 222
 223         meminfo_buff->avail_c = i;
 224         sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc),
 225              cudbg_mem_desc_cmp, NULL);
 226         (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A);
 227         (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A);
 228         (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A);
 229         (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A);
 230         (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A);
 231         (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A);
 232         (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A);
 233         (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A);
 234         (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A);
 235
 236         /* the next few have explicit upper bounds */
 237         md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A);
 238         md->limit = md->base - 1 +
 239                     t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) *
 240                     PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A));
 241         md++;
 242
 243         md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A);
 244         md->limit = md->base - 1 +
 245                     t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) *
 246                     PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A));
 247         md++;
 248
 249         if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) {
 250                 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
 251                         hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4;
 252                         md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
 253                 } else {
 254                         hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
 255                         md->base = t4_read_reg(padap,
 256                                                LE_DB_HASH_TBL_BASE_ADDR_A);
 257                 }
 258                 md->limit = 0;
 259         } else {
 260                 md->base = 0;
 261                 md->idx = ARRAY_SIZE(cudbg_region);  /* hide it */
 262         }
 263         md++;
 264
 265 #define ulp_region(reg) do { \
 266         md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\
 267         (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\
 268 } while (0)
 269
 270         ulp_region(RX_ISCSI);
 271         ulp_region(RX_TDDP);
 272         ulp_region(TX_TPT);
 273         ulp_region(RX_STAG);
 274         ulp_region(RX_RQ);
 275         ulp_region(RX_RQUDP);
 276         ulp_region(RX_PBL);
 277         ulp_region(TX_PBL);
 278 #undef ulp_region
 279         md->base = 0;
 280         md->idx = ARRAY_SIZE(cudbg_region);
 281         if (!is_t4(padap->params.chip)) {
 282                 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A);
 283                 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A);
 284                 u32 size = 0;
 285
 286                 if (is_t5(padap->params.chip)) {
 287                         if (sge_ctrl & VFIFO_ENABLE_F)
 288                                 size = DBVFIFO_SIZE_G(fifo_size);
 289                 } else {
 290                         size = T6_DBVFIFO_SIZE_G(fifo_size);
 291                 }
 292
 293                 if (size) {
 294                         md->base = BASEADDR_G(t4_read_reg(padap,
 295                                                           SGE_DBVFIFO_BADDR_A));
 296                         md->limit = md->base + (size << 2) - 1;
 297                 }
 298         }
 299
 300         md++;
 301
 302         md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A);
 303         md->limit = 0;
 304         md++;
 305         md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A);
 306         md->limit = 0;
 307         md++;
 308
 309         md->base = padap->vres.ocq.start;
 310         if (padap->vres.ocq.size)
 311                 md->limit = md->base + padap->vres.ocq.size - 1;
 312         else
 313                 md->idx = ARRAY_SIZE(cudbg_region);  /* hide it */
 314         md++;
 315
 316         /* add any address-space holes, there can be up to 3 */
 317         for (n = 0; n < i - 1; n++)
 318                 if (meminfo_buff->avail[n].limit <
 319                     meminfo_buff->avail[n + 1].base)
 320                         (md++)->base = meminfo_buff->avail[n].limit;
 321
 322         if (meminfo_buff->avail[n].limit)
 323                 (md++)->base = meminfo_buff->avail[n].limit;
 324
 325         n = md - meminfo_buff->mem;
 326         meminfo_buff->mem_c = n;
 327
 328         sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc),
 329              cudbg_mem_desc_cmp, NULL);
 330
 331         lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A);
 332         hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;
 333         meminfo_buff->up_ram_lo = lo;
 334         meminfo_buff->up_ram_hi = hi;
 335
 336         lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A);
 337         hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;
 338         meminfo_buff->up_extmem2_lo = lo;
 339         meminfo_buff->up_extmem2_hi = hi;
 340
 341         lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A);
 342         for (i = 0, meminfo_buff->free_rx_cnt = 0; i < 2; i++)
 343                 meminfo_buff->free_rx_cnt +=
 344                         FREERXPAGECOUNT_G(t4_read_reg(padap,
 345                                                       TP_FLM_FREE_RX_CNT_A));
 346
 347         meminfo_buff->rx_pages_data[0] =  PMRXMAXPAGE_G(lo);
 348         meminfo_buff->rx_pages_data[1] =
 349                 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10;
 350         meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1;
 351
 352         lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A);
 353         hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A);
 354         for (i = 0, meminfo_buff->free_tx_cnt = 0; i < 4; i++)
 355                 meminfo_buff->free_tx_cnt +=
 356                         FREETXPAGECOUNT_G(t4_read_reg(padap,
 357                                                       TP_FLM_FREE_TX_CNT_A));
 358
 359         meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo);
 360         meminfo_buff->tx_pages_data[1] =
 361                 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10);
 362         meminfo_buff->tx_pages_data[2] =
 363                 hi >= (1 << 20) ? 'M' : 'K';
 364         meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo);
 365
 366         meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A);
 367         meminfo_buff->p_structs_free_cnt =
 368                 FREEPSTRUCTCOUNT_G(t4_read_reg(padap, TP_FLM_FREE_PS_CNT_A));
 369
 370         for (i = 0; i < 4; i++) {
 371                 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
 372                         lo = t4_read_reg(padap,
 373                                          MPS_RX_MAC_BG_PG_CNT0_A + i * 4);
 374                 else
 375                         lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4);
 376                 if (is_t5(padap->params.chip)) {
 377                         used = T5_USED_G(lo);
 378                         alloc = T5_ALLOC_G(lo);
 379                 } else {
 380                         used = USED_G(lo);
 381                         alloc = ALLOC_G(lo);
 382                 }
 383                 meminfo_buff->port_used[i] = used;
 384                 meminfo_buff->port_alloc[i] = alloc;
 385         }
 386
 387         for (i = 0; i < padap->params.arch.nchan; i++) {
 388                 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
 389                         lo = t4_read_reg(padap,
 390                                          MPS_RX_LPBK_BG_PG_CNT0_A + i * 4);
 391                 else
 392                         lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4);
 393                 if (is_t5(padap->params.chip)) {
 394                         used = T5_USED_G(lo);
 395                         alloc = T5_ALLOC_G(lo);
 396                 } else {
 397                         used = USED_G(lo);
 398                         alloc = ALLOC_G(lo);
 399                 }
 400                 meminfo_buff->loopback_used[i] = used;
 401                 meminfo_buff->loopback_alloc[i] = alloc;
 402         }
 403
 404         return 0;
 405 }
 406
 407 int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init,
 408                            struct cudbg_buffer *dbg_buff,
 409                            struct cudbg_error *cudbg_err)
 410 {
 411         struct adapter *padap = pdbg_init->adap;
 412         struct cudbg_buffer temp_buff = { 0 };
 413         u32 buf_size = 0;
 414         int rc = 0;
 415
 416         if (is_t4(padap->params.chip))
 417                 buf_size = T4_REGMAP_SIZE;
 418         else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
 419                 buf_size = T5_REGMAP_SIZE;
 420
 421         rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff);
 422         if (rc)
 423                 return rc;
 424         t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size);
 425         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 426 }
 427
 428 int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init,
 429                             struct cudbg_buffer *dbg_buff,
 430                             struct cudbg_error *cudbg_err)
 431 {
 432         struct adapter *padap = pdbg_init->adap;
 433         struct cudbg_buffer temp_buff = { 0 };
 434         struct devlog_params *dparams;
 435         int rc = 0;
 436
 437         rc = t4_init_devlog_params(padap);
 438         if (rc < 0) {
 439                 cudbg_err->sys_err = rc;
 440                 return rc;
 441         }
 442
 443         dparams = &padap->params.devlog;
 444         rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff);
 445         if (rc)
 446                 return rc;
 447
 448         /* Collect FW devlog */
 449         if (dparams->start != 0) {
 450                 spin_lock(&padap->win0_lock);
 451                 rc = t4_memory_rw(padap, padap->params.drv_memwin,
 452                                   dparams->memtype, dparams->start,
 453                                   dparams->size,
 454                                   (__be32 *)(char *)temp_buff.data,
 455                                   1);
 456                 spin_unlock(&padap->win0_lock);
 457                 if (rc) {
 458                         cudbg_err->sys_err = rc;
 459                         cudbg_put_buff(pdbg_init, &temp_buff);
 460                         return rc;
 461                 }
 462         }
 463         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 464 }
 465
 466 int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
 467                          struct cudbg_buffer *dbg_buff,
 468                          struct cudbg_error *cudbg_err)
 469 {
 470         struct adapter *padap = pdbg_init->adap;
 471         struct cudbg_buffer temp_buff = { 0 };
 472         int size, rc;
 473         u32 cfg = 0;
 474
 475         if (is_t6(padap->params.chip)) {
 476                 size = padap->params.cim_la_size / 10 + 1;
 477                 size *= 10 * sizeof(u32);
 478         } else {
 479                 size = padap->params.cim_la_size / 8;
 480                 size *= 8 * sizeof(u32);
 481         }
 482
 483         size += sizeof(cfg);
 484         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
 485         if (rc)
 486                 return rc;
 487
 488         rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
 489         if (rc) {
 490                 cudbg_err->sys_err = rc;
 491                 cudbg_put_buff(pdbg_init, &temp_buff);
 492                 return rc;
 493         }
 494
 495         memcpy((char *)temp_buff.data, &cfg, sizeof(cfg));
 496         rc = t4_cim_read_la(padap,
 497                             (u32 *)((char *)temp_buff.data + sizeof(cfg)),
 498                             NULL);
 499         if (rc < 0) {
 500                 cudbg_err->sys_err = rc;
 501                 cudbg_put_buff(pdbg_init, &temp_buff);
 502                 return rc;
 503         }
 504         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 505 }
 506
 507 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
 508                             struct cudbg_buffer *dbg_buff,
 509                             struct cudbg_error *cudbg_err)
 510 {
 511         struct adapter *padap = pdbg_init->adap;
 512         struct cudbg_buffer temp_buff = { 0 };
 513         int size, rc;
 514
 515         size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
 516         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
 517         if (rc)
 518                 return rc;
 519
 520         t4_cim_read_ma_la(padap,
 521                           (u32 *)temp_buff.data,
 522                           (u32 *)((char *)temp_buff.data +
 523                                   5 * CIM_MALA_SIZE));
 524         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 525 }
 526
 527 int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
 528                            struct cudbg_buffer *dbg_buff,
 529                            struct cudbg_error *cudbg_err)
 530 {
 531         struct adapter *padap = pdbg_init->adap;
 532         struct cudbg_buffer temp_buff = { 0 };
 533         struct cudbg_cim_qcfg *cim_qcfg_data;
 534         int rc;
 535
 536         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg),
 537                             &temp_buff);
 538         if (rc)
 539                 return rc;
 540
 541         cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
 542         cim_qcfg_data->chip = padap->params.chip;
 543         rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
 544                          ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
 545         if (rc) {
 546                 cudbg_err->sys_err = rc;
 547                 cudbg_put_buff(pdbg_init, &temp_buff);
 548                 return rc;
 549         }
 550
 551         rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
 552                          ARRAY_SIZE(cim_qcfg_data->obq_wr),
 553                          cim_qcfg_data->obq_wr);
 554         if (rc) {
 555                 cudbg_err->sys_err = rc;
 556                 cudbg_put_buff(pdbg_init, &temp_buff);
 557                 return rc;
 558         }
 559
 560         t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
 561                          cim_qcfg_data->thres);
 562         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 563 }
 564
 565 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
 566                               struct cudbg_buffer *dbg_buff,
 567                               struct cudbg_error *cudbg_err, int qid)
 568 {
 569         struct adapter *padap = pdbg_init->adap;
 570         struct cudbg_buffer temp_buff = { 0 };
 571         int no_of_read_words, rc = 0;
 572         u32 qsize;
 573
 574         /* collect CIM IBQ */
 575         qsize = CIM_IBQ_SIZE * 4 * sizeof(u32);
 576         rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
 577         if (rc)
 578                 return rc;
 579
 580         /* t4_read_cim_ibq will return no. of read words or error */
 581         no_of_read_words = t4_read_cim_ibq(padap, qid,
 582                                            (u32 *)temp_buff.data, qsize);
 583         /* no_of_read_words is less than or equal to 0 means error */
 584         if (no_of_read_words <= 0) {
 585                 if (!no_of_read_words)
 586                         rc = CUDBG_SYSTEM_ERROR;
 587                 else
 588                         rc = no_of_read_words;
 589                 cudbg_err->sys_err = rc;
 590                 cudbg_put_buff(pdbg_init, &temp_buff);
 591                 return rc;
 592         }
 593         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 594 }
 595
 596 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init,
 597                               struct cudbg_buffer *dbg_buff,
 598                               struct cudbg_error *cudbg_err)
 599 {
 600         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0);
 601 }
 602
 603 int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
 604                               struct cudbg_buffer *dbg_buff,
 605                               struct cudbg_error *cudbg_err)
 606 {
 607         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1);
 608 }
 609
 610 int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
 611                               struct cudbg_buffer *dbg_buff,
 612                               struct cudbg_error *cudbg_err)
 613 {
 614         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
 615 }
 616
 617 int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
 618                                struct cudbg_buffer *dbg_buff,
 619                                struct cudbg_error *cudbg_err)
 620 {
 621         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
 622 }
 623
 624 int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
 625                                struct cudbg_buffer *dbg_buff,
 626                                struct cudbg_error *cudbg_err)
 627 {
 628         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
 629 }
 630
 631 int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
 632                                struct cudbg_buffer *dbg_buff,
 633                                struct cudbg_error *cudbg_err)
 634 {
 635         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
 636 }
 637
 638 u32 cudbg_cim_obq_size(struct adapter *padap, int qid)
 639 {
 640         u32 value;
 641
 642         t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
 643                      QUENUMSELECT_V(qid));
 644         value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A);
 645         value = CIMQSIZE_G(value) * 64; /* size in number of words */
 646         return value * sizeof(u32);
 647 }
 648
 649 static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init,
 650                               struct cudbg_buffer *dbg_buff,
 651                               struct cudbg_error *cudbg_err, int qid)
 652 {
 653         struct adapter *padap = pdbg_init->adap;
 654         struct cudbg_buffer temp_buff = { 0 };
 655         int no_of_read_words, rc = 0;
 656         u32 qsize;
 657
 658         /* collect CIM OBQ */
 659         qsize =  cudbg_cim_obq_size(padap, qid);
 660         rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
 661         if (rc)
 662                 return rc;
 663
 664         /* t4_read_cim_obq will return no. of read words or error */
 665         no_of_read_words = t4_read_cim_obq(padap, qid,
 666                                            (u32 *)temp_buff.data, qsize);
 667         /* no_of_read_words is less than or equal to 0 means error */
 668         if (no_of_read_words <= 0) {
 669                 if (!no_of_read_words)
 670                         rc = CUDBG_SYSTEM_ERROR;
 671                 else
 672                         rc = no_of_read_words;
 673                 cudbg_err->sys_err = rc;
 674                 cudbg_put_buff(pdbg_init, &temp_buff);
 675                 return rc;
 676         }
 677         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 678 }
 679
 680 int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init,
 681                                struct cudbg_buffer *dbg_buff,
 682                                struct cudbg_error *cudbg_err)
 683 {
 684         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0);
 685 }
 686
 687 int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init,
 688                                struct cudbg_buffer *dbg_buff,
 689                                struct cudbg_error *cudbg_err)
 690 {
 691         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1);
 692 }
 693
 694 int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init,
 695                                struct cudbg_buffer *dbg_buff,
 696                                struct cudbg_error *cudbg_err)
 697 {
 698         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2);
 699 }
 700
 701 int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init,
 702                                struct cudbg_buffer *dbg_buff,
 703                                struct cudbg_error *cudbg_err)
 704 {
 705         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3);
 706 }
 707
 708 int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init,
 709                               struct cudbg_buffer *dbg_buff,
 710                               struct cudbg_error *cudbg_err)
 711 {
 712         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4);
 713 }
 714
 715 int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init,
 716                                struct cudbg_buffer *dbg_buff,
 717                                struct cudbg_error *cudbg_err)
 718 {
 719         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5);
 720 }
 721
 722 int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,
 723                                 struct cudbg_buffer *dbg_buff,
 724                                 struct cudbg_error *cudbg_err)
 725 {
 726         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6);
 727 }
 728
 729 int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
 730                                 struct cudbg_buffer *dbg_buff,
 731                                 struct cudbg_error *cudbg_err)
 732 {
 733         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7);
 734 }
 735
 736 static int cudbg_meminfo_get_mem_index(struct adapter *padap,
 737                                        struct cudbg_meminfo *mem_info,
 738                                        u8 mem_type, u8 *idx)
 739 {
 740         u8 i, flag;
 741
 742         switch (mem_type) {
 743         case MEM_EDC0:
 744                 flag = EDC0_FLAG;
 745                 break;
 746         case MEM_EDC1:
 747                 flag = EDC1_FLAG;
 748                 break;
 749         case MEM_MC0:
 750                 /* Some T5 cards have both MC0 and MC1. */
 751                 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG;
 752                 break;
 753         case MEM_MC1:
 754                 flag = MC1_FLAG;
 755                 break;
 756         case MEM_HMA:
 757                 flag = HMA_FLAG;
 758                 break;
 759         default:
 760                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
 761         }
 762
 763         for (i = 0; i < mem_info->avail_c; i++) {
 764                 if (mem_info->avail[i].idx == flag) {
 765                         *idx = i;
 766                         return 0;
 767                 }
 768         }
 769
 770         return CUDBG_STATUS_ENTITY_NOT_FOUND;
 771 }
 772
 773 /* Fetch the @region_name's start and end from @meminfo. */
 774 static int cudbg_get_mem_region(struct adapter *padap,
 775                                 struct cudbg_meminfo *meminfo,
 776                                 u8 mem_type, const char *region_name,
 777                                 struct cudbg_mem_desc *mem_desc)
 778 {
 779         u8 mc, found = 0;
 780         u32 idx = 0;
 781         int rc, i;
 782
 783         rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc);
 784         if (rc)
 785                 return rc;
 786
 787         i = match_string(cudbg_region, ARRAY_SIZE(cudbg_region), region_name);
 788         if (i < 0)
 789                 return -EINVAL;
 790
 791         idx = i;
 792         for (i = 0; i < meminfo->mem_c; i++) {
 793                 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region))
 794                         continue; /* Skip holes */
 795
 796                 if (!(meminfo->mem[i].limit))
 797                         meminfo->mem[i].limit =
 798                                 i < meminfo->mem_c - 1 ?
 799                                 meminfo->mem[i + 1].base - 1 : ~0;
 800
 801                 if (meminfo->mem[i].idx == idx) {
 802                         /* Check if the region exists in @mem_type memory */
 803                         if (meminfo->mem[i].base < meminfo->avail[mc].base &&
 804                             meminfo->mem[i].limit < meminfo->avail[mc].base)
 805                                 return -EINVAL;
 806
 807                         if (meminfo->mem[i].base > meminfo->avail[mc].limit)
 808                                 return -EINVAL;
 809
 810                         memcpy(mem_desc, &meminfo->mem[i],
 811                                sizeof(struct cudbg_mem_desc));
 812                         found = 1;
 813                         break;
 814                 }
 815         }
 816         if (!found)
 817                 return -EINVAL;
 818
 819         return 0;
 820 }
 821
 822 /* Fetch and update the start and end of the requested memory region w.r.t 0
 823  * in the corresponding EDC/MC/HMA.
 824  */
 825 static int cudbg_get_mem_relative(struct adapter *padap,
 826                                   struct cudbg_meminfo *meminfo,
 827                                   u8 mem_type, u32 *out_base, u32 *out_end)
 828 {
 829         u8 mc_idx;
 830         int rc;
 831
 832         rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx);
 833         if (rc)
 834                 return rc;
 835
 836         if (*out_base < meminfo->avail[mc_idx].base)
 837                 *out_base = 0;
 838         else
 839                 *out_base -= meminfo->avail[mc_idx].base;
 840
 841         if (*out_end > meminfo->avail[mc_idx].limit)
 842                 *out_end = meminfo->avail[mc_idx].limit;
 843         else
 844                 *out_end -= meminfo->avail[mc_idx].base;
 845
 846         return 0;
 847 }
 848
 849 /* Get TX and RX Payload region */
 850 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type,
 851                                    const char *region_name,
 852                                    struct cudbg_region_info *payload)
 853 {
 854         struct cudbg_mem_desc mem_desc = { 0 };
 855         struct cudbg_meminfo meminfo;
 856         int rc;
 857
 858         rc = cudbg_fill_meminfo(padap, &meminfo);
 859         if (rc)
 860                 return rc;
 861
 862         rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name,
 863                                   &mem_desc);
 864         if (rc) {
 865                 payload->exist = false;
 866                 return 0;
 867         }
 868
 869         payload->exist = true;
 870         payload->start = mem_desc.base;
 871         payload->end = mem_desc.limit;
 872
 873         return cudbg_get_mem_relative(padap, &meminfo, mem_type,
 874                                       &payload->start, &payload->end);
 875 }
 876
 877 static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
 878                              int mtype, u32 addr, u32 len, void *hbuf)
 879 {
 880         u32 win_pf, memoffset, mem_aperture, mem_base;
 881         struct adapter *adap = pdbg_init->adap;
 882         u32 pos, offset, resid;
 883         u32 *res_buf;
 884         u64 *buf;
 885         int ret;
 886
 887         /* Argument sanity checks ...
 888          */
 889         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 890                 return -EINVAL;
 891
 892         buf = (u64 *)hbuf;
 893
 894         /* Try to do 64-bit reads.  Residual will be handled later. */
 895         resid = len & 0x7;
 896         len -= resid;
 897
 898         ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
 899                                 &mem_aperture);
 900         if (ret)
 901                 return ret;
 902
 903         addr = addr + memoffset;
 904         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 905
 906         pos = addr & ~(mem_aperture - 1);
 907         offset = addr - pos;
 908
 909         /* Set up initial PCI-E Memory Window to cover the start of our
 910          * transfer.
 911          */
 912         t4_memory_update_win(adap, win, pos | win_pf);
 913
 914         /* Transfer data from the adapter */
 915         while (len > 0) {
 916                 *buf++ = le64_to_cpu((__force __le64)
 917                                      t4_read_reg64(adap, mem_base + offset));
 918                 offset += sizeof(u64);
 919                 len -= sizeof(u64);
 920
 921                 /* If we've reached the end of our current window aperture,
 922                  * move the PCI-E Memory Window on to the next.
 923                  */
 924                 if (offset == mem_aperture) {
 925                         pos += mem_aperture;
 926                         offset = 0;
 927                         t4_memory_update_win(adap, win, pos | win_pf);
 928                 }
 929         }
 930
 931         res_buf = (u32 *)buf;
 932         /* Read residual in 32-bit multiples */
 933         while (resid > sizeof(u32)) {
 934                 *res_buf++ = le32_to_cpu((__force __le32)
 935                                          t4_read_reg(adap, mem_base + offset));
 936                 offset += sizeof(u32);
 937                 resid -= sizeof(u32);
 938
 939                 /* If we've reached the end of our current window aperture,
 940                  * move the PCI-E Memory Window on to the next.
 941                  */
 942                 if (offset == mem_aperture) {
 943                         pos += mem_aperture;
 944                         offset = 0;
 945                         t4_memory_update_win(adap, win, pos | win_pf);
 946                 }
 947         }
 948
 949         /* Transfer residual < 32-bits */
 950         if (resid)
 951                 t4_memory_rw_residual(adap, resid, mem_base + offset,
 952                                       (u8 *)res_buf, T4_MEMORY_READ);
 953
 954         return 0;
 955 }
 956
 957 #define CUDBG_YIELD_ITERATION 256
 958
 959 static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init,
 960                              struct cudbg_buffer *dbg_buff, u8 mem_type,
 961                              unsigned long tot_len,
 962                              struct cudbg_error *cudbg_err)
 963 {
 964         static const char * const region_name[] = { "Tx payload:",
 965                                                     "Rx payload:" };
 966         unsigned long bytes, bytes_left, bytes_read = 0;
 967         struct adapter *padap = pdbg_init->adap;
 968         struct cudbg_buffer temp_buff = { 0 };
 969         struct cudbg_region_info payload[2];
 970         u32 yield_count = 0;
 971         int rc = 0;
 972         u8 i;
 973
 974         /* Get TX/RX Payload region range if they exist */
 975         memset(payload, 0, sizeof(payload));
 976         for (i = 0; i < ARRAY_SIZE(region_name); i++) {
 977                 rc = cudbg_get_payload_range(padap, mem_type, region_name[i],
 978                                              &payload[i]);
 979                 if (rc)
 980                         return rc;
 981
 982                 if (payload[i].exist) {
 983                         /* Align start and end to avoid wrap around */
 984                         payload[i].start = roundup(payload[i].start,
 985                                                    CUDBG_CHUNK_SIZE);
 986                         payload[i].end = rounddown(payload[i].end,
 987                                                    CUDBG_CHUNK_SIZE);
 988                 }
 989         }
 990
 991         bytes_left = tot_len;
 992         while (bytes_left > 0) {
 993                 /* As MC size is huge and read through PIO access, this
 994                  * loop will hold cpu for a longer time. OS may think that
 995                  * the process is hanged and will generate CPU stall traces.
 996                  * So yield the cpu regularly.
 997                  */
 998                 yield_count++;
 999                 if (!(yield_count % CUDBG_YIELD_ITERATION))
1000                         schedule();
1001
1002                 bytes = min_t(unsigned long, bytes_left,
1003                               (unsigned long)CUDBG_CHUNK_SIZE);
1004                 rc = cudbg_get_buff(pdbg_init, dbg_buff, bytes, &temp_buff);
1005                 if (rc)
1006                         return rc;
1007
1008                 for (i = 0; i < ARRAY_SIZE(payload); i++)
1009                         if (payload[i].exist &&
1010                             bytes_read >= payload[i].start &&
1011                             bytes_read + bytes <= payload[i].end)
1012                                 /* TX and RX Payload regions can't overlap */
1013                                 goto skip_read;
1014
1015                 spin_lock(&padap->win0_lock);
1016                 rc = cudbg_memory_read(pdbg_init, MEMWIN_NIC, mem_type,
1017                                        bytes_read, bytes, temp_buff.data);
1018                 spin_unlock(&padap->win0_lock);
1019                 if (rc) {
1020                         cudbg_err->sys_err = rc;
1021                         cudbg_put_buff(pdbg_init, &temp_buff);
1022                         return rc;
1023                 }
1024
1025 skip_read:
1026                 bytes_left -= bytes;
1027                 bytes_read += bytes;
1028                 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
1029                                                   dbg_buff);
1030                 if (rc) {
1031                         cudbg_put_buff(pdbg_init, &temp_buff);
1032                         return rc;
1033                 }
1034         }
1035         return rc;
1036 }
1037
1038 static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init,
1039                              struct cudbg_error *cudbg_err)
1040 {
1041         struct adapter *padap = pdbg_init->adap;
1042         int rc;
1043
1044         if (is_fw_attached(pdbg_init)) {
1045                 /* Flush uP dcache before reading edcX/mcX  */
1046                 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH);
1047                 if (rc)
1048                         cudbg_err->sys_warn = rc;
1049         }
1050 }
1051
1052 static int cudbg_mem_region_size(struct cudbg_init *pdbg_init,
1053                                  struct cudbg_error *cudbg_err,
1054                                  u8 mem_type, unsigned long *region_size)
1055 {
1056         struct adapter *padap = pdbg_init->adap;
1057         struct cudbg_meminfo mem_info;
1058         u8 mc_idx;
1059         int rc;
1060
1061         memset(&mem_info, 0, sizeof(struct cudbg_meminfo));
1062         rc = cudbg_fill_meminfo(padap, &mem_info);
1063         if (rc) {
1064                 cudbg_err->sys_err = rc;
1065                 return rc;
1066         }
1067
1068         cudbg_t4_fwcache(pdbg_init, cudbg_err);
1069         rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx);
1070         if (rc) {
1071                 cudbg_err->sys_err = rc;
1072                 return rc;
1073         }
1074
1075         if (region_size)
1076                 *region_size = mem_info.avail[mc_idx].limit -
1077                                mem_info.avail[mc_idx].base;
1078
1079         return 0;
1080 }
1081
1082 static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init,
1083                                     struct cudbg_buffer *dbg_buff,
1084                                     struct cudbg_error *cudbg_err,
1085                                     u8 mem_type)
1086 {
1087         unsigned long size = 0;
1088         int rc;
1089
1090         rc = cudbg_mem_region_size(pdbg_init, cudbg_err, mem_type, &size);
1091         if (rc)
1092                 return rc;
1093
1094         return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size,
1095                                  cudbg_err);
1096 }
1097
1098 int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init,
1099                                struct cudbg_buffer *dbg_buff,
1100                                struct cudbg_error *cudbg_err)
1101 {
1102         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1103                                         MEM_EDC0);
1104 }
1105
1106 int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init,
1107                                struct cudbg_buffer *dbg_buff,
1108                                struct cudbg_error *cudbg_err)
1109 {
1110         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1111                                         MEM_EDC1);
1112 }
1113
1114 int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init,
1115                               struct cudbg_buffer *dbg_buff,
1116                               struct cudbg_error *cudbg_err)
1117 {
1118         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1119                                         MEM_MC0);
1120 }
1121
1122 int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
1123                               struct cudbg_buffer *dbg_buff,
1124                               struct cudbg_error *cudbg_err)
1125 {
1126         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1127                                         MEM_MC1);
1128 }
1129
1130 int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
1131                               struct cudbg_buffer *dbg_buff,
1132                               struct cudbg_error *cudbg_err)
1133 {
1134         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1135                                         MEM_HMA);
1136 }
1137
1138 int cudbg_collect_rss(struct cudbg_init *pdbg_init,
1139                       struct cudbg_buffer *dbg_buff,
1140                       struct cudbg_error *cudbg_err)
1141 {
1142         struct adapter *padap = pdbg_init->adap;
1143         struct cudbg_buffer temp_buff = { 0 };
1144         int rc, nentries;
1145
1146         nentries = t4_chip_rss_size(padap);
1147         rc = cudbg_get_buff(pdbg_init, dbg_buff, nentries * sizeof(u16),
1148                             &temp_buff);
1149         if (rc)
1150                 return rc;
1151
1152         rc = t4_read_rss(padap, (u16 *)temp_buff.data);
1153         if (rc) {
1154                 cudbg_err->sys_err = rc;
1155                 cudbg_put_buff(pdbg_init, &temp_buff);
1156                 return rc;
1157         }
1158         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1159 }
1160
1161 int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
1162                                 struct cudbg_buffer *dbg_buff,
1163                                 struct cudbg_error *cudbg_err)
1164 {
1165         struct adapter *padap = pdbg_init->adap;
1166         struct cudbg_buffer temp_buff = { 0 };
1167         struct cudbg_rss_vf_conf *vfconf;
1168         int vf, rc, vf_count;
1169
1170         vf_count = padap->params.arch.vfcount;
1171         rc = cudbg_get_buff(pdbg_init, dbg_buff,
1172                             vf_count * sizeof(struct cudbg_rss_vf_conf),
1173                             &temp_buff);
1174         if (rc)
1175                 return rc;
1176
1177         vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data;
1178         for (vf = 0; vf < vf_count; vf++)
1179                 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl,
1180                                       &vfconf[vf].rss_vf_vfh, true);
1181         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1182 }
1183
1184 int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
1185                            struct cudbg_buffer *dbg_buff,
1186                            struct cudbg_error *cudbg_err)
1187 {
1188         struct adapter *padap = pdbg_init->adap;
1189         struct cudbg_buffer temp_buff = { 0 };
1190         int rc;
1191
1192         rc = cudbg_get_buff(pdbg_init, dbg_buff, NMTUS * sizeof(u16),
1193                             &temp_buff);
1194         if (rc)
1195                 return rc;
1196
1197         t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);
1198         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1199 }
1200
1201 int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
1202                            struct cudbg_buffer *dbg_buff,
1203                            struct cudbg_error *cudbg_err)
1204 {
1205         struct adapter *padap = pdbg_init->adap;
1206         struct cudbg_buffer temp_buff = { 0 };
1207         struct cudbg_pm_stats *pm_stats_buff;
1208         int rc;
1209
1210         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_pm_stats),
1211                             &temp_buff);
1212         if (rc)
1213                 return rc;
1214
1215         pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data;
1216         t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
1217         t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
1218         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1219 }
1220
1221 int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
1222                            struct cudbg_buffer *dbg_buff,
1223                            struct cudbg_error *cudbg_err)
1224 {
1225         struct adapter *padap = pdbg_init->adap;
1226         struct cudbg_buffer temp_buff = { 0 };
1227         struct cudbg_hw_sched *hw_sched_buff;
1228         int i, rc = 0;
1229
1230         if (!padap->params.vpd.cclk)
1231                 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1232
1233         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_hw_sched),
1234                             &temp_buff);
1235
1236         if (rc)
1237                 return rc;
1238
1239         hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data;
1240         hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A);
1241         hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A));
1242         t4_read_pace_tbl(padap, hw_sched_buff->pace_tab);
1243         for (i = 0; i < NTX_SCHED; ++i)
1244                 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i],
1245                                 &hw_sched_buff->ipg[i], true);
1246         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1247 }
1248
1249 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
1250                               struct cudbg_buffer *dbg_buff,
1251                               struct cudbg_error *cudbg_err)
1252 {
1253         struct adapter *padap = pdbg_init->adap;
1254         struct cudbg_buffer temp_buff = { 0 };
1255         struct ireg_buf *ch_tp_pio;
1256         int i, rc, n = 0;
1257         u32 size;
1258
1259         if (is_t5(padap->params.chip))
1260                 n = sizeof(t5_tp_pio_array) +
1261                     sizeof(t5_tp_tm_pio_array) +
1262                     sizeof(t5_tp_mib_index_array);
1263         else
1264                 n = sizeof(t6_tp_pio_array) +
1265                     sizeof(t6_tp_tm_pio_array) +
1266                     sizeof(t6_tp_mib_index_array);
1267
1268         n = n / (IREG_NUM_ELEM * sizeof(u32));
1269         size = sizeof(struct ireg_buf) * n;
1270         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1271         if (rc)
1272                 return rc;
1273
1274         ch_tp_pio = (struct ireg_buf *)temp_buff.data;
1275
1276         /* TP_PIO */
1277         if (is_t5(padap->params.chip))
1278                 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1279         else if (is_t6(padap->params.chip))
1280                 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1281
1282         for (i = 0; i < n; i++) {
1283                 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1284                 u32 *buff = ch_tp_pio->outbuf;
1285
1286                 if (is_t5(padap->params.chip)) {
1287                         tp_pio->ireg_addr = t5_tp_pio_array[i][0];
1288                         tp_pio->ireg_data = t5_tp_pio_array[i][1];
1289                         tp_pio->ireg_local_offset = t5_tp_pio_array[i][2];
1290                         tp_pio->ireg_offset_range = t5_tp_pio_array[i][3];
1291                 } else if (is_t6(padap->params.chip)) {
1292                         tp_pio->ireg_addr = t6_tp_pio_array[i][0];
1293                         tp_pio->ireg_data = t6_tp_pio_array[i][1];
1294                         tp_pio->ireg_local_offset = t6_tp_pio_array[i][2];
1295                         tp_pio->ireg_offset_range = t6_tp_pio_array[i][3];
1296                 }
1297                 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,
1298                                tp_pio->ireg_local_offset, true);
1299                 ch_tp_pio++;
1300         }
1301
1302         /* TP_TM_PIO */
1303         if (is_t5(padap->params.chip))
1304                 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1305         else if (is_t6(padap->params.chip))
1306                 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1307
1308         for (i = 0; i < n; i++) {
1309                 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1310                 u32 *buff = ch_tp_pio->outbuf;
1311
1312                 if (is_t5(padap->params.chip)) {
1313                         tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0];
1314                         tp_pio->ireg_data = t5_tp_tm_pio_array[i][1];
1315                         tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2];
1316                         tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3];
1317                 } else if (is_t6(padap->params.chip)) {
1318                         tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0];
1319                         tp_pio->ireg_data = t6_tp_tm_pio_array[i][1];
1320                         tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2];
1321                         tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3];
1322                 }
1323                 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range,
1324                                   tp_pio->ireg_local_offset, true);
1325                 ch_tp_pio++;
1326         }
1327
1328         /* TP_MIB_INDEX */
1329         if (is_t5(padap->params.chip))
1330                 n = sizeof(t5_tp_mib_index_array) /
1331                     (IREG_NUM_ELEM * sizeof(u32));
1332         else if (is_t6(padap->params.chip))
1333                 n = sizeof(t6_tp_mib_index_array) /
1334                     (IREG_NUM_ELEM * sizeof(u32));
1335
1336         for (i = 0; i < n ; i++) {
1337                 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1338                 u32 *buff = ch_tp_pio->outbuf;
1339
1340                 if (is_t5(padap->params.chip)) {
1341                         tp_pio->ireg_addr = t5_tp_mib_index_array[i][0];
1342                         tp_pio->ireg_data = t5_tp_mib_index_array[i][1];
1343                         tp_pio->ireg_local_offset =
1344                                 t5_tp_mib_index_array[i][2];
1345                         tp_pio->ireg_offset_range =
1346                                 t5_tp_mib_index_array[i][3];
1347                 } else if (is_t6(padap->params.chip)) {
1348                         tp_pio->ireg_addr = t6_tp_mib_index_array[i][0];
1349                         tp_pio->ireg_data = t6_tp_mib_index_array[i][1];
1350                         tp_pio->ireg_local_offset =
1351                                 t6_tp_mib_index_array[i][2];
1352                         tp_pio->ireg_offset_range =
1353                                 t6_tp_mib_index_array[i][3];
1354                 }
1355                 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range,
1356                                tp_pio->ireg_local_offset, true);
1357                 ch_tp_pio++;
1358         }
1359         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1360 }
1361
1362 static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap,
1363                                               struct sge_qbase_reg_field *qbase,
1364                                               u32 func, bool is_pf)
1365 {
1366         u32 *buff, i;
1367
1368         if (is_pf) {
1369                 buff = qbase->pf_data_value[func];
1370         } else {
1371                 buff = qbase->vf_data_value[func];
1372                 /* In SGE_QBASE_INDEX,
1373                  * Entries 0->7 are PF0->7, Entries 8->263 are VFID0->256.
1374                  */
1375                 func += 8;
1376         }
1377
1378         t4_write_reg(padap, qbase->reg_addr, func);
1379         for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++, buff++)
1380                 *buff = t4_read_reg(padap, qbase->reg_data[i]);
1381 }
1382
1383 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
1384                                struct cudbg_buffer *dbg_buff,
1385                                struct cudbg_error *cudbg_err)
1386 {
1387         struct adapter *padap = pdbg_init->adap;
1388         struct cudbg_buffer temp_buff = { 0 };
1389         struct sge_qbase_reg_field *sge_qbase;
1390         struct ireg_buf *ch_sge_dbg;
1391         int i, rc;
1392
1393         rc = cudbg_get_buff(pdbg_init, dbg_buff,
1394                             sizeof(*ch_sge_dbg) * 2 + sizeof(*sge_qbase),
1395                             &temp_buff);
1396         if (rc)
1397                 return rc;
1398
1399         ch_sge_dbg = (struct ireg_buf *)temp_buff.data;
1400         for (i = 0; i < 2; i++) {
1401                 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio;
1402                 u32 *buff = ch_sge_dbg->outbuf;
1403
1404                 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0];
1405                 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1];
1406                 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2];
1407                 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3];
1408                 t4_read_indirect(padap,
1409                                  sge_pio->ireg_addr,
1410                                  sge_pio->ireg_data,
1411                                  buff,
1412                                  sge_pio->ireg_offset_range,
1413                                  sge_pio->ireg_local_offset);
1414                 ch_sge_dbg++;
1415         }
1416
1417         if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
1418                 sge_qbase = (struct sge_qbase_reg_field *)ch_sge_dbg;
1419                 /* 1 addr reg SGE_QBASE_INDEX and 4 data reg
1420                  * SGE_QBASE_MAP[0-3]
1421                  */
1422                 sge_qbase->reg_addr = t6_sge_qbase_index_array[0];
1423                 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++)
1424                         sge_qbase->reg_data[i] =
1425                                 t6_sge_qbase_index_array[i + 1];
1426
1427                 for (i = 0; i <= PCIE_FW_MASTER_M; i++)
1428                         cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1429                                                           i, true);
1430
1431                 for (i = 0; i < padap->params.arch.vfcount; i++)
1432                         cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1433                                                           i, false);
1434
1435                 sge_qbase->vfcount = padap->params.arch.vfcount;
1436         }
1437
1438         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1439 }
1440
1441 int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init,
1442                            struct cudbg_buffer *dbg_buff,
1443                            struct cudbg_error *cudbg_err)
1444 {
1445         struct adapter *padap = pdbg_init->adap;
1446         struct cudbg_buffer temp_buff = { 0 };
1447         struct cudbg_ulprx_la *ulprx_la_buff;
1448         int rc;
1449
1450         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulprx_la),
1451                             &temp_buff);
1452         if (rc)
1453                 return rc;
1454
1455         ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data;
1456         t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data);
1457         ulprx_la_buff->size = ULPRX_LA_SIZE;
1458         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1459 }
1460
1461 int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
1462                         struct cudbg_buffer *dbg_buff,
1463                         struct cudbg_error *cudbg_err)
1464 {
1465         struct adapter *padap = pdbg_init->adap;
1466         struct cudbg_buffer temp_buff = { 0 };
1467         struct cudbg_tp_la *tp_la_buff;
1468         int size, rc;
1469
1470         size = sizeof(struct cudbg_tp_la) + TPLA_SIZE *  sizeof(u64);
1471         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1472         if (rc)
1473                 return rc;
1474
1475         tp_la_buff = (struct cudbg_tp_la *)temp_buff.data;
1476         tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A));
1477         t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL);
1478         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1479 }
1480
1481 int cudbg_collect_meminfo(struct cudbg_init *pdbg_init,
1482                           struct cudbg_buffer *dbg_buff,
1483                           struct cudbg_error *cudbg_err)
1484 {
1485         struct adapter *padap = pdbg_init->adap;
1486         struct cudbg_buffer temp_buff = { 0 };
1487         struct cudbg_meminfo *meminfo_buff;
1488         struct cudbg_ver_hdr *ver_hdr;
1489         int rc;
1490
1491         rc = cudbg_get_buff(pdbg_init, dbg_buff,
1492                             sizeof(struct cudbg_ver_hdr) +
1493                             sizeof(struct cudbg_meminfo),
1494                             &temp_buff);
1495         if (rc)
1496                 return rc;
1497
1498         ver_hdr = (struct cudbg_ver_hdr *)temp_buff.data;
1499         ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
1500         ver_hdr->revision = CUDBG_MEMINFO_REV;
1501         ver_hdr->size = sizeof(struct cudbg_meminfo);
1502
1503         meminfo_buff = (struct cudbg_meminfo *)(temp_buff.data +
1504                                                 sizeof(*ver_hdr));
1505         rc = cudbg_fill_meminfo(padap, meminfo_buff);
1506         if (rc) {
1507                 cudbg_err->sys_err = rc;
1508                 cudbg_put_buff(pdbg_init, &temp_buff);
1509                 return rc;
1510         }
1511
1512         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1513 }
1514
1515 int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
1516                              struct cudbg_buffer *dbg_buff,
1517                              struct cudbg_error *cudbg_err)
1518 {
1519         struct cudbg_cim_pif_la *cim_pif_la_buff;
1520         struct adapter *padap = pdbg_init->adap;
1521         struct cudbg_buffer temp_buff = { 0 };
1522         int size, rc;
1523
1524         size = sizeof(struct cudbg_cim_pif_la) +
1525                2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
1526         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1527         if (rc)
1528                 return rc;
1529
1530         cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data;
1531         cim_pif_la_buff->size = CIM_PIFLA_SIZE;
1532         t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data,
1533                            (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE,
1534                            NULL, NULL);
1535         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1536 }
1537
1538 int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
1539                            struct cudbg_buffer *dbg_buff,
1540                            struct cudbg_error *cudbg_err)
1541 {
1542         struct adapter *padap = pdbg_init->adap;
1543         struct cudbg_buffer temp_buff = { 0 };
1544         struct cudbg_clk_info *clk_info_buff;
1545         u64 tp_tick_us;
1546         int rc;
1547
1548         if (!padap->params.vpd.cclk)
1549                 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1550
1551         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_clk_info),
1552                             &temp_buff);
1553         if (rc)
1554                 return rc;
1555
1556         clk_info_buff = (struct cudbg_clk_info *)temp_buff.data;
1557         clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */
1558         clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);
1559         clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res);
1560         clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res);
1561         tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;
1562
1563         clk_info_buff->dack_timer =
1564                 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 *
1565                 t4_read_reg(padap, TP_DACK_TIMER_A);
1566         clk_info_buff->retransmit_min =
1567                 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);
1568         clk_info_buff->retransmit_max =
1569                 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);
1570         clk_info_buff->persist_timer_min =
1571                 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);
1572         clk_info_buff->persist_timer_max =
1573                 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);
1574         clk_info_buff->keepalive_idle_timer =
1575                 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);
1576         clk_info_buff->keepalive_interval =
1577                 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);
1578         clk_info_buff->initial_srtt =
1579                 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));
1580         clk_info_buff->finwait2_timer =
1581                 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);
1582
1583         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1584 }
1585
1586 int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
1587                                 struct cudbg_buffer *dbg_buff,
1588                                 struct cudbg_error *cudbg_err)
1589 {
1590         struct adapter *padap = pdbg_init->adap;
1591         struct cudbg_buffer temp_buff = { 0 };
1592         struct ireg_buf *ch_pcie;
1593         int i, rc, n;
1594         u32 size;
1595
1596         n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1597         size = sizeof(struct ireg_buf) * n * 2;
1598         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1599         if (rc)
1600                 return rc;
1601
1602         ch_pcie = (struct ireg_buf *)temp_buff.data;
1603         /* PCIE_PDBG */
1604         for (i = 0; i < n; i++) {
1605                 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1606                 u32 *buff = ch_pcie->outbuf;
1607
1608                 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0];
1609                 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1];
1610                 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2];
1611                 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3];
1612                 t4_read_indirect(padap,
1613                                  pcie_pio->ireg_addr,
1614                                  pcie_pio->ireg_data,
1615                                  buff,
1616                                  pcie_pio->ireg_offset_range,
1617                                  pcie_pio->ireg_local_offset);
1618                 ch_pcie++;
1619         }
1620
1621         /* PCIE_CDBG */
1622         n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1623         for (i = 0; i < n; i++) {
1624                 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1625                 u32 *buff = ch_pcie->outbuf;
1626
1627                 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0];
1628                 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1];
1629                 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2];
1630                 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3];
1631                 t4_read_indirect(padap,
1632                                  pcie_pio->ireg_addr,
1633                                  pcie_pio->ireg_data,
1634                                  buff,
1635                                  pcie_pio->ireg_offset_range,
1636                                  pcie_pio->ireg_local_offset);
1637                 ch_pcie++;
1638         }
1639         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1640 }
1641
1642 int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
1643                               struct cudbg_buffer *dbg_buff,
1644                               struct cudbg_error *cudbg_err)
1645 {
1646         struct adapter *padap = pdbg_init->adap;
1647         struct cudbg_buffer temp_buff = { 0 };
1648         struct ireg_buf *ch_pm;
1649         int i, rc, n;
1650         u32 size;
1651
1652         n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
1653         size = sizeof(struct ireg_buf) * n * 2;
1654         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1655         if (rc)
1656                 return rc;
1657
1658         ch_pm = (struct ireg_buf *)temp_buff.data;
1659         /* PM_RX */
1660         for (i = 0; i < n; i++) {
1661                 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1662                 u32 *buff = ch_pm->outbuf;
1663
1664                 pm_pio->ireg_addr = t5_pm_rx_array[i][0];
1665                 pm_pio->ireg_data = t5_pm_rx_array[i][1];
1666                 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2];
1667                 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3];
1668                 t4_read_indirect(padap,
1669                                  pm_pio->ireg_addr,
1670                                  pm_pio->ireg_data,
1671                                  buff,
1672                                  pm_pio->ireg_offset_range,
1673                                  pm_pio->ireg_local_offset);
1674                 ch_pm++;
1675         }
1676
1677         /* PM_TX */
1678         n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32));
1679         for (i = 0; i < n; i++) {
1680                 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1681                 u32 *buff = ch_pm->outbuf;
1682
1683                 pm_pio->ireg_addr = t5_pm_tx_array[i][0];
1684                 pm_pio->ireg_data = t5_pm_tx_array[i][1];
1685                 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2];
1686                 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3];
1687                 t4_read_indirect(padap,
1688                                  pm_pio->ireg_addr,
1689                                  pm_pio->ireg_data,
1690                                  buff,
1691                                  pm_pio->ireg_offset_range,
1692                                  pm_pio->ireg_local_offset);
1693                 ch_pm++;
1694         }
1695         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1696 }
1697
1698 int cudbg_collect_tid(struct cudbg_init *pdbg_init,
1699                       struct cudbg_buffer *dbg_buff,
1700                       struct cudbg_error *cudbg_err)
1701 {
1702         struct adapter *padap = pdbg_init->adap;
1703         struct cudbg_tid_info_region_rev1 *tid1;
1704         struct cudbg_buffer temp_buff = { 0 };
1705         struct cudbg_tid_info_region *tid;
1706         u32 para[2], val[2];
1707         int rc;
1708
1709         rc = cudbg_get_buff(pdbg_init, dbg_buff,
1710                             sizeof(struct cudbg_tid_info_region_rev1),
1711                             &temp_buff);
1712         if (rc)
1713                 return rc;
1714
1715         tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data;
1716         tid = &tid1->tid;
1717         tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
1718         tid1->ver_hdr.revision = CUDBG_TID_INFO_REV;
1719         tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) -
1720                              sizeof(struct cudbg_ver_hdr);
1721
1722         /* If firmware is not attached/alive, use backdoor register
1723          * access to collect dump.
1724          */
1725         if (!is_fw_attached(pdbg_init))
1726                 goto fill_tid;
1727
1728 #define FW_PARAM_PFVF_A(param) \
1729         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
1730          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
1731          FW_PARAMS_PARAM_Y_V(0) | \
1732          FW_PARAMS_PARAM_Z_V(0))
1733
1734         para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
1735         para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
1736         rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
1737         if (rc <  0) {
1738                 cudbg_err->sys_err = rc;
1739                 cudbg_put_buff(pdbg_init, &temp_buff);
1740                 return rc;
1741         }
1742         tid->uotid_base = val[0];
1743         tid->nuotids = val[1] - val[0] + 1;
1744
1745         if (is_t5(padap->params.chip)) {
1746                 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4;
1747         } else if (is_t6(padap->params.chip)) {
1748                 tid1->tid_start =
1749                         t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
1750                 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A);
1751
1752                 para[0] = FW_PARAM_PFVF_A(HPFILTER_START);
1753                 para[1] = FW_PARAM_PFVF_A(HPFILTER_END);
1754                 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2,
1755                                      para, val);
1756                 if (rc < 0) {
1757                         cudbg_err->sys_err = rc;
1758                         cudbg_put_buff(pdbg_init, &temp_buff);
1759                         return rc;
1760                 }
1761                 tid->hpftid_base = val[0];
1762                 tid->nhpftids = val[1] - val[0] + 1;
1763         }
1764
1765 #undef FW_PARAM_PFVF_A
1766
1767 fill_tid:
1768         tid->ntids = padap->tids.ntids;
1769         tid->nstids = padap->tids.nstids;
1770         tid->stid_base = padap->tids.stid_base;
1771         tid->hash_base = padap->tids.hash_base;
1772
1773         tid->natids = padap->tids.natids;
1774         tid->nftids = padap->tids.nftids;
1775         tid->ftid_base = padap->tids.ftid_base;
1776         tid->aftid_base = padap->tids.aftid_base;
1777         tid->aftid_end = padap->tids.aftid_end;
1778
1779         tid->sftid_base = padap->tids.sftid_base;
1780         tid->nsftids = padap->tids.nsftids;
1781
1782         tid->flags = padap->flags;
1783         tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A);
1784         tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A);
1785         tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A);
1786
1787         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1788 }
1789
1790 int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init,
1791                               struct cudbg_buffer *dbg_buff,
1792                               struct cudbg_error *cudbg_err)
1793 {
1794         struct adapter *padap = pdbg_init->adap;
1795         struct cudbg_buffer temp_buff = { 0 };
1796         u32 size, *value, j;
1797         int i, rc, n;
1798
1799         size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
1800         n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32));
1801         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1802         if (rc)
1803                 return rc;
1804
1805         value = (u32 *)temp_buff.data;
1806         for (i = 0; i < n; i++) {
1807                 for (j = t5_pcie_config_array[i][0];
1808                      j <= t5_pcie_config_array[i][1]; j += 4) {
1809                         t4_hw_pci_read_cfg4(padap, j, value);
1810                         value++;
1811                 }
1812         }
1813         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1814 }
1815
1816 static int cudbg_sge_ctxt_check_valid(u32 *buf, int type)
1817 {
1818         int index, bit, bit_pos = 0;
1819
1820         switch (type) {
1821         case CTXT_EGRESS:
1822                 bit_pos = 176;
1823                 break;
1824         case CTXT_INGRESS:
1825                 bit_pos = 141;
1826                 break;
1827         case CTXT_FLM:
1828                 bit_pos = 89;
1829                 break;
1830         }
1831         index = bit_pos / 32;
1832         bit =  bit_pos % 32;
1833         return buf[index] & (1U << bit);
1834 }
1835
1836 static int cudbg_get_ctxt_region_info(struct adapter *padap,
1837                                       struct cudbg_region_info *ctx_info,
1838                                       u8 *mem_type)
1839 {
1840         struct cudbg_mem_desc mem_desc;
1841         struct cudbg_meminfo meminfo;
1842         u32 i, j, value, found;
1843         u8 flq;
1844         int rc;
1845
1846         rc = cudbg_fill_meminfo(padap, &meminfo);
1847         if (rc)
1848                 return rc;
1849
1850         /* Get EGRESS and INGRESS context region size */
1851         for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
1852                 found = 0;
1853                 memset(&mem_desc, 0, sizeof(struct cudbg_mem_desc));
1854                 for (j = 0; j < ARRAY_SIZE(meminfo.avail); j++) {
1855                         rc = cudbg_get_mem_region(padap, &meminfo, j,
1856                                                   cudbg_region[i],
1857                                                   &mem_desc);
1858                         if (!rc) {
1859                                 found = 1;
1860                                 rc = cudbg_get_mem_relative(padap, &meminfo, j,
1861                                                             &mem_desc.base,
1862                                                             &mem_desc.limit);
1863                                 if (rc) {
1864                                         ctx_info[i].exist = false;
1865                                         break;
1866                                 }
1867                                 ctx_info[i].exist = true;
1868                                 ctx_info[i].start = mem_desc.base;
1869                                 ctx_info[i].end = mem_desc.limit;
1870                                 mem_type[i] = j;
1871                                 break;
1872                         }
1873                 }
1874                 if (!found)
1875                         ctx_info[i].exist = false;
1876         }
1877
1878         /* Get FLM and CNM max qid. */
1879         value = t4_read_reg(padap, SGE_FLM_CFG_A);
1880
1881         /* Get number of data freelist queues */
1882         flq = HDRSTARTFLQ_G(value);
1883         ctx_info[CTXT_FLM].exist = true;
1884         ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE;
1885
1886         /* The number of CONM contexts are same as number of freelist
1887          * queues.
1888          */
1889         ctx_info[CTXT_CNM].exist = true;
1890         ctx_info[CTXT_CNM].end = ctx_info[CTXT_FLM].end;
1891
1892         return 0;
1893 }
1894
1895 int cudbg_dump_context_size(struct adapter *padap)
1896 {
1897         struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1898         u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1899         u32 i, size = 0;
1900         int rc;
1901
1902         /* Get max valid qid for each type of queue */
1903         rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1904         if (rc)
1905                 return rc;
1906
1907         for (i = 0; i < CTXT_CNM; i++) {
1908                 if (!region_info[i].exist) {
1909                         if (i == CTXT_EGRESS || i == CTXT_INGRESS)
1910                                 size += CUDBG_LOWMEM_MAX_CTXT_QIDS *
1911                                         SGE_CTXT_SIZE;
1912                         continue;
1913                 }
1914
1915                 size += (region_info[i].end - region_info[i].start + 1) /
1916                         SGE_CTXT_SIZE;
1917         }
1918         return size * sizeof(struct cudbg_ch_cntxt);
1919 }
1920
1921 static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
1922                                 enum ctxt_type ctype, u32 *data)
1923 {
1924         struct adapter *padap = pdbg_init->adap;
1925         int rc = -1;
1926
1927         /* Under heavy traffic, the SGE Queue contexts registers will be
1928          * frequently accessed by firmware.
1929          *
1930          * To avoid conflicts with firmware, always ask firmware to fetch
1931          * the SGE Queue contexts via mailbox. On failure, fallback to
1932          * accessing hardware registers directly.
1933          */
1934         if (is_fw_attached(pdbg_init))
1935                 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data);
1936         if (rc)
1937                 t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
1938 }
1939
1940 static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid,
1941                                   u8 ctxt_type,
1942                                   struct cudbg_ch_cntxt **out_buff)
1943 {
1944         struct cudbg_ch_cntxt *buff = *out_buff;
1945         int rc;
1946         u32 j;
1947
1948         for (j = 0; j < max_qid; j++) {
1949                 cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data);
1950                 rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type);
1951                 if (!rc)
1952                         continue;
1953
1954                 buff->cntxt_type = ctxt_type;
1955                 buff->cntxt_id = j;
1956                 buff++;
1957                 if (ctxt_type == CTXT_FLM) {
1958                         cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data);
1959                         buff->cntxt_type = CTXT_CNM;
1960                         buff->cntxt_id = j;
1961                         buff++;
1962                 }
1963         }
1964
1965         *out_buff = buff;
1966 }
1967
1968 int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
1969                                struct cudbg_buffer *dbg_buff,
1970                                struct cudbg_error *cudbg_err)
1971 {
1972         struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1973         struct adapter *padap = pdbg_init->adap;
1974         u32 j, size, max_ctx_size, max_ctx_qid;
1975         u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1976         struct cudbg_buffer temp_buff = { 0 };
1977         struct cudbg_ch_cntxt *buff;
1978         u64 *dst_off, *src_off;
1979         u8 *ctx_buf;
1980         u8 i, k;
1981         int rc;
1982
1983         /* Get max valid qid for each type of queue */
1984         rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1985         if (rc)
1986                 return rc;
1987
1988         rc = cudbg_dump_context_size(padap);
1989         if (rc <= 0)
1990                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
1991
1992         size = rc;
1993         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1994         if (rc)
1995                 return rc;
1996
1997         /* Get buffer with enough space to read the biggest context
1998          * region in memory.
1999          */
2000         max_ctx_size = max(region_info[CTXT_EGRESS].end -
2001                            region_info[CTXT_EGRESS].start + 1,
2002                            region_info[CTXT_INGRESS].end -
2003                            region_info[CTXT_INGRESS].start + 1);
2004
2005         ctx_buf = kvzalloc(max_ctx_size, GFP_KERNEL);
2006         if (!ctx_buf) {
2007                 cudbg_put_buff(pdbg_init, &temp_buff);
2008                 return -ENOMEM;
2009         }
2010
2011         buff = (struct cudbg_ch_cntxt *)temp_buff.data;
2012
2013         /* Collect EGRESS and INGRESS context data.
2014          * In case of failures, fallback to collecting via FW or
2015          * backdoor access.
2016          */
2017         for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
2018                 if (!region_info[i].exist) {
2019                         max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
2020                         cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
2021                                               &buff);
2022                         continue;
2023                 }
2024
2025                 max_ctx_size = region_info[i].end - region_info[i].start + 1;
2026                 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
2027
2028                 /* If firmware is not attached/alive, use backdoor register
2029                  * access to collect dump.
2030                  */
2031                 if (is_fw_attached(pdbg_init)) {
2032                         t4_sge_ctxt_flush(padap, padap->mbox, i);
2033
2034                         rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i],
2035                                           region_info[i].start, max_ctx_size,
2036                                           (__be32 *)ctx_buf, 1);
2037                 }
2038
2039                 if (rc || !is_fw_attached(pdbg_init)) {
2040                         max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
2041                         cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
2042                                               &buff);
2043                         continue;
2044                 }
2045
2046                 for (j = 0; j < max_ctx_qid; j++) {
2047                         src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE);
2048                         dst_off = (u64 *)buff->data;
2049
2050                         /* The data is stored in 64-bit cpu order.  Convert it
2051                          * to big endian before parsing.
2052                          */
2053                         for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++)
2054                                 dst_off[k] = cpu_to_be64(src_off[k]);
2055
2056                         rc = cudbg_sge_ctxt_check_valid(buff->data, i);
2057                         if (!rc)
2058                                 continue;
2059
2060                         buff->cntxt_type = i;
2061                         buff->cntxt_id = j;
2062                         buff++;
2063                 }
2064         }
2065
2066         kvfree(ctx_buf);
2067
2068         /* Collect FREELIST and CONGESTION MANAGER contexts */
2069         max_ctx_size = region_info[CTXT_FLM].end -
2070                        region_info[CTXT_FLM].start + 1;
2071         max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
2072         /* Since FLM and CONM are 1-to-1 mapped, the below function
2073          * will fetch both FLM and CONM contexts.
2074          */
2075         cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff);
2076
2077         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2078 }
2079
2080 static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
2081 {
2082         *mask = x | y;
2083         y = (__force u64)cpu_to_be64(y);
2084         memcpy(addr, (char *)&y + 2, ETH_ALEN);
2085 }
2086
2087 static void cudbg_mps_rpl_backdoor(struct adapter *padap,
2088                                    struct fw_ldst_mps_rplc *mps_rplc)
2089 {
2090         if (is_t5(padap->params.chip)) {
2091                 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2092                                                           MPS_VF_RPLCT_MAP3_A));
2093                 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2094                                                           MPS_VF_RPLCT_MAP2_A));
2095                 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2096                                                           MPS_VF_RPLCT_MAP1_A));
2097                 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2098                                                           MPS_VF_RPLCT_MAP0_A));
2099         } else {
2100                 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2101                                                           MPS_VF_RPLCT_MAP7_A));
2102                 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2103                                                           MPS_VF_RPLCT_MAP6_A));
2104                 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2105                                                           MPS_VF_RPLCT_MAP5_A));
2106                 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2107                                                           MPS_VF_RPLCT_MAP4_A));
2108         }
2109         mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A));
2110         mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A));
2111         mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A));
2112         mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A));
2113 }
2114
2115 static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
2116                                     struct cudbg_mps_tcam *tcam, u32 idx)
2117 {
2118         struct adapter *padap = pdbg_init->adap;
2119         u64 tcamy, tcamx, val;
2120         u32 ctl, data2;
2121         int rc = 0;
2122
2123         if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
2124                 /* CtlReqID   - 1: use Host Driver Requester ID
2125                  * CtlCmdType - 0: Read, 1: Write
2126                  * CtlTcamSel - 0: TCAM0, 1: TCAM1
2127                  * CtlXYBitSel- 0: Y bit, 1: X bit
2128                  */
2129
2130                 /* Read tcamy */
2131                 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
2132                 if (idx < 256)
2133                         ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
2134                 else
2135                         ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1);
2136
2137                 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2138                 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2139                 tcamy = DMACH_G(val) << 32;
2140                 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2141                 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2142                 tcam->lookup_type = DATALKPTYPE_G(data2);
2143
2144                 /* 0 - Outer header, 1 - Inner header
2145                  * [71:48] bit locations are overloaded for
2146                  * outer vs. inner lookup types.
2147                  */
2148                 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2149                         /* Inner header VNI */
2150                         tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2151                         tcam->vniy = (tcam->vniy << 16) | VIDL_G(val);
2152                         tcam->dip_hit = data2 & DATADIPHIT_F;
2153                 } else {
2154                         tcam->vlan_vld = data2 & DATAVIDH2_F;
2155                         tcam->ivlan = VIDL_G(val);
2156                 }
2157
2158                 tcam->port_num = DATAPORTNUM_G(data2);
2159
2160                 /* Read tcamx. Change the control param */
2161                 ctl |= CTLXYBITSEL_V(1);
2162                 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2163                 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2164                 tcamx = DMACH_G(val) << 32;
2165                 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2166                 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2167                 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2168                         /* Inner header VNI mask */
2169                         tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2170                         tcam->vnix = (tcam->vnix << 16) | VIDL_G(val);
2171                 }
2172         } else {
2173                 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx));
2174                 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx));
2175         }
2176
2177         /* If no entry, return */
2178         if (tcamx & tcamy)
2179                 return rc;
2180
2181         tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
2182         tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
2183
2184         if (is_t5(padap->params.chip))
2185                 tcam->repli = (tcam->cls_lo & REPLICATE_F);
2186         else if (is_t6(padap->params.chip))
2187                 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F);
2188
2189         if (tcam->repli) {
2190                 struct fw_ldst_cmd ldst_cmd;
2191                 struct fw_ldst_mps_rplc mps_rplc;
2192
2193                 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
2194                 ldst_cmd.op_to_addrspace =
2195                         htonl(FW_CMD_OP_V(FW_LDST_CMD) |
2196                               FW_CMD_REQUEST_F | FW_CMD_READ_F |
2197                               FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS));
2198                 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
2199                 ldst_cmd.u.mps.rplc.fid_idx =
2200                         htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
2201                               FW_LDST_CMD_IDX_V(idx));
2202
2203                 /* If firmware is not attached/alive, use backdoor register
2204                  * access to collect dump.
2205                  */
2206                 if (is_fw_attached(pdbg_init))
2207                         rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd,
2208                                         sizeof(ldst_cmd), &ldst_cmd);
2209
2210                 if (rc || !is_fw_attached(pdbg_init)) {
2211                         cudbg_mps_rpl_backdoor(padap, &mps_rplc);
2212                         /* Ignore error since we collected directly from
2213                          * reading registers.
2214                          */
2215                         rc = 0;
2216                 } else {
2217                         mps_rplc = ldst_cmd.u.mps.rplc;
2218                 }
2219
2220                 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0);
2221                 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32);
2222                 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64);
2223                 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96);
2224                 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) {
2225                         tcam->rplc[4] = ntohl(mps_rplc.rplc159_128);
2226                         tcam->rplc[5] = ntohl(mps_rplc.rplc191_160);
2227                         tcam->rplc[6] = ntohl(mps_rplc.rplc223_192);
2228                         tcam->rplc[7] = ntohl(mps_rplc.rplc255_224);
2229                 }
2230         }
2231         cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask);
2232         tcam->idx = idx;
2233         tcam->rplc_size = padap->params.arch.mps_rplc_size;
2234         return rc;
2235 }
2236
2237 int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
2238                            struct cudbg_buffer *dbg_buff,
2239                            struct cudbg_error *cudbg_err)
2240 {
2241         struct adapter *padap = pdbg_init->adap;
2242         struct cudbg_buffer temp_buff = { 0 };
2243         u32 size = 0, i, n, total_size = 0;
2244         struct cudbg_mps_tcam *tcam;
2245         int rc;
2246
2247         n = padap->params.arch.mps_tcam_size;
2248         size = sizeof(struct cudbg_mps_tcam) * n;
2249         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2250         if (rc)
2251                 return rc;
2252
2253         tcam = (struct cudbg_mps_tcam *)temp_buff.data;
2254         for (i = 0; i < n; i++) {
2255                 rc = cudbg_collect_tcam_index(pdbg_init, tcam, i);
2256                 if (rc) {
2257                         cudbg_err->sys_err = rc;
2258                         cudbg_put_buff(pdbg_init, &temp_buff);
2259                         return rc;
2260                 }
2261                 total_size += sizeof(struct cudbg_mps_tcam);
2262                 tcam++;
2263         }
2264
2265         if (!total_size) {
2266                 rc = CUDBG_SYSTEM_ERROR;
2267                 cudbg_err->sys_err = rc;
2268                 cudbg_put_buff(pdbg_init, &temp_buff);
2269                 return rc;
2270         }
2271         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2272 }
2273
2274 int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
2275                            struct cudbg_buffer *dbg_buff,
2276                            struct cudbg_error *cudbg_err)
2277 {
2278         struct adapter *padap = pdbg_init->adap;
2279         struct cudbg_buffer temp_buff = { 0 };
2280         char vpd_str[CUDBG_VPD_VER_LEN + 1];
2281         u32 scfg_vers, vpd_vers, fw_vers;
2282         struct cudbg_vpd_data *vpd_data;
2283         struct vpd_params vpd = { 0 };
2284         int rc, ret;
2285
2286         rc = t4_get_raw_vpd_params(padap, &vpd);
2287         if (rc)
2288                 return rc;
2289
2290         rc = t4_get_fw_version(padap, &fw_vers);
2291         if (rc)
2292                 return rc;
2293
2294         /* Serial Configuration Version is located beyond the PF's vpd size.
2295          * Temporarily give access to entire EEPROM to get it.
2296          */
2297         rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE);
2298         if (rc < 0)
2299                 return rc;
2300
2301         ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN,
2302                                  &scfg_vers);
2303
2304         /* Restore back to original PF's vpd size */
2305         rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE);
2306         if (rc < 0)
2307                 return rc;
2308
2309         if (ret)
2310                 return ret;
2311
2312         rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN,
2313                                 vpd_str);
2314         if (rc)
2315                 return rc;
2316
2317         vpd_str[CUDBG_VPD_VER_LEN] = '\0';
2318         rc = kstrtouint(vpd_str, 0, &vpd_vers);
2319         if (rc)
2320                 return rc;
2321
2322         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_vpd_data),
2323                             &temp_buff);
2324         if (rc)
2325                 return rc;
2326
2327         vpd_data = (struct cudbg_vpd_data *)temp_buff.data;
2328         memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1);
2329         memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1);
2330         memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1);
2331         memcpy(vpd_data->mn, vpd.id, ID_LEN + 1);
2332         vpd_data->scfg_vers = scfg_vers;
2333         vpd_data->vpd_vers = vpd_vers;
2334         vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers);
2335         vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers);
2336         vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers);
2337         vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers);
2338         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2339 }
2340
2341 static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid,
2342                           struct cudbg_tid_data *tid_data)
2343 {
2344         struct adapter *padap = pdbg_init->adap;
2345         int i, cmd_retry = 8;
2346         u32 val;
2347
2348         /* Fill REQ_DATA regs with 0's */
2349         for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++)
2350                 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0);
2351
2352         /* Write DBIG command */
2353         val = DBGICMD_V(4) | DBGITID_V(tid);
2354         t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val);
2355         tid_data->dbig_cmd = val;
2356
2357         val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */
2358         t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val);
2359         tid_data->dbig_conf = val;
2360
2361         /* Poll the DBGICMDBUSY bit */
2362         val = 1;
2363         while (val) {
2364                 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A);
2365                 val = val & DBGICMDBUSY_F;
2366                 cmd_retry--;
2367                 if (!cmd_retry)
2368                         return CUDBG_SYSTEM_ERROR;
2369         }
2370
2371         /* Check RESP status */
2372         val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A);
2373         tid_data->dbig_rsp_stat = val;
2374         if (!(val & 1))
2375                 return CUDBG_SYSTEM_ERROR;
2376
2377         /* Read RESP data */
2378         for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++)
2379                 tid_data->data[i] = t4_read_reg(padap,
2380                                                 LE_DB_DBGI_RSP_DATA_A +
2381                                                 (i << 2));
2382         tid_data->tid = tid;
2383         return 0;
2384 }
2385
2386 static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region)
2387 {
2388         int type = LE_ET_UNKNOWN;
2389
2390         if (tid < tcam_region.server_start)
2391                 type = LE_ET_TCAM_CON;
2392         else if (tid < tcam_region.filter_start)
2393                 type = LE_ET_TCAM_SERVER;
2394         else if (tid < tcam_region.clip_start)
2395                 type = LE_ET_TCAM_FILTER;
2396         else if (tid < tcam_region.routing_start)
2397                 type = LE_ET_TCAM_CLIP;
2398         else if (tid < tcam_region.tid_hash_base)
2399                 type = LE_ET_TCAM_ROUTING;
2400         else if (tid < tcam_region.max_tid)
2401                 type = LE_ET_HASH_CON;
2402         else
2403                 type = LE_ET_INVALID_TID;
2404
2405         return type;
2406 }
2407
2408 static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data,
2409                                struct cudbg_tcam tcam_region)
2410 {
2411         int ipv6 = 0;
2412         int le_type;
2413
2414         le_type = cudbg_get_le_type(tid_data->tid, tcam_region);
2415         if (tid_data->tid & 1)
2416                 return 0;
2417
2418         if (le_type == LE_ET_HASH_CON) {
2419                 ipv6 = tid_data->data[16] & 0x8000;
2420         } else if (le_type == LE_ET_TCAM_CON) {
2421                 ipv6 = tid_data->data[16] & 0x8000;
2422                 if (ipv6)
2423                         ipv6 = tid_data->data[9] == 0x00C00000;
2424         } else {
2425                 ipv6 = 0;
2426         }
2427         return ipv6;
2428 }
2429
2430 void cudbg_fill_le_tcam_info(struct adapter *padap,
2431                              struct cudbg_tcam *tcam_region)
2432 {
2433         u32 value;
2434
2435         /* Get the LE regions */
2436         value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */
2437         tcam_region->tid_hash_base = value;
2438
2439         /* Get routing table index */
2440         value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A);
2441         tcam_region->routing_start = value;
2442
2443         /* Get clip table index. For T6 there is separate CLIP TCAM */
2444         if (is_t6(padap->params.chip))
2445                 value = t4_read_reg(padap, LE_DB_CLCAM_TID_BASE_A);
2446         else
2447                 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A);
2448         tcam_region->clip_start = value;
2449
2450         /* Get filter table index */
2451         value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A);
2452         tcam_region->filter_start = value;
2453
2454         /* Get server table index */
2455         value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A);
2456         tcam_region->server_start = value;
2457
2458         /* Check whether hash is enabled and calculate the max tids */
2459         value = t4_read_reg(padap, LE_DB_CONFIG_A);
2460         if ((value >> HASHEN_S) & 1) {
2461                 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A);
2462                 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
2463                         tcam_region->max_tid = (value & 0xFFFFF) +
2464                                                tcam_region->tid_hash_base;
2465                 } else {
2466                         value = HASHTIDSIZE_G(value);
2467                         value = 1 << value;
2468                         tcam_region->max_tid = value +
2469                                                tcam_region->tid_hash_base;
2470                 }
2471         } else { /* hash not enabled */
2472                 if (is_t6(padap->params.chip))
2473                         tcam_region->max_tid = (value & ASLIPCOMPEN_F) ?
2474                                                CUDBG_MAX_TID_COMP_EN :
2475                                                CUDBG_MAX_TID_COMP_DIS;
2476                 else
2477                         tcam_region->max_tid = CUDBG_MAX_TCAM_TID;
2478         }
2479
2480         if (is_t6(padap->params.chip))
2481                 tcam_region->max_tid += CUDBG_T6_CLIP;
2482 }
2483
2484 int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init,
2485                           struct cudbg_buffer *dbg_buff,
2486                           struct cudbg_error *cudbg_err)
2487 {
2488         struct adapter *padap = pdbg_init->adap;
2489         struct cudbg_buffer temp_buff = { 0 };
2490         struct cudbg_tcam tcam_region = { 0 };
2491         struct cudbg_tid_data *tid_data;
2492         u32 bytes = 0;
2493         int rc, size;
2494         u32 i;
2495
2496         cudbg_fill_le_tcam_info(padap, &tcam_region);
2497
2498         size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
2499         size += sizeof(struct cudbg_tcam);
2500         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2501         if (rc)
2502                 return rc;
2503
2504         memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam));
2505         bytes = sizeof(struct cudbg_tcam);
2506         tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes);
2507         /* read all tid */
2508         for (i = 0; i < tcam_region.max_tid; ) {
2509                 rc = cudbg_read_tid(pdbg_init, i, tid_data);
2510                 if (rc) {
2511                         cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
2512                         /* Update tcam header and exit */
2513                         tcam_region.max_tid = i;
2514                         memcpy(temp_buff.data, &tcam_region,
2515                                sizeof(struct cudbg_tcam));
2516                         goto out;
2517                 }
2518
2519                 if (cudbg_is_ipv6_entry(tid_data, tcam_region)) {
2520                         /* T6 CLIP TCAM: ipv6 takes 4 entries */
2521                         if (is_t6(padap->params.chip) &&
2522                             i >= tcam_region.clip_start &&
2523                             i < tcam_region.clip_start + CUDBG_T6_CLIP)
2524                                 i += 4;
2525                         else /* Main TCAM: ipv6 takes two tids */
2526                                 i += 2;
2527                 } else {
2528                         i++;
2529                 }
2530
2531                 tid_data++;
2532                 bytes += sizeof(struct cudbg_tid_data);
2533         }
2534
2535 out:
2536         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2537 }
2538
2539 int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
2540                         struct cudbg_buffer *dbg_buff,
2541                         struct cudbg_error *cudbg_err)
2542 {
2543         struct adapter *padap = pdbg_init->adap;
2544         struct cudbg_buffer temp_buff = { 0 };
2545         u32 size;
2546         int rc;
2547
2548         size = sizeof(u16) * NMTUS * NCCTRL_WIN;
2549         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2550         if (rc)
2551                 return rc;
2552
2553         t4_read_cong_tbl(padap, (void *)temp_buff.data);
2554         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2555 }
2556
2557 int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
2558                               struct cudbg_buffer *dbg_buff,
2559                               struct cudbg_error *cudbg_err)
2560 {
2561         struct adapter *padap = pdbg_init->adap;
2562         struct cudbg_buffer temp_buff = { 0 };
2563         struct ireg_buf *ma_indr;
2564         int i, rc, n;
2565         u32 size, j;
2566
2567         if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2568                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2569
2570         n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2571         size = sizeof(struct ireg_buf) * n * 2;
2572         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2573         if (rc)
2574                 return rc;
2575
2576         ma_indr = (struct ireg_buf *)temp_buff.data;
2577         for (i = 0; i < n; i++) {
2578                 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2579                 u32 *buff = ma_indr->outbuf;
2580
2581                 ma_fli->ireg_addr = t6_ma_ireg_array[i][0];
2582                 ma_fli->ireg_data = t6_ma_ireg_array[i][1];
2583                 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2];
2584                 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3];
2585                 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data,
2586                                  buff, ma_fli->ireg_offset_range,
2587                                  ma_fli->ireg_local_offset);
2588                 ma_indr++;
2589         }
2590
2591         n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32));
2592         for (i = 0; i < n; i++) {
2593                 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2594                 u32 *buff = ma_indr->outbuf;
2595
2596                 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0];
2597                 ma_fli->ireg_data = t6_ma_ireg_array2[i][1];
2598                 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2];
2599                 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) {
2600                         t4_read_indirect(padap, ma_fli->ireg_addr,
2601                                          ma_fli->ireg_data, buff, 1,
2602                                          ma_fli->ireg_local_offset);
2603                         buff++;
2604                         ma_fli->ireg_local_offset += 0x20;
2605                 }
2606                 ma_indr++;
2607         }
2608         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2609 }
2610
2611 int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init,
2612                            struct cudbg_buffer *dbg_buff,
2613                            struct cudbg_error *cudbg_err)
2614 {
2615         struct adapter *padap = pdbg_init->adap;
2616         struct cudbg_buffer temp_buff = { 0 };
2617         struct cudbg_ulptx_la *ulptx_la_buff;
2618         struct cudbg_ver_hdr *ver_hdr;
2619         u32 i, j;
2620         int rc;
2621
2622         rc = cudbg_get_buff(pdbg_init, dbg_buff,
2623                             sizeof(struct cudbg_ver_hdr) +
2624                             sizeof(struct cudbg_ulptx_la),
2625                             &temp_buff);
2626         if (rc)
2627                 return rc;
2628
2629         ver_hdr = (struct cudbg_ver_hdr *)temp_buff.data;
2630         ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
2631         ver_hdr->revision = CUDBG_ULPTX_LA_REV;
2632         ver_hdr->size = sizeof(struct cudbg_ulptx_la);
2633
2634         ulptx_la_buff = (struct cudbg_ulptx_la *)(temp_buff.data +
2635                                                   sizeof(*ver_hdr));
2636         for (i = 0; i < CUDBG_NUM_ULPTX; i++) {
2637                 ulptx_la_buff->rdptr[i] = t4_read_reg(padap,
2638                                                       ULP_TX_LA_RDPTR_0_A +
2639                                                       0x10 * i);
2640                 ulptx_la_buff->wrptr[i] = t4_read_reg(padap,
2641                                                       ULP_TX_LA_WRPTR_0_A +
2642                                                       0x10 * i);
2643                 ulptx_la_buff->rddata[i] = t4_read_reg(padap,
2644                                                        ULP_TX_LA_RDDATA_0_A +
2645                                                        0x10 * i);
2646                 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++)
2647                         ulptx_la_buff->rd_data[i][j] =
2648                                 t4_read_reg(padap,
2649                                             ULP_TX_LA_RDDATA_0_A + 0x10 * i);
2650         }
2651
2652         for (i = 0; i < CUDBG_NUM_ULPTX_ASIC_READ; i++) {
2653                 t4_write_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A, 0x1);
2654                 ulptx_la_buff->rdptr_asic[i] =
2655                                 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A);
2656                 ulptx_la_buff->rddata_asic[i][0] =
2657                                 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_0_A);
2658                 ulptx_la_buff->rddata_asic[i][1] =
2659                                 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_1_A);
2660                 ulptx_la_buff->rddata_asic[i][2] =
2661                                 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_2_A);
2662                 ulptx_la_buff->rddata_asic[i][3] =
2663                                 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_3_A);
2664                 ulptx_la_buff->rddata_asic[i][4] =
2665                                 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_4_A);
2666                 ulptx_la_buff->rddata_asic[i][5] =
2667                                 t4_read_reg(padap, PM_RX_BASE_ADDR);
2668         }
2669
2670         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2671 }
2672
2673 int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
2674                                   struct cudbg_buffer *dbg_buff,
2675                                   struct cudbg_error *cudbg_err)
2676 {
2677         struct adapter *padap = pdbg_init->adap;
2678         struct cudbg_buffer temp_buff = { 0 };
2679         u32 local_offset, local_range;
2680         struct ireg_buf *up_cim;
2681         u32 size, j, iter;
2682         u32 instance = 0;
2683         int i, rc, n;
2684
2685         if (is_t5(padap->params.chip))
2686                 n = sizeof(t5_up_cim_reg_array) /
2687                     ((IREG_NUM_ELEM + 1) * sizeof(u32));
2688         else if (is_t6(padap->params.chip))
2689                 n = sizeof(t6_up_cim_reg_array) /
2690                     ((IREG_NUM_ELEM + 1) * sizeof(u32));
2691         else
2692                 return CUDBG_STATUS_NOT_IMPLEMENTED;
2693
2694         size = sizeof(struct ireg_buf) * n;
2695         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2696         if (rc)
2697                 return rc;
2698
2699         up_cim = (struct ireg_buf *)temp_buff.data;
2700         for (i = 0; i < n; i++) {
2701                 struct ireg_field *up_cim_reg = &up_cim->tp_pio;
2702                 u32 *buff = up_cim->outbuf;
2703
2704                 if (is_t5(padap->params.chip)) {
2705                         up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0];
2706                         up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1];
2707                         up_cim_reg->ireg_local_offset =
2708                                                 t5_up_cim_reg_array[i][2];
2709                         up_cim_reg->ireg_offset_range =
2710                                                 t5_up_cim_reg_array[i][3];
2711                         instance = t5_up_cim_reg_array[i][4];
2712                 } else if (is_t6(padap->params.chip)) {
2713                         up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0];
2714                         up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1];
2715                         up_cim_reg->ireg_local_offset =
2716                                                 t6_up_cim_reg_array[i][2];
2717                         up_cim_reg->ireg_offset_range =
2718                                                 t6_up_cim_reg_array[i][3];
2719                         instance = t6_up_cim_reg_array[i][4];
2720                 }
2721
2722                 switch (instance) {
2723                 case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES:
2724                         iter = up_cim_reg->ireg_offset_range;
2725                         local_offset = 0x120;
2726                         local_range = 1;
2727                         break;
2728                 case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES:
2729                         iter = up_cim_reg->ireg_offset_range;
2730                         local_offset = 0x10;
2731                         local_range = 1;
2732                         break;
2733                 default:
2734                         iter = 1;
2735                         local_offset = 0;
2736                         local_range = up_cim_reg->ireg_offset_range;
2737                         break;
2738                 }
2739
2740                 for (j = 0; j < iter; j++, buff++) {
2741                         rc = t4_cim_read(padap,
2742                                          up_cim_reg->ireg_local_offset +
2743                                          (j * local_offset), local_range, buff);
2744                         if (rc) {
2745                                 cudbg_put_buff(pdbg_init, &temp_buff);
2746                                 return rc;
2747                         }
2748                 }
2749                 up_cim++;
2750         }
2751         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2752 }
2753
2754 int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init,
2755                              struct cudbg_buffer *dbg_buff,
2756                              struct cudbg_error *cudbg_err)
2757 {
2758         struct adapter *padap = pdbg_init->adap;
2759         struct cudbg_buffer temp_buff = { 0 };
2760         struct cudbg_pbt_tables *pbt;
2761         int i, rc;
2762         u32 addr;
2763
2764         rc = cudbg_get_buff(pdbg_init, dbg_buff,
2765                             sizeof(struct cudbg_pbt_tables),
2766                             &temp_buff);
2767         if (rc)
2768                 return rc;
2769
2770         pbt = (struct cudbg_pbt_tables *)temp_buff.data;
2771         /* PBT dynamic entries */
2772         addr = CUDBG_CHAC_PBT_ADDR;
2773         for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) {
2774                 rc = t4_cim_read(padap, addr + (i * 4), 1,
2775                                  &pbt->pbt_dynamic[i]);
2776                 if (rc) {
2777                         cudbg_err->sys_err = rc;
2778                         cudbg_put_buff(pdbg_init, &temp_buff);
2779                         return rc;
2780                 }
2781         }
2782
2783         /* PBT static entries */
2784         /* static entries start when bit 6 is set */
2785         addr = CUDBG_CHAC_PBT_ADDR + (1 << 6);
2786         for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) {
2787                 rc = t4_cim_read(padap, addr + (i * 4), 1,
2788                                  &pbt->pbt_static[i]);
2789                 if (rc) {
2790                         cudbg_err->sys_err = rc;
2791                         cudbg_put_buff(pdbg_init, &temp_buff);
2792                         return rc;
2793                 }
2794         }
2795
2796         /* LRF entries */
2797         addr = CUDBG_CHAC_PBT_LRF;
2798         for (i = 0; i < CUDBG_LRF_ENTRIES; i++) {
2799                 rc = t4_cim_read(padap, addr + (i * 4), 1,
2800                                  &pbt->lrf_table[i]);
2801                 if (rc) {
2802                         cudbg_err->sys_err = rc;
2803                         cudbg_put_buff(pdbg_init, &temp_buff);
2804                         return rc;
2805                 }
2806         }
2807
2808         /* PBT data entries */
2809         addr = CUDBG_CHAC_PBT_DATA;
2810         for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) {
2811                 rc = t4_cim_read(padap, addr + (i * 4), 1,
2812                                  &pbt->pbt_data[i]);
2813                 if (rc) {
2814                         cudbg_err->sys_err = rc;
2815                         cudbg_put_buff(pdbg_init, &temp_buff);
2816                         return rc;
2817                 }
2818         }
2819         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2820 }
2821
2822 int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,
2823                            struct cudbg_buffer *dbg_buff,
2824                            struct cudbg_error *cudbg_err)
2825 {
2826         struct adapter *padap = pdbg_init->adap;
2827         struct cudbg_mbox_log *mboxlog = NULL;
2828         struct cudbg_buffer temp_buff = { 0 };
2829         struct mbox_cmd_log *log = NULL;
2830         struct mbox_cmd *entry;
2831         unsigned int entry_idx;
2832         u16 mbox_cmds;
2833         int i, k, rc;
2834         u64 flit;
2835         u32 size;
2836
2837         log = padap->mbox_log;
2838         mbox_cmds = padap->mbox_log->size;
2839         size = sizeof(struct cudbg_mbox_log) * mbox_cmds;
2840         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2841         if (rc)
2842                 return rc;
2843
2844         mboxlog = (struct cudbg_mbox_log *)temp_buff.data;
2845         for (k = 0; k < mbox_cmds; k++) {
2846                 entry_idx = log->cursor + k;
2847                 if (entry_idx >= log->size)
2848                         entry_idx -= log->size;
2849
2850                 entry = mbox_cmd_log_entry(log, entry_idx);
2851                 /* skip over unused entries */
2852                 if (entry->timestamp == 0)
2853                         continue;
2854
2855                 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd));
2856                 for (i = 0; i < MBOX_LEN / 8; i++) {
2857                         flit = entry->cmd[i];
2858                         mboxlog->hi[i] = (u32)(flit >> 32);
2859                         mboxlog->lo[i] = (u32)flit;
2860                 }
2861                 mboxlog++;
2862         }
2863         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2864 }
2865
2866 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
2867                                struct cudbg_buffer *dbg_buff,
2868                                struct cudbg_error *cudbg_err)
2869 {
2870         struct adapter *padap = pdbg_init->adap;
2871         struct cudbg_buffer temp_buff = { 0 };
2872         struct ireg_buf *hma_indr;
2873         int i, rc, n;
2874         u32 size;
2875
2876         if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2877                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2878
2879         n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2880         size = sizeof(struct ireg_buf) * n;
2881         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2882         if (rc)
2883                 return rc;
2884
2885         hma_indr = (struct ireg_buf *)temp_buff.data;
2886         for (i = 0; i < n; i++) {
2887                 struct ireg_field *hma_fli = &hma_indr->tp_pio;
2888                 u32 *buff = hma_indr->outbuf;
2889
2890                 hma_fli->ireg_addr = t6_hma_ireg_array[i][0];
2891                 hma_fli->ireg_data = t6_hma_ireg_array[i][1];
2892                 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2];
2893                 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3];
2894                 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data,
2895                                  buff, hma_fli->ireg_offset_range,
2896                                  hma_fli->ireg_local_offset);
2897                 hma_indr++;
2898         }
2899         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2900 }
2901
2902 void cudbg_fill_qdesc_num_and_size(const struct adapter *padap,
2903                                    u32 *num, u32 *size)
2904 {
2905         u32 tot_entries = 0, tot_size = 0;
2906
2907         /* NIC TXQ, RXQ, FLQ, and CTRLQ */
2908         tot_entries += MAX_ETH_QSETS * 3;
2909         tot_entries += MAX_CTRL_QUEUES;
2910
2911         tot_size += MAX_ETH_QSETS * MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2912         tot_size += MAX_ETH_QSETS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
2913         tot_size += MAX_ETH_QSETS * MAX_RX_BUFFERS * MAX_FL_DESC_SIZE;
2914         tot_size += MAX_CTRL_QUEUES * MAX_CTRL_TXQ_ENTRIES *
2915                     MAX_CTRL_TXQ_DESC_SIZE;
2916
2917         /* FW_EVTQ and INTRQ */
2918         tot_entries += INGQ_EXTRAS;
2919         tot_size += INGQ_EXTRAS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
2920
2921         /* PTP_TXQ */
2922         tot_entries += 1;
2923         tot_size += MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2924
2925         /* ULD TXQ, RXQ, and FLQ */
2926         tot_entries += CXGB4_TX_MAX * MAX_OFLD_QSETS;
2927         tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS * 2;
2928
2929         tot_size += CXGB4_TX_MAX * MAX_OFLD_QSETS * MAX_TXQ_ENTRIES *
2930                     MAX_TXQ_DESC_SIZE;
2931         tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RSPQ_ENTRIES *
2932                     MAX_RXQ_DESC_SIZE;
2933         tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RX_BUFFERS *
2934                     MAX_FL_DESC_SIZE;
2935
2936         /* ULD CIQ */
2937         tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS;
2938         tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * SGE_MAX_IQ_SIZE *
2939                     MAX_RXQ_DESC_SIZE;
2940
2941         /* ETHOFLD TXQ, RXQ, and FLQ */
2942         tot_entries += MAX_OFLD_QSETS * 3;
2943         tot_size += MAX_OFLD_QSETS * MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2944
2945         tot_size += sizeof(struct cudbg_ver_hdr) +
2946                     sizeof(struct cudbg_qdesc_info) +
2947                     sizeof(struct cudbg_qdesc_entry) * tot_entries;
2948
2949         if (num)
2950                 *num = tot_entries;
2951
2952         if (size)
2953                 *size = tot_size;
2954 }
2955
2956 int cudbg_collect_qdesc(struct cudbg_init *pdbg_init,
2957                         struct cudbg_buffer *dbg_buff,
2958                         struct cudbg_error *cudbg_err)
2959 {
2960         u32 num_queues = 0, tot_entries = 0, size = 0;
2961         struct adapter *padap = pdbg_init->adap;
2962         struct cudbg_buffer temp_buff = { 0 };
2963         struct cudbg_qdesc_entry *qdesc_entry;
2964         struct cudbg_qdesc_info *qdesc_info;
2965         struct cudbg_ver_hdr *ver_hdr;
2966         struct sge *s = &padap->sge;
2967         u32 i, j, cur_off, tot_len;
2968         u8 *data;
2969         int rc;
2970
2971         cudbg_fill_qdesc_num_and_size(padap, &tot_entries, &size);
2972         size = min_t(u32, size, CUDBG_DUMP_BUFF_SIZE);
2973         tot_len = size;
2974         data = kvzalloc(size, GFP_KERNEL);
2975         if (!data)
2976                 return -ENOMEM;
2977
2978         ver_hdr = (struct cudbg_ver_hdr *)data;
2979         ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
2980         ver_hdr->revision = CUDBG_QDESC_REV;
2981         ver_hdr->size = sizeof(struct cudbg_qdesc_info);
2982         size -= sizeof(*ver_hdr);
2983
2984         qdesc_info = (struct cudbg_qdesc_info *)(data +
2985                                                  sizeof(*ver_hdr));
2986         size -= sizeof(*qdesc_info);
2987         qdesc_entry = (struct cudbg_qdesc_entry *)qdesc_info->data;
2988
2989 #define QDESC_GET(q, desc, type, label) do { \
2990         if (size <= 0) { \
2991                 goto label; \
2992         } \
2993         if (desc) { \
2994                 cudbg_fill_qdesc_##q(q, type, qdesc_entry); \
2995                 size -= sizeof(*qdesc_entry) + qdesc_entry->data_size; \
2996                 num_queues++; \
2997                 qdesc_entry = cudbg_next_qdesc(qdesc_entry); \
2998         } \
2999 } while (0)
3000
3001 #define QDESC_GET_TXQ(q, type, label) do { \
3002         struct sge_txq *txq = (struct sge_txq *)q; \
3003         QDESC_GET(txq, txq->desc, type, label); \
3004 } while (0)
3005
3006 #define QDESC_GET_RXQ(q, type, label) do { \
3007         struct sge_rspq *rxq = (struct sge_rspq *)q; \
3008         QDESC_GET(rxq, rxq->desc, type, label); \
3009 } while (0)
3010
3011 #define QDESC_GET_FLQ(q, type, label) do { \
3012         struct sge_fl *flq = (struct sge_fl *)q; \
3013         QDESC_GET(flq, flq->desc, type, label); \
3014 } while (0)
3015
3016         /* NIC TXQ */
3017         for (i = 0; i < s->ethqsets; i++)
3018                 QDESC_GET_TXQ(&s->ethtxq[i].q, CUDBG_QTYPE_NIC_TXQ, out);
3019
3020         /* NIC RXQ */
3021         for (i = 0; i < s->ethqsets; i++)
3022                 QDESC_GET_RXQ(&s->ethrxq[i].rspq, CUDBG_QTYPE_NIC_RXQ, out);
3023
3024         /* NIC FLQ */
3025         for (i = 0; i < s->ethqsets; i++)
3026                 QDESC_GET_FLQ(&s->ethrxq[i].fl, CUDBG_QTYPE_NIC_FLQ, out);
3027
3028         /* NIC CTRLQ */
3029         for (i = 0; i < padap->params.nports; i++)
3030                 QDESC_GET_TXQ(&s->ctrlq[i].q, CUDBG_QTYPE_CTRLQ, out);
3031
3032         /* FW_EVTQ */
3033         QDESC_GET_RXQ(&s->fw_evtq, CUDBG_QTYPE_FWEVTQ, out);
3034
3035         /* INTRQ */
3036         QDESC_GET_RXQ(&s->intrq, CUDBG_QTYPE_INTRQ, out);
3037
3038         /* PTP_TXQ */
3039         QDESC_GET_TXQ(&s->ptptxq.q, CUDBG_QTYPE_PTP_TXQ, out);
3040
3041         /* ULD Queues */
3042         mutex_lock(&uld_mutex);
3043
3044         if (s->uld_txq_info) {
3045                 struct sge_uld_txq_info *utxq;
3046
3047                 /* ULD TXQ */
3048                 for (j = 0; j < CXGB4_TX_MAX; j++) {
3049                         if (!s->uld_txq_info[j])
3050                                 continue;
3051
3052                         utxq = s->uld_txq_info[j];
3053                         for (i = 0; i < utxq->ntxq; i++)
3054                                 QDESC_GET_TXQ(&utxq->uldtxq[i].q,
3055                                               cudbg_uld_txq_to_qtype(j),
3056                                               out_unlock);
3057                 }
3058         }
3059
3060         if (s->uld_rxq_info) {
3061                 struct sge_uld_rxq_info *urxq;
3062                 u32 base;
3063
3064                 /* ULD RXQ */
3065                 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3066                         if (!s->uld_rxq_info[j])
3067                                 continue;
3068
3069                         urxq = s->uld_rxq_info[j];
3070                         for (i = 0; i < urxq->nrxq; i++)
3071                                 QDESC_GET_RXQ(&urxq->uldrxq[i].rspq,
3072                                               cudbg_uld_rxq_to_qtype(j),
3073                                               out_unlock);
3074                 }
3075
3076                 /* ULD FLQ */
3077                 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3078                         if (!s->uld_rxq_info[j])
3079                                 continue;
3080
3081                         urxq = s->uld_rxq_info[j];
3082                         for (i = 0; i < urxq->nrxq; i++)
3083                                 QDESC_GET_FLQ(&urxq->uldrxq[i].fl,
3084                                               cudbg_uld_flq_to_qtype(j),
3085                                               out_unlock);
3086                 }
3087
3088                 /* ULD CIQ */
3089                 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3090                         if (!s->uld_rxq_info[j])
3091                                 continue;
3092
3093                         urxq = s->uld_rxq_info[j];
3094                         base = urxq->nrxq;
3095                         for (i = 0; i < urxq->nciq; i++)
3096                                 QDESC_GET_RXQ(&urxq->uldrxq[base + i].rspq,
3097                                               cudbg_uld_ciq_to_qtype(j),
3098                                               out_unlock);
3099                 }
3100         }
3101
3102         /* ETHOFLD TXQ */
3103         if (s->eohw_txq)
3104                 for (i = 0; i < s->eoqsets; i++)
3105                         QDESC_GET_TXQ(&s->eohw_txq[i].q,
3106                                       CUDBG_QTYPE_ETHOFLD_TXQ, out);
3107
3108         /* ETHOFLD RXQ and FLQ */
3109         if (s->eohw_rxq) {
3110                 for (i = 0; i < s->eoqsets; i++)
3111                         QDESC_GET_RXQ(&s->eohw_rxq[i].rspq,
3112                                       CUDBG_QTYPE_ETHOFLD_RXQ, out);
3113
3114                 for (i = 0; i < s->eoqsets; i++)
3115                         QDESC_GET_FLQ(&s->eohw_rxq[i].fl,
3116                                       CUDBG_QTYPE_ETHOFLD_FLQ, out);
3117         }
3118
3119 out_unlock:
3120         mutex_unlock(&uld_mutex);
3121
3122 out:
3123         qdesc_info->qdesc_entry_size = sizeof(*qdesc_entry);
3124         qdesc_info->num_queues = num_queues;
3125         cur_off = 0;
3126         while (tot_len) {
3127                 u32 chunk_size = min_t(u32, tot_len, CUDBG_CHUNK_SIZE);
3128
3129                 rc = cudbg_get_buff(pdbg_init, dbg_buff, chunk_size,
3130                                     &temp_buff);
3131                 if (rc) {
3132                         cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3133                         goto out_free;
3134                 }
3135
3136                 memcpy(temp_buff.data, data + cur_off, chunk_size);
3137                 tot_len -= chunk_size;
3138                 cur_off += chunk_size;
3139                 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
3140                                                   dbg_buff);
3141                 if (rc) {
3142                         cudbg_put_buff(pdbg_init, &temp_buff);
3143                         cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3144                         goto out_free;
3145                 }
3146         }
3147
3148 out_free:
3149         if (data)
3150                 kvfree(data);
3151
3152 #undef QDESC_GET_FLQ
3153 #undef QDESC_GET_RXQ
3154 #undef QDESC_GET_TXQ
3155 #undef QDESC_GET
3156
3157         return rc;
3158 }
3159
3160 int cudbg_collect_flash(struct cudbg_init *pdbg_init,
3161                         struct cudbg_buffer *dbg_buff,
3162                         struct cudbg_error *cudbg_err)
3163 {
3164         struct adapter *padap = pdbg_init->adap;
3165         u32 count = padap->params.sf_size, n;
3166         struct cudbg_buffer temp_buff = {0};
3167         u32 addr, i;
3168         int rc;
3169
3170         addr = FLASH_EXP_ROM_START;
3171
3172         for (i = 0; i < count; i += SF_PAGE_SIZE) {
3173                 n = min_t(u32, count - i, SF_PAGE_SIZE);
3174
3175                 rc = cudbg_get_buff(pdbg_init, dbg_buff, n, &temp_buff);
3176                 if (rc) {
3177                         cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3178                         goto out;
3179                 }
3180                 rc = t4_read_flash(padap, addr, n, (u32 *)temp_buff.data, 0);
3181                 if (rc)
3182                         goto out;
3183
3184                 addr += (n * 4);
3185                 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
3186                                                   dbg_buff);
3187                 if (rc) {
3188                         cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3189                         goto out;
3190                 }
3191         }
3192
3193 out:
3194         return rc;
3195 }