drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

   1 /*
   2  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify it
   5  *  under the terms and conditions of the GNU General Public License,
   6  *  version 2, as published by the Free Software Foundation.
   7  *
   8  *  This program is distributed in the hope it will be useful, but WITHOUT
   9  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  *  more details.
  12  *
  13  *  The full GNU General Public License is included in this distribution in
  14  *  the file called "COPYING".
  15  *
  16  */
  17
  18 #ifndef __CUDBG_ENTITY_H__
  19 #define __CUDBG_ENTITY_H__
  20
  21 #define EDC0_FLAG 3
  22 #define EDC1_FLAG 4
  23
  24 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
  25
  26 struct card_mem {
  27         u16 size_edc0;
  28         u16 size_edc1;
  29         u16 mem_flag;
  30 };
  31
  32 struct cudbg_mbox_log {
  33         struct mbox_cmd entry;
  34         u32 hi[MBOX_LEN / 8];
  35         u32 lo[MBOX_LEN / 8];
  36 };
  37
  38 struct cudbg_cim_qcfg {
  39         u8 chip;
  40         u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
  41         u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
  42         u16 thres[CIM_NUM_IBQ];
  43         u32 obq_wr[2 * CIM_NUM_OBQ_T5];
  44         u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
  45 };
  46
  47 struct cudbg_rss_vf_conf {
  48         u32 rss_vf_vfl;
  49         u32 rss_vf_vfh;
  50 };
  51
  52 struct cudbg_hw_sched {
  53         u32 kbps[NTX_SCHED];
  54         u32 ipg[NTX_SCHED];
  55         u32 pace_tab[NTX_SCHED];
  56         u32 mode;
  57         u32 map;
  58 };
  59
  60 struct ireg_field {
  61         u32 ireg_addr;
  62         u32 ireg_data;
  63         u32 ireg_local_offset;
  64         u32 ireg_offset_range;
  65 };
  66
  67 struct ireg_buf {
  68         struct ireg_field tp_pio;
  69         u32 outbuf[32];
  70 };
  71
  72 struct cudbg_ulprx_la {
  73         u32 data[ULPRX_LA_SIZE * 8];
  74         u32 size;
  75 };
  76
  77 struct cudbg_tp_la {
  78         u32 size;
  79         u32 mode;
  80         u8 data[0];
  81 };
  82
  83 struct cudbg_cim_pif_la {
  84         int size;
  85         u8 data[0];
  86 };
  87
  88 struct cudbg_tid_info_region {
  89         u32 ntids;
  90         u32 nstids;
  91         u32 stid_base;
  92         u32 hash_base;
  93
  94         u32 natids;
  95         u32 nftids;
  96         u32 ftid_base;
  97         u32 aftid_base;
  98         u32 aftid_end;
  99
 100         u32 sftid_base;
 101         u32 nsftids;
 102
 103         u32 uotid_base;
 104         u32 nuotids;
 105
 106         u32 sb;
 107         u32 flags;
 108         u32 le_db_conf;
 109         u32 ip_users;
 110         u32 ipv6_users;
 111
 112         u32 hpftid_base;
 113         u32 nhpftids;
 114 };
 115
 116 #define CUDBG_TID_INFO_REV 1
 117
 118 struct cudbg_tid_info_region_rev1 {
 119         struct cudbg_ver_hdr ver_hdr;
 120         struct cudbg_tid_info_region tid;
 121         u32 tid_start;
 122         u32 reserved[16];
 123 };
 124
 125 #define CUDBG_MAX_RPLC_SIZE 128
 126
 127 struct cudbg_mps_tcam {
 128         u64 mask;
 129         u32 rplc[8];
 130         u32 idx;
 131         u32 cls_lo;
 132         u32 cls_hi;
 133         u32 rplc_size;
 134         u32 vniy;
 135         u32 vnix;
 136         u32 dip_hit;
 137         u32 vlan_vld;
 138         u32 repli;
 139         u16 ivlan;
 140         u8 addr[ETH_ALEN];
 141         u8 lookup_type;
 142         u8 port_num;
 143         u8 reserved[2];
 144 };
 145
 146 #define CUDBG_NUM_ULPTX 11
 147 #define CUDBG_NUM_ULPTX_READ 512
 148
 149 struct cudbg_ulptx_la {
 150         u32 rdptr[CUDBG_NUM_ULPTX];
 151         u32 wrptr[CUDBG_NUM_ULPTX];
 152         u32 rddata[CUDBG_NUM_ULPTX];
 153         u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
 154 };
 155
 156 #define CUDBG_CHAC_PBT_ADDR 0x2800
 157 #define CUDBG_CHAC_PBT_LRF  0x3000
 158 #define CUDBG_CHAC_PBT_DATA 0x3800
 159 #define CUDBG_PBT_DYNAMIC_ENTRIES 8
 160 #define CUDBG_PBT_STATIC_ENTRIES 16
 161 #define CUDBG_LRF_ENTRIES 8
 162 #define CUDBG_PBT_DATA_ENTRIES 512
 163
 164 struct cudbg_pbt_tables {
 165         u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
 166         u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
 167         u32 lrf_table[CUDBG_LRF_ENTRIES];
 168         u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
 169 };
 170
 171 #define IREG_NUM_ELEM 4
 172
 173 static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
 174         {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
 175         {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
 176         {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
 177         {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
 178         {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
 179         {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
 180         {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
 181         {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
 182         {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
 183         {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
 184         {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
 185         {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
 186 };
 187
 188 static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
 189         {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
 190         {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
 191         {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
 192         {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
 193         {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
 194         {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
 195         {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
 196         {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
 197         {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
 198         {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
 199         {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
 200 };
 201
 202 static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
 203         {0x7e18, 0x7e1c, 0x0, 12}
 204 };
 205
 206 static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
 207         {0x7e18, 0x7e1c, 0x0, 12}
 208 };
 209
 210 static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
 211         {0x7e50, 0x7e54, 0x0, 13},
 212         {0x7e50, 0x7e54, 0x10, 6},
 213         {0x7e50, 0x7e54, 0x18, 21},
 214         {0x7e50, 0x7e54, 0x30, 32},
 215         {0x7e50, 0x7e54, 0x50, 22},
 216         {0x7e50, 0x7e54, 0x68, 12}
 217 };
 218
 219 static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
 220         {0x7e50, 0x7e54, 0x0, 13},
 221         {0x7e50, 0x7e54, 0x10, 6},
 222         {0x7e50, 0x7e54, 0x18, 8},
 223         {0x7e50, 0x7e54, 0x20, 13},
 224         {0x7e50, 0x7e54, 0x30, 16},
 225         {0x7e50, 0x7e54, 0x40, 16},
 226         {0x7e50, 0x7e54, 0x50, 16},
 227         {0x7e50, 0x7e54, 0x60, 6},
 228         {0x7e50, 0x7e54, 0x68, 4}
 229 };
 230
 231 static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
 232         {0x10cc, 0x10d0, 0x0, 16},
 233         {0x10cc, 0x10d4, 0x0, 16},
 234 };
 235
 236 static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
 237         {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
 238         {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
 239         {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
 240 };
 241
 242 static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
 243         {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
 244         {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
 245 };
 246
 247 static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
 248         {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
 249         {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
 250 };
 251
 252 static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
 253         {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
 254         {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
 255 };
 256
 257 static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
 258         {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
 259         {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
 260         {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
 261 };
 262
 263 static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
 264         {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
 265         {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
 266 };
 267
 268 static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {
 269         {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
 270         {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
 271         {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
 272         {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
 273         {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
 274         {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
 275         {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
 276         {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
 277         {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
 278         {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
 279         {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
 280         {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
 281         {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
 282
 283 };
 284
 285 static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {
 286         {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
 287         {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
 288         {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
 289         {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
 290         {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
 291         {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
 292         {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
 293         {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
 294         {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
 295         {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
 296         {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
 297         {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
 298         {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
 299 };
 300
 301 static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
 302         {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
 303 };
 304 #endif /* __CUDBG_ENTITY_H__ */