2 * Copyright (C) 2017 Chelsio Communications. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
18 #ifndef __CUDBG_ENTITY_H__
19 #define __CUDBG_ENTITY_H__
24 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
32 struct cudbg_mbox_log {
33 struct mbox_cmd entry;
38 struct cudbg_cim_qcfg {
40 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
41 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
42 u16 thres[CIM_NUM_IBQ];
43 u32 obq_wr[2 * CIM_NUM_OBQ_T5];
44 u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
47 struct cudbg_rss_vf_conf {
52 struct cudbg_hw_sched {
55 u32 pace_tab[NTX_SCHED];
63 u32 ireg_local_offset;
64 u32 ireg_offset_range;
68 struct ireg_field tp_pio;
72 struct cudbg_ulprx_la {
73 u32 data[ULPRX_LA_SIZE * 8];
83 struct cudbg_cim_pif_la {
88 struct cudbg_tid_info_region {
116 #define CUDBG_TID_INFO_REV 1
118 struct cudbg_tid_info_region_rev1 {
119 struct cudbg_ver_hdr ver_hdr;
120 struct cudbg_tid_info_region tid;
125 #define CUDBG_MAX_RPLC_SIZE 128
127 struct cudbg_mps_tcam {
146 #define CUDBG_NUM_ULPTX 11
147 #define CUDBG_NUM_ULPTX_READ 512
149 struct cudbg_ulptx_la {
150 u32 rdptr[CUDBG_NUM_ULPTX];
151 u32 wrptr[CUDBG_NUM_ULPTX];
152 u32 rddata[CUDBG_NUM_ULPTX];
153 u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
156 #define CUDBG_CHAC_PBT_ADDR 0x2800
157 #define CUDBG_CHAC_PBT_LRF 0x3000
158 #define CUDBG_CHAC_PBT_DATA 0x3800
159 #define CUDBG_PBT_DYNAMIC_ENTRIES 8
160 #define CUDBG_PBT_STATIC_ENTRIES 16
161 #define CUDBG_LRF_ENTRIES 8
162 #define CUDBG_PBT_DATA_ENTRIES 512
164 struct cudbg_pbt_tables {
165 u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
166 u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
167 u32 lrf_table[CUDBG_LRF_ENTRIES];
168 u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
171 #define IREG_NUM_ELEM 4
173 static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
174 {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
175 {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
176 {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
177 {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
178 {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
179 {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
180 {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
181 {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
182 {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
183 {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
184 {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
185 {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
188 static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
189 {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
190 {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
191 {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
192 {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
193 {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
194 {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
195 {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
196 {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
197 {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
198 {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
199 {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
202 static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
203 {0x7e18, 0x7e1c, 0x0, 12}
206 static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
207 {0x7e18, 0x7e1c, 0x0, 12}
210 static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
211 {0x7e50, 0x7e54, 0x0, 13},
212 {0x7e50, 0x7e54, 0x10, 6},
213 {0x7e50, 0x7e54, 0x18, 21},
214 {0x7e50, 0x7e54, 0x30, 32},
215 {0x7e50, 0x7e54, 0x50, 22},
216 {0x7e50, 0x7e54, 0x68, 12}
219 static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
220 {0x7e50, 0x7e54, 0x0, 13},
221 {0x7e50, 0x7e54, 0x10, 6},
222 {0x7e50, 0x7e54, 0x18, 8},
223 {0x7e50, 0x7e54, 0x20, 13},
224 {0x7e50, 0x7e54, 0x30, 16},
225 {0x7e50, 0x7e54, 0x40, 16},
226 {0x7e50, 0x7e54, 0x50, 16},
227 {0x7e50, 0x7e54, 0x60, 6},
228 {0x7e50, 0x7e54, 0x68, 4}
231 static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
232 {0x10cc, 0x10d0, 0x0, 16},
233 {0x10cc, 0x10d4, 0x0, 16},
236 static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
237 {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
238 {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
239 {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
242 static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
243 {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
244 {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
247 static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
248 {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
249 {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
252 static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
253 {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
254 {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
257 static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
258 {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
259 {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
260 {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
263 static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
264 {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
265 {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
268 static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {
269 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
270 {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
271 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
272 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
273 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
274 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
275 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
276 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
277 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
278 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
279 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
280 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
281 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
285 static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {
286 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
287 {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
288 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
289 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
290 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
291 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
292 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
293 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
294 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
295 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
296 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
297 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
298 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
301 static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
302 {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
304 #endif /* __CUDBG_ENTITY_H__ */