1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Cavium, Inc.
6 #include <linux/acpi.h>
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/phy.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_net.h>
19 #include "thunder_bgx.h"
21 #define DRV_NAME "thunder_bgx"
22 #define DRV_VERSION "1.0"
24 /* RX_DMAC_CTL configuration */
26 MCAST_MODE_REJECT = 0x0,
27 MCAST_MODE_ACCEPT = 0x1,
28 MCAST_MODE_CAM_FILTER = 0x2,
32 #define BCAST_ACCEPT BIT(0)
33 #define CAM_ACCEPT BIT(3)
34 #define MCAST_MODE_MASK 0x3
35 #define BGX_MCAST_MODE(x) (x << 1)
44 /* actual number of DMACs configured */
46 /* overal number of possible DMACs could be configured per LMAC */
48 struct dmac_map *dmacs; /* DMAC:VFs tracking filter array */
55 int lmacid; /* ID within BGX */
56 int lmacid_bd; /* ID on board */
57 struct net_device netdev;
58 struct phy_device *phydev;
59 unsigned int last_duplex;
60 unsigned int last_link;
61 unsigned int last_speed;
63 struct delayed_work dwork;
64 struct workqueue_struct *check_link;
69 struct lmac lmac[MAX_LMAC_PER_BGX];
73 void __iomem *reg_base;
79 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
80 static int lmac_count; /* Total no of LMACs in system */
82 static int bgx_xaui_check_link(struct lmac *lmac);
84 /* Supported devices */
85 static const struct pci_device_id bgx_id_table[] = {
86 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
87 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
88 { 0, } /* end of table */
91 MODULE_AUTHOR("Cavium Inc");
92 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
93 MODULE_LICENSE("GPL v2");
94 MODULE_VERSION(DRV_VERSION);
95 MODULE_DEVICE_TABLE(pci, bgx_id_table);
97 /* The Cavium ThunderX network controller can *only* be found in SoCs
98 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
99 * registers on this platform are implicitly strongly ordered with respect
100 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
101 * with no memory barriers in this driver. The readq()/writeq() functions add
102 * explicit ordering operation which in this case are redundant, and only
106 /* Register read/write APIs */
107 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
109 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
111 return readq_relaxed(addr);
114 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
116 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
118 writeq_relaxed(val, addr);
121 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
123 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
125 writeq_relaxed(val | readq_relaxed(addr), addr);
128 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
134 reg_val = bgx_reg_read(bgx, lmac, reg);
135 if (zero && !(reg_val & mask))
137 if (!zero && (reg_val & mask))
139 usleep_range(1000, 2000);
145 static int max_bgx_per_node;
146 static void set_max_bgx_per_node(struct pci_dev *pdev)
150 if (max_bgx_per_node)
153 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
155 case PCI_SUBSYS_DEVID_81XX_BGX:
156 case PCI_SUBSYS_DEVID_81XX_RGX:
157 max_bgx_per_node = MAX_BGX_PER_CN81XX;
159 case PCI_SUBSYS_DEVID_83XX_BGX:
160 max_bgx_per_node = MAX_BGX_PER_CN83XX;
162 case PCI_SUBSYS_DEVID_88XX_BGX:
164 max_bgx_per_node = MAX_BGX_PER_CN88XX;
169 static struct bgx *get_bgx(int node, int bgx_idx)
171 int idx = (node * max_bgx_per_node) + bgx_idx;
173 return bgx_vnic[idx];
176 /* Return number of BGX present in HW */
177 unsigned bgx_get_map(int node)
182 for (i = 0; i < max_bgx_per_node; i++) {
183 if (bgx_vnic[(node * max_bgx_per_node) + i])
189 EXPORT_SYMBOL(bgx_get_map);
191 /* Return number of LMAC configured for this BGX */
192 int bgx_get_lmac_count(int node, int bgx_idx)
196 bgx = get_bgx(node, bgx_idx);
198 return bgx->lmac_count;
202 EXPORT_SYMBOL(bgx_get_lmac_count);
204 /* Returns the current link status of LMAC */
205 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
207 struct bgx_link_status *link = (struct bgx_link_status *)status;
211 bgx = get_bgx(node, bgx_idx);
215 lmac = &bgx->lmac[lmacid];
216 link->mac_type = lmac->lmac_type;
217 link->link_up = lmac->link_up;
218 link->duplex = lmac->last_duplex;
219 link->speed = lmac->last_speed;
221 EXPORT_SYMBOL(bgx_get_lmac_link_state);
223 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
225 struct bgx *bgx = get_bgx(node, bgx_idx);
228 return bgx->lmac[lmacid].mac;
232 EXPORT_SYMBOL(bgx_get_lmac_mac);
234 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
236 struct bgx *bgx = get_bgx(node, bgx_idx);
241 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
243 EXPORT_SYMBOL(bgx_set_lmac_mac);
245 static void bgx_flush_dmac_cam_filter(struct bgx *bgx, int lmacid)
247 struct lmac *lmac = NULL;
250 lmac = &bgx->lmac[lmacid];
251 /* reset CAM filters */
252 for (idx = 0; idx < lmac->dmacs_count; idx++)
253 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
254 ((lmacid * lmac->dmacs_count) + idx) *
258 static void bgx_lmac_remove_filters(struct lmac *lmac, u8 vf_id)
265 /* We've got reset filters request from some of attached VF, while the
266 * others might want to keep their configuration. So in this case lets
267 * iterate over all of configured filters and decrease number of
268 * referencies. if some addresses get zero refs remove them from list
270 for (i = lmac->dmacs_cfg - 1; i >= 0; i--) {
271 lmac->dmacs[i].vf_map &= ~BIT_ULL(vf_id);
272 if (!lmac->dmacs[i].vf_map) {
274 lmac->dmacs[i].dmac = 0;
275 lmac->dmacs[i].vf_map = 0;
280 static int bgx_lmac_save_filter(struct lmac *lmac, u64 dmac, u8 vf_id)
287 /* At the same time we could have several VFs 'attached' to some
288 * particular LMAC, and each VF is represented as network interface
289 * for kernel. So from user perspective it should be possible to
290 * manipulate with its' (VF) receive modes. However from PF
291 * driver perspective we need to keep track of filter configurations
292 * for different VFs to prevent filter values dupes
294 for (i = 0; i < lmac->dmacs_cfg; i++) {
295 if (lmac->dmacs[i].dmac == dmac) {
296 lmac->dmacs[i].vf_map |= BIT_ULL(vf_id);
301 if (!(lmac->dmacs_cfg < lmac->dmacs_count))
304 /* keep it for further tracking */
305 lmac->dmacs[lmac->dmacs_cfg].dmac = dmac;
306 lmac->dmacs[lmac->dmacs_cfg].vf_map = BIT_ULL(vf_id);
311 static int bgx_set_dmac_cam_filter_mac(struct bgx *bgx, int lmacid,
312 u64 cam_dmac, u8 idx)
314 struct lmac *lmac = NULL;
317 /* skip zero addresses as meaningless */
318 if (!cam_dmac || !bgx)
321 lmac = &bgx->lmac[lmacid];
323 /* configure DCAM filtering for designated LMAC */
324 cfg = RX_DMACX_CAM_LMACID(lmacid & LMAC_ID_MASK) |
325 RX_DMACX_CAM_EN | cam_dmac;
326 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
327 ((lmacid * lmac->dmacs_count) + idx) * sizeof(u64), cfg);
331 void bgx_set_dmac_cam_filter(int node, int bgx_idx, int lmacid,
332 u64 cam_dmac, u8 vf_id)
334 struct bgx *bgx = get_bgx(node, bgx_idx);
335 struct lmac *lmac = NULL;
340 lmac = &bgx->lmac[lmacid];
343 cam_dmac = ether_addr_to_u64(lmac->mac);
345 /* since we might have several VFs attached to particular LMAC
346 * and kernel could call mcast config for each of them with the
347 * same MAC, check if requested MAC is already in filtering list and
348 * updare/prepare list of MACs to be applied later to HW filters
350 bgx_lmac_save_filter(lmac, cam_dmac, vf_id);
352 EXPORT_SYMBOL(bgx_set_dmac_cam_filter);
354 void bgx_set_xcast_mode(int node, int bgx_idx, int lmacid, u8 mode)
356 struct bgx *bgx = get_bgx(node, bgx_idx);
357 struct lmac *lmac = NULL;
364 lmac = &bgx->lmac[lmacid];
366 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL);
367 if (mode & BGX_XCAST_BCAST_ACCEPT)
370 cfg &= ~BCAST_ACCEPT;
372 /* disable all MCASTs and DMAC filtering */
373 cfg &= ~(CAM_ACCEPT | BGX_MCAST_MODE(MCAST_MODE_MASK));
375 /* check requested bits and set filtergin mode appropriately */
376 if (mode & (BGX_XCAST_MCAST_ACCEPT)) {
377 cfg |= (BGX_MCAST_MODE(MCAST_MODE_ACCEPT));
378 } else if (mode & BGX_XCAST_MCAST_FILTER) {
379 cfg |= (BGX_MCAST_MODE(MCAST_MODE_CAM_FILTER) | CAM_ACCEPT);
380 for (i = 0; i < lmac->dmacs_cfg; i++)
381 bgx_set_dmac_cam_filter_mac(bgx, lmacid,
382 lmac->dmacs[i].dmac, i);
384 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, cfg);
386 EXPORT_SYMBOL(bgx_set_xcast_mode);
388 void bgx_reset_xcast_mode(int node, int bgx_idx, int lmacid, u8 vf_id)
390 struct bgx *bgx = get_bgx(node, bgx_idx);
395 bgx_lmac_remove_filters(&bgx->lmac[lmacid], vf_id);
396 bgx_flush_dmac_cam_filter(bgx, lmacid);
397 bgx_set_xcast_mode(node, bgx_idx, lmacid,
398 (BGX_XCAST_BCAST_ACCEPT | BGX_XCAST_MCAST_ACCEPT));
400 EXPORT_SYMBOL(bgx_reset_xcast_mode);
402 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
404 struct bgx *bgx = get_bgx(node, bgx_idx);
410 lmac = &bgx->lmac[lmacid];
412 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
414 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
416 /* enable TX FIFO Underflow interrupt */
417 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1S,
420 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
422 /* Disable TX FIFO Underflow interrupt */
423 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1C,
426 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
429 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
431 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
433 /* Enables or disables timestamp insertion by BGX for Rx packets */
434 void bgx_config_timestamping(int node, int bgx_idx, int lmacid, bool enable)
436 struct bgx *bgx = get_bgx(node, bgx_idx);
443 lmac = &bgx->lmac[lmacid];
445 if (lmac->lmac_type == BGX_MODE_SGMII ||
446 lmac->lmac_type == BGX_MODE_QSGMII ||
447 lmac->lmac_type == BGX_MODE_RGMII)
448 csr_offset = BGX_GMP_GMI_RXX_FRM_CTL;
450 csr_offset = BGX_SMUX_RX_FRM_CTL;
452 cfg = bgx_reg_read(bgx, lmacid, csr_offset);
455 cfg |= BGX_PKT_RX_PTP_EN;
457 cfg &= ~BGX_PKT_RX_PTP_EN;
458 bgx_reg_write(bgx, lmacid, csr_offset, cfg);
460 EXPORT_SYMBOL(bgx_config_timestamping);
462 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
464 struct pfc *pfc = (struct pfc *)pause;
465 struct bgx *bgx = get_bgx(node, bgx_idx);
471 lmac = &bgx->lmac[lmacid];
475 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
476 pfc->fc_rx = cfg & RX_EN;
477 pfc->fc_tx = cfg & TX_EN;
480 EXPORT_SYMBOL(bgx_lmac_get_pfc);
482 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
484 struct pfc *pfc = (struct pfc *)pause;
485 struct bgx *bgx = get_bgx(node, bgx_idx);
491 lmac = &bgx->lmac[lmacid];
495 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
496 cfg &= ~(RX_EN | TX_EN);
497 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
498 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
499 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
501 EXPORT_SYMBOL(bgx_lmac_set_pfc);
503 static void bgx_sgmii_change_link_state(struct lmac *lmac)
505 struct bgx *bgx = lmac->bgx;
511 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
512 tx_en = cmr_cfg & CMR_PKT_TX_EN;
513 rx_en = cmr_cfg & CMR_PKT_RX_EN;
514 cmr_cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
515 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
517 /* Wait for BGX RX to be idle */
518 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
519 GMI_PORT_CFG_RX_IDLE, false)) {
520 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI RX not idle\n",
521 bgx->bgx_id, lmac->lmacid);
525 /* Wait for BGX TX to be idle */
526 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
527 GMI_PORT_CFG_TX_IDLE, false)) {
528 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI TX not idle\n",
529 bgx->bgx_id, lmac->lmacid);
533 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
534 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
537 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
538 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
539 port_cfg |= (lmac->last_duplex << 2);
541 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
544 switch (lmac->last_speed) {
546 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
547 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
548 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
549 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
550 misc_ctl |= 50; /* samp_pt */
551 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
552 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
555 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
556 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
557 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
558 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
559 misc_ctl |= 5; /* samp_pt */
560 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
561 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
564 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
565 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
566 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
567 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
568 misc_ctl |= 1; /* samp_pt */
569 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
570 if (lmac->last_duplex)
571 bgx_reg_write(bgx, lmac->lmacid,
572 BGX_GMP_GMI_TXX_BURST, 0);
574 bgx_reg_write(bgx, lmac->lmacid,
575 BGX_GMP_GMI_TXX_BURST, 8192);
580 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
581 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
583 /* Restore CMR config settings */
584 cmr_cfg |= (rx_en ? CMR_PKT_RX_EN : 0) | (tx_en ? CMR_PKT_TX_EN : 0);
585 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
587 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
588 xcv_setup_link(lmac->link_up, lmac->last_speed);
591 static void bgx_lmac_handler(struct net_device *netdev)
593 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
594 struct phy_device *phydev;
595 int link_changed = 0;
600 phydev = lmac->phydev;
602 if (!phydev->link && lmac->last_link)
606 (lmac->last_duplex != phydev->duplex ||
607 lmac->last_link != phydev->link ||
608 lmac->last_speed != phydev->speed)) {
612 lmac->last_link = phydev->link;
613 lmac->last_speed = phydev->speed;
614 lmac->last_duplex = phydev->duplex;
619 if (link_changed > 0)
620 lmac->link_up = true;
622 lmac->link_up = false;
625 bgx_sgmii_change_link_state(lmac);
627 bgx_xaui_check_link(lmac);
630 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
634 bgx = get_bgx(node, bgx_idx);
640 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
642 EXPORT_SYMBOL(bgx_get_rx_stats);
644 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
648 bgx = get_bgx(node, bgx_idx);
652 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
654 EXPORT_SYMBOL(bgx_get_tx_stats);
656 /* Configure BGX LMAC in internal loopback mode */
657 void bgx_lmac_internal_loopback(int node, int bgx_idx,
658 int lmac_idx, bool enable)
664 bgx = get_bgx(node, bgx_idx);
668 lmac = &bgx->lmac[lmac_idx];
669 if (lmac->is_sgmii) {
670 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
672 cfg |= PCS_MRX_CTL_LOOPBACK1;
674 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
675 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
677 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
679 cfg |= SPU_CTL_LOOPBACK;
681 cfg &= ~SPU_CTL_LOOPBACK;
682 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
685 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
687 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
689 int lmacid = lmac->lmacid;
692 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
693 /* max packet size */
694 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
696 /* Disable frame alignment if using preamble */
697 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
699 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
702 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
705 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
706 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
707 PCS_MRX_CTL_RESET, true)) {
708 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
712 /* power down, reset autoneg, autoneg enable */
713 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
714 cfg &= ~PCS_MRX_CTL_PWR_DN;
715 cfg |= PCS_MRX_CTL_RST_AN;
717 cfg |= PCS_MRX_CTL_AN_EN;
719 /* In scenarios where PHY driver is not present or it's a
720 * non-standard PHY, FW sets AN_EN to inform Linux driver
721 * to do auto-neg and link polling or not.
723 if (cfg & PCS_MRX_CTL_AN_EN)
724 lmac->autoneg = true;
726 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
728 if (lmac->lmac_type == BGX_MODE_QSGMII) {
729 /* Disable disparity check for QSGMII */
730 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
731 cfg &= ~PCS_MISC_CTL_DISP_EN;
732 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
736 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
737 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
738 PCS_MRX_STATUS_AN_CPT, false)) {
739 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
747 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
750 int lmacid = lmac->lmacid;
753 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
754 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
755 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
760 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
762 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
764 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
765 /* Set interleaved running disparity for RXAUI */
766 if (lmac->lmac_type == BGX_MODE_RXAUI)
767 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
768 SPU_MISC_CTL_INTLV_RDISP);
770 /* Clear receive packet disable */
771 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
772 cfg &= ~SPU_MISC_CTL_RX_DIS;
773 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
775 /* clear all interrupts */
776 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
777 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
778 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
779 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
780 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
781 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
783 if (lmac->use_training) {
784 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
785 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
786 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
787 /* training enable */
788 bgx_reg_modify(bgx, lmacid,
789 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
792 /* Append FCS to each packet */
793 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
795 /* Disable forward error correction */
796 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
797 cfg &= ~SPU_FEC_CTL_FEC_EN;
798 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
800 /* Disable autoneg */
801 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
802 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
803 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
805 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
806 if (lmac->lmac_type == BGX_MODE_10G_KR)
808 else if (lmac->lmac_type == BGX_MODE_40G_KR)
811 cfg &= ~((1 << 23) | (1 << 24));
812 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
813 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
815 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
816 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
817 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
820 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
822 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
823 cfg &= ~SPU_CTL_LOW_POWER;
824 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
826 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
827 cfg &= ~SMU_TX_CTL_UNI_EN;
828 cfg |= SMU_TX_CTL_DIC_EN;
829 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
831 /* Enable receive and transmission of pause frames */
832 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
833 BCK_EN | DRP_EN | TX_EN | RX_EN));
834 /* Configure pause time and interval */
835 bgx_reg_write(bgx, lmacid,
836 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
837 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
839 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
840 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
841 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
843 /* take lmac_count into account */
844 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
845 /* max packet size */
846 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
851 static int bgx_xaui_check_link(struct lmac *lmac)
853 struct bgx *bgx = lmac->bgx;
854 int lmacid = lmac->lmacid;
855 int lmac_type = lmac->lmac_type;
858 if (lmac->use_training) {
859 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
860 if (!(cfg & (1ull << 13))) {
861 cfg = (1ull << 13) | (1ull << 14);
862 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
863 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
865 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
870 /* wait for PCS to come out of reset */
871 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
872 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
876 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
877 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
878 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
879 SPU_BR_STATUS_BLK_LOCK, false)) {
880 dev_err(&bgx->pdev->dev,
881 "SPU_BR_STATUS_BLK_LOCK not completed\n");
885 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
886 SPU_BX_STATUS_RX_ALIGN, false)) {
887 dev_err(&bgx->pdev->dev,
888 "SPU_BX_STATUS_RX_ALIGN not completed\n");
893 /* Clear rcvflt bit (latching high) and read it back */
894 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
895 bgx_reg_modify(bgx, lmacid,
896 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
897 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
898 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
899 if (lmac->use_training) {
900 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
901 if (!(cfg & (1ull << 13))) {
902 cfg = (1ull << 13) | (1ull << 14);
903 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
904 cfg = bgx_reg_read(bgx, lmacid,
905 BGX_SPUX_BR_PMD_CRTL);
907 bgx_reg_write(bgx, lmacid,
908 BGX_SPUX_BR_PMD_CRTL, cfg);
915 /* Wait for BGX RX to be idle */
916 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
917 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
921 /* Wait for BGX TX to be idle */
922 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
923 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
927 /* Check for MAC RX faults */
928 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
929 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
930 cfg &= SMU_RX_CTL_STATUS;
934 /* Rx local/remote fault seen.
935 * Do lmac reinit to see if condition recovers
937 bgx_lmac_xaui_init(bgx, lmac);
942 static void bgx_poll_for_sgmii_link(struct lmac *lmac)
944 u64 pcs_link, an_result;
947 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
948 BGX_GMP_PCS_MRX_STATUS);
950 /*Link state bit is sticky, read it again*/
951 if (!(pcs_link & PCS_MRX_STATUS_LINK))
952 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
953 BGX_GMP_PCS_MRX_STATUS);
955 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
956 PCS_MRX_STATUS_AN_CPT, false)) {
957 lmac->link_up = false;
958 lmac->last_speed = SPEED_UNKNOWN;
959 lmac->last_duplex = DUPLEX_UNKNOWN;
963 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
964 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
965 BGX_GMP_PCS_ANX_AN_RESULTS);
967 speed = (an_result >> 3) & 0x3;
968 lmac->last_duplex = (an_result >> 1) & 0x1;
971 lmac->last_speed = SPEED_10;
974 lmac->last_speed = SPEED_100;
977 lmac->last_speed = SPEED_1000;
980 lmac->link_up = false;
981 lmac->last_speed = SPEED_UNKNOWN;
982 lmac->last_duplex = DUPLEX_UNKNOWN;
988 if (lmac->last_link != lmac->link_up) {
990 bgx_sgmii_change_link_state(lmac);
991 lmac->last_link = lmac->link_up;
994 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
997 static void bgx_poll_for_link(struct work_struct *work)
1000 u64 spu_link, smu_link;
1002 lmac = container_of(work, struct lmac, dwork.work);
1003 if (lmac->is_sgmii) {
1004 bgx_poll_for_sgmii_link(lmac);
1008 /* Receive link is latching low. Force it high and verify it */
1009 bgx_reg_modify(lmac->bgx, lmac->lmacid,
1010 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
1011 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
1012 SPU_STATUS1_RCV_LNK, false);
1014 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
1015 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
1017 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
1018 !(smu_link & SMU_RX_CTL_STATUS)) {
1019 lmac->link_up = true;
1020 if (lmac->lmac_type == BGX_MODE_XLAUI)
1021 lmac->last_speed = SPEED_40000;
1023 lmac->last_speed = SPEED_10000;
1024 lmac->last_duplex = DUPLEX_FULL;
1026 lmac->link_up = false;
1027 lmac->last_speed = SPEED_UNKNOWN;
1028 lmac->last_duplex = DUPLEX_UNKNOWN;
1031 if (lmac->last_link != lmac->link_up) {
1032 if (lmac->link_up) {
1033 if (bgx_xaui_check_link(lmac)) {
1034 /* Errors, clear link_up state */
1035 lmac->link_up = false;
1036 lmac->last_speed = SPEED_UNKNOWN;
1037 lmac->last_duplex = DUPLEX_UNKNOWN;
1040 lmac->last_link = lmac->link_up;
1043 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
1046 static int phy_interface_mode(u8 lmac_type)
1048 if (lmac_type == BGX_MODE_QSGMII)
1049 return PHY_INTERFACE_MODE_QSGMII;
1050 if (lmac_type == BGX_MODE_RGMII)
1051 return PHY_INTERFACE_MODE_RGMII_RXID;
1053 return PHY_INTERFACE_MODE_SGMII;
1056 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
1061 lmac = &bgx->lmac[lmacid];
1064 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
1065 (lmac->lmac_type == BGX_MODE_QSGMII) ||
1066 (lmac->lmac_type == BGX_MODE_RGMII)) {
1067 lmac->is_sgmii = true;
1068 if (bgx_lmac_sgmii_init(bgx, lmac))
1071 lmac->is_sgmii = false;
1072 if (bgx_lmac_xaui_init(bgx, lmac))
1076 if (lmac->is_sgmii) {
1077 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
1078 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1079 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
1080 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
1082 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
1083 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1084 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
1085 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
1088 /* actual number of filters available to exact LMAC */
1089 lmac->dmacs_count = (RX_DMAC_COUNT / bgx->lmac_count);
1090 lmac->dmacs = kcalloc(lmac->dmacs_count, sizeof(*lmac->dmacs),
1096 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
1098 /* Restore default cfg, incase low level firmware changed it */
1099 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
1101 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1102 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1103 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1104 (lmac->lmac_type != BGX_MODE_10G_KR)) {
1105 if (!lmac->phydev) {
1106 if (lmac->autoneg) {
1107 bgx_reg_write(bgx, lmacid,
1108 BGX_GMP_PCS_LINKX_TIMER,
1109 PCS_LINKX_TIMER_COUNT);
1112 /* Default to below link speed and duplex */
1113 lmac->link_up = true;
1114 lmac->last_speed = SPEED_1000;
1115 lmac->last_duplex = DUPLEX_FULL;
1116 bgx_sgmii_change_link_state(lmac);
1120 lmac->phydev->dev_flags = 0;
1122 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
1124 phy_interface_mode(lmac->lmac_type)))
1127 phy_start(lmac->phydev);
1132 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
1134 if (!lmac->check_link)
1136 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
1137 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
1142 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
1147 lmac = &bgx->lmac[lmacid];
1148 if (lmac->check_link) {
1149 /* Destroy work queue */
1150 cancel_delayed_work_sync(&lmac->dwork);
1151 destroy_workqueue(lmac->check_link);
1154 /* Disable packet reception */
1155 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1156 cfg &= ~CMR_PKT_RX_EN;
1157 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1159 /* Give chance for Rx/Tx FIFO to get drained */
1160 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
1161 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
1163 /* Disable packet transmission */
1164 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1165 cfg &= ~CMR_PKT_TX_EN;
1166 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1168 /* Disable serdes lanes */
1169 if (!lmac->is_sgmii)
1170 bgx_reg_modify(bgx, lmacid,
1171 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
1173 bgx_reg_modify(bgx, lmacid,
1174 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
1177 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1179 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1181 bgx_flush_dmac_cam_filter(bgx, lmacid);
1184 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1185 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1186 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1187 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
1188 phy_disconnect(lmac->phydev);
1190 lmac->phydev = NULL;
1193 static void bgx_init_hw(struct bgx *bgx)
1198 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
1199 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
1200 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
1202 /* Set lmac type and lane2serdes mapping */
1203 for (i = 0; i < bgx->lmac_count; i++) {
1204 lmac = &bgx->lmac[i];
1205 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
1206 (lmac->lmac_type << 8) | lmac->lane_to_sds);
1207 bgx->lmac[i].lmacid_bd = lmac_count;
1211 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
1212 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
1214 /* Set the backpressure AND mask */
1215 for (i = 0; i < bgx->lmac_count; i++)
1216 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
1217 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
1218 (i * MAX_BGX_CHANS_PER_LMAC));
1220 /* Disable all MAC filtering */
1221 for (i = 0; i < RX_DMAC_COUNT; i++)
1222 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
1224 /* Disable MAC steering (NCSI traffic) */
1225 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
1226 bgx_reg_write(bgx, 0, BGX_CMR_RX_STEERING + (i * 8), 0x00);
1229 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
1231 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
1234 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
1236 struct device *dev = &bgx->pdev->dev;
1240 if (!bgx->is_dlm && lmacid)
1243 lmac = &bgx->lmac[lmacid];
1245 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
1247 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid);
1249 switch (lmac->lmac_type) {
1250 case BGX_MODE_SGMII:
1251 dev_info(dev, "%s: SGMII\n", (char *)str);
1254 dev_info(dev, "%s: XAUI\n", (char *)str);
1256 case BGX_MODE_RXAUI:
1257 dev_info(dev, "%s: RXAUI\n", (char *)str);
1260 if (!lmac->use_training)
1261 dev_info(dev, "%s: XFI\n", (char *)str);
1263 dev_info(dev, "%s: 10G_KR\n", (char *)str);
1265 case BGX_MODE_XLAUI:
1266 if (!lmac->use_training)
1267 dev_info(dev, "%s: XLAUI\n", (char *)str);
1269 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
1271 case BGX_MODE_QSGMII:
1272 dev_info(dev, "%s: QSGMII\n", (char *)str);
1274 case BGX_MODE_RGMII:
1275 dev_info(dev, "%s: RGMII\n", (char *)str);
1277 case BGX_MODE_INVALID:
1283 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
1285 switch (lmac->lmac_type) {
1286 case BGX_MODE_SGMII:
1288 lmac->lane_to_sds = lmac->lmacid;
1291 case BGX_MODE_XLAUI:
1292 case BGX_MODE_RGMII:
1293 lmac->lane_to_sds = 0xE4;
1295 case BGX_MODE_RXAUI:
1296 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
1298 case BGX_MODE_QSGMII:
1299 /* There is no way to determine if DLM0/2 is QSGMII or
1300 * DLM1/3 is configured to QSGMII as bootloader will
1301 * configure all LMACs, so take whatever is configured
1302 * by low level firmware.
1304 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1307 lmac->lane_to_sds = 0;
1312 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1314 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1315 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1316 lmac->use_training = false;
1320 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1321 SPU_PMD_CRTL_TRAIN_EN;
1324 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1331 lmac = &bgx->lmac[idx];
1333 if (!bgx->is_dlm || bgx->is_rgx) {
1334 /* Read LMAC0 type to figure out QLM mode
1335 * This is configured by low level firmware
1337 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1338 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
1340 lmac->lmac_type = BGX_MODE_RGMII;
1341 lmac_set_training(bgx, lmac, 0);
1342 lmac_set_lane2sds(bgx, lmac);
1346 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1347 * are possible and vary across boards. Also Kernel doesn't have
1348 * any way to identify board type/info and since firmware does,
1349 * just take lmac type and serdes lane config as is.
1351 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1352 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1353 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1354 /* Check if config is reset value */
1355 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1356 lmac->lmac_type = BGX_MODE_INVALID;
1358 lmac->lmac_type = lmac_type;
1359 lmac->lane_to_sds = lane_to_sds;
1360 lmac_set_training(bgx, lmac, lmac->lmacid);
1363 static void bgx_get_qlm_mode(struct bgx *bgx)
1368 /* Init all LMAC's type to invalid */
1369 for (idx = 0; idx < bgx->max_lmac; idx++) {
1370 lmac = &bgx->lmac[idx];
1372 lmac->lmac_type = BGX_MODE_INVALID;
1373 lmac->use_training = false;
1376 /* It is assumed that low level firmware sets this value */
1377 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1378 if (bgx->lmac_count > bgx->max_lmac)
1379 bgx->lmac_count = bgx->max_lmac;
1381 for (idx = 0; idx < bgx->lmac_count; idx++) {
1382 bgx_set_lmac_config(bgx, idx);
1383 bgx_print_qlm_mode(bgx, idx);
1389 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1395 addr = fwnode_get_mac_address(acpi_fwnode_handle(adev), mac, ETH_ALEN);
1397 dev_err(dev, "MAC address invalid: %pM\n", mac);
1401 dev_info(dev, "MAC address set to: %pM\n", mac);
1403 ether_addr_copy(dst, mac);
1407 /* Currently only sets the MAC address. */
1408 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1409 u32 lvl, void *context, void **rv)
1411 struct bgx *bgx = context;
1412 struct device *dev = &bgx->pdev->dev;
1413 struct acpi_device *adev;
1415 if (acpi_bus_get_device(handle, &adev))
1418 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
1420 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
1422 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1423 bgx->acpi_lmac_idx++; /* move to next LMAC */
1428 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1429 void *context, void **ret_val)
1431 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1432 struct bgx *bgx = context;
1435 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1436 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1437 pr_warn("Invalid link device\n");
1441 if (strncmp(string.pointer, bgx_sel, 4))
1444 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1445 bgx_acpi_register_phy, NULL, bgx, NULL);
1447 kfree(string.pointer);
1448 return AE_CTRL_TERMINATE;
1451 static int bgx_init_acpi_phy(struct bgx *bgx)
1453 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1459 static int bgx_init_acpi_phy(struct bgx *bgx)
1464 #endif /* CONFIG_ACPI */
1466 #if IS_ENABLED(CONFIG_OF_MDIO)
1468 static int bgx_init_of_phy(struct bgx *bgx)
1470 struct fwnode_handle *fwn;
1471 struct device_node *node = NULL;
1474 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1475 struct phy_device *pd;
1476 struct device_node *phy_np;
1478 /* Should always be an OF node. But if it is not, we
1479 * cannot handle it, so exit the loop.
1481 node = to_of_node(fwn);
1485 of_get_mac_address(node, bgx->lmac[lmac].mac);
1487 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1488 bgx->lmac[lmac].lmacid = lmac;
1490 phy_np = of_parse_phandle(node, "phy-handle", 0);
1491 /* If there is no phy or defective firmware presents
1492 * this cortina phy, for which there is no driver
1493 * support, ignore it.
1496 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1497 /* Wait until the phy drivers are available */
1498 pd = of_phy_find_device(phy_np);
1501 bgx->lmac[lmac].phydev = pd;
1505 if (lmac == bgx->max_lmac) {
1513 /* We are bailing out, try not to leak device reference counts
1514 * for phy devices we may have already found.
1517 if (bgx->lmac[lmac].phydev) {
1518 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1519 bgx->lmac[lmac].phydev = NULL;
1524 return -EPROBE_DEFER;
1529 static int bgx_init_of_phy(struct bgx *bgx)
1534 #endif /* CONFIG_OF_MDIO */
1536 static int bgx_init_phy(struct bgx *bgx)
1539 return bgx_init_acpi_phy(bgx);
1541 return bgx_init_of_phy(bgx);
1544 static irqreturn_t bgx_intr_handler(int irq, void *data)
1546 struct bgx *bgx = (struct bgx *)data;
1550 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1551 status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT);
1552 if (status & GMI_TXX_INT_UNDFLW) {
1553 pci_err(bgx->pdev, "BGX%d lmac%d UNDFLW\n",
1555 val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG);
1557 bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
1559 bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
1561 /* clear interrupts */
1562 bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status);
1568 static void bgx_register_intr(struct pci_dev *pdev)
1570 struct bgx *bgx = pci_get_drvdata(pdev);
1573 ret = pci_alloc_irq_vectors(pdev, BGX_LMAC_VEC_OFFSET,
1574 BGX_LMAC_VEC_OFFSET, PCI_IRQ_ALL_TYPES);
1576 pci_err(pdev, "Req for #%d msix vectors failed\n",
1577 BGX_LMAC_VEC_OFFSET);
1580 ret = pci_request_irq(pdev, GMPX_GMI_TX_INT, bgx_intr_handler, NULL,
1581 bgx, "BGX%d", bgx->bgx_id);
1583 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1586 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1589 struct device *dev = &pdev->dev;
1590 struct bgx *bgx = NULL;
1594 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1599 pci_set_drvdata(pdev, bgx);
1601 err = pcim_enable_device(pdev);
1603 dev_err(dev, "Failed to enable PCI device\n");
1604 pci_set_drvdata(pdev, NULL);
1608 err = pci_request_regions(pdev, DRV_NAME);
1610 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1611 goto err_disable_device;
1614 /* MAP configuration registers */
1615 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1616 if (!bgx->reg_base) {
1617 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1619 goto err_release_regions;
1622 set_max_bgx_per_node(pdev);
1624 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1625 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1626 bgx->bgx_id = (pci_resource_start(pdev,
1627 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1628 bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node;
1629 bgx->max_lmac = MAX_LMAC_PER_BGX;
1630 bgx_vnic[bgx->bgx_id] = bgx;
1634 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1635 bgx_vnic[bgx->bgx_id] = bgx;
1639 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1640 * BGX i.e BGX2 can be split across 2 DLMs.
1642 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1643 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1644 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1647 bgx_get_qlm_mode(bgx);
1649 err = bgx_init_phy(bgx);
1655 bgx_register_intr(pdev);
1657 /* Enable all LMACs */
1658 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1659 err = bgx_lmac_enable(bgx, lmac);
1661 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1664 bgx_lmac_disable(bgx, --lmac);
1672 bgx_vnic[bgx->bgx_id] = NULL;
1673 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1674 err_release_regions:
1675 pci_release_regions(pdev);
1677 pci_disable_device(pdev);
1678 pci_set_drvdata(pdev, NULL);
1682 static void bgx_remove(struct pci_dev *pdev)
1684 struct bgx *bgx = pci_get_drvdata(pdev);
1687 /* Disable all LMACs */
1688 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1689 bgx_lmac_disable(bgx, lmac);
1691 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1693 bgx_vnic[bgx->bgx_id] = NULL;
1694 pci_release_regions(pdev);
1695 pci_disable_device(pdev);
1696 pci_set_drvdata(pdev, NULL);
1699 static struct pci_driver bgx_driver = {
1701 .id_table = bgx_id_table,
1703 .remove = bgx_remove,
1706 static int __init bgx_init_module(void)
1708 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1710 return pci_register_driver(&bgx_driver);
1713 static void __exit bgx_cleanup_module(void)
1715 pci_unregister_driver(&bgx_driver);
1718 module_init(bgx_init_module);
1719 module_exit(bgx_cleanup_module);