2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/crc32.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/circ_buf.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
22 #include <linux/gpio.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/interrupt.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/macb.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
37 #include <linux/udp.h>
38 #include <linux/tcp.h>
41 #define MACB_RX_BUFFER_SIZE 128
42 #define RX_BUFFER_MULTIPLE 64 /* bytes */
44 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
45 #define MIN_RX_RING_SIZE 64
46 #define MAX_RX_RING_SIZE 8192
47 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
50 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_TX_RING_SIZE 64
52 #define MAX_TX_RING_SIZE 4096
53 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
56 /* level of occupied TX descriptors under which we wake up TX process */
57 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
59 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
60 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
63 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
66 /* Max length of transmit frame must be a multiple of 8 bytes */
67 #define MACB_TX_LEN_ALIGN 8
68 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
69 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
71 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
72 #define MACB_NETIF_LSO NETIF_F_TSO
74 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
75 #define MACB_WOL_ENABLED (0x1 << 1)
77 /* Graceful stop timeouts in us. We should allow up to
78 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
80 #define MACB_HALT_TIMEOUT 1230
82 /* DMA buffer descriptor might be different size
83 * depends on hardware configuration:
85 * 1. dma address width 32 bits:
86 * word 1: 32 bit address of Data Buffer
89 * 2. dma address width 64 bits:
90 * word 1: 32 bit address of Data Buffer
92 * word 3: upper 32 bit address of Data Buffer
95 * 3. dma address width 32 bits with hardware timestamping:
96 * word 1: 32 bit address of Data Buffer
98 * word 3: timestamp word 1
99 * word 4: timestamp word 2
101 * 4. dma address width 64 bits with hardware timestamping:
102 * word 1: 32 bit address of Data Buffer
104 * word 3: upper 32 bit address of Data Buffer
106 * word 5: timestamp word 1
107 * word 6: timestamp word 2
109 static unsigned int macb_dma_desc_get_size(struct macb *bp)
112 unsigned int desc_size;
114 switch (bp->hw_dma_cap) {
116 desc_size = sizeof(struct macb_dma_desc)
117 + sizeof(struct macb_dma_desc_64);
120 desc_size = sizeof(struct macb_dma_desc)
121 + sizeof(struct macb_dma_desc_ptp);
123 case HW_DMA_CAP_64B_PTP:
124 desc_size = sizeof(struct macb_dma_desc)
125 + sizeof(struct macb_dma_desc_64)
126 + sizeof(struct macb_dma_desc_ptp);
129 desc_size = sizeof(struct macb_dma_desc);
133 return sizeof(struct macb_dma_desc);
136 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
139 switch (bp->hw_dma_cap) {
144 case HW_DMA_CAP_64B_PTP:
154 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
155 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
157 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
158 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
163 /* Ring buffer accessors */
164 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
166 return index & (bp->tx_ring_size - 1);
169 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
172 index = macb_tx_ring_wrap(queue->bp, index);
173 index = macb_adj_dma_desc_idx(queue->bp, index);
174 return &queue->tx_ring[index];
177 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
180 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
183 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
187 offset = macb_tx_ring_wrap(queue->bp, index) *
188 macb_dma_desc_get_size(queue->bp);
190 return queue->tx_ring_dma + offset;
193 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
195 return index & (bp->rx_ring_size - 1);
198 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
200 index = macb_rx_ring_wrap(queue->bp, index);
201 index = macb_adj_dma_desc_idx(queue->bp, index);
202 return &queue->rx_ring[index];
205 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
207 return queue->rx_buffers + queue->bp->rx_buffer_size *
208 macb_rx_ring_wrap(queue->bp, index);
212 static u32 hw_readl_native(struct macb *bp, int offset)
214 return __raw_readl(bp->regs + offset);
217 static void hw_writel_native(struct macb *bp, int offset, u32 value)
219 __raw_writel(value, bp->regs + offset);
222 static u32 hw_readl(struct macb *bp, int offset)
224 return readl_relaxed(bp->regs + offset);
227 static void hw_writel(struct macb *bp, int offset, u32 value)
229 writel_relaxed(value, bp->regs + offset);
232 /* Find the CPU endianness by using the loopback bit of NCR register. When the
233 * CPU is in big endian we need to program swapped mode for management
236 static bool hw_is_native_io(void __iomem *addr)
238 u32 value = MACB_BIT(LLB);
240 __raw_writel(value, addr + MACB_NCR);
241 value = __raw_readl(addr + MACB_NCR);
243 /* Write 0 back to disable everything */
244 __raw_writel(0, addr + MACB_NCR);
246 return value == MACB_BIT(LLB);
249 static bool hw_is_gem(void __iomem *addr, bool native_io)
254 id = __raw_readl(addr + MACB_MID);
256 id = readl_relaxed(addr + MACB_MID);
258 return MACB_BFEXT(IDNUM, id) >= 0x2;
261 static void macb_set_hwaddr(struct macb *bp)
266 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
267 macb_or_gem_writel(bp, SA1B, bottom);
268 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
269 macb_or_gem_writel(bp, SA1T, top);
271 /* Clear unused address register sets */
272 macb_or_gem_writel(bp, SA2B, 0);
273 macb_or_gem_writel(bp, SA2T, 0);
274 macb_or_gem_writel(bp, SA3B, 0);
275 macb_or_gem_writel(bp, SA3T, 0);
276 macb_or_gem_writel(bp, SA4B, 0);
277 macb_or_gem_writel(bp, SA4T, 0);
280 static void macb_get_hwaddr(struct macb *bp)
282 struct macb_platform_data *pdata;
288 pdata = dev_get_platdata(&bp->pdev->dev);
290 /* Check all 4 address register for valid address */
291 for (i = 0; i < 4; i++) {
292 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
293 top = macb_or_gem_readl(bp, SA1T + i * 8);
295 if (pdata && pdata->rev_eth_addr) {
296 addr[5] = bottom & 0xff;
297 addr[4] = (bottom >> 8) & 0xff;
298 addr[3] = (bottom >> 16) & 0xff;
299 addr[2] = (bottom >> 24) & 0xff;
300 addr[1] = top & 0xff;
301 addr[0] = (top & 0xff00) >> 8;
303 addr[0] = bottom & 0xff;
304 addr[1] = (bottom >> 8) & 0xff;
305 addr[2] = (bottom >> 16) & 0xff;
306 addr[3] = (bottom >> 24) & 0xff;
307 addr[4] = top & 0xff;
308 addr[5] = (top >> 8) & 0xff;
311 if (is_valid_ether_addr(addr)) {
312 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
317 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
318 eth_hw_addr_random(bp->dev);
321 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
323 struct macb *bp = bus->priv;
326 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
327 | MACB_BF(RW, MACB_MAN_READ)
328 | MACB_BF(PHYA, mii_id)
329 | MACB_BF(REGA, regnum)
330 | MACB_BF(CODE, MACB_MAN_CODE)));
332 /* wait for end of transfer */
333 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
336 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
341 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
344 struct macb *bp = bus->priv;
346 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
347 | MACB_BF(RW, MACB_MAN_WRITE)
348 | MACB_BF(PHYA, mii_id)
349 | MACB_BF(REGA, regnum)
350 | MACB_BF(CODE, MACB_MAN_CODE)
351 | MACB_BF(DATA, value)));
353 /* wait for end of transfer */
354 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
361 * macb_set_tx_clk() - Set a clock to a new frequency
362 * @clk Pointer to the clock to change
363 * @rate New frequency in Hz
364 * @dev Pointer to the struct net_device
366 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
368 long ferr, rate, rate_rounded;
387 rate_rounded = clk_round_rate(clk, rate);
388 if (rate_rounded < 0)
391 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
394 ferr = abs(rate_rounded - rate);
395 ferr = DIV_ROUND_UP(ferr, rate / 100000);
397 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
400 if (clk_set_rate(clk, rate_rounded))
401 netdev_err(dev, "adjusting tx_clk failed.\n");
404 static void macb_handle_link_change(struct net_device *dev)
406 struct macb *bp = netdev_priv(dev);
407 struct phy_device *phydev = dev->phydev;
409 int status_change = 0;
411 spin_lock_irqsave(&bp->lock, flags);
414 if ((bp->speed != phydev->speed) ||
415 (bp->duplex != phydev->duplex)) {
418 reg = macb_readl(bp, NCFGR);
419 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
421 reg &= ~GEM_BIT(GBE);
425 if (phydev->speed == SPEED_100)
426 reg |= MACB_BIT(SPD);
427 if (phydev->speed == SPEED_1000 &&
428 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
431 macb_or_gem_writel(bp, NCFGR, reg);
433 bp->speed = phydev->speed;
434 bp->duplex = phydev->duplex;
439 if (phydev->link != bp->link) {
444 bp->link = phydev->link;
449 spin_unlock_irqrestore(&bp->lock, flags);
453 /* Update the TX clock rate if and only if the link is
454 * up and there has been a link change.
456 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
458 netif_carrier_on(dev);
459 netdev_info(dev, "link up (%d/%s)\n",
461 phydev->duplex == DUPLEX_FULL ?
464 netif_carrier_off(dev);
465 netdev_info(dev, "link down\n");
470 /* based on au1000_eth. c*/
471 static int macb_mii_probe(struct net_device *dev)
473 struct macb *bp = netdev_priv(dev);
474 struct macb_platform_data *pdata;
475 struct phy_device *phydev;
476 struct device_node *np;
479 pdata = dev_get_platdata(&bp->pdev->dev);
480 np = bp->pdev->dev.of_node;
484 if (of_phy_is_fixed_link(np)) {
485 bp->phy_node = of_node_get(np);
487 bp->phy_node = of_parse_phandle(np, "phy-handle", 0);
488 /* fallback to standard phy registration if no
489 * phy-handle was found nor any phy found during
490 * dt phy registration
492 if (!bp->phy_node && !phy_find_first(bp->mii_bus)) {
493 for (i = 0; i < PHY_MAX_ADDR; i++) {
494 struct phy_device *phydev;
496 phydev = mdiobus_scan(bp->mii_bus, i);
497 if (IS_ERR(phydev) &&
498 PTR_ERR(phydev) != -ENODEV) {
499 ret = PTR_ERR(phydev);
511 phydev = of_phy_connect(dev, bp->phy_node,
512 &macb_handle_link_change, 0,
517 phydev = phy_find_first(bp->mii_bus);
519 netdev_err(dev, "no PHY found\n");
524 if (gpio_is_valid(pdata->phy_irq_pin)) {
525 ret = devm_gpio_request(&bp->pdev->dev,
526 pdata->phy_irq_pin, "phy int");
528 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
529 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
532 phydev->irq = PHY_POLL;
536 /* attach the mac to the phy */
537 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
540 netdev_err(dev, "Could not attach to PHY\n");
545 /* mask with MAC supported features */
546 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
547 phy_set_max_speed(phydev, SPEED_1000);
549 phy_set_max_speed(phydev, SPEED_100);
551 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
552 phy_remove_link_mode(phydev,
553 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
562 static int macb_mii_init(struct macb *bp)
564 struct macb_platform_data *pdata;
565 struct device_node *np;
568 /* Enable management port */
569 macb_writel(bp, NCR, MACB_BIT(MPE));
571 bp->mii_bus = mdiobus_alloc();
577 bp->mii_bus->name = "MACB_mii_bus";
578 bp->mii_bus->read = &macb_mdio_read;
579 bp->mii_bus->write = &macb_mdio_write;
580 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
581 bp->pdev->name, bp->pdev->id);
582 bp->mii_bus->priv = bp;
583 bp->mii_bus->parent = &bp->pdev->dev;
584 pdata = dev_get_platdata(&bp->pdev->dev);
586 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
588 np = bp->pdev->dev.of_node;
589 if (np && of_phy_is_fixed_link(np)) {
590 if (of_phy_register_fixed_link(np) < 0) {
591 dev_err(&bp->pdev->dev,
592 "broken fixed-link specification %pOF\n", np);
593 goto err_out_free_mdiobus;
596 err = mdiobus_register(bp->mii_bus);
599 bp->mii_bus->phy_mask = pdata->phy_mask;
601 err = of_mdiobus_register(bp->mii_bus, np);
605 goto err_out_free_fixed_link;
607 err = macb_mii_probe(bp->dev);
609 goto err_out_unregister_bus;
613 err_out_unregister_bus:
614 mdiobus_unregister(bp->mii_bus);
615 err_out_free_fixed_link:
616 if (np && of_phy_is_fixed_link(np))
617 of_phy_deregister_fixed_link(np);
618 err_out_free_mdiobus:
619 of_node_put(bp->phy_node);
620 mdiobus_free(bp->mii_bus);
625 static void macb_update_stats(struct macb *bp)
627 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
628 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
629 int offset = MACB_PFR;
631 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
633 for (; p < end; p++, offset += 4)
634 *p += bp->macb_reg_readl(bp, offset);
637 static int macb_halt_tx(struct macb *bp)
639 unsigned long halt_time, timeout;
642 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
644 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
647 status = macb_readl(bp, TSR);
648 if (!(status & MACB_BIT(TGO)))
652 } while (time_before(halt_time, timeout));
657 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
659 if (tx_skb->mapping) {
660 if (tx_skb->mapped_as_page)
661 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
662 tx_skb->size, DMA_TO_DEVICE);
664 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
665 tx_skb->size, DMA_TO_DEVICE);
670 dev_kfree_skb_any(tx_skb->skb);
675 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
677 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
678 struct macb_dma_desc_64 *desc_64;
680 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
681 desc_64 = macb_64b_desc(bp, desc);
682 desc_64->addrh = upper_32_bits(addr);
683 /* The low bits of RX address contain the RX_USED bit, clearing
684 * of which allows packet RX. Make sure the high bits are also
685 * visible to HW at that point.
690 desc->addr = lower_32_bits(addr);
693 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
696 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
697 struct macb_dma_desc_64 *desc_64;
699 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
700 desc_64 = macb_64b_desc(bp, desc);
701 addr = ((u64)(desc_64->addrh) << 32);
704 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
708 static void macb_tx_error_task(struct work_struct *work)
710 struct macb_queue *queue = container_of(work, struct macb_queue,
712 struct macb *bp = queue->bp;
713 struct macb_tx_skb *tx_skb;
714 struct macb_dma_desc *desc;
719 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
720 (unsigned int)(queue - bp->queues),
721 queue->tx_tail, queue->tx_head);
723 /* Prevent the queue IRQ handlers from running: each of them may call
724 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
725 * As explained below, we have to halt the transmission before updating
726 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
727 * network engine about the macb/gem being halted.
729 spin_lock_irqsave(&bp->lock, flags);
731 /* Make sure nobody is trying to queue up new packets */
732 netif_tx_stop_all_queues(bp->dev);
734 /* Stop transmission now
735 * (in case we have just queued new packets)
736 * macb/gem must be halted to write TBQP register
738 if (macb_halt_tx(bp))
739 /* Just complain for now, reinitializing TX path can be good */
740 netdev_err(bp->dev, "BUG: halt tx timed out\n");
742 /* Treat frames in TX queue including the ones that caused the error.
743 * Free transmit buffers in upper layer.
745 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
748 desc = macb_tx_desc(queue, tail);
750 tx_skb = macb_tx_skb(queue, tail);
753 if (ctrl & MACB_BIT(TX_USED)) {
754 /* skb is set for the last buffer of the frame */
756 macb_tx_unmap(bp, tx_skb);
758 tx_skb = macb_tx_skb(queue, tail);
762 /* ctrl still refers to the first buffer descriptor
763 * since it's the only one written back by the hardware
765 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
766 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
767 macb_tx_ring_wrap(bp, tail),
769 bp->dev->stats.tx_packets++;
770 queue->stats.tx_packets++;
771 bp->dev->stats.tx_bytes += skb->len;
772 queue->stats.tx_bytes += skb->len;
775 /* "Buffers exhausted mid-frame" errors may only happen
776 * if the driver is buggy, so complain loudly about
777 * those. Statistics are updated by hardware.
779 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
781 "BUG: TX buffers exhausted mid-frame\n");
783 desc->ctrl = ctrl | MACB_BIT(TX_USED);
786 macb_tx_unmap(bp, tx_skb);
789 /* Set end of TX queue */
790 desc = macb_tx_desc(queue, 0);
791 macb_set_addr(bp, desc, 0);
792 desc->ctrl = MACB_BIT(TX_USED);
794 /* Make descriptor updates visible to hardware */
797 /* Reinitialize the TX desc queue */
798 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
799 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
800 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
801 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
803 /* Make TX ring reflect state of hardware */
807 /* Housework before enabling TX IRQ */
808 macb_writel(bp, TSR, macb_readl(bp, TSR));
809 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
811 /* Now we are ready to start transmission again */
812 netif_tx_start_all_queues(bp->dev);
813 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
815 spin_unlock_irqrestore(&bp->lock, flags);
818 static void macb_tx_interrupt(struct macb_queue *queue)
823 struct macb *bp = queue->bp;
824 u16 queue_index = queue - bp->queues;
826 status = macb_readl(bp, TSR);
827 macb_writel(bp, TSR, status);
829 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
830 queue_writel(queue, ISR, MACB_BIT(TCOMP));
832 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
833 (unsigned long)status);
835 head = queue->tx_head;
836 for (tail = queue->tx_tail; tail != head; tail++) {
837 struct macb_tx_skb *tx_skb;
839 struct macb_dma_desc *desc;
842 desc = macb_tx_desc(queue, tail);
844 /* Make hw descriptor updates visible to CPU */
849 /* TX_USED bit is only set by hardware on the very first buffer
850 * descriptor of the transmitted frame.
852 if (!(ctrl & MACB_BIT(TX_USED)))
855 /* Process all buffers of the current transmitted frame */
857 tx_skb = macb_tx_skb(queue, tail);
860 /* First, update TX stats if needed */
862 if (gem_ptp_do_txstamp(queue, skb, desc) == 0) {
863 /* skb now belongs to timestamp buffer
864 * and will be removed later
868 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
869 macb_tx_ring_wrap(bp, tail),
871 bp->dev->stats.tx_packets++;
872 queue->stats.tx_packets++;
873 bp->dev->stats.tx_bytes += skb->len;
874 queue->stats.tx_bytes += skb->len;
877 /* Now we can safely release resources */
878 macb_tx_unmap(bp, tx_skb);
880 /* skb is set only for the last buffer of the frame.
881 * WARNING: at this point skb has been freed by
889 queue->tx_tail = tail;
890 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
891 CIRC_CNT(queue->tx_head, queue->tx_tail,
892 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
893 netif_wake_subqueue(bp->dev, queue_index);
896 static void gem_rx_refill(struct macb_queue *queue)
901 struct macb *bp = queue->bp;
902 struct macb_dma_desc *desc;
904 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
905 bp->rx_ring_size) > 0) {
906 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
908 /* Make hw descriptor updates visible to CPU */
911 queue->rx_prepared_head++;
912 desc = macb_rx_desc(queue, entry);
914 if (!queue->rx_skbuff[entry]) {
915 /* allocate sk_buff for this free entry in ring */
916 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
917 if (unlikely(!skb)) {
919 "Unable to allocate sk_buff\n");
923 /* now fill corresponding descriptor entry */
924 paddr = dma_map_single(&bp->pdev->dev, skb->data,
927 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
932 queue->rx_skbuff[entry] = skb;
934 if (entry == bp->rx_ring_size - 1)
935 paddr |= MACB_BIT(RX_WRAP);
937 /* Setting addr clears RX_USED and allows reception,
938 * make sure ctrl is cleared first to avoid a race.
941 macb_set_addr(bp, desc, paddr);
943 /* properly align Ethernet header */
944 skb_reserve(skb, NET_IP_ALIGN);
948 desc->addr &= ~MACB_BIT(RX_USED);
952 /* Make descriptor updates visible to hardware */
955 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
956 queue, queue->rx_prepared_head, queue->rx_tail);
959 /* Mark DMA descriptors from begin up to and not including end as unused */
960 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
965 for (frag = begin; frag != end; frag++) {
966 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
968 desc->addr &= ~MACB_BIT(RX_USED);
971 /* Make descriptor updates visible to hardware */
974 /* When this happens, the hardware stats registers for
975 * whatever caused this is updated, so we don't have to record
980 static int gem_rx(struct macb_queue *queue, int budget)
982 struct macb *bp = queue->bp;
986 struct macb_dma_desc *desc;
989 while (count < budget) {
994 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
995 desc = macb_rx_desc(queue, entry);
997 /* Make hw descriptor updates visible to CPU */
1000 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1001 addr = macb_get_addr(bp, desc);
1006 /* Ensure ctrl is at least as up-to-date as rxused */
1014 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1016 "not whole frame pointed by descriptor\n");
1017 bp->dev->stats.rx_dropped++;
1018 queue->stats.rx_dropped++;
1021 skb = queue->rx_skbuff[entry];
1022 if (unlikely(!skb)) {
1024 "inconsistent Rx descriptor chain\n");
1025 bp->dev->stats.rx_dropped++;
1026 queue->stats.rx_dropped++;
1029 /* now everything is ready for receiving packet */
1030 queue->rx_skbuff[entry] = NULL;
1031 len = ctrl & bp->rx_frm_len_mask;
1033 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1036 dma_unmap_single(&bp->pdev->dev, addr,
1037 bp->rx_buffer_size, DMA_FROM_DEVICE);
1039 skb->protocol = eth_type_trans(skb, bp->dev);
1040 skb_checksum_none_assert(skb);
1041 if (bp->dev->features & NETIF_F_RXCSUM &&
1042 !(bp->dev->flags & IFF_PROMISC) &&
1043 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1044 skb->ip_summed = CHECKSUM_UNNECESSARY;
1046 bp->dev->stats.rx_packets++;
1047 queue->stats.rx_packets++;
1048 bp->dev->stats.rx_bytes += skb->len;
1049 queue->stats.rx_bytes += skb->len;
1051 gem_ptp_do_rxstamp(bp, skb, desc);
1053 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1054 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1055 skb->len, skb->csum);
1056 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1057 skb_mac_header(skb), 16, true);
1058 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1059 skb->data, 32, true);
1062 netif_receive_skb(skb);
1065 gem_rx_refill(queue);
1070 static int macb_rx_frame(struct macb_queue *queue, unsigned int first_frag,
1071 unsigned int last_frag)
1075 unsigned int offset;
1076 struct sk_buff *skb;
1077 struct macb_dma_desc *desc;
1078 struct macb *bp = queue->bp;
1080 desc = macb_rx_desc(queue, last_frag);
1081 len = desc->ctrl & bp->rx_frm_len_mask;
1083 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1084 macb_rx_ring_wrap(bp, first_frag),
1085 macb_rx_ring_wrap(bp, last_frag), len);
1087 /* The ethernet header starts NET_IP_ALIGN bytes into the
1088 * first buffer. Since the header is 14 bytes, this makes the
1089 * payload word-aligned.
1091 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1092 * the two padding bytes into the skb so that we avoid hitting
1093 * the slowpath in memcpy(), and pull them off afterwards.
1095 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1097 bp->dev->stats.rx_dropped++;
1098 for (frag = first_frag; ; frag++) {
1099 desc = macb_rx_desc(queue, frag);
1100 desc->addr &= ~MACB_BIT(RX_USED);
1101 if (frag == last_frag)
1105 /* Make descriptor updates visible to hardware */
1112 len += NET_IP_ALIGN;
1113 skb_checksum_none_assert(skb);
1116 for (frag = first_frag; ; frag++) {
1117 unsigned int frag_len = bp->rx_buffer_size;
1119 if (offset + frag_len > len) {
1120 if (unlikely(frag != last_frag)) {
1121 dev_kfree_skb_any(skb);
1124 frag_len = len - offset;
1126 skb_copy_to_linear_data_offset(skb, offset,
1127 macb_rx_buffer(queue, frag),
1129 offset += bp->rx_buffer_size;
1130 desc = macb_rx_desc(queue, frag);
1131 desc->addr &= ~MACB_BIT(RX_USED);
1133 if (frag == last_frag)
1137 /* Make descriptor updates visible to hardware */
1140 __skb_pull(skb, NET_IP_ALIGN);
1141 skb->protocol = eth_type_trans(skb, bp->dev);
1143 bp->dev->stats.rx_packets++;
1144 bp->dev->stats.rx_bytes += skb->len;
1145 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1146 skb->len, skb->csum);
1147 netif_receive_skb(skb);
1152 static inline void macb_init_rx_ring(struct macb_queue *queue)
1154 struct macb *bp = queue->bp;
1156 struct macb_dma_desc *desc = NULL;
1159 addr = queue->rx_buffers_dma;
1160 for (i = 0; i < bp->rx_ring_size; i++) {
1161 desc = macb_rx_desc(queue, i);
1162 macb_set_addr(bp, desc, addr);
1164 addr += bp->rx_buffer_size;
1166 desc->addr |= MACB_BIT(RX_WRAP);
1170 static int macb_rx(struct macb_queue *queue, int budget)
1172 struct macb *bp = queue->bp;
1173 bool reset_rx_queue = false;
1176 int first_frag = -1;
1178 for (tail = queue->rx_tail; budget > 0; tail++) {
1179 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1182 /* Make hw descriptor updates visible to CPU */
1185 if (!(desc->addr & MACB_BIT(RX_USED)))
1188 /* Ensure ctrl is at least as up-to-date as addr */
1193 if (ctrl & MACB_BIT(RX_SOF)) {
1194 if (first_frag != -1)
1195 discard_partial_frame(queue, first_frag, tail);
1199 if (ctrl & MACB_BIT(RX_EOF)) {
1202 if (unlikely(first_frag == -1)) {
1203 reset_rx_queue = true;
1207 dropped = macb_rx_frame(queue, first_frag, tail);
1209 if (unlikely(dropped < 0)) {
1210 reset_rx_queue = true;
1220 if (unlikely(reset_rx_queue)) {
1221 unsigned long flags;
1224 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1226 spin_lock_irqsave(&bp->lock, flags);
1228 ctrl = macb_readl(bp, NCR);
1229 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1231 macb_init_rx_ring(queue);
1232 queue_writel(queue, RBQP, queue->rx_ring_dma);
1234 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1236 spin_unlock_irqrestore(&bp->lock, flags);
1240 if (first_frag != -1)
1241 queue->rx_tail = first_frag;
1243 queue->rx_tail = tail;
1248 static int macb_poll(struct napi_struct *napi, int budget)
1250 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1251 struct macb *bp = queue->bp;
1255 status = macb_readl(bp, RSR);
1256 macb_writel(bp, RSR, status);
1258 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1259 (unsigned long)status, budget);
1261 work_done = bp->macbgem_ops.mog_rx(queue, budget);
1262 if (work_done < budget) {
1263 napi_complete_done(napi, work_done);
1265 /* Packets received while interrupts were disabled */
1266 status = macb_readl(bp, RSR);
1268 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1269 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1270 napi_reschedule(napi);
1272 queue_writel(queue, IER, bp->rx_intr_mask);
1276 /* TODO: Handle errors */
1281 static void macb_hresp_error_task(unsigned long data)
1283 struct macb *bp = (struct macb *)data;
1284 struct net_device *dev = bp->dev;
1285 struct macb_queue *queue = bp->queues;
1289 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1290 queue_writel(queue, IDR, bp->rx_intr_mask |
1294 ctrl = macb_readl(bp, NCR);
1295 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1296 macb_writel(bp, NCR, ctrl);
1298 netif_tx_stop_all_queues(dev);
1299 netif_carrier_off(dev);
1301 bp->macbgem_ops.mog_init_rings(bp);
1303 /* Initialize TX and RX buffers */
1304 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1305 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
1306 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1307 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1308 queue_writel(queue, RBQPH,
1309 upper_32_bits(queue->rx_ring_dma));
1311 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1312 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1313 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1314 queue_writel(queue, TBQPH,
1315 upper_32_bits(queue->tx_ring_dma));
1318 /* Enable interrupts */
1319 queue_writel(queue, IER,
1325 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1326 macb_writel(bp, NCR, ctrl);
1328 netif_carrier_on(dev);
1329 netif_tx_start_all_queues(dev);
1332 static void macb_tx_restart(struct macb_queue *queue)
1334 unsigned int head = queue->tx_head;
1335 unsigned int tail = queue->tx_tail;
1336 struct macb *bp = queue->bp;
1338 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1339 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1344 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1347 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1349 struct macb_queue *queue = dev_id;
1350 struct macb *bp = queue->bp;
1351 struct net_device *dev = bp->dev;
1354 status = queue_readl(queue, ISR);
1356 if (unlikely(!status))
1359 spin_lock(&bp->lock);
1362 /* close possible race with dev_close */
1363 if (unlikely(!netif_running(dev))) {
1364 queue_writel(queue, IDR, -1);
1365 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1366 queue_writel(queue, ISR, -1);
1370 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1371 (unsigned int)(queue - bp->queues),
1372 (unsigned long)status);
1374 if (status & bp->rx_intr_mask) {
1375 /* There's no point taking any more interrupts
1376 * until we have processed the buffers. The
1377 * scheduling call may fail if the poll routine
1378 * is already scheduled, so disable interrupts
1381 queue_writel(queue, IDR, bp->rx_intr_mask);
1382 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1383 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1385 if (napi_schedule_prep(&queue->napi)) {
1386 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1387 __napi_schedule(&queue->napi);
1391 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1392 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1393 schedule_work(&queue->tx_error_task);
1395 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1396 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1401 if (status & MACB_BIT(TCOMP))
1402 macb_tx_interrupt(queue);
1404 if (status & MACB_BIT(TXUBR))
1405 macb_tx_restart(queue);
1407 /* Link change detection isn't possible with RMII, so we'll
1408 * add that if/when we get our hands on a full-blown MII PHY.
1411 /* There is a hardware issue under heavy load where DMA can
1412 * stop, this causes endless "used buffer descriptor read"
1413 * interrupts but it can be cleared by re-enabling RX. See
1414 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1415 * section 16.7.4 for details. RXUBR is only enabled for
1416 * these two versions.
1418 if (status & MACB_BIT(RXUBR)) {
1419 ctrl = macb_readl(bp, NCR);
1420 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1422 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1424 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1425 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1428 if (status & MACB_BIT(ISR_ROVR)) {
1429 /* We missed at least one packet */
1430 if (macb_is_gem(bp))
1431 bp->hw_stats.gem.rx_overruns++;
1433 bp->hw_stats.macb.rx_overruns++;
1435 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1436 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1439 if (status & MACB_BIT(HRESP)) {
1440 tasklet_schedule(&bp->hresp_err_tasklet);
1441 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1443 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1444 queue_writel(queue, ISR, MACB_BIT(HRESP));
1446 status = queue_readl(queue, ISR);
1449 spin_unlock(&bp->lock);
1454 #ifdef CONFIG_NET_POLL_CONTROLLER
1455 /* Polling receive - used by netconsole and other diagnostic tools
1456 * to allow network i/o with interrupts disabled.
1458 static void macb_poll_controller(struct net_device *dev)
1460 struct macb *bp = netdev_priv(dev);
1461 struct macb_queue *queue;
1462 unsigned long flags;
1465 local_irq_save(flags);
1466 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1467 macb_interrupt(dev->irq, queue);
1468 local_irq_restore(flags);
1472 static unsigned int macb_tx_map(struct macb *bp,
1473 struct macb_queue *queue,
1474 struct sk_buff *skb,
1475 unsigned int hdrlen)
1478 unsigned int len, entry, i, tx_head = queue->tx_head;
1479 struct macb_tx_skb *tx_skb = NULL;
1480 struct macb_dma_desc *desc;
1481 unsigned int offset, size, count = 0;
1482 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1483 unsigned int eof = 1, mss_mfs = 0;
1484 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1487 if (skb_shinfo(skb)->gso_size != 0) {
1488 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1490 lso_ctrl = MACB_LSO_UFO_ENABLE;
1493 lso_ctrl = MACB_LSO_TSO_ENABLE;
1496 /* First, map non-paged data */
1497 len = skb_headlen(skb);
1499 /* first buffer length */
1504 entry = macb_tx_ring_wrap(bp, tx_head);
1505 tx_skb = &queue->tx_skb[entry];
1507 mapping = dma_map_single(&bp->pdev->dev,
1509 size, DMA_TO_DEVICE);
1510 if (dma_mapping_error(&bp->pdev->dev, mapping))
1513 /* Save info to properly release resources */
1515 tx_skb->mapping = mapping;
1516 tx_skb->size = size;
1517 tx_skb->mapped_as_page = false;
1524 size = min(len, bp->max_tx_length);
1527 /* Then, map paged data from fragments */
1528 for (f = 0; f < nr_frags; f++) {
1529 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1531 len = skb_frag_size(frag);
1534 size = min(len, bp->max_tx_length);
1535 entry = macb_tx_ring_wrap(bp, tx_head);
1536 tx_skb = &queue->tx_skb[entry];
1538 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1539 offset, size, DMA_TO_DEVICE);
1540 if (dma_mapping_error(&bp->pdev->dev, mapping))
1543 /* Save info to properly release resources */
1545 tx_skb->mapping = mapping;
1546 tx_skb->size = size;
1547 tx_skb->mapped_as_page = true;
1556 /* Should never happen */
1557 if (unlikely(!tx_skb)) {
1558 netdev_err(bp->dev, "BUG! empty skb!\n");
1562 /* This is the last buffer of the frame: save socket buffer */
1565 /* Update TX ring: update buffer descriptors in reverse order
1566 * to avoid race condition
1569 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1570 * to set the end of TX queue
1573 entry = macb_tx_ring_wrap(bp, i);
1574 ctrl = MACB_BIT(TX_USED);
1575 desc = macb_tx_desc(queue, entry);
1579 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1580 /* include header and FCS in value given to h/w */
1581 mss_mfs = skb_shinfo(skb)->gso_size +
1582 skb_transport_offset(skb) +
1585 mss_mfs = skb_shinfo(skb)->gso_size;
1586 /* TCP Sequence Number Source Select
1587 * can be set only for TSO
1595 entry = macb_tx_ring_wrap(bp, i);
1596 tx_skb = &queue->tx_skb[entry];
1597 desc = macb_tx_desc(queue, entry);
1599 ctrl = (u32)tx_skb->size;
1601 ctrl |= MACB_BIT(TX_LAST);
1604 if (unlikely(entry == (bp->tx_ring_size - 1)))
1605 ctrl |= MACB_BIT(TX_WRAP);
1607 /* First descriptor is header descriptor */
1608 if (i == queue->tx_head) {
1609 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1610 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1611 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1612 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1613 ctrl |= MACB_BIT(TX_NOCRC);
1615 /* Only set MSS/MFS on payload descriptors
1616 * (second or later descriptor)
1618 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1620 /* Set TX buffer descriptor */
1621 macb_set_addr(bp, desc, tx_skb->mapping);
1622 /* desc->addr must be visible to hardware before clearing
1623 * 'TX_USED' bit in desc->ctrl.
1627 } while (i != queue->tx_head);
1629 queue->tx_head = tx_head;
1634 netdev_err(bp->dev, "TX DMA map failed\n");
1636 for (i = queue->tx_head; i != tx_head; i++) {
1637 tx_skb = macb_tx_skb(queue, i);
1639 macb_tx_unmap(bp, tx_skb);
1645 static netdev_features_t macb_features_check(struct sk_buff *skb,
1646 struct net_device *dev,
1647 netdev_features_t features)
1649 unsigned int nr_frags, f;
1650 unsigned int hdrlen;
1652 /* Validate LSO compatibility */
1654 /* there is only one buffer */
1655 if (!skb_is_nonlinear(skb))
1658 /* length of header */
1659 hdrlen = skb_transport_offset(skb);
1660 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1661 hdrlen += tcp_hdrlen(skb);
1664 * When software supplies two or more payload buffers all payload buffers
1665 * apart from the last must be a multiple of 8 bytes in size.
1667 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1668 return features & ~MACB_NETIF_LSO;
1670 nr_frags = skb_shinfo(skb)->nr_frags;
1671 /* No need to check last fragment */
1673 for (f = 0; f < nr_frags; f++) {
1674 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1676 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1677 return features & ~MACB_NETIF_LSO;
1682 static inline int macb_clear_csum(struct sk_buff *skb)
1684 /* no change for packets without checksum offloading */
1685 if (skb->ip_summed != CHECKSUM_PARTIAL)
1688 /* make sure we can modify the header */
1689 if (unlikely(skb_cow_head(skb, 0)))
1692 /* initialize checksum field
1693 * This is required - at least for Zynq, which otherwise calculates
1694 * wrong UDP header checksums for UDP packets with UDP data len <=2
1696 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1700 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1702 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1703 int padlen = ETH_ZLEN - (*skb)->len;
1704 int headroom = skb_headroom(*skb);
1705 int tailroom = skb_tailroom(*skb);
1706 struct sk_buff *nskb;
1709 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1710 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1711 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1715 /* FCS could be appeded to tailroom. */
1716 if (tailroom >= ETH_FCS_LEN)
1718 /* FCS could be appeded by moving data to headroom. */
1719 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1721 /* No room for FCS, need to reallocate skb. */
1723 padlen = ETH_FCS_LEN;
1725 /* Add room for FCS. */
1726 padlen += ETH_FCS_LEN;
1729 if (!cloned && headroom + tailroom >= padlen) {
1730 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1731 skb_set_tail_pointer(*skb, (*skb)->len);
1733 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1737 dev_kfree_skb_any(*skb);
1741 if (padlen > ETH_FCS_LEN)
1742 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1745 /* set FCS to packet */
1746 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1749 skb_put_u8(*skb, fcs & 0xff);
1750 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1751 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1752 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1757 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1759 u16 queue_index = skb_get_queue_mapping(skb);
1760 struct macb *bp = netdev_priv(dev);
1761 struct macb_queue *queue = &bp->queues[queue_index];
1762 unsigned long flags;
1763 unsigned int desc_cnt, nr_frags, frag_size, f;
1764 unsigned int hdrlen;
1765 bool is_lso, is_udp = 0;
1766 netdev_tx_t ret = NETDEV_TX_OK;
1768 if (macb_clear_csum(skb)) {
1769 dev_kfree_skb_any(skb);
1773 if (macb_pad_and_fcs(&skb, dev)) {
1774 dev_kfree_skb_any(skb);
1778 is_lso = (skb_shinfo(skb)->gso_size != 0);
1781 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1783 /* length of headers */
1785 /* only queue eth + ip headers separately for UDP */
1786 hdrlen = skb_transport_offset(skb);
1788 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1789 if (skb_headlen(skb) < hdrlen) {
1790 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1791 /* if this is required, would need to copy to single buffer */
1792 return NETDEV_TX_BUSY;
1795 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1797 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1798 netdev_vdbg(bp->dev,
1799 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1800 queue_index, skb->len, skb->head, skb->data,
1801 skb_tail_pointer(skb), skb_end_pointer(skb));
1802 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1803 skb->data, 16, true);
1806 /* Count how many TX buffer descriptors are needed to send this
1807 * socket buffer: skb fragments of jumbo frames may need to be
1808 * split into many buffer descriptors.
1810 if (is_lso && (skb_headlen(skb) > hdrlen))
1811 /* extra header descriptor if also payload in first buffer */
1812 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1814 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1815 nr_frags = skb_shinfo(skb)->nr_frags;
1816 for (f = 0; f < nr_frags; f++) {
1817 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1818 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1821 spin_lock_irqsave(&bp->lock, flags);
1823 /* This is a hard error, log it. */
1824 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1825 bp->tx_ring_size) < desc_cnt) {
1826 netif_stop_subqueue(dev, queue_index);
1827 spin_unlock_irqrestore(&bp->lock, flags);
1828 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1829 queue->tx_head, queue->tx_tail);
1830 return NETDEV_TX_BUSY;
1833 /* Map socket buffer for DMA transfer */
1834 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1835 dev_kfree_skb_any(skb);
1839 /* Make newly initialized descriptor visible to hardware */
1841 skb_tx_timestamp(skb);
1843 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1845 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1846 netif_stop_subqueue(dev, queue_index);
1849 spin_unlock_irqrestore(&bp->lock, flags);
1854 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1856 if (!macb_is_gem(bp)) {
1857 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1859 bp->rx_buffer_size = size;
1861 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1863 "RX buffer must be multiple of %d bytes, expanding\n",
1864 RX_BUFFER_MULTIPLE);
1865 bp->rx_buffer_size =
1866 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1870 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1871 bp->dev->mtu, bp->rx_buffer_size);
1874 static void gem_free_rx_buffers(struct macb *bp)
1876 struct sk_buff *skb;
1877 struct macb_dma_desc *desc;
1878 struct macb_queue *queue;
1883 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1884 if (!queue->rx_skbuff)
1887 for (i = 0; i < bp->rx_ring_size; i++) {
1888 skb = queue->rx_skbuff[i];
1893 desc = macb_rx_desc(queue, i);
1894 addr = macb_get_addr(bp, desc);
1896 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1898 dev_kfree_skb_any(skb);
1902 kfree(queue->rx_skbuff);
1903 queue->rx_skbuff = NULL;
1907 static void macb_free_rx_buffers(struct macb *bp)
1909 struct macb_queue *queue = &bp->queues[0];
1911 if (queue->rx_buffers) {
1912 dma_free_coherent(&bp->pdev->dev,
1913 bp->rx_ring_size * bp->rx_buffer_size,
1914 queue->rx_buffers, queue->rx_buffers_dma);
1915 queue->rx_buffers = NULL;
1919 static void macb_free_consistent(struct macb *bp)
1921 struct macb_queue *queue;
1925 bp->macbgem_ops.mog_free_rx_buffers(bp);
1927 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1928 kfree(queue->tx_skb);
1929 queue->tx_skb = NULL;
1930 if (queue->tx_ring) {
1931 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1932 dma_free_coherent(&bp->pdev->dev, size,
1933 queue->tx_ring, queue->tx_ring_dma);
1934 queue->tx_ring = NULL;
1936 if (queue->rx_ring) {
1937 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
1938 dma_free_coherent(&bp->pdev->dev, size,
1939 queue->rx_ring, queue->rx_ring_dma);
1940 queue->rx_ring = NULL;
1945 static int gem_alloc_rx_buffers(struct macb *bp)
1947 struct macb_queue *queue;
1951 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1952 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1953 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
1954 if (!queue->rx_skbuff)
1958 "Allocated %d RX struct sk_buff entries at %p\n",
1959 bp->rx_ring_size, queue->rx_skbuff);
1964 static int macb_alloc_rx_buffers(struct macb *bp)
1966 struct macb_queue *queue = &bp->queues[0];
1969 size = bp->rx_ring_size * bp->rx_buffer_size;
1970 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1971 &queue->rx_buffers_dma, GFP_KERNEL);
1972 if (!queue->rx_buffers)
1976 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1977 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
1981 static int macb_alloc_consistent(struct macb *bp)
1983 struct macb_queue *queue;
1987 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1988 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1989 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1990 &queue->tx_ring_dma,
1992 if (!queue->tx_ring)
1995 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1996 q, size, (unsigned long)queue->tx_ring_dma,
1999 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2000 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2004 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2005 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2006 &queue->rx_ring_dma, GFP_KERNEL);
2007 if (!queue->rx_ring)
2010 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2011 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2013 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2019 macb_free_consistent(bp);
2023 static void gem_init_rings(struct macb *bp)
2025 struct macb_queue *queue;
2026 struct macb_dma_desc *desc = NULL;
2030 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2031 for (i = 0; i < bp->tx_ring_size; i++) {
2032 desc = macb_tx_desc(queue, i);
2033 macb_set_addr(bp, desc, 0);
2034 desc->ctrl = MACB_BIT(TX_USED);
2036 desc->ctrl |= MACB_BIT(TX_WRAP);
2041 queue->rx_prepared_head = 0;
2043 gem_rx_refill(queue);
2048 static void macb_init_rings(struct macb *bp)
2051 struct macb_dma_desc *desc = NULL;
2053 macb_init_rx_ring(&bp->queues[0]);
2055 for (i = 0; i < bp->tx_ring_size; i++) {
2056 desc = macb_tx_desc(&bp->queues[0], i);
2057 macb_set_addr(bp, desc, 0);
2058 desc->ctrl = MACB_BIT(TX_USED);
2060 bp->queues[0].tx_head = 0;
2061 bp->queues[0].tx_tail = 0;
2062 desc->ctrl |= MACB_BIT(TX_WRAP);
2065 static void macb_reset_hw(struct macb *bp)
2067 struct macb_queue *queue;
2069 u32 ctrl = macb_readl(bp, NCR);
2071 /* Disable RX and TX (XXX: Should we halt the transmission
2074 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2076 /* Clear the stats registers (XXX: Update stats first?) */
2077 ctrl |= MACB_BIT(CLRSTAT);
2079 macb_writel(bp, NCR, ctrl);
2081 /* Clear all status flags */
2082 macb_writel(bp, TSR, -1);
2083 macb_writel(bp, RSR, -1);
2085 /* Disable all interrupts */
2086 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2087 queue_writel(queue, IDR, -1);
2088 queue_readl(queue, ISR);
2089 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2090 queue_writel(queue, ISR, -1);
2094 static u32 gem_mdc_clk_div(struct macb *bp)
2097 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2099 if (pclk_hz <= 20000000)
2100 config = GEM_BF(CLK, GEM_CLK_DIV8);
2101 else if (pclk_hz <= 40000000)
2102 config = GEM_BF(CLK, GEM_CLK_DIV16);
2103 else if (pclk_hz <= 80000000)
2104 config = GEM_BF(CLK, GEM_CLK_DIV32);
2105 else if (pclk_hz <= 120000000)
2106 config = GEM_BF(CLK, GEM_CLK_DIV48);
2107 else if (pclk_hz <= 160000000)
2108 config = GEM_BF(CLK, GEM_CLK_DIV64);
2110 config = GEM_BF(CLK, GEM_CLK_DIV96);
2115 static u32 macb_mdc_clk_div(struct macb *bp)
2118 unsigned long pclk_hz;
2120 if (macb_is_gem(bp))
2121 return gem_mdc_clk_div(bp);
2123 pclk_hz = clk_get_rate(bp->pclk);
2124 if (pclk_hz <= 20000000)
2125 config = MACB_BF(CLK, MACB_CLK_DIV8);
2126 else if (pclk_hz <= 40000000)
2127 config = MACB_BF(CLK, MACB_CLK_DIV16);
2128 else if (pclk_hz <= 80000000)
2129 config = MACB_BF(CLK, MACB_CLK_DIV32);
2131 config = MACB_BF(CLK, MACB_CLK_DIV64);
2136 /* Get the DMA bus width field of the network configuration register that we
2137 * should program. We find the width from decoding the design configuration
2138 * register to find the maximum supported data bus width.
2140 static u32 macb_dbw(struct macb *bp)
2142 if (!macb_is_gem(bp))
2145 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2147 return GEM_BF(DBW, GEM_DBW128);
2149 return GEM_BF(DBW, GEM_DBW64);
2152 return GEM_BF(DBW, GEM_DBW32);
2156 /* Configure the receive DMA engine
2157 * - use the correct receive buffer size
2158 * - set best burst length for DMA operations
2159 * (if not supported by FIFO, it will fallback to default)
2160 * - set both rx/tx packet buffers to full memory size
2161 * These are configurable parameters for GEM.
2163 static void macb_configure_dma(struct macb *bp)
2165 struct macb_queue *queue;
2170 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2171 if (macb_is_gem(bp)) {
2172 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2173 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2175 queue_writel(queue, RBQS, buffer_size);
2177 dmacfg |= GEM_BF(RXBS, buffer_size);
2179 if (bp->dma_burst_length)
2180 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2181 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2182 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2185 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2187 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2189 if (bp->dev->features & NETIF_F_HW_CSUM)
2190 dmacfg |= GEM_BIT(TXCOEN);
2192 dmacfg &= ~GEM_BIT(TXCOEN);
2194 dmacfg &= ~GEM_BIT(ADDR64);
2195 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2196 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2197 dmacfg |= GEM_BIT(ADDR64);
2199 #ifdef CONFIG_MACB_USE_HWSTAMP
2200 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2201 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2203 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2205 gem_writel(bp, DMACFG, dmacfg);
2209 static void macb_init_hw(struct macb *bp)
2211 struct macb_queue *queue;
2217 macb_set_hwaddr(bp);
2219 config = macb_mdc_clk_div(bp);
2220 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2221 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2222 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2223 config |= MACB_BIT(PAE); /* PAuse Enable */
2224 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2225 if (bp->caps & MACB_CAPS_JUMBO)
2226 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2228 config |= MACB_BIT(BIG); /* Receive oversized frames */
2229 if (bp->dev->flags & IFF_PROMISC)
2230 config |= MACB_BIT(CAF); /* Copy All Frames */
2231 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2232 config |= GEM_BIT(RXCOEN);
2233 if (!(bp->dev->flags & IFF_BROADCAST))
2234 config |= MACB_BIT(NBC); /* No BroadCast */
2235 config |= macb_dbw(bp);
2236 macb_writel(bp, NCFGR, config);
2237 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2238 gem_writel(bp, JML, bp->jumbo_max_len);
2239 bp->speed = SPEED_10;
2240 bp->duplex = DUPLEX_HALF;
2241 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2242 if (bp->caps & MACB_CAPS_JUMBO)
2243 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2245 macb_configure_dma(bp);
2247 /* Initialize TX and RX buffers */
2248 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2249 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
2250 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2251 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2252 queue_writel(queue, RBQPH, upper_32_bits(queue->rx_ring_dma));
2254 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2255 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2256 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2257 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2260 /* Enable interrupts */
2261 queue_writel(queue, IER,
2267 /* Enable TX and RX */
2268 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
2271 /* The hash address register is 64 bits long and takes up two
2272 * locations in the memory map. The least significant bits are stored
2273 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2275 * The unicast hash enable and the multicast hash enable bits in the
2276 * network configuration register enable the reception of hash matched
2277 * frames. The destination address is reduced to a 6 bit index into
2278 * the 64 bit hash register using the following hash function. The
2279 * hash function is an exclusive or of every sixth bit of the
2280 * destination address.
2282 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2283 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2284 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2285 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2286 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2287 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2289 * da[0] represents the least significant bit of the first byte
2290 * received, that is, the multicast/unicast indicator, and da[47]
2291 * represents the most significant bit of the last byte received. If
2292 * the hash index, hi[n], points to a bit that is set in the hash
2293 * register then the frame will be matched according to whether the
2294 * frame is multicast or unicast. A multicast match will be signalled
2295 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2296 * index points to a bit set in the hash register. A unicast match
2297 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2298 * and the hash index points to a bit set in the hash register. To
2299 * receive all multicast frames, the hash register should be set with
2300 * all ones and the multicast hash enable bit should be set in the
2301 * network configuration register.
2304 static inline int hash_bit_value(int bitnr, __u8 *addr)
2306 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2311 /* Return the hash index value for the specified address. */
2312 static int hash_get_index(__u8 *addr)
2317 for (j = 0; j < 6; j++) {
2318 for (i = 0, bitval = 0; i < 8; i++)
2319 bitval ^= hash_bit_value(i * 6 + j, addr);
2321 hash_index |= (bitval << j);
2327 /* Add multicast addresses to the internal multicast-hash table. */
2328 static void macb_sethashtable(struct net_device *dev)
2330 struct netdev_hw_addr *ha;
2331 unsigned long mc_filter[2];
2333 struct macb *bp = netdev_priv(dev);
2338 netdev_for_each_mc_addr(ha, dev) {
2339 bitnr = hash_get_index(ha->addr);
2340 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2343 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2344 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2347 /* Enable/Disable promiscuous and multicast modes. */
2348 static void macb_set_rx_mode(struct net_device *dev)
2351 struct macb *bp = netdev_priv(dev);
2353 cfg = macb_readl(bp, NCFGR);
2355 if (dev->flags & IFF_PROMISC) {
2356 /* Enable promiscuous mode */
2357 cfg |= MACB_BIT(CAF);
2359 /* Disable RX checksum offload */
2360 if (macb_is_gem(bp))
2361 cfg &= ~GEM_BIT(RXCOEN);
2363 /* Disable promiscuous mode */
2364 cfg &= ~MACB_BIT(CAF);
2366 /* Enable RX checksum offload only if requested */
2367 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2368 cfg |= GEM_BIT(RXCOEN);
2371 if (dev->flags & IFF_ALLMULTI) {
2372 /* Enable all multicast mode */
2373 macb_or_gem_writel(bp, HRB, -1);
2374 macb_or_gem_writel(bp, HRT, -1);
2375 cfg |= MACB_BIT(NCFGR_MTI);
2376 } else if (!netdev_mc_empty(dev)) {
2377 /* Enable specific multicasts */
2378 macb_sethashtable(dev);
2379 cfg |= MACB_BIT(NCFGR_MTI);
2380 } else if (dev->flags & (~IFF_ALLMULTI)) {
2381 /* Disable all multicast mode */
2382 macb_or_gem_writel(bp, HRB, 0);
2383 macb_or_gem_writel(bp, HRT, 0);
2384 cfg &= ~MACB_BIT(NCFGR_MTI);
2387 macb_writel(bp, NCFGR, cfg);
2390 static int macb_open(struct net_device *dev)
2392 struct macb *bp = netdev_priv(dev);
2393 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2394 struct macb_queue *queue;
2398 netdev_dbg(bp->dev, "open\n");
2400 /* carrier starts down */
2401 netif_carrier_off(dev);
2403 /* if the phy is not yet register, retry later*/
2407 /* RX buffers initialization */
2408 macb_init_rx_buffer_size(bp, bufsz);
2410 err = macb_alloc_consistent(bp);
2412 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2417 bp->macbgem_ops.mog_init_rings(bp);
2420 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2421 napi_enable(&queue->napi);
2423 /* schedule a link state check */
2424 phy_start(dev->phydev);
2426 netif_tx_start_all_queues(dev);
2429 bp->ptp_info->ptp_init(dev);
2434 static int macb_close(struct net_device *dev)
2436 struct macb *bp = netdev_priv(dev);
2437 struct macb_queue *queue;
2438 unsigned long flags;
2441 netif_tx_stop_all_queues(dev);
2443 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2444 napi_disable(&queue->napi);
2447 phy_stop(dev->phydev);
2449 spin_lock_irqsave(&bp->lock, flags);
2451 netif_carrier_off(dev);
2452 spin_unlock_irqrestore(&bp->lock, flags);
2454 macb_free_consistent(bp);
2457 bp->ptp_info->ptp_remove(dev);
2462 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2464 if (netif_running(dev))
2472 static void gem_update_stats(struct macb *bp)
2474 struct macb_queue *queue;
2475 unsigned int i, q, idx;
2476 unsigned long *stat;
2478 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2480 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2481 u32 offset = gem_statistics[i].offset;
2482 u64 val = bp->macb_reg_readl(bp, offset);
2484 bp->ethtool_stats[i] += val;
2487 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2488 /* Add GEM_OCTTXH, GEM_OCTRXH */
2489 val = bp->macb_reg_readl(bp, offset + 4);
2490 bp->ethtool_stats[i] += ((u64)val) << 32;
2495 idx = GEM_STATS_LEN;
2496 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2497 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2498 bp->ethtool_stats[idx++] = *stat;
2501 static struct net_device_stats *gem_get_stats(struct macb *bp)
2503 struct gem_stats *hwstat = &bp->hw_stats.gem;
2504 struct net_device_stats *nstat = &bp->dev->stats;
2506 gem_update_stats(bp);
2508 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2509 hwstat->rx_alignment_errors +
2510 hwstat->rx_resource_errors +
2511 hwstat->rx_overruns +
2512 hwstat->rx_oversize_frames +
2513 hwstat->rx_jabbers +
2514 hwstat->rx_undersized_frames +
2515 hwstat->rx_length_field_frame_errors);
2516 nstat->tx_errors = (hwstat->tx_late_collisions +
2517 hwstat->tx_excessive_collisions +
2518 hwstat->tx_underrun +
2519 hwstat->tx_carrier_sense_errors);
2520 nstat->multicast = hwstat->rx_multicast_frames;
2521 nstat->collisions = (hwstat->tx_single_collision_frames +
2522 hwstat->tx_multiple_collision_frames +
2523 hwstat->tx_excessive_collisions);
2524 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2525 hwstat->rx_jabbers +
2526 hwstat->rx_undersized_frames +
2527 hwstat->rx_length_field_frame_errors);
2528 nstat->rx_over_errors = hwstat->rx_resource_errors;
2529 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2530 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2531 nstat->rx_fifo_errors = hwstat->rx_overruns;
2532 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2533 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2534 nstat->tx_fifo_errors = hwstat->tx_underrun;
2539 static void gem_get_ethtool_stats(struct net_device *dev,
2540 struct ethtool_stats *stats, u64 *data)
2544 bp = netdev_priv(dev);
2545 gem_update_stats(bp);
2546 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2547 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2550 static int gem_get_sset_count(struct net_device *dev, int sset)
2552 struct macb *bp = netdev_priv(dev);
2556 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2562 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2564 char stat_string[ETH_GSTRING_LEN];
2565 struct macb *bp = netdev_priv(dev);
2566 struct macb_queue *queue;
2572 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2573 memcpy(p, gem_statistics[i].stat_string,
2576 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2577 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2578 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2579 q, queue_statistics[i].stat_string);
2580 memcpy(p, stat_string, ETH_GSTRING_LEN);
2587 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2589 struct macb *bp = netdev_priv(dev);
2590 struct net_device_stats *nstat = &bp->dev->stats;
2591 struct macb_stats *hwstat = &bp->hw_stats.macb;
2593 if (macb_is_gem(bp))
2594 return gem_get_stats(bp);
2596 /* read stats from hardware */
2597 macb_update_stats(bp);
2599 /* Convert HW stats into netdevice stats */
2600 nstat->rx_errors = (hwstat->rx_fcs_errors +
2601 hwstat->rx_align_errors +
2602 hwstat->rx_resource_errors +
2603 hwstat->rx_overruns +
2604 hwstat->rx_oversize_pkts +
2605 hwstat->rx_jabbers +
2606 hwstat->rx_undersize_pkts +
2607 hwstat->rx_length_mismatch);
2608 nstat->tx_errors = (hwstat->tx_late_cols +
2609 hwstat->tx_excessive_cols +
2610 hwstat->tx_underruns +
2611 hwstat->tx_carrier_errors +
2612 hwstat->sqe_test_errors);
2613 nstat->collisions = (hwstat->tx_single_cols +
2614 hwstat->tx_multiple_cols +
2615 hwstat->tx_excessive_cols);
2616 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2617 hwstat->rx_jabbers +
2618 hwstat->rx_undersize_pkts +
2619 hwstat->rx_length_mismatch);
2620 nstat->rx_over_errors = hwstat->rx_resource_errors +
2621 hwstat->rx_overruns;
2622 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2623 nstat->rx_frame_errors = hwstat->rx_align_errors;
2624 nstat->rx_fifo_errors = hwstat->rx_overruns;
2625 /* XXX: What does "missed" mean? */
2626 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2627 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2628 nstat->tx_fifo_errors = hwstat->tx_underruns;
2629 /* Don't know about heartbeat or window errors... */
2634 static int macb_get_regs_len(struct net_device *netdev)
2636 return MACB_GREGS_NBR * sizeof(u32);
2639 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2642 struct macb *bp = netdev_priv(dev);
2643 unsigned int tail, head;
2646 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2647 | MACB_GREGS_VERSION;
2649 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2650 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2652 regs_buff[0] = macb_readl(bp, NCR);
2653 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2654 regs_buff[2] = macb_readl(bp, NSR);
2655 regs_buff[3] = macb_readl(bp, TSR);
2656 regs_buff[4] = macb_readl(bp, RBQP);
2657 regs_buff[5] = macb_readl(bp, TBQP);
2658 regs_buff[6] = macb_readl(bp, RSR);
2659 regs_buff[7] = macb_readl(bp, IMR);
2661 regs_buff[8] = tail;
2662 regs_buff[9] = head;
2663 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2664 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2666 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2667 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2668 if (macb_is_gem(bp))
2669 regs_buff[13] = gem_readl(bp, DMACFG);
2672 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2674 struct macb *bp = netdev_priv(netdev);
2679 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2680 wol->supported = WAKE_MAGIC;
2682 if (bp->wol & MACB_WOL_ENABLED)
2683 wol->wolopts |= WAKE_MAGIC;
2687 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2689 struct macb *bp = netdev_priv(netdev);
2691 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2692 (wol->wolopts & ~WAKE_MAGIC))
2695 if (wol->wolopts & WAKE_MAGIC)
2696 bp->wol |= MACB_WOL_ENABLED;
2698 bp->wol &= ~MACB_WOL_ENABLED;
2700 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2705 static void macb_get_ringparam(struct net_device *netdev,
2706 struct ethtool_ringparam *ring)
2708 struct macb *bp = netdev_priv(netdev);
2710 ring->rx_max_pending = MAX_RX_RING_SIZE;
2711 ring->tx_max_pending = MAX_TX_RING_SIZE;
2713 ring->rx_pending = bp->rx_ring_size;
2714 ring->tx_pending = bp->tx_ring_size;
2717 static int macb_set_ringparam(struct net_device *netdev,
2718 struct ethtool_ringparam *ring)
2720 struct macb *bp = netdev_priv(netdev);
2721 u32 new_rx_size, new_tx_size;
2722 unsigned int reset = 0;
2724 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2727 new_rx_size = clamp_t(u32, ring->rx_pending,
2728 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2729 new_rx_size = roundup_pow_of_two(new_rx_size);
2731 new_tx_size = clamp_t(u32, ring->tx_pending,
2732 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2733 new_tx_size = roundup_pow_of_two(new_tx_size);
2735 if ((new_tx_size == bp->tx_ring_size) &&
2736 (new_rx_size == bp->rx_ring_size)) {
2741 if (netif_running(bp->dev)) {
2743 macb_close(bp->dev);
2746 bp->rx_ring_size = new_rx_size;
2747 bp->tx_ring_size = new_tx_size;
2755 #ifdef CONFIG_MACB_USE_HWSTAMP
2756 static unsigned int gem_get_tsu_rate(struct macb *bp)
2758 struct clk *tsu_clk;
2759 unsigned int tsu_rate;
2761 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2762 if (!IS_ERR(tsu_clk))
2763 tsu_rate = clk_get_rate(tsu_clk);
2764 /* try pclk instead */
2765 else if (!IS_ERR(bp->pclk)) {
2767 tsu_rate = clk_get_rate(tsu_clk);
2773 static s32 gem_get_ptp_max_adj(void)
2778 static int gem_get_ts_info(struct net_device *dev,
2779 struct ethtool_ts_info *info)
2781 struct macb *bp = netdev_priv(dev);
2783 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2784 ethtool_op_get_ts_info(dev, info);
2788 info->so_timestamping =
2789 SOF_TIMESTAMPING_TX_SOFTWARE |
2790 SOF_TIMESTAMPING_RX_SOFTWARE |
2791 SOF_TIMESTAMPING_SOFTWARE |
2792 SOF_TIMESTAMPING_TX_HARDWARE |
2793 SOF_TIMESTAMPING_RX_HARDWARE |
2794 SOF_TIMESTAMPING_RAW_HARDWARE;
2796 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2797 (1 << HWTSTAMP_TX_OFF) |
2798 (1 << HWTSTAMP_TX_ON);
2800 (1 << HWTSTAMP_FILTER_NONE) |
2801 (1 << HWTSTAMP_FILTER_ALL);
2803 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2808 static struct macb_ptp_info gem_ptp_info = {
2809 .ptp_init = gem_ptp_init,
2810 .ptp_remove = gem_ptp_remove,
2811 .get_ptp_max_adj = gem_get_ptp_max_adj,
2812 .get_tsu_rate = gem_get_tsu_rate,
2813 .get_ts_info = gem_get_ts_info,
2814 .get_hwtst = gem_get_hwtst,
2815 .set_hwtst = gem_set_hwtst,
2819 static int macb_get_ts_info(struct net_device *netdev,
2820 struct ethtool_ts_info *info)
2822 struct macb *bp = netdev_priv(netdev);
2825 return bp->ptp_info->get_ts_info(netdev, info);
2827 return ethtool_op_get_ts_info(netdev, info);
2830 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2832 struct ethtool_rx_fs_item *item;
2836 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2838 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2839 struct ethtool_rx_flow_spec *fs = &item->fs;
2840 struct ethtool_tcpip4_spec *tp4sp_m;
2842 if (fs->location >= num_t2_scr)
2845 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2847 /* enable/disable screener regs for the flow entry */
2848 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2850 /* only enable fields with no masking */
2851 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2853 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2854 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2856 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2858 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2859 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2861 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2863 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
2864 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
2866 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
2868 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
2872 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
2874 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
2875 uint16_t index = fs->location;
2881 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
2882 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2884 /* ignore field if any masking set */
2885 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
2886 /* 1st compare reg - IP source address */
2889 w0 = tp4sp_v->ip4src;
2890 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2891 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2892 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
2893 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
2894 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
2898 /* ignore field if any masking set */
2899 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
2900 /* 2nd compare reg - IP destination address */
2903 w0 = tp4sp_v->ip4dst;
2904 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2905 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2906 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
2907 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
2908 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
2912 /* ignore both port fields if masking set in both */
2913 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
2914 /* 3rd compare reg - source port, destination port */
2917 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
2918 if (tp4sp_m->psrc == tp4sp_m->pdst) {
2919 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
2920 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2921 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2922 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2924 /* only one port definition */
2925 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
2926 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
2927 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
2928 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
2929 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2930 } else { /* dst port */
2931 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2932 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
2935 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
2936 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
2941 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
2942 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
2944 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
2946 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
2948 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
2949 gem_writel_n(bp, SCRT2, index, t2_scr);
2952 static int gem_add_flow_filter(struct net_device *netdev,
2953 struct ethtool_rxnfc *cmd)
2955 struct macb *bp = netdev_priv(netdev);
2956 struct ethtool_rx_flow_spec *fs = &cmd->fs;
2957 struct ethtool_rx_fs_item *item, *newfs;
2958 unsigned long flags;
2962 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
2965 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
2968 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
2969 fs->flow_type, (int)fs->ring_cookie, fs->location,
2970 htonl(fs->h_u.tcp_ip4_spec.ip4src),
2971 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
2972 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
2974 spin_lock_irqsave(&bp->rx_fs_lock, flags);
2976 /* find correct place to add in list */
2977 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2978 if (item->fs.location > newfs->fs.location) {
2979 list_add_tail(&newfs->list, &item->list);
2982 } else if (item->fs.location == fs->location) {
2983 netdev_err(netdev, "Rule not added: location %d not free!\n",
2990 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
2992 gem_prog_cmp_regs(bp, fs);
2993 bp->rx_fs_list.count++;
2994 /* enable filtering if NTUPLE on */
2995 if (netdev->features & NETIF_F_NTUPLE)
2996 gem_enable_flow_filters(bp, 1);
2998 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3002 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3007 static int gem_del_flow_filter(struct net_device *netdev,
3008 struct ethtool_rxnfc *cmd)
3010 struct macb *bp = netdev_priv(netdev);
3011 struct ethtool_rx_fs_item *item;
3012 struct ethtool_rx_flow_spec *fs;
3013 unsigned long flags;
3015 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3017 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3018 if (item->fs.location == cmd->fs.location) {
3019 /* disable screener regs for the flow entry */
3022 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3023 fs->flow_type, (int)fs->ring_cookie, fs->location,
3024 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3025 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3026 htons(fs->h_u.tcp_ip4_spec.psrc),
3027 htons(fs->h_u.tcp_ip4_spec.pdst));
3029 gem_writel_n(bp, SCRT2, fs->location, 0);
3031 list_del(&item->list);
3032 bp->rx_fs_list.count--;
3033 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3039 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3043 static int gem_get_flow_entry(struct net_device *netdev,
3044 struct ethtool_rxnfc *cmd)
3046 struct macb *bp = netdev_priv(netdev);
3047 struct ethtool_rx_fs_item *item;
3049 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3050 if (item->fs.location == cmd->fs.location) {
3051 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3058 static int gem_get_all_flow_entries(struct net_device *netdev,
3059 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3061 struct macb *bp = netdev_priv(netdev);
3062 struct ethtool_rx_fs_item *item;
3065 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3066 if (cnt == cmd->rule_cnt)
3068 rule_locs[cnt] = item->fs.location;
3071 cmd->data = bp->max_tuples;
3072 cmd->rule_cnt = cnt;
3077 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3080 struct macb *bp = netdev_priv(netdev);
3084 case ETHTOOL_GRXRINGS:
3085 cmd->data = bp->num_queues;
3087 case ETHTOOL_GRXCLSRLCNT:
3088 cmd->rule_cnt = bp->rx_fs_list.count;
3090 case ETHTOOL_GRXCLSRULE:
3091 ret = gem_get_flow_entry(netdev, cmd);
3093 case ETHTOOL_GRXCLSRLALL:
3094 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3098 "Command parameter %d is not supported\n", cmd->cmd);
3105 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3107 struct macb *bp = netdev_priv(netdev);
3111 case ETHTOOL_SRXCLSRLINS:
3112 if ((cmd->fs.location >= bp->max_tuples)
3113 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3117 ret = gem_add_flow_filter(netdev, cmd);
3119 case ETHTOOL_SRXCLSRLDEL:
3120 ret = gem_del_flow_filter(netdev, cmd);
3124 "Command parameter %d is not supported\n", cmd->cmd);
3131 static const struct ethtool_ops macb_ethtool_ops = {
3132 .get_regs_len = macb_get_regs_len,
3133 .get_regs = macb_get_regs,
3134 .get_link = ethtool_op_get_link,
3135 .get_ts_info = ethtool_op_get_ts_info,
3136 .get_wol = macb_get_wol,
3137 .set_wol = macb_set_wol,
3138 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3139 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3140 .get_ringparam = macb_get_ringparam,
3141 .set_ringparam = macb_set_ringparam,
3144 static const struct ethtool_ops gem_ethtool_ops = {
3145 .get_regs_len = macb_get_regs_len,
3146 .get_regs = macb_get_regs,
3147 .get_link = ethtool_op_get_link,
3148 .get_ts_info = macb_get_ts_info,
3149 .get_ethtool_stats = gem_get_ethtool_stats,
3150 .get_strings = gem_get_ethtool_strings,
3151 .get_sset_count = gem_get_sset_count,
3152 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3153 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3154 .get_ringparam = macb_get_ringparam,
3155 .set_ringparam = macb_set_ringparam,
3156 .get_rxnfc = gem_get_rxnfc,
3157 .set_rxnfc = gem_set_rxnfc,
3160 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3162 struct phy_device *phydev = dev->phydev;
3163 struct macb *bp = netdev_priv(dev);
3165 if (!netif_running(dev))
3172 return phy_mii_ioctl(phydev, rq, cmd);
3176 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3178 return bp->ptp_info->get_hwtst(dev, rq);
3180 return phy_mii_ioctl(phydev, rq, cmd);
3184 static int macb_set_features(struct net_device *netdev,
3185 netdev_features_t features)
3187 struct macb *bp = netdev_priv(netdev);
3188 netdev_features_t changed = features ^ netdev->features;
3190 /* TX checksum offload */
3191 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
3194 dmacfg = gem_readl(bp, DMACFG);
3195 if (features & NETIF_F_HW_CSUM)
3196 dmacfg |= GEM_BIT(TXCOEN);
3198 dmacfg &= ~GEM_BIT(TXCOEN);
3199 gem_writel(bp, DMACFG, dmacfg);
3202 /* RX checksum offload */
3203 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
3206 netcfg = gem_readl(bp, NCFGR);
3207 if (features & NETIF_F_RXCSUM &&
3208 !(netdev->flags & IFF_PROMISC))
3209 netcfg |= GEM_BIT(RXCOEN);
3211 netcfg &= ~GEM_BIT(RXCOEN);
3212 gem_writel(bp, NCFGR, netcfg);
3215 /* RX Flow Filters */
3216 if ((changed & NETIF_F_NTUPLE) && macb_is_gem(bp)) {
3217 bool turn_on = features & NETIF_F_NTUPLE;
3219 gem_enable_flow_filters(bp, turn_on);
3224 static const struct net_device_ops macb_netdev_ops = {
3225 .ndo_open = macb_open,
3226 .ndo_stop = macb_close,
3227 .ndo_start_xmit = macb_start_xmit,
3228 .ndo_set_rx_mode = macb_set_rx_mode,
3229 .ndo_get_stats = macb_get_stats,
3230 .ndo_do_ioctl = macb_ioctl,
3231 .ndo_validate_addr = eth_validate_addr,
3232 .ndo_change_mtu = macb_change_mtu,
3233 .ndo_set_mac_address = eth_mac_addr,
3234 #ifdef CONFIG_NET_POLL_CONTROLLER
3235 .ndo_poll_controller = macb_poll_controller,
3237 .ndo_set_features = macb_set_features,
3238 .ndo_features_check = macb_features_check,
3241 /* Configure peripheral capabilities according to device tree
3242 * and integration options used
3244 static void macb_configure_caps(struct macb *bp,
3245 const struct macb_config *dt_conf)
3250 bp->caps = dt_conf->caps;
3252 if (hw_is_gem(bp->regs, bp->native_io)) {
3253 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3255 dcfg = gem_readl(bp, DCFG1);
3256 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3257 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3258 dcfg = gem_readl(bp, DCFG2);
3259 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3260 bp->caps |= MACB_CAPS_FIFO_MODE;
3261 #ifdef CONFIG_MACB_USE_HWSTAMP
3262 if (gem_has_ptp(bp)) {
3263 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3264 pr_err("GEM doesn't support hardware ptp.\n");
3266 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3267 bp->ptp_info = &gem_ptp_info;
3273 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3276 static void macb_probe_queues(void __iomem *mem,
3278 unsigned int *queue_mask,
3279 unsigned int *num_queues)
3286 /* is it macb or gem ?
3288 * We need to read directly from the hardware here because
3289 * we are early in the probe process and don't have the
3290 * MACB_CAPS_MACB_IS_GEM flag positioned
3292 if (!hw_is_gem(mem, native_io))
3295 /* bit 0 is never set but queue 0 always exists */
3296 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3300 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3301 if (*queue_mask & (1 << hw_q))
3305 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3306 struct clk **hclk, struct clk **tx_clk,
3307 struct clk **rx_clk)
3309 struct macb_platform_data *pdata;
3312 pdata = dev_get_platdata(&pdev->dev);
3314 *pclk = pdata->pclk;
3315 *hclk = pdata->hclk;
3317 *pclk = devm_clk_get(&pdev->dev, "pclk");
3318 *hclk = devm_clk_get(&pdev->dev, "hclk");
3321 if (IS_ERR(*pclk)) {
3322 err = PTR_ERR(*pclk);
3323 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
3327 if (IS_ERR(*hclk)) {
3328 err = PTR_ERR(*hclk);
3329 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
3333 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
3334 if (IS_ERR(*tx_clk))
3337 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
3338 if (IS_ERR(*rx_clk))
3341 err = clk_prepare_enable(*pclk);
3343 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3347 err = clk_prepare_enable(*hclk);
3349 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
3350 goto err_disable_pclk;
3353 err = clk_prepare_enable(*tx_clk);
3355 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
3356 goto err_disable_hclk;
3359 err = clk_prepare_enable(*rx_clk);
3361 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
3362 goto err_disable_txclk;
3368 clk_disable_unprepare(*tx_clk);
3371 clk_disable_unprepare(*hclk);
3374 clk_disable_unprepare(*pclk);
3379 static int macb_init(struct platform_device *pdev)
3381 struct net_device *dev = platform_get_drvdata(pdev);
3382 unsigned int hw_q, q;
3383 struct macb *bp = netdev_priv(dev);
3384 struct macb_queue *queue;
3388 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3389 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3391 /* set the queue register mapping once for all: queue0 has a special
3392 * register mapping but we don't want to test the queue index then
3393 * compute the corresponding register offset at run time.
3395 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3396 if (!(bp->queue_mask & (1 << hw_q)))
3399 queue = &bp->queues[q];
3401 netif_napi_add(dev, &queue->napi, macb_poll, 64);
3403 queue->ISR = GEM_ISR(hw_q - 1);
3404 queue->IER = GEM_IER(hw_q - 1);
3405 queue->IDR = GEM_IDR(hw_q - 1);
3406 queue->IMR = GEM_IMR(hw_q - 1);
3407 queue->TBQP = GEM_TBQP(hw_q - 1);
3408 queue->RBQP = GEM_RBQP(hw_q - 1);
3409 queue->RBQS = GEM_RBQS(hw_q - 1);
3410 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3411 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3412 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3413 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3417 /* queue0 uses legacy registers */
3418 queue->ISR = MACB_ISR;
3419 queue->IER = MACB_IER;
3420 queue->IDR = MACB_IDR;
3421 queue->IMR = MACB_IMR;
3422 queue->TBQP = MACB_TBQP;
3423 queue->RBQP = MACB_RBQP;
3424 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3425 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3426 queue->TBQPH = MACB_TBQPH;
3427 queue->RBQPH = MACB_RBQPH;
3432 /* get irq: here we use the linux queue index, not the hardware
3433 * queue index. the queue irq definitions in the device tree
3434 * must remove the optional gaps that could exist in the
3435 * hardware queue mask.
3437 queue->irq = platform_get_irq(pdev, q);
3438 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3439 IRQF_SHARED, dev->name, queue);
3442 "Unable to request IRQ %d (error %d)\n",
3447 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3451 dev->netdev_ops = &macb_netdev_ops;
3453 /* setup appropriated routines according to adapter type */
3454 if (macb_is_gem(bp)) {
3455 bp->max_tx_length = GEM_MAX_TX_LEN;
3456 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3457 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3458 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3459 bp->macbgem_ops.mog_rx = gem_rx;
3460 dev->ethtool_ops = &gem_ethtool_ops;
3462 bp->max_tx_length = MACB_MAX_TX_LEN;
3463 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3464 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3465 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3466 bp->macbgem_ops.mog_rx = macb_rx;
3467 dev->ethtool_ops = &macb_ethtool_ops;
3471 dev->hw_features = NETIF_F_SG;
3473 /* Check LSO capability */
3474 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3475 dev->hw_features |= MACB_NETIF_LSO;
3477 /* Checksum offload is only available on gem with packet buffer */
3478 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3479 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3480 if (bp->caps & MACB_CAPS_SG_DISABLED)
3481 dev->hw_features &= ~NETIF_F_SG;
3482 dev->features = dev->hw_features;
3484 /* Check RX Flow Filters support.
3485 * Max Rx flows set by availability of screeners & compare regs:
3486 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3488 reg = gem_readl(bp, DCFG8);
3489 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3490 GEM_BFEXT(T2SCR, reg));
3491 if (bp->max_tuples > 0) {
3492 /* also needs one ethtype match to check IPv4 */
3493 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3494 /* program this reg now */
3496 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3497 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3498 /* Filtering is supported in hw but don't enable it in kernel now */
3499 dev->hw_features |= NETIF_F_NTUPLE;
3500 /* init Rx flow definitions */
3501 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3502 bp->rx_fs_list.count = 0;
3503 spin_lock_init(&bp->rx_fs_lock);
3508 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3510 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3511 val = GEM_BIT(RGMII);
3512 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3513 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3514 val = MACB_BIT(RMII);
3515 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3516 val = MACB_BIT(MII);
3518 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3519 val |= MACB_BIT(CLKEN);
3521 macb_or_gem_writel(bp, USRIO, val);
3524 /* Set MII management clock divider */
3525 val = macb_mdc_clk_div(bp);
3526 val |= macb_dbw(bp);
3527 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3528 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3529 macb_writel(bp, NCFGR, val);
3534 #if defined(CONFIG_OF)
3535 /* 1518 rounded up */
3536 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3537 /* max number of receive buffers */
3538 #define AT91ETHER_MAX_RX_DESCR 9
3540 /* Initialize and start the Receiver and Transmit subsystems */
3541 static int at91ether_start(struct net_device *dev)
3543 struct macb *lp = netdev_priv(dev);
3544 struct macb_queue *q = &lp->queues[0];
3545 struct macb_dma_desc *desc;
3550 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3551 (AT91ETHER_MAX_RX_DESCR *
3552 macb_dma_desc_get_size(lp)),
3553 &q->rx_ring_dma, GFP_KERNEL);
3557 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3558 AT91ETHER_MAX_RX_DESCR *
3559 AT91ETHER_MAX_RBUFF_SZ,
3560 &q->rx_buffers_dma, GFP_KERNEL);
3561 if (!q->rx_buffers) {
3562 dma_free_coherent(&lp->pdev->dev,
3563 AT91ETHER_MAX_RX_DESCR *
3564 macb_dma_desc_get_size(lp),
3565 q->rx_ring, q->rx_ring_dma);
3570 addr = q->rx_buffers_dma;
3571 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3572 desc = macb_rx_desc(q, i);
3573 macb_set_addr(lp, desc, addr);
3575 addr += AT91ETHER_MAX_RBUFF_SZ;
3578 /* Set the Wrap bit on the last descriptor */
3579 desc->addr |= MACB_BIT(RX_WRAP);
3581 /* Reset buffer index */
3584 /* Program address of descriptor list in Rx Buffer Queue register */
3585 macb_writel(lp, RBQP, q->rx_ring_dma);
3587 /* Enable Receive and Transmit */
3588 ctl = macb_readl(lp, NCR);
3589 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3594 /* Open the ethernet interface */
3595 static int at91ether_open(struct net_device *dev)
3597 struct macb *lp = netdev_priv(dev);
3601 /* Clear internal statistics */
3602 ctl = macb_readl(lp, NCR);
3603 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3605 macb_set_hwaddr(lp);
3607 ret = at91ether_start(dev);
3611 /* Enable MAC interrupts */
3612 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3614 MACB_BIT(ISR_TUND) |
3617 MACB_BIT(ISR_ROVR) |
3620 /* schedule a link state check */
3621 phy_start(dev->phydev);
3623 netif_start_queue(dev);
3628 /* Close the interface */
3629 static int at91ether_close(struct net_device *dev)
3631 struct macb *lp = netdev_priv(dev);
3632 struct macb_queue *q = &lp->queues[0];
3635 /* Disable Receiver and Transmitter */
3636 ctl = macb_readl(lp, NCR);
3637 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3639 /* Disable MAC interrupts */
3640 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3642 MACB_BIT(ISR_TUND) |
3645 MACB_BIT(ISR_ROVR) |
3648 netif_stop_queue(dev);
3650 dma_free_coherent(&lp->pdev->dev,
3651 AT91ETHER_MAX_RX_DESCR *
3652 macb_dma_desc_get_size(lp),
3653 q->rx_ring, q->rx_ring_dma);
3656 dma_free_coherent(&lp->pdev->dev,
3657 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3658 q->rx_buffers, q->rx_buffers_dma);
3659 q->rx_buffers = NULL;
3664 /* Transmit packet */
3665 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3666 struct net_device *dev)
3668 struct macb *lp = netdev_priv(dev);
3670 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3671 netif_stop_queue(dev);
3673 /* Store packet information (to free when Tx completed) */
3675 lp->skb_length = skb->len;
3676 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3678 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3679 dev_kfree_skb_any(skb);
3680 dev->stats.tx_dropped++;
3681 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3682 return NETDEV_TX_OK;
3685 /* Set address of the data in the Transmit Address register */
3686 macb_writel(lp, TAR, lp->skb_physaddr);
3687 /* Set length of the packet in the Transmit Control register */
3688 macb_writel(lp, TCR, skb->len);
3691 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3692 return NETDEV_TX_BUSY;
3695 return NETDEV_TX_OK;
3698 /* Extract received frame from buffer descriptors and sent to upper layers.
3699 * (Called from interrupt context)
3701 static void at91ether_rx(struct net_device *dev)
3703 struct macb *lp = netdev_priv(dev);
3704 struct macb_queue *q = &lp->queues[0];
3705 struct macb_dma_desc *desc;
3706 unsigned char *p_recv;
3707 struct sk_buff *skb;
3708 unsigned int pktlen;
3710 desc = macb_rx_desc(q, q->rx_tail);
3711 while (desc->addr & MACB_BIT(RX_USED)) {
3712 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3713 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3714 skb = netdev_alloc_skb(dev, pktlen + 2);
3716 skb_reserve(skb, 2);
3717 skb_put_data(skb, p_recv, pktlen);
3719 skb->protocol = eth_type_trans(skb, dev);
3720 dev->stats.rx_packets++;
3721 dev->stats.rx_bytes += pktlen;
3724 dev->stats.rx_dropped++;
3727 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3728 dev->stats.multicast++;
3730 /* reset ownership bit */
3731 desc->addr &= ~MACB_BIT(RX_USED);
3733 /* wrap after last buffer */
3734 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3739 desc = macb_rx_desc(q, q->rx_tail);
3743 /* MAC interrupt handler */
3744 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3746 struct net_device *dev = dev_id;
3747 struct macb *lp = netdev_priv(dev);
3750 /* MAC Interrupt Status register indicates what interrupts are pending.
3751 * It is automatically cleared once read.
3753 intstatus = macb_readl(lp, ISR);
3755 /* Receive complete */
3756 if (intstatus & MACB_BIT(RCOMP))
3759 /* Transmit complete */
3760 if (intstatus & MACB_BIT(TCOMP)) {
3761 /* The TCOM bit is set even if the transmission failed */
3762 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3763 dev->stats.tx_errors++;
3766 dev_kfree_skb_irq(lp->skb);
3768 dma_unmap_single(NULL, lp->skb_physaddr,
3769 lp->skb_length, DMA_TO_DEVICE);
3770 dev->stats.tx_packets++;
3771 dev->stats.tx_bytes += lp->skb_length;
3773 netif_wake_queue(dev);
3776 /* Work-around for EMAC Errata section 41.3.1 */
3777 if (intstatus & MACB_BIT(RXUBR)) {
3778 ctl = macb_readl(lp, NCR);
3779 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3781 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3784 if (intstatus & MACB_BIT(ISR_ROVR))
3785 netdev_err(dev, "ROVR error\n");
3790 #ifdef CONFIG_NET_POLL_CONTROLLER
3791 static void at91ether_poll_controller(struct net_device *dev)
3793 unsigned long flags;
3795 local_irq_save(flags);
3796 at91ether_interrupt(dev->irq, dev);
3797 local_irq_restore(flags);
3801 static const struct net_device_ops at91ether_netdev_ops = {
3802 .ndo_open = at91ether_open,
3803 .ndo_stop = at91ether_close,
3804 .ndo_start_xmit = at91ether_start_xmit,
3805 .ndo_get_stats = macb_get_stats,
3806 .ndo_set_rx_mode = macb_set_rx_mode,
3807 .ndo_set_mac_address = eth_mac_addr,
3808 .ndo_do_ioctl = macb_ioctl,
3809 .ndo_validate_addr = eth_validate_addr,
3810 #ifdef CONFIG_NET_POLL_CONTROLLER
3811 .ndo_poll_controller = at91ether_poll_controller,
3815 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3816 struct clk **hclk, struct clk **tx_clk,
3817 struct clk **rx_clk)
3825 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3827 return PTR_ERR(*pclk);
3829 err = clk_prepare_enable(*pclk);
3831 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3838 static int at91ether_init(struct platform_device *pdev)
3840 struct net_device *dev = platform_get_drvdata(pdev);
3841 struct macb *bp = netdev_priv(dev);
3845 bp->queues[0].bp = bp;
3847 dev->netdev_ops = &at91ether_netdev_ops;
3848 dev->ethtool_ops = &macb_ethtool_ops;
3850 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3855 macb_writel(bp, NCR, 0);
3857 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3858 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3859 reg |= MACB_BIT(RM9200_RMII);
3861 macb_writel(bp, NCFGR, reg);
3866 static const struct macb_config at91sam9260_config = {
3867 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3868 .clk_init = macb_clk_init,
3872 static const struct macb_config sama5d3macb_config = {
3873 .caps = MACB_CAPS_SG_DISABLED
3874 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3875 .clk_init = macb_clk_init,
3879 static const struct macb_config pc302gem_config = {
3880 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3881 .dma_burst_length = 16,
3882 .clk_init = macb_clk_init,
3886 static const struct macb_config sama5d2_config = {
3887 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3888 .dma_burst_length = 16,
3889 .clk_init = macb_clk_init,
3893 static const struct macb_config sama5d3_config = {
3894 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3895 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3896 .dma_burst_length = 16,
3897 .clk_init = macb_clk_init,
3899 .jumbo_max_len = 10240,
3902 static const struct macb_config sama5d4_config = {
3903 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3904 .dma_burst_length = 4,
3905 .clk_init = macb_clk_init,
3909 static const struct macb_config emac_config = {
3910 .caps = MACB_CAPS_NEEDS_RSTONUBR,
3911 .clk_init = at91ether_clk_init,
3912 .init = at91ether_init,
3915 static const struct macb_config np4_config = {
3916 .caps = MACB_CAPS_USRIO_DISABLED,
3917 .clk_init = macb_clk_init,
3921 static const struct macb_config zynqmp_config = {
3922 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3924 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
3925 .dma_burst_length = 16,
3926 .clk_init = macb_clk_init,
3928 .jumbo_max_len = 10240,
3931 static const struct macb_config zynq_config = {
3932 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
3933 MACB_CAPS_NEEDS_RSTONUBR,
3934 .dma_burst_length = 16,
3935 .clk_init = macb_clk_init,
3939 static const struct of_device_id macb_dt_ids[] = {
3940 { .compatible = "cdns,at32ap7000-macb" },
3941 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3942 { .compatible = "cdns,macb" },
3943 { .compatible = "cdns,np4-macb", .data = &np4_config },
3944 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3945 { .compatible = "cdns,gem", .data = &pc302gem_config },
3946 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3947 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3948 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
3949 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3950 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3951 { .compatible = "cdns,emac", .data = &emac_config },
3952 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
3953 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
3956 MODULE_DEVICE_TABLE(of, macb_dt_ids);
3957 #endif /* CONFIG_OF */
3959 static const struct macb_config default_gem_config = {
3960 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3962 MACB_CAPS_GEM_HAS_PTP,
3963 .dma_burst_length = 16,
3964 .clk_init = macb_clk_init,
3966 .jumbo_max_len = 10240,
3969 static int macb_probe(struct platform_device *pdev)
3971 const struct macb_config *macb_config = &default_gem_config;
3972 int (*clk_init)(struct platform_device *, struct clk **,
3973 struct clk **, struct clk **, struct clk **)
3974 = macb_config->clk_init;
3975 int (*init)(struct platform_device *) = macb_config->init;
3976 struct device_node *np = pdev->dev.of_node;
3977 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
3978 unsigned int queue_mask, num_queues;
3979 struct macb_platform_data *pdata;
3981 struct phy_device *phydev;
3982 struct net_device *dev;
3983 struct resource *regs;
3989 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3990 mem = devm_ioremap_resource(&pdev->dev, regs);
3992 return PTR_ERR(mem);
3995 const struct of_device_id *match;
3997 match = of_match_node(macb_dt_ids, np);
3998 if (match && match->data) {
3999 macb_config = match->data;
4000 clk_init = macb_config->clk_init;
4001 init = macb_config->init;
4005 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
4009 native_io = hw_is_native_io(mem);
4011 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4012 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4015 goto err_disable_clocks;
4018 dev->base_addr = regs->start;
4020 SET_NETDEV_DEV(dev, &pdev->dev);
4022 bp = netdev_priv(dev);
4026 bp->native_io = native_io;
4028 bp->macb_reg_readl = hw_readl_native;
4029 bp->macb_reg_writel = hw_writel_native;
4031 bp->macb_reg_readl = hw_readl;
4032 bp->macb_reg_writel = hw_writel;
4034 bp->num_queues = num_queues;
4035 bp->queue_mask = queue_mask;
4037 bp->dma_burst_length = macb_config->dma_burst_length;
4040 bp->tx_clk = tx_clk;
4041 bp->rx_clk = rx_clk;
4043 bp->jumbo_max_len = macb_config->jumbo_max_len;
4046 if (of_get_property(np, "magic-packet", NULL))
4047 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4048 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4050 spin_lock_init(&bp->lock);
4052 /* setup capabilities */
4053 macb_configure_caps(bp, macb_config);
4055 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4056 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4057 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4058 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4061 platform_set_drvdata(pdev, dev);
4063 dev->irq = platform_get_irq(pdev, 0);
4066 goto err_out_free_netdev;
4069 /* MTU range: 68 - 1500 or 10240 */
4070 dev->min_mtu = GEM_MTU_MIN_SIZE;
4071 if (bp->caps & MACB_CAPS_JUMBO)
4072 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4074 dev->max_mtu = ETH_DATA_LEN;
4076 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4077 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4079 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4080 macb_dma_desc_get_size(bp);
4082 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4084 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4085 macb_dma_desc_get_size(bp);
4088 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4089 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4090 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4092 mac = of_get_mac_address(np);
4094 ether_addr_copy(bp->dev->dev_addr, mac);
4096 err = nvmem_get_mac_address(&pdev->dev, bp->dev->dev_addr);
4098 if (err == -EPROBE_DEFER)
4099 goto err_out_free_netdev;
4100 macb_get_hwaddr(bp);
4104 err = of_get_phy_mode(np);
4106 pdata = dev_get_platdata(&pdev->dev);
4107 if (pdata && pdata->is_rmii)
4108 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
4110 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4112 bp->phy_interface = err;
4115 /* IP specific init */
4118 goto err_out_free_netdev;
4120 err = macb_mii_init(bp);
4122 goto err_out_free_netdev;
4124 phydev = dev->phydev;
4126 netif_carrier_off(dev);
4128 err = register_netdev(dev);
4130 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4131 goto err_out_unregister_mdio;
4134 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4137 phy_attached_info(phydev);
4139 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4140 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4141 dev->base_addr, dev->irq, dev->dev_addr);
4145 err_out_unregister_mdio:
4146 phy_disconnect(dev->phydev);
4147 mdiobus_unregister(bp->mii_bus);
4148 of_node_put(bp->phy_node);
4149 if (np && of_phy_is_fixed_link(np))
4150 of_phy_deregister_fixed_link(np);
4151 mdiobus_free(bp->mii_bus);
4153 err_out_free_netdev:
4157 clk_disable_unprepare(tx_clk);
4158 clk_disable_unprepare(hclk);
4159 clk_disable_unprepare(pclk);
4160 clk_disable_unprepare(rx_clk);
4165 static int macb_remove(struct platform_device *pdev)
4167 struct net_device *dev;
4169 struct device_node *np = pdev->dev.of_node;
4171 dev = platform_get_drvdata(pdev);
4174 bp = netdev_priv(dev);
4176 phy_disconnect(dev->phydev);
4177 mdiobus_unregister(bp->mii_bus);
4178 if (np && of_phy_is_fixed_link(np))
4179 of_phy_deregister_fixed_link(np);
4181 mdiobus_free(bp->mii_bus);
4183 unregister_netdev(dev);
4184 clk_disable_unprepare(bp->tx_clk);
4185 clk_disable_unprepare(bp->hclk);
4186 clk_disable_unprepare(bp->pclk);
4187 clk_disable_unprepare(bp->rx_clk);
4188 of_node_put(bp->phy_node);
4195 static int __maybe_unused macb_suspend(struct device *dev)
4197 struct net_device *netdev = dev_get_drvdata(dev);
4198 struct macb *bp = netdev_priv(netdev);
4200 netif_carrier_off(netdev);
4201 netif_device_detach(netdev);
4203 if (bp->wol & MACB_WOL_ENABLED) {
4204 macb_writel(bp, IER, MACB_BIT(WOL));
4205 macb_writel(bp, WOL, MACB_BIT(MAG));
4206 enable_irq_wake(bp->queues[0].irq);
4208 clk_disable_unprepare(bp->tx_clk);
4209 clk_disable_unprepare(bp->hclk);
4210 clk_disable_unprepare(bp->pclk);
4211 clk_disable_unprepare(bp->rx_clk);
4217 static int __maybe_unused macb_resume(struct device *dev)
4219 struct net_device *netdev = dev_get_drvdata(dev);
4220 struct macb *bp = netdev_priv(netdev);
4222 if (bp->wol & MACB_WOL_ENABLED) {
4223 macb_writel(bp, IDR, MACB_BIT(WOL));
4224 macb_writel(bp, WOL, 0);
4225 disable_irq_wake(bp->queues[0].irq);
4227 clk_prepare_enable(bp->pclk);
4228 clk_prepare_enable(bp->hclk);
4229 clk_prepare_enable(bp->tx_clk);
4230 clk_prepare_enable(bp->rx_clk);
4233 netif_device_attach(netdev);
4238 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
4240 static struct platform_driver macb_driver = {
4241 .probe = macb_probe,
4242 .remove = macb_remove,
4245 .of_match_table = of_match_ptr(macb_dt_ids),
4250 module_platform_driver(macb_driver);
4252 MODULE_LICENSE("GPL");
4253 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4254 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4255 MODULE_ALIAS("platform:macb");