2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/crc32.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/circ_buf.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
22 #include <linux/gpio.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/interrupt.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/macb.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
37 #include <linux/udp.h>
38 #include <linux/tcp.h>
41 #define MACB_RX_BUFFER_SIZE 128
42 #define RX_BUFFER_MULTIPLE 64 /* bytes */
44 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
45 #define MIN_RX_RING_SIZE 64
46 #define MAX_RX_RING_SIZE 8192
47 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
50 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_TX_RING_SIZE 64
52 #define MAX_TX_RING_SIZE 4096
53 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
56 /* level of occupied TX descriptors under which we wake up TX process */
57 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
59 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
61 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
64 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
67 /* Max length of transmit frame must be a multiple of 8 bytes */
68 #define MACB_TX_LEN_ALIGN 8
69 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
70 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
72 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
73 #define MACB_NETIF_LSO NETIF_F_TSO
75 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
76 #define MACB_WOL_ENABLED (0x1 << 1)
78 /* Graceful stop timeouts in us. We should allow up to
79 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
81 #define MACB_HALT_TIMEOUT 1230
83 /* DMA buffer descriptor might be different size
84 * depends on hardware configuration:
86 * 1. dma address width 32 bits:
87 * word 1: 32 bit address of Data Buffer
90 * 2. dma address width 64 bits:
91 * word 1: 32 bit address of Data Buffer
93 * word 3: upper 32 bit address of Data Buffer
96 * 3. dma address width 32 bits with hardware timestamping:
97 * word 1: 32 bit address of Data Buffer
99 * word 3: timestamp word 1
100 * word 4: timestamp word 2
102 * 4. dma address width 64 bits with hardware timestamping:
103 * word 1: 32 bit address of Data Buffer
105 * word 3: upper 32 bit address of Data Buffer
107 * word 5: timestamp word 1
108 * word 6: timestamp word 2
110 static unsigned int macb_dma_desc_get_size(struct macb *bp)
113 unsigned int desc_size;
115 switch (bp->hw_dma_cap) {
117 desc_size = sizeof(struct macb_dma_desc)
118 + sizeof(struct macb_dma_desc_64);
121 desc_size = sizeof(struct macb_dma_desc)
122 + sizeof(struct macb_dma_desc_ptp);
124 case HW_DMA_CAP_64B_PTP:
125 desc_size = sizeof(struct macb_dma_desc)
126 + sizeof(struct macb_dma_desc_64)
127 + sizeof(struct macb_dma_desc_ptp);
130 desc_size = sizeof(struct macb_dma_desc);
134 return sizeof(struct macb_dma_desc);
137 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
140 switch (bp->hw_dma_cap) {
145 case HW_DMA_CAP_64B_PTP:
155 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
156 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
158 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
159 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
164 /* Ring buffer accessors */
165 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
167 return index & (bp->tx_ring_size - 1);
170 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
173 index = macb_tx_ring_wrap(queue->bp, index);
174 index = macb_adj_dma_desc_idx(queue->bp, index);
175 return &queue->tx_ring[index];
178 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
181 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
184 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
188 offset = macb_tx_ring_wrap(queue->bp, index) *
189 macb_dma_desc_get_size(queue->bp);
191 return queue->tx_ring_dma + offset;
194 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
196 return index & (bp->rx_ring_size - 1);
199 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
201 index = macb_rx_ring_wrap(queue->bp, index);
202 index = macb_adj_dma_desc_idx(queue->bp, index);
203 return &queue->rx_ring[index];
206 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
208 return queue->rx_buffers + queue->bp->rx_buffer_size *
209 macb_rx_ring_wrap(queue->bp, index);
213 static u32 hw_readl_native(struct macb *bp, int offset)
215 return __raw_readl(bp->regs + offset);
218 static void hw_writel_native(struct macb *bp, int offset, u32 value)
220 __raw_writel(value, bp->regs + offset);
223 static u32 hw_readl(struct macb *bp, int offset)
225 return readl_relaxed(bp->regs + offset);
228 static void hw_writel(struct macb *bp, int offset, u32 value)
230 writel_relaxed(value, bp->regs + offset);
233 /* Find the CPU endianness by using the loopback bit of NCR register. When the
234 * CPU is in big endian we need to program swapped mode for management
237 static bool hw_is_native_io(void __iomem *addr)
239 u32 value = MACB_BIT(LLB);
241 __raw_writel(value, addr + MACB_NCR);
242 value = __raw_readl(addr + MACB_NCR);
244 /* Write 0 back to disable everything */
245 __raw_writel(0, addr + MACB_NCR);
247 return value == MACB_BIT(LLB);
250 static bool hw_is_gem(void __iomem *addr, bool native_io)
255 id = __raw_readl(addr + MACB_MID);
257 id = readl_relaxed(addr + MACB_MID);
259 return MACB_BFEXT(IDNUM, id) >= 0x2;
262 static void macb_set_hwaddr(struct macb *bp)
267 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
268 macb_or_gem_writel(bp, SA1B, bottom);
269 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
270 macb_or_gem_writel(bp, SA1T, top);
272 /* Clear unused address register sets */
273 macb_or_gem_writel(bp, SA2B, 0);
274 macb_or_gem_writel(bp, SA2T, 0);
275 macb_or_gem_writel(bp, SA3B, 0);
276 macb_or_gem_writel(bp, SA3T, 0);
277 macb_or_gem_writel(bp, SA4B, 0);
278 macb_or_gem_writel(bp, SA4T, 0);
281 static void macb_get_hwaddr(struct macb *bp)
283 struct macb_platform_data *pdata;
289 pdata = dev_get_platdata(&bp->pdev->dev);
291 /* Check all 4 address register for valid address */
292 for (i = 0; i < 4; i++) {
293 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
294 top = macb_or_gem_readl(bp, SA1T + i * 8);
296 if (pdata && pdata->rev_eth_addr) {
297 addr[5] = bottom & 0xff;
298 addr[4] = (bottom >> 8) & 0xff;
299 addr[3] = (bottom >> 16) & 0xff;
300 addr[2] = (bottom >> 24) & 0xff;
301 addr[1] = top & 0xff;
302 addr[0] = (top & 0xff00) >> 8;
304 addr[0] = bottom & 0xff;
305 addr[1] = (bottom >> 8) & 0xff;
306 addr[2] = (bottom >> 16) & 0xff;
307 addr[3] = (bottom >> 24) & 0xff;
308 addr[4] = top & 0xff;
309 addr[5] = (top >> 8) & 0xff;
312 if (is_valid_ether_addr(addr)) {
313 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
318 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
319 eth_hw_addr_random(bp->dev);
322 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
324 struct macb *bp = bus->priv;
327 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
328 | MACB_BF(RW, MACB_MAN_READ)
329 | MACB_BF(PHYA, mii_id)
330 | MACB_BF(REGA, regnum)
331 | MACB_BF(CODE, MACB_MAN_CODE)));
333 /* wait for end of transfer */
334 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
337 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
342 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
345 struct macb *bp = bus->priv;
347 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
348 | MACB_BF(RW, MACB_MAN_WRITE)
349 | MACB_BF(PHYA, mii_id)
350 | MACB_BF(REGA, regnum)
351 | MACB_BF(CODE, MACB_MAN_CODE)
352 | MACB_BF(DATA, value)));
354 /* wait for end of transfer */
355 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
362 * macb_set_tx_clk() - Set a clock to a new frequency
363 * @clk Pointer to the clock to change
364 * @rate New frequency in Hz
365 * @dev Pointer to the struct net_device
367 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
369 long ferr, rate, rate_rounded;
388 rate_rounded = clk_round_rate(clk, rate);
389 if (rate_rounded < 0)
392 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
395 ferr = abs(rate_rounded - rate);
396 ferr = DIV_ROUND_UP(ferr, rate / 100000);
398 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
401 if (clk_set_rate(clk, rate_rounded))
402 netdev_err(dev, "adjusting tx_clk failed.\n");
405 static void macb_handle_link_change(struct net_device *dev)
407 struct macb *bp = netdev_priv(dev);
408 struct phy_device *phydev = dev->phydev;
410 int status_change = 0;
412 spin_lock_irqsave(&bp->lock, flags);
415 if ((bp->speed != phydev->speed) ||
416 (bp->duplex != phydev->duplex)) {
419 reg = macb_readl(bp, NCFGR);
420 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
422 reg &= ~GEM_BIT(GBE);
426 if (phydev->speed == SPEED_100)
427 reg |= MACB_BIT(SPD);
428 if (phydev->speed == SPEED_1000 &&
429 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
432 macb_or_gem_writel(bp, NCFGR, reg);
434 bp->speed = phydev->speed;
435 bp->duplex = phydev->duplex;
440 if (phydev->link != bp->link) {
445 bp->link = phydev->link;
450 spin_unlock_irqrestore(&bp->lock, flags);
454 /* Update the TX clock rate if and only if the link is
455 * up and there has been a link change.
457 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
459 netif_carrier_on(dev);
460 netdev_info(dev, "link up (%d/%s)\n",
462 phydev->duplex == DUPLEX_FULL ?
465 netif_carrier_off(dev);
466 netdev_info(dev, "link down\n");
471 /* based on au1000_eth. c*/
472 static int macb_mii_probe(struct net_device *dev)
474 struct macb *bp = netdev_priv(dev);
475 struct macb_platform_data *pdata;
476 struct phy_device *phydev;
477 struct device_node *np;
480 pdata = dev_get_platdata(&bp->pdev->dev);
481 np = bp->pdev->dev.of_node;
485 if (of_phy_is_fixed_link(np)) {
486 bp->phy_node = of_node_get(np);
488 bp->phy_node = of_parse_phandle(np, "phy-handle", 0);
489 /* fallback to standard phy registration if no
490 * phy-handle was found nor any phy found during
491 * dt phy registration
493 if (!bp->phy_node && !phy_find_first(bp->mii_bus)) {
494 for (i = 0; i < PHY_MAX_ADDR; i++) {
495 struct phy_device *phydev;
497 phydev = mdiobus_scan(bp->mii_bus, i);
498 if (IS_ERR(phydev) &&
499 PTR_ERR(phydev) != -ENODEV) {
500 ret = PTR_ERR(phydev);
512 phydev = of_phy_connect(dev, bp->phy_node,
513 &macb_handle_link_change, 0,
518 phydev = phy_find_first(bp->mii_bus);
520 netdev_err(dev, "no PHY found\n");
525 if (gpio_is_valid(pdata->phy_irq_pin)) {
526 ret = devm_gpio_request(&bp->pdev->dev,
527 pdata->phy_irq_pin, "phy int");
529 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
530 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
533 phydev->irq = PHY_POLL;
537 /* attach the mac to the phy */
538 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
541 netdev_err(dev, "Could not attach to PHY\n");
546 /* mask with MAC supported features */
547 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
548 phy_set_max_speed(phydev, SPEED_1000);
550 phy_set_max_speed(phydev, SPEED_100);
552 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
553 phy_remove_link_mode(phydev,
554 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
563 static int macb_mii_init(struct macb *bp)
565 struct macb_platform_data *pdata;
566 struct device_node *np;
569 /* Enable management port */
570 macb_writel(bp, NCR, MACB_BIT(MPE));
572 bp->mii_bus = mdiobus_alloc();
578 bp->mii_bus->name = "MACB_mii_bus";
579 bp->mii_bus->read = &macb_mdio_read;
580 bp->mii_bus->write = &macb_mdio_write;
581 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
582 bp->pdev->name, bp->pdev->id);
583 bp->mii_bus->priv = bp;
584 bp->mii_bus->parent = &bp->pdev->dev;
585 pdata = dev_get_platdata(&bp->pdev->dev);
587 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
589 np = bp->pdev->dev.of_node;
590 if (np && of_phy_is_fixed_link(np)) {
591 if (of_phy_register_fixed_link(np) < 0) {
592 dev_err(&bp->pdev->dev,
593 "broken fixed-link specification %pOF\n", np);
594 goto err_out_free_mdiobus;
597 err = mdiobus_register(bp->mii_bus);
600 bp->mii_bus->phy_mask = pdata->phy_mask;
602 err = of_mdiobus_register(bp->mii_bus, np);
606 goto err_out_free_fixed_link;
608 err = macb_mii_probe(bp->dev);
610 goto err_out_unregister_bus;
614 err_out_unregister_bus:
615 mdiobus_unregister(bp->mii_bus);
616 err_out_free_fixed_link:
617 if (np && of_phy_is_fixed_link(np))
618 of_phy_deregister_fixed_link(np);
619 err_out_free_mdiobus:
620 of_node_put(bp->phy_node);
621 mdiobus_free(bp->mii_bus);
626 static void macb_update_stats(struct macb *bp)
628 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
629 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
630 int offset = MACB_PFR;
632 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
634 for (; p < end; p++, offset += 4)
635 *p += bp->macb_reg_readl(bp, offset);
638 static int macb_halt_tx(struct macb *bp)
640 unsigned long halt_time, timeout;
643 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
645 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
648 status = macb_readl(bp, TSR);
649 if (!(status & MACB_BIT(TGO)))
653 } while (time_before(halt_time, timeout));
658 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
660 if (tx_skb->mapping) {
661 if (tx_skb->mapped_as_page)
662 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
663 tx_skb->size, DMA_TO_DEVICE);
665 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
666 tx_skb->size, DMA_TO_DEVICE);
671 dev_kfree_skb_any(tx_skb->skb);
676 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
678 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
679 struct macb_dma_desc_64 *desc_64;
681 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
682 desc_64 = macb_64b_desc(bp, desc);
683 desc_64->addrh = upper_32_bits(addr);
684 /* The low bits of RX address contain the RX_USED bit, clearing
685 * of which allows packet RX. Make sure the high bits are also
686 * visible to HW at that point.
691 desc->addr = lower_32_bits(addr);
694 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
697 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
698 struct macb_dma_desc_64 *desc_64;
700 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
701 desc_64 = macb_64b_desc(bp, desc);
702 addr = ((u64)(desc_64->addrh) << 32);
705 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
709 static void macb_tx_error_task(struct work_struct *work)
711 struct macb_queue *queue = container_of(work, struct macb_queue,
713 struct macb *bp = queue->bp;
714 struct macb_tx_skb *tx_skb;
715 struct macb_dma_desc *desc;
720 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
721 (unsigned int)(queue - bp->queues),
722 queue->tx_tail, queue->tx_head);
724 /* Prevent the queue IRQ handlers from running: each of them may call
725 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
726 * As explained below, we have to halt the transmission before updating
727 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
728 * network engine about the macb/gem being halted.
730 spin_lock_irqsave(&bp->lock, flags);
732 /* Make sure nobody is trying to queue up new packets */
733 netif_tx_stop_all_queues(bp->dev);
735 /* Stop transmission now
736 * (in case we have just queued new packets)
737 * macb/gem must be halted to write TBQP register
739 if (macb_halt_tx(bp))
740 /* Just complain for now, reinitializing TX path can be good */
741 netdev_err(bp->dev, "BUG: halt tx timed out\n");
743 /* Treat frames in TX queue including the ones that caused the error.
744 * Free transmit buffers in upper layer.
746 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
749 desc = macb_tx_desc(queue, tail);
751 tx_skb = macb_tx_skb(queue, tail);
754 if (ctrl & MACB_BIT(TX_USED)) {
755 /* skb is set for the last buffer of the frame */
757 macb_tx_unmap(bp, tx_skb);
759 tx_skb = macb_tx_skb(queue, tail);
763 /* ctrl still refers to the first buffer descriptor
764 * since it's the only one written back by the hardware
766 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
767 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
768 macb_tx_ring_wrap(bp, tail),
770 bp->dev->stats.tx_packets++;
771 queue->stats.tx_packets++;
772 bp->dev->stats.tx_bytes += skb->len;
773 queue->stats.tx_bytes += skb->len;
776 /* "Buffers exhausted mid-frame" errors may only happen
777 * if the driver is buggy, so complain loudly about
778 * those. Statistics are updated by hardware.
780 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
782 "BUG: TX buffers exhausted mid-frame\n");
784 desc->ctrl = ctrl | MACB_BIT(TX_USED);
787 macb_tx_unmap(bp, tx_skb);
790 /* Set end of TX queue */
791 desc = macb_tx_desc(queue, 0);
792 macb_set_addr(bp, desc, 0);
793 desc->ctrl = MACB_BIT(TX_USED);
795 /* Make descriptor updates visible to hardware */
798 /* Reinitialize the TX desc queue */
799 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
800 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
801 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
802 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
804 /* Make TX ring reflect state of hardware */
808 /* Housework before enabling TX IRQ */
809 macb_writel(bp, TSR, macb_readl(bp, TSR));
810 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
812 /* Now we are ready to start transmission again */
813 netif_tx_start_all_queues(bp->dev);
814 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
816 spin_unlock_irqrestore(&bp->lock, flags);
819 static void macb_tx_interrupt(struct macb_queue *queue)
824 struct macb *bp = queue->bp;
825 u16 queue_index = queue - bp->queues;
827 status = macb_readl(bp, TSR);
828 macb_writel(bp, TSR, status);
830 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
831 queue_writel(queue, ISR, MACB_BIT(TCOMP));
833 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
834 (unsigned long)status);
836 head = queue->tx_head;
837 for (tail = queue->tx_tail; tail != head; tail++) {
838 struct macb_tx_skb *tx_skb;
840 struct macb_dma_desc *desc;
843 desc = macb_tx_desc(queue, tail);
845 /* Make hw descriptor updates visible to CPU */
850 /* TX_USED bit is only set by hardware on the very first buffer
851 * descriptor of the transmitted frame.
853 if (!(ctrl & MACB_BIT(TX_USED)))
856 /* Process all buffers of the current transmitted frame */
858 tx_skb = macb_tx_skb(queue, tail);
861 /* First, update TX stats if needed */
863 if (gem_ptp_do_txstamp(queue, skb, desc) == 0) {
864 /* skb now belongs to timestamp buffer
865 * and will be removed later
869 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
870 macb_tx_ring_wrap(bp, tail),
872 bp->dev->stats.tx_packets++;
873 queue->stats.tx_packets++;
874 bp->dev->stats.tx_bytes += skb->len;
875 queue->stats.tx_bytes += skb->len;
878 /* Now we can safely release resources */
879 macb_tx_unmap(bp, tx_skb);
881 /* skb is set only for the last buffer of the frame.
882 * WARNING: at this point skb has been freed by
890 queue->tx_tail = tail;
891 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
892 CIRC_CNT(queue->tx_head, queue->tx_tail,
893 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
894 netif_wake_subqueue(bp->dev, queue_index);
897 static void gem_rx_refill(struct macb_queue *queue)
902 struct macb *bp = queue->bp;
903 struct macb_dma_desc *desc;
905 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
906 bp->rx_ring_size) > 0) {
907 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
909 /* Make hw descriptor updates visible to CPU */
912 queue->rx_prepared_head++;
913 desc = macb_rx_desc(queue, entry);
915 if (!queue->rx_skbuff[entry]) {
916 /* allocate sk_buff for this free entry in ring */
917 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
918 if (unlikely(!skb)) {
920 "Unable to allocate sk_buff\n");
924 /* now fill corresponding descriptor entry */
925 paddr = dma_map_single(&bp->pdev->dev, skb->data,
928 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
933 queue->rx_skbuff[entry] = skb;
935 if (entry == bp->rx_ring_size - 1)
936 paddr |= MACB_BIT(RX_WRAP);
938 /* Setting addr clears RX_USED and allows reception,
939 * make sure ctrl is cleared first to avoid a race.
942 macb_set_addr(bp, desc, paddr);
944 /* properly align Ethernet header */
945 skb_reserve(skb, NET_IP_ALIGN);
949 desc->addr &= ~MACB_BIT(RX_USED);
953 /* Make descriptor updates visible to hardware */
956 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
957 queue, queue->rx_prepared_head, queue->rx_tail);
960 /* Mark DMA descriptors from begin up to and not including end as unused */
961 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
966 for (frag = begin; frag != end; frag++) {
967 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
969 desc->addr &= ~MACB_BIT(RX_USED);
972 /* Make descriptor updates visible to hardware */
975 /* When this happens, the hardware stats registers for
976 * whatever caused this is updated, so we don't have to record
981 static int gem_rx(struct macb_queue *queue, int budget)
983 struct macb *bp = queue->bp;
987 struct macb_dma_desc *desc;
990 while (count < budget) {
995 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
996 desc = macb_rx_desc(queue, entry);
998 /* Make hw descriptor updates visible to CPU */
1001 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1002 addr = macb_get_addr(bp, desc);
1007 /* Ensure ctrl is at least as up-to-date as rxused */
1015 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1017 "not whole frame pointed by descriptor\n");
1018 bp->dev->stats.rx_dropped++;
1019 queue->stats.rx_dropped++;
1022 skb = queue->rx_skbuff[entry];
1023 if (unlikely(!skb)) {
1025 "inconsistent Rx descriptor chain\n");
1026 bp->dev->stats.rx_dropped++;
1027 queue->stats.rx_dropped++;
1030 /* now everything is ready for receiving packet */
1031 queue->rx_skbuff[entry] = NULL;
1032 len = ctrl & bp->rx_frm_len_mask;
1034 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1037 dma_unmap_single(&bp->pdev->dev, addr,
1038 bp->rx_buffer_size, DMA_FROM_DEVICE);
1040 skb->protocol = eth_type_trans(skb, bp->dev);
1041 skb_checksum_none_assert(skb);
1042 if (bp->dev->features & NETIF_F_RXCSUM &&
1043 !(bp->dev->flags & IFF_PROMISC) &&
1044 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1045 skb->ip_summed = CHECKSUM_UNNECESSARY;
1047 bp->dev->stats.rx_packets++;
1048 queue->stats.rx_packets++;
1049 bp->dev->stats.rx_bytes += skb->len;
1050 queue->stats.rx_bytes += skb->len;
1052 gem_ptp_do_rxstamp(bp, skb, desc);
1054 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1055 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1056 skb->len, skb->csum);
1057 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1058 skb_mac_header(skb), 16, true);
1059 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1060 skb->data, 32, true);
1063 netif_receive_skb(skb);
1066 gem_rx_refill(queue);
1071 static int macb_rx_frame(struct macb_queue *queue, unsigned int first_frag,
1072 unsigned int last_frag)
1076 unsigned int offset;
1077 struct sk_buff *skb;
1078 struct macb_dma_desc *desc;
1079 struct macb *bp = queue->bp;
1081 desc = macb_rx_desc(queue, last_frag);
1082 len = desc->ctrl & bp->rx_frm_len_mask;
1084 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1085 macb_rx_ring_wrap(bp, first_frag),
1086 macb_rx_ring_wrap(bp, last_frag), len);
1088 /* The ethernet header starts NET_IP_ALIGN bytes into the
1089 * first buffer. Since the header is 14 bytes, this makes the
1090 * payload word-aligned.
1092 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1093 * the two padding bytes into the skb so that we avoid hitting
1094 * the slowpath in memcpy(), and pull them off afterwards.
1096 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1098 bp->dev->stats.rx_dropped++;
1099 for (frag = first_frag; ; frag++) {
1100 desc = macb_rx_desc(queue, frag);
1101 desc->addr &= ~MACB_BIT(RX_USED);
1102 if (frag == last_frag)
1106 /* Make descriptor updates visible to hardware */
1113 len += NET_IP_ALIGN;
1114 skb_checksum_none_assert(skb);
1117 for (frag = first_frag; ; frag++) {
1118 unsigned int frag_len = bp->rx_buffer_size;
1120 if (offset + frag_len > len) {
1121 if (unlikely(frag != last_frag)) {
1122 dev_kfree_skb_any(skb);
1125 frag_len = len - offset;
1127 skb_copy_to_linear_data_offset(skb, offset,
1128 macb_rx_buffer(queue, frag),
1130 offset += bp->rx_buffer_size;
1131 desc = macb_rx_desc(queue, frag);
1132 desc->addr &= ~MACB_BIT(RX_USED);
1134 if (frag == last_frag)
1138 /* Make descriptor updates visible to hardware */
1141 __skb_pull(skb, NET_IP_ALIGN);
1142 skb->protocol = eth_type_trans(skb, bp->dev);
1144 bp->dev->stats.rx_packets++;
1145 bp->dev->stats.rx_bytes += skb->len;
1146 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1147 skb->len, skb->csum);
1148 netif_receive_skb(skb);
1153 static inline void macb_init_rx_ring(struct macb_queue *queue)
1155 struct macb *bp = queue->bp;
1157 struct macb_dma_desc *desc = NULL;
1160 addr = queue->rx_buffers_dma;
1161 for (i = 0; i < bp->rx_ring_size; i++) {
1162 desc = macb_rx_desc(queue, i);
1163 macb_set_addr(bp, desc, addr);
1165 addr += bp->rx_buffer_size;
1167 desc->addr |= MACB_BIT(RX_WRAP);
1171 static int macb_rx(struct macb_queue *queue, int budget)
1173 struct macb *bp = queue->bp;
1174 bool reset_rx_queue = false;
1177 int first_frag = -1;
1179 for (tail = queue->rx_tail; budget > 0; tail++) {
1180 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1183 /* Make hw descriptor updates visible to CPU */
1186 if (!(desc->addr & MACB_BIT(RX_USED)))
1189 /* Ensure ctrl is at least as up-to-date as addr */
1194 if (ctrl & MACB_BIT(RX_SOF)) {
1195 if (first_frag != -1)
1196 discard_partial_frame(queue, first_frag, tail);
1200 if (ctrl & MACB_BIT(RX_EOF)) {
1203 if (unlikely(first_frag == -1)) {
1204 reset_rx_queue = true;
1208 dropped = macb_rx_frame(queue, first_frag, tail);
1210 if (unlikely(dropped < 0)) {
1211 reset_rx_queue = true;
1221 if (unlikely(reset_rx_queue)) {
1222 unsigned long flags;
1225 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1227 spin_lock_irqsave(&bp->lock, flags);
1229 ctrl = macb_readl(bp, NCR);
1230 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1232 macb_init_rx_ring(queue);
1233 queue_writel(queue, RBQP, queue->rx_ring_dma);
1235 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1237 spin_unlock_irqrestore(&bp->lock, flags);
1241 if (first_frag != -1)
1242 queue->rx_tail = first_frag;
1244 queue->rx_tail = tail;
1249 static int macb_poll(struct napi_struct *napi, int budget)
1251 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1252 struct macb *bp = queue->bp;
1256 status = macb_readl(bp, RSR);
1257 macb_writel(bp, RSR, status);
1259 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1260 (unsigned long)status, budget);
1262 work_done = bp->macbgem_ops.mog_rx(queue, budget);
1263 if (work_done < budget) {
1264 napi_complete_done(napi, work_done);
1266 /* Packets received while interrupts were disabled */
1267 status = macb_readl(bp, RSR);
1269 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1270 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1271 napi_reschedule(napi);
1273 queue_writel(queue, IER, MACB_RX_INT_FLAGS);
1277 /* TODO: Handle errors */
1282 static void macb_hresp_error_task(unsigned long data)
1284 struct macb *bp = (struct macb *)data;
1285 struct net_device *dev = bp->dev;
1286 struct macb_queue *queue = bp->queues;
1290 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1291 queue_writel(queue, IDR, MACB_RX_INT_FLAGS |
1295 ctrl = macb_readl(bp, NCR);
1296 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1297 macb_writel(bp, NCR, ctrl);
1299 netif_tx_stop_all_queues(dev);
1300 netif_carrier_off(dev);
1302 bp->macbgem_ops.mog_init_rings(bp);
1304 /* Initialize TX and RX buffers */
1305 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1306 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
1307 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1308 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1309 queue_writel(queue, RBQPH,
1310 upper_32_bits(queue->rx_ring_dma));
1312 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1313 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1314 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1315 queue_writel(queue, TBQPH,
1316 upper_32_bits(queue->tx_ring_dma));
1319 /* Enable interrupts */
1320 queue_writel(queue, IER,
1326 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1327 macb_writel(bp, NCR, ctrl);
1329 netif_carrier_on(dev);
1330 netif_tx_start_all_queues(dev);
1333 static void macb_tx_restart(struct macb_queue *queue)
1335 unsigned int head = queue->tx_head;
1336 unsigned int tail = queue->tx_tail;
1337 struct macb *bp = queue->bp;
1339 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1340 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1345 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1348 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1350 struct macb_queue *queue = dev_id;
1351 struct macb *bp = queue->bp;
1352 struct net_device *dev = bp->dev;
1355 status = queue_readl(queue, ISR);
1357 if (unlikely(!status))
1360 spin_lock(&bp->lock);
1363 /* close possible race with dev_close */
1364 if (unlikely(!netif_running(dev))) {
1365 queue_writel(queue, IDR, -1);
1366 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1367 queue_writel(queue, ISR, -1);
1371 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1372 (unsigned int)(queue - bp->queues),
1373 (unsigned long)status);
1375 if (status & MACB_RX_INT_FLAGS) {
1376 /* There's no point taking any more interrupts
1377 * until we have processed the buffers. The
1378 * scheduling call may fail if the poll routine
1379 * is already scheduled, so disable interrupts
1382 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1383 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1384 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1386 if (napi_schedule_prep(&queue->napi)) {
1387 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1388 __napi_schedule(&queue->napi);
1392 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1393 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1394 schedule_work(&queue->tx_error_task);
1396 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1397 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1402 if (status & MACB_BIT(TCOMP))
1403 macb_tx_interrupt(queue);
1405 if (status & MACB_BIT(TXUBR))
1406 macb_tx_restart(queue);
1408 /* Link change detection isn't possible with RMII, so we'll
1409 * add that if/when we get our hands on a full-blown MII PHY.
1412 /* There is a hardware issue under heavy load where DMA can
1413 * stop, this causes endless "used buffer descriptor read"
1414 * interrupts but it can be cleared by re-enabling RX. See
1415 * the at91 manual, section 41.3.1 or the Zynq manual
1416 * section 16.7.4 for details.
1418 if (status & MACB_BIT(RXUBR)) {
1419 ctrl = macb_readl(bp, NCR);
1420 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1422 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1424 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1425 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1428 if (status & MACB_BIT(ISR_ROVR)) {
1429 /* We missed at least one packet */
1430 if (macb_is_gem(bp))
1431 bp->hw_stats.gem.rx_overruns++;
1433 bp->hw_stats.macb.rx_overruns++;
1435 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1436 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1439 if (status & MACB_BIT(HRESP)) {
1440 tasklet_schedule(&bp->hresp_err_tasklet);
1441 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1443 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1444 queue_writel(queue, ISR, MACB_BIT(HRESP));
1446 status = queue_readl(queue, ISR);
1449 spin_unlock(&bp->lock);
1454 #ifdef CONFIG_NET_POLL_CONTROLLER
1455 /* Polling receive - used by netconsole and other diagnostic tools
1456 * to allow network i/o with interrupts disabled.
1458 static void macb_poll_controller(struct net_device *dev)
1460 struct macb *bp = netdev_priv(dev);
1461 struct macb_queue *queue;
1462 unsigned long flags;
1465 local_irq_save(flags);
1466 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1467 macb_interrupt(dev->irq, queue);
1468 local_irq_restore(flags);
1472 static unsigned int macb_tx_map(struct macb *bp,
1473 struct macb_queue *queue,
1474 struct sk_buff *skb,
1475 unsigned int hdrlen)
1478 unsigned int len, entry, i, tx_head = queue->tx_head;
1479 struct macb_tx_skb *tx_skb = NULL;
1480 struct macb_dma_desc *desc;
1481 unsigned int offset, size, count = 0;
1482 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1483 unsigned int eof = 1, mss_mfs = 0;
1484 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1487 if (skb_shinfo(skb)->gso_size != 0) {
1488 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1490 lso_ctrl = MACB_LSO_UFO_ENABLE;
1493 lso_ctrl = MACB_LSO_TSO_ENABLE;
1496 /* First, map non-paged data */
1497 len = skb_headlen(skb);
1499 /* first buffer length */
1504 entry = macb_tx_ring_wrap(bp, tx_head);
1505 tx_skb = &queue->tx_skb[entry];
1507 mapping = dma_map_single(&bp->pdev->dev,
1509 size, DMA_TO_DEVICE);
1510 if (dma_mapping_error(&bp->pdev->dev, mapping))
1513 /* Save info to properly release resources */
1515 tx_skb->mapping = mapping;
1516 tx_skb->size = size;
1517 tx_skb->mapped_as_page = false;
1524 size = min(len, bp->max_tx_length);
1527 /* Then, map paged data from fragments */
1528 for (f = 0; f < nr_frags; f++) {
1529 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1531 len = skb_frag_size(frag);
1534 size = min(len, bp->max_tx_length);
1535 entry = macb_tx_ring_wrap(bp, tx_head);
1536 tx_skb = &queue->tx_skb[entry];
1538 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1539 offset, size, DMA_TO_DEVICE);
1540 if (dma_mapping_error(&bp->pdev->dev, mapping))
1543 /* Save info to properly release resources */
1545 tx_skb->mapping = mapping;
1546 tx_skb->size = size;
1547 tx_skb->mapped_as_page = true;
1556 /* Should never happen */
1557 if (unlikely(!tx_skb)) {
1558 netdev_err(bp->dev, "BUG! empty skb!\n");
1562 /* This is the last buffer of the frame: save socket buffer */
1565 /* Update TX ring: update buffer descriptors in reverse order
1566 * to avoid race condition
1569 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1570 * to set the end of TX queue
1573 entry = macb_tx_ring_wrap(bp, i);
1574 ctrl = MACB_BIT(TX_USED);
1575 desc = macb_tx_desc(queue, entry);
1579 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1580 /* include header and FCS in value given to h/w */
1581 mss_mfs = skb_shinfo(skb)->gso_size +
1582 skb_transport_offset(skb) +
1585 mss_mfs = skb_shinfo(skb)->gso_size;
1586 /* TCP Sequence Number Source Select
1587 * can be set only for TSO
1595 entry = macb_tx_ring_wrap(bp, i);
1596 tx_skb = &queue->tx_skb[entry];
1597 desc = macb_tx_desc(queue, entry);
1599 ctrl = (u32)tx_skb->size;
1601 ctrl |= MACB_BIT(TX_LAST);
1604 if (unlikely(entry == (bp->tx_ring_size - 1)))
1605 ctrl |= MACB_BIT(TX_WRAP);
1607 /* First descriptor is header descriptor */
1608 if (i == queue->tx_head) {
1609 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1610 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1611 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1612 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1613 ctrl |= MACB_BIT(TX_NOCRC);
1615 /* Only set MSS/MFS on payload descriptors
1616 * (second or later descriptor)
1618 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1620 /* Set TX buffer descriptor */
1621 macb_set_addr(bp, desc, tx_skb->mapping);
1622 /* desc->addr must be visible to hardware before clearing
1623 * 'TX_USED' bit in desc->ctrl.
1627 } while (i != queue->tx_head);
1629 queue->tx_head = tx_head;
1634 netdev_err(bp->dev, "TX DMA map failed\n");
1636 for (i = queue->tx_head; i != tx_head; i++) {
1637 tx_skb = macb_tx_skb(queue, i);
1639 macb_tx_unmap(bp, tx_skb);
1645 static netdev_features_t macb_features_check(struct sk_buff *skb,
1646 struct net_device *dev,
1647 netdev_features_t features)
1649 unsigned int nr_frags, f;
1650 unsigned int hdrlen;
1652 /* Validate LSO compatibility */
1654 /* there is only one buffer */
1655 if (!skb_is_nonlinear(skb))
1658 /* length of header */
1659 hdrlen = skb_transport_offset(skb);
1660 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1661 hdrlen += tcp_hdrlen(skb);
1664 * When software supplies two or more payload buffers all payload buffers
1665 * apart from the last must be a multiple of 8 bytes in size.
1667 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1668 return features & ~MACB_NETIF_LSO;
1670 nr_frags = skb_shinfo(skb)->nr_frags;
1671 /* No need to check last fragment */
1673 for (f = 0; f < nr_frags; f++) {
1674 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1676 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1677 return features & ~MACB_NETIF_LSO;
1682 static inline int macb_clear_csum(struct sk_buff *skb)
1684 /* no change for packets without checksum offloading */
1685 if (skb->ip_summed != CHECKSUM_PARTIAL)
1688 /* make sure we can modify the header */
1689 if (unlikely(skb_cow_head(skb, 0)))
1692 /* initialize checksum field
1693 * This is required - at least for Zynq, which otherwise calculates
1694 * wrong UDP header checksums for UDP packets with UDP data len <=2
1696 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1700 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1702 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1703 int padlen = ETH_ZLEN - (*skb)->len;
1704 int headroom = skb_headroom(*skb);
1705 int tailroom = skb_tailroom(*skb);
1706 struct sk_buff *nskb;
1709 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1710 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1711 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1715 /* FCS could be appeded to tailroom. */
1716 if (tailroom >= ETH_FCS_LEN)
1718 /* FCS could be appeded by moving data to headroom. */
1719 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1721 /* No room for FCS, need to reallocate skb. */
1723 padlen = ETH_FCS_LEN;
1725 /* Add room for FCS. */
1726 padlen += ETH_FCS_LEN;
1729 if (!cloned && headroom + tailroom >= padlen) {
1730 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1731 skb_set_tail_pointer(*skb, (*skb)->len);
1733 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1737 dev_kfree_skb_any(*skb);
1742 if (padlen >= ETH_FCS_LEN)
1743 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1745 skb_trim(*skb, ETH_FCS_LEN - padlen);
1749 /* set FCS to packet */
1750 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1753 skb_put_u8(*skb, fcs & 0xff);
1754 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1755 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1756 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1761 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1763 u16 queue_index = skb_get_queue_mapping(skb);
1764 struct macb *bp = netdev_priv(dev);
1765 struct macb_queue *queue = &bp->queues[queue_index];
1766 unsigned long flags;
1767 unsigned int desc_cnt, nr_frags, frag_size, f;
1768 unsigned int hdrlen;
1769 bool is_lso, is_udp = 0;
1770 netdev_tx_t ret = NETDEV_TX_OK;
1772 if (macb_clear_csum(skb)) {
1773 dev_kfree_skb_any(skb);
1777 if (macb_pad_and_fcs(&skb, dev)) {
1778 dev_kfree_skb_any(skb);
1782 is_lso = (skb_shinfo(skb)->gso_size != 0);
1785 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1787 /* length of headers */
1789 /* only queue eth + ip headers separately for UDP */
1790 hdrlen = skb_transport_offset(skb);
1792 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1793 if (skb_headlen(skb) < hdrlen) {
1794 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1795 /* if this is required, would need to copy to single buffer */
1796 return NETDEV_TX_BUSY;
1799 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1801 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1802 netdev_vdbg(bp->dev,
1803 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1804 queue_index, skb->len, skb->head, skb->data,
1805 skb_tail_pointer(skb), skb_end_pointer(skb));
1806 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1807 skb->data, 16, true);
1810 /* Count how many TX buffer descriptors are needed to send this
1811 * socket buffer: skb fragments of jumbo frames may need to be
1812 * split into many buffer descriptors.
1814 if (is_lso && (skb_headlen(skb) > hdrlen))
1815 /* extra header descriptor if also payload in first buffer */
1816 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1818 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1819 nr_frags = skb_shinfo(skb)->nr_frags;
1820 for (f = 0; f < nr_frags; f++) {
1821 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1822 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1825 spin_lock_irqsave(&bp->lock, flags);
1827 /* This is a hard error, log it. */
1828 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1829 bp->tx_ring_size) < desc_cnt) {
1830 netif_stop_subqueue(dev, queue_index);
1831 spin_unlock_irqrestore(&bp->lock, flags);
1832 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1833 queue->tx_head, queue->tx_tail);
1834 return NETDEV_TX_BUSY;
1837 /* Map socket buffer for DMA transfer */
1838 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1839 dev_kfree_skb_any(skb);
1843 /* Make newly initialized descriptor visible to hardware */
1845 skb_tx_timestamp(skb);
1847 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1849 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1850 netif_stop_subqueue(dev, queue_index);
1853 spin_unlock_irqrestore(&bp->lock, flags);
1858 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1860 if (!macb_is_gem(bp)) {
1861 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1863 bp->rx_buffer_size = size;
1865 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1867 "RX buffer must be multiple of %d bytes, expanding\n",
1868 RX_BUFFER_MULTIPLE);
1869 bp->rx_buffer_size =
1870 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1874 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1875 bp->dev->mtu, bp->rx_buffer_size);
1878 static void gem_free_rx_buffers(struct macb *bp)
1880 struct sk_buff *skb;
1881 struct macb_dma_desc *desc;
1882 struct macb_queue *queue;
1887 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1888 if (!queue->rx_skbuff)
1891 for (i = 0; i < bp->rx_ring_size; i++) {
1892 skb = queue->rx_skbuff[i];
1897 desc = macb_rx_desc(queue, i);
1898 addr = macb_get_addr(bp, desc);
1900 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1902 dev_kfree_skb_any(skb);
1906 kfree(queue->rx_skbuff);
1907 queue->rx_skbuff = NULL;
1911 static void macb_free_rx_buffers(struct macb *bp)
1913 struct macb_queue *queue = &bp->queues[0];
1915 if (queue->rx_buffers) {
1916 dma_free_coherent(&bp->pdev->dev,
1917 bp->rx_ring_size * bp->rx_buffer_size,
1918 queue->rx_buffers, queue->rx_buffers_dma);
1919 queue->rx_buffers = NULL;
1923 static void macb_free_consistent(struct macb *bp)
1925 struct macb_queue *queue;
1929 bp->macbgem_ops.mog_free_rx_buffers(bp);
1931 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1932 kfree(queue->tx_skb);
1933 queue->tx_skb = NULL;
1934 if (queue->tx_ring) {
1935 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1936 dma_free_coherent(&bp->pdev->dev, size,
1937 queue->tx_ring, queue->tx_ring_dma);
1938 queue->tx_ring = NULL;
1940 if (queue->rx_ring) {
1941 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
1942 dma_free_coherent(&bp->pdev->dev, size,
1943 queue->rx_ring, queue->rx_ring_dma);
1944 queue->rx_ring = NULL;
1949 static int gem_alloc_rx_buffers(struct macb *bp)
1951 struct macb_queue *queue;
1955 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1956 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1957 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
1958 if (!queue->rx_skbuff)
1962 "Allocated %d RX struct sk_buff entries at %p\n",
1963 bp->rx_ring_size, queue->rx_skbuff);
1968 static int macb_alloc_rx_buffers(struct macb *bp)
1970 struct macb_queue *queue = &bp->queues[0];
1973 size = bp->rx_ring_size * bp->rx_buffer_size;
1974 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1975 &queue->rx_buffers_dma, GFP_KERNEL);
1976 if (!queue->rx_buffers)
1980 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1981 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
1985 static int macb_alloc_consistent(struct macb *bp)
1987 struct macb_queue *queue;
1991 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1992 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1993 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1994 &queue->tx_ring_dma,
1996 if (!queue->tx_ring)
1999 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2000 q, size, (unsigned long)queue->tx_ring_dma,
2003 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2004 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2008 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2009 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2010 &queue->rx_ring_dma, GFP_KERNEL);
2011 if (!queue->rx_ring)
2014 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2015 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2017 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2023 macb_free_consistent(bp);
2027 static void gem_init_rings(struct macb *bp)
2029 struct macb_queue *queue;
2030 struct macb_dma_desc *desc = NULL;
2034 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2035 for (i = 0; i < bp->tx_ring_size; i++) {
2036 desc = macb_tx_desc(queue, i);
2037 macb_set_addr(bp, desc, 0);
2038 desc->ctrl = MACB_BIT(TX_USED);
2040 desc->ctrl |= MACB_BIT(TX_WRAP);
2045 queue->rx_prepared_head = 0;
2047 gem_rx_refill(queue);
2052 static void macb_init_rings(struct macb *bp)
2055 struct macb_dma_desc *desc = NULL;
2057 macb_init_rx_ring(&bp->queues[0]);
2059 for (i = 0; i < bp->tx_ring_size; i++) {
2060 desc = macb_tx_desc(&bp->queues[0], i);
2061 macb_set_addr(bp, desc, 0);
2062 desc->ctrl = MACB_BIT(TX_USED);
2064 bp->queues[0].tx_head = 0;
2065 bp->queues[0].tx_tail = 0;
2066 desc->ctrl |= MACB_BIT(TX_WRAP);
2069 static void macb_reset_hw(struct macb *bp)
2071 struct macb_queue *queue;
2073 u32 ctrl = macb_readl(bp, NCR);
2075 /* Disable RX and TX (XXX: Should we halt the transmission
2078 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2080 /* Clear the stats registers (XXX: Update stats first?) */
2081 ctrl |= MACB_BIT(CLRSTAT);
2083 macb_writel(bp, NCR, ctrl);
2085 /* Clear all status flags */
2086 macb_writel(bp, TSR, -1);
2087 macb_writel(bp, RSR, -1);
2089 /* Disable all interrupts */
2090 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2091 queue_writel(queue, IDR, -1);
2092 queue_readl(queue, ISR);
2093 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2094 queue_writel(queue, ISR, -1);
2098 static u32 gem_mdc_clk_div(struct macb *bp)
2101 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2103 if (pclk_hz <= 20000000)
2104 config = GEM_BF(CLK, GEM_CLK_DIV8);
2105 else if (pclk_hz <= 40000000)
2106 config = GEM_BF(CLK, GEM_CLK_DIV16);
2107 else if (pclk_hz <= 80000000)
2108 config = GEM_BF(CLK, GEM_CLK_DIV32);
2109 else if (pclk_hz <= 120000000)
2110 config = GEM_BF(CLK, GEM_CLK_DIV48);
2111 else if (pclk_hz <= 160000000)
2112 config = GEM_BF(CLK, GEM_CLK_DIV64);
2114 config = GEM_BF(CLK, GEM_CLK_DIV96);
2119 static u32 macb_mdc_clk_div(struct macb *bp)
2122 unsigned long pclk_hz;
2124 if (macb_is_gem(bp))
2125 return gem_mdc_clk_div(bp);
2127 pclk_hz = clk_get_rate(bp->pclk);
2128 if (pclk_hz <= 20000000)
2129 config = MACB_BF(CLK, MACB_CLK_DIV8);
2130 else if (pclk_hz <= 40000000)
2131 config = MACB_BF(CLK, MACB_CLK_DIV16);
2132 else if (pclk_hz <= 80000000)
2133 config = MACB_BF(CLK, MACB_CLK_DIV32);
2135 config = MACB_BF(CLK, MACB_CLK_DIV64);
2140 /* Get the DMA bus width field of the network configuration register that we
2141 * should program. We find the width from decoding the design configuration
2142 * register to find the maximum supported data bus width.
2144 static u32 macb_dbw(struct macb *bp)
2146 if (!macb_is_gem(bp))
2149 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2151 return GEM_BF(DBW, GEM_DBW128);
2153 return GEM_BF(DBW, GEM_DBW64);
2156 return GEM_BF(DBW, GEM_DBW32);
2160 /* Configure the receive DMA engine
2161 * - use the correct receive buffer size
2162 * - set best burst length for DMA operations
2163 * (if not supported by FIFO, it will fallback to default)
2164 * - set both rx/tx packet buffers to full memory size
2165 * These are configurable parameters for GEM.
2167 static void macb_configure_dma(struct macb *bp)
2169 struct macb_queue *queue;
2174 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2175 if (macb_is_gem(bp)) {
2176 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2177 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2179 queue_writel(queue, RBQS, buffer_size);
2181 dmacfg |= GEM_BF(RXBS, buffer_size);
2183 if (bp->dma_burst_length)
2184 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2185 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2186 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2189 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2191 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2193 if (bp->dev->features & NETIF_F_HW_CSUM)
2194 dmacfg |= GEM_BIT(TXCOEN);
2196 dmacfg &= ~GEM_BIT(TXCOEN);
2198 dmacfg &= ~GEM_BIT(ADDR64);
2199 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2200 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2201 dmacfg |= GEM_BIT(ADDR64);
2203 #ifdef CONFIG_MACB_USE_HWSTAMP
2204 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2205 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2207 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2209 gem_writel(bp, DMACFG, dmacfg);
2213 static void macb_init_hw(struct macb *bp)
2215 struct macb_queue *queue;
2221 macb_set_hwaddr(bp);
2223 config = macb_mdc_clk_div(bp);
2224 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2225 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2226 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2227 config |= MACB_BIT(PAE); /* PAuse Enable */
2228 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2229 if (bp->caps & MACB_CAPS_JUMBO)
2230 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2232 config |= MACB_BIT(BIG); /* Receive oversized frames */
2233 if (bp->dev->flags & IFF_PROMISC)
2234 config |= MACB_BIT(CAF); /* Copy All Frames */
2235 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2236 config |= GEM_BIT(RXCOEN);
2237 if (!(bp->dev->flags & IFF_BROADCAST))
2238 config |= MACB_BIT(NBC); /* No BroadCast */
2239 config |= macb_dbw(bp);
2240 macb_writel(bp, NCFGR, config);
2241 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2242 gem_writel(bp, JML, bp->jumbo_max_len);
2243 bp->speed = SPEED_10;
2244 bp->duplex = DUPLEX_HALF;
2245 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2246 if (bp->caps & MACB_CAPS_JUMBO)
2247 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2249 macb_configure_dma(bp);
2251 /* Initialize TX and RX buffers */
2252 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2253 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
2254 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2255 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2256 queue_writel(queue, RBQPH, upper_32_bits(queue->rx_ring_dma));
2258 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2259 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2260 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2261 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2264 /* Enable interrupts */
2265 queue_writel(queue, IER,
2271 /* Enable TX and RX */
2272 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
2275 /* The hash address register is 64 bits long and takes up two
2276 * locations in the memory map. The least significant bits are stored
2277 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2279 * The unicast hash enable and the multicast hash enable bits in the
2280 * network configuration register enable the reception of hash matched
2281 * frames. The destination address is reduced to a 6 bit index into
2282 * the 64 bit hash register using the following hash function. The
2283 * hash function is an exclusive or of every sixth bit of the
2284 * destination address.
2286 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2287 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2288 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2289 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2290 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2291 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2293 * da[0] represents the least significant bit of the first byte
2294 * received, that is, the multicast/unicast indicator, and da[47]
2295 * represents the most significant bit of the last byte received. If
2296 * the hash index, hi[n], points to a bit that is set in the hash
2297 * register then the frame will be matched according to whether the
2298 * frame is multicast or unicast. A multicast match will be signalled
2299 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2300 * index points to a bit set in the hash register. A unicast match
2301 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2302 * and the hash index points to a bit set in the hash register. To
2303 * receive all multicast frames, the hash register should be set with
2304 * all ones and the multicast hash enable bit should be set in the
2305 * network configuration register.
2308 static inline int hash_bit_value(int bitnr, __u8 *addr)
2310 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2315 /* Return the hash index value for the specified address. */
2316 static int hash_get_index(__u8 *addr)
2321 for (j = 0; j < 6; j++) {
2322 for (i = 0, bitval = 0; i < 8; i++)
2323 bitval ^= hash_bit_value(i * 6 + j, addr);
2325 hash_index |= (bitval << j);
2331 /* Add multicast addresses to the internal multicast-hash table. */
2332 static void macb_sethashtable(struct net_device *dev)
2334 struct netdev_hw_addr *ha;
2335 unsigned long mc_filter[2];
2337 struct macb *bp = netdev_priv(dev);
2342 netdev_for_each_mc_addr(ha, dev) {
2343 bitnr = hash_get_index(ha->addr);
2344 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2347 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2348 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2351 /* Enable/Disable promiscuous and multicast modes. */
2352 static void macb_set_rx_mode(struct net_device *dev)
2355 struct macb *bp = netdev_priv(dev);
2357 cfg = macb_readl(bp, NCFGR);
2359 if (dev->flags & IFF_PROMISC) {
2360 /* Enable promiscuous mode */
2361 cfg |= MACB_BIT(CAF);
2363 /* Disable RX checksum offload */
2364 if (macb_is_gem(bp))
2365 cfg &= ~GEM_BIT(RXCOEN);
2367 /* Disable promiscuous mode */
2368 cfg &= ~MACB_BIT(CAF);
2370 /* Enable RX checksum offload only if requested */
2371 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2372 cfg |= GEM_BIT(RXCOEN);
2375 if (dev->flags & IFF_ALLMULTI) {
2376 /* Enable all multicast mode */
2377 macb_or_gem_writel(bp, HRB, -1);
2378 macb_or_gem_writel(bp, HRT, -1);
2379 cfg |= MACB_BIT(NCFGR_MTI);
2380 } else if (!netdev_mc_empty(dev)) {
2381 /* Enable specific multicasts */
2382 macb_sethashtable(dev);
2383 cfg |= MACB_BIT(NCFGR_MTI);
2384 } else if (dev->flags & (~IFF_ALLMULTI)) {
2385 /* Disable all multicast mode */
2386 macb_or_gem_writel(bp, HRB, 0);
2387 macb_or_gem_writel(bp, HRT, 0);
2388 cfg &= ~MACB_BIT(NCFGR_MTI);
2391 macb_writel(bp, NCFGR, cfg);
2394 static int macb_open(struct net_device *dev)
2396 struct macb *bp = netdev_priv(dev);
2397 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2398 struct macb_queue *queue;
2402 netdev_dbg(bp->dev, "open\n");
2404 /* carrier starts down */
2405 netif_carrier_off(dev);
2407 /* if the phy is not yet register, retry later*/
2411 /* RX buffers initialization */
2412 macb_init_rx_buffer_size(bp, bufsz);
2414 err = macb_alloc_consistent(bp);
2416 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2421 bp->macbgem_ops.mog_init_rings(bp);
2424 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2425 napi_enable(&queue->napi);
2427 /* schedule a link state check */
2428 phy_start(dev->phydev);
2430 netif_tx_start_all_queues(dev);
2433 bp->ptp_info->ptp_init(dev);
2438 static int macb_close(struct net_device *dev)
2440 struct macb *bp = netdev_priv(dev);
2441 struct macb_queue *queue;
2442 unsigned long flags;
2445 netif_tx_stop_all_queues(dev);
2447 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2448 napi_disable(&queue->napi);
2451 phy_stop(dev->phydev);
2453 spin_lock_irqsave(&bp->lock, flags);
2455 netif_carrier_off(dev);
2456 spin_unlock_irqrestore(&bp->lock, flags);
2458 macb_free_consistent(bp);
2461 bp->ptp_info->ptp_remove(dev);
2466 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2468 if (netif_running(dev))
2476 static void gem_update_stats(struct macb *bp)
2478 struct macb_queue *queue;
2479 unsigned int i, q, idx;
2480 unsigned long *stat;
2482 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2484 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2485 u32 offset = gem_statistics[i].offset;
2486 u64 val = bp->macb_reg_readl(bp, offset);
2488 bp->ethtool_stats[i] += val;
2491 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2492 /* Add GEM_OCTTXH, GEM_OCTRXH */
2493 val = bp->macb_reg_readl(bp, offset + 4);
2494 bp->ethtool_stats[i] += ((u64)val) << 32;
2499 idx = GEM_STATS_LEN;
2500 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2501 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2502 bp->ethtool_stats[idx++] = *stat;
2505 static struct net_device_stats *gem_get_stats(struct macb *bp)
2507 struct gem_stats *hwstat = &bp->hw_stats.gem;
2508 struct net_device_stats *nstat = &bp->dev->stats;
2510 gem_update_stats(bp);
2512 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2513 hwstat->rx_alignment_errors +
2514 hwstat->rx_resource_errors +
2515 hwstat->rx_overruns +
2516 hwstat->rx_oversize_frames +
2517 hwstat->rx_jabbers +
2518 hwstat->rx_undersized_frames +
2519 hwstat->rx_length_field_frame_errors);
2520 nstat->tx_errors = (hwstat->tx_late_collisions +
2521 hwstat->tx_excessive_collisions +
2522 hwstat->tx_underrun +
2523 hwstat->tx_carrier_sense_errors);
2524 nstat->multicast = hwstat->rx_multicast_frames;
2525 nstat->collisions = (hwstat->tx_single_collision_frames +
2526 hwstat->tx_multiple_collision_frames +
2527 hwstat->tx_excessive_collisions);
2528 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2529 hwstat->rx_jabbers +
2530 hwstat->rx_undersized_frames +
2531 hwstat->rx_length_field_frame_errors);
2532 nstat->rx_over_errors = hwstat->rx_resource_errors;
2533 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2534 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2535 nstat->rx_fifo_errors = hwstat->rx_overruns;
2536 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2537 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2538 nstat->tx_fifo_errors = hwstat->tx_underrun;
2543 static void gem_get_ethtool_stats(struct net_device *dev,
2544 struct ethtool_stats *stats, u64 *data)
2548 bp = netdev_priv(dev);
2549 gem_update_stats(bp);
2550 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2551 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2554 static int gem_get_sset_count(struct net_device *dev, int sset)
2556 struct macb *bp = netdev_priv(dev);
2560 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2566 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2568 char stat_string[ETH_GSTRING_LEN];
2569 struct macb *bp = netdev_priv(dev);
2570 struct macb_queue *queue;
2576 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2577 memcpy(p, gem_statistics[i].stat_string,
2580 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2581 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2582 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2583 q, queue_statistics[i].stat_string);
2584 memcpy(p, stat_string, ETH_GSTRING_LEN);
2591 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2593 struct macb *bp = netdev_priv(dev);
2594 struct net_device_stats *nstat = &bp->dev->stats;
2595 struct macb_stats *hwstat = &bp->hw_stats.macb;
2597 if (macb_is_gem(bp))
2598 return gem_get_stats(bp);
2600 /* read stats from hardware */
2601 macb_update_stats(bp);
2603 /* Convert HW stats into netdevice stats */
2604 nstat->rx_errors = (hwstat->rx_fcs_errors +
2605 hwstat->rx_align_errors +
2606 hwstat->rx_resource_errors +
2607 hwstat->rx_overruns +
2608 hwstat->rx_oversize_pkts +
2609 hwstat->rx_jabbers +
2610 hwstat->rx_undersize_pkts +
2611 hwstat->rx_length_mismatch);
2612 nstat->tx_errors = (hwstat->tx_late_cols +
2613 hwstat->tx_excessive_cols +
2614 hwstat->tx_underruns +
2615 hwstat->tx_carrier_errors +
2616 hwstat->sqe_test_errors);
2617 nstat->collisions = (hwstat->tx_single_cols +
2618 hwstat->tx_multiple_cols +
2619 hwstat->tx_excessive_cols);
2620 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2621 hwstat->rx_jabbers +
2622 hwstat->rx_undersize_pkts +
2623 hwstat->rx_length_mismatch);
2624 nstat->rx_over_errors = hwstat->rx_resource_errors +
2625 hwstat->rx_overruns;
2626 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2627 nstat->rx_frame_errors = hwstat->rx_align_errors;
2628 nstat->rx_fifo_errors = hwstat->rx_overruns;
2629 /* XXX: What does "missed" mean? */
2630 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2631 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2632 nstat->tx_fifo_errors = hwstat->tx_underruns;
2633 /* Don't know about heartbeat or window errors... */
2638 static int macb_get_regs_len(struct net_device *netdev)
2640 return MACB_GREGS_NBR * sizeof(u32);
2643 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2646 struct macb *bp = netdev_priv(dev);
2647 unsigned int tail, head;
2650 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2651 | MACB_GREGS_VERSION;
2653 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2654 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2656 regs_buff[0] = macb_readl(bp, NCR);
2657 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2658 regs_buff[2] = macb_readl(bp, NSR);
2659 regs_buff[3] = macb_readl(bp, TSR);
2660 regs_buff[4] = macb_readl(bp, RBQP);
2661 regs_buff[5] = macb_readl(bp, TBQP);
2662 regs_buff[6] = macb_readl(bp, RSR);
2663 regs_buff[7] = macb_readl(bp, IMR);
2665 regs_buff[8] = tail;
2666 regs_buff[9] = head;
2667 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2668 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2670 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2671 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2672 if (macb_is_gem(bp))
2673 regs_buff[13] = gem_readl(bp, DMACFG);
2676 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2678 struct macb *bp = netdev_priv(netdev);
2683 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2684 wol->supported = WAKE_MAGIC;
2686 if (bp->wol & MACB_WOL_ENABLED)
2687 wol->wolopts |= WAKE_MAGIC;
2691 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2693 struct macb *bp = netdev_priv(netdev);
2695 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2696 (wol->wolopts & ~WAKE_MAGIC))
2699 if (wol->wolopts & WAKE_MAGIC)
2700 bp->wol |= MACB_WOL_ENABLED;
2702 bp->wol &= ~MACB_WOL_ENABLED;
2704 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2709 static void macb_get_ringparam(struct net_device *netdev,
2710 struct ethtool_ringparam *ring)
2712 struct macb *bp = netdev_priv(netdev);
2714 ring->rx_max_pending = MAX_RX_RING_SIZE;
2715 ring->tx_max_pending = MAX_TX_RING_SIZE;
2717 ring->rx_pending = bp->rx_ring_size;
2718 ring->tx_pending = bp->tx_ring_size;
2721 static int macb_set_ringparam(struct net_device *netdev,
2722 struct ethtool_ringparam *ring)
2724 struct macb *bp = netdev_priv(netdev);
2725 u32 new_rx_size, new_tx_size;
2726 unsigned int reset = 0;
2728 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2731 new_rx_size = clamp_t(u32, ring->rx_pending,
2732 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2733 new_rx_size = roundup_pow_of_two(new_rx_size);
2735 new_tx_size = clamp_t(u32, ring->tx_pending,
2736 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2737 new_tx_size = roundup_pow_of_two(new_tx_size);
2739 if ((new_tx_size == bp->tx_ring_size) &&
2740 (new_rx_size == bp->rx_ring_size)) {
2745 if (netif_running(bp->dev)) {
2747 macb_close(bp->dev);
2750 bp->rx_ring_size = new_rx_size;
2751 bp->tx_ring_size = new_tx_size;
2759 #ifdef CONFIG_MACB_USE_HWSTAMP
2760 static unsigned int gem_get_tsu_rate(struct macb *bp)
2762 struct clk *tsu_clk;
2763 unsigned int tsu_rate;
2765 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2766 if (!IS_ERR(tsu_clk))
2767 tsu_rate = clk_get_rate(tsu_clk);
2768 /* try pclk instead */
2769 else if (!IS_ERR(bp->pclk)) {
2771 tsu_rate = clk_get_rate(tsu_clk);
2777 static s32 gem_get_ptp_max_adj(void)
2782 static int gem_get_ts_info(struct net_device *dev,
2783 struct ethtool_ts_info *info)
2785 struct macb *bp = netdev_priv(dev);
2787 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2788 ethtool_op_get_ts_info(dev, info);
2792 info->so_timestamping =
2793 SOF_TIMESTAMPING_TX_SOFTWARE |
2794 SOF_TIMESTAMPING_RX_SOFTWARE |
2795 SOF_TIMESTAMPING_SOFTWARE |
2796 SOF_TIMESTAMPING_TX_HARDWARE |
2797 SOF_TIMESTAMPING_RX_HARDWARE |
2798 SOF_TIMESTAMPING_RAW_HARDWARE;
2800 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2801 (1 << HWTSTAMP_TX_OFF) |
2802 (1 << HWTSTAMP_TX_ON);
2804 (1 << HWTSTAMP_FILTER_NONE) |
2805 (1 << HWTSTAMP_FILTER_ALL);
2807 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2812 static struct macb_ptp_info gem_ptp_info = {
2813 .ptp_init = gem_ptp_init,
2814 .ptp_remove = gem_ptp_remove,
2815 .get_ptp_max_adj = gem_get_ptp_max_adj,
2816 .get_tsu_rate = gem_get_tsu_rate,
2817 .get_ts_info = gem_get_ts_info,
2818 .get_hwtst = gem_get_hwtst,
2819 .set_hwtst = gem_set_hwtst,
2823 static int macb_get_ts_info(struct net_device *netdev,
2824 struct ethtool_ts_info *info)
2826 struct macb *bp = netdev_priv(netdev);
2829 return bp->ptp_info->get_ts_info(netdev, info);
2831 return ethtool_op_get_ts_info(netdev, info);
2834 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2836 struct ethtool_rx_fs_item *item;
2840 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2842 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2843 struct ethtool_rx_flow_spec *fs = &item->fs;
2844 struct ethtool_tcpip4_spec *tp4sp_m;
2846 if (fs->location >= num_t2_scr)
2849 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2851 /* enable/disable screener regs for the flow entry */
2852 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2854 /* only enable fields with no masking */
2855 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2857 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2858 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2860 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2862 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2863 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2865 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2867 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
2868 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
2870 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
2872 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
2876 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
2878 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
2879 uint16_t index = fs->location;
2885 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
2886 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2888 /* ignore field if any masking set */
2889 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
2890 /* 1st compare reg - IP source address */
2893 w0 = tp4sp_v->ip4src;
2894 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2895 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2896 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
2897 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
2898 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
2902 /* ignore field if any masking set */
2903 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
2904 /* 2nd compare reg - IP destination address */
2907 w0 = tp4sp_v->ip4dst;
2908 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2909 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2910 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
2911 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
2912 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
2916 /* ignore both port fields if masking set in both */
2917 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
2918 /* 3rd compare reg - source port, destination port */
2921 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
2922 if (tp4sp_m->psrc == tp4sp_m->pdst) {
2923 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
2924 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2925 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2926 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2928 /* only one port definition */
2929 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
2930 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
2931 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
2932 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
2933 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2934 } else { /* dst port */
2935 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2936 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
2939 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
2940 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
2945 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
2946 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
2948 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
2950 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
2952 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
2953 gem_writel_n(bp, SCRT2, index, t2_scr);
2956 static int gem_add_flow_filter(struct net_device *netdev,
2957 struct ethtool_rxnfc *cmd)
2959 struct macb *bp = netdev_priv(netdev);
2960 struct ethtool_rx_flow_spec *fs = &cmd->fs;
2961 struct ethtool_rx_fs_item *item, *newfs;
2962 unsigned long flags;
2966 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
2969 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
2972 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
2973 fs->flow_type, (int)fs->ring_cookie, fs->location,
2974 htonl(fs->h_u.tcp_ip4_spec.ip4src),
2975 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
2976 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
2978 spin_lock_irqsave(&bp->rx_fs_lock, flags);
2980 /* find correct place to add in list */
2981 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2982 if (item->fs.location > newfs->fs.location) {
2983 list_add_tail(&newfs->list, &item->list);
2986 } else if (item->fs.location == fs->location) {
2987 netdev_err(netdev, "Rule not added: location %d not free!\n",
2994 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
2996 gem_prog_cmp_regs(bp, fs);
2997 bp->rx_fs_list.count++;
2998 /* enable filtering if NTUPLE on */
2999 if (netdev->features & NETIF_F_NTUPLE)
3000 gem_enable_flow_filters(bp, 1);
3002 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3006 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3011 static int gem_del_flow_filter(struct net_device *netdev,
3012 struct ethtool_rxnfc *cmd)
3014 struct macb *bp = netdev_priv(netdev);
3015 struct ethtool_rx_fs_item *item;
3016 struct ethtool_rx_flow_spec *fs;
3017 unsigned long flags;
3019 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3021 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3022 if (item->fs.location == cmd->fs.location) {
3023 /* disable screener regs for the flow entry */
3026 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3027 fs->flow_type, (int)fs->ring_cookie, fs->location,
3028 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3029 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3030 htons(fs->h_u.tcp_ip4_spec.psrc),
3031 htons(fs->h_u.tcp_ip4_spec.pdst));
3033 gem_writel_n(bp, SCRT2, fs->location, 0);
3035 list_del(&item->list);
3036 bp->rx_fs_list.count--;
3037 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3043 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3047 static int gem_get_flow_entry(struct net_device *netdev,
3048 struct ethtool_rxnfc *cmd)
3050 struct macb *bp = netdev_priv(netdev);
3051 struct ethtool_rx_fs_item *item;
3053 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3054 if (item->fs.location == cmd->fs.location) {
3055 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3062 static int gem_get_all_flow_entries(struct net_device *netdev,
3063 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3065 struct macb *bp = netdev_priv(netdev);
3066 struct ethtool_rx_fs_item *item;
3069 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3070 if (cnt == cmd->rule_cnt)
3072 rule_locs[cnt] = item->fs.location;
3075 cmd->data = bp->max_tuples;
3076 cmd->rule_cnt = cnt;
3081 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3084 struct macb *bp = netdev_priv(netdev);
3088 case ETHTOOL_GRXRINGS:
3089 cmd->data = bp->num_queues;
3091 case ETHTOOL_GRXCLSRLCNT:
3092 cmd->rule_cnt = bp->rx_fs_list.count;
3094 case ETHTOOL_GRXCLSRULE:
3095 ret = gem_get_flow_entry(netdev, cmd);
3097 case ETHTOOL_GRXCLSRLALL:
3098 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3102 "Command parameter %d is not supported\n", cmd->cmd);
3109 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3111 struct macb *bp = netdev_priv(netdev);
3115 case ETHTOOL_SRXCLSRLINS:
3116 if ((cmd->fs.location >= bp->max_tuples)
3117 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3121 ret = gem_add_flow_filter(netdev, cmd);
3123 case ETHTOOL_SRXCLSRLDEL:
3124 ret = gem_del_flow_filter(netdev, cmd);
3128 "Command parameter %d is not supported\n", cmd->cmd);
3135 static const struct ethtool_ops macb_ethtool_ops = {
3136 .get_regs_len = macb_get_regs_len,
3137 .get_regs = macb_get_regs,
3138 .get_link = ethtool_op_get_link,
3139 .get_ts_info = ethtool_op_get_ts_info,
3140 .get_wol = macb_get_wol,
3141 .set_wol = macb_set_wol,
3142 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3143 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3144 .get_ringparam = macb_get_ringparam,
3145 .set_ringparam = macb_set_ringparam,
3148 static const struct ethtool_ops gem_ethtool_ops = {
3149 .get_regs_len = macb_get_regs_len,
3150 .get_regs = macb_get_regs,
3151 .get_link = ethtool_op_get_link,
3152 .get_ts_info = macb_get_ts_info,
3153 .get_ethtool_stats = gem_get_ethtool_stats,
3154 .get_strings = gem_get_ethtool_strings,
3155 .get_sset_count = gem_get_sset_count,
3156 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3157 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3158 .get_ringparam = macb_get_ringparam,
3159 .set_ringparam = macb_set_ringparam,
3160 .get_rxnfc = gem_get_rxnfc,
3161 .set_rxnfc = gem_set_rxnfc,
3164 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3166 struct phy_device *phydev = dev->phydev;
3167 struct macb *bp = netdev_priv(dev);
3169 if (!netif_running(dev))
3176 return phy_mii_ioctl(phydev, rq, cmd);
3180 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3182 return bp->ptp_info->get_hwtst(dev, rq);
3184 return phy_mii_ioctl(phydev, rq, cmd);
3188 static int macb_set_features(struct net_device *netdev,
3189 netdev_features_t features)
3191 struct macb *bp = netdev_priv(netdev);
3192 netdev_features_t changed = features ^ netdev->features;
3194 /* TX checksum offload */
3195 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
3198 dmacfg = gem_readl(bp, DMACFG);
3199 if (features & NETIF_F_HW_CSUM)
3200 dmacfg |= GEM_BIT(TXCOEN);
3202 dmacfg &= ~GEM_BIT(TXCOEN);
3203 gem_writel(bp, DMACFG, dmacfg);
3206 /* RX checksum offload */
3207 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
3210 netcfg = gem_readl(bp, NCFGR);
3211 if (features & NETIF_F_RXCSUM &&
3212 !(netdev->flags & IFF_PROMISC))
3213 netcfg |= GEM_BIT(RXCOEN);
3215 netcfg &= ~GEM_BIT(RXCOEN);
3216 gem_writel(bp, NCFGR, netcfg);
3219 /* RX Flow Filters */
3220 if ((changed & NETIF_F_NTUPLE) && macb_is_gem(bp)) {
3221 bool turn_on = features & NETIF_F_NTUPLE;
3223 gem_enable_flow_filters(bp, turn_on);
3228 static const struct net_device_ops macb_netdev_ops = {
3229 .ndo_open = macb_open,
3230 .ndo_stop = macb_close,
3231 .ndo_start_xmit = macb_start_xmit,
3232 .ndo_set_rx_mode = macb_set_rx_mode,
3233 .ndo_get_stats = macb_get_stats,
3234 .ndo_do_ioctl = macb_ioctl,
3235 .ndo_validate_addr = eth_validate_addr,
3236 .ndo_change_mtu = macb_change_mtu,
3237 .ndo_set_mac_address = eth_mac_addr,
3238 #ifdef CONFIG_NET_POLL_CONTROLLER
3239 .ndo_poll_controller = macb_poll_controller,
3241 .ndo_set_features = macb_set_features,
3242 .ndo_features_check = macb_features_check,
3245 /* Configure peripheral capabilities according to device tree
3246 * and integration options used
3248 static void macb_configure_caps(struct macb *bp,
3249 const struct macb_config *dt_conf)
3254 bp->caps = dt_conf->caps;
3256 if (hw_is_gem(bp->regs, bp->native_io)) {
3257 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3259 dcfg = gem_readl(bp, DCFG1);
3260 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3261 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3262 dcfg = gem_readl(bp, DCFG2);
3263 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3264 bp->caps |= MACB_CAPS_FIFO_MODE;
3265 #ifdef CONFIG_MACB_USE_HWSTAMP
3266 if (gem_has_ptp(bp)) {
3267 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3268 pr_err("GEM doesn't support hardware ptp.\n");
3270 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3271 bp->ptp_info = &gem_ptp_info;
3277 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3280 static void macb_probe_queues(void __iomem *mem,
3282 unsigned int *queue_mask,
3283 unsigned int *num_queues)
3290 /* is it macb or gem ?
3292 * We need to read directly from the hardware here because
3293 * we are early in the probe process and don't have the
3294 * MACB_CAPS_MACB_IS_GEM flag positioned
3296 if (!hw_is_gem(mem, native_io))
3299 /* bit 0 is never set but queue 0 always exists */
3300 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3304 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3305 if (*queue_mask & (1 << hw_q))
3309 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3310 struct clk **hclk, struct clk **tx_clk,
3311 struct clk **rx_clk)
3313 struct macb_platform_data *pdata;
3316 pdata = dev_get_platdata(&pdev->dev);
3318 *pclk = pdata->pclk;
3319 *hclk = pdata->hclk;
3321 *pclk = devm_clk_get(&pdev->dev, "pclk");
3322 *hclk = devm_clk_get(&pdev->dev, "hclk");
3325 if (IS_ERR(*pclk)) {
3326 err = PTR_ERR(*pclk);
3327 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
3331 if (IS_ERR(*hclk)) {
3332 err = PTR_ERR(*hclk);
3333 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
3337 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
3338 if (IS_ERR(*tx_clk))
3341 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
3342 if (IS_ERR(*rx_clk))
3345 err = clk_prepare_enable(*pclk);
3347 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3351 err = clk_prepare_enable(*hclk);
3353 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
3354 goto err_disable_pclk;
3357 err = clk_prepare_enable(*tx_clk);
3359 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
3360 goto err_disable_hclk;
3363 err = clk_prepare_enable(*rx_clk);
3365 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
3366 goto err_disable_txclk;
3372 clk_disable_unprepare(*tx_clk);
3375 clk_disable_unprepare(*hclk);
3378 clk_disable_unprepare(*pclk);
3383 static int macb_init(struct platform_device *pdev)
3385 struct net_device *dev = platform_get_drvdata(pdev);
3386 unsigned int hw_q, q;
3387 struct macb *bp = netdev_priv(dev);
3388 struct macb_queue *queue;
3392 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3393 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3395 /* set the queue register mapping once for all: queue0 has a special
3396 * register mapping but we don't want to test the queue index then
3397 * compute the corresponding register offset at run time.
3399 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3400 if (!(bp->queue_mask & (1 << hw_q)))
3403 queue = &bp->queues[q];
3405 netif_napi_add(dev, &queue->napi, macb_poll, 64);
3407 queue->ISR = GEM_ISR(hw_q - 1);
3408 queue->IER = GEM_IER(hw_q - 1);
3409 queue->IDR = GEM_IDR(hw_q - 1);
3410 queue->IMR = GEM_IMR(hw_q - 1);
3411 queue->TBQP = GEM_TBQP(hw_q - 1);
3412 queue->RBQP = GEM_RBQP(hw_q - 1);
3413 queue->RBQS = GEM_RBQS(hw_q - 1);
3414 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3415 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3416 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3417 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3421 /* queue0 uses legacy registers */
3422 queue->ISR = MACB_ISR;
3423 queue->IER = MACB_IER;
3424 queue->IDR = MACB_IDR;
3425 queue->IMR = MACB_IMR;
3426 queue->TBQP = MACB_TBQP;
3427 queue->RBQP = MACB_RBQP;
3428 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3429 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3430 queue->TBQPH = MACB_TBQPH;
3431 queue->RBQPH = MACB_RBQPH;
3436 /* get irq: here we use the linux queue index, not the hardware
3437 * queue index. the queue irq definitions in the device tree
3438 * must remove the optional gaps that could exist in the
3439 * hardware queue mask.
3441 queue->irq = platform_get_irq(pdev, q);
3442 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3443 IRQF_SHARED, dev->name, queue);
3446 "Unable to request IRQ %d (error %d)\n",
3451 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3455 dev->netdev_ops = &macb_netdev_ops;
3457 /* setup appropriated routines according to adapter type */
3458 if (macb_is_gem(bp)) {
3459 bp->max_tx_length = GEM_MAX_TX_LEN;
3460 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3461 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3462 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3463 bp->macbgem_ops.mog_rx = gem_rx;
3464 dev->ethtool_ops = &gem_ethtool_ops;
3466 bp->max_tx_length = MACB_MAX_TX_LEN;
3467 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3468 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3469 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3470 bp->macbgem_ops.mog_rx = macb_rx;
3471 dev->ethtool_ops = &macb_ethtool_ops;
3475 dev->hw_features = NETIF_F_SG;
3477 /* Check LSO capability */
3478 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3479 dev->hw_features |= MACB_NETIF_LSO;
3481 /* Checksum offload is only available on gem with packet buffer */
3482 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3483 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3484 if (bp->caps & MACB_CAPS_SG_DISABLED)
3485 dev->hw_features &= ~NETIF_F_SG;
3486 dev->features = dev->hw_features;
3488 /* Check RX Flow Filters support.
3489 * Max Rx flows set by availability of screeners & compare regs:
3490 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3492 reg = gem_readl(bp, DCFG8);
3493 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3494 GEM_BFEXT(T2SCR, reg));
3495 if (bp->max_tuples > 0) {
3496 /* also needs one ethtype match to check IPv4 */
3497 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3498 /* program this reg now */
3500 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3501 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3502 /* Filtering is supported in hw but don't enable it in kernel now */
3503 dev->hw_features |= NETIF_F_NTUPLE;
3504 /* init Rx flow definitions */
3505 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3506 bp->rx_fs_list.count = 0;
3507 spin_lock_init(&bp->rx_fs_lock);
3512 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3514 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3515 val = GEM_BIT(RGMII);
3516 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3517 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3518 val = MACB_BIT(RMII);
3519 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3520 val = MACB_BIT(MII);
3522 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3523 val |= MACB_BIT(CLKEN);
3525 macb_or_gem_writel(bp, USRIO, val);
3528 /* Set MII management clock divider */
3529 val = macb_mdc_clk_div(bp);
3530 val |= macb_dbw(bp);
3531 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3532 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3533 macb_writel(bp, NCFGR, val);
3538 #if defined(CONFIG_OF)
3539 /* 1518 rounded up */
3540 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3541 /* max number of receive buffers */
3542 #define AT91ETHER_MAX_RX_DESCR 9
3544 /* Initialize and start the Receiver and Transmit subsystems */
3545 static int at91ether_start(struct net_device *dev)
3547 struct macb *lp = netdev_priv(dev);
3548 struct macb_queue *q = &lp->queues[0];
3549 struct macb_dma_desc *desc;
3554 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3555 (AT91ETHER_MAX_RX_DESCR *
3556 macb_dma_desc_get_size(lp)),
3557 &q->rx_ring_dma, GFP_KERNEL);
3561 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3562 AT91ETHER_MAX_RX_DESCR *
3563 AT91ETHER_MAX_RBUFF_SZ,
3564 &q->rx_buffers_dma, GFP_KERNEL);
3565 if (!q->rx_buffers) {
3566 dma_free_coherent(&lp->pdev->dev,
3567 AT91ETHER_MAX_RX_DESCR *
3568 macb_dma_desc_get_size(lp),
3569 q->rx_ring, q->rx_ring_dma);
3574 addr = q->rx_buffers_dma;
3575 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3576 desc = macb_rx_desc(q, i);
3577 macb_set_addr(lp, desc, addr);
3579 addr += AT91ETHER_MAX_RBUFF_SZ;
3582 /* Set the Wrap bit on the last descriptor */
3583 desc->addr |= MACB_BIT(RX_WRAP);
3585 /* Reset buffer index */
3588 /* Program address of descriptor list in Rx Buffer Queue register */
3589 macb_writel(lp, RBQP, q->rx_ring_dma);
3591 /* Enable Receive and Transmit */
3592 ctl = macb_readl(lp, NCR);
3593 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3598 /* Open the ethernet interface */
3599 static int at91ether_open(struct net_device *dev)
3601 struct macb *lp = netdev_priv(dev);
3605 /* Clear internal statistics */
3606 ctl = macb_readl(lp, NCR);
3607 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3609 macb_set_hwaddr(lp);
3611 ret = at91ether_start(dev);
3615 /* Enable MAC interrupts */
3616 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3618 MACB_BIT(ISR_TUND) |
3621 MACB_BIT(ISR_ROVR) |
3624 /* schedule a link state check */
3625 phy_start(dev->phydev);
3627 netif_start_queue(dev);
3632 /* Close the interface */
3633 static int at91ether_close(struct net_device *dev)
3635 struct macb *lp = netdev_priv(dev);
3636 struct macb_queue *q = &lp->queues[0];
3639 /* Disable Receiver and Transmitter */
3640 ctl = macb_readl(lp, NCR);
3641 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3643 /* Disable MAC interrupts */
3644 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3646 MACB_BIT(ISR_TUND) |
3649 MACB_BIT(ISR_ROVR) |
3652 netif_stop_queue(dev);
3654 dma_free_coherent(&lp->pdev->dev,
3655 AT91ETHER_MAX_RX_DESCR *
3656 macb_dma_desc_get_size(lp),
3657 q->rx_ring, q->rx_ring_dma);
3660 dma_free_coherent(&lp->pdev->dev,
3661 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3662 q->rx_buffers, q->rx_buffers_dma);
3663 q->rx_buffers = NULL;
3668 /* Transmit packet */
3669 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3670 struct net_device *dev)
3672 struct macb *lp = netdev_priv(dev);
3674 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3675 netif_stop_queue(dev);
3677 /* Store packet information (to free when Tx completed) */
3679 lp->skb_length = skb->len;
3680 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3682 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3683 dev_kfree_skb_any(skb);
3684 dev->stats.tx_dropped++;
3685 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3686 return NETDEV_TX_OK;
3689 /* Set address of the data in the Transmit Address register */
3690 macb_writel(lp, TAR, lp->skb_physaddr);
3691 /* Set length of the packet in the Transmit Control register */
3692 macb_writel(lp, TCR, skb->len);
3695 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3696 return NETDEV_TX_BUSY;
3699 return NETDEV_TX_OK;
3702 /* Extract received frame from buffer descriptors and sent to upper layers.
3703 * (Called from interrupt context)
3705 static void at91ether_rx(struct net_device *dev)
3707 struct macb *lp = netdev_priv(dev);
3708 struct macb_queue *q = &lp->queues[0];
3709 struct macb_dma_desc *desc;
3710 unsigned char *p_recv;
3711 struct sk_buff *skb;
3712 unsigned int pktlen;
3714 desc = macb_rx_desc(q, q->rx_tail);
3715 while (desc->addr & MACB_BIT(RX_USED)) {
3716 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3717 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3718 skb = netdev_alloc_skb(dev, pktlen + 2);
3720 skb_reserve(skb, 2);
3721 skb_put_data(skb, p_recv, pktlen);
3723 skb->protocol = eth_type_trans(skb, dev);
3724 dev->stats.rx_packets++;
3725 dev->stats.rx_bytes += pktlen;
3728 dev->stats.rx_dropped++;
3731 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3732 dev->stats.multicast++;
3734 /* reset ownership bit */
3735 desc->addr &= ~MACB_BIT(RX_USED);
3737 /* wrap after last buffer */
3738 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3743 desc = macb_rx_desc(q, q->rx_tail);
3747 /* MAC interrupt handler */
3748 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3750 struct net_device *dev = dev_id;
3751 struct macb *lp = netdev_priv(dev);
3754 /* MAC Interrupt Status register indicates what interrupts are pending.
3755 * It is automatically cleared once read.
3757 intstatus = macb_readl(lp, ISR);
3759 /* Receive complete */
3760 if (intstatus & MACB_BIT(RCOMP))
3763 /* Transmit complete */
3764 if (intstatus & MACB_BIT(TCOMP)) {
3765 /* The TCOM bit is set even if the transmission failed */
3766 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3767 dev->stats.tx_errors++;
3770 dev_kfree_skb_irq(lp->skb);
3772 dma_unmap_single(NULL, lp->skb_physaddr,
3773 lp->skb_length, DMA_TO_DEVICE);
3774 dev->stats.tx_packets++;
3775 dev->stats.tx_bytes += lp->skb_length;
3777 netif_wake_queue(dev);
3780 /* Work-around for EMAC Errata section 41.3.1 */
3781 if (intstatus & MACB_BIT(RXUBR)) {
3782 ctl = macb_readl(lp, NCR);
3783 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3785 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3788 if (intstatus & MACB_BIT(ISR_ROVR))
3789 netdev_err(dev, "ROVR error\n");
3794 #ifdef CONFIG_NET_POLL_CONTROLLER
3795 static void at91ether_poll_controller(struct net_device *dev)
3797 unsigned long flags;
3799 local_irq_save(flags);
3800 at91ether_interrupt(dev->irq, dev);
3801 local_irq_restore(flags);
3805 static const struct net_device_ops at91ether_netdev_ops = {
3806 .ndo_open = at91ether_open,
3807 .ndo_stop = at91ether_close,
3808 .ndo_start_xmit = at91ether_start_xmit,
3809 .ndo_get_stats = macb_get_stats,
3810 .ndo_set_rx_mode = macb_set_rx_mode,
3811 .ndo_set_mac_address = eth_mac_addr,
3812 .ndo_do_ioctl = macb_ioctl,
3813 .ndo_validate_addr = eth_validate_addr,
3814 #ifdef CONFIG_NET_POLL_CONTROLLER
3815 .ndo_poll_controller = at91ether_poll_controller,
3819 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3820 struct clk **hclk, struct clk **tx_clk,
3821 struct clk **rx_clk)
3829 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3831 return PTR_ERR(*pclk);
3833 err = clk_prepare_enable(*pclk);
3835 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3842 static int at91ether_init(struct platform_device *pdev)
3844 struct net_device *dev = platform_get_drvdata(pdev);
3845 struct macb *bp = netdev_priv(dev);
3849 bp->queues[0].bp = bp;
3851 dev->netdev_ops = &at91ether_netdev_ops;
3852 dev->ethtool_ops = &macb_ethtool_ops;
3854 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3859 macb_writel(bp, NCR, 0);
3861 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3862 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3863 reg |= MACB_BIT(RM9200_RMII);
3865 macb_writel(bp, NCFGR, reg);
3870 static const struct macb_config at91sam9260_config = {
3871 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3872 .clk_init = macb_clk_init,
3876 static const struct macb_config sama5d3macb_config = {
3877 .caps = MACB_CAPS_SG_DISABLED
3878 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3879 .clk_init = macb_clk_init,
3883 static const struct macb_config pc302gem_config = {
3884 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3885 .dma_burst_length = 16,
3886 .clk_init = macb_clk_init,
3890 static const struct macb_config sama5d2_config = {
3891 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3892 .dma_burst_length = 16,
3893 .clk_init = macb_clk_init,
3897 static const struct macb_config sama5d3_config = {
3898 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3899 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3900 .dma_burst_length = 16,
3901 .clk_init = macb_clk_init,
3903 .jumbo_max_len = 10240,
3906 static const struct macb_config sama5d4_config = {
3907 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3908 .dma_burst_length = 4,
3909 .clk_init = macb_clk_init,
3913 static const struct macb_config emac_config = {
3914 .clk_init = at91ether_clk_init,
3915 .init = at91ether_init,
3918 static const struct macb_config np4_config = {
3919 .caps = MACB_CAPS_USRIO_DISABLED,
3920 .clk_init = macb_clk_init,
3924 static const struct macb_config zynqmp_config = {
3925 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3927 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
3928 .dma_burst_length = 16,
3929 .clk_init = macb_clk_init,
3931 .jumbo_max_len = 10240,
3934 static const struct macb_config zynq_config = {
3935 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
3936 .dma_burst_length = 16,
3937 .clk_init = macb_clk_init,
3941 static const struct of_device_id macb_dt_ids[] = {
3942 { .compatible = "cdns,at32ap7000-macb" },
3943 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3944 { .compatible = "cdns,macb" },
3945 { .compatible = "cdns,np4-macb", .data = &np4_config },
3946 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3947 { .compatible = "cdns,gem", .data = &pc302gem_config },
3948 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3949 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3950 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
3951 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3952 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3953 { .compatible = "cdns,emac", .data = &emac_config },
3954 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
3955 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
3958 MODULE_DEVICE_TABLE(of, macb_dt_ids);
3959 #endif /* CONFIG_OF */
3961 static const struct macb_config default_gem_config = {
3962 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3964 MACB_CAPS_GEM_HAS_PTP,
3965 .dma_burst_length = 16,
3966 .clk_init = macb_clk_init,
3968 .jumbo_max_len = 10240,
3971 static int macb_probe(struct platform_device *pdev)
3973 const struct macb_config *macb_config = &default_gem_config;
3974 int (*clk_init)(struct platform_device *, struct clk **,
3975 struct clk **, struct clk **, struct clk **)
3976 = macb_config->clk_init;
3977 int (*init)(struct platform_device *) = macb_config->init;
3978 struct device_node *np = pdev->dev.of_node;
3979 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
3980 unsigned int queue_mask, num_queues;
3981 struct macb_platform_data *pdata;
3983 struct phy_device *phydev;
3984 struct net_device *dev;
3985 struct resource *regs;
3991 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3992 mem = devm_ioremap_resource(&pdev->dev, regs);
3994 return PTR_ERR(mem);
3997 const struct of_device_id *match;
3999 match = of_match_node(macb_dt_ids, np);
4000 if (match && match->data) {
4001 macb_config = match->data;
4002 clk_init = macb_config->clk_init;
4003 init = macb_config->init;
4007 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
4011 native_io = hw_is_native_io(mem);
4013 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4014 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4017 goto err_disable_clocks;
4020 dev->base_addr = regs->start;
4022 SET_NETDEV_DEV(dev, &pdev->dev);
4024 bp = netdev_priv(dev);
4028 bp->native_io = native_io;
4030 bp->macb_reg_readl = hw_readl_native;
4031 bp->macb_reg_writel = hw_writel_native;
4033 bp->macb_reg_readl = hw_readl;
4034 bp->macb_reg_writel = hw_writel;
4036 bp->num_queues = num_queues;
4037 bp->queue_mask = queue_mask;
4039 bp->dma_burst_length = macb_config->dma_burst_length;
4042 bp->tx_clk = tx_clk;
4043 bp->rx_clk = rx_clk;
4045 bp->jumbo_max_len = macb_config->jumbo_max_len;
4048 if (of_get_property(np, "magic-packet", NULL))
4049 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4050 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4052 spin_lock_init(&bp->lock);
4054 /* setup capabilities */
4055 macb_configure_caps(bp, macb_config);
4057 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4058 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4059 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4060 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4063 platform_set_drvdata(pdev, dev);
4065 dev->irq = platform_get_irq(pdev, 0);
4068 goto err_out_free_netdev;
4071 /* MTU range: 68 - 1500 or 10240 */
4072 dev->min_mtu = GEM_MTU_MIN_SIZE;
4073 if (bp->caps & MACB_CAPS_JUMBO)
4074 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4076 dev->max_mtu = ETH_DATA_LEN;
4078 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4079 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4081 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4082 macb_dma_desc_get_size(bp);
4084 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4086 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4087 macb_dma_desc_get_size(bp);
4090 mac = of_get_mac_address(np);
4092 ether_addr_copy(bp->dev->dev_addr, mac);
4094 err = nvmem_get_mac_address(&pdev->dev, bp->dev->dev_addr);
4096 if (err == -EPROBE_DEFER)
4097 goto err_out_free_netdev;
4098 macb_get_hwaddr(bp);
4102 err = of_get_phy_mode(np);
4104 pdata = dev_get_platdata(&pdev->dev);
4105 if (pdata && pdata->is_rmii)
4106 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
4108 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4110 bp->phy_interface = err;
4113 /* IP specific init */
4116 goto err_out_free_netdev;
4118 err = macb_mii_init(bp);
4120 goto err_out_free_netdev;
4122 phydev = dev->phydev;
4124 netif_carrier_off(dev);
4126 err = register_netdev(dev);
4128 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4129 goto err_out_unregister_mdio;
4132 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4135 phy_attached_info(phydev);
4137 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4138 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4139 dev->base_addr, dev->irq, dev->dev_addr);
4143 err_out_unregister_mdio:
4144 phy_disconnect(dev->phydev);
4145 mdiobus_unregister(bp->mii_bus);
4146 of_node_put(bp->phy_node);
4147 if (np && of_phy_is_fixed_link(np))
4148 of_phy_deregister_fixed_link(np);
4149 mdiobus_free(bp->mii_bus);
4151 err_out_free_netdev:
4155 clk_disable_unprepare(tx_clk);
4156 clk_disable_unprepare(hclk);
4157 clk_disable_unprepare(pclk);
4158 clk_disable_unprepare(rx_clk);
4163 static int macb_remove(struct platform_device *pdev)
4165 struct net_device *dev;
4167 struct device_node *np = pdev->dev.of_node;
4169 dev = platform_get_drvdata(pdev);
4172 bp = netdev_priv(dev);
4174 phy_disconnect(dev->phydev);
4175 mdiobus_unregister(bp->mii_bus);
4176 if (np && of_phy_is_fixed_link(np))
4177 of_phy_deregister_fixed_link(np);
4179 mdiobus_free(bp->mii_bus);
4181 unregister_netdev(dev);
4182 clk_disable_unprepare(bp->tx_clk);
4183 clk_disable_unprepare(bp->hclk);
4184 clk_disable_unprepare(bp->pclk);
4185 clk_disable_unprepare(bp->rx_clk);
4186 of_node_put(bp->phy_node);
4193 static int __maybe_unused macb_suspend(struct device *dev)
4195 struct net_device *netdev = dev_get_drvdata(dev);
4196 struct macb *bp = netdev_priv(netdev);
4198 netif_carrier_off(netdev);
4199 netif_device_detach(netdev);
4201 if (bp->wol & MACB_WOL_ENABLED) {
4202 macb_writel(bp, IER, MACB_BIT(WOL));
4203 macb_writel(bp, WOL, MACB_BIT(MAG));
4204 enable_irq_wake(bp->queues[0].irq);
4206 clk_disable_unprepare(bp->tx_clk);
4207 clk_disable_unprepare(bp->hclk);
4208 clk_disable_unprepare(bp->pclk);
4209 clk_disable_unprepare(bp->rx_clk);
4215 static int __maybe_unused macb_resume(struct device *dev)
4217 struct net_device *netdev = dev_get_drvdata(dev);
4218 struct macb *bp = netdev_priv(netdev);
4220 if (bp->wol & MACB_WOL_ENABLED) {
4221 macb_writel(bp, IDR, MACB_BIT(WOL));
4222 macb_writel(bp, WOL, 0);
4223 disable_irq_wake(bp->queues[0].irq);
4225 clk_prepare_enable(bp->pclk);
4226 clk_prepare_enable(bp->hclk);
4227 clk_prepare_enable(bp->tx_clk);
4228 clk_prepare_enable(bp->rx_clk);
4231 netif_device_attach(netdev);
4236 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
4238 static struct platform_driver macb_driver = {
4239 .probe = macb_probe,
4240 .remove = macb_remove,
4243 .of_match_table = of_match_ptr(macb_dt_ids),
4248 module_platform_driver(macb_driver);
4250 MODULE_LICENSE("GPL");
4251 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4252 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4253 MODULE_ALIAS("platform:macb");