1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phylink.h>
30 #include <linux/of_device.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_mdio.h>
33 #include <linux/of_net.h>
35 #include <linux/udp.h>
36 #include <linux/tcp.h>
37 #include <linux/iopoll.h>
38 #include <linux/pm_runtime.h>
41 /* This structure is only used for MACB on SiFive FU540 devices */
42 struct sifive_fu540_macb_mgmt {
48 #define MACB_RX_BUFFER_SIZE 128
49 #define RX_BUFFER_MULTIPLE 64 /* bytes */
51 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
52 #define MIN_RX_RING_SIZE 64
53 #define MAX_RX_RING_SIZE 8192
54 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
57 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
58 #define MIN_TX_RING_SIZE 64
59 #define MAX_TX_RING_SIZE 4096
60 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
63 /* level of occupied TX descriptors under which we wake up TX process */
64 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
66 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
67 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
70 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
73 /* Max length of transmit frame must be a multiple of 8 bytes */
74 #define MACB_TX_LEN_ALIGN 8
75 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
76 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
77 * false amba_error in TX path from the DMA assuming there is not enough
78 * space in the SRAM (16KB) even when there is.
80 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
82 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
83 #define MACB_NETIF_LSO NETIF_F_TSO
85 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
86 #define MACB_WOL_ENABLED (0x1 << 1)
88 /* Graceful stop timeouts in us. We should allow up to
89 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
91 #define MACB_HALT_TIMEOUT 1230
93 #define MACB_PM_TIMEOUT 100 /* ms */
95 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
97 /* DMA buffer descriptor might be different size
98 * depends on hardware configuration:
100 * 1. dma address width 32 bits:
101 * word 1: 32 bit address of Data Buffer
104 * 2. dma address width 64 bits:
105 * word 1: 32 bit address of Data Buffer
107 * word 3: upper 32 bit address of Data Buffer
110 * 3. dma address width 32 bits with hardware timestamping:
111 * word 1: 32 bit address of Data Buffer
113 * word 3: timestamp word 1
114 * word 4: timestamp word 2
116 * 4. dma address width 64 bits with hardware timestamping:
117 * word 1: 32 bit address of Data Buffer
119 * word 3: upper 32 bit address of Data Buffer
121 * word 5: timestamp word 1
122 * word 6: timestamp word 2
124 static unsigned int macb_dma_desc_get_size(struct macb *bp)
127 unsigned int desc_size;
129 switch (bp->hw_dma_cap) {
131 desc_size = sizeof(struct macb_dma_desc)
132 + sizeof(struct macb_dma_desc_64);
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_ptp);
138 case HW_DMA_CAP_64B_PTP:
139 desc_size = sizeof(struct macb_dma_desc)
140 + sizeof(struct macb_dma_desc_64)
141 + sizeof(struct macb_dma_desc_ptp);
144 desc_size = sizeof(struct macb_dma_desc);
148 return sizeof(struct macb_dma_desc);
151 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
154 switch (bp->hw_dma_cap) {
159 case HW_DMA_CAP_64B_PTP:
169 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
170 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
172 return (struct macb_dma_desc_64 *)((void *)desc
173 + sizeof(struct macb_dma_desc));
177 /* Ring buffer accessors */
178 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
180 return index & (bp->tx_ring_size - 1);
183 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
186 index = macb_tx_ring_wrap(queue->bp, index);
187 index = macb_adj_dma_desc_idx(queue->bp, index);
188 return &queue->tx_ring[index];
191 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
194 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
197 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
201 offset = macb_tx_ring_wrap(queue->bp, index) *
202 macb_dma_desc_get_size(queue->bp);
204 return queue->tx_ring_dma + offset;
207 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
209 return index & (bp->rx_ring_size - 1);
212 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
214 index = macb_rx_ring_wrap(queue->bp, index);
215 index = macb_adj_dma_desc_idx(queue->bp, index);
216 return &queue->rx_ring[index];
219 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
221 return queue->rx_buffers + queue->bp->rx_buffer_size *
222 macb_rx_ring_wrap(queue->bp, index);
226 static u32 hw_readl_native(struct macb *bp, int offset)
228 return __raw_readl(bp->regs + offset);
231 static void hw_writel_native(struct macb *bp, int offset, u32 value)
233 __raw_writel(value, bp->regs + offset);
236 static u32 hw_readl(struct macb *bp, int offset)
238 return readl_relaxed(bp->regs + offset);
241 static void hw_writel(struct macb *bp, int offset, u32 value)
243 writel_relaxed(value, bp->regs + offset);
246 /* Find the CPU endianness by using the loopback bit of NCR register. When the
247 * CPU is in big endian we need to program swapped mode for management
250 static bool hw_is_native_io(void __iomem *addr)
252 u32 value = MACB_BIT(LLB);
254 __raw_writel(value, addr + MACB_NCR);
255 value = __raw_readl(addr + MACB_NCR);
257 /* Write 0 back to disable everything */
258 __raw_writel(0, addr + MACB_NCR);
260 return value == MACB_BIT(LLB);
263 static bool hw_is_gem(void __iomem *addr, bool native_io)
268 id = __raw_readl(addr + MACB_MID);
270 id = readl_relaxed(addr + MACB_MID);
272 return MACB_BFEXT(IDNUM, id) >= 0x2;
275 static void macb_set_hwaddr(struct macb *bp)
280 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
281 macb_or_gem_writel(bp, SA1B, bottom);
282 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
283 macb_or_gem_writel(bp, SA1T, top);
285 /* Clear unused address register sets */
286 macb_or_gem_writel(bp, SA2B, 0);
287 macb_or_gem_writel(bp, SA2T, 0);
288 macb_or_gem_writel(bp, SA3B, 0);
289 macb_or_gem_writel(bp, SA3T, 0);
290 macb_or_gem_writel(bp, SA4B, 0);
291 macb_or_gem_writel(bp, SA4T, 0);
294 static void macb_get_hwaddr(struct macb *bp)
301 /* Check all 4 address register for valid address */
302 for (i = 0; i < 4; i++) {
303 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
304 top = macb_or_gem_readl(bp, SA1T + i * 8);
306 addr[0] = bottom & 0xff;
307 addr[1] = (bottom >> 8) & 0xff;
308 addr[2] = (bottom >> 16) & 0xff;
309 addr[3] = (bottom >> 24) & 0xff;
310 addr[4] = top & 0xff;
311 addr[5] = (top >> 8) & 0xff;
313 if (is_valid_ether_addr(addr)) {
314 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
319 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
320 eth_hw_addr_random(bp->dev);
323 static int macb_mdio_wait_for_idle(struct macb *bp)
327 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
328 1, MACB_MDIO_TIMEOUT);
331 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
333 struct macb *bp = bus->priv;
336 status = pm_runtime_get_sync(&bp->pdev->dev);
338 pm_runtime_put_noidle(&bp->pdev->dev);
342 status = macb_mdio_wait_for_idle(bp);
346 if (regnum & MII_ADDR_C45) {
347 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
348 | MACB_BF(RW, MACB_MAN_C45_ADDR)
349 | MACB_BF(PHYA, mii_id)
350 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
351 | MACB_BF(DATA, regnum & 0xFFFF)
352 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
354 status = macb_mdio_wait_for_idle(bp);
358 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
359 | MACB_BF(RW, MACB_MAN_C45_READ)
360 | MACB_BF(PHYA, mii_id)
361 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
362 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
364 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
365 | MACB_BF(RW, MACB_MAN_C22_READ)
366 | MACB_BF(PHYA, mii_id)
367 | MACB_BF(REGA, regnum)
368 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
371 status = macb_mdio_wait_for_idle(bp);
375 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
378 pm_runtime_mark_last_busy(&bp->pdev->dev);
379 pm_runtime_put_autosuspend(&bp->pdev->dev);
384 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
387 struct macb *bp = bus->priv;
390 status = pm_runtime_get_sync(&bp->pdev->dev);
392 pm_runtime_put_noidle(&bp->pdev->dev);
396 status = macb_mdio_wait_for_idle(bp);
398 goto mdio_write_exit;
400 if (regnum & MII_ADDR_C45) {
401 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
402 | MACB_BF(RW, MACB_MAN_C45_ADDR)
403 | MACB_BF(PHYA, mii_id)
404 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
405 | MACB_BF(DATA, regnum & 0xFFFF)
406 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
408 status = macb_mdio_wait_for_idle(bp);
410 goto mdio_write_exit;
412 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
413 | MACB_BF(RW, MACB_MAN_C45_WRITE)
414 | MACB_BF(PHYA, mii_id)
415 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
416 | MACB_BF(CODE, MACB_MAN_C45_CODE)
417 | MACB_BF(DATA, value)));
419 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
420 | MACB_BF(RW, MACB_MAN_C22_WRITE)
421 | MACB_BF(PHYA, mii_id)
422 | MACB_BF(REGA, regnum)
423 | MACB_BF(CODE, MACB_MAN_C22_CODE)
424 | MACB_BF(DATA, value)));
427 status = macb_mdio_wait_for_idle(bp);
429 goto mdio_write_exit;
432 pm_runtime_mark_last_busy(&bp->pdev->dev);
433 pm_runtime_put_autosuspend(&bp->pdev->dev);
438 static void macb_init_buffers(struct macb *bp)
440 struct macb_queue *queue;
443 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
444 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
445 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
446 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
447 queue_writel(queue, RBQPH,
448 upper_32_bits(queue->rx_ring_dma));
450 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
451 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
452 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
453 queue_writel(queue, TBQPH,
454 upper_32_bits(queue->tx_ring_dma));
460 * macb_set_tx_clk() - Set a clock to a new frequency
461 * @clk Pointer to the clock to change
462 * @rate New frequency in Hz
463 * @dev Pointer to the struct net_device
465 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
467 long ferr, rate, rate_rounded;
486 rate_rounded = clk_round_rate(clk, rate);
487 if (rate_rounded < 0)
490 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
493 ferr = abs(rate_rounded - rate);
494 ferr = DIV_ROUND_UP(ferr, rate / 100000);
496 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
499 if (clk_set_rate(clk, rate_rounded))
500 netdev_err(dev, "adjusting tx_clk failed.\n");
503 static void macb_validate(struct phylink_config *config,
504 unsigned long *supported,
505 struct phylink_link_state *state)
507 struct net_device *ndev = to_net_dev(config->dev);
508 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
509 struct macb *bp = netdev_priv(ndev);
511 /* We only support MII, RMII, GMII, RGMII & SGMII. */
512 if (state->interface != PHY_INTERFACE_MODE_NA &&
513 state->interface != PHY_INTERFACE_MODE_MII &&
514 state->interface != PHY_INTERFACE_MODE_RMII &&
515 state->interface != PHY_INTERFACE_MODE_GMII &&
516 state->interface != PHY_INTERFACE_MODE_SGMII &&
517 !phy_interface_mode_is_rgmii(state->interface)) {
518 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
522 if (!macb_is_gem(bp) &&
523 (state->interface == PHY_INTERFACE_MODE_GMII ||
524 phy_interface_mode_is_rgmii(state->interface))) {
525 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
529 phylink_set_port_modes(mask);
530 phylink_set(mask, Autoneg);
531 phylink_set(mask, Asym_Pause);
533 phylink_set(mask, 10baseT_Half);
534 phylink_set(mask, 10baseT_Full);
535 phylink_set(mask, 100baseT_Half);
536 phylink_set(mask, 100baseT_Full);
538 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
539 (state->interface == PHY_INTERFACE_MODE_NA ||
540 state->interface == PHY_INTERFACE_MODE_GMII ||
541 state->interface == PHY_INTERFACE_MODE_SGMII ||
542 phy_interface_mode_is_rgmii(state->interface))) {
543 phylink_set(mask, 1000baseT_Full);
544 phylink_set(mask, 1000baseX_Full);
546 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
547 phylink_set(mask, 1000baseT_Half);
550 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
551 bitmap_and(state->advertising, state->advertising, mask,
552 __ETHTOOL_LINK_MODE_MASK_NBITS);
555 static void macb_mac_pcs_get_state(struct phylink_config *config,
556 struct phylink_link_state *state)
561 static void macb_mac_an_restart(struct phylink_config *config)
566 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
567 const struct phylink_link_state *state)
569 struct net_device *ndev = to_net_dev(config->dev);
570 struct macb *bp = netdev_priv(ndev);
574 spin_lock_irqsave(&bp->lock, flags);
576 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
578 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
579 if (state->interface == PHY_INTERFACE_MODE_RMII)
580 ctrl |= MACB_BIT(RM9200_RMII);
582 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
584 if (state->interface == PHY_INTERFACE_MODE_SGMII)
585 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
588 /* Apply the new configuration, if any */
590 macb_or_gem_writel(bp, NCFGR, ctrl);
592 spin_unlock_irqrestore(&bp->lock, flags);
595 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
596 phy_interface_t interface)
598 struct net_device *ndev = to_net_dev(config->dev);
599 struct macb *bp = netdev_priv(ndev);
600 struct macb_queue *queue;
604 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
605 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
606 queue_writel(queue, IDR,
607 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
609 /* Disable Rx and Tx */
610 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
611 macb_writel(bp, NCR, ctrl);
613 netif_tx_stop_all_queues(ndev);
616 static void macb_mac_link_up(struct phylink_config *config,
617 struct phy_device *phy,
618 unsigned int mode, phy_interface_t interface,
619 int speed, int duplex,
620 bool tx_pause, bool rx_pause)
622 struct net_device *ndev = to_net_dev(config->dev);
623 struct macb *bp = netdev_priv(ndev);
624 struct macb_queue *queue;
629 spin_lock_irqsave(&bp->lock, flags);
631 ctrl = macb_or_gem_readl(bp, NCFGR);
633 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
635 if (speed == SPEED_100)
636 ctrl |= MACB_BIT(SPD);
639 ctrl |= MACB_BIT(FD);
641 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
642 ctrl &= ~(GEM_BIT(GBE) | MACB_BIT(PAE));
644 if (speed == SPEED_1000)
645 ctrl |= GEM_BIT(GBE);
647 /* We do not support MLO_PAUSE_RX yet */
649 ctrl |= MACB_BIT(PAE);
651 macb_set_tx_clk(bp->tx_clk, speed, ndev);
653 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
654 * cleared the pipeline and control registers.
656 bp->macbgem_ops.mog_init_rings(bp);
657 macb_init_buffers(bp);
659 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
660 queue_writel(queue, IER,
661 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
664 macb_or_gem_writel(bp, NCFGR, ctrl);
666 spin_unlock_irqrestore(&bp->lock, flags);
668 /* Enable Rx and Tx */
669 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
671 netif_tx_wake_all_queues(ndev);
674 static const struct phylink_mac_ops macb_phylink_ops = {
675 .validate = macb_validate,
676 .mac_pcs_get_state = macb_mac_pcs_get_state,
677 .mac_an_restart = macb_mac_an_restart,
678 .mac_config = macb_mac_config,
679 .mac_link_down = macb_mac_link_down,
680 .mac_link_up = macb_mac_link_up,
683 static bool macb_phy_handle_exists(struct device_node *dn)
685 dn = of_parse_phandle(dn, "phy-handle", 0);
690 static int macb_phylink_connect(struct macb *bp)
692 struct device_node *dn = bp->pdev->dev.of_node;
693 struct net_device *dev = bp->dev;
694 struct phy_device *phydev;
698 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
700 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
701 phydev = phy_find_first(bp->mii_bus);
703 netdev_err(dev, "no PHY found\n");
707 /* attach the mac to the phy */
708 ret = phylink_connect_phy(bp->phylink, phydev);
712 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
716 phylink_start(bp->phylink);
721 /* based on au1000_eth. c*/
722 static int macb_mii_probe(struct net_device *dev)
724 struct macb *bp = netdev_priv(dev);
726 bp->phylink_config.dev = &dev->dev;
727 bp->phylink_config.type = PHYLINK_NETDEV;
729 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
730 bp->phy_interface, &macb_phylink_ops);
731 if (IS_ERR(bp->phylink)) {
732 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
733 PTR_ERR(bp->phylink));
734 return PTR_ERR(bp->phylink);
740 static int macb_mdiobus_register(struct macb *bp)
742 struct device_node *child, *np = bp->pdev->dev.of_node;
744 if (of_phy_is_fixed_link(np))
745 return mdiobus_register(bp->mii_bus);
747 /* Only create the PHY from the device tree if at least one PHY is
748 * described. Otherwise scan the entire MDIO bus. We do this to support
749 * old device tree that did not follow the best practices and did not
750 * describe their network PHYs.
752 for_each_available_child_of_node(np, child)
753 if (of_mdiobus_child_is_phy(child)) {
754 /* The loop increments the child refcount,
755 * decrement it before returning.
759 return of_mdiobus_register(bp->mii_bus, np);
762 return mdiobus_register(bp->mii_bus);
765 static int macb_mii_init(struct macb *bp)
769 /* Enable management port */
770 macb_writel(bp, NCR, MACB_BIT(MPE));
772 bp->mii_bus = mdiobus_alloc();
778 bp->mii_bus->name = "MACB_mii_bus";
779 bp->mii_bus->read = &macb_mdio_read;
780 bp->mii_bus->write = &macb_mdio_write;
781 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
782 bp->pdev->name, bp->pdev->id);
783 bp->mii_bus->priv = bp;
784 bp->mii_bus->parent = &bp->pdev->dev;
786 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
788 err = macb_mdiobus_register(bp);
790 goto err_out_free_mdiobus;
792 err = macb_mii_probe(bp->dev);
794 goto err_out_unregister_bus;
798 err_out_unregister_bus:
799 mdiobus_unregister(bp->mii_bus);
800 err_out_free_mdiobus:
801 mdiobus_free(bp->mii_bus);
806 static void macb_update_stats(struct macb *bp)
808 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
809 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
810 int offset = MACB_PFR;
812 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
814 for (; p < end; p++, offset += 4)
815 *p += bp->macb_reg_readl(bp, offset);
818 static int macb_halt_tx(struct macb *bp)
820 unsigned long halt_time, timeout;
823 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
825 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
828 status = macb_readl(bp, TSR);
829 if (!(status & MACB_BIT(TGO)))
833 } while (time_before(halt_time, timeout));
838 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
840 if (tx_skb->mapping) {
841 if (tx_skb->mapped_as_page)
842 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
843 tx_skb->size, DMA_TO_DEVICE);
845 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
846 tx_skb->size, DMA_TO_DEVICE);
851 dev_kfree_skb_any(tx_skb->skb);
856 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
858 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
859 struct macb_dma_desc_64 *desc_64;
861 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
862 desc_64 = macb_64b_desc(bp, desc);
863 desc_64->addrh = upper_32_bits(addr);
864 /* The low bits of RX address contain the RX_USED bit, clearing
865 * of which allows packet RX. Make sure the high bits are also
866 * visible to HW at that point.
871 desc->addr = lower_32_bits(addr);
874 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
877 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
878 struct macb_dma_desc_64 *desc_64;
880 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
881 desc_64 = macb_64b_desc(bp, desc);
882 addr = ((u64)(desc_64->addrh) << 32);
885 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
889 static void macb_tx_error_task(struct work_struct *work)
891 struct macb_queue *queue = container_of(work, struct macb_queue,
893 struct macb *bp = queue->bp;
894 struct macb_tx_skb *tx_skb;
895 struct macb_dma_desc *desc;
900 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
901 (unsigned int)(queue - bp->queues),
902 queue->tx_tail, queue->tx_head);
904 /* Prevent the queue IRQ handlers from running: each of them may call
905 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
906 * As explained below, we have to halt the transmission before updating
907 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
908 * network engine about the macb/gem being halted.
910 spin_lock_irqsave(&bp->lock, flags);
912 /* Make sure nobody is trying to queue up new packets */
913 netif_tx_stop_all_queues(bp->dev);
915 /* Stop transmission now
916 * (in case we have just queued new packets)
917 * macb/gem must be halted to write TBQP register
919 if (macb_halt_tx(bp))
920 /* Just complain for now, reinitializing TX path can be good */
921 netdev_err(bp->dev, "BUG: halt tx timed out\n");
923 /* Treat frames in TX queue including the ones that caused the error.
924 * Free transmit buffers in upper layer.
926 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
929 desc = macb_tx_desc(queue, tail);
931 tx_skb = macb_tx_skb(queue, tail);
934 if (ctrl & MACB_BIT(TX_USED)) {
935 /* skb is set for the last buffer of the frame */
937 macb_tx_unmap(bp, tx_skb);
939 tx_skb = macb_tx_skb(queue, tail);
943 /* ctrl still refers to the first buffer descriptor
944 * since it's the only one written back by the hardware
946 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
947 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
948 macb_tx_ring_wrap(bp, tail),
950 bp->dev->stats.tx_packets++;
951 queue->stats.tx_packets++;
952 bp->dev->stats.tx_bytes += skb->len;
953 queue->stats.tx_bytes += skb->len;
956 /* "Buffers exhausted mid-frame" errors may only happen
957 * if the driver is buggy, so complain loudly about
958 * those. Statistics are updated by hardware.
960 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
962 "BUG: TX buffers exhausted mid-frame\n");
964 desc->ctrl = ctrl | MACB_BIT(TX_USED);
967 macb_tx_unmap(bp, tx_skb);
970 /* Set end of TX queue */
971 desc = macb_tx_desc(queue, 0);
972 macb_set_addr(bp, desc, 0);
973 desc->ctrl = MACB_BIT(TX_USED);
975 /* Make descriptor updates visible to hardware */
978 /* Reinitialize the TX desc queue */
979 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
980 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
981 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
982 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
984 /* Make TX ring reflect state of hardware */
988 /* Housework before enabling TX IRQ */
989 macb_writel(bp, TSR, macb_readl(bp, TSR));
990 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
992 /* Now we are ready to start transmission again */
993 netif_tx_start_all_queues(bp->dev);
994 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
996 spin_unlock_irqrestore(&bp->lock, flags);
999 static void macb_tx_interrupt(struct macb_queue *queue)
1004 struct macb *bp = queue->bp;
1005 u16 queue_index = queue - bp->queues;
1007 status = macb_readl(bp, TSR);
1008 macb_writel(bp, TSR, status);
1010 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1011 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1013 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
1014 (unsigned long)status);
1016 head = queue->tx_head;
1017 for (tail = queue->tx_tail; tail != head; tail++) {
1018 struct macb_tx_skb *tx_skb;
1019 struct sk_buff *skb;
1020 struct macb_dma_desc *desc;
1023 desc = macb_tx_desc(queue, tail);
1025 /* Make hw descriptor updates visible to CPU */
1030 /* TX_USED bit is only set by hardware on the very first buffer
1031 * descriptor of the transmitted frame.
1033 if (!(ctrl & MACB_BIT(TX_USED)))
1036 /* Process all buffers of the current transmitted frame */
1038 tx_skb = macb_tx_skb(queue, tail);
1041 /* First, update TX stats if needed */
1043 if (unlikely(skb_shinfo(skb)->tx_flags &
1045 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1046 /* skb now belongs to timestamp buffer
1047 * and will be removed later
1051 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1052 macb_tx_ring_wrap(bp, tail),
1054 bp->dev->stats.tx_packets++;
1055 queue->stats.tx_packets++;
1056 bp->dev->stats.tx_bytes += skb->len;
1057 queue->stats.tx_bytes += skb->len;
1060 /* Now we can safely release resources */
1061 macb_tx_unmap(bp, tx_skb);
1063 /* skb is set only for the last buffer of the frame.
1064 * WARNING: at this point skb has been freed by
1072 queue->tx_tail = tail;
1073 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1074 CIRC_CNT(queue->tx_head, queue->tx_tail,
1075 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1076 netif_wake_subqueue(bp->dev, queue_index);
1079 static void gem_rx_refill(struct macb_queue *queue)
1082 struct sk_buff *skb;
1084 struct macb *bp = queue->bp;
1085 struct macb_dma_desc *desc;
1087 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1088 bp->rx_ring_size) > 0) {
1089 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1091 /* Make hw descriptor updates visible to CPU */
1094 queue->rx_prepared_head++;
1095 desc = macb_rx_desc(queue, entry);
1097 if (!queue->rx_skbuff[entry]) {
1098 /* allocate sk_buff for this free entry in ring */
1099 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1100 if (unlikely(!skb)) {
1102 "Unable to allocate sk_buff\n");
1106 /* now fill corresponding descriptor entry */
1107 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1110 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1115 queue->rx_skbuff[entry] = skb;
1117 if (entry == bp->rx_ring_size - 1)
1118 paddr |= MACB_BIT(RX_WRAP);
1120 /* Setting addr clears RX_USED and allows reception,
1121 * make sure ctrl is cleared first to avoid a race.
1124 macb_set_addr(bp, desc, paddr);
1126 /* properly align Ethernet header */
1127 skb_reserve(skb, NET_IP_ALIGN);
1131 desc->addr &= ~MACB_BIT(RX_USED);
1135 /* Make descriptor updates visible to hardware */
1138 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1139 queue, queue->rx_prepared_head, queue->rx_tail);
1142 /* Mark DMA descriptors from begin up to and not including end as unused */
1143 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1148 for (frag = begin; frag != end; frag++) {
1149 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1151 desc->addr &= ~MACB_BIT(RX_USED);
1154 /* Make descriptor updates visible to hardware */
1157 /* When this happens, the hardware stats registers for
1158 * whatever caused this is updated, so we don't have to record
1163 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1166 struct macb *bp = queue->bp;
1169 struct sk_buff *skb;
1170 struct macb_dma_desc *desc;
1173 while (count < budget) {
1178 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1179 desc = macb_rx_desc(queue, entry);
1181 /* Make hw descriptor updates visible to CPU */
1184 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1185 addr = macb_get_addr(bp, desc);
1190 /* Ensure ctrl is at least as up-to-date as rxused */
1198 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1200 "not whole frame pointed by descriptor\n");
1201 bp->dev->stats.rx_dropped++;
1202 queue->stats.rx_dropped++;
1205 skb = queue->rx_skbuff[entry];
1206 if (unlikely(!skb)) {
1208 "inconsistent Rx descriptor chain\n");
1209 bp->dev->stats.rx_dropped++;
1210 queue->stats.rx_dropped++;
1213 /* now everything is ready for receiving packet */
1214 queue->rx_skbuff[entry] = NULL;
1215 len = ctrl & bp->rx_frm_len_mask;
1217 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1220 dma_unmap_single(&bp->pdev->dev, addr,
1221 bp->rx_buffer_size, DMA_FROM_DEVICE);
1223 skb->protocol = eth_type_trans(skb, bp->dev);
1224 skb_checksum_none_assert(skb);
1225 if (bp->dev->features & NETIF_F_RXCSUM &&
1226 !(bp->dev->flags & IFF_PROMISC) &&
1227 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1228 skb->ip_summed = CHECKSUM_UNNECESSARY;
1230 bp->dev->stats.rx_packets++;
1231 queue->stats.rx_packets++;
1232 bp->dev->stats.rx_bytes += skb->len;
1233 queue->stats.rx_bytes += skb->len;
1235 gem_ptp_do_rxstamp(bp, skb, desc);
1237 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1238 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1239 skb->len, skb->csum);
1240 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1241 skb_mac_header(skb), 16, true);
1242 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1243 skb->data, 32, true);
1246 napi_gro_receive(napi, skb);
1249 gem_rx_refill(queue);
1254 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1255 unsigned int first_frag, unsigned int last_frag)
1259 unsigned int offset;
1260 struct sk_buff *skb;
1261 struct macb_dma_desc *desc;
1262 struct macb *bp = queue->bp;
1264 desc = macb_rx_desc(queue, last_frag);
1265 len = desc->ctrl & bp->rx_frm_len_mask;
1267 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1268 macb_rx_ring_wrap(bp, first_frag),
1269 macb_rx_ring_wrap(bp, last_frag), len);
1271 /* The ethernet header starts NET_IP_ALIGN bytes into the
1272 * first buffer. Since the header is 14 bytes, this makes the
1273 * payload word-aligned.
1275 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1276 * the two padding bytes into the skb so that we avoid hitting
1277 * the slowpath in memcpy(), and pull them off afterwards.
1279 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1281 bp->dev->stats.rx_dropped++;
1282 for (frag = first_frag; ; frag++) {
1283 desc = macb_rx_desc(queue, frag);
1284 desc->addr &= ~MACB_BIT(RX_USED);
1285 if (frag == last_frag)
1289 /* Make descriptor updates visible to hardware */
1296 len += NET_IP_ALIGN;
1297 skb_checksum_none_assert(skb);
1300 for (frag = first_frag; ; frag++) {
1301 unsigned int frag_len = bp->rx_buffer_size;
1303 if (offset + frag_len > len) {
1304 if (unlikely(frag != last_frag)) {
1305 dev_kfree_skb_any(skb);
1308 frag_len = len - offset;
1310 skb_copy_to_linear_data_offset(skb, offset,
1311 macb_rx_buffer(queue, frag),
1313 offset += bp->rx_buffer_size;
1314 desc = macb_rx_desc(queue, frag);
1315 desc->addr &= ~MACB_BIT(RX_USED);
1317 if (frag == last_frag)
1321 /* Make descriptor updates visible to hardware */
1324 __skb_pull(skb, NET_IP_ALIGN);
1325 skb->protocol = eth_type_trans(skb, bp->dev);
1327 bp->dev->stats.rx_packets++;
1328 bp->dev->stats.rx_bytes += skb->len;
1329 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1330 skb->len, skb->csum);
1331 napi_gro_receive(napi, skb);
1336 static inline void macb_init_rx_ring(struct macb_queue *queue)
1338 struct macb *bp = queue->bp;
1340 struct macb_dma_desc *desc = NULL;
1343 addr = queue->rx_buffers_dma;
1344 for (i = 0; i < bp->rx_ring_size; i++) {
1345 desc = macb_rx_desc(queue, i);
1346 macb_set_addr(bp, desc, addr);
1348 addr += bp->rx_buffer_size;
1350 desc->addr |= MACB_BIT(RX_WRAP);
1354 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1357 struct macb *bp = queue->bp;
1358 bool reset_rx_queue = false;
1361 int first_frag = -1;
1363 for (tail = queue->rx_tail; budget > 0; tail++) {
1364 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1367 /* Make hw descriptor updates visible to CPU */
1370 if (!(desc->addr & MACB_BIT(RX_USED)))
1373 /* Ensure ctrl is at least as up-to-date as addr */
1378 if (ctrl & MACB_BIT(RX_SOF)) {
1379 if (first_frag != -1)
1380 discard_partial_frame(queue, first_frag, tail);
1384 if (ctrl & MACB_BIT(RX_EOF)) {
1387 if (unlikely(first_frag == -1)) {
1388 reset_rx_queue = true;
1392 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1394 if (unlikely(dropped < 0)) {
1395 reset_rx_queue = true;
1405 if (unlikely(reset_rx_queue)) {
1406 unsigned long flags;
1409 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1411 spin_lock_irqsave(&bp->lock, flags);
1413 ctrl = macb_readl(bp, NCR);
1414 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1416 macb_init_rx_ring(queue);
1417 queue_writel(queue, RBQP, queue->rx_ring_dma);
1419 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1421 spin_unlock_irqrestore(&bp->lock, flags);
1425 if (first_frag != -1)
1426 queue->rx_tail = first_frag;
1428 queue->rx_tail = tail;
1433 static int macb_poll(struct napi_struct *napi, int budget)
1435 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1436 struct macb *bp = queue->bp;
1440 status = macb_readl(bp, RSR);
1441 macb_writel(bp, RSR, status);
1443 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1444 (unsigned long)status, budget);
1446 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1447 if (work_done < budget) {
1448 napi_complete_done(napi, work_done);
1450 /* Packets received while interrupts were disabled */
1451 status = macb_readl(bp, RSR);
1453 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1454 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1455 napi_reschedule(napi);
1457 queue_writel(queue, IER, bp->rx_intr_mask);
1461 /* TODO: Handle errors */
1466 static void macb_hresp_error_task(unsigned long data)
1468 struct macb *bp = (struct macb *)data;
1469 struct net_device *dev = bp->dev;
1470 struct macb_queue *queue;
1474 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1475 queue_writel(queue, IDR, bp->rx_intr_mask |
1479 ctrl = macb_readl(bp, NCR);
1480 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1481 macb_writel(bp, NCR, ctrl);
1483 netif_tx_stop_all_queues(dev);
1484 netif_carrier_off(dev);
1486 bp->macbgem_ops.mog_init_rings(bp);
1488 /* Initialize TX and RX buffers */
1489 macb_init_buffers(bp);
1491 /* Enable interrupts */
1492 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1493 queue_writel(queue, IER,
1498 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1499 macb_writel(bp, NCR, ctrl);
1501 netif_carrier_on(dev);
1502 netif_tx_start_all_queues(dev);
1505 static void macb_tx_restart(struct macb_queue *queue)
1507 unsigned int head = queue->tx_head;
1508 unsigned int tail = queue->tx_tail;
1509 struct macb *bp = queue->bp;
1511 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1512 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1517 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1520 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1522 struct macb_queue *queue = dev_id;
1523 struct macb *bp = queue->bp;
1526 status = queue_readl(queue, ISR);
1528 if (unlikely(!status))
1531 spin_lock(&bp->lock);
1533 if (status & MACB_BIT(WOL)) {
1534 queue_writel(queue, IDR, MACB_BIT(WOL));
1535 macb_writel(bp, WOL, 0);
1536 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1537 (unsigned int)(queue - bp->queues),
1538 (unsigned long)status);
1539 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1540 queue_writel(queue, ISR, MACB_BIT(WOL));
1541 pm_wakeup_event(&bp->pdev->dev, 0);
1544 spin_unlock(&bp->lock);
1549 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1551 struct macb_queue *queue = dev_id;
1552 struct macb *bp = queue->bp;
1555 status = queue_readl(queue, ISR);
1557 if (unlikely(!status))
1560 spin_lock(&bp->lock);
1562 if (status & GEM_BIT(WOL)) {
1563 queue_writel(queue, IDR, GEM_BIT(WOL));
1564 gem_writel(bp, WOL, 0);
1565 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1566 (unsigned int)(queue - bp->queues),
1567 (unsigned long)status);
1568 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1569 queue_writel(queue, ISR, GEM_BIT(WOL));
1570 pm_wakeup_event(&bp->pdev->dev, 0);
1573 spin_unlock(&bp->lock);
1578 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1580 struct macb_queue *queue = dev_id;
1581 struct macb *bp = queue->bp;
1582 struct net_device *dev = bp->dev;
1585 status = queue_readl(queue, ISR);
1587 if (unlikely(!status))
1590 spin_lock(&bp->lock);
1593 /* close possible race with dev_close */
1594 if (unlikely(!netif_running(dev))) {
1595 queue_writel(queue, IDR, -1);
1596 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1597 queue_writel(queue, ISR, -1);
1601 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1602 (unsigned int)(queue - bp->queues),
1603 (unsigned long)status);
1605 if (status & bp->rx_intr_mask) {
1606 /* There's no point taking any more interrupts
1607 * until we have processed the buffers. The
1608 * scheduling call may fail if the poll routine
1609 * is already scheduled, so disable interrupts
1612 queue_writel(queue, IDR, bp->rx_intr_mask);
1613 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1614 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1616 if (napi_schedule_prep(&queue->napi)) {
1617 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1618 __napi_schedule(&queue->napi);
1622 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1623 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1624 schedule_work(&queue->tx_error_task);
1626 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1627 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1632 if (status & MACB_BIT(TCOMP))
1633 macb_tx_interrupt(queue);
1635 if (status & MACB_BIT(TXUBR))
1636 macb_tx_restart(queue);
1638 /* Link change detection isn't possible with RMII, so we'll
1639 * add that if/when we get our hands on a full-blown MII PHY.
1642 /* There is a hardware issue under heavy load where DMA can
1643 * stop, this causes endless "used buffer descriptor read"
1644 * interrupts but it can be cleared by re-enabling RX. See
1645 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1646 * section 16.7.4 for details. RXUBR is only enabled for
1647 * these two versions.
1649 if (status & MACB_BIT(RXUBR)) {
1650 ctrl = macb_readl(bp, NCR);
1651 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1653 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1655 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1656 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1659 if (status & MACB_BIT(ISR_ROVR)) {
1660 /* We missed at least one packet */
1661 if (macb_is_gem(bp))
1662 bp->hw_stats.gem.rx_overruns++;
1664 bp->hw_stats.macb.rx_overruns++;
1666 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1667 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1670 if (status & MACB_BIT(HRESP)) {
1671 tasklet_schedule(&bp->hresp_err_tasklet);
1672 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1674 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1675 queue_writel(queue, ISR, MACB_BIT(HRESP));
1677 status = queue_readl(queue, ISR);
1680 spin_unlock(&bp->lock);
1685 #ifdef CONFIG_NET_POLL_CONTROLLER
1686 /* Polling receive - used by netconsole and other diagnostic tools
1687 * to allow network i/o with interrupts disabled.
1689 static void macb_poll_controller(struct net_device *dev)
1691 struct macb *bp = netdev_priv(dev);
1692 struct macb_queue *queue;
1693 unsigned long flags;
1696 local_irq_save(flags);
1697 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1698 macb_interrupt(dev->irq, queue);
1699 local_irq_restore(flags);
1703 static unsigned int macb_tx_map(struct macb *bp,
1704 struct macb_queue *queue,
1705 struct sk_buff *skb,
1706 unsigned int hdrlen)
1709 unsigned int len, entry, i, tx_head = queue->tx_head;
1710 struct macb_tx_skb *tx_skb = NULL;
1711 struct macb_dma_desc *desc;
1712 unsigned int offset, size, count = 0;
1713 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1714 unsigned int eof = 1, mss_mfs = 0;
1715 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1718 if (skb_shinfo(skb)->gso_size != 0) {
1719 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1721 lso_ctrl = MACB_LSO_UFO_ENABLE;
1724 lso_ctrl = MACB_LSO_TSO_ENABLE;
1727 /* First, map non-paged data */
1728 len = skb_headlen(skb);
1730 /* first buffer length */
1735 entry = macb_tx_ring_wrap(bp, tx_head);
1736 tx_skb = &queue->tx_skb[entry];
1738 mapping = dma_map_single(&bp->pdev->dev,
1740 size, DMA_TO_DEVICE);
1741 if (dma_mapping_error(&bp->pdev->dev, mapping))
1744 /* Save info to properly release resources */
1746 tx_skb->mapping = mapping;
1747 tx_skb->size = size;
1748 tx_skb->mapped_as_page = false;
1755 size = min(len, bp->max_tx_length);
1758 /* Then, map paged data from fragments */
1759 for (f = 0; f < nr_frags; f++) {
1760 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1762 len = skb_frag_size(frag);
1765 size = min(len, bp->max_tx_length);
1766 entry = macb_tx_ring_wrap(bp, tx_head);
1767 tx_skb = &queue->tx_skb[entry];
1769 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1770 offset, size, DMA_TO_DEVICE);
1771 if (dma_mapping_error(&bp->pdev->dev, mapping))
1774 /* Save info to properly release resources */
1776 tx_skb->mapping = mapping;
1777 tx_skb->size = size;
1778 tx_skb->mapped_as_page = true;
1787 /* Should never happen */
1788 if (unlikely(!tx_skb)) {
1789 netdev_err(bp->dev, "BUG! empty skb!\n");
1793 /* This is the last buffer of the frame: save socket buffer */
1796 /* Update TX ring: update buffer descriptors in reverse order
1797 * to avoid race condition
1800 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1801 * to set the end of TX queue
1804 entry = macb_tx_ring_wrap(bp, i);
1805 ctrl = MACB_BIT(TX_USED);
1806 desc = macb_tx_desc(queue, entry);
1810 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1811 /* include header and FCS in value given to h/w */
1812 mss_mfs = skb_shinfo(skb)->gso_size +
1813 skb_transport_offset(skb) +
1816 mss_mfs = skb_shinfo(skb)->gso_size;
1817 /* TCP Sequence Number Source Select
1818 * can be set only for TSO
1826 entry = macb_tx_ring_wrap(bp, i);
1827 tx_skb = &queue->tx_skb[entry];
1828 desc = macb_tx_desc(queue, entry);
1830 ctrl = (u32)tx_skb->size;
1832 ctrl |= MACB_BIT(TX_LAST);
1835 if (unlikely(entry == (bp->tx_ring_size - 1)))
1836 ctrl |= MACB_BIT(TX_WRAP);
1838 /* First descriptor is header descriptor */
1839 if (i == queue->tx_head) {
1840 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1841 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1842 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1843 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1844 ctrl |= MACB_BIT(TX_NOCRC);
1846 /* Only set MSS/MFS on payload descriptors
1847 * (second or later descriptor)
1849 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1851 /* Set TX buffer descriptor */
1852 macb_set_addr(bp, desc, tx_skb->mapping);
1853 /* desc->addr must be visible to hardware before clearing
1854 * 'TX_USED' bit in desc->ctrl.
1858 } while (i != queue->tx_head);
1860 queue->tx_head = tx_head;
1865 netdev_err(bp->dev, "TX DMA map failed\n");
1867 for (i = queue->tx_head; i != tx_head; i++) {
1868 tx_skb = macb_tx_skb(queue, i);
1870 macb_tx_unmap(bp, tx_skb);
1876 static netdev_features_t macb_features_check(struct sk_buff *skb,
1877 struct net_device *dev,
1878 netdev_features_t features)
1880 unsigned int nr_frags, f;
1881 unsigned int hdrlen;
1883 /* Validate LSO compatibility */
1885 /* there is only one buffer or protocol is not UDP */
1886 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1889 /* length of header */
1890 hdrlen = skb_transport_offset(skb);
1893 * When software supplies two or more payload buffers all payload buffers
1894 * apart from the last must be a multiple of 8 bytes in size.
1896 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1897 return features & ~MACB_NETIF_LSO;
1899 nr_frags = skb_shinfo(skb)->nr_frags;
1900 /* No need to check last fragment */
1902 for (f = 0; f < nr_frags; f++) {
1903 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1905 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1906 return features & ~MACB_NETIF_LSO;
1911 static inline int macb_clear_csum(struct sk_buff *skb)
1913 /* no change for packets without checksum offloading */
1914 if (skb->ip_summed != CHECKSUM_PARTIAL)
1917 /* make sure we can modify the header */
1918 if (unlikely(skb_cow_head(skb, 0)))
1921 /* initialize checksum field
1922 * This is required - at least for Zynq, which otherwise calculates
1923 * wrong UDP header checksums for UDP packets with UDP data len <=2
1925 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1929 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1931 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1932 int padlen = ETH_ZLEN - (*skb)->len;
1933 int headroom = skb_headroom(*skb);
1934 int tailroom = skb_tailroom(*skb);
1935 struct sk_buff *nskb;
1938 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1939 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1940 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1944 /* FCS could be appeded to tailroom. */
1945 if (tailroom >= ETH_FCS_LEN)
1947 /* FCS could be appeded by moving data to headroom. */
1948 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1950 /* No room for FCS, need to reallocate skb. */
1952 padlen = ETH_FCS_LEN;
1954 /* Add room for FCS. */
1955 padlen += ETH_FCS_LEN;
1958 if (!cloned && headroom + tailroom >= padlen) {
1959 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1960 skb_set_tail_pointer(*skb, (*skb)->len);
1962 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1966 dev_consume_skb_any(*skb);
1970 if (padlen > ETH_FCS_LEN)
1971 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1974 /* set FCS to packet */
1975 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1978 skb_put_u8(*skb, fcs & 0xff);
1979 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1980 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1981 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1986 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1988 u16 queue_index = skb_get_queue_mapping(skb);
1989 struct macb *bp = netdev_priv(dev);
1990 struct macb_queue *queue = &bp->queues[queue_index];
1991 unsigned long flags;
1992 unsigned int desc_cnt, nr_frags, frag_size, f;
1993 unsigned int hdrlen;
1995 netdev_tx_t ret = NETDEV_TX_OK;
1997 if (macb_clear_csum(skb)) {
1998 dev_kfree_skb_any(skb);
2002 if (macb_pad_and_fcs(&skb, dev)) {
2003 dev_kfree_skb_any(skb);
2007 is_lso = (skb_shinfo(skb)->gso_size != 0);
2010 /* length of headers */
2011 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2012 /* only queue eth + ip headers separately for UDP */
2013 hdrlen = skb_transport_offset(skb);
2015 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
2016 if (skb_headlen(skb) < hdrlen) {
2017 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2018 /* if this is required, would need to copy to single buffer */
2019 return NETDEV_TX_BUSY;
2022 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2024 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2025 netdev_vdbg(bp->dev,
2026 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2027 queue_index, skb->len, skb->head, skb->data,
2028 skb_tail_pointer(skb), skb_end_pointer(skb));
2029 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2030 skb->data, 16, true);
2033 /* Count how many TX buffer descriptors are needed to send this
2034 * socket buffer: skb fragments of jumbo frames may need to be
2035 * split into many buffer descriptors.
2037 if (is_lso && (skb_headlen(skb) > hdrlen))
2038 /* extra header descriptor if also payload in first buffer */
2039 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2041 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2042 nr_frags = skb_shinfo(skb)->nr_frags;
2043 for (f = 0; f < nr_frags; f++) {
2044 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2045 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2048 spin_lock_irqsave(&bp->lock, flags);
2050 /* This is a hard error, log it. */
2051 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2052 bp->tx_ring_size) < desc_cnt) {
2053 netif_stop_subqueue(dev, queue_index);
2054 spin_unlock_irqrestore(&bp->lock, flags);
2055 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2056 queue->tx_head, queue->tx_tail);
2057 return NETDEV_TX_BUSY;
2060 /* Map socket buffer for DMA transfer */
2061 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2062 dev_kfree_skb_any(skb);
2066 /* Make newly initialized descriptor visible to hardware */
2068 skb_tx_timestamp(skb);
2070 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2072 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2073 netif_stop_subqueue(dev, queue_index);
2076 spin_unlock_irqrestore(&bp->lock, flags);
2081 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2083 if (!macb_is_gem(bp)) {
2084 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2086 bp->rx_buffer_size = size;
2088 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2090 "RX buffer must be multiple of %d bytes, expanding\n",
2091 RX_BUFFER_MULTIPLE);
2092 bp->rx_buffer_size =
2093 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2097 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2098 bp->dev->mtu, bp->rx_buffer_size);
2101 static void gem_free_rx_buffers(struct macb *bp)
2103 struct sk_buff *skb;
2104 struct macb_dma_desc *desc;
2105 struct macb_queue *queue;
2110 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2111 if (!queue->rx_skbuff)
2114 for (i = 0; i < bp->rx_ring_size; i++) {
2115 skb = queue->rx_skbuff[i];
2120 desc = macb_rx_desc(queue, i);
2121 addr = macb_get_addr(bp, desc);
2123 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2125 dev_kfree_skb_any(skb);
2129 kfree(queue->rx_skbuff);
2130 queue->rx_skbuff = NULL;
2134 static void macb_free_rx_buffers(struct macb *bp)
2136 struct macb_queue *queue = &bp->queues[0];
2138 if (queue->rx_buffers) {
2139 dma_free_coherent(&bp->pdev->dev,
2140 bp->rx_ring_size * bp->rx_buffer_size,
2141 queue->rx_buffers, queue->rx_buffers_dma);
2142 queue->rx_buffers = NULL;
2146 static void macb_free_consistent(struct macb *bp)
2148 struct macb_queue *queue;
2152 bp->macbgem_ops.mog_free_rx_buffers(bp);
2154 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2155 kfree(queue->tx_skb);
2156 queue->tx_skb = NULL;
2157 if (queue->tx_ring) {
2158 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2159 dma_free_coherent(&bp->pdev->dev, size,
2160 queue->tx_ring, queue->tx_ring_dma);
2161 queue->tx_ring = NULL;
2163 if (queue->rx_ring) {
2164 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2165 dma_free_coherent(&bp->pdev->dev, size,
2166 queue->rx_ring, queue->rx_ring_dma);
2167 queue->rx_ring = NULL;
2172 static int gem_alloc_rx_buffers(struct macb *bp)
2174 struct macb_queue *queue;
2178 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2179 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2180 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2181 if (!queue->rx_skbuff)
2185 "Allocated %d RX struct sk_buff entries at %p\n",
2186 bp->rx_ring_size, queue->rx_skbuff);
2191 static int macb_alloc_rx_buffers(struct macb *bp)
2193 struct macb_queue *queue = &bp->queues[0];
2196 size = bp->rx_ring_size * bp->rx_buffer_size;
2197 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2198 &queue->rx_buffers_dma, GFP_KERNEL);
2199 if (!queue->rx_buffers)
2203 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2204 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2208 static int macb_alloc_consistent(struct macb *bp)
2210 struct macb_queue *queue;
2214 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2215 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2216 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2217 &queue->tx_ring_dma,
2219 if (!queue->tx_ring)
2222 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2223 q, size, (unsigned long)queue->tx_ring_dma,
2226 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2227 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2231 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2232 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2233 &queue->rx_ring_dma, GFP_KERNEL);
2234 if (!queue->rx_ring)
2237 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2238 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2240 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2246 macb_free_consistent(bp);
2250 static void gem_init_rings(struct macb *bp)
2252 struct macb_queue *queue;
2253 struct macb_dma_desc *desc = NULL;
2257 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2258 for (i = 0; i < bp->tx_ring_size; i++) {
2259 desc = macb_tx_desc(queue, i);
2260 macb_set_addr(bp, desc, 0);
2261 desc->ctrl = MACB_BIT(TX_USED);
2263 desc->ctrl |= MACB_BIT(TX_WRAP);
2268 queue->rx_prepared_head = 0;
2270 gem_rx_refill(queue);
2275 static void macb_init_rings(struct macb *bp)
2278 struct macb_dma_desc *desc = NULL;
2280 macb_init_rx_ring(&bp->queues[0]);
2282 for (i = 0; i < bp->tx_ring_size; i++) {
2283 desc = macb_tx_desc(&bp->queues[0], i);
2284 macb_set_addr(bp, desc, 0);
2285 desc->ctrl = MACB_BIT(TX_USED);
2287 bp->queues[0].tx_head = 0;
2288 bp->queues[0].tx_tail = 0;
2289 desc->ctrl |= MACB_BIT(TX_WRAP);
2292 static void macb_reset_hw(struct macb *bp)
2294 struct macb_queue *queue;
2296 u32 ctrl = macb_readl(bp, NCR);
2298 /* Disable RX and TX (XXX: Should we halt the transmission
2301 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2303 /* Clear the stats registers (XXX: Update stats first?) */
2304 ctrl |= MACB_BIT(CLRSTAT);
2306 macb_writel(bp, NCR, ctrl);
2308 /* Clear all status flags */
2309 macb_writel(bp, TSR, -1);
2310 macb_writel(bp, RSR, -1);
2312 /* Disable all interrupts */
2313 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2314 queue_writel(queue, IDR, -1);
2315 queue_readl(queue, ISR);
2316 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2317 queue_writel(queue, ISR, -1);
2321 static u32 gem_mdc_clk_div(struct macb *bp)
2324 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2326 if (pclk_hz <= 20000000)
2327 config = GEM_BF(CLK, GEM_CLK_DIV8);
2328 else if (pclk_hz <= 40000000)
2329 config = GEM_BF(CLK, GEM_CLK_DIV16);
2330 else if (pclk_hz <= 80000000)
2331 config = GEM_BF(CLK, GEM_CLK_DIV32);
2332 else if (pclk_hz <= 120000000)
2333 config = GEM_BF(CLK, GEM_CLK_DIV48);
2334 else if (pclk_hz <= 160000000)
2335 config = GEM_BF(CLK, GEM_CLK_DIV64);
2337 config = GEM_BF(CLK, GEM_CLK_DIV96);
2342 static u32 macb_mdc_clk_div(struct macb *bp)
2345 unsigned long pclk_hz;
2347 if (macb_is_gem(bp))
2348 return gem_mdc_clk_div(bp);
2350 pclk_hz = clk_get_rate(bp->pclk);
2351 if (pclk_hz <= 20000000)
2352 config = MACB_BF(CLK, MACB_CLK_DIV8);
2353 else if (pclk_hz <= 40000000)
2354 config = MACB_BF(CLK, MACB_CLK_DIV16);
2355 else if (pclk_hz <= 80000000)
2356 config = MACB_BF(CLK, MACB_CLK_DIV32);
2358 config = MACB_BF(CLK, MACB_CLK_DIV64);
2363 /* Get the DMA bus width field of the network configuration register that we
2364 * should program. We find the width from decoding the design configuration
2365 * register to find the maximum supported data bus width.
2367 static u32 macb_dbw(struct macb *bp)
2369 if (!macb_is_gem(bp))
2372 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2374 return GEM_BF(DBW, GEM_DBW128);
2376 return GEM_BF(DBW, GEM_DBW64);
2379 return GEM_BF(DBW, GEM_DBW32);
2383 /* Configure the receive DMA engine
2384 * - use the correct receive buffer size
2385 * - set best burst length for DMA operations
2386 * (if not supported by FIFO, it will fallback to default)
2387 * - set both rx/tx packet buffers to full memory size
2388 * These are configurable parameters for GEM.
2390 static void macb_configure_dma(struct macb *bp)
2392 struct macb_queue *queue;
2397 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2398 if (macb_is_gem(bp)) {
2399 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2400 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2402 queue_writel(queue, RBQS, buffer_size);
2404 dmacfg |= GEM_BF(RXBS, buffer_size);
2406 if (bp->dma_burst_length)
2407 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2408 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2409 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2412 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2414 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2416 if (bp->dev->features & NETIF_F_HW_CSUM)
2417 dmacfg |= GEM_BIT(TXCOEN);
2419 dmacfg &= ~GEM_BIT(TXCOEN);
2421 dmacfg &= ~GEM_BIT(ADDR64);
2422 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2423 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2424 dmacfg |= GEM_BIT(ADDR64);
2426 #ifdef CONFIG_MACB_USE_HWSTAMP
2427 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2428 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2430 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2432 gem_writel(bp, DMACFG, dmacfg);
2436 static void macb_init_hw(struct macb *bp)
2441 macb_set_hwaddr(bp);
2443 config = macb_mdc_clk_div(bp);
2444 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2445 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2446 if (bp->caps & MACB_CAPS_JUMBO)
2447 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2449 config |= MACB_BIT(BIG); /* Receive oversized frames */
2450 if (bp->dev->flags & IFF_PROMISC)
2451 config |= MACB_BIT(CAF); /* Copy All Frames */
2452 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2453 config |= GEM_BIT(RXCOEN);
2454 if (!(bp->dev->flags & IFF_BROADCAST))
2455 config |= MACB_BIT(NBC); /* No BroadCast */
2456 config |= macb_dbw(bp);
2457 macb_writel(bp, NCFGR, config);
2458 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2459 gem_writel(bp, JML, bp->jumbo_max_len);
2460 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2461 if (bp->caps & MACB_CAPS_JUMBO)
2462 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2464 macb_configure_dma(bp);
2467 /* The hash address register is 64 bits long and takes up two
2468 * locations in the memory map. The least significant bits are stored
2469 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2471 * The unicast hash enable and the multicast hash enable bits in the
2472 * network configuration register enable the reception of hash matched
2473 * frames. The destination address is reduced to a 6 bit index into
2474 * the 64 bit hash register using the following hash function. The
2475 * hash function is an exclusive or of every sixth bit of the
2476 * destination address.
2478 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2479 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2480 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2481 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2482 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2483 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2485 * da[0] represents the least significant bit of the first byte
2486 * received, that is, the multicast/unicast indicator, and da[47]
2487 * represents the most significant bit of the last byte received. If
2488 * the hash index, hi[n], points to a bit that is set in the hash
2489 * register then the frame will be matched according to whether the
2490 * frame is multicast or unicast. A multicast match will be signalled
2491 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2492 * index points to a bit set in the hash register. A unicast match
2493 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2494 * and the hash index points to a bit set in the hash register. To
2495 * receive all multicast frames, the hash register should be set with
2496 * all ones and the multicast hash enable bit should be set in the
2497 * network configuration register.
2500 static inline int hash_bit_value(int bitnr, __u8 *addr)
2502 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2507 /* Return the hash index value for the specified address. */
2508 static int hash_get_index(__u8 *addr)
2513 for (j = 0; j < 6; j++) {
2514 for (i = 0, bitval = 0; i < 8; i++)
2515 bitval ^= hash_bit_value(i * 6 + j, addr);
2517 hash_index |= (bitval << j);
2523 /* Add multicast addresses to the internal multicast-hash table. */
2524 static void macb_sethashtable(struct net_device *dev)
2526 struct netdev_hw_addr *ha;
2527 unsigned long mc_filter[2];
2529 struct macb *bp = netdev_priv(dev);
2534 netdev_for_each_mc_addr(ha, dev) {
2535 bitnr = hash_get_index(ha->addr);
2536 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2539 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2540 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2543 /* Enable/Disable promiscuous and multicast modes. */
2544 static void macb_set_rx_mode(struct net_device *dev)
2547 struct macb *bp = netdev_priv(dev);
2549 cfg = macb_readl(bp, NCFGR);
2551 if (dev->flags & IFF_PROMISC) {
2552 /* Enable promiscuous mode */
2553 cfg |= MACB_BIT(CAF);
2555 /* Disable RX checksum offload */
2556 if (macb_is_gem(bp))
2557 cfg &= ~GEM_BIT(RXCOEN);
2559 /* Disable promiscuous mode */
2560 cfg &= ~MACB_BIT(CAF);
2562 /* Enable RX checksum offload only if requested */
2563 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2564 cfg |= GEM_BIT(RXCOEN);
2567 if (dev->flags & IFF_ALLMULTI) {
2568 /* Enable all multicast mode */
2569 macb_or_gem_writel(bp, HRB, -1);
2570 macb_or_gem_writel(bp, HRT, -1);
2571 cfg |= MACB_BIT(NCFGR_MTI);
2572 } else if (!netdev_mc_empty(dev)) {
2573 /* Enable specific multicasts */
2574 macb_sethashtable(dev);
2575 cfg |= MACB_BIT(NCFGR_MTI);
2576 } else if (dev->flags & (~IFF_ALLMULTI)) {
2577 /* Disable all multicast mode */
2578 macb_or_gem_writel(bp, HRB, 0);
2579 macb_or_gem_writel(bp, HRT, 0);
2580 cfg &= ~MACB_BIT(NCFGR_MTI);
2583 macb_writel(bp, NCFGR, cfg);
2586 static int macb_open(struct net_device *dev)
2588 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2589 struct macb *bp = netdev_priv(dev);
2590 struct macb_queue *queue;
2594 netdev_dbg(bp->dev, "open\n");
2596 err = pm_runtime_get_sync(&bp->pdev->dev);
2600 /* RX buffers initialization */
2601 macb_init_rx_buffer_size(bp, bufsz);
2603 err = macb_alloc_consistent(bp);
2605 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2610 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2611 napi_enable(&queue->napi);
2615 err = macb_phylink_connect(bp);
2619 netif_tx_start_all_queues(dev);
2622 bp->ptp_info->ptp_init(dev);
2628 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2629 napi_disable(&queue->napi);
2630 macb_free_consistent(bp);
2632 pm_runtime_put_sync(&bp->pdev->dev);
2636 static int macb_close(struct net_device *dev)
2638 struct macb *bp = netdev_priv(dev);
2639 struct macb_queue *queue;
2640 unsigned long flags;
2643 netif_tx_stop_all_queues(dev);
2645 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2646 napi_disable(&queue->napi);
2648 phylink_stop(bp->phylink);
2649 phylink_disconnect_phy(bp->phylink);
2651 spin_lock_irqsave(&bp->lock, flags);
2653 netif_carrier_off(dev);
2654 spin_unlock_irqrestore(&bp->lock, flags);
2656 macb_free_consistent(bp);
2659 bp->ptp_info->ptp_remove(dev);
2661 pm_runtime_put(&bp->pdev->dev);
2666 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2668 if (netif_running(dev))
2676 static void gem_update_stats(struct macb *bp)
2678 struct macb_queue *queue;
2679 unsigned int i, q, idx;
2680 unsigned long *stat;
2682 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2684 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2685 u32 offset = gem_statistics[i].offset;
2686 u64 val = bp->macb_reg_readl(bp, offset);
2688 bp->ethtool_stats[i] += val;
2691 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2692 /* Add GEM_OCTTXH, GEM_OCTRXH */
2693 val = bp->macb_reg_readl(bp, offset + 4);
2694 bp->ethtool_stats[i] += ((u64)val) << 32;
2699 idx = GEM_STATS_LEN;
2700 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2701 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2702 bp->ethtool_stats[idx++] = *stat;
2705 static struct net_device_stats *gem_get_stats(struct macb *bp)
2707 struct gem_stats *hwstat = &bp->hw_stats.gem;
2708 struct net_device_stats *nstat = &bp->dev->stats;
2710 gem_update_stats(bp);
2712 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2713 hwstat->rx_alignment_errors +
2714 hwstat->rx_resource_errors +
2715 hwstat->rx_overruns +
2716 hwstat->rx_oversize_frames +
2717 hwstat->rx_jabbers +
2718 hwstat->rx_undersized_frames +
2719 hwstat->rx_length_field_frame_errors);
2720 nstat->tx_errors = (hwstat->tx_late_collisions +
2721 hwstat->tx_excessive_collisions +
2722 hwstat->tx_underrun +
2723 hwstat->tx_carrier_sense_errors);
2724 nstat->multicast = hwstat->rx_multicast_frames;
2725 nstat->collisions = (hwstat->tx_single_collision_frames +
2726 hwstat->tx_multiple_collision_frames +
2727 hwstat->tx_excessive_collisions);
2728 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2729 hwstat->rx_jabbers +
2730 hwstat->rx_undersized_frames +
2731 hwstat->rx_length_field_frame_errors);
2732 nstat->rx_over_errors = hwstat->rx_resource_errors;
2733 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2734 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2735 nstat->rx_fifo_errors = hwstat->rx_overruns;
2736 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2737 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2738 nstat->tx_fifo_errors = hwstat->tx_underrun;
2743 static void gem_get_ethtool_stats(struct net_device *dev,
2744 struct ethtool_stats *stats, u64 *data)
2748 bp = netdev_priv(dev);
2749 gem_update_stats(bp);
2750 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2751 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2754 static int gem_get_sset_count(struct net_device *dev, int sset)
2756 struct macb *bp = netdev_priv(dev);
2760 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2766 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2768 char stat_string[ETH_GSTRING_LEN];
2769 struct macb *bp = netdev_priv(dev);
2770 struct macb_queue *queue;
2776 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2777 memcpy(p, gem_statistics[i].stat_string,
2780 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2781 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2782 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2783 q, queue_statistics[i].stat_string);
2784 memcpy(p, stat_string, ETH_GSTRING_LEN);
2791 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2793 struct macb *bp = netdev_priv(dev);
2794 struct net_device_stats *nstat = &bp->dev->stats;
2795 struct macb_stats *hwstat = &bp->hw_stats.macb;
2797 if (macb_is_gem(bp))
2798 return gem_get_stats(bp);
2800 /* read stats from hardware */
2801 macb_update_stats(bp);
2803 /* Convert HW stats into netdevice stats */
2804 nstat->rx_errors = (hwstat->rx_fcs_errors +
2805 hwstat->rx_align_errors +
2806 hwstat->rx_resource_errors +
2807 hwstat->rx_overruns +
2808 hwstat->rx_oversize_pkts +
2809 hwstat->rx_jabbers +
2810 hwstat->rx_undersize_pkts +
2811 hwstat->rx_length_mismatch);
2812 nstat->tx_errors = (hwstat->tx_late_cols +
2813 hwstat->tx_excessive_cols +
2814 hwstat->tx_underruns +
2815 hwstat->tx_carrier_errors +
2816 hwstat->sqe_test_errors);
2817 nstat->collisions = (hwstat->tx_single_cols +
2818 hwstat->tx_multiple_cols +
2819 hwstat->tx_excessive_cols);
2820 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2821 hwstat->rx_jabbers +
2822 hwstat->rx_undersize_pkts +
2823 hwstat->rx_length_mismatch);
2824 nstat->rx_over_errors = hwstat->rx_resource_errors +
2825 hwstat->rx_overruns;
2826 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2827 nstat->rx_frame_errors = hwstat->rx_align_errors;
2828 nstat->rx_fifo_errors = hwstat->rx_overruns;
2829 /* XXX: What does "missed" mean? */
2830 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2831 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2832 nstat->tx_fifo_errors = hwstat->tx_underruns;
2833 /* Don't know about heartbeat or window errors... */
2838 static int macb_get_regs_len(struct net_device *netdev)
2840 return MACB_GREGS_NBR * sizeof(u32);
2843 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2846 struct macb *bp = netdev_priv(dev);
2847 unsigned int tail, head;
2850 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2851 | MACB_GREGS_VERSION;
2853 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2854 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2856 regs_buff[0] = macb_readl(bp, NCR);
2857 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2858 regs_buff[2] = macb_readl(bp, NSR);
2859 regs_buff[3] = macb_readl(bp, TSR);
2860 regs_buff[4] = macb_readl(bp, RBQP);
2861 regs_buff[5] = macb_readl(bp, TBQP);
2862 regs_buff[6] = macb_readl(bp, RSR);
2863 regs_buff[7] = macb_readl(bp, IMR);
2865 regs_buff[8] = tail;
2866 regs_buff[9] = head;
2867 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2868 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2870 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2871 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2872 if (macb_is_gem(bp))
2873 regs_buff[13] = gem_readl(bp, DMACFG);
2876 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2878 struct macb *bp = netdev_priv(netdev);
2880 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2881 phylink_ethtool_get_wol(bp->phylink, wol);
2882 wol->supported |= WAKE_MAGIC;
2884 if (bp->wol & MACB_WOL_ENABLED)
2885 wol->wolopts |= WAKE_MAGIC;
2889 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2891 struct macb *bp = netdev_priv(netdev);
2894 /* Pass the order to phylink layer */
2895 ret = phylink_ethtool_set_wol(bp->phylink, wol);
2896 /* Don't manage WoL on MAC if handled by the PHY
2897 * or if there's a failure in talking to the PHY
2899 if (!ret || ret != -EOPNOTSUPP)
2902 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2903 (wol->wolopts & ~WAKE_MAGIC))
2906 if (wol->wolopts & WAKE_MAGIC)
2907 bp->wol |= MACB_WOL_ENABLED;
2909 bp->wol &= ~MACB_WOL_ENABLED;
2911 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2916 static int macb_get_link_ksettings(struct net_device *netdev,
2917 struct ethtool_link_ksettings *kset)
2919 struct macb *bp = netdev_priv(netdev);
2921 return phylink_ethtool_ksettings_get(bp->phylink, kset);
2924 static int macb_set_link_ksettings(struct net_device *netdev,
2925 const struct ethtool_link_ksettings *kset)
2927 struct macb *bp = netdev_priv(netdev);
2929 return phylink_ethtool_ksettings_set(bp->phylink, kset);
2932 static void macb_get_ringparam(struct net_device *netdev,
2933 struct ethtool_ringparam *ring)
2935 struct macb *bp = netdev_priv(netdev);
2937 ring->rx_max_pending = MAX_RX_RING_SIZE;
2938 ring->tx_max_pending = MAX_TX_RING_SIZE;
2940 ring->rx_pending = bp->rx_ring_size;
2941 ring->tx_pending = bp->tx_ring_size;
2944 static int macb_set_ringparam(struct net_device *netdev,
2945 struct ethtool_ringparam *ring)
2947 struct macb *bp = netdev_priv(netdev);
2948 u32 new_rx_size, new_tx_size;
2949 unsigned int reset = 0;
2951 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2954 new_rx_size = clamp_t(u32, ring->rx_pending,
2955 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2956 new_rx_size = roundup_pow_of_two(new_rx_size);
2958 new_tx_size = clamp_t(u32, ring->tx_pending,
2959 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2960 new_tx_size = roundup_pow_of_two(new_tx_size);
2962 if ((new_tx_size == bp->tx_ring_size) &&
2963 (new_rx_size == bp->rx_ring_size)) {
2968 if (netif_running(bp->dev)) {
2970 macb_close(bp->dev);
2973 bp->rx_ring_size = new_rx_size;
2974 bp->tx_ring_size = new_tx_size;
2982 #ifdef CONFIG_MACB_USE_HWSTAMP
2983 static unsigned int gem_get_tsu_rate(struct macb *bp)
2985 struct clk *tsu_clk;
2986 unsigned int tsu_rate;
2988 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2989 if (!IS_ERR(tsu_clk))
2990 tsu_rate = clk_get_rate(tsu_clk);
2991 /* try pclk instead */
2992 else if (!IS_ERR(bp->pclk)) {
2994 tsu_rate = clk_get_rate(tsu_clk);
3000 static s32 gem_get_ptp_max_adj(void)
3005 static int gem_get_ts_info(struct net_device *dev,
3006 struct ethtool_ts_info *info)
3008 struct macb *bp = netdev_priv(dev);
3010 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3011 ethtool_op_get_ts_info(dev, info);
3015 info->so_timestamping =
3016 SOF_TIMESTAMPING_TX_SOFTWARE |
3017 SOF_TIMESTAMPING_RX_SOFTWARE |
3018 SOF_TIMESTAMPING_SOFTWARE |
3019 SOF_TIMESTAMPING_TX_HARDWARE |
3020 SOF_TIMESTAMPING_RX_HARDWARE |
3021 SOF_TIMESTAMPING_RAW_HARDWARE;
3023 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3024 (1 << HWTSTAMP_TX_OFF) |
3025 (1 << HWTSTAMP_TX_ON);
3027 (1 << HWTSTAMP_FILTER_NONE) |
3028 (1 << HWTSTAMP_FILTER_ALL);
3030 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3035 static struct macb_ptp_info gem_ptp_info = {
3036 .ptp_init = gem_ptp_init,
3037 .ptp_remove = gem_ptp_remove,
3038 .get_ptp_max_adj = gem_get_ptp_max_adj,
3039 .get_tsu_rate = gem_get_tsu_rate,
3040 .get_ts_info = gem_get_ts_info,
3041 .get_hwtst = gem_get_hwtst,
3042 .set_hwtst = gem_set_hwtst,
3046 static int macb_get_ts_info(struct net_device *netdev,
3047 struct ethtool_ts_info *info)
3049 struct macb *bp = netdev_priv(netdev);
3052 return bp->ptp_info->get_ts_info(netdev, info);
3054 return ethtool_op_get_ts_info(netdev, info);
3057 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3059 struct net_device *netdev = bp->dev;
3060 struct ethtool_rx_fs_item *item;
3064 if (!(netdev->features & NETIF_F_NTUPLE))
3067 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3069 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3070 struct ethtool_rx_flow_spec *fs = &item->fs;
3071 struct ethtool_tcpip4_spec *tp4sp_m;
3073 if (fs->location >= num_t2_scr)
3076 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3078 /* enable/disable screener regs for the flow entry */
3079 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3081 /* only enable fields with no masking */
3082 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3084 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3085 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3087 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3089 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3090 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3092 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3094 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3095 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3097 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3099 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3103 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3105 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3106 uint16_t index = fs->location;
3112 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3113 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3115 /* ignore field if any masking set */
3116 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3117 /* 1st compare reg - IP source address */
3120 w0 = tp4sp_v->ip4src;
3121 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3122 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3123 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3124 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3125 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3129 /* ignore field if any masking set */
3130 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3131 /* 2nd compare reg - IP destination address */
3134 w0 = tp4sp_v->ip4dst;
3135 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3136 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3137 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3138 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3139 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3143 /* ignore both port fields if masking set in both */
3144 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3145 /* 3rd compare reg - source port, destination port */
3148 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3149 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3150 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3151 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3152 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3153 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3155 /* only one port definition */
3156 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3157 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3158 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3159 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3160 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3161 } else { /* dst port */
3162 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3163 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3166 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3167 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3172 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3173 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3175 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3177 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3179 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3180 gem_writel_n(bp, SCRT2, index, t2_scr);
3183 static int gem_add_flow_filter(struct net_device *netdev,
3184 struct ethtool_rxnfc *cmd)
3186 struct macb *bp = netdev_priv(netdev);
3187 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3188 struct ethtool_rx_fs_item *item, *newfs;
3189 unsigned long flags;
3193 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3196 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3199 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3200 fs->flow_type, (int)fs->ring_cookie, fs->location,
3201 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3202 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3203 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3205 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3207 /* find correct place to add in list */
3208 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3209 if (item->fs.location > newfs->fs.location) {
3210 list_add_tail(&newfs->list, &item->list);
3213 } else if (item->fs.location == fs->location) {
3214 netdev_err(netdev, "Rule not added: location %d not free!\n",
3221 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3223 gem_prog_cmp_regs(bp, fs);
3224 bp->rx_fs_list.count++;
3225 /* enable filtering if NTUPLE on */
3226 gem_enable_flow_filters(bp, 1);
3228 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3232 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3237 static int gem_del_flow_filter(struct net_device *netdev,
3238 struct ethtool_rxnfc *cmd)
3240 struct macb *bp = netdev_priv(netdev);
3241 struct ethtool_rx_fs_item *item;
3242 struct ethtool_rx_flow_spec *fs;
3243 unsigned long flags;
3245 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3247 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3248 if (item->fs.location == cmd->fs.location) {
3249 /* disable screener regs for the flow entry */
3252 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3253 fs->flow_type, (int)fs->ring_cookie, fs->location,
3254 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3255 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3256 htons(fs->h_u.tcp_ip4_spec.psrc),
3257 htons(fs->h_u.tcp_ip4_spec.pdst));
3259 gem_writel_n(bp, SCRT2, fs->location, 0);
3261 list_del(&item->list);
3262 bp->rx_fs_list.count--;
3263 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3269 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3273 static int gem_get_flow_entry(struct net_device *netdev,
3274 struct ethtool_rxnfc *cmd)
3276 struct macb *bp = netdev_priv(netdev);
3277 struct ethtool_rx_fs_item *item;
3279 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3280 if (item->fs.location == cmd->fs.location) {
3281 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3288 static int gem_get_all_flow_entries(struct net_device *netdev,
3289 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3291 struct macb *bp = netdev_priv(netdev);
3292 struct ethtool_rx_fs_item *item;
3295 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3296 if (cnt == cmd->rule_cnt)
3298 rule_locs[cnt] = item->fs.location;
3301 cmd->data = bp->max_tuples;
3302 cmd->rule_cnt = cnt;
3307 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3310 struct macb *bp = netdev_priv(netdev);
3314 case ETHTOOL_GRXRINGS:
3315 cmd->data = bp->num_queues;
3317 case ETHTOOL_GRXCLSRLCNT:
3318 cmd->rule_cnt = bp->rx_fs_list.count;
3320 case ETHTOOL_GRXCLSRULE:
3321 ret = gem_get_flow_entry(netdev, cmd);
3323 case ETHTOOL_GRXCLSRLALL:
3324 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3328 "Command parameter %d is not supported\n", cmd->cmd);
3335 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3337 struct macb *bp = netdev_priv(netdev);
3341 case ETHTOOL_SRXCLSRLINS:
3342 if ((cmd->fs.location >= bp->max_tuples)
3343 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3347 ret = gem_add_flow_filter(netdev, cmd);
3349 case ETHTOOL_SRXCLSRLDEL:
3350 ret = gem_del_flow_filter(netdev, cmd);
3354 "Command parameter %d is not supported\n", cmd->cmd);
3361 static const struct ethtool_ops macb_ethtool_ops = {
3362 .get_regs_len = macb_get_regs_len,
3363 .get_regs = macb_get_regs,
3364 .get_link = ethtool_op_get_link,
3365 .get_ts_info = ethtool_op_get_ts_info,
3366 .get_wol = macb_get_wol,
3367 .set_wol = macb_set_wol,
3368 .get_link_ksettings = macb_get_link_ksettings,
3369 .set_link_ksettings = macb_set_link_ksettings,
3370 .get_ringparam = macb_get_ringparam,
3371 .set_ringparam = macb_set_ringparam,
3374 static const struct ethtool_ops gem_ethtool_ops = {
3375 .get_regs_len = macb_get_regs_len,
3376 .get_regs = macb_get_regs,
3377 .get_wol = macb_get_wol,
3378 .set_wol = macb_set_wol,
3379 .get_link = ethtool_op_get_link,
3380 .get_ts_info = macb_get_ts_info,
3381 .get_ethtool_stats = gem_get_ethtool_stats,
3382 .get_strings = gem_get_ethtool_strings,
3383 .get_sset_count = gem_get_sset_count,
3384 .get_link_ksettings = macb_get_link_ksettings,
3385 .set_link_ksettings = macb_set_link_ksettings,
3386 .get_ringparam = macb_get_ringparam,
3387 .set_ringparam = macb_set_ringparam,
3388 .get_rxnfc = gem_get_rxnfc,
3389 .set_rxnfc = gem_set_rxnfc,
3392 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3394 struct macb *bp = netdev_priv(dev);
3396 if (!netif_running(dev))
3402 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3404 return bp->ptp_info->get_hwtst(dev, rq);
3408 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3411 static inline void macb_set_txcsum_feature(struct macb *bp,
3412 netdev_features_t features)
3416 if (!macb_is_gem(bp))
3419 val = gem_readl(bp, DMACFG);
3420 if (features & NETIF_F_HW_CSUM)
3421 val |= GEM_BIT(TXCOEN);
3423 val &= ~GEM_BIT(TXCOEN);
3425 gem_writel(bp, DMACFG, val);
3428 static inline void macb_set_rxcsum_feature(struct macb *bp,
3429 netdev_features_t features)
3431 struct net_device *netdev = bp->dev;
3434 if (!macb_is_gem(bp))
3437 val = gem_readl(bp, NCFGR);
3438 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3439 val |= GEM_BIT(RXCOEN);
3441 val &= ~GEM_BIT(RXCOEN);
3443 gem_writel(bp, NCFGR, val);
3446 static inline void macb_set_rxflow_feature(struct macb *bp,
3447 netdev_features_t features)
3449 if (!macb_is_gem(bp))
3452 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3455 static int macb_set_features(struct net_device *netdev,
3456 netdev_features_t features)
3458 struct macb *bp = netdev_priv(netdev);
3459 netdev_features_t changed = features ^ netdev->features;
3461 /* TX checksum offload */
3462 if (changed & NETIF_F_HW_CSUM)
3463 macb_set_txcsum_feature(bp, features);
3465 /* RX checksum offload */
3466 if (changed & NETIF_F_RXCSUM)
3467 macb_set_rxcsum_feature(bp, features);
3469 /* RX Flow Filters */
3470 if (changed & NETIF_F_NTUPLE)
3471 macb_set_rxflow_feature(bp, features);
3476 static void macb_restore_features(struct macb *bp)
3478 struct net_device *netdev = bp->dev;
3479 netdev_features_t features = netdev->features;
3481 /* TX checksum offload */
3482 macb_set_txcsum_feature(bp, features);
3484 /* RX checksum offload */
3485 macb_set_rxcsum_feature(bp, features);
3487 /* RX Flow Filters */
3488 macb_set_rxflow_feature(bp, features);
3491 static const struct net_device_ops macb_netdev_ops = {
3492 .ndo_open = macb_open,
3493 .ndo_stop = macb_close,
3494 .ndo_start_xmit = macb_start_xmit,
3495 .ndo_set_rx_mode = macb_set_rx_mode,
3496 .ndo_get_stats = macb_get_stats,
3497 .ndo_do_ioctl = macb_ioctl,
3498 .ndo_validate_addr = eth_validate_addr,
3499 .ndo_change_mtu = macb_change_mtu,
3500 .ndo_set_mac_address = eth_mac_addr,
3501 #ifdef CONFIG_NET_POLL_CONTROLLER
3502 .ndo_poll_controller = macb_poll_controller,
3504 .ndo_set_features = macb_set_features,
3505 .ndo_features_check = macb_features_check,
3508 /* Configure peripheral capabilities according to device tree
3509 * and integration options used
3511 static void macb_configure_caps(struct macb *bp,
3512 const struct macb_config *dt_conf)
3517 bp->caps = dt_conf->caps;
3519 if (hw_is_gem(bp->regs, bp->native_io)) {
3520 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3522 dcfg = gem_readl(bp, DCFG1);
3523 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3524 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3525 dcfg = gem_readl(bp, DCFG2);
3526 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3527 bp->caps |= MACB_CAPS_FIFO_MODE;
3528 #ifdef CONFIG_MACB_USE_HWSTAMP
3529 if (gem_has_ptp(bp)) {
3530 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3531 dev_err(&bp->pdev->dev,
3532 "GEM doesn't support hardware ptp.\n");
3534 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3535 bp->ptp_info = &gem_ptp_info;
3541 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3544 static void macb_probe_queues(void __iomem *mem,
3546 unsigned int *queue_mask,
3547 unsigned int *num_queues)
3552 /* is it macb or gem ?
3554 * We need to read directly from the hardware here because
3555 * we are early in the probe process and don't have the
3556 * MACB_CAPS_MACB_IS_GEM flag positioned
3558 if (!hw_is_gem(mem, native_io))
3561 /* bit 0 is never set but queue 0 always exists */
3562 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3563 *num_queues = hweight32(*queue_mask);
3566 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3567 struct clk **hclk, struct clk **tx_clk,
3568 struct clk **rx_clk, struct clk **tsu_clk)
3570 struct macb_platform_data *pdata;
3573 pdata = dev_get_platdata(&pdev->dev);
3575 *pclk = pdata->pclk;
3576 *hclk = pdata->hclk;
3578 *pclk = devm_clk_get(&pdev->dev, "pclk");
3579 *hclk = devm_clk_get(&pdev->dev, "hclk");
3582 if (IS_ERR_OR_NULL(*pclk)) {
3583 err = PTR_ERR(*pclk);
3587 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3591 if (IS_ERR_OR_NULL(*hclk)) {
3592 err = PTR_ERR(*hclk);
3596 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3600 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3601 if (IS_ERR(*tx_clk))
3602 return PTR_ERR(*tx_clk);
3604 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3605 if (IS_ERR(*rx_clk))
3606 return PTR_ERR(*rx_clk);
3608 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3609 if (IS_ERR(*tsu_clk))
3610 return PTR_ERR(*tsu_clk);
3612 err = clk_prepare_enable(*pclk);
3614 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3618 err = clk_prepare_enable(*hclk);
3620 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3621 goto err_disable_pclk;
3624 err = clk_prepare_enable(*tx_clk);
3626 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3627 goto err_disable_hclk;
3630 err = clk_prepare_enable(*rx_clk);
3632 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3633 goto err_disable_txclk;
3636 err = clk_prepare_enable(*tsu_clk);
3638 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3639 goto err_disable_rxclk;
3645 clk_disable_unprepare(*rx_clk);
3648 clk_disable_unprepare(*tx_clk);
3651 clk_disable_unprepare(*hclk);
3654 clk_disable_unprepare(*pclk);
3659 static int macb_init(struct platform_device *pdev)
3661 struct net_device *dev = platform_get_drvdata(pdev);
3662 unsigned int hw_q, q;
3663 struct macb *bp = netdev_priv(dev);
3664 struct macb_queue *queue;
3668 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3669 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3671 /* set the queue register mapping once for all: queue0 has a special
3672 * register mapping but we don't want to test the queue index then
3673 * compute the corresponding register offset at run time.
3675 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3676 if (!(bp->queue_mask & (1 << hw_q)))
3679 queue = &bp->queues[q];
3681 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3683 queue->ISR = GEM_ISR(hw_q - 1);
3684 queue->IER = GEM_IER(hw_q - 1);
3685 queue->IDR = GEM_IDR(hw_q - 1);
3686 queue->IMR = GEM_IMR(hw_q - 1);
3687 queue->TBQP = GEM_TBQP(hw_q - 1);
3688 queue->RBQP = GEM_RBQP(hw_q - 1);
3689 queue->RBQS = GEM_RBQS(hw_q - 1);
3690 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3691 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3692 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3693 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3697 /* queue0 uses legacy registers */
3698 queue->ISR = MACB_ISR;
3699 queue->IER = MACB_IER;
3700 queue->IDR = MACB_IDR;
3701 queue->IMR = MACB_IMR;
3702 queue->TBQP = MACB_TBQP;
3703 queue->RBQP = MACB_RBQP;
3704 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3705 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3706 queue->TBQPH = MACB_TBQPH;
3707 queue->RBQPH = MACB_RBQPH;
3712 /* get irq: here we use the linux queue index, not the hardware
3713 * queue index. the queue irq definitions in the device tree
3714 * must remove the optional gaps that could exist in the
3715 * hardware queue mask.
3717 queue->irq = platform_get_irq(pdev, q);
3718 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3719 IRQF_SHARED, dev->name, queue);
3722 "Unable to request IRQ %d (error %d)\n",
3727 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3731 dev->netdev_ops = &macb_netdev_ops;
3733 /* setup appropriated routines according to adapter type */
3734 if (macb_is_gem(bp)) {
3735 bp->max_tx_length = GEM_MAX_TX_LEN;
3736 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3737 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3738 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3739 bp->macbgem_ops.mog_rx = gem_rx;
3740 dev->ethtool_ops = &gem_ethtool_ops;
3742 bp->max_tx_length = MACB_MAX_TX_LEN;
3743 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3744 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3745 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3746 bp->macbgem_ops.mog_rx = macb_rx;
3747 dev->ethtool_ops = &macb_ethtool_ops;
3751 dev->hw_features = NETIF_F_SG;
3753 /* Check LSO capability */
3754 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3755 dev->hw_features |= MACB_NETIF_LSO;
3757 /* Checksum offload is only available on gem with packet buffer */
3758 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3759 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3760 if (bp->caps & MACB_CAPS_SG_DISABLED)
3761 dev->hw_features &= ~NETIF_F_SG;
3762 dev->features = dev->hw_features;
3764 /* Check RX Flow Filters support.
3765 * Max Rx flows set by availability of screeners & compare regs:
3766 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3768 reg = gem_readl(bp, DCFG8);
3769 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3770 GEM_BFEXT(T2SCR, reg));
3771 if (bp->max_tuples > 0) {
3772 /* also needs one ethtype match to check IPv4 */
3773 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3774 /* program this reg now */
3776 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3777 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3778 /* Filtering is supported in hw but don't enable it in kernel now */
3779 dev->hw_features |= NETIF_F_NTUPLE;
3780 /* init Rx flow definitions */
3781 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3782 bp->rx_fs_list.count = 0;
3783 spin_lock_init(&bp->rx_fs_lock);
3788 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3790 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3791 val = GEM_BIT(RGMII);
3792 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3793 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3794 val = MACB_BIT(RMII);
3795 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3796 val = MACB_BIT(MII);
3798 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3799 val |= MACB_BIT(CLKEN);
3801 macb_or_gem_writel(bp, USRIO, val);
3804 /* Set MII management clock divider */
3805 val = macb_mdc_clk_div(bp);
3806 val |= macb_dbw(bp);
3807 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3808 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3809 macb_writel(bp, NCFGR, val);
3814 #if defined(CONFIG_OF)
3815 /* 1518 rounded up */
3816 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3817 /* max number of receive buffers */
3818 #define AT91ETHER_MAX_RX_DESCR 9
3820 static struct sifive_fu540_macb_mgmt *mgmt;
3822 static int at91ether_alloc_coherent(struct macb *lp)
3824 struct macb_queue *q = &lp->queues[0];
3826 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3827 (AT91ETHER_MAX_RX_DESCR *
3828 macb_dma_desc_get_size(lp)),
3829 &q->rx_ring_dma, GFP_KERNEL);
3833 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3834 AT91ETHER_MAX_RX_DESCR *
3835 AT91ETHER_MAX_RBUFF_SZ,
3836 &q->rx_buffers_dma, GFP_KERNEL);
3837 if (!q->rx_buffers) {
3838 dma_free_coherent(&lp->pdev->dev,
3839 AT91ETHER_MAX_RX_DESCR *
3840 macb_dma_desc_get_size(lp),
3841 q->rx_ring, q->rx_ring_dma);
3849 static void at91ether_free_coherent(struct macb *lp)
3851 struct macb_queue *q = &lp->queues[0];
3854 dma_free_coherent(&lp->pdev->dev,
3855 AT91ETHER_MAX_RX_DESCR *
3856 macb_dma_desc_get_size(lp),
3857 q->rx_ring, q->rx_ring_dma);
3861 if (q->rx_buffers) {
3862 dma_free_coherent(&lp->pdev->dev,
3863 AT91ETHER_MAX_RX_DESCR *
3864 AT91ETHER_MAX_RBUFF_SZ,
3865 q->rx_buffers, q->rx_buffers_dma);
3866 q->rx_buffers = NULL;
3870 /* Initialize and start the Receiver and Transmit subsystems */
3871 static int at91ether_start(struct macb *lp)
3873 struct macb_queue *q = &lp->queues[0];
3874 struct macb_dma_desc *desc;
3879 ret = at91ether_alloc_coherent(lp);
3883 addr = q->rx_buffers_dma;
3884 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3885 desc = macb_rx_desc(q, i);
3886 macb_set_addr(lp, desc, addr);
3888 addr += AT91ETHER_MAX_RBUFF_SZ;
3891 /* Set the Wrap bit on the last descriptor */
3892 desc->addr |= MACB_BIT(RX_WRAP);
3894 /* Reset buffer index */
3897 /* Program address of descriptor list in Rx Buffer Queue register */
3898 macb_writel(lp, RBQP, q->rx_ring_dma);
3900 /* Enable Receive and Transmit */
3901 ctl = macb_readl(lp, NCR);
3902 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3904 /* Enable MAC interrupts */
3905 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3907 MACB_BIT(ISR_TUND) |
3910 MACB_BIT(ISR_ROVR) |
3916 static void at91ether_stop(struct macb *lp)
3920 /* Disable MAC interrupts */
3921 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3923 MACB_BIT(ISR_TUND) |
3926 MACB_BIT(ISR_ROVR) |
3929 /* Disable Receiver and Transmitter */
3930 ctl = macb_readl(lp, NCR);
3931 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3933 /* Free resources. */
3934 at91ether_free_coherent(lp);
3937 /* Open the ethernet interface */
3938 static int at91ether_open(struct net_device *dev)
3940 struct macb *lp = netdev_priv(dev);
3944 ret = pm_runtime_get_sync(&lp->pdev->dev);
3946 pm_runtime_put_noidle(&lp->pdev->dev);
3950 /* Clear internal statistics */
3951 ctl = macb_readl(lp, NCR);
3952 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3954 macb_set_hwaddr(lp);
3956 ret = at91ether_start(lp);
3960 ret = macb_phylink_connect(lp);
3964 netif_start_queue(dev);
3971 pm_runtime_put_sync(&lp->pdev->dev);
3975 /* Close the interface */
3976 static int at91ether_close(struct net_device *dev)
3978 struct macb *lp = netdev_priv(dev);
3980 netif_stop_queue(dev);
3982 phylink_stop(lp->phylink);
3983 phylink_disconnect_phy(lp->phylink);
3987 return pm_runtime_put(&lp->pdev->dev);
3990 /* Transmit packet */
3991 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3992 struct net_device *dev)
3994 struct macb *lp = netdev_priv(dev);
3996 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3997 netif_stop_queue(dev);
3999 /* Store packet information (to free when Tx completed) */
4001 lp->skb_length = skb->len;
4002 lp->skb_physaddr = dma_map_single(&lp->pdev->dev, skb->data,
4003 skb->len, DMA_TO_DEVICE);
4004 if (dma_mapping_error(&lp->pdev->dev, lp->skb_physaddr)) {
4005 dev_kfree_skb_any(skb);
4006 dev->stats.tx_dropped++;
4007 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4008 return NETDEV_TX_OK;
4011 /* Set address of the data in the Transmit Address register */
4012 macb_writel(lp, TAR, lp->skb_physaddr);
4013 /* Set length of the packet in the Transmit Control register */
4014 macb_writel(lp, TCR, skb->len);
4017 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4018 return NETDEV_TX_BUSY;
4021 return NETDEV_TX_OK;
4024 /* Extract received frame from buffer descriptors and sent to upper layers.
4025 * (Called from interrupt context)
4027 static void at91ether_rx(struct net_device *dev)
4029 struct macb *lp = netdev_priv(dev);
4030 struct macb_queue *q = &lp->queues[0];
4031 struct macb_dma_desc *desc;
4032 unsigned char *p_recv;
4033 struct sk_buff *skb;
4034 unsigned int pktlen;
4036 desc = macb_rx_desc(q, q->rx_tail);
4037 while (desc->addr & MACB_BIT(RX_USED)) {
4038 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4039 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4040 skb = netdev_alloc_skb(dev, pktlen + 2);
4042 skb_reserve(skb, 2);
4043 skb_put_data(skb, p_recv, pktlen);
4045 skb->protocol = eth_type_trans(skb, dev);
4046 dev->stats.rx_packets++;
4047 dev->stats.rx_bytes += pktlen;
4050 dev->stats.rx_dropped++;
4053 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4054 dev->stats.multicast++;
4056 /* reset ownership bit */
4057 desc->addr &= ~MACB_BIT(RX_USED);
4059 /* wrap after last buffer */
4060 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4065 desc = macb_rx_desc(q, q->rx_tail);
4069 /* MAC interrupt handler */
4070 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4072 struct net_device *dev = dev_id;
4073 struct macb *lp = netdev_priv(dev);
4076 /* MAC Interrupt Status register indicates what interrupts are pending.
4077 * It is automatically cleared once read.
4079 intstatus = macb_readl(lp, ISR);
4081 /* Receive complete */
4082 if (intstatus & MACB_BIT(RCOMP))
4085 /* Transmit complete */
4086 if (intstatus & MACB_BIT(TCOMP)) {
4087 /* The TCOM bit is set even if the transmission failed */
4088 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4089 dev->stats.tx_errors++;
4092 dev_consume_skb_irq(lp->skb);
4094 dma_unmap_single(&lp->pdev->dev, lp->skb_physaddr,
4095 lp->skb_length, DMA_TO_DEVICE);
4096 dev->stats.tx_packets++;
4097 dev->stats.tx_bytes += lp->skb_length;
4099 netif_wake_queue(dev);
4102 /* Work-around for EMAC Errata section 41.3.1 */
4103 if (intstatus & MACB_BIT(RXUBR)) {
4104 ctl = macb_readl(lp, NCR);
4105 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4107 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4110 if (intstatus & MACB_BIT(ISR_ROVR))
4111 netdev_err(dev, "ROVR error\n");
4116 #ifdef CONFIG_NET_POLL_CONTROLLER
4117 static void at91ether_poll_controller(struct net_device *dev)
4119 unsigned long flags;
4121 local_irq_save(flags);
4122 at91ether_interrupt(dev->irq, dev);
4123 local_irq_restore(flags);
4127 static const struct net_device_ops at91ether_netdev_ops = {
4128 .ndo_open = at91ether_open,
4129 .ndo_stop = at91ether_close,
4130 .ndo_start_xmit = at91ether_start_xmit,
4131 .ndo_get_stats = macb_get_stats,
4132 .ndo_set_rx_mode = macb_set_rx_mode,
4133 .ndo_set_mac_address = eth_mac_addr,
4134 .ndo_do_ioctl = macb_ioctl,
4135 .ndo_validate_addr = eth_validate_addr,
4136 #ifdef CONFIG_NET_POLL_CONTROLLER
4137 .ndo_poll_controller = at91ether_poll_controller,
4141 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4142 struct clk **hclk, struct clk **tx_clk,
4143 struct clk **rx_clk, struct clk **tsu_clk)
4152 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4154 return PTR_ERR(*pclk);
4156 err = clk_prepare_enable(*pclk);
4158 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4165 static int at91ether_init(struct platform_device *pdev)
4167 struct net_device *dev = platform_get_drvdata(pdev);
4168 struct macb *bp = netdev_priv(dev);
4171 bp->queues[0].bp = bp;
4173 dev->netdev_ops = &at91ether_netdev_ops;
4174 dev->ethtool_ops = &macb_ethtool_ops;
4176 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4181 macb_writel(bp, NCR, 0);
4183 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4188 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4189 unsigned long parent_rate)
4194 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4195 unsigned long *parent_rate)
4197 if (WARN_ON(rate < 2500000))
4199 else if (rate == 2500000)
4201 else if (WARN_ON(rate < 13750000))
4203 else if (WARN_ON(rate < 25000000))
4205 else if (rate == 25000000)
4207 else if (WARN_ON(rate < 75000000))
4209 else if (WARN_ON(rate < 125000000))
4211 else if (rate == 125000000)
4214 WARN_ON(rate > 125000000);
4219 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4220 unsigned long parent_rate)
4222 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4223 if (rate != 125000000)
4224 iowrite32(1, mgmt->reg);
4226 iowrite32(0, mgmt->reg);
4232 static const struct clk_ops fu540_c000_ops = {
4233 .recalc_rate = fu540_macb_tx_recalc_rate,
4234 .round_rate = fu540_macb_tx_round_rate,
4235 .set_rate = fu540_macb_tx_set_rate,
4238 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4239 struct clk **hclk, struct clk **tx_clk,
4240 struct clk **rx_clk, struct clk **tsu_clk)
4242 struct clk_init_data init;
4245 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4249 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4253 init.name = "sifive-gemgxl-mgmt";
4254 init.ops = &fu540_c000_ops;
4256 init.num_parents = 0;
4259 mgmt->hw.init = &init;
4261 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4262 if (IS_ERR(*tx_clk))
4263 return PTR_ERR(*tx_clk);
4265 err = clk_prepare_enable(*tx_clk);
4267 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4269 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4274 static int fu540_c000_init(struct platform_device *pdev)
4276 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4277 if (IS_ERR(mgmt->reg))
4278 return PTR_ERR(mgmt->reg);
4280 return macb_init(pdev);
4283 static const struct macb_config fu540_c000_config = {
4284 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4285 MACB_CAPS_GEM_HAS_PTP,
4286 .dma_burst_length = 16,
4287 .clk_init = fu540_c000_clk_init,
4288 .init = fu540_c000_init,
4289 .jumbo_max_len = 10240,
4292 static const struct macb_config at91sam9260_config = {
4293 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4294 .clk_init = macb_clk_init,
4298 static const struct macb_config sama5d3macb_config = {
4299 .caps = MACB_CAPS_SG_DISABLED
4300 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4301 .clk_init = macb_clk_init,
4305 static const struct macb_config pc302gem_config = {
4306 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4307 .dma_burst_length = 16,
4308 .clk_init = macb_clk_init,
4312 static const struct macb_config sama5d2_config = {
4313 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4314 .dma_burst_length = 16,
4315 .clk_init = macb_clk_init,
4319 static const struct macb_config sama5d3_config = {
4320 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4321 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4322 .dma_burst_length = 16,
4323 .clk_init = macb_clk_init,
4325 .jumbo_max_len = 10240,
4328 static const struct macb_config sama5d4_config = {
4329 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4330 .dma_burst_length = 4,
4331 .clk_init = macb_clk_init,
4335 static const struct macb_config emac_config = {
4336 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4337 .clk_init = at91ether_clk_init,
4338 .init = at91ether_init,
4341 static const struct macb_config np4_config = {
4342 .caps = MACB_CAPS_USRIO_DISABLED,
4343 .clk_init = macb_clk_init,
4347 static const struct macb_config zynqmp_config = {
4348 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4350 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4351 .dma_burst_length = 16,
4352 .clk_init = macb_clk_init,
4354 .jumbo_max_len = 10240,
4357 static const struct macb_config zynq_config = {
4358 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4359 MACB_CAPS_NEEDS_RSTONUBR,
4360 .dma_burst_length = 16,
4361 .clk_init = macb_clk_init,
4365 static const struct of_device_id macb_dt_ids[] = {
4366 { .compatible = "cdns,at32ap7000-macb" },
4367 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4368 { .compatible = "cdns,macb" },
4369 { .compatible = "cdns,np4-macb", .data = &np4_config },
4370 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4371 { .compatible = "cdns,gem", .data = &pc302gem_config },
4372 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4373 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4374 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4375 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4376 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4377 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4378 { .compatible = "cdns,emac", .data = &emac_config },
4379 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4380 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4381 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4384 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4385 #endif /* CONFIG_OF */
4387 static const struct macb_config default_gem_config = {
4388 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4390 MACB_CAPS_GEM_HAS_PTP,
4391 .dma_burst_length = 16,
4392 .clk_init = macb_clk_init,
4394 .jumbo_max_len = 10240,
4397 static int macb_probe(struct platform_device *pdev)
4399 const struct macb_config *macb_config = &default_gem_config;
4400 int (*clk_init)(struct platform_device *, struct clk **,
4401 struct clk **, struct clk **, struct clk **,
4402 struct clk **) = macb_config->clk_init;
4403 int (*init)(struct platform_device *) = macb_config->init;
4404 struct device_node *np = pdev->dev.of_node;
4405 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4406 struct clk *tsu_clk = NULL;
4407 unsigned int queue_mask, num_queues;
4409 phy_interface_t interface;
4410 struct net_device *dev;
4411 struct resource *regs;
4417 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4418 mem = devm_ioremap_resource(&pdev->dev, regs);
4420 return PTR_ERR(mem);
4423 const struct of_device_id *match;
4425 match = of_match_node(macb_dt_ids, np);
4426 if (match && match->data) {
4427 macb_config = match->data;
4428 clk_init = macb_config->clk_init;
4429 init = macb_config->init;
4433 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4437 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4438 pm_runtime_use_autosuspend(&pdev->dev);
4439 pm_runtime_get_noresume(&pdev->dev);
4440 pm_runtime_set_active(&pdev->dev);
4441 pm_runtime_enable(&pdev->dev);
4442 native_io = hw_is_native_io(mem);
4444 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4445 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4448 goto err_disable_clocks;
4451 dev->base_addr = regs->start;
4453 SET_NETDEV_DEV(dev, &pdev->dev);
4455 bp = netdev_priv(dev);
4459 bp->native_io = native_io;
4461 bp->macb_reg_readl = hw_readl_native;
4462 bp->macb_reg_writel = hw_writel_native;
4464 bp->macb_reg_readl = hw_readl;
4465 bp->macb_reg_writel = hw_writel;
4467 bp->num_queues = num_queues;
4468 bp->queue_mask = queue_mask;
4470 bp->dma_burst_length = macb_config->dma_burst_length;
4473 bp->tx_clk = tx_clk;
4474 bp->rx_clk = rx_clk;
4475 bp->tsu_clk = tsu_clk;
4477 bp->jumbo_max_len = macb_config->jumbo_max_len;
4480 if (of_get_property(np, "magic-packet", NULL))
4481 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4482 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4484 spin_lock_init(&bp->lock);
4486 /* setup capabilities */
4487 macb_configure_caps(bp, macb_config);
4489 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4490 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4491 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4492 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4495 platform_set_drvdata(pdev, dev);
4497 dev->irq = platform_get_irq(pdev, 0);
4500 goto err_out_free_netdev;
4503 /* MTU range: 68 - 1500 or 10240 */
4504 dev->min_mtu = GEM_MTU_MIN_SIZE;
4505 if (bp->caps & MACB_CAPS_JUMBO)
4506 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4508 dev->max_mtu = ETH_DATA_LEN;
4510 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4511 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4513 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4514 macb_dma_desc_get_size(bp);
4516 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4518 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4519 macb_dma_desc_get_size(bp);
4522 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4523 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4524 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4526 mac = of_get_mac_address(np);
4527 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4528 err = -EPROBE_DEFER;
4529 goto err_out_free_netdev;
4530 } else if (!IS_ERR_OR_NULL(mac)) {
4531 ether_addr_copy(bp->dev->dev_addr, mac);
4533 macb_get_hwaddr(bp);
4536 err = of_get_phy_mode(np, &interface);
4538 /* not found in DT, MII by default */
4539 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4541 bp->phy_interface = interface;
4543 /* IP specific init */
4546 goto err_out_free_netdev;
4548 err = macb_mii_init(bp);
4550 goto err_out_free_netdev;
4552 netif_carrier_off(dev);
4554 err = register_netdev(dev);
4556 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4557 goto err_out_unregister_mdio;
4560 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4563 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4564 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4565 dev->base_addr, dev->irq, dev->dev_addr);
4567 pm_runtime_mark_last_busy(&bp->pdev->dev);
4568 pm_runtime_put_autosuspend(&bp->pdev->dev);
4572 err_out_unregister_mdio:
4573 mdiobus_unregister(bp->mii_bus);
4574 mdiobus_free(bp->mii_bus);
4576 err_out_free_netdev:
4580 clk_disable_unprepare(tx_clk);
4581 clk_disable_unprepare(hclk);
4582 clk_disable_unprepare(pclk);
4583 clk_disable_unprepare(rx_clk);
4584 clk_disable_unprepare(tsu_clk);
4585 pm_runtime_disable(&pdev->dev);
4586 pm_runtime_set_suspended(&pdev->dev);
4587 pm_runtime_dont_use_autosuspend(&pdev->dev);
4592 static int macb_remove(struct platform_device *pdev)
4594 struct net_device *dev;
4597 dev = platform_get_drvdata(pdev);
4600 bp = netdev_priv(dev);
4601 mdiobus_unregister(bp->mii_bus);
4602 mdiobus_free(bp->mii_bus);
4604 unregister_netdev(dev);
4605 tasklet_kill(&bp->hresp_err_tasklet);
4606 pm_runtime_disable(&pdev->dev);
4607 pm_runtime_dont_use_autosuspend(&pdev->dev);
4608 if (!pm_runtime_suspended(&pdev->dev)) {
4609 clk_disable_unprepare(bp->tx_clk);
4610 clk_disable_unprepare(bp->hclk);
4611 clk_disable_unprepare(bp->pclk);
4612 clk_disable_unprepare(bp->rx_clk);
4613 clk_disable_unprepare(bp->tsu_clk);
4614 pm_runtime_set_suspended(&pdev->dev);
4616 phylink_destroy(bp->phylink);
4623 static int __maybe_unused macb_suspend(struct device *dev)
4625 struct net_device *netdev = dev_get_drvdata(dev);
4626 struct macb *bp = netdev_priv(netdev);
4627 struct macb_queue *queue = bp->queues;
4628 unsigned long flags;
4632 if (!netif_running(netdev))
4635 if (bp->wol & MACB_WOL_ENABLED) {
4636 spin_lock_irqsave(&bp->lock, flags);
4637 /* Flush all status bits */
4638 macb_writel(bp, TSR, -1);
4639 macb_writel(bp, RSR, -1);
4640 for (q = 0, queue = bp->queues; q < bp->num_queues;
4642 /* Disable all interrupts */
4643 queue_writel(queue, IDR, -1);
4644 queue_readl(queue, ISR);
4645 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4646 queue_writel(queue, ISR, -1);
4648 /* Change interrupt handler and
4649 * Enable WoL IRQ on queue 0
4651 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4652 if (macb_is_gem(bp)) {
4653 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
4654 IRQF_SHARED, netdev->name, bp->queues);
4657 "Unable to request IRQ %d (error %d)\n",
4658 bp->queues[0].irq, err);
4659 spin_unlock_irqrestore(&bp->lock, flags);
4662 queue_writel(bp->queues, IER, GEM_BIT(WOL));
4663 gem_writel(bp, WOL, MACB_BIT(MAG));
4665 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
4666 IRQF_SHARED, netdev->name, bp->queues);
4669 "Unable to request IRQ %d (error %d)\n",
4670 bp->queues[0].irq, err);
4671 spin_unlock_irqrestore(&bp->lock, flags);
4674 queue_writel(bp->queues, IER, MACB_BIT(WOL));
4675 macb_writel(bp, WOL, MACB_BIT(MAG));
4677 spin_unlock_irqrestore(&bp->lock, flags);
4679 enable_irq_wake(bp->queues[0].irq);
4682 netif_device_detach(netdev);
4683 for (q = 0, queue = bp->queues; q < bp->num_queues;
4685 napi_disable(&queue->napi);
4687 if (!(bp->wol & MACB_WOL_ENABLED)) {
4689 phylink_stop(bp->phylink);
4691 spin_lock_irqsave(&bp->lock, flags);
4693 spin_unlock_irqrestore(&bp->lock, flags);
4696 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4697 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4699 if (netdev->hw_features & NETIF_F_NTUPLE)
4700 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4703 bp->ptp_info->ptp_remove(netdev);
4704 if (!device_may_wakeup(dev))
4705 pm_runtime_force_suspend(dev);
4710 static int __maybe_unused macb_resume(struct device *dev)
4712 struct net_device *netdev = dev_get_drvdata(dev);
4713 struct macb *bp = netdev_priv(netdev);
4714 struct macb_queue *queue = bp->queues;
4715 unsigned long flags;
4719 if (!netif_running(netdev))
4722 if (!device_may_wakeup(dev))
4723 pm_runtime_force_resume(dev);
4725 if (bp->wol & MACB_WOL_ENABLED) {
4726 spin_lock_irqsave(&bp->lock, flags);
4728 if (macb_is_gem(bp)) {
4729 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
4730 gem_writel(bp, WOL, 0);
4732 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
4733 macb_writel(bp, WOL, 0);
4735 /* Clear ISR on queue 0 */
4736 queue_readl(bp->queues, ISR);
4737 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4738 queue_writel(bp->queues, ISR, -1);
4739 /* Replace interrupt handler on queue 0 */
4740 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4741 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
4742 IRQF_SHARED, netdev->name, bp->queues);
4745 "Unable to request IRQ %d (error %d)\n",
4746 bp->queues[0].irq, err);
4747 spin_unlock_irqrestore(&bp->lock, flags);
4750 spin_unlock_irqrestore(&bp->lock, flags);
4752 disable_irq_wake(bp->queues[0].irq);
4754 /* Now make sure we disable phy before moving
4755 * to common restore path
4758 phylink_stop(bp->phylink);
4762 for (q = 0, queue = bp->queues; q < bp->num_queues;
4764 napi_enable(&queue->napi);
4766 if (netdev->hw_features & NETIF_F_NTUPLE)
4767 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4769 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4770 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4772 macb_writel(bp, NCR, MACB_BIT(MPE));
4774 macb_set_rx_mode(netdev);
4775 macb_restore_features(bp);
4777 phylink_start(bp->phylink);
4780 netif_device_attach(netdev);
4782 bp->ptp_info->ptp_init(netdev);
4787 static int __maybe_unused macb_runtime_suspend(struct device *dev)
4789 struct net_device *netdev = dev_get_drvdata(dev);
4790 struct macb *bp = netdev_priv(netdev);
4792 if (!(device_may_wakeup(dev))) {
4793 clk_disable_unprepare(bp->tx_clk);
4794 clk_disable_unprepare(bp->hclk);
4795 clk_disable_unprepare(bp->pclk);
4796 clk_disable_unprepare(bp->rx_clk);
4798 clk_disable_unprepare(bp->tsu_clk);
4803 static int __maybe_unused macb_runtime_resume(struct device *dev)
4805 struct net_device *netdev = dev_get_drvdata(dev);
4806 struct macb *bp = netdev_priv(netdev);
4808 if (!(device_may_wakeup(dev))) {
4809 clk_prepare_enable(bp->pclk);
4810 clk_prepare_enable(bp->hclk);
4811 clk_prepare_enable(bp->tx_clk);
4812 clk_prepare_enable(bp->rx_clk);
4814 clk_prepare_enable(bp->tsu_clk);
4819 static const struct dev_pm_ops macb_pm_ops = {
4820 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
4821 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
4824 static struct platform_driver macb_driver = {
4825 .probe = macb_probe,
4826 .remove = macb_remove,
4829 .of_match_table = of_match_ptr(macb_dt_ids),
4834 module_platform_driver(macb_driver);
4836 MODULE_LICENSE("GPL");
4837 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4838 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4839 MODULE_ALIAS("platform:macb");