1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
29 #include <linux/of_device.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
34 #include <linux/udp.h>
35 #include <linux/tcp.h>
36 #include <linux/iopoll.h>
37 #include <linux/phy/phy.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/ptp_classify.h>
40 #include <linux/reset.h>
41 #include <linux/firmware/xlnx-zynqmp.h>
44 /* This structure is only used for MACB on SiFive FU540 devices */
45 struct sifive_fu540_macb_mgmt {
51 #define MACB_RX_BUFFER_SIZE 128
52 #define RX_BUFFER_MULTIPLE 64 /* bytes */
54 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
55 #define MIN_RX_RING_SIZE 64
56 #define MAX_RX_RING_SIZE 8192
57 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
60 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
61 #define MIN_TX_RING_SIZE 64
62 #define MAX_TX_RING_SIZE 4096
63 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
66 /* level of occupied TX descriptors under which we wake up TX process */
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
69 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
70 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
73 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
76 /* Max length of transmit frame must be a multiple of 8 bytes */
77 #define MACB_TX_LEN_ALIGN 8
78 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
79 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
80 * false amba_error in TX path from the DMA assuming there is not enough
81 * space in the SRAM (16KB) even when there is.
83 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
85 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
86 #define MACB_NETIF_LSO NETIF_F_TSO
88 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
89 #define MACB_WOL_ENABLED (0x1 << 1)
91 #define HS_SPEED_10000M 4
92 #define MACB_SERDES_RATE_10G 1
94 /* Graceful stop timeouts in us. We should allow up to
95 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
97 #define MACB_HALT_TIMEOUT 1230
99 #define MACB_PM_TIMEOUT 100 /* ms */
101 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
103 /* DMA buffer descriptor might be different size
104 * depends on hardware configuration:
106 * 1. dma address width 32 bits:
107 * word 1: 32 bit address of Data Buffer
110 * 2. dma address width 64 bits:
111 * word 1: 32 bit address of Data Buffer
113 * word 3: upper 32 bit address of Data Buffer
116 * 3. dma address width 32 bits with hardware timestamping:
117 * word 1: 32 bit address of Data Buffer
119 * word 3: timestamp word 1
120 * word 4: timestamp word 2
122 * 4. dma address width 64 bits with hardware timestamping:
123 * word 1: 32 bit address of Data Buffer
125 * word 3: upper 32 bit address of Data Buffer
127 * word 5: timestamp word 1
128 * word 6: timestamp word 2
130 static unsigned int macb_dma_desc_get_size(struct macb *bp)
133 unsigned int desc_size;
135 switch (bp->hw_dma_cap) {
137 desc_size = sizeof(struct macb_dma_desc)
138 + sizeof(struct macb_dma_desc_64);
141 desc_size = sizeof(struct macb_dma_desc)
142 + sizeof(struct macb_dma_desc_ptp);
144 case HW_DMA_CAP_64B_PTP:
145 desc_size = sizeof(struct macb_dma_desc)
146 + sizeof(struct macb_dma_desc_64)
147 + sizeof(struct macb_dma_desc_ptp);
150 desc_size = sizeof(struct macb_dma_desc);
154 return sizeof(struct macb_dma_desc);
157 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
160 switch (bp->hw_dma_cap) {
165 case HW_DMA_CAP_64B_PTP:
175 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
176 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
178 return (struct macb_dma_desc_64 *)((void *)desc
179 + sizeof(struct macb_dma_desc));
183 /* Ring buffer accessors */
184 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
186 return index & (bp->tx_ring_size - 1);
189 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
192 index = macb_tx_ring_wrap(queue->bp, index);
193 index = macb_adj_dma_desc_idx(queue->bp, index);
194 return &queue->tx_ring[index];
197 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
200 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
203 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
207 offset = macb_tx_ring_wrap(queue->bp, index) *
208 macb_dma_desc_get_size(queue->bp);
210 return queue->tx_ring_dma + offset;
213 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
215 return index & (bp->rx_ring_size - 1);
218 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
220 index = macb_rx_ring_wrap(queue->bp, index);
221 index = macb_adj_dma_desc_idx(queue->bp, index);
222 return &queue->rx_ring[index];
225 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
227 return queue->rx_buffers + queue->bp->rx_buffer_size *
228 macb_rx_ring_wrap(queue->bp, index);
232 static u32 hw_readl_native(struct macb *bp, int offset)
234 return __raw_readl(bp->regs + offset);
237 static void hw_writel_native(struct macb *bp, int offset, u32 value)
239 __raw_writel(value, bp->regs + offset);
242 static u32 hw_readl(struct macb *bp, int offset)
244 return readl_relaxed(bp->regs + offset);
247 static void hw_writel(struct macb *bp, int offset, u32 value)
249 writel_relaxed(value, bp->regs + offset);
252 /* Find the CPU endianness by using the loopback bit of NCR register. When the
253 * CPU is in big endian we need to program swapped mode for management
256 static bool hw_is_native_io(void __iomem *addr)
258 u32 value = MACB_BIT(LLB);
260 __raw_writel(value, addr + MACB_NCR);
261 value = __raw_readl(addr + MACB_NCR);
263 /* Write 0 back to disable everything */
264 __raw_writel(0, addr + MACB_NCR);
266 return value == MACB_BIT(LLB);
269 static bool hw_is_gem(void __iomem *addr, bool native_io)
274 id = __raw_readl(addr + MACB_MID);
276 id = readl_relaxed(addr + MACB_MID);
278 return MACB_BFEXT(IDNUM, id) >= 0x2;
281 static void macb_set_hwaddr(struct macb *bp)
286 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
287 macb_or_gem_writel(bp, SA1B, bottom);
288 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
289 macb_or_gem_writel(bp, SA1T, top);
291 /* Clear unused address register sets */
292 macb_or_gem_writel(bp, SA2B, 0);
293 macb_or_gem_writel(bp, SA2T, 0);
294 macb_or_gem_writel(bp, SA3B, 0);
295 macb_or_gem_writel(bp, SA3T, 0);
296 macb_or_gem_writel(bp, SA4B, 0);
297 macb_or_gem_writel(bp, SA4T, 0);
300 static void macb_get_hwaddr(struct macb *bp)
307 /* Check all 4 address register for valid address */
308 for (i = 0; i < 4; i++) {
309 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
310 top = macb_or_gem_readl(bp, SA1T + i * 8);
312 addr[0] = bottom & 0xff;
313 addr[1] = (bottom >> 8) & 0xff;
314 addr[2] = (bottom >> 16) & 0xff;
315 addr[3] = (bottom >> 24) & 0xff;
316 addr[4] = top & 0xff;
317 addr[5] = (top >> 8) & 0xff;
319 if (is_valid_ether_addr(addr)) {
320 eth_hw_addr_set(bp->dev, addr);
325 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
326 eth_hw_addr_random(bp->dev);
329 static int macb_mdio_wait_for_idle(struct macb *bp)
333 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
334 1, MACB_MDIO_TIMEOUT);
337 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
339 struct macb *bp = bus->priv;
342 status = pm_runtime_resume_and_get(&bp->pdev->dev);
346 status = macb_mdio_wait_for_idle(bp);
350 if (regnum & MII_ADDR_C45) {
351 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
352 | MACB_BF(RW, MACB_MAN_C45_ADDR)
353 | MACB_BF(PHYA, mii_id)
354 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
355 | MACB_BF(DATA, regnum & 0xFFFF)
356 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
358 status = macb_mdio_wait_for_idle(bp);
362 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
363 | MACB_BF(RW, MACB_MAN_C45_READ)
364 | MACB_BF(PHYA, mii_id)
365 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
366 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
368 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
369 | MACB_BF(RW, MACB_MAN_C22_READ)
370 | MACB_BF(PHYA, mii_id)
371 | MACB_BF(REGA, regnum)
372 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
375 status = macb_mdio_wait_for_idle(bp);
379 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
382 pm_runtime_mark_last_busy(&bp->pdev->dev);
383 pm_runtime_put_autosuspend(&bp->pdev->dev);
388 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
391 struct macb *bp = bus->priv;
394 status = pm_runtime_resume_and_get(&bp->pdev->dev);
398 status = macb_mdio_wait_for_idle(bp);
400 goto mdio_write_exit;
402 if (regnum & MII_ADDR_C45) {
403 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
404 | MACB_BF(RW, MACB_MAN_C45_ADDR)
405 | MACB_BF(PHYA, mii_id)
406 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
407 | MACB_BF(DATA, regnum & 0xFFFF)
408 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
410 status = macb_mdio_wait_for_idle(bp);
412 goto mdio_write_exit;
414 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
415 | MACB_BF(RW, MACB_MAN_C45_WRITE)
416 | MACB_BF(PHYA, mii_id)
417 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
418 | MACB_BF(CODE, MACB_MAN_C45_CODE)
419 | MACB_BF(DATA, value)));
421 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
422 | MACB_BF(RW, MACB_MAN_C22_WRITE)
423 | MACB_BF(PHYA, mii_id)
424 | MACB_BF(REGA, regnum)
425 | MACB_BF(CODE, MACB_MAN_C22_CODE)
426 | MACB_BF(DATA, value)));
429 status = macb_mdio_wait_for_idle(bp);
431 goto mdio_write_exit;
434 pm_runtime_mark_last_busy(&bp->pdev->dev);
435 pm_runtime_put_autosuspend(&bp->pdev->dev);
440 static void macb_init_buffers(struct macb *bp)
442 struct macb_queue *queue;
445 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
446 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
447 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
448 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
449 queue_writel(queue, RBQPH,
450 upper_32_bits(queue->rx_ring_dma));
452 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
453 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
454 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
455 queue_writel(queue, TBQPH,
456 upper_32_bits(queue->tx_ring_dma));
462 * macb_set_tx_clk() - Set a clock to a new frequency
463 * @bp: pointer to struct macb
464 * @speed: New frequency in Hz
466 static void macb_set_tx_clk(struct macb *bp, int speed)
468 long ferr, rate, rate_rounded;
470 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
473 /* In case of MII the PHY is the clock master */
474 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
491 rate_rounded = clk_round_rate(bp->tx_clk, rate);
492 if (rate_rounded < 0)
495 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
498 ferr = abs(rate_rounded - rate);
499 ferr = DIV_ROUND_UP(ferr, rate / 100000);
502 "unable to generate target frequency: %ld Hz\n",
505 if (clk_set_rate(bp->tx_clk, rate_rounded))
506 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
509 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
510 phy_interface_t interface, int speed,
513 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
516 config = gem_readl(bp, USX_CONTROL);
517 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
518 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
519 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
520 config |= GEM_BIT(TX_EN);
521 gem_writel(bp, USX_CONTROL, config);
524 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
525 struct phylink_link_state *state)
527 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
530 state->speed = SPEED_10000;
532 state->an_complete = 1;
534 val = gem_readl(bp, USX_STATUS);
535 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
536 val = gem_readl(bp, NCFGR);
537 if (val & GEM_BIT(PAE))
538 state->pause = MLO_PAUSE_RX;
541 static int macb_usx_pcs_config(struct phylink_pcs *pcs,
543 phy_interface_t interface,
544 const unsigned long *advertising,
545 bool permit_pause_to_mac)
547 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
549 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
555 static void macb_pcs_get_state(struct phylink_pcs *pcs,
556 struct phylink_link_state *state)
561 static void macb_pcs_an_restart(struct phylink_pcs *pcs)
566 static int macb_pcs_config(struct phylink_pcs *pcs,
568 phy_interface_t interface,
569 const unsigned long *advertising,
570 bool permit_pause_to_mac)
575 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
576 .pcs_get_state = macb_usx_pcs_get_state,
577 .pcs_config = macb_usx_pcs_config,
578 .pcs_link_up = macb_usx_pcs_link_up,
581 static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
582 .pcs_get_state = macb_pcs_get_state,
583 .pcs_an_restart = macb_pcs_an_restart,
584 .pcs_config = macb_pcs_config,
587 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
588 const struct phylink_link_state *state)
590 struct net_device *ndev = to_net_dev(config->dev);
591 struct macb *bp = netdev_priv(ndev);
596 spin_lock_irqsave(&bp->lock, flags);
598 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
599 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
601 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
602 if (state->interface == PHY_INTERFACE_MODE_RMII)
603 ctrl |= MACB_BIT(RM9200_RMII);
604 } else if (macb_is_gem(bp)) {
605 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
606 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
608 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
609 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
610 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
611 ctrl |= GEM_BIT(PCSSEL);
612 ncr |= GEM_BIT(ENABLE_HS_MAC);
613 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
614 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
615 ncr |= MACB_BIT(MIIONRGMII);
619 /* Apply the new configuration, if any */
621 macb_or_gem_writel(bp, NCFGR, ctrl);
624 macb_or_gem_writel(bp, NCR, ncr);
626 /* Disable AN for SGMII fixed link configuration, enable otherwise.
627 * Must be written after PCSSEL is set in NCFGR,
628 * otherwise writes will not take effect.
630 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
631 u32 pcsctrl, old_pcsctrl;
633 old_pcsctrl = gem_readl(bp, PCSCNTRL);
634 if (mode == MLO_AN_FIXED)
635 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
637 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
638 if (old_pcsctrl != pcsctrl)
639 gem_writel(bp, PCSCNTRL, pcsctrl);
642 spin_unlock_irqrestore(&bp->lock, flags);
645 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
646 phy_interface_t interface)
648 struct net_device *ndev = to_net_dev(config->dev);
649 struct macb *bp = netdev_priv(ndev);
650 struct macb_queue *queue;
654 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
655 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
656 queue_writel(queue, IDR,
657 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
659 /* Disable Rx and Tx */
660 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
661 macb_writel(bp, NCR, ctrl);
663 netif_tx_stop_all_queues(ndev);
666 static void macb_mac_link_up(struct phylink_config *config,
667 struct phy_device *phy,
668 unsigned int mode, phy_interface_t interface,
669 int speed, int duplex,
670 bool tx_pause, bool rx_pause)
672 struct net_device *ndev = to_net_dev(config->dev);
673 struct macb *bp = netdev_priv(ndev);
674 struct macb_queue *queue;
679 spin_lock_irqsave(&bp->lock, flags);
681 ctrl = macb_or_gem_readl(bp, NCFGR);
683 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
685 if (speed == SPEED_100)
686 ctrl |= MACB_BIT(SPD);
689 ctrl |= MACB_BIT(FD);
691 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
692 ctrl &= ~MACB_BIT(PAE);
693 if (macb_is_gem(bp)) {
694 ctrl &= ~GEM_BIT(GBE);
696 if (speed == SPEED_1000)
697 ctrl |= GEM_BIT(GBE);
701 ctrl |= MACB_BIT(PAE);
703 macb_set_tx_clk(bp, speed);
705 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
706 * cleared the pipeline and control registers.
708 bp->macbgem_ops.mog_init_rings(bp);
709 macb_init_buffers(bp);
711 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
712 queue_writel(queue, IER,
713 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
716 macb_or_gem_writel(bp, NCFGR, ctrl);
718 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
719 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
720 gem_readl(bp, HS_MAC_CONFIG)));
722 spin_unlock_irqrestore(&bp->lock, flags);
724 /* Enable Rx and Tx */
725 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
727 netif_tx_wake_all_queues(ndev);
730 static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
731 phy_interface_t interface)
733 struct net_device *ndev = to_net_dev(config->dev);
734 struct macb *bp = netdev_priv(ndev);
736 if (interface == PHY_INTERFACE_MODE_10GBASER)
737 return &bp->phylink_usx_pcs;
738 else if (interface == PHY_INTERFACE_MODE_SGMII)
739 return &bp->phylink_sgmii_pcs;
744 static const struct phylink_mac_ops macb_phylink_ops = {
745 .mac_select_pcs = macb_mac_select_pcs,
746 .mac_config = macb_mac_config,
747 .mac_link_down = macb_mac_link_down,
748 .mac_link_up = macb_mac_link_up,
751 static bool macb_phy_handle_exists(struct device_node *dn)
753 dn = of_parse_phandle(dn, "phy-handle", 0);
758 static int macb_phylink_connect(struct macb *bp)
760 struct device_node *dn = bp->pdev->dev.of_node;
761 struct net_device *dev = bp->dev;
762 struct phy_device *phydev;
766 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
768 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
769 phydev = phy_find_first(bp->mii_bus);
771 netdev_err(dev, "no PHY found\n");
775 /* attach the mac to the phy */
776 ret = phylink_connect_phy(bp->phylink, phydev);
780 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
784 phylink_start(bp->phylink);
789 static void macb_get_pcs_fixed_state(struct phylink_config *config,
790 struct phylink_link_state *state)
792 struct net_device *ndev = to_net_dev(config->dev);
793 struct macb *bp = netdev_priv(ndev);
795 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
798 /* based on au1000_eth. c*/
799 static int macb_mii_probe(struct net_device *dev)
801 struct macb *bp = netdev_priv(dev);
803 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
804 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
806 bp->phylink_config.dev = &dev->dev;
807 bp->phylink_config.type = PHYLINK_NETDEV;
808 bp->phylink_config.mac_managed_pm = true;
810 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
811 bp->phylink_config.poll_fixed_state = true;
812 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
815 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
818 __set_bit(PHY_INTERFACE_MODE_MII,
819 bp->phylink_config.supported_interfaces);
820 __set_bit(PHY_INTERFACE_MODE_RMII,
821 bp->phylink_config.supported_interfaces);
823 /* Determine what modes are supported */
824 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
825 bp->phylink_config.mac_capabilities |= MAC_1000FD;
826 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
827 bp->phylink_config.mac_capabilities |= MAC_1000HD;
829 __set_bit(PHY_INTERFACE_MODE_GMII,
830 bp->phylink_config.supported_interfaces);
831 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
833 if (bp->caps & MACB_CAPS_PCS)
834 __set_bit(PHY_INTERFACE_MODE_SGMII,
835 bp->phylink_config.supported_interfaces);
837 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
838 __set_bit(PHY_INTERFACE_MODE_10GBASER,
839 bp->phylink_config.supported_interfaces);
840 bp->phylink_config.mac_capabilities |= MAC_10000FD;
844 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
845 bp->phy_interface, &macb_phylink_ops);
846 if (IS_ERR(bp->phylink)) {
847 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
848 PTR_ERR(bp->phylink));
849 return PTR_ERR(bp->phylink);
855 static int macb_mdiobus_register(struct macb *bp)
857 struct device_node *child, *np = bp->pdev->dev.of_node;
859 /* If we have a child named mdio, probe it instead of looking for PHYs
860 * directly under the MAC node
862 child = of_get_child_by_name(np, "mdio");
864 int ret = of_mdiobus_register(bp->mii_bus, child);
870 if (of_phy_is_fixed_link(np))
871 return mdiobus_register(bp->mii_bus);
873 /* Only create the PHY from the device tree if at least one PHY is
874 * described. Otherwise scan the entire MDIO bus. We do this to support
875 * old device tree that did not follow the best practices and did not
876 * describe their network PHYs.
878 for_each_available_child_of_node(np, child)
879 if (of_mdiobus_child_is_phy(child)) {
880 /* The loop increments the child refcount,
881 * decrement it before returning.
885 return of_mdiobus_register(bp->mii_bus, np);
888 return mdiobus_register(bp->mii_bus);
891 static int macb_mii_init(struct macb *bp)
895 /* Enable management port */
896 macb_writel(bp, NCR, MACB_BIT(MPE));
898 bp->mii_bus = mdiobus_alloc();
904 bp->mii_bus->name = "MACB_mii_bus";
905 bp->mii_bus->read = &macb_mdio_read;
906 bp->mii_bus->write = &macb_mdio_write;
907 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
908 bp->pdev->name, bp->pdev->id);
909 bp->mii_bus->priv = bp;
910 bp->mii_bus->parent = &bp->pdev->dev;
912 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
914 err = macb_mdiobus_register(bp);
916 goto err_out_free_mdiobus;
918 err = macb_mii_probe(bp->dev);
920 goto err_out_unregister_bus;
924 err_out_unregister_bus:
925 mdiobus_unregister(bp->mii_bus);
926 err_out_free_mdiobus:
927 mdiobus_free(bp->mii_bus);
932 static void macb_update_stats(struct macb *bp)
934 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
935 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
936 int offset = MACB_PFR;
938 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
940 for (; p < end; p++, offset += 4)
941 *p += bp->macb_reg_readl(bp, offset);
944 static int macb_halt_tx(struct macb *bp)
946 unsigned long halt_time, timeout;
949 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
951 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
954 status = macb_readl(bp, TSR);
955 if (!(status & MACB_BIT(TGO)))
959 } while (time_before(halt_time, timeout));
964 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget)
966 if (tx_skb->mapping) {
967 if (tx_skb->mapped_as_page)
968 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
969 tx_skb->size, DMA_TO_DEVICE);
971 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
972 tx_skb->size, DMA_TO_DEVICE);
977 napi_consume_skb(tx_skb->skb, budget);
982 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
984 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
985 struct macb_dma_desc_64 *desc_64;
987 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
988 desc_64 = macb_64b_desc(bp, desc);
989 desc_64->addrh = upper_32_bits(addr);
990 /* The low bits of RX address contain the RX_USED bit, clearing
991 * of which allows packet RX. Make sure the high bits are also
992 * visible to HW at that point.
997 desc->addr = lower_32_bits(addr);
1000 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1002 dma_addr_t addr = 0;
1003 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1004 struct macb_dma_desc_64 *desc_64;
1006 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1007 desc_64 = macb_64b_desc(bp, desc);
1008 addr = ((u64)(desc_64->addrh) << 32);
1011 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1015 static void macb_tx_error_task(struct work_struct *work)
1017 struct macb_queue *queue = container_of(work, struct macb_queue,
1019 struct macb *bp = queue->bp;
1020 struct macb_tx_skb *tx_skb;
1021 struct macb_dma_desc *desc;
1022 struct sk_buff *skb;
1024 unsigned long flags;
1026 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1027 (unsigned int)(queue - bp->queues),
1028 queue->tx_tail, queue->tx_head);
1030 /* Prevent the queue NAPI TX poll from running, as it calls
1031 * macb_tx_complete(), which in turn may call netif_wake_subqueue().
1032 * As explained below, we have to halt the transmission before updating
1033 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1034 * network engine about the macb/gem being halted.
1036 napi_disable(&queue->napi_tx);
1037 spin_lock_irqsave(&bp->lock, flags);
1039 /* Make sure nobody is trying to queue up new packets */
1040 netif_tx_stop_all_queues(bp->dev);
1042 /* Stop transmission now
1043 * (in case we have just queued new packets)
1044 * macb/gem must be halted to write TBQP register
1046 if (macb_halt_tx(bp))
1047 /* Just complain for now, reinitializing TX path can be good */
1048 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1050 /* Treat frames in TX queue including the ones that caused the error.
1051 * Free transmit buffers in upper layer.
1053 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1056 desc = macb_tx_desc(queue, tail);
1058 tx_skb = macb_tx_skb(queue, tail);
1061 if (ctrl & MACB_BIT(TX_USED)) {
1062 /* skb is set for the last buffer of the frame */
1064 macb_tx_unmap(bp, tx_skb, 0);
1066 tx_skb = macb_tx_skb(queue, tail);
1070 /* ctrl still refers to the first buffer descriptor
1071 * since it's the only one written back by the hardware
1073 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1074 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1075 macb_tx_ring_wrap(bp, tail),
1077 bp->dev->stats.tx_packets++;
1078 queue->stats.tx_packets++;
1079 bp->dev->stats.tx_bytes += skb->len;
1080 queue->stats.tx_bytes += skb->len;
1083 /* "Buffers exhausted mid-frame" errors may only happen
1084 * if the driver is buggy, so complain loudly about
1085 * those. Statistics are updated by hardware.
1087 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1089 "BUG: TX buffers exhausted mid-frame\n");
1091 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1094 macb_tx_unmap(bp, tx_skb, 0);
1097 /* Set end of TX queue */
1098 desc = macb_tx_desc(queue, 0);
1099 macb_set_addr(bp, desc, 0);
1100 desc->ctrl = MACB_BIT(TX_USED);
1102 /* Make descriptor updates visible to hardware */
1105 /* Reinitialize the TX desc queue */
1106 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1107 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1108 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1109 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1111 /* Make TX ring reflect state of hardware */
1115 /* Housework before enabling TX IRQ */
1116 macb_writel(bp, TSR, macb_readl(bp, TSR));
1117 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1119 /* Now we are ready to start transmission again */
1120 netif_tx_start_all_queues(bp->dev);
1121 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1123 spin_unlock_irqrestore(&bp->lock, flags);
1124 napi_enable(&queue->napi_tx);
1127 static bool ptp_one_step_sync(struct sk_buff *skb)
1129 struct ptp_header *hdr;
1130 unsigned int ptp_class;
1133 /* No need to parse packet if PTP TS is not involved */
1134 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
1137 /* Identify and return whether PTP one step sync is being processed */
1138 ptp_class = ptp_classify_raw(skb);
1139 if (ptp_class == PTP_CLASS_NONE)
1142 hdr = ptp_parse_header(skb, ptp_class);
1146 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP)
1149 msgtype = ptp_get_msgtype(hdr, ptp_class);
1150 if (msgtype == PTP_MSGTYPE_SYNC)
1157 static int macb_tx_complete(struct macb_queue *queue, int budget)
1159 struct macb *bp = queue->bp;
1160 u16 queue_index = queue - bp->queues;
1165 spin_lock(&queue->tx_ptr_lock);
1166 head = queue->tx_head;
1167 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) {
1168 struct macb_tx_skb *tx_skb;
1169 struct sk_buff *skb;
1170 struct macb_dma_desc *desc;
1173 desc = macb_tx_desc(queue, tail);
1175 /* Make hw descriptor updates visible to CPU */
1180 /* TX_USED bit is only set by hardware on the very first buffer
1181 * descriptor of the transmitted frame.
1183 if (!(ctrl & MACB_BIT(TX_USED)))
1186 /* Process all buffers of the current transmitted frame */
1188 tx_skb = macb_tx_skb(queue, tail);
1191 /* First, update TX stats if needed */
1193 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1194 !ptp_one_step_sync(skb) &&
1195 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1196 /* skb now belongs to timestamp buffer
1197 * and will be removed later
1201 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1202 macb_tx_ring_wrap(bp, tail),
1204 bp->dev->stats.tx_packets++;
1205 queue->stats.tx_packets++;
1206 bp->dev->stats.tx_bytes += skb->len;
1207 queue->stats.tx_bytes += skb->len;
1211 /* Now we can safely release resources */
1212 macb_tx_unmap(bp, tx_skb, budget);
1214 /* skb is set only for the last buffer of the frame.
1215 * WARNING: at this point skb has been freed by
1223 queue->tx_tail = tail;
1224 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1225 CIRC_CNT(queue->tx_head, queue->tx_tail,
1226 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1227 netif_wake_subqueue(bp->dev, queue_index);
1228 spin_unlock(&queue->tx_ptr_lock);
1233 static void gem_rx_refill(struct macb_queue *queue)
1236 struct sk_buff *skb;
1238 struct macb *bp = queue->bp;
1239 struct macb_dma_desc *desc;
1241 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1242 bp->rx_ring_size) > 0) {
1243 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1245 /* Make hw descriptor updates visible to CPU */
1248 desc = macb_rx_desc(queue, entry);
1250 if (!queue->rx_skbuff[entry]) {
1251 /* allocate sk_buff for this free entry in ring */
1252 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1253 if (unlikely(!skb)) {
1255 "Unable to allocate sk_buff\n");
1259 /* now fill corresponding descriptor entry */
1260 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1263 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1268 queue->rx_skbuff[entry] = skb;
1270 if (entry == bp->rx_ring_size - 1)
1271 paddr |= MACB_BIT(RX_WRAP);
1273 /* Setting addr clears RX_USED and allows reception,
1274 * make sure ctrl is cleared first to avoid a race.
1277 macb_set_addr(bp, desc, paddr);
1279 /* properly align Ethernet header */
1280 skb_reserve(skb, NET_IP_ALIGN);
1284 desc->addr &= ~MACB_BIT(RX_USED);
1286 queue->rx_prepared_head++;
1289 /* Make descriptor updates visible to hardware */
1292 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1293 queue, queue->rx_prepared_head, queue->rx_tail);
1296 /* Mark DMA descriptors from begin up to and not including end as unused */
1297 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1302 for (frag = begin; frag != end; frag++) {
1303 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1305 desc->addr &= ~MACB_BIT(RX_USED);
1308 /* Make descriptor updates visible to hardware */
1311 /* When this happens, the hardware stats registers for
1312 * whatever caused this is updated, so we don't have to record
1317 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1320 struct macb *bp = queue->bp;
1323 struct sk_buff *skb;
1324 struct macb_dma_desc *desc;
1327 while (count < budget) {
1332 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1333 desc = macb_rx_desc(queue, entry);
1335 /* Make hw descriptor updates visible to CPU */
1338 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1339 addr = macb_get_addr(bp, desc);
1344 /* Ensure ctrl is at least as up-to-date as rxused */
1352 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1354 "not whole frame pointed by descriptor\n");
1355 bp->dev->stats.rx_dropped++;
1356 queue->stats.rx_dropped++;
1359 skb = queue->rx_skbuff[entry];
1360 if (unlikely(!skb)) {
1362 "inconsistent Rx descriptor chain\n");
1363 bp->dev->stats.rx_dropped++;
1364 queue->stats.rx_dropped++;
1367 /* now everything is ready for receiving packet */
1368 queue->rx_skbuff[entry] = NULL;
1369 len = ctrl & bp->rx_frm_len_mask;
1371 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1374 dma_unmap_single(&bp->pdev->dev, addr,
1375 bp->rx_buffer_size, DMA_FROM_DEVICE);
1377 skb->protocol = eth_type_trans(skb, bp->dev);
1378 skb_checksum_none_assert(skb);
1379 if (bp->dev->features & NETIF_F_RXCSUM &&
1380 !(bp->dev->flags & IFF_PROMISC) &&
1381 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1382 skb->ip_summed = CHECKSUM_UNNECESSARY;
1384 bp->dev->stats.rx_packets++;
1385 queue->stats.rx_packets++;
1386 bp->dev->stats.rx_bytes += skb->len;
1387 queue->stats.rx_bytes += skb->len;
1389 gem_ptp_do_rxstamp(bp, skb, desc);
1391 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1392 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1393 skb->len, skb->csum);
1394 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1395 skb_mac_header(skb), 16, true);
1396 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1397 skb->data, 32, true);
1400 napi_gro_receive(napi, skb);
1403 gem_rx_refill(queue);
1408 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1409 unsigned int first_frag, unsigned int last_frag)
1413 unsigned int offset;
1414 struct sk_buff *skb;
1415 struct macb_dma_desc *desc;
1416 struct macb *bp = queue->bp;
1418 desc = macb_rx_desc(queue, last_frag);
1419 len = desc->ctrl & bp->rx_frm_len_mask;
1421 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1422 macb_rx_ring_wrap(bp, first_frag),
1423 macb_rx_ring_wrap(bp, last_frag), len);
1425 /* The ethernet header starts NET_IP_ALIGN bytes into the
1426 * first buffer. Since the header is 14 bytes, this makes the
1427 * payload word-aligned.
1429 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1430 * the two padding bytes into the skb so that we avoid hitting
1431 * the slowpath in memcpy(), and pull them off afterwards.
1433 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1435 bp->dev->stats.rx_dropped++;
1436 for (frag = first_frag; ; frag++) {
1437 desc = macb_rx_desc(queue, frag);
1438 desc->addr &= ~MACB_BIT(RX_USED);
1439 if (frag == last_frag)
1443 /* Make descriptor updates visible to hardware */
1450 len += NET_IP_ALIGN;
1451 skb_checksum_none_assert(skb);
1454 for (frag = first_frag; ; frag++) {
1455 unsigned int frag_len = bp->rx_buffer_size;
1457 if (offset + frag_len > len) {
1458 if (unlikely(frag != last_frag)) {
1459 dev_kfree_skb_any(skb);
1462 frag_len = len - offset;
1464 skb_copy_to_linear_data_offset(skb, offset,
1465 macb_rx_buffer(queue, frag),
1467 offset += bp->rx_buffer_size;
1468 desc = macb_rx_desc(queue, frag);
1469 desc->addr &= ~MACB_BIT(RX_USED);
1471 if (frag == last_frag)
1475 /* Make descriptor updates visible to hardware */
1478 __skb_pull(skb, NET_IP_ALIGN);
1479 skb->protocol = eth_type_trans(skb, bp->dev);
1481 bp->dev->stats.rx_packets++;
1482 bp->dev->stats.rx_bytes += skb->len;
1483 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1484 skb->len, skb->csum);
1485 napi_gro_receive(napi, skb);
1490 static inline void macb_init_rx_ring(struct macb_queue *queue)
1492 struct macb *bp = queue->bp;
1494 struct macb_dma_desc *desc = NULL;
1497 addr = queue->rx_buffers_dma;
1498 for (i = 0; i < bp->rx_ring_size; i++) {
1499 desc = macb_rx_desc(queue, i);
1500 macb_set_addr(bp, desc, addr);
1502 addr += bp->rx_buffer_size;
1504 desc->addr |= MACB_BIT(RX_WRAP);
1508 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1511 struct macb *bp = queue->bp;
1512 bool reset_rx_queue = false;
1515 int first_frag = -1;
1517 for (tail = queue->rx_tail; budget > 0; tail++) {
1518 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1521 /* Make hw descriptor updates visible to CPU */
1524 if (!(desc->addr & MACB_BIT(RX_USED)))
1527 /* Ensure ctrl is at least as up-to-date as addr */
1532 if (ctrl & MACB_BIT(RX_SOF)) {
1533 if (first_frag != -1)
1534 discard_partial_frame(queue, first_frag, tail);
1538 if (ctrl & MACB_BIT(RX_EOF)) {
1541 if (unlikely(first_frag == -1)) {
1542 reset_rx_queue = true;
1546 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1548 if (unlikely(dropped < 0)) {
1549 reset_rx_queue = true;
1559 if (unlikely(reset_rx_queue)) {
1560 unsigned long flags;
1563 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1565 spin_lock_irqsave(&bp->lock, flags);
1567 ctrl = macb_readl(bp, NCR);
1568 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1570 macb_init_rx_ring(queue);
1571 queue_writel(queue, RBQP, queue->rx_ring_dma);
1573 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1575 spin_unlock_irqrestore(&bp->lock, flags);
1579 if (first_frag != -1)
1580 queue->rx_tail = first_frag;
1582 queue->rx_tail = tail;
1587 static bool macb_rx_pending(struct macb_queue *queue)
1589 struct macb *bp = queue->bp;
1591 struct macb_dma_desc *desc;
1593 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1594 desc = macb_rx_desc(queue, entry);
1596 /* Make hw descriptor updates visible to CPU */
1599 return (desc->addr & MACB_BIT(RX_USED)) != 0;
1602 static int macb_rx_poll(struct napi_struct *napi, int budget)
1604 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx);
1605 struct macb *bp = queue->bp;
1608 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1610 netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n",
1611 (unsigned int)(queue - bp->queues), work_done, budget);
1613 if (work_done < budget && napi_complete_done(napi, work_done)) {
1614 queue_writel(queue, IER, bp->rx_intr_mask);
1616 /* Packet completions only seem to propagate to raise
1617 * interrupts when interrupts are enabled at the time, so if
1618 * packets were received while interrupts were disabled,
1619 * they will not cause another interrupt to be generated when
1620 * interrupts are re-enabled.
1621 * Check for this case here to avoid losing a wakeup. This can
1622 * potentially race with the interrupt handler doing the same
1623 * actions if an interrupt is raised just after enabling them,
1624 * but this should be harmless.
1626 if (macb_rx_pending(queue)) {
1627 queue_writel(queue, IDR, bp->rx_intr_mask);
1628 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1629 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1630 netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n");
1631 napi_schedule(napi);
1635 /* TODO: Handle errors */
1640 static void macb_tx_restart(struct macb_queue *queue)
1642 struct macb *bp = queue->bp;
1643 unsigned int head_idx, tbqp;
1645 spin_lock(&queue->tx_ptr_lock);
1647 if (queue->tx_head == queue->tx_tail)
1648 goto out_tx_ptr_unlock;
1650 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1651 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1652 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head));
1654 if (tbqp == head_idx)
1655 goto out_tx_ptr_unlock;
1657 spin_lock_irq(&bp->lock);
1658 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1659 spin_unlock_irq(&bp->lock);
1662 spin_unlock(&queue->tx_ptr_lock);
1665 static bool macb_tx_complete_pending(struct macb_queue *queue)
1667 bool retval = false;
1669 spin_lock(&queue->tx_ptr_lock);
1670 if (queue->tx_head != queue->tx_tail) {
1671 /* Make hw descriptor updates visible to CPU */
1674 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED))
1677 spin_unlock(&queue->tx_ptr_lock);
1681 static int macb_tx_poll(struct napi_struct *napi, int budget)
1683 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx);
1684 struct macb *bp = queue->bp;
1687 work_done = macb_tx_complete(queue, budget);
1689 rmb(); // ensure txubr_pending is up to date
1690 if (queue->txubr_pending) {
1691 queue->txubr_pending = false;
1692 netdev_vdbg(bp->dev, "poll: tx restart\n");
1693 macb_tx_restart(queue);
1696 netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n",
1697 (unsigned int)(queue - bp->queues), work_done, budget);
1699 if (work_done < budget && napi_complete_done(napi, work_done)) {
1700 queue_writel(queue, IER, MACB_BIT(TCOMP));
1702 /* Packet completions only seem to propagate to raise
1703 * interrupts when interrupts are enabled at the time, so if
1704 * packets were sent while interrupts were disabled,
1705 * they will not cause another interrupt to be generated when
1706 * interrupts are re-enabled.
1707 * Check for this case here to avoid losing a wakeup. This can
1708 * potentially race with the interrupt handler doing the same
1709 * actions if an interrupt is raised just after enabling them,
1710 * but this should be harmless.
1712 if (macb_tx_complete_pending(queue)) {
1713 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1714 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1715 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1716 netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n");
1717 napi_schedule(napi);
1724 static void macb_hresp_error_task(struct tasklet_struct *t)
1726 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1727 struct net_device *dev = bp->dev;
1728 struct macb_queue *queue;
1732 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1733 queue_writel(queue, IDR, bp->rx_intr_mask |
1737 ctrl = macb_readl(bp, NCR);
1738 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1739 macb_writel(bp, NCR, ctrl);
1741 netif_tx_stop_all_queues(dev);
1742 netif_carrier_off(dev);
1744 bp->macbgem_ops.mog_init_rings(bp);
1746 /* Initialize TX and RX buffers */
1747 macb_init_buffers(bp);
1749 /* Enable interrupts */
1750 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1751 queue_writel(queue, IER,
1756 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1757 macb_writel(bp, NCR, ctrl);
1759 netif_carrier_on(dev);
1760 netif_tx_start_all_queues(dev);
1763 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1765 struct macb_queue *queue = dev_id;
1766 struct macb *bp = queue->bp;
1769 status = queue_readl(queue, ISR);
1771 if (unlikely(!status))
1774 spin_lock(&bp->lock);
1776 if (status & MACB_BIT(WOL)) {
1777 queue_writel(queue, IDR, MACB_BIT(WOL));
1778 macb_writel(bp, WOL, 0);
1779 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1780 (unsigned int)(queue - bp->queues),
1781 (unsigned long)status);
1782 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1783 queue_writel(queue, ISR, MACB_BIT(WOL));
1784 pm_wakeup_event(&bp->pdev->dev, 0);
1787 spin_unlock(&bp->lock);
1792 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1794 struct macb_queue *queue = dev_id;
1795 struct macb *bp = queue->bp;
1798 status = queue_readl(queue, ISR);
1800 if (unlikely(!status))
1803 spin_lock(&bp->lock);
1805 if (status & GEM_BIT(WOL)) {
1806 queue_writel(queue, IDR, GEM_BIT(WOL));
1807 gem_writel(bp, WOL, 0);
1808 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1809 (unsigned int)(queue - bp->queues),
1810 (unsigned long)status);
1811 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1812 queue_writel(queue, ISR, GEM_BIT(WOL));
1813 pm_wakeup_event(&bp->pdev->dev, 0);
1816 spin_unlock(&bp->lock);
1821 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1823 struct macb_queue *queue = dev_id;
1824 struct macb *bp = queue->bp;
1825 struct net_device *dev = bp->dev;
1828 status = queue_readl(queue, ISR);
1830 if (unlikely(!status))
1833 spin_lock(&bp->lock);
1836 /* close possible race with dev_close */
1837 if (unlikely(!netif_running(dev))) {
1838 queue_writel(queue, IDR, -1);
1839 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1840 queue_writel(queue, ISR, -1);
1844 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1845 (unsigned int)(queue - bp->queues),
1846 (unsigned long)status);
1848 if (status & bp->rx_intr_mask) {
1849 /* There's no point taking any more interrupts
1850 * until we have processed the buffers. The
1851 * scheduling call may fail if the poll routine
1852 * is already scheduled, so disable interrupts
1855 queue_writel(queue, IDR, bp->rx_intr_mask);
1856 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1857 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1859 if (napi_schedule_prep(&queue->napi_rx)) {
1860 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1861 __napi_schedule(&queue->napi_rx);
1865 if (status & (MACB_BIT(TCOMP) |
1867 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1868 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1869 queue_writel(queue, ISR, MACB_BIT(TCOMP) |
1872 if (status & MACB_BIT(TXUBR)) {
1873 queue->txubr_pending = true;
1874 wmb(); // ensure softirq can see update
1877 if (napi_schedule_prep(&queue->napi_tx)) {
1878 netdev_vdbg(bp->dev, "scheduling TX softirq\n");
1879 __napi_schedule(&queue->napi_tx);
1883 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1884 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1885 schedule_work(&queue->tx_error_task);
1887 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1888 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1893 /* Link change detection isn't possible with RMII, so we'll
1894 * add that if/when we get our hands on a full-blown MII PHY.
1897 /* There is a hardware issue under heavy load where DMA can
1898 * stop, this causes endless "used buffer descriptor read"
1899 * interrupts but it can be cleared by re-enabling RX. See
1900 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1901 * section 16.7.4 for details. RXUBR is only enabled for
1902 * these two versions.
1904 if (status & MACB_BIT(RXUBR)) {
1905 ctrl = macb_readl(bp, NCR);
1906 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1908 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1910 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1911 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1914 if (status & MACB_BIT(ISR_ROVR)) {
1915 /* We missed at least one packet */
1916 if (macb_is_gem(bp))
1917 bp->hw_stats.gem.rx_overruns++;
1919 bp->hw_stats.macb.rx_overruns++;
1921 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1922 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1925 if (status & MACB_BIT(HRESP)) {
1926 tasklet_schedule(&bp->hresp_err_tasklet);
1927 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1929 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1930 queue_writel(queue, ISR, MACB_BIT(HRESP));
1932 status = queue_readl(queue, ISR);
1935 spin_unlock(&bp->lock);
1940 #ifdef CONFIG_NET_POLL_CONTROLLER
1941 /* Polling receive - used by netconsole and other diagnostic tools
1942 * to allow network i/o with interrupts disabled.
1944 static void macb_poll_controller(struct net_device *dev)
1946 struct macb *bp = netdev_priv(dev);
1947 struct macb_queue *queue;
1948 unsigned long flags;
1951 local_irq_save(flags);
1952 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1953 macb_interrupt(dev->irq, queue);
1954 local_irq_restore(flags);
1958 static unsigned int macb_tx_map(struct macb *bp,
1959 struct macb_queue *queue,
1960 struct sk_buff *skb,
1961 unsigned int hdrlen)
1964 unsigned int len, entry, i, tx_head = queue->tx_head;
1965 struct macb_tx_skb *tx_skb = NULL;
1966 struct macb_dma_desc *desc;
1967 unsigned int offset, size, count = 0;
1968 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1969 unsigned int eof = 1, mss_mfs = 0;
1970 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1973 if (skb_shinfo(skb)->gso_size != 0) {
1974 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1976 lso_ctrl = MACB_LSO_UFO_ENABLE;
1979 lso_ctrl = MACB_LSO_TSO_ENABLE;
1982 /* First, map non-paged data */
1983 len = skb_headlen(skb);
1985 /* first buffer length */
1990 entry = macb_tx_ring_wrap(bp, tx_head);
1991 tx_skb = &queue->tx_skb[entry];
1993 mapping = dma_map_single(&bp->pdev->dev,
1995 size, DMA_TO_DEVICE);
1996 if (dma_mapping_error(&bp->pdev->dev, mapping))
1999 /* Save info to properly release resources */
2001 tx_skb->mapping = mapping;
2002 tx_skb->size = size;
2003 tx_skb->mapped_as_page = false;
2010 size = min(len, bp->max_tx_length);
2013 /* Then, map paged data from fragments */
2014 for (f = 0; f < nr_frags; f++) {
2015 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2017 len = skb_frag_size(frag);
2020 size = min(len, bp->max_tx_length);
2021 entry = macb_tx_ring_wrap(bp, tx_head);
2022 tx_skb = &queue->tx_skb[entry];
2024 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
2025 offset, size, DMA_TO_DEVICE);
2026 if (dma_mapping_error(&bp->pdev->dev, mapping))
2029 /* Save info to properly release resources */
2031 tx_skb->mapping = mapping;
2032 tx_skb->size = size;
2033 tx_skb->mapped_as_page = true;
2042 /* Should never happen */
2043 if (unlikely(!tx_skb)) {
2044 netdev_err(bp->dev, "BUG! empty skb!\n");
2048 /* This is the last buffer of the frame: save socket buffer */
2051 /* Update TX ring: update buffer descriptors in reverse order
2052 * to avoid race condition
2055 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
2056 * to set the end of TX queue
2059 entry = macb_tx_ring_wrap(bp, i);
2060 ctrl = MACB_BIT(TX_USED);
2061 desc = macb_tx_desc(queue, entry);
2065 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
2066 /* include header and FCS in value given to h/w */
2067 mss_mfs = skb_shinfo(skb)->gso_size +
2068 skb_transport_offset(skb) +
2071 mss_mfs = skb_shinfo(skb)->gso_size;
2072 /* TCP Sequence Number Source Select
2073 * can be set only for TSO
2081 entry = macb_tx_ring_wrap(bp, i);
2082 tx_skb = &queue->tx_skb[entry];
2083 desc = macb_tx_desc(queue, entry);
2085 ctrl = (u32)tx_skb->size;
2087 ctrl |= MACB_BIT(TX_LAST);
2090 if (unlikely(entry == (bp->tx_ring_size - 1)))
2091 ctrl |= MACB_BIT(TX_WRAP);
2093 /* First descriptor is header descriptor */
2094 if (i == queue->tx_head) {
2095 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2096 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2097 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2098 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl &&
2099 !ptp_one_step_sync(skb))
2100 ctrl |= MACB_BIT(TX_NOCRC);
2102 /* Only set MSS/MFS on payload descriptors
2103 * (second or later descriptor)
2105 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2107 /* Set TX buffer descriptor */
2108 macb_set_addr(bp, desc, tx_skb->mapping);
2109 /* desc->addr must be visible to hardware before clearing
2110 * 'TX_USED' bit in desc->ctrl.
2114 } while (i != queue->tx_head);
2116 queue->tx_head = tx_head;
2121 netdev_err(bp->dev, "TX DMA map failed\n");
2123 for (i = queue->tx_head; i != tx_head; i++) {
2124 tx_skb = macb_tx_skb(queue, i);
2126 macb_tx_unmap(bp, tx_skb, 0);
2132 static netdev_features_t macb_features_check(struct sk_buff *skb,
2133 struct net_device *dev,
2134 netdev_features_t features)
2136 unsigned int nr_frags, f;
2137 unsigned int hdrlen;
2139 /* Validate LSO compatibility */
2141 /* there is only one buffer or protocol is not UDP */
2142 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2145 /* length of header */
2146 hdrlen = skb_transport_offset(skb);
2149 * When software supplies two or more payload buffers all payload buffers
2150 * apart from the last must be a multiple of 8 bytes in size.
2152 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2153 return features & ~MACB_NETIF_LSO;
2155 nr_frags = skb_shinfo(skb)->nr_frags;
2156 /* No need to check last fragment */
2158 for (f = 0; f < nr_frags; f++) {
2159 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2161 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2162 return features & ~MACB_NETIF_LSO;
2167 static inline int macb_clear_csum(struct sk_buff *skb)
2169 /* no change for packets without checksum offloading */
2170 if (skb->ip_summed != CHECKSUM_PARTIAL)
2173 /* make sure we can modify the header */
2174 if (unlikely(skb_cow_head(skb, 0)))
2177 /* initialize checksum field
2178 * This is required - at least for Zynq, which otherwise calculates
2179 * wrong UDP header checksums for UDP packets with UDP data len <=2
2181 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2185 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2187 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2188 skb_is_nonlinear(*skb);
2189 int padlen = ETH_ZLEN - (*skb)->len;
2190 int headroom = skb_headroom(*skb);
2191 int tailroom = skb_tailroom(*skb);
2192 struct sk_buff *nskb;
2195 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2196 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2197 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb))
2201 /* FCS could be appeded to tailroom. */
2202 if (tailroom >= ETH_FCS_LEN)
2204 /* FCS could be appeded by moving data to headroom. */
2205 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
2207 /* No room for FCS, need to reallocate skb. */
2209 padlen = ETH_FCS_LEN;
2211 /* Add room for FCS. */
2212 padlen += ETH_FCS_LEN;
2215 if (!cloned && headroom + tailroom >= padlen) {
2216 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
2217 skb_set_tail_pointer(*skb, (*skb)->len);
2219 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2223 dev_consume_skb_any(*skb);
2227 if (padlen > ETH_FCS_LEN)
2228 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2231 /* set FCS to packet */
2232 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2235 skb_put_u8(*skb, fcs & 0xff);
2236 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2237 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2238 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2243 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2245 u16 queue_index = skb_get_queue_mapping(skb);
2246 struct macb *bp = netdev_priv(dev);
2247 struct macb_queue *queue = &bp->queues[queue_index];
2248 unsigned int desc_cnt, nr_frags, frag_size, f;
2249 unsigned int hdrlen;
2251 netdev_tx_t ret = NETDEV_TX_OK;
2253 if (macb_clear_csum(skb)) {
2254 dev_kfree_skb_any(skb);
2258 if (macb_pad_and_fcs(&skb, dev)) {
2259 dev_kfree_skb_any(skb);
2263 is_lso = (skb_shinfo(skb)->gso_size != 0);
2266 /* length of headers */
2267 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2268 /* only queue eth + ip headers separately for UDP */
2269 hdrlen = skb_transport_offset(skb);
2271 hdrlen = skb_tcp_all_headers(skb);
2272 if (skb_headlen(skb) < hdrlen) {
2273 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2274 /* if this is required, would need to copy to single buffer */
2275 return NETDEV_TX_BUSY;
2278 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2280 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2281 netdev_vdbg(bp->dev,
2282 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2283 queue_index, skb->len, skb->head, skb->data,
2284 skb_tail_pointer(skb), skb_end_pointer(skb));
2285 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2286 skb->data, 16, true);
2289 /* Count how many TX buffer descriptors are needed to send this
2290 * socket buffer: skb fragments of jumbo frames may need to be
2291 * split into many buffer descriptors.
2293 if (is_lso && (skb_headlen(skb) > hdrlen))
2294 /* extra header descriptor if also payload in first buffer */
2295 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2297 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2298 nr_frags = skb_shinfo(skb)->nr_frags;
2299 for (f = 0; f < nr_frags; f++) {
2300 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2301 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2304 spin_lock_bh(&queue->tx_ptr_lock);
2306 /* This is a hard error, log it. */
2307 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2308 bp->tx_ring_size) < desc_cnt) {
2309 netif_stop_subqueue(dev, queue_index);
2310 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2311 queue->tx_head, queue->tx_tail);
2312 ret = NETDEV_TX_BUSY;
2316 /* Map socket buffer for DMA transfer */
2317 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2318 dev_kfree_skb_any(skb);
2322 /* Make newly initialized descriptor visible to hardware */
2324 skb_tx_timestamp(skb);
2326 spin_lock_irq(&bp->lock);
2327 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2328 spin_unlock_irq(&bp->lock);
2330 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2331 netif_stop_subqueue(dev, queue_index);
2334 spin_unlock_bh(&queue->tx_ptr_lock);
2339 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2341 if (!macb_is_gem(bp)) {
2342 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2344 bp->rx_buffer_size = size;
2346 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2348 "RX buffer must be multiple of %d bytes, expanding\n",
2349 RX_BUFFER_MULTIPLE);
2350 bp->rx_buffer_size =
2351 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2355 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2356 bp->dev->mtu, bp->rx_buffer_size);
2359 static void gem_free_rx_buffers(struct macb *bp)
2361 struct sk_buff *skb;
2362 struct macb_dma_desc *desc;
2363 struct macb_queue *queue;
2368 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2369 if (!queue->rx_skbuff)
2372 for (i = 0; i < bp->rx_ring_size; i++) {
2373 skb = queue->rx_skbuff[i];
2378 desc = macb_rx_desc(queue, i);
2379 addr = macb_get_addr(bp, desc);
2381 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2383 dev_kfree_skb_any(skb);
2387 kfree(queue->rx_skbuff);
2388 queue->rx_skbuff = NULL;
2392 static void macb_free_rx_buffers(struct macb *bp)
2394 struct macb_queue *queue = &bp->queues[0];
2396 if (queue->rx_buffers) {
2397 dma_free_coherent(&bp->pdev->dev,
2398 bp->rx_ring_size * bp->rx_buffer_size,
2399 queue->rx_buffers, queue->rx_buffers_dma);
2400 queue->rx_buffers = NULL;
2404 static void macb_free_consistent(struct macb *bp)
2406 struct macb_queue *queue;
2410 bp->macbgem_ops.mog_free_rx_buffers(bp);
2412 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2413 kfree(queue->tx_skb);
2414 queue->tx_skb = NULL;
2415 if (queue->tx_ring) {
2416 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2417 dma_free_coherent(&bp->pdev->dev, size,
2418 queue->tx_ring, queue->tx_ring_dma);
2419 queue->tx_ring = NULL;
2421 if (queue->rx_ring) {
2422 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2423 dma_free_coherent(&bp->pdev->dev, size,
2424 queue->rx_ring, queue->rx_ring_dma);
2425 queue->rx_ring = NULL;
2430 static int gem_alloc_rx_buffers(struct macb *bp)
2432 struct macb_queue *queue;
2436 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2437 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2438 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2439 if (!queue->rx_skbuff)
2443 "Allocated %d RX struct sk_buff entries at %p\n",
2444 bp->rx_ring_size, queue->rx_skbuff);
2449 static int macb_alloc_rx_buffers(struct macb *bp)
2451 struct macb_queue *queue = &bp->queues[0];
2454 size = bp->rx_ring_size * bp->rx_buffer_size;
2455 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2456 &queue->rx_buffers_dma, GFP_KERNEL);
2457 if (!queue->rx_buffers)
2461 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2462 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2466 static int macb_alloc_consistent(struct macb *bp)
2468 struct macb_queue *queue;
2472 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2473 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2474 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2475 &queue->tx_ring_dma,
2477 if (!queue->tx_ring)
2480 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2481 q, size, (unsigned long)queue->tx_ring_dma,
2484 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2485 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2489 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2490 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2491 &queue->rx_ring_dma, GFP_KERNEL);
2492 if (!queue->rx_ring)
2495 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2496 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2498 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2504 macb_free_consistent(bp);
2508 static void gem_init_rings(struct macb *bp)
2510 struct macb_queue *queue;
2511 struct macb_dma_desc *desc = NULL;
2515 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2516 for (i = 0; i < bp->tx_ring_size; i++) {
2517 desc = macb_tx_desc(queue, i);
2518 macb_set_addr(bp, desc, 0);
2519 desc->ctrl = MACB_BIT(TX_USED);
2521 desc->ctrl |= MACB_BIT(TX_WRAP);
2526 queue->rx_prepared_head = 0;
2528 gem_rx_refill(queue);
2533 static void macb_init_rings(struct macb *bp)
2536 struct macb_dma_desc *desc = NULL;
2538 macb_init_rx_ring(&bp->queues[0]);
2540 for (i = 0; i < bp->tx_ring_size; i++) {
2541 desc = macb_tx_desc(&bp->queues[0], i);
2542 macb_set_addr(bp, desc, 0);
2543 desc->ctrl = MACB_BIT(TX_USED);
2545 bp->queues[0].tx_head = 0;
2546 bp->queues[0].tx_tail = 0;
2547 desc->ctrl |= MACB_BIT(TX_WRAP);
2550 static void macb_reset_hw(struct macb *bp)
2552 struct macb_queue *queue;
2554 u32 ctrl = macb_readl(bp, NCR);
2556 /* Disable RX and TX (XXX: Should we halt the transmission
2559 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2561 /* Clear the stats registers (XXX: Update stats first?) */
2562 ctrl |= MACB_BIT(CLRSTAT);
2564 macb_writel(bp, NCR, ctrl);
2566 /* Clear all status flags */
2567 macb_writel(bp, TSR, -1);
2568 macb_writel(bp, RSR, -1);
2570 /* Disable all interrupts */
2571 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2572 queue_writel(queue, IDR, -1);
2573 queue_readl(queue, ISR);
2574 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2575 queue_writel(queue, ISR, -1);
2579 static u32 gem_mdc_clk_div(struct macb *bp)
2582 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2584 if (pclk_hz <= 20000000)
2585 config = GEM_BF(CLK, GEM_CLK_DIV8);
2586 else if (pclk_hz <= 40000000)
2587 config = GEM_BF(CLK, GEM_CLK_DIV16);
2588 else if (pclk_hz <= 80000000)
2589 config = GEM_BF(CLK, GEM_CLK_DIV32);
2590 else if (pclk_hz <= 120000000)
2591 config = GEM_BF(CLK, GEM_CLK_DIV48);
2592 else if (pclk_hz <= 160000000)
2593 config = GEM_BF(CLK, GEM_CLK_DIV64);
2595 config = GEM_BF(CLK, GEM_CLK_DIV96);
2600 static u32 macb_mdc_clk_div(struct macb *bp)
2603 unsigned long pclk_hz;
2605 if (macb_is_gem(bp))
2606 return gem_mdc_clk_div(bp);
2608 pclk_hz = clk_get_rate(bp->pclk);
2609 if (pclk_hz <= 20000000)
2610 config = MACB_BF(CLK, MACB_CLK_DIV8);
2611 else if (pclk_hz <= 40000000)
2612 config = MACB_BF(CLK, MACB_CLK_DIV16);
2613 else if (pclk_hz <= 80000000)
2614 config = MACB_BF(CLK, MACB_CLK_DIV32);
2616 config = MACB_BF(CLK, MACB_CLK_DIV64);
2621 /* Get the DMA bus width field of the network configuration register that we
2622 * should program. We find the width from decoding the design configuration
2623 * register to find the maximum supported data bus width.
2625 static u32 macb_dbw(struct macb *bp)
2627 if (!macb_is_gem(bp))
2630 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2632 return GEM_BF(DBW, GEM_DBW128);
2634 return GEM_BF(DBW, GEM_DBW64);
2637 return GEM_BF(DBW, GEM_DBW32);
2641 /* Configure the receive DMA engine
2642 * - use the correct receive buffer size
2643 * - set best burst length for DMA operations
2644 * (if not supported by FIFO, it will fallback to default)
2645 * - set both rx/tx packet buffers to full memory size
2646 * These are configurable parameters for GEM.
2648 static void macb_configure_dma(struct macb *bp)
2650 struct macb_queue *queue;
2655 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2656 if (macb_is_gem(bp)) {
2657 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2658 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2660 queue_writel(queue, RBQS, buffer_size);
2662 dmacfg |= GEM_BF(RXBS, buffer_size);
2664 if (bp->dma_burst_length)
2665 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2666 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2667 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2670 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2672 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2674 if (bp->dev->features & NETIF_F_HW_CSUM)
2675 dmacfg |= GEM_BIT(TXCOEN);
2677 dmacfg &= ~GEM_BIT(TXCOEN);
2679 dmacfg &= ~GEM_BIT(ADDR64);
2680 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2681 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2682 dmacfg |= GEM_BIT(ADDR64);
2684 #ifdef CONFIG_MACB_USE_HWSTAMP
2685 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2686 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2688 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2690 gem_writel(bp, DMACFG, dmacfg);
2694 static void macb_init_hw(struct macb *bp)
2699 macb_set_hwaddr(bp);
2701 config = macb_mdc_clk_div(bp);
2702 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2703 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2704 if (bp->caps & MACB_CAPS_JUMBO)
2705 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2707 config |= MACB_BIT(BIG); /* Receive oversized frames */
2708 if (bp->dev->flags & IFF_PROMISC)
2709 config |= MACB_BIT(CAF); /* Copy All Frames */
2710 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2711 config |= GEM_BIT(RXCOEN);
2712 if (!(bp->dev->flags & IFF_BROADCAST))
2713 config |= MACB_BIT(NBC); /* No BroadCast */
2714 config |= macb_dbw(bp);
2715 macb_writel(bp, NCFGR, config);
2716 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2717 gem_writel(bp, JML, bp->jumbo_max_len);
2718 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2719 if (bp->caps & MACB_CAPS_JUMBO)
2720 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2722 macb_configure_dma(bp);
2725 /* The hash address register is 64 bits long and takes up two
2726 * locations in the memory map. The least significant bits are stored
2727 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2729 * The unicast hash enable and the multicast hash enable bits in the
2730 * network configuration register enable the reception of hash matched
2731 * frames. The destination address is reduced to a 6 bit index into
2732 * the 64 bit hash register using the following hash function. The
2733 * hash function is an exclusive or of every sixth bit of the
2734 * destination address.
2736 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2737 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2738 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2739 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2740 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2741 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2743 * da[0] represents the least significant bit of the first byte
2744 * received, that is, the multicast/unicast indicator, and da[47]
2745 * represents the most significant bit of the last byte received. If
2746 * the hash index, hi[n], points to a bit that is set in the hash
2747 * register then the frame will be matched according to whether the
2748 * frame is multicast or unicast. A multicast match will be signalled
2749 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2750 * index points to a bit set in the hash register. A unicast match
2751 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2752 * and the hash index points to a bit set in the hash register. To
2753 * receive all multicast frames, the hash register should be set with
2754 * all ones and the multicast hash enable bit should be set in the
2755 * network configuration register.
2758 static inline int hash_bit_value(int bitnr, __u8 *addr)
2760 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2765 /* Return the hash index value for the specified address. */
2766 static int hash_get_index(__u8 *addr)
2771 for (j = 0; j < 6; j++) {
2772 for (i = 0, bitval = 0; i < 8; i++)
2773 bitval ^= hash_bit_value(i * 6 + j, addr);
2775 hash_index |= (bitval << j);
2781 /* Add multicast addresses to the internal multicast-hash table. */
2782 static void macb_sethashtable(struct net_device *dev)
2784 struct netdev_hw_addr *ha;
2785 unsigned long mc_filter[2];
2787 struct macb *bp = netdev_priv(dev);
2792 netdev_for_each_mc_addr(ha, dev) {
2793 bitnr = hash_get_index(ha->addr);
2794 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2797 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2798 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2801 /* Enable/Disable promiscuous and multicast modes. */
2802 static void macb_set_rx_mode(struct net_device *dev)
2805 struct macb *bp = netdev_priv(dev);
2807 cfg = macb_readl(bp, NCFGR);
2809 if (dev->flags & IFF_PROMISC) {
2810 /* Enable promiscuous mode */
2811 cfg |= MACB_BIT(CAF);
2813 /* Disable RX checksum offload */
2814 if (macb_is_gem(bp))
2815 cfg &= ~GEM_BIT(RXCOEN);
2817 /* Disable promiscuous mode */
2818 cfg &= ~MACB_BIT(CAF);
2820 /* Enable RX checksum offload only if requested */
2821 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2822 cfg |= GEM_BIT(RXCOEN);
2825 if (dev->flags & IFF_ALLMULTI) {
2826 /* Enable all multicast mode */
2827 macb_or_gem_writel(bp, HRB, -1);
2828 macb_or_gem_writel(bp, HRT, -1);
2829 cfg |= MACB_BIT(NCFGR_MTI);
2830 } else if (!netdev_mc_empty(dev)) {
2831 /* Enable specific multicasts */
2832 macb_sethashtable(dev);
2833 cfg |= MACB_BIT(NCFGR_MTI);
2834 } else if (dev->flags & (~IFF_ALLMULTI)) {
2835 /* Disable all multicast mode */
2836 macb_or_gem_writel(bp, HRB, 0);
2837 macb_or_gem_writel(bp, HRT, 0);
2838 cfg &= ~MACB_BIT(NCFGR_MTI);
2841 macb_writel(bp, NCFGR, cfg);
2844 static int macb_open(struct net_device *dev)
2846 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2847 struct macb *bp = netdev_priv(dev);
2848 struct macb_queue *queue;
2852 netdev_dbg(bp->dev, "open\n");
2854 err = pm_runtime_resume_and_get(&bp->pdev->dev);
2858 /* RX buffers initialization */
2859 macb_init_rx_buffer_size(bp, bufsz);
2861 err = macb_alloc_consistent(bp);
2863 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2868 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2869 napi_enable(&queue->napi_rx);
2870 napi_enable(&queue->napi_tx);
2875 err = phy_power_on(bp->sgmii_phy);
2879 err = macb_phylink_connect(bp);
2883 netif_tx_start_all_queues(dev);
2886 bp->ptp_info->ptp_init(dev);
2891 phy_power_off(bp->sgmii_phy);
2895 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2896 napi_disable(&queue->napi_rx);
2897 napi_disable(&queue->napi_tx);
2899 macb_free_consistent(bp);
2901 pm_runtime_put_sync(&bp->pdev->dev);
2905 static int macb_close(struct net_device *dev)
2907 struct macb *bp = netdev_priv(dev);
2908 struct macb_queue *queue;
2909 unsigned long flags;
2912 netif_tx_stop_all_queues(dev);
2914 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2915 napi_disable(&queue->napi_rx);
2916 napi_disable(&queue->napi_tx);
2919 phylink_stop(bp->phylink);
2920 phylink_disconnect_phy(bp->phylink);
2922 phy_power_off(bp->sgmii_phy);
2924 spin_lock_irqsave(&bp->lock, flags);
2926 netif_carrier_off(dev);
2927 spin_unlock_irqrestore(&bp->lock, flags);
2929 macb_free_consistent(bp);
2932 bp->ptp_info->ptp_remove(dev);
2934 pm_runtime_put(&bp->pdev->dev);
2939 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2941 if (netif_running(dev))
2949 static int macb_set_mac_addr(struct net_device *dev, void *addr)
2953 err = eth_mac_addr(dev, addr);
2957 macb_set_hwaddr(netdev_priv(dev));
2961 static void gem_update_stats(struct macb *bp)
2963 struct macb_queue *queue;
2964 unsigned int i, q, idx;
2965 unsigned long *stat;
2967 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2969 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2970 u32 offset = gem_statistics[i].offset;
2971 u64 val = bp->macb_reg_readl(bp, offset);
2973 bp->ethtool_stats[i] += val;
2976 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2977 /* Add GEM_OCTTXH, GEM_OCTRXH */
2978 val = bp->macb_reg_readl(bp, offset + 4);
2979 bp->ethtool_stats[i] += ((u64)val) << 32;
2984 idx = GEM_STATS_LEN;
2985 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2986 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2987 bp->ethtool_stats[idx++] = *stat;
2990 static struct net_device_stats *gem_get_stats(struct macb *bp)
2992 struct gem_stats *hwstat = &bp->hw_stats.gem;
2993 struct net_device_stats *nstat = &bp->dev->stats;
2995 if (!netif_running(bp->dev))
2998 gem_update_stats(bp);
3000 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
3001 hwstat->rx_alignment_errors +
3002 hwstat->rx_resource_errors +
3003 hwstat->rx_overruns +
3004 hwstat->rx_oversize_frames +
3005 hwstat->rx_jabbers +
3006 hwstat->rx_undersized_frames +
3007 hwstat->rx_length_field_frame_errors);
3008 nstat->tx_errors = (hwstat->tx_late_collisions +
3009 hwstat->tx_excessive_collisions +
3010 hwstat->tx_underrun +
3011 hwstat->tx_carrier_sense_errors);
3012 nstat->multicast = hwstat->rx_multicast_frames;
3013 nstat->collisions = (hwstat->tx_single_collision_frames +
3014 hwstat->tx_multiple_collision_frames +
3015 hwstat->tx_excessive_collisions);
3016 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
3017 hwstat->rx_jabbers +
3018 hwstat->rx_undersized_frames +
3019 hwstat->rx_length_field_frame_errors);
3020 nstat->rx_over_errors = hwstat->rx_resource_errors;
3021 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
3022 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
3023 nstat->rx_fifo_errors = hwstat->rx_overruns;
3024 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
3025 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
3026 nstat->tx_fifo_errors = hwstat->tx_underrun;
3031 static void gem_get_ethtool_stats(struct net_device *dev,
3032 struct ethtool_stats *stats, u64 *data)
3036 bp = netdev_priv(dev);
3037 gem_update_stats(bp);
3038 memcpy(data, &bp->ethtool_stats, sizeof(u64)
3039 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
3042 static int gem_get_sset_count(struct net_device *dev, int sset)
3044 struct macb *bp = netdev_priv(dev);
3048 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
3054 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
3056 char stat_string[ETH_GSTRING_LEN];
3057 struct macb *bp = netdev_priv(dev);
3058 struct macb_queue *queue;
3064 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
3065 memcpy(p, gem_statistics[i].stat_string,
3068 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3069 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
3070 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
3071 q, queue_statistics[i].stat_string);
3072 memcpy(p, stat_string, ETH_GSTRING_LEN);
3079 static struct net_device_stats *macb_get_stats(struct net_device *dev)
3081 struct macb *bp = netdev_priv(dev);
3082 struct net_device_stats *nstat = &bp->dev->stats;
3083 struct macb_stats *hwstat = &bp->hw_stats.macb;
3085 if (macb_is_gem(bp))
3086 return gem_get_stats(bp);
3088 /* read stats from hardware */
3089 macb_update_stats(bp);
3091 /* Convert HW stats into netdevice stats */
3092 nstat->rx_errors = (hwstat->rx_fcs_errors +
3093 hwstat->rx_align_errors +
3094 hwstat->rx_resource_errors +
3095 hwstat->rx_overruns +
3096 hwstat->rx_oversize_pkts +
3097 hwstat->rx_jabbers +
3098 hwstat->rx_undersize_pkts +
3099 hwstat->rx_length_mismatch);
3100 nstat->tx_errors = (hwstat->tx_late_cols +
3101 hwstat->tx_excessive_cols +
3102 hwstat->tx_underruns +
3103 hwstat->tx_carrier_errors +
3104 hwstat->sqe_test_errors);
3105 nstat->collisions = (hwstat->tx_single_cols +
3106 hwstat->tx_multiple_cols +
3107 hwstat->tx_excessive_cols);
3108 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
3109 hwstat->rx_jabbers +
3110 hwstat->rx_undersize_pkts +
3111 hwstat->rx_length_mismatch);
3112 nstat->rx_over_errors = hwstat->rx_resource_errors +
3113 hwstat->rx_overruns;
3114 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
3115 nstat->rx_frame_errors = hwstat->rx_align_errors;
3116 nstat->rx_fifo_errors = hwstat->rx_overruns;
3117 /* XXX: What does "missed" mean? */
3118 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3119 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3120 nstat->tx_fifo_errors = hwstat->tx_underruns;
3121 /* Don't know about heartbeat or window errors... */
3126 static int macb_get_regs_len(struct net_device *netdev)
3128 return MACB_GREGS_NBR * sizeof(u32);
3131 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3134 struct macb *bp = netdev_priv(dev);
3135 unsigned int tail, head;
3138 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3139 | MACB_GREGS_VERSION;
3141 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3142 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3144 regs_buff[0] = macb_readl(bp, NCR);
3145 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3146 regs_buff[2] = macb_readl(bp, NSR);
3147 regs_buff[3] = macb_readl(bp, TSR);
3148 regs_buff[4] = macb_readl(bp, RBQP);
3149 regs_buff[5] = macb_readl(bp, TBQP);
3150 regs_buff[6] = macb_readl(bp, RSR);
3151 regs_buff[7] = macb_readl(bp, IMR);
3153 regs_buff[8] = tail;
3154 regs_buff[9] = head;
3155 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3156 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3158 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3159 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3160 if (macb_is_gem(bp))
3161 regs_buff[13] = gem_readl(bp, DMACFG);
3164 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3166 struct macb *bp = netdev_priv(netdev);
3168 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
3169 phylink_ethtool_get_wol(bp->phylink, wol);
3170 wol->supported |= WAKE_MAGIC;
3172 if (bp->wol & MACB_WOL_ENABLED)
3173 wol->wolopts |= WAKE_MAGIC;
3177 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3179 struct macb *bp = netdev_priv(netdev);
3182 /* Pass the order to phylink layer */
3183 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3184 /* Don't manage WoL on MAC if handled by the PHY
3185 * or if there's a failure in talking to the PHY
3187 if (!ret || ret != -EOPNOTSUPP)
3190 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3191 (wol->wolopts & ~WAKE_MAGIC))
3194 if (wol->wolopts & WAKE_MAGIC)
3195 bp->wol |= MACB_WOL_ENABLED;
3197 bp->wol &= ~MACB_WOL_ENABLED;
3199 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3204 static int macb_get_link_ksettings(struct net_device *netdev,
3205 struct ethtool_link_ksettings *kset)
3207 struct macb *bp = netdev_priv(netdev);
3209 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3212 static int macb_set_link_ksettings(struct net_device *netdev,
3213 const struct ethtool_link_ksettings *kset)
3215 struct macb *bp = netdev_priv(netdev);
3217 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3220 static void macb_get_ringparam(struct net_device *netdev,
3221 struct ethtool_ringparam *ring,
3222 struct kernel_ethtool_ringparam *kernel_ring,
3223 struct netlink_ext_ack *extack)
3225 struct macb *bp = netdev_priv(netdev);
3227 ring->rx_max_pending = MAX_RX_RING_SIZE;
3228 ring->tx_max_pending = MAX_TX_RING_SIZE;
3230 ring->rx_pending = bp->rx_ring_size;
3231 ring->tx_pending = bp->tx_ring_size;
3234 static int macb_set_ringparam(struct net_device *netdev,
3235 struct ethtool_ringparam *ring,
3236 struct kernel_ethtool_ringparam *kernel_ring,
3237 struct netlink_ext_ack *extack)
3239 struct macb *bp = netdev_priv(netdev);
3240 u32 new_rx_size, new_tx_size;
3241 unsigned int reset = 0;
3243 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3246 new_rx_size = clamp_t(u32, ring->rx_pending,
3247 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3248 new_rx_size = roundup_pow_of_two(new_rx_size);
3250 new_tx_size = clamp_t(u32, ring->tx_pending,
3251 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3252 new_tx_size = roundup_pow_of_two(new_tx_size);
3254 if ((new_tx_size == bp->tx_ring_size) &&
3255 (new_rx_size == bp->rx_ring_size)) {
3260 if (netif_running(bp->dev)) {
3262 macb_close(bp->dev);
3265 bp->rx_ring_size = new_rx_size;
3266 bp->tx_ring_size = new_tx_size;
3274 #ifdef CONFIG_MACB_USE_HWSTAMP
3275 static unsigned int gem_get_tsu_rate(struct macb *bp)
3277 struct clk *tsu_clk;
3278 unsigned int tsu_rate;
3280 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3281 if (!IS_ERR(tsu_clk))
3282 tsu_rate = clk_get_rate(tsu_clk);
3283 /* try pclk instead */
3284 else if (!IS_ERR(bp->pclk)) {
3286 tsu_rate = clk_get_rate(tsu_clk);
3292 static s32 gem_get_ptp_max_adj(void)
3297 static int gem_get_ts_info(struct net_device *dev,
3298 struct ethtool_ts_info *info)
3300 struct macb *bp = netdev_priv(dev);
3302 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3303 ethtool_op_get_ts_info(dev, info);
3307 info->so_timestamping =
3308 SOF_TIMESTAMPING_TX_SOFTWARE |
3309 SOF_TIMESTAMPING_RX_SOFTWARE |
3310 SOF_TIMESTAMPING_SOFTWARE |
3311 SOF_TIMESTAMPING_TX_HARDWARE |
3312 SOF_TIMESTAMPING_RX_HARDWARE |
3313 SOF_TIMESTAMPING_RAW_HARDWARE;
3315 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3316 (1 << HWTSTAMP_TX_OFF) |
3317 (1 << HWTSTAMP_TX_ON);
3319 (1 << HWTSTAMP_FILTER_NONE) |
3320 (1 << HWTSTAMP_FILTER_ALL);
3322 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3327 static struct macb_ptp_info gem_ptp_info = {
3328 .ptp_init = gem_ptp_init,
3329 .ptp_remove = gem_ptp_remove,
3330 .get_ptp_max_adj = gem_get_ptp_max_adj,
3331 .get_tsu_rate = gem_get_tsu_rate,
3332 .get_ts_info = gem_get_ts_info,
3333 .get_hwtst = gem_get_hwtst,
3334 .set_hwtst = gem_set_hwtst,
3338 static int macb_get_ts_info(struct net_device *netdev,
3339 struct ethtool_ts_info *info)
3341 struct macb *bp = netdev_priv(netdev);
3344 return bp->ptp_info->get_ts_info(netdev, info);
3346 return ethtool_op_get_ts_info(netdev, info);
3349 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3351 struct net_device *netdev = bp->dev;
3352 struct ethtool_rx_fs_item *item;
3356 if (!(netdev->features & NETIF_F_NTUPLE))
3359 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3361 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3362 struct ethtool_rx_flow_spec *fs = &item->fs;
3363 struct ethtool_tcpip4_spec *tp4sp_m;
3365 if (fs->location >= num_t2_scr)
3368 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3370 /* enable/disable screener regs for the flow entry */
3371 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3373 /* only enable fields with no masking */
3374 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3376 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3377 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3379 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3381 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3382 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3384 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3386 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3387 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3389 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3391 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3395 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3397 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3398 uint16_t index = fs->location;
3404 if (!macb_is_gem(bp))
3407 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3408 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3410 /* ignore field if any masking set */
3411 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3412 /* 1st compare reg - IP source address */
3415 w0 = tp4sp_v->ip4src;
3416 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3417 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3418 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3419 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3420 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3424 /* ignore field if any masking set */
3425 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3426 /* 2nd compare reg - IP destination address */
3429 w0 = tp4sp_v->ip4dst;
3430 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3431 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3432 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3433 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3434 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3438 /* ignore both port fields if masking set in both */
3439 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3440 /* 3rd compare reg - source port, destination port */
3443 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3444 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3445 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3446 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3447 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3448 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3450 /* only one port definition */
3451 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3452 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3453 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3454 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3455 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3456 } else { /* dst port */
3457 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3458 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3461 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3462 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3467 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3468 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3470 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3472 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3474 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3475 gem_writel_n(bp, SCRT2, index, t2_scr);
3478 static int gem_add_flow_filter(struct net_device *netdev,
3479 struct ethtool_rxnfc *cmd)
3481 struct macb *bp = netdev_priv(netdev);
3482 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3483 struct ethtool_rx_fs_item *item, *newfs;
3484 unsigned long flags;
3488 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3491 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3494 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3495 fs->flow_type, (int)fs->ring_cookie, fs->location,
3496 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3497 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3498 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3499 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3501 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3503 /* find correct place to add in list */
3504 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3505 if (item->fs.location > newfs->fs.location) {
3506 list_add_tail(&newfs->list, &item->list);
3509 } else if (item->fs.location == fs->location) {
3510 netdev_err(netdev, "Rule not added: location %d not free!\n",
3517 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3519 gem_prog_cmp_regs(bp, fs);
3520 bp->rx_fs_list.count++;
3521 /* enable filtering if NTUPLE on */
3522 gem_enable_flow_filters(bp, 1);
3524 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3528 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3533 static int gem_del_flow_filter(struct net_device *netdev,
3534 struct ethtool_rxnfc *cmd)
3536 struct macb *bp = netdev_priv(netdev);
3537 struct ethtool_rx_fs_item *item;
3538 struct ethtool_rx_flow_spec *fs;
3539 unsigned long flags;
3541 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3543 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3544 if (item->fs.location == cmd->fs.location) {
3545 /* disable screener regs for the flow entry */
3548 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3549 fs->flow_type, (int)fs->ring_cookie, fs->location,
3550 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3551 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3552 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3553 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3555 gem_writel_n(bp, SCRT2, fs->location, 0);
3557 list_del(&item->list);
3558 bp->rx_fs_list.count--;
3559 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3565 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3569 static int gem_get_flow_entry(struct net_device *netdev,
3570 struct ethtool_rxnfc *cmd)
3572 struct macb *bp = netdev_priv(netdev);
3573 struct ethtool_rx_fs_item *item;
3575 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3576 if (item->fs.location == cmd->fs.location) {
3577 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3584 static int gem_get_all_flow_entries(struct net_device *netdev,
3585 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3587 struct macb *bp = netdev_priv(netdev);
3588 struct ethtool_rx_fs_item *item;
3591 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3592 if (cnt == cmd->rule_cnt)
3594 rule_locs[cnt] = item->fs.location;
3597 cmd->data = bp->max_tuples;
3598 cmd->rule_cnt = cnt;
3603 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3606 struct macb *bp = netdev_priv(netdev);
3610 case ETHTOOL_GRXRINGS:
3611 cmd->data = bp->num_queues;
3613 case ETHTOOL_GRXCLSRLCNT:
3614 cmd->rule_cnt = bp->rx_fs_list.count;
3616 case ETHTOOL_GRXCLSRULE:
3617 ret = gem_get_flow_entry(netdev, cmd);
3619 case ETHTOOL_GRXCLSRLALL:
3620 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3624 "Command parameter %d is not supported\n", cmd->cmd);
3631 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3633 struct macb *bp = netdev_priv(netdev);
3637 case ETHTOOL_SRXCLSRLINS:
3638 if ((cmd->fs.location >= bp->max_tuples)
3639 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3643 ret = gem_add_flow_filter(netdev, cmd);
3645 case ETHTOOL_SRXCLSRLDEL:
3646 ret = gem_del_flow_filter(netdev, cmd);
3650 "Command parameter %d is not supported\n", cmd->cmd);
3657 static const struct ethtool_ops macb_ethtool_ops = {
3658 .get_regs_len = macb_get_regs_len,
3659 .get_regs = macb_get_regs,
3660 .get_link = ethtool_op_get_link,
3661 .get_ts_info = ethtool_op_get_ts_info,
3662 .get_wol = macb_get_wol,
3663 .set_wol = macb_set_wol,
3664 .get_link_ksettings = macb_get_link_ksettings,
3665 .set_link_ksettings = macb_set_link_ksettings,
3666 .get_ringparam = macb_get_ringparam,
3667 .set_ringparam = macb_set_ringparam,
3670 static const struct ethtool_ops gem_ethtool_ops = {
3671 .get_regs_len = macb_get_regs_len,
3672 .get_regs = macb_get_regs,
3673 .get_wol = macb_get_wol,
3674 .set_wol = macb_set_wol,
3675 .get_link = ethtool_op_get_link,
3676 .get_ts_info = macb_get_ts_info,
3677 .get_ethtool_stats = gem_get_ethtool_stats,
3678 .get_strings = gem_get_ethtool_strings,
3679 .get_sset_count = gem_get_sset_count,
3680 .get_link_ksettings = macb_get_link_ksettings,
3681 .set_link_ksettings = macb_set_link_ksettings,
3682 .get_ringparam = macb_get_ringparam,
3683 .set_ringparam = macb_set_ringparam,
3684 .get_rxnfc = gem_get_rxnfc,
3685 .set_rxnfc = gem_set_rxnfc,
3688 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3690 struct macb *bp = netdev_priv(dev);
3692 if (!netif_running(dev))
3698 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3700 return bp->ptp_info->get_hwtst(dev, rq);
3704 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3707 static inline void macb_set_txcsum_feature(struct macb *bp,
3708 netdev_features_t features)
3712 if (!macb_is_gem(bp))
3715 val = gem_readl(bp, DMACFG);
3716 if (features & NETIF_F_HW_CSUM)
3717 val |= GEM_BIT(TXCOEN);
3719 val &= ~GEM_BIT(TXCOEN);
3721 gem_writel(bp, DMACFG, val);
3724 static inline void macb_set_rxcsum_feature(struct macb *bp,
3725 netdev_features_t features)
3727 struct net_device *netdev = bp->dev;
3730 if (!macb_is_gem(bp))
3733 val = gem_readl(bp, NCFGR);
3734 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3735 val |= GEM_BIT(RXCOEN);
3737 val &= ~GEM_BIT(RXCOEN);
3739 gem_writel(bp, NCFGR, val);
3742 static inline void macb_set_rxflow_feature(struct macb *bp,
3743 netdev_features_t features)
3745 if (!macb_is_gem(bp))
3748 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3751 static int macb_set_features(struct net_device *netdev,
3752 netdev_features_t features)
3754 struct macb *bp = netdev_priv(netdev);
3755 netdev_features_t changed = features ^ netdev->features;
3757 /* TX checksum offload */
3758 if (changed & NETIF_F_HW_CSUM)
3759 macb_set_txcsum_feature(bp, features);
3761 /* RX checksum offload */
3762 if (changed & NETIF_F_RXCSUM)
3763 macb_set_rxcsum_feature(bp, features);
3765 /* RX Flow Filters */
3766 if (changed & NETIF_F_NTUPLE)
3767 macb_set_rxflow_feature(bp, features);
3772 static void macb_restore_features(struct macb *bp)
3774 struct net_device *netdev = bp->dev;
3775 netdev_features_t features = netdev->features;
3776 struct ethtool_rx_fs_item *item;
3778 /* TX checksum offload */
3779 macb_set_txcsum_feature(bp, features);
3781 /* RX checksum offload */
3782 macb_set_rxcsum_feature(bp, features);
3784 /* RX Flow Filters */
3785 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3786 gem_prog_cmp_regs(bp, &item->fs);
3788 macb_set_rxflow_feature(bp, features);
3791 static const struct net_device_ops macb_netdev_ops = {
3792 .ndo_open = macb_open,
3793 .ndo_stop = macb_close,
3794 .ndo_start_xmit = macb_start_xmit,
3795 .ndo_set_rx_mode = macb_set_rx_mode,
3796 .ndo_get_stats = macb_get_stats,
3797 .ndo_eth_ioctl = macb_ioctl,
3798 .ndo_validate_addr = eth_validate_addr,
3799 .ndo_change_mtu = macb_change_mtu,
3800 .ndo_set_mac_address = macb_set_mac_addr,
3801 #ifdef CONFIG_NET_POLL_CONTROLLER
3802 .ndo_poll_controller = macb_poll_controller,
3804 .ndo_set_features = macb_set_features,
3805 .ndo_features_check = macb_features_check,
3808 /* Configure peripheral capabilities according to device tree
3809 * and integration options used
3811 static void macb_configure_caps(struct macb *bp,
3812 const struct macb_config *dt_conf)
3817 bp->caps = dt_conf->caps;
3819 if (hw_is_gem(bp->regs, bp->native_io)) {
3820 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3822 dcfg = gem_readl(bp, DCFG1);
3823 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3824 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3825 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3826 bp->caps |= MACB_CAPS_PCS;
3827 dcfg = gem_readl(bp, DCFG12);
3828 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3829 bp->caps |= MACB_CAPS_HIGH_SPEED;
3830 dcfg = gem_readl(bp, DCFG2);
3831 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3832 bp->caps |= MACB_CAPS_FIFO_MODE;
3833 #ifdef CONFIG_MACB_USE_HWSTAMP
3834 if (gem_has_ptp(bp)) {
3835 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3836 dev_err(&bp->pdev->dev,
3837 "GEM doesn't support hardware ptp.\n");
3839 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3840 bp->ptp_info = &gem_ptp_info;
3846 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3849 static void macb_probe_queues(void __iomem *mem,
3851 unsigned int *queue_mask,
3852 unsigned int *num_queues)
3857 /* is it macb or gem ?
3859 * We need to read directly from the hardware here because
3860 * we are early in the probe process and don't have the
3861 * MACB_CAPS_MACB_IS_GEM flag positioned
3863 if (!hw_is_gem(mem, native_io))
3866 /* bit 0 is never set but queue 0 always exists */
3867 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3868 *num_queues = hweight32(*queue_mask);
3871 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3872 struct clk *rx_clk, struct clk *tsu_clk)
3874 struct clk_bulk_data clks[] = {
3875 { .clk = tsu_clk, },
3882 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
3885 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3886 struct clk **hclk, struct clk **tx_clk,
3887 struct clk **rx_clk, struct clk **tsu_clk)
3889 struct macb_platform_data *pdata;
3892 pdata = dev_get_platdata(&pdev->dev);
3894 *pclk = pdata->pclk;
3895 *hclk = pdata->hclk;
3897 *pclk = devm_clk_get(&pdev->dev, "pclk");
3898 *hclk = devm_clk_get(&pdev->dev, "hclk");
3901 if (IS_ERR_OR_NULL(*pclk))
3902 return dev_err_probe(&pdev->dev,
3903 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
3904 "failed to get pclk\n");
3906 if (IS_ERR_OR_NULL(*hclk))
3907 return dev_err_probe(&pdev->dev,
3908 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
3909 "failed to get hclk\n");
3911 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3912 if (IS_ERR(*tx_clk))
3913 return PTR_ERR(*tx_clk);
3915 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3916 if (IS_ERR(*rx_clk))
3917 return PTR_ERR(*rx_clk);
3919 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3920 if (IS_ERR(*tsu_clk))
3921 return PTR_ERR(*tsu_clk);
3923 err = clk_prepare_enable(*pclk);
3925 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3929 err = clk_prepare_enable(*hclk);
3931 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3932 goto err_disable_pclk;
3935 err = clk_prepare_enable(*tx_clk);
3937 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3938 goto err_disable_hclk;
3941 err = clk_prepare_enable(*rx_clk);
3943 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3944 goto err_disable_txclk;
3947 err = clk_prepare_enable(*tsu_clk);
3949 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3950 goto err_disable_rxclk;
3956 clk_disable_unprepare(*rx_clk);
3959 clk_disable_unprepare(*tx_clk);
3962 clk_disable_unprepare(*hclk);
3965 clk_disable_unprepare(*pclk);
3970 static int macb_init(struct platform_device *pdev)
3972 struct net_device *dev = platform_get_drvdata(pdev);
3973 unsigned int hw_q, q;
3974 struct macb *bp = netdev_priv(dev);
3975 struct macb_queue *queue;
3979 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3980 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3982 /* set the queue register mapping once for all: queue0 has a special
3983 * register mapping but we don't want to test the queue index then
3984 * compute the corresponding register offset at run time.
3986 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3987 if (!(bp->queue_mask & (1 << hw_q)))
3990 queue = &bp->queues[q];
3992 spin_lock_init(&queue->tx_ptr_lock);
3993 netif_napi_add(dev, &queue->napi_rx, macb_rx_poll);
3994 netif_napi_add(dev, &queue->napi_tx, macb_tx_poll);
3996 queue->ISR = GEM_ISR(hw_q - 1);
3997 queue->IER = GEM_IER(hw_q - 1);
3998 queue->IDR = GEM_IDR(hw_q - 1);
3999 queue->IMR = GEM_IMR(hw_q - 1);
4000 queue->TBQP = GEM_TBQP(hw_q - 1);
4001 queue->RBQP = GEM_RBQP(hw_q - 1);
4002 queue->RBQS = GEM_RBQS(hw_q - 1);
4003 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4004 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4005 queue->TBQPH = GEM_TBQPH(hw_q - 1);
4006 queue->RBQPH = GEM_RBQPH(hw_q - 1);
4010 /* queue0 uses legacy registers */
4011 queue->ISR = MACB_ISR;
4012 queue->IER = MACB_IER;
4013 queue->IDR = MACB_IDR;
4014 queue->IMR = MACB_IMR;
4015 queue->TBQP = MACB_TBQP;
4016 queue->RBQP = MACB_RBQP;
4017 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4018 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4019 queue->TBQPH = MACB_TBQPH;
4020 queue->RBQPH = MACB_RBQPH;
4025 /* get irq: here we use the linux queue index, not the hardware
4026 * queue index. the queue irq definitions in the device tree
4027 * must remove the optional gaps that could exist in the
4028 * hardware queue mask.
4030 queue->irq = platform_get_irq(pdev, q);
4031 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
4032 IRQF_SHARED, dev->name, queue);
4035 "Unable to request IRQ %d (error %d)\n",
4040 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
4044 dev->netdev_ops = &macb_netdev_ops;
4046 /* setup appropriated routines according to adapter type */
4047 if (macb_is_gem(bp)) {
4048 bp->max_tx_length = GEM_MAX_TX_LEN;
4049 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
4050 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
4051 bp->macbgem_ops.mog_init_rings = gem_init_rings;
4052 bp->macbgem_ops.mog_rx = gem_rx;
4053 dev->ethtool_ops = &gem_ethtool_ops;
4055 bp->max_tx_length = MACB_MAX_TX_LEN;
4056 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
4057 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
4058 bp->macbgem_ops.mog_init_rings = macb_init_rings;
4059 bp->macbgem_ops.mog_rx = macb_rx;
4060 dev->ethtool_ops = &macb_ethtool_ops;
4063 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4066 dev->hw_features = NETIF_F_SG;
4068 /* Check LSO capability */
4069 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
4070 dev->hw_features |= MACB_NETIF_LSO;
4072 /* Checksum offload is only available on gem with packet buffer */
4073 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
4074 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
4075 if (bp->caps & MACB_CAPS_SG_DISABLED)
4076 dev->hw_features &= ~NETIF_F_SG;
4077 dev->features = dev->hw_features;
4079 /* Check RX Flow Filters support.
4080 * Max Rx flows set by availability of screeners & compare regs:
4081 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
4083 reg = gem_readl(bp, DCFG8);
4084 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
4085 GEM_BFEXT(T2SCR, reg));
4086 INIT_LIST_HEAD(&bp->rx_fs_list.list);
4087 if (bp->max_tuples > 0) {
4088 /* also needs one ethtype match to check IPv4 */
4089 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
4090 /* program this reg now */
4092 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
4093 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
4094 /* Filtering is supported in hw but don't enable it in kernel now */
4095 dev->hw_features |= NETIF_F_NTUPLE;
4096 /* init Rx flow definitions */
4097 bp->rx_fs_list.count = 0;
4098 spin_lock_init(&bp->rx_fs_lock);
4103 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
4105 if (phy_interface_mode_is_rgmii(bp->phy_interface))
4106 val = bp->usrio->rgmii;
4107 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
4108 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4109 val = bp->usrio->rmii;
4110 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4111 val = bp->usrio->mii;
4113 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
4114 val |= bp->usrio->refclk;
4116 macb_or_gem_writel(bp, USRIO, val);
4119 /* Set MII management clock divider */
4120 val = macb_mdc_clk_div(bp);
4121 val |= macb_dbw(bp);
4122 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4123 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4124 macb_writel(bp, NCFGR, val);
4129 static const struct macb_usrio_config macb_default_usrio = {
4130 .mii = MACB_BIT(MII),
4131 .rmii = MACB_BIT(RMII),
4132 .rgmii = GEM_BIT(RGMII),
4133 .refclk = MACB_BIT(CLKEN),
4136 #if defined(CONFIG_OF)
4137 /* 1518 rounded up */
4138 #define AT91ETHER_MAX_RBUFF_SZ 0x600
4139 /* max number of receive buffers */
4140 #define AT91ETHER_MAX_RX_DESCR 9
4142 static struct sifive_fu540_macb_mgmt *mgmt;
4144 static int at91ether_alloc_coherent(struct macb *lp)
4146 struct macb_queue *q = &lp->queues[0];
4148 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4149 (AT91ETHER_MAX_RX_DESCR *
4150 macb_dma_desc_get_size(lp)),
4151 &q->rx_ring_dma, GFP_KERNEL);
4155 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4156 AT91ETHER_MAX_RX_DESCR *
4157 AT91ETHER_MAX_RBUFF_SZ,
4158 &q->rx_buffers_dma, GFP_KERNEL);
4159 if (!q->rx_buffers) {
4160 dma_free_coherent(&lp->pdev->dev,
4161 AT91ETHER_MAX_RX_DESCR *
4162 macb_dma_desc_get_size(lp),
4163 q->rx_ring, q->rx_ring_dma);
4171 static void at91ether_free_coherent(struct macb *lp)
4173 struct macb_queue *q = &lp->queues[0];
4176 dma_free_coherent(&lp->pdev->dev,
4177 AT91ETHER_MAX_RX_DESCR *
4178 macb_dma_desc_get_size(lp),
4179 q->rx_ring, q->rx_ring_dma);
4183 if (q->rx_buffers) {
4184 dma_free_coherent(&lp->pdev->dev,
4185 AT91ETHER_MAX_RX_DESCR *
4186 AT91ETHER_MAX_RBUFF_SZ,
4187 q->rx_buffers, q->rx_buffers_dma);
4188 q->rx_buffers = NULL;
4192 /* Initialize and start the Receiver and Transmit subsystems */
4193 static int at91ether_start(struct macb *lp)
4195 struct macb_queue *q = &lp->queues[0];
4196 struct macb_dma_desc *desc;
4201 ret = at91ether_alloc_coherent(lp);
4205 addr = q->rx_buffers_dma;
4206 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4207 desc = macb_rx_desc(q, i);
4208 macb_set_addr(lp, desc, addr);
4210 addr += AT91ETHER_MAX_RBUFF_SZ;
4213 /* Set the Wrap bit on the last descriptor */
4214 desc->addr |= MACB_BIT(RX_WRAP);
4216 /* Reset buffer index */
4219 /* Program address of descriptor list in Rx Buffer Queue register */
4220 macb_writel(lp, RBQP, q->rx_ring_dma);
4222 /* Enable Receive and Transmit */
4223 ctl = macb_readl(lp, NCR);
4224 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4226 /* Enable MAC interrupts */
4227 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4229 MACB_BIT(ISR_TUND) |
4232 MACB_BIT(ISR_ROVR) |
4238 static void at91ether_stop(struct macb *lp)
4242 /* Disable MAC interrupts */
4243 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4245 MACB_BIT(ISR_TUND) |
4248 MACB_BIT(ISR_ROVR) |
4251 /* Disable Receiver and Transmitter */
4252 ctl = macb_readl(lp, NCR);
4253 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4255 /* Free resources. */
4256 at91ether_free_coherent(lp);
4259 /* Open the ethernet interface */
4260 static int at91ether_open(struct net_device *dev)
4262 struct macb *lp = netdev_priv(dev);
4266 ret = pm_runtime_resume_and_get(&lp->pdev->dev);
4270 /* Clear internal statistics */
4271 ctl = macb_readl(lp, NCR);
4272 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4274 macb_set_hwaddr(lp);
4276 ret = at91ether_start(lp);
4280 ret = macb_phylink_connect(lp);
4284 netif_start_queue(dev);
4291 pm_runtime_put_sync(&lp->pdev->dev);
4295 /* Close the interface */
4296 static int at91ether_close(struct net_device *dev)
4298 struct macb *lp = netdev_priv(dev);
4300 netif_stop_queue(dev);
4302 phylink_stop(lp->phylink);
4303 phylink_disconnect_phy(lp->phylink);
4307 return pm_runtime_put(&lp->pdev->dev);
4310 /* Transmit packet */
4311 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4312 struct net_device *dev)
4314 struct macb *lp = netdev_priv(dev);
4316 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4319 netif_stop_queue(dev);
4321 /* Store packet information (to free when Tx completed) */
4322 lp->rm9200_txq[desc].skb = skb;
4323 lp->rm9200_txq[desc].size = skb->len;
4324 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4325 skb->len, DMA_TO_DEVICE);
4326 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4327 dev_kfree_skb_any(skb);
4328 dev->stats.tx_dropped++;
4329 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4330 return NETDEV_TX_OK;
4333 /* Set address of the data in the Transmit Address register */
4334 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4335 /* Set length of the packet in the Transmit Control register */
4336 macb_writel(lp, TCR, skb->len);
4339 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4340 return NETDEV_TX_BUSY;
4343 return NETDEV_TX_OK;
4346 /* Extract received frame from buffer descriptors and sent to upper layers.
4347 * (Called from interrupt context)
4349 static void at91ether_rx(struct net_device *dev)
4351 struct macb *lp = netdev_priv(dev);
4352 struct macb_queue *q = &lp->queues[0];
4353 struct macb_dma_desc *desc;
4354 unsigned char *p_recv;
4355 struct sk_buff *skb;
4356 unsigned int pktlen;
4358 desc = macb_rx_desc(q, q->rx_tail);
4359 while (desc->addr & MACB_BIT(RX_USED)) {
4360 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4361 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4362 skb = netdev_alloc_skb(dev, pktlen + 2);
4364 skb_reserve(skb, 2);
4365 skb_put_data(skb, p_recv, pktlen);
4367 skb->protocol = eth_type_trans(skb, dev);
4368 dev->stats.rx_packets++;
4369 dev->stats.rx_bytes += pktlen;
4372 dev->stats.rx_dropped++;
4375 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4376 dev->stats.multicast++;
4378 /* reset ownership bit */
4379 desc->addr &= ~MACB_BIT(RX_USED);
4381 /* wrap after last buffer */
4382 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4387 desc = macb_rx_desc(q, q->rx_tail);
4391 /* MAC interrupt handler */
4392 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4394 struct net_device *dev = dev_id;
4395 struct macb *lp = netdev_priv(dev);
4399 /* MAC Interrupt Status register indicates what interrupts are pending.
4400 * It is automatically cleared once read.
4402 intstatus = macb_readl(lp, ISR);
4404 /* Receive complete */
4405 if (intstatus & MACB_BIT(RCOMP))
4408 /* Transmit complete */
4409 if (intstatus & MACB_BIT(TCOMP)) {
4410 /* The TCOM bit is set even if the transmission failed */
4411 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4412 dev->stats.tx_errors++;
4415 if (lp->rm9200_txq[desc].skb) {
4416 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4417 lp->rm9200_txq[desc].skb = NULL;
4418 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4419 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4420 dev->stats.tx_packets++;
4421 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4423 netif_wake_queue(dev);
4426 /* Work-around for EMAC Errata section 41.3.1 */
4427 if (intstatus & MACB_BIT(RXUBR)) {
4428 ctl = macb_readl(lp, NCR);
4429 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4431 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4434 if (intstatus & MACB_BIT(ISR_ROVR))
4435 netdev_err(dev, "ROVR error\n");
4440 #ifdef CONFIG_NET_POLL_CONTROLLER
4441 static void at91ether_poll_controller(struct net_device *dev)
4443 unsigned long flags;
4445 local_irq_save(flags);
4446 at91ether_interrupt(dev->irq, dev);
4447 local_irq_restore(flags);
4451 static const struct net_device_ops at91ether_netdev_ops = {
4452 .ndo_open = at91ether_open,
4453 .ndo_stop = at91ether_close,
4454 .ndo_start_xmit = at91ether_start_xmit,
4455 .ndo_get_stats = macb_get_stats,
4456 .ndo_set_rx_mode = macb_set_rx_mode,
4457 .ndo_set_mac_address = eth_mac_addr,
4458 .ndo_eth_ioctl = macb_ioctl,
4459 .ndo_validate_addr = eth_validate_addr,
4460 #ifdef CONFIG_NET_POLL_CONTROLLER
4461 .ndo_poll_controller = at91ether_poll_controller,
4465 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4466 struct clk **hclk, struct clk **tx_clk,
4467 struct clk **rx_clk, struct clk **tsu_clk)
4476 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4478 return PTR_ERR(*pclk);
4480 err = clk_prepare_enable(*pclk);
4482 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4489 static int at91ether_init(struct platform_device *pdev)
4491 struct net_device *dev = platform_get_drvdata(pdev);
4492 struct macb *bp = netdev_priv(dev);
4495 bp->queues[0].bp = bp;
4497 dev->netdev_ops = &at91ether_netdev_ops;
4498 dev->ethtool_ops = &macb_ethtool_ops;
4500 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4505 macb_writel(bp, NCR, 0);
4507 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4512 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4513 unsigned long parent_rate)
4518 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4519 unsigned long *parent_rate)
4521 if (WARN_ON(rate < 2500000))
4523 else if (rate == 2500000)
4525 else if (WARN_ON(rate < 13750000))
4527 else if (WARN_ON(rate < 25000000))
4529 else if (rate == 25000000)
4531 else if (WARN_ON(rate < 75000000))
4533 else if (WARN_ON(rate < 125000000))
4535 else if (rate == 125000000)
4538 WARN_ON(rate > 125000000);
4543 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4544 unsigned long parent_rate)
4546 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4547 if (rate != 125000000)
4548 iowrite32(1, mgmt->reg);
4550 iowrite32(0, mgmt->reg);
4556 static const struct clk_ops fu540_c000_ops = {
4557 .recalc_rate = fu540_macb_tx_recalc_rate,
4558 .round_rate = fu540_macb_tx_round_rate,
4559 .set_rate = fu540_macb_tx_set_rate,
4562 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4563 struct clk **hclk, struct clk **tx_clk,
4564 struct clk **rx_clk, struct clk **tsu_clk)
4566 struct clk_init_data init;
4569 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4573 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4576 goto err_disable_clks;
4579 init.name = "sifive-gemgxl-mgmt";
4580 init.ops = &fu540_c000_ops;
4582 init.num_parents = 0;
4585 mgmt->hw.init = &init;
4587 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4588 if (IS_ERR(*tx_clk)) {
4589 err = PTR_ERR(*tx_clk);
4590 goto err_disable_clks;
4593 err = clk_prepare_enable(*tx_clk);
4595 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4597 goto err_disable_clks;
4599 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4605 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4610 static int fu540_c000_init(struct platform_device *pdev)
4612 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4613 if (IS_ERR(mgmt->reg))
4614 return PTR_ERR(mgmt->reg);
4616 return macb_init(pdev);
4619 static int init_reset_optional(struct platform_device *pdev)
4621 struct net_device *dev = platform_get_drvdata(pdev);
4622 struct macb *bp = netdev_priv(dev);
4625 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4626 /* Ensure PHY device used in SGMII mode is ready */
4627 bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);
4629 if (IS_ERR(bp->sgmii_phy))
4630 return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy),
4631 "failed to get SGMII PHY\n");
4633 ret = phy_init(bp->sgmii_phy);
4635 return dev_err_probe(&pdev->dev, ret,
4636 "failed to init SGMII PHY\n");
4639 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG);
4643 ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
4644 pm_info, ARRAY_SIZE(pm_info));
4646 dev_err(&pdev->dev, "Failed to read power management information\n");
4647 goto err_out_phy_exit;
4649 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0);
4651 goto err_out_phy_exit;
4653 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1);
4655 goto err_out_phy_exit;
4658 /* Fully reset controller at hardware level if mapped in device tree */
4659 ret = device_reset_optional(&pdev->dev);
4661 phy_exit(bp->sgmii_phy);
4662 return dev_err_probe(&pdev->dev, ret, "failed to reset controller");
4665 ret = macb_init(pdev);
4669 phy_exit(bp->sgmii_phy);
4674 static const struct macb_usrio_config sama7g5_usrio = {
4682 static const struct macb_config fu540_c000_config = {
4683 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4684 MACB_CAPS_GEM_HAS_PTP,
4685 .dma_burst_length = 16,
4686 .clk_init = fu540_c000_clk_init,
4687 .init = fu540_c000_init,
4688 .jumbo_max_len = 10240,
4689 .usrio = &macb_default_usrio,
4692 static const struct macb_config at91sam9260_config = {
4693 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4694 .clk_init = macb_clk_init,
4696 .usrio = &macb_default_usrio,
4699 static const struct macb_config sama5d3macb_config = {
4700 .caps = MACB_CAPS_SG_DISABLED |
4701 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4702 .clk_init = macb_clk_init,
4704 .usrio = &macb_default_usrio,
4707 static const struct macb_config pc302gem_config = {
4708 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4709 .dma_burst_length = 16,
4710 .clk_init = macb_clk_init,
4712 .usrio = &macb_default_usrio,
4715 static const struct macb_config sama5d2_config = {
4716 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4717 .dma_burst_length = 16,
4718 .clk_init = macb_clk_init,
4720 .usrio = &macb_default_usrio,
4723 static const struct macb_config sama5d29_config = {
4724 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
4725 .dma_burst_length = 16,
4726 .clk_init = macb_clk_init,
4728 .usrio = &macb_default_usrio,
4731 static const struct macb_config sama5d3_config = {
4732 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4733 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4734 .dma_burst_length = 16,
4735 .clk_init = macb_clk_init,
4737 .jumbo_max_len = 10240,
4738 .usrio = &macb_default_usrio,
4741 static const struct macb_config sama5d4_config = {
4742 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4743 .dma_burst_length = 4,
4744 .clk_init = macb_clk_init,
4746 .usrio = &macb_default_usrio,
4749 static const struct macb_config emac_config = {
4750 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4751 .clk_init = at91ether_clk_init,
4752 .init = at91ether_init,
4753 .usrio = &macb_default_usrio,
4756 static const struct macb_config np4_config = {
4757 .caps = MACB_CAPS_USRIO_DISABLED,
4758 .clk_init = macb_clk_init,
4760 .usrio = &macb_default_usrio,
4763 static const struct macb_config zynqmp_config = {
4764 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4766 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4767 .dma_burst_length = 16,
4768 .clk_init = macb_clk_init,
4769 .init = init_reset_optional,
4770 .jumbo_max_len = 10240,
4771 .usrio = &macb_default_usrio,
4774 static const struct macb_config zynq_config = {
4775 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4776 MACB_CAPS_NEEDS_RSTONUBR,
4777 .dma_burst_length = 16,
4778 .clk_init = macb_clk_init,
4780 .usrio = &macb_default_usrio,
4783 static const struct macb_config mpfs_config = {
4784 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4786 MACB_CAPS_GEM_HAS_PTP,
4787 .dma_burst_length = 16,
4788 .clk_init = macb_clk_init,
4789 .init = init_reset_optional,
4790 .usrio = &macb_default_usrio,
4791 .jumbo_max_len = 10240,
4794 static const struct macb_config sama7g5_gem_config = {
4795 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
4796 MACB_CAPS_MIIONRGMII,
4797 .dma_burst_length = 16,
4798 .clk_init = macb_clk_init,
4800 .usrio = &sama7g5_usrio,
4803 static const struct macb_config sama7g5_emac_config = {
4804 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
4805 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII,
4806 .dma_burst_length = 16,
4807 .clk_init = macb_clk_init,
4809 .usrio = &sama7g5_usrio,
4812 static const struct macb_config versal_config = {
4813 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4814 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK,
4815 .dma_burst_length = 16,
4816 .clk_init = macb_clk_init,
4817 .init = init_reset_optional,
4818 .jumbo_max_len = 10240,
4819 .usrio = &macb_default_usrio,
4822 static const struct of_device_id macb_dt_ids[] = {
4823 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4824 { .compatible = "cdns,macb" },
4825 { .compatible = "cdns,np4-macb", .data = &np4_config },
4826 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4827 { .compatible = "cdns,gem", .data = &pc302gem_config },
4828 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4829 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4830 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4831 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4832 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4833 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4834 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4835 { .compatible = "cdns,emac", .data = &emac_config },
4836 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
4837 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
4838 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4839 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
4840 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4841 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4842 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
4843 { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
4844 { .compatible = "xlnx,versal-gem", .data = &versal_config},
4847 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4848 #endif /* CONFIG_OF */
4850 static const struct macb_config default_gem_config = {
4851 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4853 MACB_CAPS_GEM_HAS_PTP,
4854 .dma_burst_length = 16,
4855 .clk_init = macb_clk_init,
4857 .usrio = &macb_default_usrio,
4858 .jumbo_max_len = 10240,
4861 static int macb_probe(struct platform_device *pdev)
4863 const struct macb_config *macb_config = &default_gem_config;
4864 int (*clk_init)(struct platform_device *, struct clk **,
4865 struct clk **, struct clk **, struct clk **,
4866 struct clk **) = macb_config->clk_init;
4867 int (*init)(struct platform_device *) = macb_config->init;
4868 struct device_node *np = pdev->dev.of_node;
4869 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4870 struct clk *tsu_clk = NULL;
4871 unsigned int queue_mask, num_queues;
4873 phy_interface_t interface;
4874 struct net_device *dev;
4875 struct resource *regs;
4880 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
4882 return PTR_ERR(mem);
4885 const struct of_device_id *match;
4887 match = of_match_node(macb_dt_ids, np);
4888 if (match && match->data) {
4889 macb_config = match->data;
4890 clk_init = macb_config->clk_init;
4891 init = macb_config->init;
4895 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4899 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4900 pm_runtime_use_autosuspend(&pdev->dev);
4901 pm_runtime_get_noresume(&pdev->dev);
4902 pm_runtime_set_active(&pdev->dev);
4903 pm_runtime_enable(&pdev->dev);
4904 native_io = hw_is_native_io(mem);
4906 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4907 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4910 goto err_disable_clocks;
4913 dev->base_addr = regs->start;
4915 SET_NETDEV_DEV(dev, &pdev->dev);
4917 bp = netdev_priv(dev);
4921 bp->native_io = native_io;
4923 bp->macb_reg_readl = hw_readl_native;
4924 bp->macb_reg_writel = hw_writel_native;
4926 bp->macb_reg_readl = hw_readl;
4927 bp->macb_reg_writel = hw_writel;
4929 bp->num_queues = num_queues;
4930 bp->queue_mask = queue_mask;
4932 bp->dma_burst_length = macb_config->dma_burst_length;
4935 bp->tx_clk = tx_clk;
4936 bp->rx_clk = rx_clk;
4937 bp->tsu_clk = tsu_clk;
4939 bp->jumbo_max_len = macb_config->jumbo_max_len;
4942 if (of_get_property(np, "magic-packet", NULL))
4943 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4944 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4946 bp->usrio = macb_config->usrio;
4948 spin_lock_init(&bp->lock);
4950 /* setup capabilities */
4951 macb_configure_caps(bp, macb_config);
4953 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4954 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4955 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
4956 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4959 platform_set_drvdata(pdev, dev);
4961 dev->irq = platform_get_irq(pdev, 0);
4964 goto err_out_free_netdev;
4967 /* MTU range: 68 - 1500 or 10240 */
4968 dev->min_mtu = GEM_MTU_MIN_SIZE;
4969 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
4970 dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN;
4972 dev->max_mtu = ETH_DATA_LEN;
4974 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4975 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4977 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4978 macb_dma_desc_get_size(bp);
4980 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4982 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4983 macb_dma_desc_get_size(bp);
4986 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4987 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4988 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4990 err = of_get_ethdev_address(np, bp->dev);
4991 if (err == -EPROBE_DEFER)
4992 goto err_out_free_netdev;
4994 macb_get_hwaddr(bp);
4996 err = of_get_phy_mode(np, &interface);
4998 /* not found in DT, MII by default */
4999 bp->phy_interface = PHY_INTERFACE_MODE_MII;
5001 bp->phy_interface = interface;
5003 /* IP specific init */
5006 goto err_out_free_netdev;
5008 err = macb_mii_init(bp);
5010 goto err_out_phy_exit;
5012 netif_carrier_off(dev);
5014 err = register_netdev(dev);
5016 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5017 goto err_out_unregister_mdio;
5020 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
5022 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
5023 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
5024 dev->base_addr, dev->irq, dev->dev_addr);
5026 pm_runtime_mark_last_busy(&bp->pdev->dev);
5027 pm_runtime_put_autosuspend(&bp->pdev->dev);
5031 err_out_unregister_mdio:
5032 mdiobus_unregister(bp->mii_bus);
5033 mdiobus_free(bp->mii_bus);
5036 phy_exit(bp->sgmii_phy);
5038 err_out_free_netdev:
5042 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
5043 pm_runtime_disable(&pdev->dev);
5044 pm_runtime_set_suspended(&pdev->dev);
5045 pm_runtime_dont_use_autosuspend(&pdev->dev);
5050 static int macb_remove(struct platform_device *pdev)
5052 struct net_device *dev;
5055 dev = platform_get_drvdata(pdev);
5058 bp = netdev_priv(dev);
5059 phy_exit(bp->sgmii_phy);
5060 mdiobus_unregister(bp->mii_bus);
5061 mdiobus_free(bp->mii_bus);
5063 unregister_netdev(dev);
5064 tasklet_kill(&bp->hresp_err_tasklet);
5065 pm_runtime_disable(&pdev->dev);
5066 pm_runtime_dont_use_autosuspend(&pdev->dev);
5067 if (!pm_runtime_suspended(&pdev->dev)) {
5068 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
5069 bp->rx_clk, bp->tsu_clk);
5070 pm_runtime_set_suspended(&pdev->dev);
5072 phylink_destroy(bp->phylink);
5079 static int __maybe_unused macb_suspend(struct device *dev)
5081 struct net_device *netdev = dev_get_drvdata(dev);
5082 struct macb *bp = netdev_priv(netdev);
5083 struct macb_queue *queue;
5084 unsigned long flags;
5088 if (!netif_running(netdev))
5091 if (bp->wol & MACB_WOL_ENABLED) {
5092 spin_lock_irqsave(&bp->lock, flags);
5093 /* Flush all status bits */
5094 macb_writel(bp, TSR, -1);
5095 macb_writel(bp, RSR, -1);
5096 for (q = 0, queue = bp->queues; q < bp->num_queues;
5098 /* Disable all interrupts */
5099 queue_writel(queue, IDR, -1);
5100 queue_readl(queue, ISR);
5101 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5102 queue_writel(queue, ISR, -1);
5104 /* Change interrupt handler and
5105 * Enable WoL IRQ on queue 0
5107 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5108 if (macb_is_gem(bp)) {
5109 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
5110 IRQF_SHARED, netdev->name, bp->queues);
5113 "Unable to request IRQ %d (error %d)\n",
5114 bp->queues[0].irq, err);
5115 spin_unlock_irqrestore(&bp->lock, flags);
5118 queue_writel(bp->queues, IER, GEM_BIT(WOL));
5119 gem_writel(bp, WOL, MACB_BIT(MAG));
5121 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
5122 IRQF_SHARED, netdev->name, bp->queues);
5125 "Unable to request IRQ %d (error %d)\n",
5126 bp->queues[0].irq, err);
5127 spin_unlock_irqrestore(&bp->lock, flags);
5130 queue_writel(bp->queues, IER, MACB_BIT(WOL));
5131 macb_writel(bp, WOL, MACB_BIT(MAG));
5133 spin_unlock_irqrestore(&bp->lock, flags);
5135 enable_irq_wake(bp->queues[0].irq);
5138 netif_device_detach(netdev);
5139 for (q = 0, queue = bp->queues; q < bp->num_queues;
5141 napi_disable(&queue->napi_rx);
5142 napi_disable(&queue->napi_tx);
5145 if (!(bp->wol & MACB_WOL_ENABLED)) {
5147 phylink_stop(bp->phylink);
5148 phy_exit(bp->sgmii_phy);
5150 spin_lock_irqsave(&bp->lock, flags);
5152 spin_unlock_irqrestore(&bp->lock, flags);
5155 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5156 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
5158 if (netdev->hw_features & NETIF_F_NTUPLE)
5159 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5162 bp->ptp_info->ptp_remove(netdev);
5163 if (!device_may_wakeup(dev))
5164 pm_runtime_force_suspend(dev);
5169 static int __maybe_unused macb_resume(struct device *dev)
5171 struct net_device *netdev = dev_get_drvdata(dev);
5172 struct macb *bp = netdev_priv(netdev);
5173 struct macb_queue *queue;
5174 unsigned long flags;
5178 if (!netif_running(netdev))
5181 if (!device_may_wakeup(dev))
5182 pm_runtime_force_resume(dev);
5184 if (bp->wol & MACB_WOL_ENABLED) {
5185 spin_lock_irqsave(&bp->lock, flags);
5187 if (macb_is_gem(bp)) {
5188 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5189 gem_writel(bp, WOL, 0);
5191 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5192 macb_writel(bp, WOL, 0);
5194 /* Clear ISR on queue 0 */
5195 queue_readl(bp->queues, ISR);
5196 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5197 queue_writel(bp->queues, ISR, -1);
5198 /* Replace interrupt handler on queue 0 */
5199 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5200 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
5201 IRQF_SHARED, netdev->name, bp->queues);
5204 "Unable to request IRQ %d (error %d)\n",
5205 bp->queues[0].irq, err);
5206 spin_unlock_irqrestore(&bp->lock, flags);
5209 spin_unlock_irqrestore(&bp->lock, flags);
5211 disable_irq_wake(bp->queues[0].irq);
5213 /* Now make sure we disable phy before moving
5214 * to common restore path
5217 phylink_stop(bp->phylink);
5221 for (q = 0, queue = bp->queues; q < bp->num_queues;
5223 napi_enable(&queue->napi_rx);
5224 napi_enable(&queue->napi_tx);
5227 if (netdev->hw_features & NETIF_F_NTUPLE)
5228 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5230 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5231 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5233 macb_writel(bp, NCR, MACB_BIT(MPE));
5235 macb_set_rx_mode(netdev);
5236 macb_restore_features(bp);
5238 if (!device_may_wakeup(&bp->dev->dev))
5239 phy_init(bp->sgmii_phy);
5241 phylink_start(bp->phylink);
5244 netif_device_attach(netdev);
5246 bp->ptp_info->ptp_init(netdev);
5251 static int __maybe_unused macb_runtime_suspend(struct device *dev)
5253 struct net_device *netdev = dev_get_drvdata(dev);
5254 struct macb *bp = netdev_priv(netdev);
5256 if (!(device_may_wakeup(dev)))
5257 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5258 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK))
5259 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5264 static int __maybe_unused macb_runtime_resume(struct device *dev)
5266 struct net_device *netdev = dev_get_drvdata(dev);
5267 struct macb *bp = netdev_priv(netdev);
5269 if (!(device_may_wakeup(dev))) {
5270 clk_prepare_enable(bp->pclk);
5271 clk_prepare_enable(bp->hclk);
5272 clk_prepare_enable(bp->tx_clk);
5273 clk_prepare_enable(bp->rx_clk);
5274 clk_prepare_enable(bp->tsu_clk);
5275 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) {
5276 clk_prepare_enable(bp->tsu_clk);
5282 static const struct dev_pm_ops macb_pm_ops = {
5283 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5284 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5287 static struct platform_driver macb_driver = {
5288 .probe = macb_probe,
5289 .remove = macb_remove,
5292 .of_match_table = of_match_ptr(macb_dt_ids),
5297 module_platform_driver(macb_driver);
5299 MODULE_LICENSE("GPL");
5300 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5301 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5302 MODULE_ALIAS("platform:macb");