1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
29 #include <linux/of_device.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
34 #include <linux/udp.h>
35 #include <linux/tcp.h>
36 #include <linux/iopoll.h>
37 #include <linux/pm_runtime.h>
40 /* This structure is only used for MACB on SiFive FU540 devices */
41 struct sifive_fu540_macb_mgmt {
47 #define MACB_RX_BUFFER_SIZE 128
48 #define RX_BUFFER_MULTIPLE 64 /* bytes */
50 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_RX_RING_SIZE 64
52 #define MAX_RX_RING_SIZE 8192
53 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
56 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
57 #define MIN_TX_RING_SIZE 64
58 #define MAX_TX_RING_SIZE 4096
59 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
62 /* level of occupied TX descriptors under which we wake up TX process */
63 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
65 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
66 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
69 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
72 /* Max length of transmit frame must be a multiple of 8 bytes */
73 #define MACB_TX_LEN_ALIGN 8
74 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
75 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
76 * false amba_error in TX path from the DMA assuming there is not enough
77 * space in the SRAM (16KB) even when there is.
79 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
81 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
82 #define MACB_NETIF_LSO NETIF_F_TSO
84 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
85 #define MACB_WOL_ENABLED (0x1 << 1)
87 #define HS_SPEED_10000M 4
88 #define MACB_SERDES_RATE_10G 1
90 /* Graceful stop timeouts in us. We should allow up to
91 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
93 #define MACB_HALT_TIMEOUT 1230
95 #define MACB_PM_TIMEOUT 100 /* ms */
97 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
99 /* DMA buffer descriptor might be different size
100 * depends on hardware configuration:
102 * 1. dma address width 32 bits:
103 * word 1: 32 bit address of Data Buffer
106 * 2. dma address width 64 bits:
107 * word 1: 32 bit address of Data Buffer
109 * word 3: upper 32 bit address of Data Buffer
112 * 3. dma address width 32 bits with hardware timestamping:
113 * word 1: 32 bit address of Data Buffer
115 * word 3: timestamp word 1
116 * word 4: timestamp word 2
118 * 4. dma address width 64 bits with hardware timestamping:
119 * word 1: 32 bit address of Data Buffer
121 * word 3: upper 32 bit address of Data Buffer
123 * word 5: timestamp word 1
124 * word 6: timestamp word 2
126 static unsigned int macb_dma_desc_get_size(struct macb *bp)
129 unsigned int desc_size;
131 switch (bp->hw_dma_cap) {
133 desc_size = sizeof(struct macb_dma_desc)
134 + sizeof(struct macb_dma_desc_64);
137 desc_size = sizeof(struct macb_dma_desc)
138 + sizeof(struct macb_dma_desc_ptp);
140 case HW_DMA_CAP_64B_PTP:
141 desc_size = sizeof(struct macb_dma_desc)
142 + sizeof(struct macb_dma_desc_64)
143 + sizeof(struct macb_dma_desc_ptp);
146 desc_size = sizeof(struct macb_dma_desc);
150 return sizeof(struct macb_dma_desc);
153 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
156 switch (bp->hw_dma_cap) {
161 case HW_DMA_CAP_64B_PTP:
171 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
172 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
174 return (struct macb_dma_desc_64 *)((void *)desc
175 + sizeof(struct macb_dma_desc));
179 /* Ring buffer accessors */
180 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
182 return index & (bp->tx_ring_size - 1);
185 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
188 index = macb_tx_ring_wrap(queue->bp, index);
189 index = macb_adj_dma_desc_idx(queue->bp, index);
190 return &queue->tx_ring[index];
193 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
196 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
199 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
203 offset = macb_tx_ring_wrap(queue->bp, index) *
204 macb_dma_desc_get_size(queue->bp);
206 return queue->tx_ring_dma + offset;
209 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
211 return index & (bp->rx_ring_size - 1);
214 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
216 index = macb_rx_ring_wrap(queue->bp, index);
217 index = macb_adj_dma_desc_idx(queue->bp, index);
218 return &queue->rx_ring[index];
221 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
223 return queue->rx_buffers + queue->bp->rx_buffer_size *
224 macb_rx_ring_wrap(queue->bp, index);
228 static u32 hw_readl_native(struct macb *bp, int offset)
230 return __raw_readl(bp->regs + offset);
233 static void hw_writel_native(struct macb *bp, int offset, u32 value)
235 __raw_writel(value, bp->regs + offset);
238 static u32 hw_readl(struct macb *bp, int offset)
240 return readl_relaxed(bp->regs + offset);
243 static void hw_writel(struct macb *bp, int offset, u32 value)
245 writel_relaxed(value, bp->regs + offset);
248 /* Find the CPU endianness by using the loopback bit of NCR register. When the
249 * CPU is in big endian we need to program swapped mode for management
252 static bool hw_is_native_io(void __iomem *addr)
254 u32 value = MACB_BIT(LLB);
256 __raw_writel(value, addr + MACB_NCR);
257 value = __raw_readl(addr + MACB_NCR);
259 /* Write 0 back to disable everything */
260 __raw_writel(0, addr + MACB_NCR);
262 return value == MACB_BIT(LLB);
265 static bool hw_is_gem(void __iomem *addr, bool native_io)
270 id = __raw_readl(addr + MACB_MID);
272 id = readl_relaxed(addr + MACB_MID);
274 return MACB_BFEXT(IDNUM, id) >= 0x2;
277 static void macb_set_hwaddr(struct macb *bp)
282 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
283 macb_or_gem_writel(bp, SA1B, bottom);
284 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
285 macb_or_gem_writel(bp, SA1T, top);
287 /* Clear unused address register sets */
288 macb_or_gem_writel(bp, SA2B, 0);
289 macb_or_gem_writel(bp, SA2T, 0);
290 macb_or_gem_writel(bp, SA3B, 0);
291 macb_or_gem_writel(bp, SA3T, 0);
292 macb_or_gem_writel(bp, SA4B, 0);
293 macb_or_gem_writel(bp, SA4T, 0);
296 static void macb_get_hwaddr(struct macb *bp)
303 /* Check all 4 address register for valid address */
304 for (i = 0; i < 4; i++) {
305 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
306 top = macb_or_gem_readl(bp, SA1T + i * 8);
308 addr[0] = bottom & 0xff;
309 addr[1] = (bottom >> 8) & 0xff;
310 addr[2] = (bottom >> 16) & 0xff;
311 addr[3] = (bottom >> 24) & 0xff;
312 addr[4] = top & 0xff;
313 addr[5] = (top >> 8) & 0xff;
315 if (is_valid_ether_addr(addr)) {
316 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
321 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
322 eth_hw_addr_random(bp->dev);
325 static int macb_mdio_wait_for_idle(struct macb *bp)
329 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
330 1, MACB_MDIO_TIMEOUT);
333 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
335 struct macb *bp = bus->priv;
338 status = pm_runtime_get_sync(&bp->pdev->dev);
340 pm_runtime_put_noidle(&bp->pdev->dev);
344 status = macb_mdio_wait_for_idle(bp);
348 if (regnum & MII_ADDR_C45) {
349 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
350 | MACB_BF(RW, MACB_MAN_C45_ADDR)
351 | MACB_BF(PHYA, mii_id)
352 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
353 | MACB_BF(DATA, regnum & 0xFFFF)
354 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
356 status = macb_mdio_wait_for_idle(bp);
360 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
361 | MACB_BF(RW, MACB_MAN_C45_READ)
362 | MACB_BF(PHYA, mii_id)
363 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
364 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
366 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
367 | MACB_BF(RW, MACB_MAN_C22_READ)
368 | MACB_BF(PHYA, mii_id)
369 | MACB_BF(REGA, regnum)
370 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
373 status = macb_mdio_wait_for_idle(bp);
377 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
380 pm_runtime_mark_last_busy(&bp->pdev->dev);
381 pm_runtime_put_autosuspend(&bp->pdev->dev);
386 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
389 struct macb *bp = bus->priv;
392 status = pm_runtime_get_sync(&bp->pdev->dev);
394 pm_runtime_put_noidle(&bp->pdev->dev);
398 status = macb_mdio_wait_for_idle(bp);
400 goto mdio_write_exit;
402 if (regnum & MII_ADDR_C45) {
403 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
404 | MACB_BF(RW, MACB_MAN_C45_ADDR)
405 | MACB_BF(PHYA, mii_id)
406 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
407 | MACB_BF(DATA, regnum & 0xFFFF)
408 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
410 status = macb_mdio_wait_for_idle(bp);
412 goto mdio_write_exit;
414 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
415 | MACB_BF(RW, MACB_MAN_C45_WRITE)
416 | MACB_BF(PHYA, mii_id)
417 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
418 | MACB_BF(CODE, MACB_MAN_C45_CODE)
419 | MACB_BF(DATA, value)));
421 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
422 | MACB_BF(RW, MACB_MAN_C22_WRITE)
423 | MACB_BF(PHYA, mii_id)
424 | MACB_BF(REGA, regnum)
425 | MACB_BF(CODE, MACB_MAN_C22_CODE)
426 | MACB_BF(DATA, value)));
429 status = macb_mdio_wait_for_idle(bp);
431 goto mdio_write_exit;
434 pm_runtime_mark_last_busy(&bp->pdev->dev);
435 pm_runtime_put_autosuspend(&bp->pdev->dev);
440 static void macb_init_buffers(struct macb *bp)
442 struct macb_queue *queue;
445 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
446 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
447 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
448 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
449 queue_writel(queue, RBQPH,
450 upper_32_bits(queue->rx_ring_dma));
452 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
453 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
454 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
455 queue_writel(queue, TBQPH,
456 upper_32_bits(queue->tx_ring_dma));
462 * macb_set_tx_clk() - Set a clock to a new frequency
463 * @bp: pointer to struct macb
464 * @speed: New frequency in Hz
466 static void macb_set_tx_clk(struct macb *bp, int speed)
468 long ferr, rate, rate_rounded;
470 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
473 /* In case of MII the PHY is the clock master */
474 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
491 rate_rounded = clk_round_rate(bp->tx_clk, rate);
492 if (rate_rounded < 0)
495 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
498 ferr = abs(rate_rounded - rate);
499 ferr = DIV_ROUND_UP(ferr, rate / 100000);
502 "unable to generate target frequency: %ld Hz\n",
505 if (clk_set_rate(bp->tx_clk, rate_rounded))
506 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
509 static void macb_validate(struct phylink_config *config,
510 unsigned long *supported,
511 struct phylink_link_state *state)
513 struct net_device *ndev = to_net_dev(config->dev);
514 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
515 struct macb *bp = netdev_priv(ndev);
517 /* We only support MII, RMII, GMII, RGMII & SGMII. */
518 if (state->interface != PHY_INTERFACE_MODE_NA &&
519 state->interface != PHY_INTERFACE_MODE_MII &&
520 state->interface != PHY_INTERFACE_MODE_RMII &&
521 state->interface != PHY_INTERFACE_MODE_GMII &&
522 state->interface != PHY_INTERFACE_MODE_SGMII &&
523 state->interface != PHY_INTERFACE_MODE_10GBASER &&
524 !phy_interface_mode_is_rgmii(state->interface)) {
525 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
529 if (!macb_is_gem(bp) &&
530 (state->interface == PHY_INTERFACE_MODE_GMII ||
531 phy_interface_mode_is_rgmii(state->interface))) {
532 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
536 if (state->interface == PHY_INTERFACE_MODE_10GBASER &&
537 !(bp->caps & MACB_CAPS_HIGH_SPEED &&
538 bp->caps & MACB_CAPS_PCS)) {
539 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
543 phylink_set_port_modes(mask);
544 phylink_set(mask, Autoneg);
545 phylink_set(mask, Asym_Pause);
547 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
548 (state->interface == PHY_INTERFACE_MODE_NA ||
549 state->interface == PHY_INTERFACE_MODE_10GBASER)) {
550 phylink_set(mask, 10000baseCR_Full);
551 phylink_set(mask, 10000baseER_Full);
552 phylink_set(mask, 10000baseKR_Full);
553 phylink_set(mask, 10000baseLR_Full);
554 phylink_set(mask, 10000baseLRM_Full);
555 phylink_set(mask, 10000baseSR_Full);
556 phylink_set(mask, 10000baseT_Full);
557 if (state->interface != PHY_INTERFACE_MODE_NA)
561 phylink_set(mask, 10baseT_Half);
562 phylink_set(mask, 10baseT_Full);
563 phylink_set(mask, 100baseT_Half);
564 phylink_set(mask, 100baseT_Full);
566 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
567 (state->interface == PHY_INTERFACE_MODE_NA ||
568 state->interface == PHY_INTERFACE_MODE_GMII ||
569 state->interface == PHY_INTERFACE_MODE_SGMII ||
570 phy_interface_mode_is_rgmii(state->interface))) {
571 phylink_set(mask, 1000baseT_Full);
572 phylink_set(mask, 1000baseX_Full);
574 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
575 phylink_set(mask, 1000baseT_Half);
578 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
579 bitmap_and(state->advertising, state->advertising, mask,
580 __ETHTOOL_LINK_MODE_MASK_NBITS);
583 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
584 phy_interface_t interface, int speed,
587 struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
590 config = gem_readl(bp, USX_CONTROL);
591 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
592 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
593 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
594 config |= GEM_BIT(TX_EN);
595 gem_writel(bp, USX_CONTROL, config);
598 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
599 struct phylink_link_state *state)
601 struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
604 state->speed = SPEED_10000;
606 state->an_complete = 1;
608 val = gem_readl(bp, USX_STATUS);
609 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
610 val = gem_readl(bp, NCFGR);
611 if (val & GEM_BIT(PAE))
612 state->pause = MLO_PAUSE_RX;
615 static int macb_usx_pcs_config(struct phylink_pcs *pcs,
617 phy_interface_t interface,
618 const unsigned long *advertising,
619 bool permit_pause_to_mac)
621 struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
623 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
629 static void macb_pcs_get_state(struct phylink_pcs *pcs,
630 struct phylink_link_state *state)
635 static void macb_pcs_an_restart(struct phylink_pcs *pcs)
640 static int macb_pcs_config(struct phylink_pcs *pcs,
642 phy_interface_t interface,
643 const unsigned long *advertising,
644 bool permit_pause_to_mac)
649 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
650 .pcs_get_state = macb_usx_pcs_get_state,
651 .pcs_config = macb_usx_pcs_config,
652 .pcs_link_up = macb_usx_pcs_link_up,
655 static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
656 .pcs_get_state = macb_pcs_get_state,
657 .pcs_an_restart = macb_pcs_an_restart,
658 .pcs_config = macb_pcs_config,
661 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
662 const struct phylink_link_state *state)
664 struct net_device *ndev = to_net_dev(config->dev);
665 struct macb *bp = netdev_priv(ndev);
670 spin_lock_irqsave(&bp->lock, flags);
672 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
673 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
675 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
676 if (state->interface == PHY_INTERFACE_MODE_RMII)
677 ctrl |= MACB_BIT(RM9200_RMII);
678 } else if (macb_is_gem(bp)) {
679 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
680 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
682 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
683 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
684 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
685 ctrl |= GEM_BIT(PCSSEL);
686 ncr |= GEM_BIT(ENABLE_HS_MAC);
690 /* Apply the new configuration, if any */
692 macb_or_gem_writel(bp, NCFGR, ctrl);
695 macb_or_gem_writel(bp, NCR, ncr);
697 /* Disable AN for SGMII fixed link configuration, enable otherwise.
698 * Must be written after PCSSEL is set in NCFGR,
699 * otherwise writes will not take effect.
701 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
702 u32 pcsctrl, old_pcsctrl;
704 old_pcsctrl = gem_readl(bp, PCSCNTRL);
705 if (mode == MLO_AN_FIXED)
706 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
708 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
709 if (old_pcsctrl != pcsctrl)
710 gem_writel(bp, PCSCNTRL, pcsctrl);
713 spin_unlock_irqrestore(&bp->lock, flags);
716 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
717 phy_interface_t interface)
719 struct net_device *ndev = to_net_dev(config->dev);
720 struct macb *bp = netdev_priv(ndev);
721 struct macb_queue *queue;
725 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
726 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
727 queue_writel(queue, IDR,
728 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
730 /* Disable Rx and Tx */
731 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
732 macb_writel(bp, NCR, ctrl);
734 netif_tx_stop_all_queues(ndev);
737 static void macb_mac_link_up(struct phylink_config *config,
738 struct phy_device *phy,
739 unsigned int mode, phy_interface_t interface,
740 int speed, int duplex,
741 bool tx_pause, bool rx_pause)
743 struct net_device *ndev = to_net_dev(config->dev);
744 struct macb *bp = netdev_priv(ndev);
745 struct macb_queue *queue;
750 spin_lock_irqsave(&bp->lock, flags);
752 ctrl = macb_or_gem_readl(bp, NCFGR);
754 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
756 if (speed == SPEED_100)
757 ctrl |= MACB_BIT(SPD);
760 ctrl |= MACB_BIT(FD);
762 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
763 ctrl &= ~MACB_BIT(PAE);
764 if (macb_is_gem(bp)) {
765 ctrl &= ~GEM_BIT(GBE);
767 if (speed == SPEED_1000)
768 ctrl |= GEM_BIT(GBE);
772 ctrl |= MACB_BIT(PAE);
774 macb_set_tx_clk(bp, speed);
776 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
777 * cleared the pipeline and control registers.
779 bp->macbgem_ops.mog_init_rings(bp);
780 macb_init_buffers(bp);
782 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
783 queue_writel(queue, IER,
784 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
787 macb_or_gem_writel(bp, NCFGR, ctrl);
789 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
790 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
791 gem_readl(bp, HS_MAC_CONFIG)));
793 spin_unlock_irqrestore(&bp->lock, flags);
795 /* Enable Rx and Tx */
796 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
798 netif_tx_wake_all_queues(ndev);
801 static int macb_mac_prepare(struct phylink_config *config, unsigned int mode,
802 phy_interface_t interface)
804 struct net_device *ndev = to_net_dev(config->dev);
805 struct macb *bp = netdev_priv(ndev);
807 if (interface == PHY_INTERFACE_MODE_10GBASER)
808 bp->phylink_pcs.ops = &macb_phylink_usx_pcs_ops;
809 else if (interface == PHY_INTERFACE_MODE_SGMII)
810 bp->phylink_pcs.ops = &macb_phylink_pcs_ops;
812 bp->phylink_pcs.ops = NULL;
814 if (bp->phylink_pcs.ops)
815 phylink_set_pcs(bp->phylink, &bp->phylink_pcs);
820 static const struct phylink_mac_ops macb_phylink_ops = {
821 .validate = macb_validate,
822 .mac_prepare = macb_mac_prepare,
823 .mac_config = macb_mac_config,
824 .mac_link_down = macb_mac_link_down,
825 .mac_link_up = macb_mac_link_up,
828 static bool macb_phy_handle_exists(struct device_node *dn)
830 dn = of_parse_phandle(dn, "phy-handle", 0);
835 static int macb_phylink_connect(struct macb *bp)
837 struct device_node *dn = bp->pdev->dev.of_node;
838 struct net_device *dev = bp->dev;
839 struct phy_device *phydev;
843 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
845 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
846 phydev = phy_find_first(bp->mii_bus);
848 netdev_err(dev, "no PHY found\n");
852 /* attach the mac to the phy */
853 ret = phylink_connect_phy(bp->phylink, phydev);
857 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
861 phylink_start(bp->phylink);
866 static void macb_get_pcs_fixed_state(struct phylink_config *config,
867 struct phylink_link_state *state)
869 struct net_device *ndev = to_net_dev(config->dev);
870 struct macb *bp = netdev_priv(ndev);
872 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
875 /* based on au1000_eth. c*/
876 static int macb_mii_probe(struct net_device *dev)
878 struct macb *bp = netdev_priv(dev);
880 bp->phylink_config.dev = &dev->dev;
881 bp->phylink_config.type = PHYLINK_NETDEV;
883 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
884 bp->phylink_config.poll_fixed_state = true;
885 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
888 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
889 bp->phy_interface, &macb_phylink_ops);
890 if (IS_ERR(bp->phylink)) {
891 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
892 PTR_ERR(bp->phylink));
893 return PTR_ERR(bp->phylink);
899 static int macb_mdiobus_register(struct macb *bp)
901 struct device_node *child, *np = bp->pdev->dev.of_node;
903 if (of_phy_is_fixed_link(np))
904 return mdiobus_register(bp->mii_bus);
906 /* Only create the PHY from the device tree if at least one PHY is
907 * described. Otherwise scan the entire MDIO bus. We do this to support
908 * old device tree that did not follow the best practices and did not
909 * describe their network PHYs.
911 for_each_available_child_of_node(np, child)
912 if (of_mdiobus_child_is_phy(child)) {
913 /* The loop increments the child refcount,
914 * decrement it before returning.
918 return of_mdiobus_register(bp->mii_bus, np);
921 return mdiobus_register(bp->mii_bus);
924 static int macb_mii_init(struct macb *bp)
928 /* Enable management port */
929 macb_writel(bp, NCR, MACB_BIT(MPE));
931 bp->mii_bus = mdiobus_alloc();
937 bp->mii_bus->name = "MACB_mii_bus";
938 bp->mii_bus->read = &macb_mdio_read;
939 bp->mii_bus->write = &macb_mdio_write;
940 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
941 bp->pdev->name, bp->pdev->id);
942 bp->mii_bus->priv = bp;
943 bp->mii_bus->parent = &bp->pdev->dev;
945 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
947 err = macb_mdiobus_register(bp);
949 goto err_out_free_mdiobus;
951 err = macb_mii_probe(bp->dev);
953 goto err_out_unregister_bus;
957 err_out_unregister_bus:
958 mdiobus_unregister(bp->mii_bus);
959 err_out_free_mdiobus:
960 mdiobus_free(bp->mii_bus);
965 static void macb_update_stats(struct macb *bp)
967 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
968 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
969 int offset = MACB_PFR;
971 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
973 for (; p < end; p++, offset += 4)
974 *p += bp->macb_reg_readl(bp, offset);
977 static int macb_halt_tx(struct macb *bp)
979 unsigned long halt_time, timeout;
982 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
984 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
987 status = macb_readl(bp, TSR);
988 if (!(status & MACB_BIT(TGO)))
992 } while (time_before(halt_time, timeout));
997 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
999 if (tx_skb->mapping) {
1000 if (tx_skb->mapped_as_page)
1001 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
1002 tx_skb->size, DMA_TO_DEVICE);
1004 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
1005 tx_skb->size, DMA_TO_DEVICE);
1006 tx_skb->mapping = 0;
1010 dev_kfree_skb_any(tx_skb->skb);
1015 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
1017 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1018 struct macb_dma_desc_64 *desc_64;
1020 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1021 desc_64 = macb_64b_desc(bp, desc);
1022 desc_64->addrh = upper_32_bits(addr);
1023 /* The low bits of RX address contain the RX_USED bit, clearing
1024 * of which allows packet RX. Make sure the high bits are also
1025 * visible to HW at that point.
1030 desc->addr = lower_32_bits(addr);
1033 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1035 dma_addr_t addr = 0;
1036 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1037 struct macb_dma_desc_64 *desc_64;
1039 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1040 desc_64 = macb_64b_desc(bp, desc);
1041 addr = ((u64)(desc_64->addrh) << 32);
1044 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1048 static void macb_tx_error_task(struct work_struct *work)
1050 struct macb_queue *queue = container_of(work, struct macb_queue,
1052 struct macb *bp = queue->bp;
1053 struct macb_tx_skb *tx_skb;
1054 struct macb_dma_desc *desc;
1055 struct sk_buff *skb;
1057 unsigned long flags;
1059 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1060 (unsigned int)(queue - bp->queues),
1061 queue->tx_tail, queue->tx_head);
1063 /* Prevent the queue IRQ handlers from running: each of them may call
1064 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
1065 * As explained below, we have to halt the transmission before updating
1066 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1067 * network engine about the macb/gem being halted.
1069 spin_lock_irqsave(&bp->lock, flags);
1071 /* Make sure nobody is trying to queue up new packets */
1072 netif_tx_stop_all_queues(bp->dev);
1074 /* Stop transmission now
1075 * (in case we have just queued new packets)
1076 * macb/gem must be halted to write TBQP register
1078 if (macb_halt_tx(bp))
1079 /* Just complain for now, reinitializing TX path can be good */
1080 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1082 /* Treat frames in TX queue including the ones that caused the error.
1083 * Free transmit buffers in upper layer.
1085 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1088 desc = macb_tx_desc(queue, tail);
1090 tx_skb = macb_tx_skb(queue, tail);
1093 if (ctrl & MACB_BIT(TX_USED)) {
1094 /* skb is set for the last buffer of the frame */
1096 macb_tx_unmap(bp, tx_skb);
1098 tx_skb = macb_tx_skb(queue, tail);
1102 /* ctrl still refers to the first buffer descriptor
1103 * since it's the only one written back by the hardware
1105 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1106 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1107 macb_tx_ring_wrap(bp, tail),
1109 bp->dev->stats.tx_packets++;
1110 queue->stats.tx_packets++;
1111 bp->dev->stats.tx_bytes += skb->len;
1112 queue->stats.tx_bytes += skb->len;
1115 /* "Buffers exhausted mid-frame" errors may only happen
1116 * if the driver is buggy, so complain loudly about
1117 * those. Statistics are updated by hardware.
1119 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1121 "BUG: TX buffers exhausted mid-frame\n");
1123 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1126 macb_tx_unmap(bp, tx_skb);
1129 /* Set end of TX queue */
1130 desc = macb_tx_desc(queue, 0);
1131 macb_set_addr(bp, desc, 0);
1132 desc->ctrl = MACB_BIT(TX_USED);
1134 /* Make descriptor updates visible to hardware */
1137 /* Reinitialize the TX desc queue */
1138 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1139 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1140 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1141 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1143 /* Make TX ring reflect state of hardware */
1147 /* Housework before enabling TX IRQ */
1148 macb_writel(bp, TSR, macb_readl(bp, TSR));
1149 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1151 /* Now we are ready to start transmission again */
1152 netif_tx_start_all_queues(bp->dev);
1153 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1155 spin_unlock_irqrestore(&bp->lock, flags);
1158 static void macb_tx_interrupt(struct macb_queue *queue)
1163 struct macb *bp = queue->bp;
1164 u16 queue_index = queue - bp->queues;
1166 status = macb_readl(bp, TSR);
1167 macb_writel(bp, TSR, status);
1169 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1170 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1172 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
1173 (unsigned long)status);
1175 head = queue->tx_head;
1176 for (tail = queue->tx_tail; tail != head; tail++) {
1177 struct macb_tx_skb *tx_skb;
1178 struct sk_buff *skb;
1179 struct macb_dma_desc *desc;
1182 desc = macb_tx_desc(queue, tail);
1184 /* Make hw descriptor updates visible to CPU */
1189 /* TX_USED bit is only set by hardware on the very first buffer
1190 * descriptor of the transmitted frame.
1192 if (!(ctrl & MACB_BIT(TX_USED)))
1195 /* Process all buffers of the current transmitted frame */
1197 tx_skb = macb_tx_skb(queue, tail);
1200 /* First, update TX stats if needed */
1202 if (unlikely(skb_shinfo(skb)->tx_flags &
1204 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1205 /* skb now belongs to timestamp buffer
1206 * and will be removed later
1210 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1211 macb_tx_ring_wrap(bp, tail),
1213 bp->dev->stats.tx_packets++;
1214 queue->stats.tx_packets++;
1215 bp->dev->stats.tx_bytes += skb->len;
1216 queue->stats.tx_bytes += skb->len;
1219 /* Now we can safely release resources */
1220 macb_tx_unmap(bp, tx_skb);
1222 /* skb is set only for the last buffer of the frame.
1223 * WARNING: at this point skb has been freed by
1231 queue->tx_tail = tail;
1232 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1233 CIRC_CNT(queue->tx_head, queue->tx_tail,
1234 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1235 netif_wake_subqueue(bp->dev, queue_index);
1238 static void gem_rx_refill(struct macb_queue *queue)
1241 struct sk_buff *skb;
1243 struct macb *bp = queue->bp;
1244 struct macb_dma_desc *desc;
1246 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1247 bp->rx_ring_size) > 0) {
1248 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1250 /* Make hw descriptor updates visible to CPU */
1253 queue->rx_prepared_head++;
1254 desc = macb_rx_desc(queue, entry);
1256 if (!queue->rx_skbuff[entry]) {
1257 /* allocate sk_buff for this free entry in ring */
1258 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1259 if (unlikely(!skb)) {
1261 "Unable to allocate sk_buff\n");
1265 /* now fill corresponding descriptor entry */
1266 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1269 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1274 queue->rx_skbuff[entry] = skb;
1276 if (entry == bp->rx_ring_size - 1)
1277 paddr |= MACB_BIT(RX_WRAP);
1279 /* Setting addr clears RX_USED and allows reception,
1280 * make sure ctrl is cleared first to avoid a race.
1283 macb_set_addr(bp, desc, paddr);
1285 /* properly align Ethernet header */
1286 skb_reserve(skb, NET_IP_ALIGN);
1290 desc->addr &= ~MACB_BIT(RX_USED);
1294 /* Make descriptor updates visible to hardware */
1297 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1298 queue, queue->rx_prepared_head, queue->rx_tail);
1301 /* Mark DMA descriptors from begin up to and not including end as unused */
1302 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1307 for (frag = begin; frag != end; frag++) {
1308 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1310 desc->addr &= ~MACB_BIT(RX_USED);
1313 /* Make descriptor updates visible to hardware */
1316 /* When this happens, the hardware stats registers for
1317 * whatever caused this is updated, so we don't have to record
1322 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1325 struct macb *bp = queue->bp;
1328 struct sk_buff *skb;
1329 struct macb_dma_desc *desc;
1332 while (count < budget) {
1337 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1338 desc = macb_rx_desc(queue, entry);
1340 /* Make hw descriptor updates visible to CPU */
1343 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1344 addr = macb_get_addr(bp, desc);
1349 /* Ensure ctrl is at least as up-to-date as rxused */
1357 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1359 "not whole frame pointed by descriptor\n");
1360 bp->dev->stats.rx_dropped++;
1361 queue->stats.rx_dropped++;
1364 skb = queue->rx_skbuff[entry];
1365 if (unlikely(!skb)) {
1367 "inconsistent Rx descriptor chain\n");
1368 bp->dev->stats.rx_dropped++;
1369 queue->stats.rx_dropped++;
1372 /* now everything is ready for receiving packet */
1373 queue->rx_skbuff[entry] = NULL;
1374 len = ctrl & bp->rx_frm_len_mask;
1376 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1379 dma_unmap_single(&bp->pdev->dev, addr,
1380 bp->rx_buffer_size, DMA_FROM_DEVICE);
1382 skb->protocol = eth_type_trans(skb, bp->dev);
1383 skb_checksum_none_assert(skb);
1384 if (bp->dev->features & NETIF_F_RXCSUM &&
1385 !(bp->dev->flags & IFF_PROMISC) &&
1386 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1387 skb->ip_summed = CHECKSUM_UNNECESSARY;
1389 bp->dev->stats.rx_packets++;
1390 queue->stats.rx_packets++;
1391 bp->dev->stats.rx_bytes += skb->len;
1392 queue->stats.rx_bytes += skb->len;
1394 gem_ptp_do_rxstamp(bp, skb, desc);
1396 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1397 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1398 skb->len, skb->csum);
1399 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1400 skb_mac_header(skb), 16, true);
1401 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1402 skb->data, 32, true);
1405 napi_gro_receive(napi, skb);
1408 gem_rx_refill(queue);
1413 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1414 unsigned int first_frag, unsigned int last_frag)
1418 unsigned int offset;
1419 struct sk_buff *skb;
1420 struct macb_dma_desc *desc;
1421 struct macb *bp = queue->bp;
1423 desc = macb_rx_desc(queue, last_frag);
1424 len = desc->ctrl & bp->rx_frm_len_mask;
1426 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1427 macb_rx_ring_wrap(bp, first_frag),
1428 macb_rx_ring_wrap(bp, last_frag), len);
1430 /* The ethernet header starts NET_IP_ALIGN bytes into the
1431 * first buffer. Since the header is 14 bytes, this makes the
1432 * payload word-aligned.
1434 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1435 * the two padding bytes into the skb so that we avoid hitting
1436 * the slowpath in memcpy(), and pull them off afterwards.
1438 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1440 bp->dev->stats.rx_dropped++;
1441 for (frag = first_frag; ; frag++) {
1442 desc = macb_rx_desc(queue, frag);
1443 desc->addr &= ~MACB_BIT(RX_USED);
1444 if (frag == last_frag)
1448 /* Make descriptor updates visible to hardware */
1455 len += NET_IP_ALIGN;
1456 skb_checksum_none_assert(skb);
1459 for (frag = first_frag; ; frag++) {
1460 unsigned int frag_len = bp->rx_buffer_size;
1462 if (offset + frag_len > len) {
1463 if (unlikely(frag != last_frag)) {
1464 dev_kfree_skb_any(skb);
1467 frag_len = len - offset;
1469 skb_copy_to_linear_data_offset(skb, offset,
1470 macb_rx_buffer(queue, frag),
1472 offset += bp->rx_buffer_size;
1473 desc = macb_rx_desc(queue, frag);
1474 desc->addr &= ~MACB_BIT(RX_USED);
1476 if (frag == last_frag)
1480 /* Make descriptor updates visible to hardware */
1483 __skb_pull(skb, NET_IP_ALIGN);
1484 skb->protocol = eth_type_trans(skb, bp->dev);
1486 bp->dev->stats.rx_packets++;
1487 bp->dev->stats.rx_bytes += skb->len;
1488 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1489 skb->len, skb->csum);
1490 napi_gro_receive(napi, skb);
1495 static inline void macb_init_rx_ring(struct macb_queue *queue)
1497 struct macb *bp = queue->bp;
1499 struct macb_dma_desc *desc = NULL;
1502 addr = queue->rx_buffers_dma;
1503 for (i = 0; i < bp->rx_ring_size; i++) {
1504 desc = macb_rx_desc(queue, i);
1505 macb_set_addr(bp, desc, addr);
1507 addr += bp->rx_buffer_size;
1509 desc->addr |= MACB_BIT(RX_WRAP);
1513 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1516 struct macb *bp = queue->bp;
1517 bool reset_rx_queue = false;
1520 int first_frag = -1;
1522 for (tail = queue->rx_tail; budget > 0; tail++) {
1523 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1526 /* Make hw descriptor updates visible to CPU */
1529 if (!(desc->addr & MACB_BIT(RX_USED)))
1532 /* Ensure ctrl is at least as up-to-date as addr */
1537 if (ctrl & MACB_BIT(RX_SOF)) {
1538 if (first_frag != -1)
1539 discard_partial_frame(queue, first_frag, tail);
1543 if (ctrl & MACB_BIT(RX_EOF)) {
1546 if (unlikely(first_frag == -1)) {
1547 reset_rx_queue = true;
1551 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1553 if (unlikely(dropped < 0)) {
1554 reset_rx_queue = true;
1564 if (unlikely(reset_rx_queue)) {
1565 unsigned long flags;
1568 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1570 spin_lock_irqsave(&bp->lock, flags);
1572 ctrl = macb_readl(bp, NCR);
1573 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1575 macb_init_rx_ring(queue);
1576 queue_writel(queue, RBQP, queue->rx_ring_dma);
1578 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1580 spin_unlock_irqrestore(&bp->lock, flags);
1584 if (first_frag != -1)
1585 queue->rx_tail = first_frag;
1587 queue->rx_tail = tail;
1592 static int macb_poll(struct napi_struct *napi, int budget)
1594 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1595 struct macb *bp = queue->bp;
1599 status = macb_readl(bp, RSR);
1600 macb_writel(bp, RSR, status);
1602 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1603 (unsigned long)status, budget);
1605 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1606 if (work_done < budget) {
1607 napi_complete_done(napi, work_done);
1609 /* Packets received while interrupts were disabled */
1610 status = macb_readl(bp, RSR);
1612 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1613 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1614 napi_reschedule(napi);
1616 queue_writel(queue, IER, bp->rx_intr_mask);
1620 /* TODO: Handle errors */
1625 static void macb_hresp_error_task(struct tasklet_struct *t)
1627 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1628 struct net_device *dev = bp->dev;
1629 struct macb_queue *queue;
1633 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1634 queue_writel(queue, IDR, bp->rx_intr_mask |
1638 ctrl = macb_readl(bp, NCR);
1639 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1640 macb_writel(bp, NCR, ctrl);
1642 netif_tx_stop_all_queues(dev);
1643 netif_carrier_off(dev);
1645 bp->macbgem_ops.mog_init_rings(bp);
1647 /* Initialize TX and RX buffers */
1648 macb_init_buffers(bp);
1650 /* Enable interrupts */
1651 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1652 queue_writel(queue, IER,
1657 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1658 macb_writel(bp, NCR, ctrl);
1660 netif_carrier_on(dev);
1661 netif_tx_start_all_queues(dev);
1664 static void macb_tx_restart(struct macb_queue *queue)
1666 unsigned int head = queue->tx_head;
1667 unsigned int tail = queue->tx_tail;
1668 struct macb *bp = queue->bp;
1670 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1671 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1676 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1679 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1681 struct macb_queue *queue = dev_id;
1682 struct macb *bp = queue->bp;
1685 status = queue_readl(queue, ISR);
1687 if (unlikely(!status))
1690 spin_lock(&bp->lock);
1692 if (status & MACB_BIT(WOL)) {
1693 queue_writel(queue, IDR, MACB_BIT(WOL));
1694 macb_writel(bp, WOL, 0);
1695 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1696 (unsigned int)(queue - bp->queues),
1697 (unsigned long)status);
1698 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1699 queue_writel(queue, ISR, MACB_BIT(WOL));
1700 pm_wakeup_event(&bp->pdev->dev, 0);
1703 spin_unlock(&bp->lock);
1708 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1710 struct macb_queue *queue = dev_id;
1711 struct macb *bp = queue->bp;
1714 status = queue_readl(queue, ISR);
1716 if (unlikely(!status))
1719 spin_lock(&bp->lock);
1721 if (status & GEM_BIT(WOL)) {
1722 queue_writel(queue, IDR, GEM_BIT(WOL));
1723 gem_writel(bp, WOL, 0);
1724 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1725 (unsigned int)(queue - bp->queues),
1726 (unsigned long)status);
1727 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1728 queue_writel(queue, ISR, GEM_BIT(WOL));
1729 pm_wakeup_event(&bp->pdev->dev, 0);
1732 spin_unlock(&bp->lock);
1737 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1739 struct macb_queue *queue = dev_id;
1740 struct macb *bp = queue->bp;
1741 struct net_device *dev = bp->dev;
1744 status = queue_readl(queue, ISR);
1746 if (unlikely(!status))
1749 spin_lock(&bp->lock);
1752 /* close possible race with dev_close */
1753 if (unlikely(!netif_running(dev))) {
1754 queue_writel(queue, IDR, -1);
1755 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1756 queue_writel(queue, ISR, -1);
1760 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1761 (unsigned int)(queue - bp->queues),
1762 (unsigned long)status);
1764 if (status & bp->rx_intr_mask) {
1765 /* There's no point taking any more interrupts
1766 * until we have processed the buffers. The
1767 * scheduling call may fail if the poll routine
1768 * is already scheduled, so disable interrupts
1771 queue_writel(queue, IDR, bp->rx_intr_mask);
1772 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1773 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1775 if (napi_schedule_prep(&queue->napi)) {
1776 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1777 __napi_schedule(&queue->napi);
1781 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1782 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1783 schedule_work(&queue->tx_error_task);
1785 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1786 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1791 if (status & MACB_BIT(TCOMP))
1792 macb_tx_interrupt(queue);
1794 if (status & MACB_BIT(TXUBR))
1795 macb_tx_restart(queue);
1797 /* Link change detection isn't possible with RMII, so we'll
1798 * add that if/when we get our hands on a full-blown MII PHY.
1801 /* There is a hardware issue under heavy load where DMA can
1802 * stop, this causes endless "used buffer descriptor read"
1803 * interrupts but it can be cleared by re-enabling RX. See
1804 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1805 * section 16.7.4 for details. RXUBR is only enabled for
1806 * these two versions.
1808 if (status & MACB_BIT(RXUBR)) {
1809 ctrl = macb_readl(bp, NCR);
1810 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1812 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1814 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1815 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1818 if (status & MACB_BIT(ISR_ROVR)) {
1819 /* We missed at least one packet */
1820 if (macb_is_gem(bp))
1821 bp->hw_stats.gem.rx_overruns++;
1823 bp->hw_stats.macb.rx_overruns++;
1825 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1826 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1829 if (status & MACB_BIT(HRESP)) {
1830 tasklet_schedule(&bp->hresp_err_tasklet);
1831 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1833 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1834 queue_writel(queue, ISR, MACB_BIT(HRESP));
1836 status = queue_readl(queue, ISR);
1839 spin_unlock(&bp->lock);
1844 #ifdef CONFIG_NET_POLL_CONTROLLER
1845 /* Polling receive - used by netconsole and other diagnostic tools
1846 * to allow network i/o with interrupts disabled.
1848 static void macb_poll_controller(struct net_device *dev)
1850 struct macb *bp = netdev_priv(dev);
1851 struct macb_queue *queue;
1852 unsigned long flags;
1855 local_irq_save(flags);
1856 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1857 macb_interrupt(dev->irq, queue);
1858 local_irq_restore(flags);
1862 static unsigned int macb_tx_map(struct macb *bp,
1863 struct macb_queue *queue,
1864 struct sk_buff *skb,
1865 unsigned int hdrlen)
1868 unsigned int len, entry, i, tx_head = queue->tx_head;
1869 struct macb_tx_skb *tx_skb = NULL;
1870 struct macb_dma_desc *desc;
1871 unsigned int offset, size, count = 0;
1872 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1873 unsigned int eof = 1, mss_mfs = 0;
1874 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1877 if (skb_shinfo(skb)->gso_size != 0) {
1878 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1880 lso_ctrl = MACB_LSO_UFO_ENABLE;
1883 lso_ctrl = MACB_LSO_TSO_ENABLE;
1886 /* First, map non-paged data */
1887 len = skb_headlen(skb);
1889 /* first buffer length */
1894 entry = macb_tx_ring_wrap(bp, tx_head);
1895 tx_skb = &queue->tx_skb[entry];
1897 mapping = dma_map_single(&bp->pdev->dev,
1899 size, DMA_TO_DEVICE);
1900 if (dma_mapping_error(&bp->pdev->dev, mapping))
1903 /* Save info to properly release resources */
1905 tx_skb->mapping = mapping;
1906 tx_skb->size = size;
1907 tx_skb->mapped_as_page = false;
1914 size = min(len, bp->max_tx_length);
1917 /* Then, map paged data from fragments */
1918 for (f = 0; f < nr_frags; f++) {
1919 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1921 len = skb_frag_size(frag);
1924 size = min(len, bp->max_tx_length);
1925 entry = macb_tx_ring_wrap(bp, tx_head);
1926 tx_skb = &queue->tx_skb[entry];
1928 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1929 offset, size, DMA_TO_DEVICE);
1930 if (dma_mapping_error(&bp->pdev->dev, mapping))
1933 /* Save info to properly release resources */
1935 tx_skb->mapping = mapping;
1936 tx_skb->size = size;
1937 tx_skb->mapped_as_page = true;
1946 /* Should never happen */
1947 if (unlikely(!tx_skb)) {
1948 netdev_err(bp->dev, "BUG! empty skb!\n");
1952 /* This is the last buffer of the frame: save socket buffer */
1955 /* Update TX ring: update buffer descriptors in reverse order
1956 * to avoid race condition
1959 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1960 * to set the end of TX queue
1963 entry = macb_tx_ring_wrap(bp, i);
1964 ctrl = MACB_BIT(TX_USED);
1965 desc = macb_tx_desc(queue, entry);
1969 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1970 /* include header and FCS in value given to h/w */
1971 mss_mfs = skb_shinfo(skb)->gso_size +
1972 skb_transport_offset(skb) +
1975 mss_mfs = skb_shinfo(skb)->gso_size;
1976 /* TCP Sequence Number Source Select
1977 * can be set only for TSO
1985 entry = macb_tx_ring_wrap(bp, i);
1986 tx_skb = &queue->tx_skb[entry];
1987 desc = macb_tx_desc(queue, entry);
1989 ctrl = (u32)tx_skb->size;
1991 ctrl |= MACB_BIT(TX_LAST);
1994 if (unlikely(entry == (bp->tx_ring_size - 1)))
1995 ctrl |= MACB_BIT(TX_WRAP);
1997 /* First descriptor is header descriptor */
1998 if (i == queue->tx_head) {
1999 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2000 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2001 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2002 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
2003 ctrl |= MACB_BIT(TX_NOCRC);
2005 /* Only set MSS/MFS on payload descriptors
2006 * (second or later descriptor)
2008 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2010 /* Set TX buffer descriptor */
2011 macb_set_addr(bp, desc, tx_skb->mapping);
2012 /* desc->addr must be visible to hardware before clearing
2013 * 'TX_USED' bit in desc->ctrl.
2017 } while (i != queue->tx_head);
2019 queue->tx_head = tx_head;
2024 netdev_err(bp->dev, "TX DMA map failed\n");
2026 for (i = queue->tx_head; i != tx_head; i++) {
2027 tx_skb = macb_tx_skb(queue, i);
2029 macb_tx_unmap(bp, tx_skb);
2035 static netdev_features_t macb_features_check(struct sk_buff *skb,
2036 struct net_device *dev,
2037 netdev_features_t features)
2039 unsigned int nr_frags, f;
2040 unsigned int hdrlen;
2042 /* Validate LSO compatibility */
2044 /* there is only one buffer or protocol is not UDP */
2045 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2048 /* length of header */
2049 hdrlen = skb_transport_offset(skb);
2052 * When software supplies two or more payload buffers all payload buffers
2053 * apart from the last must be a multiple of 8 bytes in size.
2055 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2056 return features & ~MACB_NETIF_LSO;
2058 nr_frags = skb_shinfo(skb)->nr_frags;
2059 /* No need to check last fragment */
2061 for (f = 0; f < nr_frags; f++) {
2062 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2064 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2065 return features & ~MACB_NETIF_LSO;
2070 static inline int macb_clear_csum(struct sk_buff *skb)
2072 /* no change for packets without checksum offloading */
2073 if (skb->ip_summed != CHECKSUM_PARTIAL)
2076 /* make sure we can modify the header */
2077 if (unlikely(skb_cow_head(skb, 0)))
2080 /* initialize checksum field
2081 * This is required - at least for Zynq, which otherwise calculates
2082 * wrong UDP header checksums for UDP packets with UDP data len <=2
2084 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2088 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2090 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2091 skb_is_nonlinear(*skb);
2092 int padlen = ETH_ZLEN - (*skb)->len;
2093 int headroom = skb_headroom(*skb);
2094 int tailroom = skb_tailroom(*skb);
2095 struct sk_buff *nskb;
2098 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2099 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2100 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
2104 /* FCS could be appeded to tailroom. */
2105 if (tailroom >= ETH_FCS_LEN)
2107 /* FCS could be appeded by moving data to headroom. */
2108 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
2110 /* No room for FCS, need to reallocate skb. */
2112 padlen = ETH_FCS_LEN;
2114 /* Add room for FCS. */
2115 padlen += ETH_FCS_LEN;
2118 if (!cloned && headroom + tailroom >= padlen) {
2119 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
2120 skb_set_tail_pointer(*skb, (*skb)->len);
2122 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2126 dev_consume_skb_any(*skb);
2130 if (padlen > ETH_FCS_LEN)
2131 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2134 /* set FCS to packet */
2135 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2138 skb_put_u8(*skb, fcs & 0xff);
2139 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2140 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2141 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2146 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2148 u16 queue_index = skb_get_queue_mapping(skb);
2149 struct macb *bp = netdev_priv(dev);
2150 struct macb_queue *queue = &bp->queues[queue_index];
2151 unsigned long flags;
2152 unsigned int desc_cnt, nr_frags, frag_size, f;
2153 unsigned int hdrlen;
2155 netdev_tx_t ret = NETDEV_TX_OK;
2157 if (macb_clear_csum(skb)) {
2158 dev_kfree_skb_any(skb);
2162 if (macb_pad_and_fcs(&skb, dev)) {
2163 dev_kfree_skb_any(skb);
2167 is_lso = (skb_shinfo(skb)->gso_size != 0);
2170 /* length of headers */
2171 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2172 /* only queue eth + ip headers separately for UDP */
2173 hdrlen = skb_transport_offset(skb);
2175 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
2176 if (skb_headlen(skb) < hdrlen) {
2177 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2178 /* if this is required, would need to copy to single buffer */
2179 return NETDEV_TX_BUSY;
2182 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2184 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2185 netdev_vdbg(bp->dev,
2186 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2187 queue_index, skb->len, skb->head, skb->data,
2188 skb_tail_pointer(skb), skb_end_pointer(skb));
2189 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2190 skb->data, 16, true);
2193 /* Count how many TX buffer descriptors are needed to send this
2194 * socket buffer: skb fragments of jumbo frames may need to be
2195 * split into many buffer descriptors.
2197 if (is_lso && (skb_headlen(skb) > hdrlen))
2198 /* extra header descriptor if also payload in first buffer */
2199 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2201 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2202 nr_frags = skb_shinfo(skb)->nr_frags;
2203 for (f = 0; f < nr_frags; f++) {
2204 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2205 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2208 spin_lock_irqsave(&bp->lock, flags);
2210 /* This is a hard error, log it. */
2211 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2212 bp->tx_ring_size) < desc_cnt) {
2213 netif_stop_subqueue(dev, queue_index);
2214 spin_unlock_irqrestore(&bp->lock, flags);
2215 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2216 queue->tx_head, queue->tx_tail);
2217 return NETDEV_TX_BUSY;
2220 /* Map socket buffer for DMA transfer */
2221 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2222 dev_kfree_skb_any(skb);
2226 /* Make newly initialized descriptor visible to hardware */
2228 skb_tx_timestamp(skb);
2230 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2232 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2233 netif_stop_subqueue(dev, queue_index);
2236 spin_unlock_irqrestore(&bp->lock, flags);
2241 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2243 if (!macb_is_gem(bp)) {
2244 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2246 bp->rx_buffer_size = size;
2248 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2250 "RX buffer must be multiple of %d bytes, expanding\n",
2251 RX_BUFFER_MULTIPLE);
2252 bp->rx_buffer_size =
2253 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2257 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2258 bp->dev->mtu, bp->rx_buffer_size);
2261 static void gem_free_rx_buffers(struct macb *bp)
2263 struct sk_buff *skb;
2264 struct macb_dma_desc *desc;
2265 struct macb_queue *queue;
2270 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2271 if (!queue->rx_skbuff)
2274 for (i = 0; i < bp->rx_ring_size; i++) {
2275 skb = queue->rx_skbuff[i];
2280 desc = macb_rx_desc(queue, i);
2281 addr = macb_get_addr(bp, desc);
2283 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2285 dev_kfree_skb_any(skb);
2289 kfree(queue->rx_skbuff);
2290 queue->rx_skbuff = NULL;
2294 static void macb_free_rx_buffers(struct macb *bp)
2296 struct macb_queue *queue = &bp->queues[0];
2298 if (queue->rx_buffers) {
2299 dma_free_coherent(&bp->pdev->dev,
2300 bp->rx_ring_size * bp->rx_buffer_size,
2301 queue->rx_buffers, queue->rx_buffers_dma);
2302 queue->rx_buffers = NULL;
2306 static void macb_free_consistent(struct macb *bp)
2308 struct macb_queue *queue;
2312 bp->macbgem_ops.mog_free_rx_buffers(bp);
2314 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2315 kfree(queue->tx_skb);
2316 queue->tx_skb = NULL;
2317 if (queue->tx_ring) {
2318 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2319 dma_free_coherent(&bp->pdev->dev, size,
2320 queue->tx_ring, queue->tx_ring_dma);
2321 queue->tx_ring = NULL;
2323 if (queue->rx_ring) {
2324 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2325 dma_free_coherent(&bp->pdev->dev, size,
2326 queue->rx_ring, queue->rx_ring_dma);
2327 queue->rx_ring = NULL;
2332 static int gem_alloc_rx_buffers(struct macb *bp)
2334 struct macb_queue *queue;
2338 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2339 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2340 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2341 if (!queue->rx_skbuff)
2345 "Allocated %d RX struct sk_buff entries at %p\n",
2346 bp->rx_ring_size, queue->rx_skbuff);
2351 static int macb_alloc_rx_buffers(struct macb *bp)
2353 struct macb_queue *queue = &bp->queues[0];
2356 size = bp->rx_ring_size * bp->rx_buffer_size;
2357 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2358 &queue->rx_buffers_dma, GFP_KERNEL);
2359 if (!queue->rx_buffers)
2363 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2364 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2368 static int macb_alloc_consistent(struct macb *bp)
2370 struct macb_queue *queue;
2374 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2375 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2376 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2377 &queue->tx_ring_dma,
2379 if (!queue->tx_ring)
2382 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2383 q, size, (unsigned long)queue->tx_ring_dma,
2386 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2387 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2391 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2392 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2393 &queue->rx_ring_dma, GFP_KERNEL);
2394 if (!queue->rx_ring)
2397 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2398 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2400 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2406 macb_free_consistent(bp);
2410 static void gem_init_rings(struct macb *bp)
2412 struct macb_queue *queue;
2413 struct macb_dma_desc *desc = NULL;
2417 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2418 for (i = 0; i < bp->tx_ring_size; i++) {
2419 desc = macb_tx_desc(queue, i);
2420 macb_set_addr(bp, desc, 0);
2421 desc->ctrl = MACB_BIT(TX_USED);
2423 desc->ctrl |= MACB_BIT(TX_WRAP);
2428 queue->rx_prepared_head = 0;
2430 gem_rx_refill(queue);
2435 static void macb_init_rings(struct macb *bp)
2438 struct macb_dma_desc *desc = NULL;
2440 macb_init_rx_ring(&bp->queues[0]);
2442 for (i = 0; i < bp->tx_ring_size; i++) {
2443 desc = macb_tx_desc(&bp->queues[0], i);
2444 macb_set_addr(bp, desc, 0);
2445 desc->ctrl = MACB_BIT(TX_USED);
2447 bp->queues[0].tx_head = 0;
2448 bp->queues[0].tx_tail = 0;
2449 desc->ctrl |= MACB_BIT(TX_WRAP);
2452 static void macb_reset_hw(struct macb *bp)
2454 struct macb_queue *queue;
2456 u32 ctrl = macb_readl(bp, NCR);
2458 /* Disable RX and TX (XXX: Should we halt the transmission
2461 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2463 /* Clear the stats registers (XXX: Update stats first?) */
2464 ctrl |= MACB_BIT(CLRSTAT);
2466 macb_writel(bp, NCR, ctrl);
2468 /* Clear all status flags */
2469 macb_writel(bp, TSR, -1);
2470 macb_writel(bp, RSR, -1);
2472 /* Disable all interrupts */
2473 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2474 queue_writel(queue, IDR, -1);
2475 queue_readl(queue, ISR);
2476 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2477 queue_writel(queue, ISR, -1);
2481 static u32 gem_mdc_clk_div(struct macb *bp)
2484 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2486 if (pclk_hz <= 20000000)
2487 config = GEM_BF(CLK, GEM_CLK_DIV8);
2488 else if (pclk_hz <= 40000000)
2489 config = GEM_BF(CLK, GEM_CLK_DIV16);
2490 else if (pclk_hz <= 80000000)
2491 config = GEM_BF(CLK, GEM_CLK_DIV32);
2492 else if (pclk_hz <= 120000000)
2493 config = GEM_BF(CLK, GEM_CLK_DIV48);
2494 else if (pclk_hz <= 160000000)
2495 config = GEM_BF(CLK, GEM_CLK_DIV64);
2497 config = GEM_BF(CLK, GEM_CLK_DIV96);
2502 static u32 macb_mdc_clk_div(struct macb *bp)
2505 unsigned long pclk_hz;
2507 if (macb_is_gem(bp))
2508 return gem_mdc_clk_div(bp);
2510 pclk_hz = clk_get_rate(bp->pclk);
2511 if (pclk_hz <= 20000000)
2512 config = MACB_BF(CLK, MACB_CLK_DIV8);
2513 else if (pclk_hz <= 40000000)
2514 config = MACB_BF(CLK, MACB_CLK_DIV16);
2515 else if (pclk_hz <= 80000000)
2516 config = MACB_BF(CLK, MACB_CLK_DIV32);
2518 config = MACB_BF(CLK, MACB_CLK_DIV64);
2523 /* Get the DMA bus width field of the network configuration register that we
2524 * should program. We find the width from decoding the design configuration
2525 * register to find the maximum supported data bus width.
2527 static u32 macb_dbw(struct macb *bp)
2529 if (!macb_is_gem(bp))
2532 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2534 return GEM_BF(DBW, GEM_DBW128);
2536 return GEM_BF(DBW, GEM_DBW64);
2539 return GEM_BF(DBW, GEM_DBW32);
2543 /* Configure the receive DMA engine
2544 * - use the correct receive buffer size
2545 * - set best burst length for DMA operations
2546 * (if not supported by FIFO, it will fallback to default)
2547 * - set both rx/tx packet buffers to full memory size
2548 * These are configurable parameters for GEM.
2550 static void macb_configure_dma(struct macb *bp)
2552 struct macb_queue *queue;
2557 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2558 if (macb_is_gem(bp)) {
2559 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2560 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2562 queue_writel(queue, RBQS, buffer_size);
2564 dmacfg |= GEM_BF(RXBS, buffer_size);
2566 if (bp->dma_burst_length)
2567 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2568 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2569 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2572 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2574 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2576 if (bp->dev->features & NETIF_F_HW_CSUM)
2577 dmacfg |= GEM_BIT(TXCOEN);
2579 dmacfg &= ~GEM_BIT(TXCOEN);
2581 dmacfg &= ~GEM_BIT(ADDR64);
2582 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2583 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2584 dmacfg |= GEM_BIT(ADDR64);
2586 #ifdef CONFIG_MACB_USE_HWSTAMP
2587 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2588 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2590 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2592 gem_writel(bp, DMACFG, dmacfg);
2596 static void macb_init_hw(struct macb *bp)
2601 macb_set_hwaddr(bp);
2603 config = macb_mdc_clk_div(bp);
2604 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2605 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2606 if (bp->caps & MACB_CAPS_JUMBO)
2607 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2609 config |= MACB_BIT(BIG); /* Receive oversized frames */
2610 if (bp->dev->flags & IFF_PROMISC)
2611 config |= MACB_BIT(CAF); /* Copy All Frames */
2612 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2613 config |= GEM_BIT(RXCOEN);
2614 if (!(bp->dev->flags & IFF_BROADCAST))
2615 config |= MACB_BIT(NBC); /* No BroadCast */
2616 config |= macb_dbw(bp);
2617 macb_writel(bp, NCFGR, config);
2618 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2619 gem_writel(bp, JML, bp->jumbo_max_len);
2620 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2621 if (bp->caps & MACB_CAPS_JUMBO)
2622 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2624 macb_configure_dma(bp);
2627 /* The hash address register is 64 bits long and takes up two
2628 * locations in the memory map. The least significant bits are stored
2629 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2631 * The unicast hash enable and the multicast hash enable bits in the
2632 * network configuration register enable the reception of hash matched
2633 * frames. The destination address is reduced to a 6 bit index into
2634 * the 64 bit hash register using the following hash function. The
2635 * hash function is an exclusive or of every sixth bit of the
2636 * destination address.
2638 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2639 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2640 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2641 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2642 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2643 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2645 * da[0] represents the least significant bit of the first byte
2646 * received, that is, the multicast/unicast indicator, and da[47]
2647 * represents the most significant bit of the last byte received. If
2648 * the hash index, hi[n], points to a bit that is set in the hash
2649 * register then the frame will be matched according to whether the
2650 * frame is multicast or unicast. A multicast match will be signalled
2651 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2652 * index points to a bit set in the hash register. A unicast match
2653 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2654 * and the hash index points to a bit set in the hash register. To
2655 * receive all multicast frames, the hash register should be set with
2656 * all ones and the multicast hash enable bit should be set in the
2657 * network configuration register.
2660 static inline int hash_bit_value(int bitnr, __u8 *addr)
2662 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2667 /* Return the hash index value for the specified address. */
2668 static int hash_get_index(__u8 *addr)
2673 for (j = 0; j < 6; j++) {
2674 for (i = 0, bitval = 0; i < 8; i++)
2675 bitval ^= hash_bit_value(i * 6 + j, addr);
2677 hash_index |= (bitval << j);
2683 /* Add multicast addresses to the internal multicast-hash table. */
2684 static void macb_sethashtable(struct net_device *dev)
2686 struct netdev_hw_addr *ha;
2687 unsigned long mc_filter[2];
2689 struct macb *bp = netdev_priv(dev);
2694 netdev_for_each_mc_addr(ha, dev) {
2695 bitnr = hash_get_index(ha->addr);
2696 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2699 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2700 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2703 /* Enable/Disable promiscuous and multicast modes. */
2704 static void macb_set_rx_mode(struct net_device *dev)
2707 struct macb *bp = netdev_priv(dev);
2709 cfg = macb_readl(bp, NCFGR);
2711 if (dev->flags & IFF_PROMISC) {
2712 /* Enable promiscuous mode */
2713 cfg |= MACB_BIT(CAF);
2715 /* Disable RX checksum offload */
2716 if (macb_is_gem(bp))
2717 cfg &= ~GEM_BIT(RXCOEN);
2719 /* Disable promiscuous mode */
2720 cfg &= ~MACB_BIT(CAF);
2722 /* Enable RX checksum offload only if requested */
2723 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2724 cfg |= GEM_BIT(RXCOEN);
2727 if (dev->flags & IFF_ALLMULTI) {
2728 /* Enable all multicast mode */
2729 macb_or_gem_writel(bp, HRB, -1);
2730 macb_or_gem_writel(bp, HRT, -1);
2731 cfg |= MACB_BIT(NCFGR_MTI);
2732 } else if (!netdev_mc_empty(dev)) {
2733 /* Enable specific multicasts */
2734 macb_sethashtable(dev);
2735 cfg |= MACB_BIT(NCFGR_MTI);
2736 } else if (dev->flags & (~IFF_ALLMULTI)) {
2737 /* Disable all multicast mode */
2738 macb_or_gem_writel(bp, HRB, 0);
2739 macb_or_gem_writel(bp, HRT, 0);
2740 cfg &= ~MACB_BIT(NCFGR_MTI);
2743 macb_writel(bp, NCFGR, cfg);
2746 static int macb_open(struct net_device *dev)
2748 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2749 struct macb *bp = netdev_priv(dev);
2750 struct macb_queue *queue;
2754 netdev_dbg(bp->dev, "open\n");
2756 err = pm_runtime_get_sync(&bp->pdev->dev);
2760 /* RX buffers initialization */
2761 macb_init_rx_buffer_size(bp, bufsz);
2763 err = macb_alloc_consistent(bp);
2765 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2770 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2771 napi_enable(&queue->napi);
2775 err = macb_phylink_connect(bp);
2779 netif_tx_start_all_queues(dev);
2782 bp->ptp_info->ptp_init(dev);
2788 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2789 napi_disable(&queue->napi);
2790 macb_free_consistent(bp);
2792 pm_runtime_put_sync(&bp->pdev->dev);
2796 static int macb_close(struct net_device *dev)
2798 struct macb *bp = netdev_priv(dev);
2799 struct macb_queue *queue;
2800 unsigned long flags;
2803 netif_tx_stop_all_queues(dev);
2805 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2806 napi_disable(&queue->napi);
2808 phylink_stop(bp->phylink);
2809 phylink_disconnect_phy(bp->phylink);
2811 spin_lock_irqsave(&bp->lock, flags);
2813 netif_carrier_off(dev);
2814 spin_unlock_irqrestore(&bp->lock, flags);
2816 macb_free_consistent(bp);
2819 bp->ptp_info->ptp_remove(dev);
2821 pm_runtime_put(&bp->pdev->dev);
2826 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2828 if (netif_running(dev))
2836 static void gem_update_stats(struct macb *bp)
2838 struct macb_queue *queue;
2839 unsigned int i, q, idx;
2840 unsigned long *stat;
2842 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2844 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2845 u32 offset = gem_statistics[i].offset;
2846 u64 val = bp->macb_reg_readl(bp, offset);
2848 bp->ethtool_stats[i] += val;
2851 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2852 /* Add GEM_OCTTXH, GEM_OCTRXH */
2853 val = bp->macb_reg_readl(bp, offset + 4);
2854 bp->ethtool_stats[i] += ((u64)val) << 32;
2859 idx = GEM_STATS_LEN;
2860 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2861 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2862 bp->ethtool_stats[idx++] = *stat;
2865 static struct net_device_stats *gem_get_stats(struct macb *bp)
2867 struct gem_stats *hwstat = &bp->hw_stats.gem;
2868 struct net_device_stats *nstat = &bp->dev->stats;
2870 if (!netif_running(bp->dev))
2873 gem_update_stats(bp);
2875 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2876 hwstat->rx_alignment_errors +
2877 hwstat->rx_resource_errors +
2878 hwstat->rx_overruns +
2879 hwstat->rx_oversize_frames +
2880 hwstat->rx_jabbers +
2881 hwstat->rx_undersized_frames +
2882 hwstat->rx_length_field_frame_errors);
2883 nstat->tx_errors = (hwstat->tx_late_collisions +
2884 hwstat->tx_excessive_collisions +
2885 hwstat->tx_underrun +
2886 hwstat->tx_carrier_sense_errors);
2887 nstat->multicast = hwstat->rx_multicast_frames;
2888 nstat->collisions = (hwstat->tx_single_collision_frames +
2889 hwstat->tx_multiple_collision_frames +
2890 hwstat->tx_excessive_collisions);
2891 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2892 hwstat->rx_jabbers +
2893 hwstat->rx_undersized_frames +
2894 hwstat->rx_length_field_frame_errors);
2895 nstat->rx_over_errors = hwstat->rx_resource_errors;
2896 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2897 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2898 nstat->rx_fifo_errors = hwstat->rx_overruns;
2899 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2900 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2901 nstat->tx_fifo_errors = hwstat->tx_underrun;
2906 static void gem_get_ethtool_stats(struct net_device *dev,
2907 struct ethtool_stats *stats, u64 *data)
2911 bp = netdev_priv(dev);
2912 gem_update_stats(bp);
2913 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2914 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2917 static int gem_get_sset_count(struct net_device *dev, int sset)
2919 struct macb *bp = netdev_priv(dev);
2923 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2929 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2931 char stat_string[ETH_GSTRING_LEN];
2932 struct macb *bp = netdev_priv(dev);
2933 struct macb_queue *queue;
2939 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2940 memcpy(p, gem_statistics[i].stat_string,
2943 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2944 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2945 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2946 q, queue_statistics[i].stat_string);
2947 memcpy(p, stat_string, ETH_GSTRING_LEN);
2954 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2956 struct macb *bp = netdev_priv(dev);
2957 struct net_device_stats *nstat = &bp->dev->stats;
2958 struct macb_stats *hwstat = &bp->hw_stats.macb;
2960 if (macb_is_gem(bp))
2961 return gem_get_stats(bp);
2963 /* read stats from hardware */
2964 macb_update_stats(bp);
2966 /* Convert HW stats into netdevice stats */
2967 nstat->rx_errors = (hwstat->rx_fcs_errors +
2968 hwstat->rx_align_errors +
2969 hwstat->rx_resource_errors +
2970 hwstat->rx_overruns +
2971 hwstat->rx_oversize_pkts +
2972 hwstat->rx_jabbers +
2973 hwstat->rx_undersize_pkts +
2974 hwstat->rx_length_mismatch);
2975 nstat->tx_errors = (hwstat->tx_late_cols +
2976 hwstat->tx_excessive_cols +
2977 hwstat->tx_underruns +
2978 hwstat->tx_carrier_errors +
2979 hwstat->sqe_test_errors);
2980 nstat->collisions = (hwstat->tx_single_cols +
2981 hwstat->tx_multiple_cols +
2982 hwstat->tx_excessive_cols);
2983 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2984 hwstat->rx_jabbers +
2985 hwstat->rx_undersize_pkts +
2986 hwstat->rx_length_mismatch);
2987 nstat->rx_over_errors = hwstat->rx_resource_errors +
2988 hwstat->rx_overruns;
2989 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2990 nstat->rx_frame_errors = hwstat->rx_align_errors;
2991 nstat->rx_fifo_errors = hwstat->rx_overruns;
2992 /* XXX: What does "missed" mean? */
2993 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2994 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2995 nstat->tx_fifo_errors = hwstat->tx_underruns;
2996 /* Don't know about heartbeat or window errors... */
3001 static int macb_get_regs_len(struct net_device *netdev)
3003 return MACB_GREGS_NBR * sizeof(u32);
3006 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3009 struct macb *bp = netdev_priv(dev);
3010 unsigned int tail, head;
3013 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3014 | MACB_GREGS_VERSION;
3016 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3017 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3019 regs_buff[0] = macb_readl(bp, NCR);
3020 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3021 regs_buff[2] = macb_readl(bp, NSR);
3022 regs_buff[3] = macb_readl(bp, TSR);
3023 regs_buff[4] = macb_readl(bp, RBQP);
3024 regs_buff[5] = macb_readl(bp, TBQP);
3025 regs_buff[6] = macb_readl(bp, RSR);
3026 regs_buff[7] = macb_readl(bp, IMR);
3028 regs_buff[8] = tail;
3029 regs_buff[9] = head;
3030 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3031 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3033 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3034 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3035 if (macb_is_gem(bp))
3036 regs_buff[13] = gem_readl(bp, DMACFG);
3039 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3041 struct macb *bp = netdev_priv(netdev);
3043 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
3044 phylink_ethtool_get_wol(bp->phylink, wol);
3045 wol->supported |= WAKE_MAGIC;
3047 if (bp->wol & MACB_WOL_ENABLED)
3048 wol->wolopts |= WAKE_MAGIC;
3052 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3054 struct macb *bp = netdev_priv(netdev);
3057 /* Pass the order to phylink layer */
3058 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3059 /* Don't manage WoL on MAC if handled by the PHY
3060 * or if there's a failure in talking to the PHY
3062 if (!ret || ret != -EOPNOTSUPP)
3065 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3066 (wol->wolopts & ~WAKE_MAGIC))
3069 if (wol->wolopts & WAKE_MAGIC)
3070 bp->wol |= MACB_WOL_ENABLED;
3072 bp->wol &= ~MACB_WOL_ENABLED;
3074 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3079 static int macb_get_link_ksettings(struct net_device *netdev,
3080 struct ethtool_link_ksettings *kset)
3082 struct macb *bp = netdev_priv(netdev);
3084 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3087 static int macb_set_link_ksettings(struct net_device *netdev,
3088 const struct ethtool_link_ksettings *kset)
3090 struct macb *bp = netdev_priv(netdev);
3092 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3095 static void macb_get_ringparam(struct net_device *netdev,
3096 struct ethtool_ringparam *ring)
3098 struct macb *bp = netdev_priv(netdev);
3100 ring->rx_max_pending = MAX_RX_RING_SIZE;
3101 ring->tx_max_pending = MAX_TX_RING_SIZE;
3103 ring->rx_pending = bp->rx_ring_size;
3104 ring->tx_pending = bp->tx_ring_size;
3107 static int macb_set_ringparam(struct net_device *netdev,
3108 struct ethtool_ringparam *ring)
3110 struct macb *bp = netdev_priv(netdev);
3111 u32 new_rx_size, new_tx_size;
3112 unsigned int reset = 0;
3114 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3117 new_rx_size = clamp_t(u32, ring->rx_pending,
3118 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3119 new_rx_size = roundup_pow_of_two(new_rx_size);
3121 new_tx_size = clamp_t(u32, ring->tx_pending,
3122 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3123 new_tx_size = roundup_pow_of_two(new_tx_size);
3125 if ((new_tx_size == bp->tx_ring_size) &&
3126 (new_rx_size == bp->rx_ring_size)) {
3131 if (netif_running(bp->dev)) {
3133 macb_close(bp->dev);
3136 bp->rx_ring_size = new_rx_size;
3137 bp->tx_ring_size = new_tx_size;
3145 #ifdef CONFIG_MACB_USE_HWSTAMP
3146 static unsigned int gem_get_tsu_rate(struct macb *bp)
3148 struct clk *tsu_clk;
3149 unsigned int tsu_rate;
3151 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3152 if (!IS_ERR(tsu_clk))
3153 tsu_rate = clk_get_rate(tsu_clk);
3154 /* try pclk instead */
3155 else if (!IS_ERR(bp->pclk)) {
3157 tsu_rate = clk_get_rate(tsu_clk);
3163 static s32 gem_get_ptp_max_adj(void)
3168 static int gem_get_ts_info(struct net_device *dev,
3169 struct ethtool_ts_info *info)
3171 struct macb *bp = netdev_priv(dev);
3173 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3174 ethtool_op_get_ts_info(dev, info);
3178 info->so_timestamping =
3179 SOF_TIMESTAMPING_TX_SOFTWARE |
3180 SOF_TIMESTAMPING_RX_SOFTWARE |
3181 SOF_TIMESTAMPING_SOFTWARE |
3182 SOF_TIMESTAMPING_TX_HARDWARE |
3183 SOF_TIMESTAMPING_RX_HARDWARE |
3184 SOF_TIMESTAMPING_RAW_HARDWARE;
3186 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3187 (1 << HWTSTAMP_TX_OFF) |
3188 (1 << HWTSTAMP_TX_ON);
3190 (1 << HWTSTAMP_FILTER_NONE) |
3191 (1 << HWTSTAMP_FILTER_ALL);
3193 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3198 static struct macb_ptp_info gem_ptp_info = {
3199 .ptp_init = gem_ptp_init,
3200 .ptp_remove = gem_ptp_remove,
3201 .get_ptp_max_adj = gem_get_ptp_max_adj,
3202 .get_tsu_rate = gem_get_tsu_rate,
3203 .get_ts_info = gem_get_ts_info,
3204 .get_hwtst = gem_get_hwtst,
3205 .set_hwtst = gem_set_hwtst,
3209 static int macb_get_ts_info(struct net_device *netdev,
3210 struct ethtool_ts_info *info)
3212 struct macb *bp = netdev_priv(netdev);
3215 return bp->ptp_info->get_ts_info(netdev, info);
3217 return ethtool_op_get_ts_info(netdev, info);
3220 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3222 struct net_device *netdev = bp->dev;
3223 struct ethtool_rx_fs_item *item;
3227 if (!(netdev->features & NETIF_F_NTUPLE))
3230 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3232 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3233 struct ethtool_rx_flow_spec *fs = &item->fs;
3234 struct ethtool_tcpip4_spec *tp4sp_m;
3236 if (fs->location >= num_t2_scr)
3239 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3241 /* enable/disable screener regs for the flow entry */
3242 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3244 /* only enable fields with no masking */
3245 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3247 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3248 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3250 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3252 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3253 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3255 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3257 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3258 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3260 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3262 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3266 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3268 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3269 uint16_t index = fs->location;
3275 if (!macb_is_gem(bp))
3278 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3279 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3281 /* ignore field if any masking set */
3282 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3283 /* 1st compare reg - IP source address */
3286 w0 = tp4sp_v->ip4src;
3287 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3288 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3289 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3290 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3291 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3295 /* ignore field if any masking set */
3296 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3297 /* 2nd compare reg - IP destination address */
3300 w0 = tp4sp_v->ip4dst;
3301 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3302 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3303 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3304 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3305 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3309 /* ignore both port fields if masking set in both */
3310 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3311 /* 3rd compare reg - source port, destination port */
3314 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3315 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3316 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3317 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3318 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3319 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3321 /* only one port definition */
3322 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3323 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3324 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3325 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3326 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3327 } else { /* dst port */
3328 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3329 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3332 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3333 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3338 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3339 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3341 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3343 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3345 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3346 gem_writel_n(bp, SCRT2, index, t2_scr);
3349 static int gem_add_flow_filter(struct net_device *netdev,
3350 struct ethtool_rxnfc *cmd)
3352 struct macb *bp = netdev_priv(netdev);
3353 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3354 struct ethtool_rx_fs_item *item, *newfs;
3355 unsigned long flags;
3359 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3362 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3365 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3366 fs->flow_type, (int)fs->ring_cookie, fs->location,
3367 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3368 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3369 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3371 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3373 /* find correct place to add in list */
3374 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3375 if (item->fs.location > newfs->fs.location) {
3376 list_add_tail(&newfs->list, &item->list);
3379 } else if (item->fs.location == fs->location) {
3380 netdev_err(netdev, "Rule not added: location %d not free!\n",
3387 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3389 gem_prog_cmp_regs(bp, fs);
3390 bp->rx_fs_list.count++;
3391 /* enable filtering if NTUPLE on */
3392 gem_enable_flow_filters(bp, 1);
3394 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3398 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3403 static int gem_del_flow_filter(struct net_device *netdev,
3404 struct ethtool_rxnfc *cmd)
3406 struct macb *bp = netdev_priv(netdev);
3407 struct ethtool_rx_fs_item *item;
3408 struct ethtool_rx_flow_spec *fs;
3409 unsigned long flags;
3411 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3413 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3414 if (item->fs.location == cmd->fs.location) {
3415 /* disable screener regs for the flow entry */
3418 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3419 fs->flow_type, (int)fs->ring_cookie, fs->location,
3420 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3421 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3422 htons(fs->h_u.tcp_ip4_spec.psrc),
3423 htons(fs->h_u.tcp_ip4_spec.pdst));
3425 gem_writel_n(bp, SCRT2, fs->location, 0);
3427 list_del(&item->list);
3428 bp->rx_fs_list.count--;
3429 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3435 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3439 static int gem_get_flow_entry(struct net_device *netdev,
3440 struct ethtool_rxnfc *cmd)
3442 struct macb *bp = netdev_priv(netdev);
3443 struct ethtool_rx_fs_item *item;
3445 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3446 if (item->fs.location == cmd->fs.location) {
3447 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3454 static int gem_get_all_flow_entries(struct net_device *netdev,
3455 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3457 struct macb *bp = netdev_priv(netdev);
3458 struct ethtool_rx_fs_item *item;
3461 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3462 if (cnt == cmd->rule_cnt)
3464 rule_locs[cnt] = item->fs.location;
3467 cmd->data = bp->max_tuples;
3468 cmd->rule_cnt = cnt;
3473 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3476 struct macb *bp = netdev_priv(netdev);
3480 case ETHTOOL_GRXRINGS:
3481 cmd->data = bp->num_queues;
3483 case ETHTOOL_GRXCLSRLCNT:
3484 cmd->rule_cnt = bp->rx_fs_list.count;
3486 case ETHTOOL_GRXCLSRULE:
3487 ret = gem_get_flow_entry(netdev, cmd);
3489 case ETHTOOL_GRXCLSRLALL:
3490 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3494 "Command parameter %d is not supported\n", cmd->cmd);
3501 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3503 struct macb *bp = netdev_priv(netdev);
3507 case ETHTOOL_SRXCLSRLINS:
3508 if ((cmd->fs.location >= bp->max_tuples)
3509 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3513 ret = gem_add_flow_filter(netdev, cmd);
3515 case ETHTOOL_SRXCLSRLDEL:
3516 ret = gem_del_flow_filter(netdev, cmd);
3520 "Command parameter %d is not supported\n", cmd->cmd);
3527 static const struct ethtool_ops macb_ethtool_ops = {
3528 .get_regs_len = macb_get_regs_len,
3529 .get_regs = macb_get_regs,
3530 .get_link = ethtool_op_get_link,
3531 .get_ts_info = ethtool_op_get_ts_info,
3532 .get_wol = macb_get_wol,
3533 .set_wol = macb_set_wol,
3534 .get_link_ksettings = macb_get_link_ksettings,
3535 .set_link_ksettings = macb_set_link_ksettings,
3536 .get_ringparam = macb_get_ringparam,
3537 .set_ringparam = macb_set_ringparam,
3540 static const struct ethtool_ops gem_ethtool_ops = {
3541 .get_regs_len = macb_get_regs_len,
3542 .get_regs = macb_get_regs,
3543 .get_wol = macb_get_wol,
3544 .set_wol = macb_set_wol,
3545 .get_link = ethtool_op_get_link,
3546 .get_ts_info = macb_get_ts_info,
3547 .get_ethtool_stats = gem_get_ethtool_stats,
3548 .get_strings = gem_get_ethtool_strings,
3549 .get_sset_count = gem_get_sset_count,
3550 .get_link_ksettings = macb_get_link_ksettings,
3551 .set_link_ksettings = macb_set_link_ksettings,
3552 .get_ringparam = macb_get_ringparam,
3553 .set_ringparam = macb_set_ringparam,
3554 .get_rxnfc = gem_get_rxnfc,
3555 .set_rxnfc = gem_set_rxnfc,
3558 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3560 struct macb *bp = netdev_priv(dev);
3562 if (!netif_running(dev))
3568 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3570 return bp->ptp_info->get_hwtst(dev, rq);
3574 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3577 static inline void macb_set_txcsum_feature(struct macb *bp,
3578 netdev_features_t features)
3582 if (!macb_is_gem(bp))
3585 val = gem_readl(bp, DMACFG);
3586 if (features & NETIF_F_HW_CSUM)
3587 val |= GEM_BIT(TXCOEN);
3589 val &= ~GEM_BIT(TXCOEN);
3591 gem_writel(bp, DMACFG, val);
3594 static inline void macb_set_rxcsum_feature(struct macb *bp,
3595 netdev_features_t features)
3597 struct net_device *netdev = bp->dev;
3600 if (!macb_is_gem(bp))
3603 val = gem_readl(bp, NCFGR);
3604 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3605 val |= GEM_BIT(RXCOEN);
3607 val &= ~GEM_BIT(RXCOEN);
3609 gem_writel(bp, NCFGR, val);
3612 static inline void macb_set_rxflow_feature(struct macb *bp,
3613 netdev_features_t features)
3615 if (!macb_is_gem(bp))
3618 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3621 static int macb_set_features(struct net_device *netdev,
3622 netdev_features_t features)
3624 struct macb *bp = netdev_priv(netdev);
3625 netdev_features_t changed = features ^ netdev->features;
3627 /* TX checksum offload */
3628 if (changed & NETIF_F_HW_CSUM)
3629 macb_set_txcsum_feature(bp, features);
3631 /* RX checksum offload */
3632 if (changed & NETIF_F_RXCSUM)
3633 macb_set_rxcsum_feature(bp, features);
3635 /* RX Flow Filters */
3636 if (changed & NETIF_F_NTUPLE)
3637 macb_set_rxflow_feature(bp, features);
3642 static void macb_restore_features(struct macb *bp)
3644 struct net_device *netdev = bp->dev;
3645 netdev_features_t features = netdev->features;
3646 struct ethtool_rx_fs_item *item;
3648 /* TX checksum offload */
3649 macb_set_txcsum_feature(bp, features);
3651 /* RX checksum offload */
3652 macb_set_rxcsum_feature(bp, features);
3654 /* RX Flow Filters */
3655 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3656 gem_prog_cmp_regs(bp, &item->fs);
3658 macb_set_rxflow_feature(bp, features);
3661 static const struct net_device_ops macb_netdev_ops = {
3662 .ndo_open = macb_open,
3663 .ndo_stop = macb_close,
3664 .ndo_start_xmit = macb_start_xmit,
3665 .ndo_set_rx_mode = macb_set_rx_mode,
3666 .ndo_get_stats = macb_get_stats,
3667 .ndo_do_ioctl = macb_ioctl,
3668 .ndo_validate_addr = eth_validate_addr,
3669 .ndo_change_mtu = macb_change_mtu,
3670 .ndo_set_mac_address = eth_mac_addr,
3671 #ifdef CONFIG_NET_POLL_CONTROLLER
3672 .ndo_poll_controller = macb_poll_controller,
3674 .ndo_set_features = macb_set_features,
3675 .ndo_features_check = macb_features_check,
3678 /* Configure peripheral capabilities according to device tree
3679 * and integration options used
3681 static void macb_configure_caps(struct macb *bp,
3682 const struct macb_config *dt_conf)
3687 bp->caps = dt_conf->caps;
3689 if (hw_is_gem(bp->regs, bp->native_io)) {
3690 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3692 dcfg = gem_readl(bp, DCFG1);
3693 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3694 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3695 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3696 bp->caps |= MACB_CAPS_PCS;
3697 dcfg = gem_readl(bp, DCFG12);
3698 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3699 bp->caps |= MACB_CAPS_HIGH_SPEED;
3700 dcfg = gem_readl(bp, DCFG2);
3701 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3702 bp->caps |= MACB_CAPS_FIFO_MODE;
3703 #ifdef CONFIG_MACB_USE_HWSTAMP
3704 if (gem_has_ptp(bp)) {
3705 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3706 dev_err(&bp->pdev->dev,
3707 "GEM doesn't support hardware ptp.\n");
3709 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3710 bp->ptp_info = &gem_ptp_info;
3716 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3719 static void macb_probe_queues(void __iomem *mem,
3721 unsigned int *queue_mask,
3722 unsigned int *num_queues)
3727 /* is it macb or gem ?
3729 * We need to read directly from the hardware here because
3730 * we are early in the probe process and don't have the
3731 * MACB_CAPS_MACB_IS_GEM flag positioned
3733 if (!hw_is_gem(mem, native_io))
3736 /* bit 0 is never set but queue 0 always exists */
3737 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3738 *num_queues = hweight32(*queue_mask);
3741 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3742 struct clk *rx_clk, struct clk *tsu_clk)
3744 struct clk_bulk_data clks[] = {
3745 { .clk = tsu_clk, },
3752 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
3755 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3756 struct clk **hclk, struct clk **tx_clk,
3757 struct clk **rx_clk, struct clk **tsu_clk)
3759 struct macb_platform_data *pdata;
3762 pdata = dev_get_platdata(&pdev->dev);
3764 *pclk = pdata->pclk;
3765 *hclk = pdata->hclk;
3767 *pclk = devm_clk_get(&pdev->dev, "pclk");
3768 *hclk = devm_clk_get(&pdev->dev, "hclk");
3771 if (IS_ERR_OR_NULL(*pclk))
3772 return dev_err_probe(&pdev->dev,
3773 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
3774 "failed to get pclk\n");
3776 if (IS_ERR_OR_NULL(*hclk))
3777 return dev_err_probe(&pdev->dev,
3778 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
3779 "failed to get hclk\n");
3781 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3782 if (IS_ERR(*tx_clk))
3783 return PTR_ERR(*tx_clk);
3785 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3786 if (IS_ERR(*rx_clk))
3787 return PTR_ERR(*rx_clk);
3789 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3790 if (IS_ERR(*tsu_clk))
3791 return PTR_ERR(*tsu_clk);
3793 err = clk_prepare_enable(*pclk);
3795 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3799 err = clk_prepare_enable(*hclk);
3801 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3802 goto err_disable_pclk;
3805 err = clk_prepare_enable(*tx_clk);
3807 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3808 goto err_disable_hclk;
3811 err = clk_prepare_enable(*rx_clk);
3813 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3814 goto err_disable_txclk;
3817 err = clk_prepare_enable(*tsu_clk);
3819 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3820 goto err_disable_rxclk;
3826 clk_disable_unprepare(*rx_clk);
3829 clk_disable_unprepare(*tx_clk);
3832 clk_disable_unprepare(*hclk);
3835 clk_disable_unprepare(*pclk);
3840 static int macb_init(struct platform_device *pdev)
3842 struct net_device *dev = platform_get_drvdata(pdev);
3843 unsigned int hw_q, q;
3844 struct macb *bp = netdev_priv(dev);
3845 struct macb_queue *queue;
3849 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3850 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3852 /* set the queue register mapping once for all: queue0 has a special
3853 * register mapping but we don't want to test the queue index then
3854 * compute the corresponding register offset at run time.
3856 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3857 if (!(bp->queue_mask & (1 << hw_q)))
3860 queue = &bp->queues[q];
3862 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3864 queue->ISR = GEM_ISR(hw_q - 1);
3865 queue->IER = GEM_IER(hw_q - 1);
3866 queue->IDR = GEM_IDR(hw_q - 1);
3867 queue->IMR = GEM_IMR(hw_q - 1);
3868 queue->TBQP = GEM_TBQP(hw_q - 1);
3869 queue->RBQP = GEM_RBQP(hw_q - 1);
3870 queue->RBQS = GEM_RBQS(hw_q - 1);
3871 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3872 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3873 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3874 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3878 /* queue0 uses legacy registers */
3879 queue->ISR = MACB_ISR;
3880 queue->IER = MACB_IER;
3881 queue->IDR = MACB_IDR;
3882 queue->IMR = MACB_IMR;
3883 queue->TBQP = MACB_TBQP;
3884 queue->RBQP = MACB_RBQP;
3885 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3886 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3887 queue->TBQPH = MACB_TBQPH;
3888 queue->RBQPH = MACB_RBQPH;
3893 /* get irq: here we use the linux queue index, not the hardware
3894 * queue index. the queue irq definitions in the device tree
3895 * must remove the optional gaps that could exist in the
3896 * hardware queue mask.
3898 queue->irq = platform_get_irq(pdev, q);
3899 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3900 IRQF_SHARED, dev->name, queue);
3903 "Unable to request IRQ %d (error %d)\n",
3908 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3912 dev->netdev_ops = &macb_netdev_ops;
3914 /* setup appropriated routines according to adapter type */
3915 if (macb_is_gem(bp)) {
3916 bp->max_tx_length = GEM_MAX_TX_LEN;
3917 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3918 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3919 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3920 bp->macbgem_ops.mog_rx = gem_rx;
3921 dev->ethtool_ops = &gem_ethtool_ops;
3923 bp->max_tx_length = MACB_MAX_TX_LEN;
3924 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3925 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3926 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3927 bp->macbgem_ops.mog_rx = macb_rx;
3928 dev->ethtool_ops = &macb_ethtool_ops;
3932 dev->hw_features = NETIF_F_SG;
3934 /* Check LSO capability */
3935 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3936 dev->hw_features |= MACB_NETIF_LSO;
3938 /* Checksum offload is only available on gem with packet buffer */
3939 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3940 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3941 if (bp->caps & MACB_CAPS_SG_DISABLED)
3942 dev->hw_features &= ~NETIF_F_SG;
3943 dev->features = dev->hw_features;
3945 /* Check RX Flow Filters support.
3946 * Max Rx flows set by availability of screeners & compare regs:
3947 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3949 reg = gem_readl(bp, DCFG8);
3950 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3951 GEM_BFEXT(T2SCR, reg));
3952 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3953 if (bp->max_tuples > 0) {
3954 /* also needs one ethtype match to check IPv4 */
3955 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3956 /* program this reg now */
3958 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3959 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3960 /* Filtering is supported in hw but don't enable it in kernel now */
3961 dev->hw_features |= NETIF_F_NTUPLE;
3962 /* init Rx flow definitions */
3963 bp->rx_fs_list.count = 0;
3964 spin_lock_init(&bp->rx_fs_lock);
3969 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3971 if (phy_interface_mode_is_rgmii(bp->phy_interface))
3972 val = bp->usrio->rgmii;
3973 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3974 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3975 val = bp->usrio->rmii;
3976 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3977 val = bp->usrio->mii;
3979 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3980 val |= bp->usrio->refclk;
3982 macb_or_gem_writel(bp, USRIO, val);
3985 /* Set MII management clock divider */
3986 val = macb_mdc_clk_div(bp);
3987 val |= macb_dbw(bp);
3988 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3989 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3990 macb_writel(bp, NCFGR, val);
3995 static const struct macb_usrio_config macb_default_usrio = {
3996 .mii = MACB_BIT(MII),
3997 .rmii = MACB_BIT(RMII),
3998 .rgmii = GEM_BIT(RGMII),
3999 .refclk = MACB_BIT(CLKEN),
4002 #if defined(CONFIG_OF)
4003 /* 1518 rounded up */
4004 #define AT91ETHER_MAX_RBUFF_SZ 0x600
4005 /* max number of receive buffers */
4006 #define AT91ETHER_MAX_RX_DESCR 9
4008 static struct sifive_fu540_macb_mgmt *mgmt;
4010 static int at91ether_alloc_coherent(struct macb *lp)
4012 struct macb_queue *q = &lp->queues[0];
4014 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4015 (AT91ETHER_MAX_RX_DESCR *
4016 macb_dma_desc_get_size(lp)),
4017 &q->rx_ring_dma, GFP_KERNEL);
4021 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4022 AT91ETHER_MAX_RX_DESCR *
4023 AT91ETHER_MAX_RBUFF_SZ,
4024 &q->rx_buffers_dma, GFP_KERNEL);
4025 if (!q->rx_buffers) {
4026 dma_free_coherent(&lp->pdev->dev,
4027 AT91ETHER_MAX_RX_DESCR *
4028 macb_dma_desc_get_size(lp),
4029 q->rx_ring, q->rx_ring_dma);
4037 static void at91ether_free_coherent(struct macb *lp)
4039 struct macb_queue *q = &lp->queues[0];
4042 dma_free_coherent(&lp->pdev->dev,
4043 AT91ETHER_MAX_RX_DESCR *
4044 macb_dma_desc_get_size(lp),
4045 q->rx_ring, q->rx_ring_dma);
4049 if (q->rx_buffers) {
4050 dma_free_coherent(&lp->pdev->dev,
4051 AT91ETHER_MAX_RX_DESCR *
4052 AT91ETHER_MAX_RBUFF_SZ,
4053 q->rx_buffers, q->rx_buffers_dma);
4054 q->rx_buffers = NULL;
4058 /* Initialize and start the Receiver and Transmit subsystems */
4059 static int at91ether_start(struct macb *lp)
4061 struct macb_queue *q = &lp->queues[0];
4062 struct macb_dma_desc *desc;
4067 ret = at91ether_alloc_coherent(lp);
4071 addr = q->rx_buffers_dma;
4072 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4073 desc = macb_rx_desc(q, i);
4074 macb_set_addr(lp, desc, addr);
4076 addr += AT91ETHER_MAX_RBUFF_SZ;
4079 /* Set the Wrap bit on the last descriptor */
4080 desc->addr |= MACB_BIT(RX_WRAP);
4082 /* Reset buffer index */
4085 /* Program address of descriptor list in Rx Buffer Queue register */
4086 macb_writel(lp, RBQP, q->rx_ring_dma);
4088 /* Enable Receive and Transmit */
4089 ctl = macb_readl(lp, NCR);
4090 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4092 /* Enable MAC interrupts */
4093 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4095 MACB_BIT(ISR_TUND) |
4098 MACB_BIT(ISR_ROVR) |
4104 static void at91ether_stop(struct macb *lp)
4108 /* Disable MAC interrupts */
4109 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4111 MACB_BIT(ISR_TUND) |
4114 MACB_BIT(ISR_ROVR) |
4117 /* Disable Receiver and Transmitter */
4118 ctl = macb_readl(lp, NCR);
4119 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4121 /* Free resources. */
4122 at91ether_free_coherent(lp);
4125 /* Open the ethernet interface */
4126 static int at91ether_open(struct net_device *dev)
4128 struct macb *lp = netdev_priv(dev);
4132 ret = pm_runtime_get_sync(&lp->pdev->dev);
4134 pm_runtime_put_noidle(&lp->pdev->dev);
4138 /* Clear internal statistics */
4139 ctl = macb_readl(lp, NCR);
4140 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4142 macb_set_hwaddr(lp);
4144 ret = at91ether_start(lp);
4148 ret = macb_phylink_connect(lp);
4152 netif_start_queue(dev);
4159 pm_runtime_put_sync(&lp->pdev->dev);
4163 /* Close the interface */
4164 static int at91ether_close(struct net_device *dev)
4166 struct macb *lp = netdev_priv(dev);
4168 netif_stop_queue(dev);
4170 phylink_stop(lp->phylink);
4171 phylink_disconnect_phy(lp->phylink);
4175 return pm_runtime_put(&lp->pdev->dev);
4178 /* Transmit packet */
4179 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4180 struct net_device *dev)
4182 struct macb *lp = netdev_priv(dev);
4184 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4187 netif_stop_queue(dev);
4189 /* Store packet information (to free when Tx completed) */
4190 lp->rm9200_txq[desc].skb = skb;
4191 lp->rm9200_txq[desc].size = skb->len;
4192 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4193 skb->len, DMA_TO_DEVICE);
4194 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4195 dev_kfree_skb_any(skb);
4196 dev->stats.tx_dropped++;
4197 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4198 return NETDEV_TX_OK;
4201 /* Set address of the data in the Transmit Address register */
4202 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4203 /* Set length of the packet in the Transmit Control register */
4204 macb_writel(lp, TCR, skb->len);
4207 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4208 return NETDEV_TX_BUSY;
4211 return NETDEV_TX_OK;
4214 /* Extract received frame from buffer descriptors and sent to upper layers.
4215 * (Called from interrupt context)
4217 static void at91ether_rx(struct net_device *dev)
4219 struct macb *lp = netdev_priv(dev);
4220 struct macb_queue *q = &lp->queues[0];
4221 struct macb_dma_desc *desc;
4222 unsigned char *p_recv;
4223 struct sk_buff *skb;
4224 unsigned int pktlen;
4226 desc = macb_rx_desc(q, q->rx_tail);
4227 while (desc->addr & MACB_BIT(RX_USED)) {
4228 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4229 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4230 skb = netdev_alloc_skb(dev, pktlen + 2);
4232 skb_reserve(skb, 2);
4233 skb_put_data(skb, p_recv, pktlen);
4235 skb->protocol = eth_type_trans(skb, dev);
4236 dev->stats.rx_packets++;
4237 dev->stats.rx_bytes += pktlen;
4240 dev->stats.rx_dropped++;
4243 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4244 dev->stats.multicast++;
4246 /* reset ownership bit */
4247 desc->addr &= ~MACB_BIT(RX_USED);
4249 /* wrap after last buffer */
4250 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4255 desc = macb_rx_desc(q, q->rx_tail);
4259 /* MAC interrupt handler */
4260 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4262 struct net_device *dev = dev_id;
4263 struct macb *lp = netdev_priv(dev);
4267 /* MAC Interrupt Status register indicates what interrupts are pending.
4268 * It is automatically cleared once read.
4270 intstatus = macb_readl(lp, ISR);
4272 /* Receive complete */
4273 if (intstatus & MACB_BIT(RCOMP))
4276 /* Transmit complete */
4277 if (intstatus & MACB_BIT(TCOMP)) {
4278 /* The TCOM bit is set even if the transmission failed */
4279 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4280 dev->stats.tx_errors++;
4283 if (lp->rm9200_txq[desc].skb) {
4284 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4285 lp->rm9200_txq[desc].skb = NULL;
4286 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4287 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4288 dev->stats.tx_packets++;
4289 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4291 netif_wake_queue(dev);
4294 /* Work-around for EMAC Errata section 41.3.1 */
4295 if (intstatus & MACB_BIT(RXUBR)) {
4296 ctl = macb_readl(lp, NCR);
4297 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4299 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4302 if (intstatus & MACB_BIT(ISR_ROVR))
4303 netdev_err(dev, "ROVR error\n");
4308 #ifdef CONFIG_NET_POLL_CONTROLLER
4309 static void at91ether_poll_controller(struct net_device *dev)
4311 unsigned long flags;
4313 local_irq_save(flags);
4314 at91ether_interrupt(dev->irq, dev);
4315 local_irq_restore(flags);
4319 static const struct net_device_ops at91ether_netdev_ops = {
4320 .ndo_open = at91ether_open,
4321 .ndo_stop = at91ether_close,
4322 .ndo_start_xmit = at91ether_start_xmit,
4323 .ndo_get_stats = macb_get_stats,
4324 .ndo_set_rx_mode = macb_set_rx_mode,
4325 .ndo_set_mac_address = eth_mac_addr,
4326 .ndo_do_ioctl = macb_ioctl,
4327 .ndo_validate_addr = eth_validate_addr,
4328 #ifdef CONFIG_NET_POLL_CONTROLLER
4329 .ndo_poll_controller = at91ether_poll_controller,
4333 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4334 struct clk **hclk, struct clk **tx_clk,
4335 struct clk **rx_clk, struct clk **tsu_clk)
4344 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4346 return PTR_ERR(*pclk);
4348 err = clk_prepare_enable(*pclk);
4350 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4357 static int at91ether_init(struct platform_device *pdev)
4359 struct net_device *dev = platform_get_drvdata(pdev);
4360 struct macb *bp = netdev_priv(dev);
4363 bp->queues[0].bp = bp;
4365 dev->netdev_ops = &at91ether_netdev_ops;
4366 dev->ethtool_ops = &macb_ethtool_ops;
4368 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4373 macb_writel(bp, NCR, 0);
4375 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4380 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4381 unsigned long parent_rate)
4386 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4387 unsigned long *parent_rate)
4389 if (WARN_ON(rate < 2500000))
4391 else if (rate == 2500000)
4393 else if (WARN_ON(rate < 13750000))
4395 else if (WARN_ON(rate < 25000000))
4397 else if (rate == 25000000)
4399 else if (WARN_ON(rate < 75000000))
4401 else if (WARN_ON(rate < 125000000))
4403 else if (rate == 125000000)
4406 WARN_ON(rate > 125000000);
4411 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4412 unsigned long parent_rate)
4414 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4415 if (rate != 125000000)
4416 iowrite32(1, mgmt->reg);
4418 iowrite32(0, mgmt->reg);
4424 static const struct clk_ops fu540_c000_ops = {
4425 .recalc_rate = fu540_macb_tx_recalc_rate,
4426 .round_rate = fu540_macb_tx_round_rate,
4427 .set_rate = fu540_macb_tx_set_rate,
4430 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4431 struct clk **hclk, struct clk **tx_clk,
4432 struct clk **rx_clk, struct clk **tsu_clk)
4434 struct clk_init_data init;
4437 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4441 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4444 goto err_disable_clks;
4447 init.name = "sifive-gemgxl-mgmt";
4448 init.ops = &fu540_c000_ops;
4450 init.num_parents = 0;
4453 mgmt->hw.init = &init;
4455 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4456 if (IS_ERR(*tx_clk)) {
4457 err = PTR_ERR(*tx_clk);
4458 goto err_disable_clks;
4461 err = clk_prepare_enable(*tx_clk);
4463 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4465 goto err_disable_clks;
4467 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4473 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4478 static int fu540_c000_init(struct platform_device *pdev)
4480 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4481 if (IS_ERR(mgmt->reg))
4482 return PTR_ERR(mgmt->reg);
4484 return macb_init(pdev);
4487 static const struct macb_usrio_config sama7g5_usrio = {
4495 static const struct macb_config fu540_c000_config = {
4496 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4497 MACB_CAPS_GEM_HAS_PTP,
4498 .dma_burst_length = 16,
4499 .clk_init = fu540_c000_clk_init,
4500 .init = fu540_c000_init,
4501 .jumbo_max_len = 10240,
4502 .usrio = &macb_default_usrio,
4505 static const struct macb_config at91sam9260_config = {
4506 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4507 .clk_init = macb_clk_init,
4509 .usrio = &macb_default_usrio,
4512 static const struct macb_config sama5d3macb_config = {
4513 .caps = MACB_CAPS_SG_DISABLED
4514 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4515 .clk_init = macb_clk_init,
4517 .usrio = &macb_default_usrio,
4520 static const struct macb_config pc302gem_config = {
4521 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4522 .dma_burst_length = 16,
4523 .clk_init = macb_clk_init,
4525 .usrio = &macb_default_usrio,
4528 static const struct macb_config sama5d2_config = {
4529 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4530 .dma_burst_length = 16,
4531 .clk_init = macb_clk_init,
4533 .usrio = &macb_default_usrio,
4536 static const struct macb_config sama5d3_config = {
4537 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4538 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4539 .dma_burst_length = 16,
4540 .clk_init = macb_clk_init,
4542 .jumbo_max_len = 10240,
4543 .usrio = &macb_default_usrio,
4546 static const struct macb_config sama5d4_config = {
4547 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4548 .dma_burst_length = 4,
4549 .clk_init = macb_clk_init,
4551 .usrio = &macb_default_usrio,
4554 static const struct macb_config emac_config = {
4555 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4556 .clk_init = at91ether_clk_init,
4557 .init = at91ether_init,
4558 .usrio = &macb_default_usrio,
4561 static const struct macb_config np4_config = {
4562 .caps = MACB_CAPS_USRIO_DISABLED,
4563 .clk_init = macb_clk_init,
4565 .usrio = &macb_default_usrio,
4568 static const struct macb_config zynqmp_config = {
4569 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4571 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4572 .dma_burst_length = 16,
4573 .clk_init = macb_clk_init,
4575 .jumbo_max_len = 10240,
4576 .usrio = &macb_default_usrio,
4579 static const struct macb_config zynq_config = {
4580 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4581 MACB_CAPS_NEEDS_RSTONUBR,
4582 .dma_burst_length = 16,
4583 .clk_init = macb_clk_init,
4585 .usrio = &macb_default_usrio,
4588 static const struct macb_config sama7g5_gem_config = {
4589 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG,
4590 .dma_burst_length = 16,
4591 .clk_init = macb_clk_init,
4593 .usrio = &sama7g5_usrio,
4596 static const struct macb_config sama7g5_emac_config = {
4597 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN,
4598 .dma_burst_length = 16,
4599 .clk_init = macb_clk_init,
4601 .usrio = &sama7g5_usrio,
4604 static const struct of_device_id macb_dt_ids[] = {
4605 { .compatible = "cdns,at32ap7000-macb" },
4606 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4607 { .compatible = "cdns,macb" },
4608 { .compatible = "cdns,np4-macb", .data = &np4_config },
4609 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4610 { .compatible = "cdns,gem", .data = &pc302gem_config },
4611 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4612 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4613 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4614 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4615 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4616 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4617 { .compatible = "cdns,emac", .data = &emac_config },
4618 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4619 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4620 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4621 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4622 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4625 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4626 #endif /* CONFIG_OF */
4628 static const struct macb_config default_gem_config = {
4629 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4631 MACB_CAPS_GEM_HAS_PTP,
4632 .dma_burst_length = 16,
4633 .clk_init = macb_clk_init,
4635 .usrio = &macb_default_usrio,
4636 .jumbo_max_len = 10240,
4639 static int macb_probe(struct platform_device *pdev)
4641 const struct macb_config *macb_config = &default_gem_config;
4642 int (*clk_init)(struct platform_device *, struct clk **,
4643 struct clk **, struct clk **, struct clk **,
4644 struct clk **) = macb_config->clk_init;
4645 int (*init)(struct platform_device *) = macb_config->init;
4646 struct device_node *np = pdev->dev.of_node;
4647 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4648 struct clk *tsu_clk = NULL;
4649 unsigned int queue_mask, num_queues;
4651 phy_interface_t interface;
4652 struct net_device *dev;
4653 struct resource *regs;
4658 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
4660 return PTR_ERR(mem);
4663 const struct of_device_id *match;
4665 match = of_match_node(macb_dt_ids, np);
4666 if (match && match->data) {
4667 macb_config = match->data;
4668 clk_init = macb_config->clk_init;
4669 init = macb_config->init;
4673 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4677 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4678 pm_runtime_use_autosuspend(&pdev->dev);
4679 pm_runtime_get_noresume(&pdev->dev);
4680 pm_runtime_set_active(&pdev->dev);
4681 pm_runtime_enable(&pdev->dev);
4682 native_io = hw_is_native_io(mem);
4684 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4685 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4688 goto err_disable_clocks;
4691 dev->base_addr = regs->start;
4693 SET_NETDEV_DEV(dev, &pdev->dev);
4695 bp = netdev_priv(dev);
4699 bp->native_io = native_io;
4701 bp->macb_reg_readl = hw_readl_native;
4702 bp->macb_reg_writel = hw_writel_native;
4704 bp->macb_reg_readl = hw_readl;
4705 bp->macb_reg_writel = hw_writel;
4707 bp->num_queues = num_queues;
4708 bp->queue_mask = queue_mask;
4710 bp->dma_burst_length = macb_config->dma_burst_length;
4713 bp->tx_clk = tx_clk;
4714 bp->rx_clk = rx_clk;
4715 bp->tsu_clk = tsu_clk;
4717 bp->jumbo_max_len = macb_config->jumbo_max_len;
4720 if (of_get_property(np, "magic-packet", NULL))
4721 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4722 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4724 bp->usrio = macb_config->usrio;
4726 spin_lock_init(&bp->lock);
4728 /* setup capabilities */
4729 macb_configure_caps(bp, macb_config);
4731 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4732 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4733 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4734 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4737 platform_set_drvdata(pdev, dev);
4739 dev->irq = platform_get_irq(pdev, 0);
4742 goto err_out_free_netdev;
4745 /* MTU range: 68 - 1500 or 10240 */
4746 dev->min_mtu = GEM_MTU_MIN_SIZE;
4747 if (bp->caps & MACB_CAPS_JUMBO)
4748 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4750 dev->max_mtu = ETH_DATA_LEN;
4752 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4753 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4755 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4756 macb_dma_desc_get_size(bp);
4758 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4760 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4761 macb_dma_desc_get_size(bp);
4764 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4765 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4766 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4768 err = of_get_mac_address(np, bp->dev->dev_addr);
4769 if (err == -EPROBE_DEFER)
4770 goto err_out_free_netdev;
4772 macb_get_hwaddr(bp);
4774 err = of_get_phy_mode(np, &interface);
4776 /* not found in DT, MII by default */
4777 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4779 bp->phy_interface = interface;
4781 /* IP specific init */
4784 goto err_out_free_netdev;
4786 err = macb_mii_init(bp);
4788 goto err_out_free_netdev;
4790 netif_carrier_off(dev);
4792 err = register_netdev(dev);
4794 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4795 goto err_out_unregister_mdio;
4798 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
4800 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4801 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4802 dev->base_addr, dev->irq, dev->dev_addr);
4804 pm_runtime_mark_last_busy(&bp->pdev->dev);
4805 pm_runtime_put_autosuspend(&bp->pdev->dev);
4809 err_out_unregister_mdio:
4810 mdiobus_unregister(bp->mii_bus);
4811 mdiobus_free(bp->mii_bus);
4813 err_out_free_netdev:
4817 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
4818 pm_runtime_disable(&pdev->dev);
4819 pm_runtime_set_suspended(&pdev->dev);
4820 pm_runtime_dont_use_autosuspend(&pdev->dev);
4825 static int macb_remove(struct platform_device *pdev)
4827 struct net_device *dev;
4830 dev = platform_get_drvdata(pdev);
4833 bp = netdev_priv(dev);
4834 mdiobus_unregister(bp->mii_bus);
4835 mdiobus_free(bp->mii_bus);
4837 unregister_netdev(dev);
4838 tasklet_kill(&bp->hresp_err_tasklet);
4839 pm_runtime_disable(&pdev->dev);
4840 pm_runtime_dont_use_autosuspend(&pdev->dev);
4841 if (!pm_runtime_suspended(&pdev->dev)) {
4842 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
4843 bp->rx_clk, bp->tsu_clk);
4844 pm_runtime_set_suspended(&pdev->dev);
4846 phylink_destroy(bp->phylink);
4853 static int __maybe_unused macb_suspend(struct device *dev)
4855 struct net_device *netdev = dev_get_drvdata(dev);
4856 struct macb *bp = netdev_priv(netdev);
4857 struct macb_queue *queue;
4858 unsigned long flags;
4862 if (!netif_running(netdev))
4865 if (bp->wol & MACB_WOL_ENABLED) {
4866 spin_lock_irqsave(&bp->lock, flags);
4867 /* Flush all status bits */
4868 macb_writel(bp, TSR, -1);
4869 macb_writel(bp, RSR, -1);
4870 for (q = 0, queue = bp->queues; q < bp->num_queues;
4872 /* Disable all interrupts */
4873 queue_writel(queue, IDR, -1);
4874 queue_readl(queue, ISR);
4875 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4876 queue_writel(queue, ISR, -1);
4878 /* Change interrupt handler and
4879 * Enable WoL IRQ on queue 0
4881 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4882 if (macb_is_gem(bp)) {
4883 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
4884 IRQF_SHARED, netdev->name, bp->queues);
4887 "Unable to request IRQ %d (error %d)\n",
4888 bp->queues[0].irq, err);
4889 spin_unlock_irqrestore(&bp->lock, flags);
4892 queue_writel(bp->queues, IER, GEM_BIT(WOL));
4893 gem_writel(bp, WOL, MACB_BIT(MAG));
4895 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
4896 IRQF_SHARED, netdev->name, bp->queues);
4899 "Unable to request IRQ %d (error %d)\n",
4900 bp->queues[0].irq, err);
4901 spin_unlock_irqrestore(&bp->lock, flags);
4904 queue_writel(bp->queues, IER, MACB_BIT(WOL));
4905 macb_writel(bp, WOL, MACB_BIT(MAG));
4907 spin_unlock_irqrestore(&bp->lock, flags);
4909 enable_irq_wake(bp->queues[0].irq);
4912 netif_device_detach(netdev);
4913 for (q = 0, queue = bp->queues; q < bp->num_queues;
4915 napi_disable(&queue->napi);
4917 if (!(bp->wol & MACB_WOL_ENABLED)) {
4919 phylink_stop(bp->phylink);
4921 spin_lock_irqsave(&bp->lock, flags);
4923 spin_unlock_irqrestore(&bp->lock, flags);
4926 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4927 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4929 if (netdev->hw_features & NETIF_F_NTUPLE)
4930 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4933 bp->ptp_info->ptp_remove(netdev);
4934 if (!device_may_wakeup(dev))
4935 pm_runtime_force_suspend(dev);
4940 static int __maybe_unused macb_resume(struct device *dev)
4942 struct net_device *netdev = dev_get_drvdata(dev);
4943 struct macb *bp = netdev_priv(netdev);
4944 struct macb_queue *queue;
4945 unsigned long flags;
4949 if (!netif_running(netdev))
4952 if (!device_may_wakeup(dev))
4953 pm_runtime_force_resume(dev);
4955 if (bp->wol & MACB_WOL_ENABLED) {
4956 spin_lock_irqsave(&bp->lock, flags);
4958 if (macb_is_gem(bp)) {
4959 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
4960 gem_writel(bp, WOL, 0);
4962 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
4963 macb_writel(bp, WOL, 0);
4965 /* Clear ISR on queue 0 */
4966 queue_readl(bp->queues, ISR);
4967 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4968 queue_writel(bp->queues, ISR, -1);
4969 /* Replace interrupt handler on queue 0 */
4970 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4971 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
4972 IRQF_SHARED, netdev->name, bp->queues);
4975 "Unable to request IRQ %d (error %d)\n",
4976 bp->queues[0].irq, err);
4977 spin_unlock_irqrestore(&bp->lock, flags);
4980 spin_unlock_irqrestore(&bp->lock, flags);
4982 disable_irq_wake(bp->queues[0].irq);
4984 /* Now make sure we disable phy before moving
4985 * to common restore path
4988 phylink_stop(bp->phylink);
4992 for (q = 0, queue = bp->queues; q < bp->num_queues;
4994 napi_enable(&queue->napi);
4996 if (netdev->hw_features & NETIF_F_NTUPLE)
4997 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4999 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5000 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5002 macb_writel(bp, NCR, MACB_BIT(MPE));
5004 macb_set_rx_mode(netdev);
5005 macb_restore_features(bp);
5007 phylink_start(bp->phylink);
5010 netif_device_attach(netdev);
5012 bp->ptp_info->ptp_init(netdev);
5017 static int __maybe_unused macb_runtime_suspend(struct device *dev)
5019 struct net_device *netdev = dev_get_drvdata(dev);
5020 struct macb *bp = netdev_priv(netdev);
5022 if (!(device_may_wakeup(dev)))
5023 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5025 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5030 static int __maybe_unused macb_runtime_resume(struct device *dev)
5032 struct net_device *netdev = dev_get_drvdata(dev);
5033 struct macb *bp = netdev_priv(netdev);
5035 if (!(device_may_wakeup(dev))) {
5036 clk_prepare_enable(bp->pclk);
5037 clk_prepare_enable(bp->hclk);
5038 clk_prepare_enable(bp->tx_clk);
5039 clk_prepare_enable(bp->rx_clk);
5041 clk_prepare_enable(bp->tsu_clk);
5046 static const struct dev_pm_ops macb_pm_ops = {
5047 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5048 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5051 static struct platform_driver macb_driver = {
5052 .probe = macb_probe,
5053 .remove = macb_remove,
5056 .of_match_table = of_match_ptr(macb_dt_ids),
5061 module_platform_driver(macb_driver);
5063 MODULE_LICENSE("GPL");
5064 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5065 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5066 MODULE_ALIAS("platform:macb");